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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/drivers/hid/intel-thc-hid/Kconfig
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# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2024, Intel Corporation.
menu "Intel THC HID Support"
depends on X86_64 && PCI
config INTEL_THC_HID
tristate "Intel Touch Host Controller"
depends on ACPI
select SGL_ALLOC
help
THC (Touch Host Controller) is the name of the IP block in PCH that
interfaces with Touch Devices (ex: touchscreen, touchpad etc.). It
is comprised of 3 key functional blocks: A natively half-duplex
Quad I/O capable SPI master; a low latency I2C interface to support
HIDI2C compliant devices; a hardware sequencer with Read/Write DMA
capability to system memory.
Say Y/M here if you want to support Intel THC. If unsure, say N.
config INTEL_QUICKSPI
tristate "Intel QuickSPI driver based on Intel Touch Host Controller"
depends on INTEL_THC_HID
help
Intel QuickSPI, based on Touch Host Controller (THC), implements
HIDSPI (HID over SPI) protocol. It configures THC to work at SPI
mode, and controls THC hardware sequencer to accelerate HIDSPI
transaction flow.
Say Y/M here if you want to support Intel QuickSPI. If unsure, say N.
config INTEL_QUICKI2C
tristate "Intel QuickI2C driver based on Intel Touch Host Controller"
depends on INTEL_THC_HID
help
Intel QuickI2C, uses Touch Host Controller (THC) hardware, implements
HIDI2C (HID over I2C) protocol. It configures THC to work in I2C
mode, and controls THC hardware sequencer to accelerate HIDI2C
transaction flow.
Say Y/M here if you want to support Intel QuickI2C. If unsure, say N.
endmenu
linux-7.2.3/drivers/hid/intel-thc-hid/Makefile
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# SPDX-License-Identifier: GPL-2.0
#
# Makefile - Intel Touch Host Controller (THC) drivers
# Copyright (c) 2024, Intel Corporation.
#
#
obj-$(CONFIG_INTEL_THC_HID) += intel-thc.o
intel-thc-objs += intel-thc/intel-thc-dev.o
intel-thc-objs += intel-thc/intel-thc-dma.o
intel-thc-objs += intel-thc/intel-thc-wot.o
obj-$(CONFIG_INTEL_QUICKSPI) += intel-quickspi.o
intel-quickspi-objs += intel-quickspi/pci-quickspi.o
intel-quickspi-objs += intel-quickspi/quickspi-hid.o
intel-quickspi-objs += intel-quickspi/quickspi-protocol.o
obj-$(CONFIG_INTEL_QUICKI2C) += intel-quicki2c.o
intel-quicki2c-objs += intel-quicki2c/pci-quicki2c.o
intel-quicki2c-objs += intel-quicki2c/quicki2c-hid.o
intel-quicki2c-objs += intel-quicki2c/quicki2c-protocol.o
ccflags-y += -I $(src)/intel-thc
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quicki2c/pci-quicki2c.c
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linux-7.2.3/drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-dev.h
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _QUICKI2C_DEV_H_
#define _QUICKI2C_DEV_H_
#include <linux/hid-over-i2c.h>
#include <linux/workqueue.h>
#define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT1 0xA848
#define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT2 0xA84A
#define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT1 0xE348
#define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT2 0xE34A
#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT1 0xE448
#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT2 0xE44A
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT1 0x4D48
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT2 0x4D4A
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_I2C_PORT1 0xD348
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_I2C_PORT2 0xD34A
/* Packet size value, the unit is 16 bytes */
#define MAX_PACKET_SIZE_VALUE_LNL 256
/* HIDI2C special ACPI parameters DSD name */
#define QUICKI2C_ACPI_METHOD_NAME_ICRS "ICRS"
#define QUICKI2C_ACPI_METHOD_NAME_ISUB "ISUB"
/* HIDI2C special ACPI parameters DSM methods */
#define QUICKI2C_ACPI_REVISION_NUM 1
#define QUICKI2C_ACPI_FUNC_NUM_HID_DESC_ADDR 1
#define QUICKI2C_ACPI_FUNC_NUM_ACTIVE_LTR_VAL 1
#define QUICKI2C_ACPI_FUNC_NUM_LP_LTR_VAL 2
#define QUICKI2C_SUBIP_STANDARD_MODE_MAX_SPEED 100000
#define QUICKI2C_SUBIP_FAST_MODE_MAX_SPEED 400000
#define QUICKI2C_SUBIP_FASTPLUS_MODE_MAX_SPEED 1000000
#define QUICKI2C_SUBIP_HIGH_SPEED_MODE_MAX_SPEED 3400000
#define QUICKI2C_DEFAULT_ACTIVE_LTR_VALUE 5
#define QUICKI2C_DEFAULT_LP_LTR_VALUE 500
#define QUICKI2C_RPM_TIMEOUT_MS 500
/* PTL Max packet size detection capability is 255 Bytes */
#define MAX_RX_DETECT_SIZE_PTL 255
/* NVL Max packet size detection capability is 64K Bytes */
#define MAX_RX_DETECT_SIZE_NVL 65535
/* Max interrupt delay capability is 2.56ms */
#define MAX_RX_INTERRUPT_DELAY 256
/* Default interrupt delay is 1ms, suitable for most devices */
#define DEFAULT_INTERRUPT_DELAY_US (1 * USEC_PER_MSEC)
/*
* THC uses runtime auto suspend to dynamically switch between THC active LTR
* and low power LTR to save CPU power.
* Default value is 5000ms, that means if no touch event in this time, THC will
* change to low power LTR mode.
*/
#define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000
enum quicki2c_dev_state {
QUICKI2C_NONE,
QUICKI2C_RESETING,
QUICKI2C_RESETED,
QUICKI2C_INITED,
QUICKI2C_ENABLED,
QUICKI2C_DISABLED,
};
enum {
HIDI2C_ADDRESSING_MODE_7BIT,
HIDI2C_ADDRESSING_MODE_10BIT,
};
/**
* struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
* @device_address: I2C device slave address
* @connection_speed: I2C device expected connection speed
* @addressing_mode: I2C device slave address mode, 7bit or 10bit
*
* Those properties get from QUICKI2C_ACPI_METHOD_NAME_ICRS method, used for
* Bus parameter.
*/
struct quicki2c_subip_acpi_parameter {
u16 device_address;
u64 connection_speed;
u8 addressing_mode;
u8 reserved;
} __packed;
/**
* struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
* @SMHX: Standard Mode (100 kbit/s) Serial Clock Line HIGH Period
* @SMLX: Standard Mode (100 kbit/s) Serial Clock Line LOW Period
* @SMTD: Standard Mode (100 kbit/s) Serial Data Line Transmit Hold Period
* @SMRD: Standard Mode (100 kbit/s) Serial Data Receive Hold Period
* @FMHX: Fast Mode (400 kbit/s) Serial Clock Line HIGH Period
* @FMLX: Fast Mode (400 kbit/s) Serial Clock Line LOW Period
* @FMTD: Fast Mode (400 kbit/s) Serial Data Line Transmit Hold Period
* @FMRD: Fast Mode (400 kbit/s) Serial Data Line Receive Hold Period
* @FMSL: Maximum length (in ic_clk_cycles) of suppressed spikes
* in Standard Mode, Fast Mode and Fast Mode Plus
* @FPHX: Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period
* @FPLX: Fast Mode Plus (1Mbit/sec) Serial Clock Line LOW Period
* @FPTD: Fast Mode Plus (1Mbit/sec) Serial Data Line Transmit HOLD Period
* @FPRD: Fast Mode Plus (1Mbit/sec) Serial Data Line Receive HOLD Period
* @HMHX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line HIGH Period
* @HMLX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line LOW Period
* @HMTD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Transmit HOLD Period
* @HMRD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Receive HOLD Period
* @HMSL: Maximum length (in ic_clk_cycles) of suppressed spikes in High Speed Mode
* @FSEN: Maximum Frame Size Feature Enable Control
* @FSVL: Maximum Frame Size Value (unit in Bytes)
* @INDE: Interrupt Delay Feature Enable Control
* @INDV: Interrupt Delay Value (unit in 10 us)
*
* Those properties get from QUICKI2C_ACPI_METHOD_NAME_ISUB method, used for
* I2C timing configure.
*/
struct quicki2c_subip_acpi_config {
u64 SMHX;
u64 SMLX;
u64 SMTD;
u64 SMRD;
u64 FMHX;
u64 FMLX;
u64 FMTD;
u64 FMRD;
u64 FMSL;
u64 FPHX;
u64 FPLX;
u64 FPTD;
u64 FPRD;
u64 HMHX;
u64 HMLX;
u64 HMTD;
u64 HMRD;
u64 HMSL;
u64 FSEN;
u64 FSVL;
u64 INDE;
u64 INDV;
u8 reserved;
};
/**
* struct quicki2c_ddata - Driver specific data for quicki2c device
* @max_detect_size: Identify max packet size detect for rx
* @interrupt_delay: Identify max interrupt detect delay for rx
*/
struct quicki2c_ddata {
u32 max_detect_size;
u32 max_interrupt_delay;
};
struct device;
struct pci_dev;
struct thc_device;
struct hid_device;
struct acpi_device;
/**
* struct quicki2c_device - THC QuickI2C device struct
* @dev: Point to kernel device
* @pdev: Point to PCI device
* @thc_hw: Point to THC device
* @hid_dev: Point to HID device
* @acpi_dev: Point to ACPI device
* @ddata: Point to QuickI2C platform specific driver data
* @state: THC I2C device state
* @mem_addr: MMIO memory address
* @dev_desc: Device descriptor for HIDI2C protocol
* @i2c_slave_addr: HIDI2C device slave address
* @hid_desc_addr: Register address for retrieve HID device descriptor
* @active_ltr_val: THC active LTR value
* @low_power_ltr_val: THC low power LTR value
* @i2c_speed_mode: 0 - standard mode, 1 - fast mode, 2 - fast mode plus
* @i2c_clock_hcnt: I2C CLK high period time (unit in cycle count)
* @i2c_clock_lcnt: I2C CLK low period time (unit in cycle count)
* @report_descriptor: Store a copy of device report descriptor
* @input_buf: Store a copy of latest input report data
* @report_buf: Store a copy of latest input/output report packet from set/get feature
* @report_len: The length of input/output report packet
* @reset_ack_wq: Workqueue for waiting reset response from device
* @reset_ack: Indicate reset response received or not
* @i2c_max_frame_size_enable: Indicate max frame size feature enabled or not
* @i2c_max_frame_size: Max RX frame size (unit in Bytes)
* @i2c_int_delay_enable: Indicate interrupt delay feature enabled or not
* @i2c_int_delay: Interrupt detection delay value (unit in 10 us)
*/
struct quicki2c_device {
struct device *dev;
struct pci_dev *pdev;
struct thc_device *thc_hw;
struct hid_device *hid_dev;
struct acpi_device *acpi_dev;
const struct quicki2c_ddata *ddata;
enum quicki2c_dev_state state;
void __iomem *mem_addr;
struct hidi2c_dev_descriptor dev_desc;
u8 i2c_slave_addr;
u16 hid_desc_addr;
u32 active_ltr_val;
u32 low_power_ltr_val;
u32 i2c_speed_mode;
u32 i2c_clock_hcnt;
u32 i2c_clock_lcnt;
u8 *report_descriptor;
u8 *input_buf;
u8 *report_buf;
size_t report_len;
wait_queue_head_t reset_ack_wq;
bool reset_ack;
u32 i2c_max_frame_size_enable;
u32 i2c_max_frame_size;
u32 i2c_int_delay_enable;
u32 i2c_int_delay;
};
#endif /* _QUICKI2C_DEV_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-hid.c
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#include <linux/hid.h>
#include <linux/input.h>
#include <linux/pm_runtime.h>
#include "quicki2c-dev.h"
#include "quicki2c-hid.h"
#include "quicki2c-protocol.h"
/**
* quicki2c_hid_parse() - HID core parse() callback
*
* @hid: HID device instance
*
* This function gets called during call to hid_add_device
*
* Return: 0 on success and non zero on error.
*/
static int quicki2c_hid_parse(struct hid_device *hid)
{
struct quicki2c_device *qcdev = hid->driver_data;
if (qcdev->report_descriptor)
return hid_parse_report(hid, qcdev->report_descriptor,
le16_to_cpu(qcdev->dev_desc.report_desc_len));
dev_err_once(qcdev->dev, "invalid report descriptor\n");
return -EINVAL;
}
static int quicki2c_hid_start(struct hid_device *hid)
{
return 0;
}
static void quicki2c_hid_stop(struct hid_device *hid)
{
}
static int quicki2c_hid_open(struct hid_device *hid)
{
return 0;
}
static void quicki2c_hid_close(struct hid_device *hid)
{
}
static int quicki2c_hid_raw_request(struct hid_device *hid,
unsigned char reportnum,
__u8 *buf, size_t len,
unsigned char rtype, int reqtype)
{
struct quicki2c_device *qcdev = hid->driver_data;
int ret = 0;
ret = pm_runtime_resume_and_get(qcdev->dev);
if (ret)
return ret;
switch (reqtype) {
case HID_REQ_GET_REPORT:
ret = quicki2c_get_report(qcdev, rtype, reportnum, buf, len);
break;
case HID_REQ_SET_REPORT:
ret = quicki2c_set_report(qcdev, rtype, reportnum, buf, len);
break;
default:
dev_err(qcdev->dev, "Not supported request type %d\n", reqtype);
break;
}
pm_runtime_put_autosuspend(qcdev->dev);
return ret;
}
static int quicki2c_hid_power(struct hid_device *hid, int lvl)
{
return 0;
}
static int quicki2c_hid_output_report(struct hid_device *hid, u8 *buf, size_t count)
{
struct quicki2c_device *qcdev = hid->driver_data;
return quicki2c_output_report(qcdev, buf, count);
}
static struct hid_ll_driver quicki2c_hid_ll_driver = {
.parse = quicki2c_hid_parse,
.start = quicki2c_hid_start,
.stop = quicki2c_hid_stop,
.open = quicki2c_hid_open,
.close = quicki2c_hid_close,
.power = quicki2c_hid_power,
.raw_request = quicki2c_hid_raw_request,
.output_report = quicki2c_hid_output_report,
};
/**
* quicki2c_hid_probe() - Register HID low level driver
*
* @qcdev: point to quicki2c device
*
* This function is used to allocate and add HID device.
*
* Return: 0 on success, non zero on error.
*/
int quicki2c_hid_probe(struct quicki2c_device *qcdev)
{
struct hid_device *hid;
int ret;
hid = hid_allocate_device();
if (IS_ERR(hid))
return PTR_ERR(hid);
hid->ll_driver = &quicki2c_hid_ll_driver;
hid->bus = BUS_PCI;
hid->dev.parent = qcdev->dev;
hid->driver_data = qcdev;
hid->version = le16_to_cpu(qcdev->dev_desc.version_id);
hid->vendor = le16_to_cpu(qcdev->dev_desc.vendor_id);
hid->product = le16_to_cpu(qcdev->dev_desc.product_id);
snprintf(hid->name, sizeof(hid->name), "%s %04X:%04X", "quicki2c-hid",
hid->vendor, hid->product);
strscpy(hid->phys, dev_name(qcdev->dev), sizeof(hid->phys));
ret = hid_add_device(hid);
if (ret) {
hid_destroy_device(hid);
return ret;
}
qcdev->hid_dev = hid;
return 0;
}
/**
* quicki2c_hid_remove() - Destroy HID device
*
* @qcdev: point to quicki2c device
*
* Return: 0 on success, non zero on error.
*/
void quicki2c_hid_remove(struct quicki2c_device *qcdev)
{
hid_destroy_device(qcdev->hid_dev);
}
/**
* quicki2c_hid_send_report() - Send HID input report data to HID core
*
* @qcdev: point to quicki2c device
* @data: point to input report data buffer
* @data_len: the length of input report data
*
* Return: 0 on success, non zero on error.
*/
int quicki2c_hid_send_report(struct quicki2c_device *qcdev,
void *data, size_t data_len)
{
int ret;
ret = hid_input_report(qcdev->hid_dev, HID_INPUT_REPORT, data, data_len, 1);
if (ret)
dev_err(qcdev->dev, "Failed to send HID input report, ret = %d.\n", ret);
return ret;
}
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-hid.h
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _QUICKI2C_HID_H_
#define _QUICKI2C_HID_H_
struct quicki2c_device;
int quicki2c_hid_send_report(struct quicki2c_device *qcdev,
void *data, size_t data_size);
int quicki2c_hid_probe(struct quicki2c_device *qcdev);
void quicki2c_hid_remove(struct quicki2c_device *qcdev);
#endif /* _QUICKI2C_HID_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-protocol.c
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2024 Intel Corporation */
#include <linux/bitfield.h>
#include <linux/hid.h>
#include <linux/hid-over-i2c.h>
#include <linux/unaligned.h>
#include "intel-thc-dev.h"
#include "intel-thc-dma.h"
#include "quicki2c-dev.h"
#include "quicki2c-hid.h"
#include "quicki2c-protocol.h"
static ssize_t quicki2c_init_write_buf(struct quicki2c_device *qcdev, u32 cmd, size_t cmd_len,
bool append_data_reg, u8 *data, size_t data_len,
u8 *write_buf, size_t write_buf_len)
{
size_t buf_len, offset = 0;
buf_len = HIDI2C_REG_LEN + cmd_len;
if (append_data_reg)
buf_len += HIDI2C_REG_LEN;
if (data && data_len)
buf_len += data_len + HIDI2C_LENGTH_LEN;
if (buf_len > write_buf_len)
return -EINVAL;
if (cmd_len) {
memcpy(write_buf, &qcdev->dev_desc.cmd_reg, HIDI2C_REG_LEN);
offset += HIDI2C_REG_LEN;
memcpy(write_buf + offset, &cmd, cmd_len);
offset += cmd_len;
if (append_data_reg) {
memcpy(write_buf + offset, &qcdev->dev_desc.data_reg, HIDI2C_REG_LEN);
offset += HIDI2C_REG_LEN;
}
} else {
memcpy(write_buf, &qcdev->dev_desc.output_reg, HIDI2C_REG_LEN);
offset += HIDI2C_REG_LEN;
}
if (data && data_len) {
put_unaligned_le16(data_len + HIDI2C_LENGTH_LEN, write_buf + offset);
offset += HIDI2C_LENGTH_LEN;
memcpy(write_buf + offset, data, data_len);
}
return buf_len;
}
static size_t quicki2c_encode_cmd(struct quicki2c_device *qcdev, u32 *cmd_buf,
u8 opcode, u8 report_type, u8 report_id)
{
size_t cmd_len;
*cmd_buf = FIELD_PREP(HIDI2C_CMD_OPCODE, opcode) |
FIELD_PREP(HIDI2C_CMD_REPORT_TYPE, report_type);
if (report_id < HIDI2C_CMD_MAX_RI) {
*cmd_buf |= FIELD_PREP(HIDI2C_CMD_REPORT_ID, report_id);
cmd_len = HIDI2C_CMD_LEN;
} else {
*cmd_buf |= FIELD_PREP(HIDI2C_CMD_REPORT_ID, HIDI2C_CMD_MAX_RI) |
FIELD_PREP(HIDI2C_CMD_3RD_BYTE, report_id);
cmd_len = HIDI2C_CMD_LEN_OPT;
}
return cmd_len;
}
static int write_cmd_to_txdma(struct quicki2c_device *qcdev, int opcode,
int report_type, int report_id, u8 *buf, size_t buf_len)
{
size_t cmd_len;
ssize_t len;
u32 cmd;
cmd_len = quicki2c_encode_cmd(qcdev, &cmd, opcode, report_type, report_id);
len = quicki2c_init_write_buf(qcdev, cmd, cmd_len, buf ? true : false, buf,
buf_len, qcdev->report_buf, qcdev->report_len);
if (len < 0)
return len;
return thc_dma_write(qcdev->thc_hw, qcdev->report_buf, len);
}
int quicki2c_set_power(struct quicki2c_device *qcdev, enum hidi2c_power_state power_state)
{
return write_cmd_to_txdma(qcdev, HIDI2C_SET_POWER, HIDI2C_RESERVED, power_state, NULL, 0);
}
int quicki2c_get_device_descriptor(struct quicki2c_device *qcdev)
{
u32 read_len = 0;
int ret;
ret = thc_tic_pio_write_and_read(qcdev->thc_hw, qcdev->hid_desc_addr,
HIDI2C_REG_LEN, NULL, HIDI2C_DEV_DESC_LEN,
&read_len, (u32 *)&qcdev->dev_desc);
if (ret || HIDI2C_DEV_DESC_LEN != read_len) {
dev_err_once(qcdev->dev, "Get device descriptor failed, ret %d, read len %u\n",
ret, read_len);
return -EIO;
}
if (le16_to_cpu(qcdev->dev_desc.bcd_ver) != HIDI2C_HID_DESC_BCDVERSION)
return -EOPNOTSUPP;
return 0;
}
int quicki2c_get_report_descriptor(struct quicki2c_device *qcdev)
{
u16 desc_reg = le16_to_cpu(qcdev->dev_desc.report_desc_reg);
size_t read_len = le16_to_cpu(qcdev->dev_desc.report_desc_len);
u32 prd_len = read_len;
return thc_swdma_read(qcdev->thc_hw, (u8 *)&desc_reg, HIDI2C_REG_LEN,
&prd_len, qcdev->report_descriptor, &read_len);
}
int quicki2c_get_report(struct quicki2c_device *qcdev, u8 report_type,
unsigned int reportnum, void *buf, size_t buf_len)
{
struct hidi2c_report_packet *rpt;
size_t cmd_len, read_len = 0;
int rep_type, ret;
ssize_t len;
u32 cmd;
if (report_type == HID_INPUT_REPORT) {
rep_type = HIDI2C_INPUT;
} else if (report_type == HID_FEATURE_REPORT) {
rep_type = HIDI2C_FEATURE;
} else {
dev_err(qcdev->dev, "Unsupported report type for GET REPORT: %d\n", report_type);
return -EINVAL;
}
cmd_len = quicki2c_encode_cmd(qcdev, &cmd, HIDI2C_GET_REPORT, rep_type, reportnum);
len = quicki2c_init_write_buf(qcdev, cmd, cmd_len, true, NULL, 0,
qcdev->report_buf, qcdev->report_len);
if (len < 0)
return len;
rpt = (struct hidi2c_report_packet *)qcdev->input_buf;
ret = thc_swdma_read(qcdev->thc_hw, qcdev->report_buf, len, NULL, rpt, &read_len);
if (ret) {
dev_err_once(qcdev->dev, "Get report failed, ret %d, read len (%zu vs %zu)\n",
ret, read_len, buf_len);
return ret;
}
if (HIDI2C_DATA_LEN(le16_to_cpu(rpt->len)) != buf_len || rpt->data[0] != reportnum) {
dev_err_once(qcdev->dev, "Invalid packet, len (%d vs %zu) report id (%d vs %d)\n",
le16_to_cpu(rpt->len), buf_len, rpt->data[0], reportnum);
return -EINVAL;
}
memcpy(buf, rpt->data, buf_len);
return buf_len;
}
int quicki2c_set_report(struct quicki2c_device *qcdev, u8 report_type,
unsigned int reportnum, void *buf, size_t buf_len)
{
int rep_type;
int ret;
if (report_type == HID_OUTPUT_REPORT) {
rep_type = HIDI2C_OUTPUT;
} else if (report_type == HID_FEATURE_REPORT) {
rep_type = HIDI2C_FEATURE;
} else {
dev_err(qcdev->dev, "Unsupported report type for SET REPORT: %d\n", report_type);
return -EINVAL;
}
ret = write_cmd_to_txdma(qcdev, HIDI2C_SET_REPORT, rep_type, reportnum, buf, buf_len);
if (ret) {
dev_err_once(qcdev->dev, "Set Report failed, ret %d\n", ret);
return ret;
}
return buf_len;
}
int quicki2c_output_report(struct quicki2c_device *qcdev, void *buf, size_t buf_len)
{
ssize_t len;
int ret;
len = quicki2c_init_write_buf(qcdev, 0, 0, false, buf, buf_len,
qcdev->report_buf, qcdev->report_len);
if (len < 0)
return -EINVAL;
ret = thc_dma_write(qcdev->thc_hw, qcdev->report_buf, len);
if (ret) {
dev_err(qcdev->dev, "Output Report failed, ret %d\n", ret);
return ret;
}
return buf_len;
}
#define HIDI2C_RESET_TIMEOUT 5
int quicki2c_reset(struct quicki2c_device *qcdev)
{
u16 input_reg = le16_to_cpu(qcdev->dev_desc.input_reg);
size_t read_len = HIDI2C_LENGTH_LEN;
u32 prd_len = read_len;
int ret;
qcdev->reset_ack = false;
qcdev->state = QUICKI2C_RESETING;
ret = write_cmd_to_txdma(qcdev, HIDI2C_RESET, HIDI2C_RESERVED, 0, NULL, 0);
if (ret) {
dev_err_once(qcdev->dev, "Send reset command failed, ret %d\n", ret);
return ret;
}
ret = wait_event_interruptible_timeout(qcdev->reset_ack_wq, qcdev->reset_ack,
HIDI2C_RESET_TIMEOUT * HZ);
if (qcdev->reset_ack)
return 0;
/*
* Manually read reset response if it wasn't received, in case reset interrupt
* was missed by touch device or THC hardware.
*/
ret = thc_tic_pio_read(qcdev->thc_hw, input_reg, read_len, &prd_len,
(u32 *)qcdev->input_buf);
if (ret) {
dev_err_once(qcdev->dev, "Read Reset Response failed, ret %d\n", ret);
return ret;
}
/*
* Check response packet length, it's first 16 bits of packet.
* If response packet length is zero, it's reset response, otherwise not.
*/
if (get_unaligned_le16(qcdev->input_buf)) {
dev_err_once(qcdev->dev,
"Wait reset response timed out ret:%d timeout:%ds\n",
ret, HIDI2C_RESET_TIMEOUT);
return -ETIMEDOUT;
}
qcdev->reset_ack = true;
return 0;
}
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-protocol.h
+21
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _QUICKI2C_PROTOCOL_H_
#define _QUICKI2C_PROTOCOL_H_
#include <linux/hid-over-i2c.h>
struct quicki2c_device;
int quicki2c_set_power(struct quicki2c_device *qcdev, enum hidi2c_power_state power_state);
int quicki2c_get_report(struct quicki2c_device *qcdev, u8 report_type,
unsigned int reportnum, void *buf, size_t buf_len);
int quicki2c_set_report(struct quicki2c_device *qcdev, u8 report_type,
unsigned int reportnum, void *buf, size_t buf_len);
int quicki2c_output_report(struct quicki2c_device *qcdev, void *buf, size_t buf_len);
int quicki2c_get_device_descriptor(struct quicki2c_device *qcdev);
int quicki2c_get_report_descriptor(struct quicki2c_device *qcdev);
int quicki2c_reset(struct quicki2c_device *qcdev);
#endif /* _QUICKI2C_PROTOCOL_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quickspi/pci-quickspi.c
+1068
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quickspi/quickspi-dev.h
+178
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _QUICKSPI_DEV_H_
#define _QUICKSPI_DEV_H_
#include <linux/bits.h>
#include <linux/hid-over-spi.h>
#include <linux/sizes.h>
#include <linux/wait.h>
#include "quickspi-protocol.h"
#define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT1 0x7E49
#define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT2 0x7E4B
#define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT1 0xA849
#define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT2 0xA84B
#define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT1 0xE349
#define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT2 0xE34B
#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT1 0xE449
#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT2 0xE44B
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT1 0x4D49
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT2 0x4D4B
#define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT1 0x7749
#define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT2 0x774B
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT1 0xD349
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT2 0xD34B
/* HIDSPI special ACPI parameters DSM methods */
#define ACPI_QUICKSPI_REVISION_NUM 2
#define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_HDR_ADDR 1
#define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_BDY_ADDR 2
#define ACPI_QUICKSPI_FUNC_NUM_OUTPUT_REP_ADDR 3
#define ACPI_QUICKSPI_FUNC_NUM_READ_OPCODE 4
#define ACPI_QUICKSPI_FUNC_NUM_WRITE_OPCODE 5
#define ACPI_QUICKSPI_FUNC_NUM_IO_MODE 6
/* QickSPI device special ACPI parameters DSM methods */
#define ACPI_QUICKSPI_FUNC_NUM_CONNECTION_SPEED 1
#define ACPI_QUICKSPI_FUNC_NUM_LIMIT_PACKET_SIZE 2
#define ACPI_QUICKSPI_FUNC_NUM_PERFORMANCE_LIMIT 3
/* Platform special ACPI parameters DSM methods */
#define ACPI_QUICKSPI_FUNC_NUM_ACTIVE_LTR 1
#define ACPI_QUICKSPI_FUNC_NUM_LP_LTR 2
#define SPI_WRITE_IO_MODE BIT(13)
#define SPI_IO_MODE_OPCODE GENMASK(15, 14)
#define PERFORMANCE_LIMITATION GENMASK(15, 0)
/* Packet size value, the unit is 16 bytes */
#define DEFAULT_MIN_PACKET_SIZE_VALUE 4
#define MAX_PACKET_SIZE_VALUE_MTL 128
#define MAX_PACKET_SIZE_VALUE_LNL 256
/*
* THC uses runtime auto suspend to dynamically switch between THC active LTR
* and low power LTR to save CPU power.
* Default value is 5000ms, that means if no touch event in this time, THC will
* change to low power LTR mode.
*/
#define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000
enum quickspi_dev_state {
QUICKSPI_NONE,
QUICKSPI_INITIATED,
QUICKSPI_RESETING,
QUICKSPI_RESET,
QUICKSPI_ENABLED,
QUICKSPI_DISABLED,
};
/**
* struct quickspi_driver_data - Driver specific data for quickspi device
* @max_packet_size_value: identify max packet size, unit is 16 bytes
*/
struct quickspi_driver_data {
u32 max_packet_size_value;
};
struct device;
struct pci_dev;
struct thc_device;
struct hid_device;
struct acpi_device;
/**
* struct quickspi_device - THC QuickSpi device struct
* @dev: point to kernel device
* @pdev: point to PCI device
* @thc_hw: point to THC device
* @hid_dev: point to hid device
* @acpi_dev: point to ACPI device
* @driver_data: point to quickspi specific driver data
* @state: THC SPI device state
* @mem_addr: MMIO memory address
* @dev_desc: device descriptor for HIDSPI protocol
* @input_report_hdr_addr: device input report header address
* @input_report_bdy_addr: device input report body address
* @output_report_bdy_addr: device output report address
* @spi_freq_val: device supported max SPI frequnecy, in Hz
* @spi_read_io_mode: device supported SPI read io mode
* @spi_write_io_mode: device supported SPI write io mode
* @spi_read_opcode: device read opcode
* @spi_write_opcode: device write opcode
* @limit_packet_size: 1 - limit read/write packet to 64Bytes
* 0 - device no packet size limiation for read/write
* @performance_limit: delay time, in ms.
* if device has performance limitation, must give a delay
* before write operation after a read operation.
* @active_ltr_val: THC active LTR value
* @low_power_ltr_val: THC low power LTR value
* @report_descriptor: store a copy of device report descriptor
* @input_buf: store a copy of latest input report data
* @report_buf: store a copy of latest input/output report packet from set/get feature
* @report_len: the length of input/output report packet
* @reset_ack_wq: workqueue for waiting reset response from device
* @reset_ack: indicate reset response received or not
* @nondma_int_received_wq: workqueue for waiting THC non-DMA interrupt
* @nondma_int_received: indicate THC non-DMA interrupt received or not
* @report_desc_got_wq: workqueue for waiting device report descriptor
* @report_desc_got: indicate device report descritor received or not
* @set_power_on_wq: workqueue for waiting set power on response from device
* @set_power_on: indicate set power on response received or not
* @get_feature_cmpl_wq: workqueue for waiting get feature response from device
* @get_feature_cmpl: indicate get feature received or not
* @set_feature_cmpl_wq: workqueue for waiting set feature to device
* @set_feature_cmpl: indicate set feature send complete or not
*/
struct quickspi_device {
struct device *dev;
struct pci_dev *pdev;
struct thc_device *thc_hw;
struct hid_device *hid_dev;
struct acpi_device *acpi_dev;
struct quickspi_driver_data *driver_data;
enum quickspi_dev_state state;
void __iomem *mem_addr;
struct hidspi_dev_descriptor dev_desc;
u32 input_report_hdr_addr;
u32 input_report_bdy_addr;
u32 output_report_addr;
u32 spi_freq_val;
u32 spi_read_io_mode;
u32 spi_write_io_mode;
u32 spi_read_opcode;
u32 spi_write_opcode;
u32 limit_packet_size;
u32 spi_packet_size;
u32 performance_limit;
u32 active_ltr_val;
u32 low_power_ltr_val;
u8 *report_descriptor;
u8 *input_buf;
u8 *report_buf;
u32 report_len;
wait_queue_head_t reset_ack_wq;
bool reset_ack;
wait_queue_head_t nondma_int_received_wq;
bool nondma_int_received;
wait_queue_head_t report_desc_got_wq;
bool report_desc_got;
wait_queue_head_t get_report_cmpl_wq;
bool get_report_cmpl;
wait_queue_head_t set_report_cmpl_wq;
bool set_report_cmpl;
};
#endif /* _QUICKSPI_DEV_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quickspi/quickspi-hid.c
+165
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#include <linux/hid.h>
#include <linux/input.h>
#include <linux/pm_runtime.h>
#include "quickspi-dev.h"
#include "quickspi-hid.h"
/**
* quickspi_hid_parse() - HID core parse() callback
*
* @hid: HID device instance
*
* This function gets called during call to hid_add_device
*
* Return: 0 on success and non zero on error.
*/
static int quickspi_hid_parse(struct hid_device *hid)
{
struct quickspi_device *qsdev = hid->driver_data;
if (qsdev->report_descriptor)
return hid_parse_report(hid, qsdev->report_descriptor,
le16_to_cpu(qsdev->dev_desc.rep_desc_len));
dev_err(qsdev->dev, "invalid report descriptor\n");
return -EINVAL;
}
static int quickspi_hid_start(struct hid_device *hid)
{
return 0;
}
static void quickspi_hid_stop(struct hid_device *hid)
{
}
static int quickspi_hid_open(struct hid_device *hid)
{
return 0;
}
static void quickspi_hid_close(struct hid_device *hid)
{
}
static int quickspi_hid_raw_request(struct hid_device *hid,
unsigned char reportnum,
__u8 *buf, size_t len,
unsigned char rtype, int reqtype)
{
struct quickspi_device *qsdev = hid->driver_data;
int ret = 0;
ret = pm_runtime_resume_and_get(qsdev->dev);
if (ret)
return ret;
switch (reqtype) {
case HID_REQ_GET_REPORT:
ret = quickspi_get_report(qsdev, rtype, reportnum, buf);
break;
case HID_REQ_SET_REPORT:
ret = quickspi_set_report(qsdev, rtype, reportnum, buf, len);
break;
default:
dev_err_once(qsdev->dev, "Not supported request type %d\n", reqtype);
break;
}
pm_runtime_put_autosuspend(qsdev->dev);
return ret;
}
static int quickspi_hid_power(struct hid_device *hid, int lvl)
{
return 0;
}
static struct hid_ll_driver quickspi_hid_ll_driver = {
.parse = quickspi_hid_parse,
.start = quickspi_hid_start,
.stop = quickspi_hid_stop,
.open = quickspi_hid_open,
.close = quickspi_hid_close,
.power = quickspi_hid_power,
.raw_request = quickspi_hid_raw_request,
};
/**
* quickspi_hid_probe() - Register HID low level driver
*
* @qsdev: point to quickspi device
*
* This function is used to allocate and add HID device.
*
* Return: 0 on success, non zero on error.
*/
int quickspi_hid_probe(struct quickspi_device *qsdev)
{
struct hid_device *hid;
int ret;
hid = hid_allocate_device();
if (IS_ERR(hid))
return PTR_ERR(hid);
hid->ll_driver = &quickspi_hid_ll_driver;
hid->bus = BUS_PCI;
hid->dev.parent = qsdev->dev;
hid->driver_data = qsdev;
hid->version = le16_to_cpu(qsdev->dev_desc.version_id);
hid->vendor = le16_to_cpu(qsdev->dev_desc.vendor_id);
hid->product = le16_to_cpu(qsdev->dev_desc.product_id);
snprintf(hid->name, sizeof(hid->name), "%s %04X:%04X", "quickspi-hid",
hid->vendor, hid->product);
strscpy(hid->phys, dev_name(qsdev->dev), sizeof(hid->phys));
ret = hid_add_device(hid);
if (ret) {
hid_destroy_device(hid);
return ret;
}
qsdev->hid_dev = hid;
return 0;
}
/**
* quickspi_hid_remove() - Destroy HID device
*
* @qsdev: point to quickspi device
*
* Return: 0 on success, non zero on error.
*/
void quickspi_hid_remove(struct quickspi_device *qsdev)
{
hid_destroy_device(qsdev->hid_dev);
}
/**
* quickspi_hid_send_report() - Send HID input report data to HID core
*
* @qsdev: point to quickspi device
* @data: point to input report data buffer
* @data_len: the length of input report data
*
* Return: 0 on success, non zero on error.
*/
int quickspi_hid_send_report(struct quickspi_device *qsdev,
void *data, size_t data_len)
{
int ret;
ret = hid_input_report(qsdev->hid_dev, HID_INPUT_REPORT, data, data_len, 1);
if (ret)
dev_err(qsdev->dev, "Failed to send HID input report, ret = %d.\n", ret);
return ret;
}
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quickspi/quickspi-hid.h
+14
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _QUICKSPI_HID_H_
#define _QUICKSPI_HID_H_
struct quickspi_device;
int quickspi_hid_send_report(struct quickspi_device *qsdev,
void *data, size_t data_size);
int quickspi_hid_probe(struct quickspi_device *qsdev);
void quickspi_hid_remove(struct quickspi_device *qsdev);
#endif /* _QUICKSPI_HID_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quickspi/quickspi-protocol.c
+413
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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright © 2024 Intel Corporation */
#include <linux/acpi.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/hid.h>
#include "intel-thc-dev.h"
#include "intel-thc-dma.h"
#include "quickspi-dev.h"
#include "quickspi-hid.h"
#include "quickspi-protocol.h"
/* THC uses HW to accelerate HID over SPI protocol, THC_M_PRT_DEV_INT_CAUSE
* register is used to store message header and body header, below definition
* let driver retrieve needed data filed easier from THC_M_PRT_DEV_INT_CAUSE
* register.
*/
#define HIDSPI_IN_REP_BDY_HDR_REP_TYPE GENMASK(7, 0)
static int write_cmd_to_txdma(struct quickspi_device *qsdev,
int report_type, int report_id,
u8 *report_buf, const int report_buf_len)
{
struct output_report *write_buf;
int write_buf_len;
int ret;
write_buf = (struct output_report *)qsdev->report_buf;
write_buf->output_hdr.report_type = report_type;
write_buf->output_hdr.content_len = cpu_to_le16(report_buf_len);
write_buf->output_hdr.content_id = report_id;
if (report_buf && report_buf_len > 0)
memcpy(write_buf->content, report_buf, report_buf_len);
write_buf_len = HIDSPI_OUTPUT_REPORT_SIZE(report_buf_len);
ret = thc_dma_write(qsdev->thc_hw, write_buf, write_buf_len);
if (ret)
dev_err_once(qsdev->dev, "DMA write failed, ret = %d\n", ret);
return ret;
}
static int quickspi_get_device_descriptor(struct quickspi_device *qsdev)
{
u8 read_buf[HIDSPI_INPUT_DEVICE_DESCRIPTOR_SIZE];
struct output_report output_rep;
u32 input_len, read_len = 0;
u32 int_cause_val;
u8 input_rep_type;
int ret;
output_rep.output_hdr.report_type = DEVICE_DESCRIPTOR;
output_rep.output_hdr.content_len = 0;
output_rep.output_hdr.content_id = 0;
qsdev->nondma_int_received = false;
ret = thc_tic_pio_write(qsdev->thc_hw, qsdev->output_report_addr,
HIDSPI_OUTPUT_REPORT_SIZE(0), (u32 *)&output_rep);
if (ret) {
dev_err_once(qsdev->dev,
"Write DEVICE_DESCRIPTOR command failed, ret = %d\n", ret);
return ret;
}
ret = wait_event_interruptible_timeout(qsdev->nondma_int_received_wq,
qsdev->nondma_int_received,
QUICKSPI_ACK_WAIT_TIMEOUT * HZ);
if (ret <= 0 || !qsdev->nondma_int_received) {
dev_err_once(qsdev->dev, "Wait DEVICE_DESCRIPTOR timeout, ret:%d\n", ret);
return -ETIMEDOUT;
}
qsdev->nondma_int_received = false;
int_cause_val = thc_int_cause_read(qsdev->thc_hw);
input_len = FIELD_GET(HIDSPI_INPUT_HEADER_REPORT_LEN, int_cause_val);
input_len = input_len * sizeof(u32);
if (input_len != HIDSPI_INPUT_DEVICE_DESCRIPTOR_SIZE) {
dev_err_once(qsdev->dev, "Receive wrong DEVICE_DESCRIPTOR length, len = %u\n",
input_len);
return -EINVAL;
}
ret = thc_tic_pio_read(qsdev->thc_hw, qsdev->input_report_bdy_addr,
input_len, &read_len, (u32 *)read_buf);
if (ret || read_len != input_len) {
dev_err_once(qsdev->dev, "Read DEVICE_DESCRIPTOR failed, ret = %d\n", ret);
dev_err_once(qsdev->dev, "DEVICE_DESCRIPTOR expected len = %u, actual read = %u\n",
input_len, read_len);
return ret ?: -EINVAL;
}
input_rep_type = ((struct input_report_body_header *)read_buf)->input_report_type;
if (input_rep_type == DEVICE_DESCRIPTOR_RESPONSE) {
memcpy(&qsdev->dev_desc,
read_buf + HIDSPI_INPUT_BODY_HEADER_SIZE,
HIDSPI_DEVICE_DESCRIPTOR_SIZE);
return 0;
}
dev_err_once(qsdev->dev, "Unexpected input report type: %d\n", input_rep_type);
return -EINVAL;
}
int quickspi_get_report_descriptor(struct quickspi_device *qsdev)
{
int ret;
ret = write_cmd_to_txdma(qsdev, REPORT_DESCRIPTOR, 0, NULL, 0);
if (ret) {
dev_err_once(qsdev->dev,
"Write REPORT_DESCRIPTOR command failed, ret = %d\n", ret);
return ret;
}
ret = wait_event_interruptible_timeout(qsdev->report_desc_got_wq,
qsdev->report_desc_got,
QUICKSPI_ACK_WAIT_TIMEOUT * HZ);
if (ret <= 0 || !qsdev->report_desc_got) {
dev_err_once(qsdev->dev, "Wait Report Descriptor timeout, ret:%d\n", ret);
return -ETIMEDOUT;
}
qsdev->report_desc_got = false;
return 0;
}
int quickspi_set_power(struct quickspi_device *qsdev,
enum hidspi_power_state power_state)
{
u8 cmd_content = power_state;
int ret;
ret = write_cmd_to_txdma(qsdev, COMMAND_CONTENT,
HIDSPI_SET_POWER_CMD_ID,
&cmd_content,
sizeof(cmd_content));
if (ret) {
dev_err_once(qsdev->dev, "Write SET_POWER command failed, ret = %d\n", ret);
return ret;
}
return 0;
}
void quickspi_handle_input_data(struct quickspi_device *qsdev, u32 buf_len)
{
struct input_report_body_header *body_hdr;
struct input_report_body *input_body;
u8 *input_report;
u32 input_len;
int ret = 0;
input_body = (struct input_report_body *)qsdev->input_buf;
body_hdr = &input_body->body_hdr;
input_len = le16_to_cpu(body_hdr->content_len);
if (HIDSPI_INPUT_BODY_SIZE(input_len) > buf_len) {
dev_err_once(qsdev->dev, "Wrong input report length: %u",
input_len);
return;
}
switch (body_hdr->input_report_type) {
case REPORT_DESCRIPTOR_RESPONSE:
if (input_len != le16_to_cpu(qsdev->dev_desc.rep_desc_len)) {
dev_err_once(qsdev->dev, "Unexpected report descriptor length: %u\n",
input_len);
return;
}
memcpy(qsdev->report_descriptor, input_body->content, input_len);
qsdev->report_desc_got = true;
wake_up_interruptible(&qsdev->report_desc_got_wq);
break;
case COMMAND_RESPONSE:
if (body_hdr->content_id == HIDSPI_SET_POWER_CMD_ID) {
dev_dbg(qsdev->dev, "Receive set power on response\n");
} else {
dev_err_once(qsdev->dev, "Unknown command response type: %u\n",
body_hdr->content_id);
}
break;
case RESET_RESPONSE:
if (qsdev->state == QUICKSPI_RESETING) {
qsdev->reset_ack = true;
wake_up_interruptible(&qsdev->reset_ack_wq);
dev_dbg(qsdev->dev, "Receive HIR reset response\n");
} else {
dev_info(qsdev->dev, "Receive DIR\n");
}
break;
case GET_FEATURE_RESPONSE:
case GET_INPUT_REPORT_RESPONSE:
qsdev->report_len = sizeof(body_hdr->content_id) + input_len;
input_report = input_body->content - sizeof(body_hdr->content_id);
memcpy(qsdev->report_buf, input_report, qsdev->report_len);
qsdev->get_report_cmpl = true;
wake_up_interruptible(&qsdev->get_report_cmpl_wq);
break;
case SET_FEATURE_RESPONSE:
case OUTPUT_REPORT_RESPONSE:
qsdev->set_report_cmpl = true;
wake_up_interruptible(&qsdev->set_report_cmpl_wq);
break;
case DATA:
if (qsdev->state != QUICKSPI_ENABLED)
return;
if (input_len > le16_to_cpu(qsdev->dev_desc.max_input_len)) {
dev_err_once(qsdev->dev, "Unexpected too large input report length: %u\n",
input_len);
return;
}
input_len = sizeof(body_hdr->content_id) + input_len;
input_report = input_body->content - sizeof(body_hdr->content_id);
ret = quickspi_hid_send_report(qsdev, input_report, input_len);
if (ret)
dev_err_once(qsdev->dev, "Failed to send HID input report: %d\n", ret);
break;
default:
dev_err_once(qsdev->dev, "Unsupported input report type: %u\n",
body_hdr->input_report_type);
break;
}
}
static int acpi_tic_reset(struct quickspi_device *qsdev)
{
acpi_status status = 0;
acpi_handle handle;
if (!qsdev->acpi_dev)
return -ENODEV;
handle = acpi_device_handle(qsdev->acpi_dev);
status = acpi_execute_simple_method(handle, "_RST", 0);
if (ACPI_FAILURE(status)) {
dev_err_once(qsdev->dev,
"Failed to reset device through ACPI method, ret = %d\n", status);
return -EIO;
}
return 0;
}
int reset_tic(struct quickspi_device *qsdev)
{
u32 actual_read_len, read_len = 0;
u32 input_report_len, reset_response, int_cause_val;
u8 input_rep_type;
int ret;
qsdev->state = QUICKSPI_RESETING;
qsdev->reset_ack = false;
thc_int_trigger_type_select(qsdev->thc_hw, true);
ret = acpi_tic_reset(qsdev);
if (ret)
return ret;
ret = thc_interrupt_quiesce(qsdev->thc_hw, false);
if (ret)
return ret;
ret = wait_event_interruptible_timeout(qsdev->reset_ack_wq,
qsdev->reset_ack,
QUICKSPI_ACK_WAIT_TIMEOUT * HZ);
if (ret <= 0 || !qsdev->reset_ack) {
dev_err_once(qsdev->dev, "Wait RESET_RESPONSE timeout, ret:%d\n", ret);
return -ETIMEDOUT;
}
int_cause_val = thc_int_cause_read(qsdev->thc_hw);
input_report_len = FIELD_GET(HIDSPI_INPUT_HEADER_REPORT_LEN, int_cause_val);
read_len = input_report_len * sizeof(u32);
if (read_len != HIDSPI_INPUT_BODY_SIZE(0)) {
dev_err_once(qsdev->dev, "Receive wrong RESET_RESPONSE, len = %u\n",
read_len);
return -EINVAL;
}
/* Switch to edge trigger matching with HIDSPI protocol definition */
thc_int_trigger_type_select(qsdev->thc_hw, true);
ret = thc_tic_pio_read(qsdev->thc_hw, qsdev->input_report_bdy_addr,
read_len, &actual_read_len,
(u32 *)&reset_response);
if (ret || actual_read_len != read_len) {
dev_err_once(qsdev->dev, "Read RESET_RESPONSE body failed, ret = %d\n", ret);
dev_err_once(qsdev->dev, "RESET_RESPONSE body expected len = %u, actual = %u\n",
read_len, actual_read_len);
return ret ?: -EINVAL;
}
input_rep_type = FIELD_GET(HIDSPI_IN_REP_BDY_HDR_REP_TYPE, reset_response);
if (input_rep_type == RESET_RESPONSE) {
dev_dbg(qsdev->dev, "RESET_RESPONSE received\n");
} else {
dev_err_once(qsdev->dev,
"Unexpected input report type: %d, expect RESET_RESPONSE\n",
input_rep_type);
return -EINVAL;
}
qsdev->state = QUICKSPI_RESET;
ret = quickspi_get_device_descriptor(qsdev);
if (ret)
return ret;
return 0;
}
int quickspi_get_report(struct quickspi_device *qsdev,
u8 report_type, unsigned int report_id, void *buf)
{
int rep_type;
int ret;
if (report_type == HID_INPUT_REPORT) {
rep_type = GET_INPUT_REPORT;
} else if (report_type == HID_FEATURE_REPORT) {
rep_type = GET_FEATURE;
} else {
dev_err_once(qsdev->dev, "Unsupported report type for GET REPORT: %d\n",
report_type);
return -EINVAL;
}
ret = write_cmd_to_txdma(qsdev, rep_type, report_id, NULL, 0);
if (ret) {
dev_err_once(qsdev->dev, "Write GET_REPORT command failed, ret = %d\n", ret);
return ret;
}
ret = wait_event_interruptible_timeout(qsdev->get_report_cmpl_wq,
qsdev->get_report_cmpl,
QUICKSPI_ACK_WAIT_TIMEOUT * HZ);
if (ret <= 0 || !qsdev->get_report_cmpl) {
dev_err_once(qsdev->dev, "Wait Get Report Response timeout, ret:%d\n", ret);
return -ETIMEDOUT;
}
qsdev->get_report_cmpl = false;
memcpy(buf, qsdev->report_buf, qsdev->report_len);
return qsdev->report_len;
}
int quickspi_set_report(struct quickspi_device *qsdev,
u8 report_type, unsigned int report_id,
void *buf, u32 buf_len)
{
int rep_type;
int ret;
if (report_type == HID_OUTPUT_REPORT) {
rep_type = OUTPUT_REPORT;
} else if (report_type == HID_FEATURE_REPORT) {
rep_type = SET_FEATURE;
} else {
dev_err_once(qsdev->dev, "Unsupported report type for SET REPORT: %d\n",
report_type);
return -EINVAL;
}
ret = write_cmd_to_txdma(qsdev, rep_type, report_id, buf + 1, buf_len - 1);
if (ret) {
dev_err_once(qsdev->dev, "Write SET_REPORT command failed, ret = %d\n", ret);
return ret;
}
ret = wait_event_interruptible_timeout(qsdev->set_report_cmpl_wq,
qsdev->set_report_cmpl,
QUICKSPI_ACK_WAIT_TIMEOUT * HZ);
if (ret <= 0 || !qsdev->set_report_cmpl) {
dev_err_once(qsdev->dev, "Wait Set Report Response timeout, ret:%d\n", ret);
return -ETIMEDOUT;
}
qsdev->set_report_cmpl = false;
return buf_len;
}
linux-7.2.3/drivers/hid/intel-thc-hid/intel-quickspi/quickspi-protocol.h
+25
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@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _QUICKSPI_PROTOCOL_H_
#define _QUICKSPI_PROTOCOL_H_
#include <linux/hid-over-spi.h>
#define QUICKSPI_ACK_WAIT_TIMEOUT 5
struct quickspi_device;
void quickspi_handle_input_data(struct quickspi_device *qsdev, u32 buf_len);
int quickspi_get_report(struct quickspi_device *qsdev, u8 report_type,
unsigned int report_id, void *buf);
int quickspi_set_report(struct quickspi_device *qsdev, u8 report_type,
unsigned int report_id, void *buf, u32 buf_len);
int quickspi_get_report_descriptor(struct quickspi_device *qsdev);
int quickspi_set_power(struct quickspi_device *qsdev,
enum hidspi_power_state power_state);
int reset_tic(struct quickspi_device *qsdev);
#endif /* _QUICKSPI_PROTOCOL_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-dev.c
+1768
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-dev.h
+133
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@@ -0,0 +1,133 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _INTEL_THC_DEV_H_
#define _INTEL_THC_DEV_H_
#include <linux/cdev.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include "intel-thc-dma.h"
#include "intel-thc-wot.h"
#define THC_REGMAP_COMMON_OFFSET 0x10
#define THC_REGMAP_MMIO_OFFSET 0x1000
/*
* THC Port type
* @THC_PORT_TYPE_SPI: This port is used for HIDSPI
* @THC_PORT_TYPE_I2C: This port is used for HIDI2C
*/
enum thc_port_type {
THC_PORT_TYPE_SPI = 0,
THC_PORT_TYPE_I2C = 1,
};
/**
* THC interrupt flag
* @THC_NONDMA_INT: THC non-DMA interrupt
* @THC_RXDMA1_INT: THC RxDMA1 interrupt
* @THC_RXDMA2_INT: THC RxDMA2 interrupt
* @THC_SWDMA_INT: THC SWDMA interrupt
* @THC_TXDMA_INT: THC TXDMA interrupt
* @THC_PIO_DONE_INT: THC PIO complete interrupt
* @THC_I2CSUBIP_INT: THC I2C subsystem interrupt
* @THC_TXN_ERR_INT: THC transfer error interrupt
* @THC_FATAL_ERR_INT: THC fatal error interrupt
*/
enum thc_int_type {
THC_NONDMA_INT = 0,
THC_RXDMA1_INT = 1,
THC_RXDMA2_INT = 2,
THC_SWDMA_INT = 3,
THC_TXDMA_INT = 4,
THC_PIO_DONE_INT = 5,
THC_I2CSUBIP_INT = 6,
THC_TXN_ERR_INT = 7,
THC_FATAL_ERR_INT = 8,
THC_UNKNOWN_INT
};
/**
* struct thc_device - THC private device struct
* @thc_regmap: MMIO regmap structure for accessing THC registers
* @mmio_addr: MMIO registers address
* @thc_bus_lock: Mutex locker for THC config
* @port_type: Port type of THC port instance
* @pio_int_supported: PIO interrupt supported flag
* @dma_ctx: DMA specific data
* @wot: THC Wake-on-Touch data
* @write_complete_wait: Signal event for DMA write complete
* @swdma_complete_wait: Signal event for SWDMA sequence complete
* @write_done: Bool value that indicates if DMA write is done
* @swdma_done: Bool value that indicates if SWDMA sequence is done
* @perf_limit: The delay between read operation and write operation
* @i2c_subip_regs: The copy of THC I2C sub-system registers for resuming restore
* @i2c_max_rx_size: I2C Rx transfer max input size
* @i2c_int_delay_us: I2C input interrupt delay, unit is us
* @i2c_max_rx_size_en: Bool value that indicates I2C max input size control enabled or not
* @i2c_int_delay_en: Bool value that indicates I2C input interrupt delay enabled or not
*/
struct thc_device {
struct device *dev;
struct regmap *thc_regmap;
void __iomem *mmio_addr;
struct mutex thc_bus_lock;
enum thc_port_type port_type;
bool pio_int_supported;
struct thc_dma_context *dma_ctx;
struct thc_wot wot;
wait_queue_head_t write_complete_wait;
wait_queue_head_t swdma_complete_wait;
bool write_done;
bool swdma_done;
u32 perf_limit;
u32 *i2c_subip_regs;
u32 i2c_max_rx_size;
u32 i2c_int_delay_us;
bool i2c_max_rx_size_en;
bool i2c_int_delay_en;
};
struct thc_device *thc_dev_init(struct device *device, void __iomem *mem_addr);
int thc_tic_pio_read(struct thc_device *dev, const u32 address,
const u32 size, u32 *actual_size, u32 *buffer);
int thc_tic_pio_write(struct thc_device *dev, const u32 address,
const u32 size, const u32 *buffer);
int thc_tic_pio_write_and_read(struct thc_device *dev, const u32 address,
const u32 write_size, const u32 *write_buffer,
const u32 read_size, u32 *actual_size, u32 *read_buffer);
void thc_interrupt_config(struct thc_device *dev);
void thc_int_trigger_type_select(struct thc_device *dev, bool edge_trigger);
void thc_interrupt_enable(struct thc_device *dev, bool int_enable);
void thc_set_pio_interrupt_support(struct thc_device *dev, bool supported);
int thc_interrupt_quiesce(const struct thc_device *dev, bool int_quiesce);
void thc_ltr_config(struct thc_device *dev, u32 active_ltr_us, u32 lp_ltr_us);
void thc_change_ltr_mode(struct thc_device *dev, u32 ltr_mode);
void thc_ltr_unconfig(struct thc_device *dev);
u32 thc_int_cause_read(struct thc_device *dev);
int thc_interrupt_handler(struct thc_device *dev);
int thc_port_select(struct thc_device *dev, enum thc_port_type port_type);
int thc_spi_read_config(struct thc_device *dev, u32 spi_freq_val,
u32 io_mode, u32 opcode, u32 spi_rd_mps);
int thc_spi_write_config(struct thc_device *dev, u32 spi_freq_val,
u32 io_mode, u32 opcode, u32 spi_wr_mps, u32 perf_limit);
void thc_spi_input_output_address_config(struct thc_device *dev, u32 input_hdr_addr,
u32 input_bdy_addr, u32 output_addr);
int thc_i2c_subip_init(struct thc_device *dev, const u32 target_address,
const u32 speed, const u32 hcnt, const u32 lcnt);
int thc_i2c_subip_regs_save(struct thc_device *dev);
int thc_i2c_subip_regs_restore(struct thc_device *dev);
int thc_i2c_set_rx_max_size(struct thc_device *dev, u32 max_rx_size);
int thc_i2c_rx_max_size_enable(struct thc_device *dev, bool enable);
int thc_i2c_set_rx_int_delay(struct thc_device *dev, u32 delay_us);
int thc_i2c_rx_int_delay_enable(struct thc_device *dev, bool enable);
#endif /* _INTEL_THC_DEV_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c
+1016
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.h
+156
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@@ -0,0 +1,156 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _INTEL_THC_DMA_H_
#define _INTEL_THC_DMA_H_
#include <linux/bits.h>
#include <linux/dma-mapping.h>
#include <linux/sizes.h>
#include <linux/time64.h>
#include <linux/types.h>
#define THC_POINTER_MASK GENMASK(6, 0)
#define THC_POINTER_WRAPAROUND 0x80
#define THC_WRAPAROUND_VALUE_ODD 0x10
#define THC_WRAPAROUND_VALUE_EVEN 0x90
#define THC_MIN_BYTES_PER_SG_LIST_ENTRY SZ_4K
#define THC_DEFAULT_RXDMA_POLLING_US_INTERVAL 100
#define THC_DEFAULT_RXDMA_POLLING_US_TIMEOUT (10 * USEC_PER_MSEC)
/*
* THC needs 1KB aligned address, dest_addr is 54 bits, not 64,
* so don't need to send the lower 10-bits of address.
*/
#define THC_ADDRESS_SHIFT 10
/**
* THC DMA channels:
* @THC_RXDMA1: Legacy channel, reserved for raw data reading
* @THC_RXDMA2: DMA to read HID data from touch device
* @THC_TXDMA: DMA to write to touch device
* @THC_SWDMA: SW triggered DMA to write and read from touch device
*/
enum thc_dma_channel {
THC_RXDMA1 = 0,
THC_RXDMA2 = 1,
THC_TXDMA = 2,
THC_SWDMA = 3,
MAX_THC_DMA_CHANNEL
};
/**
* THC DMA Physical Memory Descriptor (PRD)
* @dest_addr: Bit[53:0], destination address in system memory
* @int_on_completion: Bit[63], if set, thc will trigger interrupt to driver
* @len: Bit[87:64], length of this entry
* @end_of_prd: Bit[88], if set, this entry is last one of current PRD table
* @hw_status: Bit[90:89], hardware status bits
*/
struct thc_prd_entry {
u64 dest_addr : 54;
u64 reserved1 : 9;
u64 int_on_completion : 1;
u64 len : 24;
u64 end_of_prd : 1;
u64 hw_status : 2;
u64 reserved2 : 37;
};
/*
* Max OS memory fragmentation will be at a 4KB boundary, thus to address 1MB
* of virtually contiguous memory 256 PRD entries are required for a single
* PRD Table. SW writes the number of PRD Entries for each PRD table in the
* THC_M_PRT_RPRD_CNTRL.PTEC register field. The PRD entry's length must be
* multiple of 4KB except for the last entry in a PRD table.
* This is the max possible number of etries supported by HW, in practise we
* there will be less entries in each prd table(the actual number will be
* given by scatter-gather list allocation).
*/
#define PRD_ENTRIES_NUM 16
/*
* Number of PRD tables equals to number of data buffers.
* The max number of PRD tables supported by the HW is 128,
* but we allocate only 16.
*/
#define PRD_TABLES_NUM 16
/* THC DMA Physical Memory Descriptor Table */
struct thc_prd_table {
struct thc_prd_entry entries[PRD_ENTRIES_NUM];
};
#define PRD_TABLE_SIZE sizeof(struct thc_prd_table)
/**
* struct thc_dma_configuration - THC DMA configure
* @dma_channel: DMA channel for current DMA configuration
* @prd_tbls_dma_handle: DMA buffer handle
* @dir: Direction of DMA for this config
* @prd_tbls: PRD tables for current DMA
* @sgls: Array of pointers to scatter-gather lists
* @sgls_nent_pages: Number of pages per scatter-gather list
* @sgls_nent: Actual number of entries per scatter-gather list
* @prd_tbl_num: Actual number of PRD tables
* @max_packet_size: Size of the buffer needed for 1 DMA message (1 PRD table)
* @prd_base_addr_high: High 32bits memory address where stores PRD table
* @prd_base_addr_low: Low 32bits memory address where stores PRD table
* @prd_cntrl: PRD control register value
* @dma_cntrl: DMA control register value
*/
struct thc_dma_configuration {
enum thc_dma_channel dma_channel;
dma_addr_t prd_tbls_dma_handle;
enum dma_data_direction dir;
bool is_enabled;
struct thc_prd_table *prd_tbls;
struct scatterlist *sgls[PRD_TABLES_NUM];
u8 sgls_nent_pages[PRD_TABLES_NUM];
u8 sgls_nent[PRD_TABLES_NUM];
u8 prd_tbl_num;
size_t max_packet_size;
u32 prd_base_addr_high;
u32 prd_base_addr_low;
u32 prd_cntrl;
u32 dma_cntrl;
};
/**
* struct thc_dma_context - THC DMA context
* @thc_dma_configuration: Array of all THC Channel configures
* @use_write_interrupts: Indicate TxDMA using interrupt or polling
* @rx_max_size_en: Temp flag to indicate THC I2C Rx max input size control feature
* enabled or not, only be used during SWDMA operation.
* @rx_int_delay_en: Temp flag to indicate THC I2C Rx interrupt delay feature
* enabled or not, only be used during SWDMA operation.
*/
struct thc_dma_context {
struct thc_dma_configuration dma_config[MAX_THC_DMA_CHANNEL];
u8 use_write_interrupts;
bool rx_max_size_en;
bool rx_int_delay_en;
};
struct thc_device;
int thc_dma_set_max_packet_sizes(struct thc_device *dev,
size_t mps_read1, size_t mps_read2,
size_t mps_write, size_t mps_swdma);
int thc_dma_allocate(struct thc_device *dev);
int thc_dma_configure(struct thc_device *dev);
void thc_dma_unconfigure(struct thc_device *dev);
void thc_dma_release(struct thc_device *dev);
int thc_rxdma_read(struct thc_device *dev, enum thc_dma_channel dma_channel,
void *read_buff, size_t *read_len, int *read_finished);
int thc_swdma_read(struct thc_device *dev, void *write_buff, size_t write_len,
u32 *prd_tbl_len, void *read_buff, size_t *read_len);
int thc_dma_write(struct thc_device *dev, void *buffer, size_t buf_len);
struct thc_dma_context *thc_dma_init(struct thc_device *dev);
#endif /* _INTEL_THC_DMA_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h
+890
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@@ -0,0 +1,890 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Intel Corporation */
#ifndef _INTEL_THC_HW_H_
#define _INTEL_THC_HW_H_
#include <linux/bits.h>
/* THC registers offset */
/* Touch Host Controller Control Register */
#define THC_M_PRT_CONTROL_OFFSET 0x1008
/* THC SPI Bus Configuration Register */
#define THC_M_PRT_SPI_CFG_OFFSET 0x1010
/* THC SPI Bus Read Opcode Register */
#define THC_M_PRT_SPI_ICRRD_OPCODE_OFFSET 0x1014
/* THC SPI Bus Read Opcode Register */
#define THC_M_PRT_SPI_DMARD_OPCODE_OFFSET 0x1018
/* THC SPI Bus Write Opcode Register */
#define THC_M_PRT_SPI_WR_OPCODE_OFFSET 0x101C
/* THC Interrupt Enable Register */
#define THC_M_PRT_INT_EN_OFFSET 0x1020
/* THC Interrupt Status Register */
#define THC_M_PRT_INT_STATUS_OFFSET 0x1024
/* THC Error Cause Register */
#define THC_M_PRT_ERR_CAUSE_OFFSET 0x1028
/* THC SW sequencing Control */
#define THC_M_PRT_SW_SEQ_CNTRL_OFFSET 0x1040
/* THC SW sequencing Status */
#define THC_M_PRT_SW_SEQ_STS_OFFSET 0x1044
/* THC SW Sequencing Data DW0 or SPI Address Register */
#define THC_M_PRT_SW_SEQ_DATA0_ADDR_OFFSET 0x1048
/* THC SW sequencing Data DW1 */
#define THC_M_PRT_SW_SEQ_DATA1_OFFSET 0x104C
/* THC SW sequencing Data DW2 */
#define THC_M_PRT_SW_SEQ_DATA2_OFFSET 0x1050
/* THC SW sequencing Data DW3 */
#define THC_M_PRT_SW_SEQ_DATA3_OFFSET 0x1054
/* THC SW sequencing Data DW4 */
#define THC_M_PRT_SW_SEQ_DATA4_OFFSET 0x1058
/* THC SW sequencing Data DW5 */
#define THC_M_PRT_SW_SEQ_DATA5_OFFSET 0x105C
/* THC SW sequencing Data DW6 */
#define THC_M_PRT_SW_SEQ_DATA6_OFFSET 0x1060
/* THC SW sequencing Data DW7 */
#define THC_M_PRT_SW_SEQ_DATA7_OFFSET 0x1064
/* THC SW sequencing Data DW8 */
#define THC_M_PRT_SW_SEQ_DATA8_OFFSET 0x1068
/* THC SW sequencing Data DW9 */
#define THC_M_PRT_SW_SEQ_DATA9_OFFSET 0x106C
/* THC SW sequencing Data DW10 */
#define THC_M_PRT_SW_SEQ_DATA10_OFFSET 0x1070
/* THC SW sequencing Data DW11 */
#define THC_M_PRT_SW_SEQ_DATA11_OFFSET 0x1074
/* THC SW sequencing Data DW12 */
#define THC_M_PRT_SW_SEQ_DATA12_OFFSET 0x1078
/* THC SW sequencing Data DW13 */
#define THC_M_PRT_SW_SEQ_DATA13_OFFSET 0x107C
/* THC SW sequencing Data DW14 */
#define THC_M_PRT_SW_SEQ_DATA14_OFFSET 0x1080
/* THC SW sequencing Data DW15 */
#define THC_M_PRT_SW_SEQ_DATA15_OFFSET 0x1084
/* THC SW sequencing Data DW16 */
#define THC_M_PRT_SW_SEQ_DATA16_OFFSET 0x1088
/* THC Write PRD Base Address Register Low */
#define THC_M_PRT_WPRD_BA_LOW_OFFSET 0x1090
/* THC Write PRD Base Address Register High */
#define THC_M_PRT_WPRD_BA_HI_OFFSET 0x1094
/* THC Write DMA Control */
#define THC_M_PRT_WRITE_DMA_CNTRL_OFFSET 0x1098
/* THC Write Interrupt Status */
#define THC_M_PRT_WRITE_INT_STS_OFFSET 0x109C
/* THC Write DMA Error Register */
#define THC_M_PRT_WRITE_DMA_ERR_OFFSET 0x10A0
/* THC device address for the bulk write */
#define THC_M_PRT_WR_BULK_ADDR_OFFSET 0x10B4
/* THC Device Interrupt Cause Register Address */
#define THC_M_PRT_DEV_INT_CAUSE_ADDR_OFFSET 0x10B8
/* THC Device Interrupt Cause Register Value */
#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_OFFSET 0x10BC
/* THC TXDMA Frame Count */
#define THC_M_PRT_TX_FRM_CNT_OFFSET 0x10E0
/* THC TXDMA Packet Count */
#define THC_M_PRT_TXDMA_PKT_CNT_OFFSET 0x10E4
/* THC Device Interrupt Count on this port */
#define THC_M_PRT_DEVINT_CNT_OFFSET 0x10E8
/* Touch Device Interrupt Cause register Format Configuration Register 1 */
#define THC_M_PRT_DEVINT_CFG_1_OFFSET 0x10EC
/* Touch Device Interrupt Cause register Format Configuration Register 2 */
#define THC_M_PRT_DEVINT_CFG_2_OFFSET 0x10F0
/* THC Read PRD Base Address Low for the 1st RXDMA */
#define THC_M_PRT_RPRD_BA_LOW_1_OFFSET 0x1100
/* THC Read PRD Base Address High for the 1st RXDMA */
#define THC_M_PRT_RPRD_BA_HI_1_OFFSET 0x1104
/* THC Read PRD Control for the 1st RXDMA */
#define THC_M_PRT_RPRD_CNTRL_1_OFFSET 0x1108
/* THC Read DMA Control for the 1st RXDMA */
#define THC_M_PRT_READ_DMA_CNTRL_1_OFFSET 0x110C
/* THC Read Interrupt Status for the 1st RXDMA */
#define THC_M_PRT_READ_DMA_INT_STS_1_OFFSET 0x1110
/* THC Read DMA Error Register for the 1st RXDMA */
#define THC_M_PRT_READ_DMA_ERR_1_OFFSET 0x1114
/* Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA */
#define THC_M_PRT_GUC_OFFSET_LOW_1_OFFSET 0x1118
/* Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA */
#define THC_M_PRT_GUC_OFFSET_HI_1_OFFSET 0x111C
/* Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA */
#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_1_OFFSET 0x1120
/* Touch Host Controller GuC Control register for the 1st RXDMA */
#define THC_M_PRT_GUC_WORKQ_SZ_1_OFFSET 0x1124
/* Touch Sequencer Control for the 1st DMA */
#define THC_M_PRT_TSEQ_CNTRL_1_OFFSET 0x1128
/* Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA */
#define THC_M_PRT_GUC_DB_ADDR_LOW_1_OFFSET 0x1130
/* Touch Sequencer GuC Doorbell Address High for the 1st RXDMA */
#define THC_M_PRT_GUC_DB_ADDR_HI_1_OFFSET 0x1134
/* Touch Sequencer GuC Doorbell Data */
#define THC_M_PRT_GUC_DB_DATA_1_OFFSET 0x1138
/* Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA */
#define THC_M_PRT_GUC_OFFSET_INITVAL_1_OFFSET 0x1140
/* THC Device Address for the bulk/touch data read for the 1st RXDMA */
#define THC_M_PRT_RD_BULK_ADDR_1_OFFSET 0x1170
/* THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port */
#define THC_M_PRT_DB_CNT_1_OFFSET 0x11A0
/* THC Frame Count from the 1st Stream RXDMA on this port */
#define THC_M_PRT_FRM_CNT_1_OFFSET 0x11A4
/* THC Micro Frame Count from the 1st Stream RXDMA on this port */
#define THC_M_PRT_UFRM_CNT_1_OFFSET 0x11A8
/* THC Packet Count from the 1st Stream RXDMA on this port */
#define THC_M_PRT_RXDMA_PKT_CNT_1_OFFSET 0x11AC
/*
* THC Software Interrupt Count from the 1st Stream RXDMA
* on this port
*/
#define THC_M_PRT_SWINT_CNT_1_OFFSET 0x11B0
/* Touch Sequencer Frame Drop Counter for the 1st RXDMA */
#define THC_M_PRT_FRAME_DROP_CNT_1_OFFSET 0x11B4
/* THC Coaescing 1 */
#define THC_M_PRT_COALESCE_1_OFFSET 0x11B8
/* THC Read PRD Base Address Low for the 2nd RXDMA */
#define THC_M_PRT_RPRD_BA_LOW_2_OFFSET 0x1200
/* THC Read PRD Base Address High for the 2nd RXDMA */
#define THC_M_PRT_RPRD_BA_HI_2_OFFSET 0x1204
/* THC Read PRD Control for the 2nd RXDMA */
#define THC_M_PRT_RPRD_CNTRL_2_OFFSET 0x1208
/* THC Read DMA Control for the 2nd RXDMA */
#define THC_M_PRT_READ_DMA_CNTRL_2_OFFSET 0x120C
/* THC Read Interrupt Status for the 2nd RXDMA */
#define THC_M_PRT_READ_DMA_INT_STS_2_OFFSET 0x1210
/* THC Read DMA Error Register for the 2nd RXDMA */
#define THC_M_PRT_READ_DMA_ERR_2_OFFSET 0x1214
/* Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA */
#define THC_M_PRT_GUC_OFFSET_LOW_2_OFFSET 0x1218
/* Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA */
#define THC_M_PRT_GUC_OFFSET_HI_2_OFFSET 0x121C
/* Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA */
#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_2_OFFSET 0x1220
/* Touch Host Controller GuC Control register for the 2nd RXDMA */
#define THC_M_PRT_GUC_WORKQ_SZ_2_OFFSET 0x1224
/* Touch Sequencer Control for the 2nd DMA */
#define THC_M_PRT_TSEQ_CNTRL_2_OFFSET 0x1228
/* Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA */
#define THC_M_PRT_GUC_DB_ADDR_LOW_2_OFFSET 0x1230
/* Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA */
#define THC_M_PRT_GUC_DB_ADDR_HI_2_OFFSET 0x1234
/* Touch Sequencer GuC Doorbell Data for PRD2 */
#define THC_M_PRT_GUC_DB_DATA_2_OFFSET 0x1238
/* Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA */
#define THC_M_PRT_GUC_OFFSET_INITVAL_2_OFFSET 0x1240
/* THC Device Address for the bulk/touch data read for the 2nd RXDMA */
#define THC_M_PRT_RD_BULK_ADDR_2_OFFSET 0x1270
/* THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port */
#define THC_M_PRT_DB_CNT_2_OFFSET 0x12A0
/* THC Frame Count from the 2nd Stream RXDMA on this port */
#define THC_M_PRT_FRM_CNT_2_OFFSET 0x12A4
/* THC Micro Frame Count from the 2nd Stream RXDMA on this port */
#define THC_M_PRT_UFRM_CNT_2_OFFSET 0x12A8
/* THC Packet Count from the 2nd Stream RXDMA on this port */
#define THC_M_PRT_RXDMA_PKT_CNT_2_OFFSET 0x12AC
/*
* THC Software Interrupt Count from the 2nd Stream RXDMA
* on this port
*/
#define THC_M_PRT_SWINT_CNT_2_OFFSET 0x12B0
/* Touch Sequencer Frame Drop Counter for the 2nd RXDMA */
#define THC_M_PRT_FRAME_DROP_CNT_2_OFFSET 0x12B4
/* THC Coaescing 2 */
#define THC_M_PRT_COALESCE_2_OFFSET 0x12B8
/* THC SPARE REGISTER */
#define THC_M_PRT_SPARE_REG_OFFSET 0x12BC
/* THC Read PRD Base Address Low for the SW RXDMA */
#define THC_M_PRT_RPRD_BA_LOW_SW_OFFSET 0x12C0
/* THC Read PRD Base Address High for the SW RXDMA */
#define THC_M_PRT_RPRD_BA_HI_SW_OFFSET 0x12C4
/* THC Read PRD Control for the SW RXDMA */
#define THC_M_PRT_RPRD_CNTRL_SW_OFFSET 0x12C8
/* THC Read DMA Control for the SW RXDMA */
#define THC_M_PRT_READ_DMA_CNTRL_SW_OFFSET 0x12CC
/* THC Read Interrupt Status for the SW RXDMA */
#define THC_M_PRT_READ_DMA_INT_STS_SW_OFFSET 0x12D0
/* Touch Sequencer Control for the SW DMA */
#define THC_M_PRT_TSEQ_CNTRL_SW_OFFSET 0x12D4
/* Address for the bulk read for SW DMA engine */
#define THC_M_PRT_RD_BULK_ADDR_SW_OFFSET 0x12D8
/* THC Frame Count from the SW RXDMA on this port */
#define THC_M_PRT_FRM_CNT_SW_OFFSET 0x12DC
/* THC Packet Count from the SW RXDMA on this port */
#define THC_M_PRT_RXDMA_PKT_CNT_SW_OFFSET 0x12E0
/* SW DMA PRD Table Length */
#define THC_M_PRT_SW_DMA_PRD_TABLE_LEN_OFFSET 0x12E4
/* THC timing based Frame/Interrupt caolescing control register for 1st RXDMA */
#define THC_M_PRT_COALESCE_CNTRL_1_OFFSET 0x12E8
/* THC timing based Frame/Interrupt caolescing control register for 2nd RXDMA */
#define THC_M_PRT_COALESCE_CNTRL_2_OFFSET 0x12EC
/* Touch Sequencer PRD Table Empty Counter for the 1st RXDMA */
#define THC_M_PRT_PRD_EMPTY_CNT_1_OFFSET 0x12F0
/* Touch Sequencer PRD Table Empty Counter for the 2nd RXDM */
#define THC_M_PRT_PRD_EMPTY_CNT_2_OFFSET 0x12F4
/* THC coalescing status to reflect the current coalescing FSM state for 1st RXDMA */
#define THC_M_PRT_COALESCE_STS_1_OFFSET 0x12F8
/* THC coalescing status to reflect the current coalescing FSM state for 2nd RXDMA */
#define THC_M_PRT_COALESCE_STS_2_OFFSET 0x12FC
/* THC Register for the SPI Port Duty Cycle Configuration */
#define THC_M_PRT_SPI_DUTYC_CFG_OFFSET 0x1300
/* THC Register for SW I2C Wtite Sequecning control */
#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_OFFSET 0x1304
/* THC current Timestamp Register for RXDMA1 */
#define THC_M_PRT_TIMESTAMP_1_OFFSET 0x1308
/* THC current Timestamp Register for RXDMA2 */
#define THC_M_PRT_TIMESTAMP_2_OFFSET 0x130C
/* Current SYNC Event Timestamp Register */
#define THC_M_PRT_SYNC_TIMESTAMP_OFFSET 0x1310
/* THC Display Sync Register */
#define THC_M_PRT_DISP_SYNC_OFFSET 0x1314
/* THC Display Sync Register */
#define THC_M_PRT_DISP_SYNC_2_OFFSET 0x1318
/* THC Register for SW I2C Wtite Sequecning control */
#define THC_M_PRT_I2C_CFG_OFFSET 0x131C
/* THC register bits definition */
#define TXN_ERR_INT_STS_BIT BIT(28)
#define TXN_FATAL_INT_STS_BIT BIT(30)
#define NONDMA_INT_STS_BIT BIT(4)
#define EOF_INT_STS_BIT BIT(5)
#define THC_CFG_DID_VID_VID GENMASK(15, 0)
#define THC_CFG_DID_VID_DID GENMASK(31, 16)
#define THC_CFG_STS_CMD_IOSE BIT(0)
#define THC_CFG_STS_CMD_MSE BIT(1)
#define THC_CFG_STS_CMD_BME BIT(2)
#define THC_CFG_STS_CMD_SPCYC BIT(3)
#define THC_CFG_STS_CMD_MWRIEN BIT(4)
#define THC_CFG_STS_CMD_VGAPS BIT(5)
#define THC_CFG_STS_CMD_PERRR BIT(6)
#define THC_CFG_STS_CMD_SERREN BIT(8)
#define THC_CFG_STS_CMD_FBTBEN BIT(9)
#define THC_CFG_STS_CMD_INTD BIT(10)
#define THC_CFG_STS_CMD_INTS BIT(19)
#define THC_CFG_STS_CMD_CAPL BIT(20)
#define THC_CFG_STS_CMD_MCAP BIT(21)
#define THC_CFG_STS_CMD_FBTBC BIT(23)
#define THC_CFG_STS_CMD_MDPE BIT(24)
#define THC_CFG_STS_CMD_DEVT GENMASK(26, 25)
#define THC_CFG_STS_CMD_STA BIT(27)
#define THC_CFG_STS_CMD_RTA BIT(28)
#define THC_CFG_STS_CMD_RMA BIT(29)
#define THC_CFG_STS_CMD_SSE BIT(30)
#define THC_CFG_STS_CMD_DPE BIT(31)
#define THC_CFG_CC_RID_RID GENMASK(7, 0)
#define THC_CFG_CC_RID_PI GENMASK(15, 8)
#define THC_CFG_CC_RID_SCC GENMASK(23, 16)
#define THC_CFG_CC_RID_BCC GENMASK(31, 24)
#define THC_CFG_BIST_HTYPE_LT_CLS_CLSZ GENMASK(7, 0)
#define THC_CFG_BIST_HTYPE_LT_CLS_LT GENMASK(15, 8)
#define THC_CFG_BIST_HTYPE_LT_CLS_HTYPE GENMASK(22, 16)
#define THC_CFG_BIST_HTYPE_LT_CLS_MFD BIT(23)
#define THC_CFG_BAR0_LOW_MEMSPACE BIT(0)
#define THC_CFG_BAR0_LOW_TYP GENMASK(2, 1)
#define THC_CFG_BAR0_LOW_PREFETCH BIT(3)
#define THC_CFG_BAR0_LOW_MEMSIZE GENMASK(14, 4)
#define THC_CFG_BAR0_LOW_MEMBAR GENMASK(31, 15)
#define THC_CFG_BAR0_HI_MEMBAR GENMASK(31, 0)
#define THC_CFG_SID_SVID_SSVID GENMASK(15, 0)
#define THC_CFG_SID_SVID_SSID GENMASK(31, 16)
#define THC_CFG_CAPP_CP GENMASK(7, 0)
#define THC_CFG_INT_ILINE GENMASK(7, 0)
#define THC_CFG_INT_IPIN GENMASK(15, 8)
#define THC_CFG_UR_STS_CTL_URRE BIT(0)
#define THC_CFG_UR_STS_CTL_URD BIT(1)
#define THC_CFG_UR_STS_CTL_FD BIT(2)
#define THC_CFG_MSIMC_MSINP_MSICID_CAPID GENMASK(7, 0)
#define THC_CFG_MSIMC_MSINP_MSICID_NXTP GENMASK(15, 8)
#define THC_CFG_MSIMC_MSINP_MSICID_MSIE BIT(16)
#define THC_CFG_MSIMC_MSINP_MSICID_MMC GENMASK(19, 17)
#define THC_CFG_MSIMC_MSINP_MSICID_MMEN GENMASK(22, 20)
#define THC_CFG_MSIMC_MSINP_MSICID_XAC BIT(23)
#define THC_CFG_MSIMC_MSINP_MSICID_PVMC BIT(24)
#define THC_CFG_MSIMA_MADDR GENMASK(31, 2)
#define THC_CFG_MSIMUA_MAUDDR GENMASK(31, 0)
#define THC_CFG_MSIMD_MDAT GENMASK(15, 0)
#define THC_CFG_PMCAP_PMNP_PMCID_CAPP GENMASK(7, 0)
#define THC_CFG_PMCAP_PMNP_PMCID_NXTP GENMASK(15, 8)
#define THC_CFG_PMCAP_PMNP_PMCID_VER GENMASK(18, 16)
#define THC_CFG_PMCAP_PMNP_PMCID_PMECLK BIT(19)
#define THC_CFG_PMCAP_PMNP_PMCID_DSI BIT(21)
#define THC_CFG_PMCAP_PMNP_PMCID_AUXC GENMASK(24, 22)
#define THC_CFG_PMCAP_PMNP_PMCID_D1S BIT(25)
#define THC_CFG_PMCAP_PMNP_PMCID_D2S BIT(26)
#define THC_CFG_PMCAP_PMNP_PMCID_PMES GENMASK(31, 27)
#define THC_CFG_PMD_PMCSRBSE_PMCSR_PWRST GENMASK(1, 0)
#define THC_CFG_PMD_PMCSRBSE_PMCSR_NSR BIT(3)
#define THC_CFG_PMD_PMCSRBSE_PMCSR_PMEEN BIT(8)
#define THC_CFG_PMD_PMCSRBSE_PMCSR_DSEL GENMASK(12, 9)
#define THC_CFG_PMD_PMCSRBSE_PMCSR_DS GENMASK(14, 13)
#define THC_CFG_PMD_PMCSRBSE_PMCSR_PMESTS BIT(15)
#define THC_CFG_DEVIDLE_CAPPID GENMASK(7, 0)
#define THC_CFG_DEVIDLE_NCAPPP GENMASK(15, 8)
#define THC_CFG_DEVIDLE_LENGTH GENMASK(23, 16)
#define THC_CFG_DEVIDLE_REV GENMASK(27, 24)
#define THC_CFG_DEVIDLE_VID GENMASK(31, 28)
#define THC_CFG_VSHDR_VSECID GENMASK(15, 0)
#define THC_CFG_VSHDR_VSECR GENMASK(19, 16)
#define THC_CFG_VSHDR_VSECL GENMASK(31, 20)
#define THC_CFG_SWLTRPTR_VALID BIT(0)
#define THC_CFG_SWLTRPTR_BARNUM GENMASK(3, 1)
#define THC_CFG_SWLTRPTR_SWLTRLOC GENMASK(31, 4)
#define THC_CFG_DEVIDLEPTR_VALID BIT(0)
#define THC_CFG_DEVIDLEPTR_BARNUM GENMASK(3, 1)
#define THC_CFG_DEVIDLEPTR_DEVIDLELOC GENMASK(31, 4)
#define THC_CFG_DEVIDLEPOL_POLV GENMASK(9, 0)
#define THC_CFG_DEVIDLEPOL_POLS GENMASK(12, 10)
#define THC_CFG_PCE_SPE BIT(0)
#define THC_CFG_PCE_I3E BIT(1)
#define THC_CFG_PCE_D3HE BIT(2)
#define THC_CFG_PCE_SE BIT(3)
#define THC_CFG_PCE_HAE BIT(5)
#define THC_CFG_MANID_PROC GENMASK(7, 0)
#define THC_CFG_MANID_MID GENMASK(15, 8)
#define THC_CFG_MANID_MSID GENMASK(23, 16)
#define THC_CFG_MANID_DOT GENMASK(27, 24)
#define THC_M_CMN_DEVIDLECTRL_CIP BIT(0)
#define THC_M_CMN_DEVIDLECTRL_IR BIT(1)
#define THC_M_CMN_DEVIDLECTRL_DEVIDLE BIT(2)
#define THC_M_CMN_DEVIDLECTRL_RR BIT(3)
#define THC_M_CMN_DEVIDLECTRL_IRC BIT(4)
#define THC_M_CMN_LTR_CTRL_OFFSET 0x14
#define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_REQ BIT(0)
#define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_EN BIT(1)
#define THC_M_CMN_LTR_CTRL_LP_LTR_REQ BIT(2)
#define THC_M_CMN_LTR_CTRL_LP_LTR_EN BIT(3)
#define THC_M_CMN_LTR_CTRL_LP_LTR_SCALE GENMASK(6, 4)
#define THC_M_CMN_LTR_CTRL_LP_LTR_VAL GENMASK(16, 7)
#define THC_M_CMN_LTR_CTRL_ACT_LTR_SCALE GENMASK(19, 17)
#define THC_M_CMN_LTR_CTRL_ACT_LTR_VAL GENMASK(29, 20)
#define THC_M_CMN_LTR_CTRL_LAST_LTR_SENT GENMASK(31, 30)
#define THC_M_PRT_CONTROL_TSFTRST BIT(0)
#define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_EN BIT(1)
#define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_HW_STS BIT(2)
#define THC_M_PRT_CONTROL_DEVRST BIT(3)
#define THC_M_PRT_CONTROL_THC_DRV_LOCK_EN BIT(13)
#define THC_M_PRT_CONTROL_THC_INSTANCE_INDEX GENMASK(18, 16)
#define THC_M_PRT_CONTROL_PORT_INDEX GENMASK(22, 20)
#define THC_M_PRT_CONTROL_THC_ARB_POLICY GENMASK(25, 24)
#define THC_M_PRT_CONTROL_THC_BIOS_LOCK_EN BIT(27)
#define THC_M_PRT_CONTROL_PORT_SUPPORTED BIT(28)
#define THC_M_PRT_CONTROL_SPI_IO_RDY BIT(29)
#define THC_M_PRT_CONTROL_PORT_TYPE GENMASK(31, 30)
#define THC_M_PRT_SPI_CFG_SPI_TRDC GENMASK(1, 0)
#define THC_M_PRT_SPI_CFG_SPI_TRMODE GENMASK(3, 2)
#define THC_M_PRT_SPI_CFG_SPI_TCRF GENMASK(6, 4)
#define THC_M_PRT_SPI_CFG_SPI_RD_MPS GENMASK(15, 7)
#define THC_M_PRT_SPI_CFG_SPI_TWMODE GENMASK(19, 18)
#define THC_M_PRT_SPI_CFG_SPI_TCWF GENMASK(22, 20)
#define THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN BIT(23)
#define THC_M_PRT_SPI_CFG_SPI_WR_MPS GENMASK(31, 24)
#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_SIO GENMASK(31, 24)
#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_DIO GENMASK(23, 16)
#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_QIO GENMASK(15, 8)
#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_MAX_SIZE GENMASK(15, 0)
#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_INTERVAL GENMASK(23, 16)
#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_INTERVAL_EN BIT(30)
#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_MAX_SIZE_EN BIT(31)
#define THC_M_PRT_INT_EN_SIPE BIT(0)
#define THC_M_PRT_INT_EN_SBO BIT(1)
#define THC_M_PRT_INT_EN_SIDR BIT(2)
#define THC_M_PRT_INT_EN_SOFB BIT(3)
#define THC_M_PRT_INT_EN_INVLD_DEV_ENTRY_INT_EN BIT(9)
#define THC_M_PRT_INT_EN_FRAME_BABBLE_ERR_INT_EN BIT(10)
#define THC_M_PRT_INT_EN_BUF_OVRRUN_ERR_INT_EN BIT(12)
#define THC_M_PRT_INT_EN_PRD_ENTRY_ERR_INT_EN BIT(13)
#define THC_M_PRT_INT_EN_DISP_SYNC_EVT_INT_EN BIT(14)
#define THC_M_PRT_INT_EN_DEV_RAW_INT_EN BIT(15)
#define THC_M_PRT_INT_EN_FATAL_ERR_INT_EN BIT(16)
#define THC_M_PRT_INT_EN_THC_I2C_IC_RX_UNDER_INT_EN BIT(17)
#define THC_M_PRT_INT_EN_THC_I2C_IC_RX_OVER_INT_EN BIT(18)
#define THC_M_PRT_INT_EN_THC_I2C_IC_RX_FULL_INT_EN BIT(19)
#define THC_M_PRT_INT_EN_THC_I2C_IC_TX_OVER_INT_EN BIT(20)
#define THC_M_PRT_INT_EN_THC_I2C_IC_TX_EMPTY_INT_EN BIT(21)
#define THC_M_PRT_INT_EN_THC_I2C_IC_TX_ABRT_INT_EN BIT(22)
#define THC_M_PRT_INT_EN_THC_I2C_IC_SCL_STUCK_AT_LOW_DET_INT_EN BIT(24)
#define THC_M_PRT_INT_EN_THC_I2C_IC_STOP_DET_INT_EN BIT(25)
#define THC_M_PRT_INT_EN_THC_I2C_IC_START_DET_INT_EN BIT(26)
#define THC_M_PRT_INT_EN_THC_I2C_IC_MST_ON_HOLD_INT_EN BIT(27)
#define THC_M_PRT_INT_EN_TXN_ERR_INT_EN BIT(29)
#define THC_M_PRT_INT_EN_GBL_INT_EN BIT(31)
#define THC_M_PRT_INT_STATUS_DISP_SYNC_EVT_INT_STS BIT(14)
#define THC_M_PRT_INT_STATUS_DEV_RAW_INT_STS BIT(15)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_UNDER_INT_STS BIT(17)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_OVER_INT_STS BIT(18)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_FULL_INT_STS BIT(19)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_OVER_INT_STS BIT(20)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_EMPTY_INT_STS BIT(21)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_ABRT_INT_STS BIT(22)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_ACTIVITY_INT_STS BIT(23)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_SCL_STUCK_AT_LOW_INT_STS BIT(24)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_STOP_DET_INT_STS BIT(25)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_START_DET_INT_STS BIT(26)
#define THC_M_PRT_INT_STATUS_THC_I2C_IC_MST_ON_HOLD_INT_STS BIT(27)
#define THC_M_PRT_INT_STATUS_TXN_ERR_INT_STS BIT(28)
#define THC_M_PRT_INT_STATUS_FATAL_ERR_INT_STS BIT(30)
#define THC_M_PRT_ERR_CAUSE_INVLD_DEV_ENTRY BIT(9)
#define THC_M_PRT_ERR_CAUSE_FRAME_BABBLE_ERR BIT(10)
#define THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR BIT(12)
#define THC_M_PRT_ERR_CAUSE_PRD_ENTRY_ERR BIT(13)
#define THC_M_PRT_ERR_CAUSE_FATAL_ERR_CAUSE GENMASK(23, 16)
#define THC_M_PRT_SW_SEQ_CNTRL_TSSGO BIT(0)
#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CD_IE BIT(1)
#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CMD GENMASK(15, 8)
#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_BC GENMASK(31, 16)
#define THC_M_PRT_SW_SEQ_STS_TSSDONE BIT(0)
#define THC_M_PRT_SW_SEQ_STS_THC_SS_ERR BIT(1)
#define THC_M_PRT_SW_SEQ_STS_THC_SS_CIP BIT(3)
#define THC_M_PRT_SW_SEQ_DATA0_ADDR_THC_SW_SEQ_DATA0_ADDR GENMASK(31, 0)
#define THC_M_PRT_SW_SEQ_DATA1_THC_SW_SEQ_DATA1 GENMASK(31, 0)
#define THC_M_PRT_WPRD_BA_LOW_THC_M_PRT_WPRD_BA_LOW GENMASK(31, 12)
#define THC_M_PRT_WPRD_BA_HI_THC_M_PRT_WPRD_BA_HI GENMASK(31, 0)
#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_START BIT(0)
#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_ERROR BIT(1)
#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC BIT(2)
#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_DMACPL BIT(3)
#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_UHS BIT(23)
#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_PTEC GENMASK(31, 24)
#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_CMPL_STATUS BIT(0)
#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ERROR_STS BIT(1)
#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_IOC_STS BIT(2)
#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ACTIVE BIT(3)
#define THC_M_PRT_WR_BULK_ADDR_THC_M_PRT_WR_BULK_ADDR GENMASK(31, 0)
#define THC_M_PRT_DEV_INT_CAUSE_ADDR_THC_M_PRT_DEV_INT_CAUSE_ADDR GENMASK(31, 0)
#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_INTERRUPT_TYPE GENMASK(3, 0)
#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_MICRO_FRAME_SIZE GENMASK(23, 4)
#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_BEGINNING_OF_FRAME BIT(29)
#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_END_OF_FRAME BIT(30)
#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_FRAME_TYPE BIT(31)
#define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT GENMASK(30, 0)
#define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT_RST BIT(31)
#define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT GENMASK(30, 0)
#define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT_RST BIT(31)
#define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT GENMASK(30, 0)
#define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT_RST BIT(31)
#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_OFFSET GENMASK(4, 0)
#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_LEN GENMASK(9, 5)
#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_EOF_OFFSET GENMASK(14, 10)
#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_SEND_ICR_US_EN BIT(15)
#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_DATA_VAL GENMASK(31, 16)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_OFFSET GENMASK(4, 0)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_LEN GENMASK(9, 5)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_UNIT GENMASK(15, 12)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_IGNORE BIT(16)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_VAL BIT(17)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_ADDRINC_DIS BIT(24)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_ADDRINC_DIS BIT(25)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_PKT_STRM_EN BIT(26)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_PKT_STRM_EN BIT(27)
#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_DEVINT_POL BIT(28)
#define THC_M_PRT_RPRD_BA_LOW_1_THC_M_PRT_RPRD_BA_LOW GENMASK(31, 12)
#define THC_M_PRT_RPRD_BA_HI_1_THC_M_PRT_RPRD_BA_HI GENMASK(31, 0)
#define THC_M_PRT_RPRD_CNTRL_PCD GENMASK(6, 0)
#define THC_M_PRT_RPRD_CNTRL_PTEC GENMASK(15, 8)
#define THC_M_PRT_RPRD_CNTRL_PREFETCH_WM GENMASK(19, 16)
#define THC_M_PRT_READ_DMA_CNTRL_START BIT(0)
#define THC_M_PRT_READ_DMA_CNTRL_IE_ERROR BIT(1)
#define THC_M_PRT_READ_DMA_CNTRL_IE_IOC BIT(2)
#define THC_M_PRT_READ_DMA_CNTRL_IE_STALL BIT(3)
#define THC_M_PRT_READ_DMA_CNTRL_IE_NDDI BIT(4)
#define THC_M_PRT_READ_DMA_CNTRL_IE_EOF BIT(5)
#define THC_M_PRT_READ_DMA_CNTRL_IE_DMACPL BIT(7)
#define THC_M_PRT_READ_DMA_CNTRL_TPCRP GENMASK(15, 8)
#define THC_M_PRT_READ_DMA_CNTRL_TPCWP GENMASK(23, 16)
#define THC_M_PRT_READ_DMA_CNTRL_INT_SW_DMA_EN BIT(28)
#define THC_M_PRT_READ_DMA_CNTRL_SOO BIT(29)
#define THC_M_PRT_READ_DMA_CNTRL_UHS BIT(30)
#define THC_M_PRT_READ_DMA_CNTRL_TPCPR BIT(31)
#define THC_M_PRT_READ_DMA_INT_STS_DMACPL_STS BIT(0)
#define THC_M_PRT_READ_DMA_INT_STS_ERROR_STS BIT(1)
#define THC_M_PRT_READ_DMA_INT_STS_IOC_STS BIT(2)
#define THC_M_PRT_READ_DMA_INT_STS_STALL_STS BIT(3)
#define THC_M_PRT_READ_DMA_INT_STS_NONDMA_INT_STS BIT(4)
#define THC_M_PRT_READ_DMA_INT_STS_EOF_INT_STS BIT(5)
#define THC_M_PRT_READ_DMA_INT_STS_ACTIVE BIT(8)
#define THC_M_PRT_READ_DMA_ERR_1_DLERR BIT(0)
#define THC_M_PRT_GUC_OFFSET_LOW_1_THC_M_PRT_GUC_OFFSET_LOW GENMASK(31, 3)
#define THC_M_PRT_GUC_OFFSET_HI_1_THC_M_PRT_GUC_OFFSET_HI GENMASK(31, 0)
#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_1_WORKQ_ITEM_SZ GENMASK(23, 0)
#define THC_M_PRT_GUC_WORKQ_SZ_1_WORKQ_SZ GENMASK(23, 0)
#define THC_M_PRT_GUC_WORKQ_SZ_1_FCD GENMASK(27, 24)
#define THC_M_PRT_GUC_WORKQ_SZ_1_GIC GENMASK(31, 28)
#define THC_M_PRT_TSEQ_CNTRL_1_RGD BIT(2)
#define THC_M_PRT_TSEQ_CNTRL_1_EGP BIT(3)
#define THC_M_PRT_TSEQ_CNTRL_1_RTO BIT(4)
#define THC_M_PRT_TSEQ_CNTRL_1_EWOG BIT(5)
#define THC_M_PRT_TSEQ_CNTRL_1_RWOGC BIT(6)
#define THC_M_PRT_TSEQ_CNTRL_1_RX_DATA_FIFO_WR_WM GENMASK(25, 16)
#define THC_M_PRT_TSEQ_CNTRL_1_RESET_PREP_CHICKEN BIT(30)
#define THC_M_PRT_TSEQ_CNTRL_1_INT_EDG_DET_EN BIT(31)
#define THC_M_PRT_GUC_DB_ADDR_LOW_1_GUC_DB_ADDR_LOW GENMASK(31, 2)
#define THC_M_PRT_GUC_DB_ADDR_HI_1_GUC_DB_ADDR_HI GENMASK(31, 0)
#define THC_M_PRT_GUC_DB_DATA_1_GUC_DB_DATA GENMASK(31, 0)
#define THC_M_PRT_GUC_OFFSET_INITVAL_1_THC_M_PRT_GUC_OFFSET_INITVAL GENMASK(31, 0)
#define THC_M_PRT_RD_BULK_ADDR_1_THC_M_PRT_RD_BULK_ADDR GENMASK(31, 0)
#define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT GENMASK(30, 0)
#define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT_RST BIT(31)
#define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT GENMASK(30, 0)
#define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT_RST BIT(31)
#define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT GENMASK(30, 0)
#define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT_RST BIT(31)
#define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT GENMASK(30, 0)
#define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT_RST BIT(31)
#define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT GENMASK(30, 0)
#define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT_RST BIT(31)
#define THC_M_PRT_FRAME_DROP_CNT_1_NOFD GENMASK(30, 0)
#define THC_M_PRT_FRAME_DROP_CNT_1_RFDC BIT(31)
#define THC_M_PRT_COALESCE_1_COALESCE_TIMEOUT GENMASK(6, 0)
#define THC_M_PRT_RPRD_BA_LOW_2_THC_M_PRT_RPRD_BA_LOW GENMASK(31, 12)
#define THC_M_PRT_RPRD_BA_HI_2_THC_M_PRT_RPRD_BA_HI GENMASK(31, 0)
#define THC_M_PRT_READ_DMA_ERR_2_DLERR BIT(0)
#define THC_M_PRT_GUC_OFFSET_LOW_2_THC_M_PRT_GUC_OFFSET_LOW GENMASK(31, 3)
#define THC_M_PRT_GUC_OFFSET_HI_2_THC_M_PRT_GUC_OFFSET_HI GENMASK(31, 0)
#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_2_WORKQ_ITEM_SZ GENMASK(23, 0)
#define THC_M_PRT_GUC_WORKQ_SZ_2_WORKQ_SZ GENMASK(23, 0)
#define THC_M_PRT_GUC_WORKQ_SZ_2_FCD GENMASK(27, 24)
#define THC_M_PRT_GUC_WORKQ_SZ_2_GIC GENMASK(31, 28)
#define THC_M_PRT_TSEQ_CNTRL_2_RGD BIT(2)
#define THC_M_PRT_TSEQ_CNTRL_2_EGP BIT(3)
#define THC_M_PRT_TSEQ_CNTRL_2_RTO BIT(4)
#define THC_M_PRT_GUC_DB_ADDR_LOW_2_GUC_DB_ADDR_LOW GENMASK(31, 2)
#define THC_M_PRT_GUC_DB_ADDR_HI_2_GUC_DB_ADDR_HI GENMASK(31, 0)
#define THC_M_PRT_GUC_DB_DATA_2_GUC_DB_DATA GENMASK(31, 0)
#define THC_M_PRT_GUC_OFFSET_INITVAL_2_THC_M_PRT_GUC_OFFSET_INITVAL GENMASK(31, 0)
#define THC_M_PRT_RD_BULK_ADDR_2_THC_M_PRT_RD_BULK_ADDR GENMASK(31, 0)
#define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT GENMASK(30, 0)
#define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT_RST BIT(31)
#define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT GENMASK(30, 0)
#define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT_RST BIT(31)
#define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT GENMASK(30, 0)
#define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT_RST BIT(31)
#define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT GENMASK(30, 0)
#define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT_RST BIT(31)
#define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT GENMASK(30, 0)
#define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT_RST BIT(31)
#define THC_M_PRT_FRAME_DROP_CNT_2_NOFD GENMASK(30, 0)
#define THC_M_PRT_FRAME_DROP_CNT_2_RFDC BIT(31)
#define THC_M_PRT_COALESCE_2_COALESCE_TIMEOUT GENMASK(6, 0)
#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_I2C_RW_PIO_EN BIT(23)
#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_PIO_I2C_WBC GENMASK(31, 26)
#define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_RX_DLEN_EN BIT(23)
#define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_WBC GENMASK(31, 26)
#define THC_M_PRT_PRD_EMPTY_CNT_1_RPTEC BIT(31)
#define THC_M_PRT_PRD_EMPTY_CNT_2_RPTEC BIT(31)
#define THC_M_PRT_SW_DMA_PRD_TABLE_LEN_THC_M_PRT_SW_DMA_PRD_TABLE_LEN GENMASK(23, 0)
#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_VAL GENMASK(3, 0)
#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN BIT(25)
#define THC_M_PRT_SPI_DUTYC_CFG_SPI_TCRF_HALF_DIV_EN BIT(30)
#define THC_M_PRT_SPI_DUTYC_CFG_SPI_TCWF_HALF_DIV_EN BIT(31)
#define THC_M_PRT_SPARE_REG_SPI_CLK_INV_ENABLE BIT(2)
/* CS Assertion delay default value */
#define THC_CSA_CK_DELAY_VAL_DEFAULT 4
/* ARB policy definition */
/* Arbiter switches on packet boundary */
#define THC_ARB_POLICY_PACKET_BOUNDARY 0
/* Arbiter switches on Micro Frame boundary */
#define THC_ARB_POLICY_UFRAME_BOUNDARY 1
/* Arbiter switches on Frame boundary */
#define THC_ARB_POLICY_FRAME_BOUNDARY 2
#define THC_REGMAP_POLLING_INTERVAL_US 10 /* 10us */
#define THC_PIO_DONE_TIMEOUT_US USEC_PER_SEC /* 1s */
/* Default configures for HIDSPI */
#define THC_BIT_OFFSET_INTERRUPT_TYPE 4
/* input_report_type is 4 bits for HIDSPI */
#define THC_BIT_LENGTH_INTERRUPT_TYPE 4
/* Last fragment indicator is bit 15 for HIDSPI */
#define THC_BIT_OFFSET_LAST_FRAGMENT_FLAG 22
#define THC_BIT_OFFSET_MICROFRAME_SIZE 8
/* input_report_length is 14 bits for HIDSPI */
#define THC_BIT_LENGTH_MICROFRAME_SIZE 14
/* MFS unit in power of 2 */
#define THC_UNIT_MICROFRAME_SIZE 2
#define THC_BITMASK_INTERRUPT_TYPE_DATA 1
#define THC_BITMASK_INVALID_TYPE_DATA 2
/* Interrupt Quiesce default timeout value */
#define THC_QUIESCE_EN_TIMEOUT_US USEC_PER_SEC /* 1s */
/* LTR definition */
/*
* THC uses scale to calculate final LTR value.
* Scale is geometric progression of 2^5 step, starting from 2^0.
* For example, THC_LTR_SCALE_2(2) means 2^(5 * 2) = 1024, unit is ns.
*/
#define THC_LTR_SCALE_0 0
#define THC_LTR_SCALE_1 1
#define THC_LTR_SCALE_2 2
#define THC_LTR_SCALE_3 3
#define THC_LTR_SCALE_4 4
#define THC_LTR_SCALE_5 5
#define THC_LTR_MODE_ACTIVE 0
#define THC_LTR_MODE_LP 1
#define THC_LTR_MIN_VAL_SCALE_3 BIT(10)
#define THC_LTR_MAX_VAL_SCALE_3 BIT(15)
#define THC_LTR_MIN_VAL_SCALE_4 BIT(15)
#define THC_LTR_MAX_VAL_SCALE_4 BIT(20)
#define THC_LTR_MIN_VAL_SCALE_5 BIT(20)
#define THC_LTR_MAX_VAL_SCALE_5 BIT(25)
/*
* THC PIO opcode default value
* @THC_PIO_OP_SPI_TIC_READ: THC opcode for SPI PIO read
* @THC_PIO_OP_SPI_TIC_WRITE: THC opcode for SPI PIO write
* @THC_PIO_OP_I2C_SUBSYSTEM_READ: THC opcode for read I2C subsystem registers
* @THC_PIO_OP_I2C_SUBSYSTEM_WRITE: THC opcode for write I2C subsystem registers
* @THC_PIO_OP_I2C_TIC_READ: THC opcode for read I2C device
* @THC_PIO_OP_I2C_TIC_WRITE: THC opcode for write I2C device
* @THC_PIO_OP_I2C_TIC_WRITE_AND_READ: THC opcode for write followed by read I2C device
*/
enum thc_pio_opcode {
THC_PIO_OP_SPI_TIC_READ = 0x4,
THC_PIO_OP_SPI_TIC_WRITE = 0x6,
THC_PIO_OP_I2C_SUBSYSTEM_READ = 0x12,
THC_PIO_OP_I2C_SUBSYSTEM_WRITE = 0x13,
THC_PIO_OP_I2C_TIC_READ = 0x14,
THC_PIO_OP_I2C_TIC_WRITE = 0x18,
THC_PIO_OP_I2C_TIC_WRITE_AND_READ = 0x1C,
};
/**
* THC SPI IO mode
* @THC_SINGLE_IO: single IO mode, 1(opcode) - 1(address) - 1(data)
* @THC_DUAL_IO: dual IO mode, 1(opcode) - 2(address) - 2(data)
* @THC_QUAD_IO: quad IO mode, 1(opcode) - 4(address) - 4(data)
* @THC_QUAD_PARALLEL_IO: parallel quad IO mode, 4(opcode) - 4(address) - 4(data)
*/
enum thc_spi_iomode {
THC_SINGLE_IO = 0,
THC_DUAL_IO = 1,
THC_QUAD_IO = 2,
THC_QUAD_PARALLEL_IO = 3,
};
/**
* THC SPI frequency divider
*
* This DIV final value is determined by THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN bit.
* If THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN isn't be set, THC takes the DIV value directly;
* If THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN is set, THC takes the DIV value multiply by 8.
*
* For example, if THC input clock is 125MHz:
* When THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN isn't set, THC_SPI_FRQ_DIV_3 means DIV is 3,
* THC final clock is 125 / 3 = 41.667MHz;
* When THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN is set, THC_SPI_FRQ_DIV_3 means DIV is 3 * 8,
* THC final clock is 125 / (3 * 8) = 5.208MHz;
*/
enum thc_spi_frq_div {
THC_SPI_FRQ_RESERVED = 0,
THC_SPI_FRQ_DIV_1 = 1,
THC_SPI_FRQ_DIV_2 = 2,
THC_SPI_FRQ_DIV_3 = 3,
THC_SPI_FRQ_DIV_4 = 4,
THC_SPI_FRQ_DIV_5 = 5,
THC_SPI_FRQ_DIV_6 = 6,
THC_SPI_FRQ_DIV_7 = 7,
};
/* THC I2C sub-system registers */
#define THC_I2C_IC_CON_OFFSET 0x0
#define THC_I2C_IC_TAR_OFFSET 0x4
#define THC_I2C_IC_SAR_OFFSET 0x8
#define THC_I2C_IC_HS_MADDR_OFFSET 0xC
#define THC_I2C_IC_DATA_CMD_OFFSET 0x10
#define THC_I2C_IC_SS_SCL_HCNT_OFFSET 0x14
#define THC_I2C_IC_UFM_SCL_HCNT_OFFSET 0x14
#define THC_I2C_IC_SS_SCL_LCNT_OFFSET 0x18
#define THC_I2C_IC_UFM_SCL_LCNT_OFFSET 0x18
#define THC_I2C_IC_FS_SCL_HCNT_OFFSET 0x1C
#define THC_I2C_IC_UFM_TBUF_CNT_OFFSET 0x1C
#define THC_I2C_IC_FS_SCL_LCNT_OFFSET 0x20
#define THC_I2C_IC_HS_SCL_HCNT_OFFSET 0x24
#define THC_I2C_IC_HS_SCL_LCNT_OFFSET 0x28
#define THC_I2C_IC_INTR_STAT_OFFSET 0x2C
#define THC_I2C_IC_INTR_MASK_OFFSET 0x30
#define THC_I2C_IC_RAW_INTR_STAT_OFFSET 0x34
#define THC_I2C_IC_RX_TL_OFFSET 0x38
#define THC_I2C_IC_TX_TL_OFFSET 0x3C
#define THC_I2C_IC_CLR_INTR_OFFSET 0x40
#define THC_I2C_IC_CLR_RX_UNDER_OFFSET 0x44
#define THC_I2C_IC_CLR_RX_OVER_OFFSET 0x48
#define THC_I2C_IC_CLR_TX_OVER_OFFSET 0x4C
#define THC_I2C_IC_CLR_RD_REQ_OFFSET 0x50
#define THC_I2C_IC_CLR_TX_ABRT_OFFSET 0x54
#define THC_I2C_IC_CLR_RX_DONE_OFFSET 0x58
#define THC_I2C_IC_CLR_ACTIVITY_OFFSET 0x5C
#define THC_I2C_IC_CLR_STOP_DET_OFFSET 0x60
#define THC_I2C_IC_CLR_START_DET_OFFSET 0x64
#define THC_I2C_IC_CLR_GEN_CALL_OFFSET 0x68
#define THC_I2C_IC_ENABLE_OFFSET 0x6C
#define THC_I2C_IC_STATUS_OFFSET 0x70
#define THC_I2C_IC_TXFLR_OFFSET 0x74
#define THC_I2C_IC_RXFLR_OFFSET 0x78
#define THC_I2C_IC_SDA_HOLD_OFFSET 0x7C
#define THC_I2C_IC_TX_ABRT_SOURCE_OFFSET 0x80
#define THC_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x84
#define THC_I2C_IC_DMA_CR_OFFSET 0x88
#define THC_I2C_IC_DMA_TDLR_OFFSET 0x8C
#define THC_I2C_IC_DMA_RDLR_OFFSET 0x90
#define THC_I2C_IC_SDA_SETUP_OFFSET 0x94
#define THC_I2C_IC_ACK_GENERAL_CALL_OFFSET 0x98
#define THC_I2C_IC_ENABLE_STATUS_OFFSET 0x9C
#define THC_I2C_IC_FS_SPKLEN_OFFSET 0xA0
#define THC_I2C_IC_UFM_SPKLEN_OFFSET 0xA0
#define THC_I2C_IC_HS_SPKLEN_OFFSET 0xA4
#define THC_I2C_IC_CLR_RESTART_DET_OFFSET 0xA8
#define THC_I2C_IC_SCL_STUCK_AT_LOW_TIMEOUT_OFFSET 0xAC
#define THC_I2C_IC_SDA_STUCK_AT_LOW_TIMEOUT_OFFSET 0xB0
#define THC_I2C_IC_CLR_SCL_STUCK_DET_OFFSET 0xB4
#define THC_I2C_IC_DEVICE_ID_OFFSET 0xB8
#define THC_I2C_IC_SMBUS_CLK_LOW_SEXT_OFFSET 0xBC
#define THC_I2C_IC_SMBUS_CLK_LOW_MEXT_OFFSET 0xC0
#define THC_I2C_IC_SMBUS_THIGH_MAX_IDLE_COUNT_OFFSET 0xC4
#define THC_I2C_IC_SMBUS_INTR_STAT_OFFSET 0xC8
#define THC_I2C_IC_SMBUS_INTR_MASK_OFFSET 0xCC
#define THC_I2C_IC_SMBUS_RAW_INTR_STAT_OFFSET 0xD0
#define THC_I2C_IC_CLR_SMBUS_INTR_OFFSET 0xD4
#define THC_I2C_IC_OPTIONAL_SAR_OFFSET 0xD8
#define THC_I2C_IC_SMBUS_UDID_LSB_OFFSET 0xDC
#define THC_I2C_IC_SMBUS_UDID_WORD0_OFFSET 0xDC
#define THC_I2C_IC_SMBUS_UDID_WORD1_OFFSET 0xE0
#define THC_I2C_IC_SMBUS_UDID_WORD2_OFFSET 0xE4
#define THC_I2C_IC_SMBUS_UDID_WORD3_OFFSET 0xE8
#define THC_I2C_IC_COMP_PARAM_1_OFFSET 0xF4
#define THC_I2C_IC_COMP_VERSION_OFFSET 0xF8
#define THC_I2C_IC_COMP_TYPE_OFFSET 0xFC
/**
* THC I2C sub-system supported speed mode
*/
enum THC_I2C_SPEED_MODE {
THC_I2C_STANDARD = 1,
THC_I2C_FAST_AND_PLUS = 2,
THC_I2C_HIGH_SPEED = 3,
};
/* THC I2C sub-system register bits definition */
#define THC_I2C_IC_ENABLE_ENABLE BIT(0)
#define THC_I2C_IC_ENABLE_ABORT BIT(1)
#define THC_I2C_IC_ENABLE_TX_CMD_BLOCK BIT(2)
#define THC_I2C_IC_ENABLE_SDA_STUCK_RECOVERY_ENABLE BIT(3)
#define THC_I2C_IC_ENABLE_SMBUS_CLK_RESET BIT(16)
#define THC_I2C_IC_ENABLE_SMBUS_SUSPEND_EN BIT(17)
#define THC_I2C_IC_ENABLE_SMBUS_ALERT_EN BIT(18)
#define THC_I2C_IC_CON_MASTER_MODE BIT(0)
#define THC_I2C_IC_CON_SPEED GENMASK(2, 1)
#define THC_I2C_IC_CON_IC_10BITADDR_SLAVE BIT(3)
#define THC_I2C_IC_CON_IC_10BITADDR_MASTER BIT(4)
#define THC_I2C_IC_CON_IC_RESTART_EN BIT(5)
#define THC_I2C_IC_CON_IC_SLAVE_DISABLE BIT(6)
#define THC_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
#define THC_I2C_IC_CON_TX_EMPTY_CTRL BIT(8)
#define THC_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
#define THC_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE BIT(10)
#define THC_I2C_IC_CON_BUS_CLEAR_FEATURE_CTRL BIT(11)
#define THC_I2C_IC_CON_OPTIONAL_SAR_CTRL BIT(16)
#define THC_I2C_IC_CON_SMBUS_SLAVE_QUICK_EN BIT(17)
#define THC_I2C_IC_CON_SMBUS_ARP_EN BIT(18)
#define THC_I2C_IC_CON_SMBUS_PERSISTENT_SLV_ADDR_EN BIT(19)
#define THC_I2C_IC_TAR_IC_TAR GENMASK(9, 0)
#define THC_I2C_IC_TAR_GC_OR_START BIT(10)
#define THC_I2C_IC_TAR_SPECIAL BIT(11)
#define THC_I2C_IC_TAR_IC_10BITADDR_MASTER BIT(12)
#define THC_I2C_IC_TAR_DEVICE_ID BIT(13)
#define THC_I2C_IC_TAR_SMBUS_QUICK_CMD BIT(16)
#define THC_I2C_IC_INTR_MASK_M_RX_UNDER BIT(0)
#define THC_I2C_IC_INTR_MASK_M_RX_OVER BIT(1)
#define THC_I2C_IC_INTR_MASK_M_RX_FULL BIT(2)
#define THC_I2C_IC_INTR_MASK_M_TX_OVER BIT(3)
#define THC_I2C_IC_INTR_MASK_M_TX_EMPTY BIT(4)
#define THC_I2C_IC_INTR_MASK_M_RD_REQ BIT(5)
#define THC_I2C_IC_INTR_MASK_M_TX_ABRT BIT(6)
#define THC_I2C_IC_INTR_MASK_M_RX_DONE BIT(7)
#define THC_I2C_IC_INTR_MASK_M_ACTIVITY BIT(8)
#define THC_I2C_IC_INTR_MASK_M_STOP_DET BIT(9)
#define THC_I2C_IC_INTR_MASK_M_START_DET BIT(10)
#define THC_I2C_IC_INTR_MASK_M_GEN_CALL BIT(11)
#define THC_I2C_IC_INTR_MASK_M_RESTART_DET BIT(12)
#define THC_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD BIT(13)
#define THC_I2C_IC_INTR_MASK_M_SCL_STUCK_AT_LOW BIT(14)
#define THC_I2C_IC_DMA_CR_RDMAE BIT(0)
#define THC_I2C_IC_DMA_CR_TDMAE BIT(1)
#endif /* _INTEL_THC_HW_H_ */
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-wot.c
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2025 Intel Corporation */
#include <linux/acpi.h>
#include <linux/pm_wakeirq.h>
#include "intel-thc-dev.h"
#include "intel-thc-wot.h"
/**
* thc_wot_config - Query and configure wake-on-touch feature
* @thc_dev: Point to thc_device structure
* @gpio_map: Point to ACPI GPIO resource mapping structure
*
* THC ACPI device only provides _CRS with GpioInt() resources, doesn't contain
* _DSD to map this GPIO resource, so this function first registers wake GPIO
* mapping manually, then queries wake-on-touch GPIO resource from ACPI,
* if it exists and is wake-able, configure driver to enable it, otherwise,
* return immediately.
* This function will not return error as it doesn't impact major function.
*/
void thc_wot_config(struct thc_device *thc_dev, const struct acpi_gpio_mapping *gpio_map)
{
struct acpi_device *adev;
struct thc_wot *wot;
int ret;
if (!thc_dev)
return;
adev = ACPI_COMPANION(thc_dev->dev);
if (!adev)
return;
wot = &thc_dev->wot;
ret = acpi_dev_add_driver_gpios(adev, gpio_map);
if (ret) {
dev_warn(thc_dev->dev, "Can't add wake GPIO resource, ret = %d\n", ret);
return;
}
wot->gpio_irq = acpi_dev_gpio_irq_wake_get_by(adev, "wake-on-touch", 0,
&wot->gpio_irq_wakeable);
if (wot->gpio_irq <= 0) {
dev_warn(thc_dev->dev, "Can't find wake GPIO resource\n");
return;
}
if (!wot->gpio_irq_wakeable) {
dev_warn(thc_dev->dev, "GPIO resource isn't wakeable\n");
return;
}
ret = device_init_wakeup(thc_dev->dev, true);
if (ret) {
dev_warn(thc_dev->dev, "Failed to init wake up.\n");
return;
}
ret = dev_pm_set_dedicated_wake_irq(thc_dev->dev, wot->gpio_irq);
if (ret) {
dev_warn(thc_dev->dev, "Failed to set wake up IRQ.\n");
device_init_wakeup(thc_dev->dev, false);
}
}
EXPORT_SYMBOL_NS_GPL(thc_wot_config, "INTEL_THC");
/**
* thc_wot_unconfig - Unconfig wake-on-touch feature
* @thc_dev: Point to thc_device structure
*
* Configure driver to disable wake-on-touch and release ACPI resource.
*/
void thc_wot_unconfig(struct thc_device *thc_dev)
{
struct acpi_device *adev;
if (!thc_dev)
return;
adev = ACPI_COMPANION(thc_dev->dev);
if (!adev)
return;
if (thc_dev->wot.gpio_irq_wakeable)
device_init_wakeup(thc_dev->dev, false);
if (thc_dev->wot.gpio_irq > 0) {
dev_pm_clear_wake_irq(thc_dev->dev);
acpi_dev_remove_driver_gpios(adev);
}
}
EXPORT_SYMBOL_NS_GPL(thc_wot_unconfig, "INTEL_THC");
linux-7.2.3/drivers/hid/intel-thc-hid/intel-thc/intel-thc-wot.h
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2025 Intel Corporation */
#ifndef _INTEL_THC_WOT_H_
#define _INTEL_THC_WOT_H_
#include <linux/types.h>
#include <linux/gpio/consumer.h>
/**
* struct thc_wot - THC Wake-on-Touch data structure
* @gpio_irq : GPIO interrupt IRQ number for wake-on-touch
* @gpio_irq_wakeable : Indicate GPIO IRQ workable or not
*/
struct thc_wot {
int gpio_irq;
bool gpio_irq_wakeable;
};
struct thc_device;
void thc_wot_config(struct thc_device *thc_dev, const struct acpi_gpio_mapping *gpio_map);
void thc_wot_unconfig(struct thc_device *thc_dev);
#endif /* _INTEL_THC_WOT_H_ */