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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/iio/health/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
#
# Health sensors
#
# When adding new entries keep the list in alphabetical order
menu "Health Sensors"
menu "Heart Rate Monitors"
config AFE4403
tristate "TI AFE4403 Heart Rate Monitor"
depends on SPI_MASTER
select REGMAP_SPI
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes to choose the Texas Instruments AFE4403
heart rate monitor and low-cost pulse oximeter.
To compile this driver as a module, choose M here: the
module will be called afe4403.
config AFE4404
tristate "TI AFE4404 heart rate and pulse oximeter sensor"
depends on I2C
select REGMAP_I2C
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes to choose the Texas Instruments AFE4404
heart rate monitor and low-cost pulse oximeter.
To compile this driver as a module, choose M here: the
module will be called afe4404.
config MAX30100
tristate "MAX30100 heart rate and pulse oximeter sensor"
depends on I2C
select REGMAP_I2C
select IIO_BUFFER
select IIO_KFIFO_BUF
help
Say Y here to build I2C interface support for the Maxim
MAX30100 heart rate, and pulse oximeter sensor.
To compile this driver as a module, choose M here: the
module will be called max30100.
config MAX30102
tristate "MAX30102 heart rate and pulse oximeter sensor"
depends on I2C
select REGMAP_I2C
select IIO_BUFFER
select IIO_KFIFO_BUF
help
Say Y here to build I2C interface support for the Maxim
MAX30102 heart rate, and pulse oximeter sensor.
To compile this driver as a module, choose M here: the
module will be called max30102.
endmenu
endmenu
linux-7.2.3/drivers/iio/health/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for IIO Health sensors
#
# When adding new entries keep the list in alphabetical order
obj-$(CONFIG_AFE4403) += afe4403.o
obj-$(CONFIG_AFE4404) += afe4404.o
obj-$(CONFIG_MAX30100) += max30100.o
obj-$(CONFIG_MAX30102) += max30102.o
linux-7.2.3/drivers/iio/health/afe4403.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters
*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/unaligned.h>
#include "afe440x.h"
#define AFE4403_DRIVER_NAME "afe4403"
/* AFE4403 Registers */
#define AFE4403_TIAGAIN 0x20
#define AFE4403_TIA_AMB_GAIN 0x21
enum afe4403_fields {
/* Gains */
F_RF_LED1, F_CF_LED1,
F_RF_LED, F_CF_LED,
/* LED Current */
F_ILED1, F_ILED2,
/* sentinel */
F_MAX_FIELDS
};
static const struct reg_field afe4403_reg_fields[] = {
/* Gains */
[F_RF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 0, 2),
[F_CF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 3, 7),
[F_RF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
[F_CF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
/* LED Current */
[F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
[F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
};
/**
* struct afe4403_data - AFE4403 device instance data
* @spi: SPI device handle
* @regmap: Register map of the device
* @fields: Register fields of the device
* @regulator: Pointer to the regulator for the IC
* @trig: IIO trigger for this device
* @irq: ADC_RDY line interrupt number
* @buffer: Used to construct data layout to push into IIO buffer.
*/
struct afe4403_data {
struct spi_device *spi;
struct regmap *regmap;
struct regmap_field *fields[F_MAX_FIELDS];
struct regulator *regulator;
struct iio_trigger *trig;
int irq;
/* Ensure suitable alignment for timestamp */
s32 buffer[8] __aligned(8);
};
enum afe4403_chan_id {
LED2 = 1,
ALED2,
LED1,
ALED1,
LED2_ALED2,
LED1_ALED1,
};
static const unsigned int afe4403_channel_values[] = {
[LED2] = AFE440X_LED2VAL,
[ALED2] = AFE440X_ALED2VAL,
[LED1] = AFE440X_LED1VAL,
[ALED1] = AFE440X_ALED1VAL,
[LED2_ALED2] = AFE440X_LED2_ALED2VAL,
[LED1_ALED1] = AFE440X_LED1_ALED1VAL,
};
static const unsigned int afe4403_channel_leds[] = {
[LED2] = F_ILED2,
[LED1] = F_ILED1,
};
static const struct iio_chan_spec afe4403_channels[] = {
/* ADC values */
AFE440X_INTENSITY_CHAN(LED2, 0),
AFE440X_INTENSITY_CHAN(ALED2, 0),
AFE440X_INTENSITY_CHAN(LED1, 0),
AFE440X_INTENSITY_CHAN(ALED1, 0),
AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
/* LED current */
AFE440X_CURRENT_CHAN(LED2),
AFE440X_CURRENT_CHAN(LED1),
};
static const struct afe440x_val_table afe4403_res_table[] = {
{ 500000 }, { 250000 }, { 100000 }, { 50000 },
{ 25000 }, { 10000 }, { 1000000 }, { 0 },
};
AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
static const struct afe440x_val_table afe4403_cap_table[] = {
{ 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
{ 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
{ 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
{ 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
{ 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
{ 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
{ 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
{ 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
};
AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
static ssize_t afe440x_show_register(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4403_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
unsigned int reg_val;
int vals[2];
int ret;
ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
if (ret)
return ret;
if (reg_val >= afe440x_attr->table_size)
return -EINVAL;
vals[0] = afe440x_attr->val_table[reg_val].integer;
vals[1] = afe440x_attr->val_table[reg_val].fract;
return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
}
static ssize_t afe440x_store_register(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4403_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
int val, integer, fract, ret;
ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
if (ret)
return ret;
for (val = 0; val < afe440x_attr->table_size; val++)
if (afe440x_attr->val_table[val].integer == integer &&
afe440x_attr->val_table[val].fract == fract)
break;
if (val == afe440x_attr->table_size)
return -EINVAL;
ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
if (ret)
return ret;
return count;
}
static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
static struct attribute *afe440x_attributes[] = {
&dev_attr_in_intensity_resistance_available.attr,
&dev_attr_in_intensity_capacitance_available.attr,
&afe440x_attr_in_intensity1_resistance.dev_attr.attr,
&afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
&afe440x_attr_in_intensity2_resistance.dev_attr.attr,
&afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
&afe440x_attr_in_intensity3_resistance.dev_attr.attr,
&afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
&afe440x_attr_in_intensity4_resistance.dev_attr.attr,
&afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
NULL
};
static const struct attribute_group afe440x_attribute_group = {
.attrs = afe440x_attributes
};
static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
{
u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
u8 rx[3];
int ret;
/* Enable reading from the device */
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
return ret;
ret = spi_write_then_read(afe->spi, &reg, 1, rx, sizeof(rx));
if (ret)
return ret;
*val = get_unaligned_be24(&rx[0]);
/* Disable reading from the device */
tx[3] = AFE440X_CONTROL0_WRITE;
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
return ret;
return 0;
}
static int afe4403_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct afe4403_data *afe = iio_priv(indio_dev);
unsigned int reg, field;
int ret;
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_RAW:
reg = afe4403_channel_values[chan->address];
ret = afe4403_read(afe, reg, val);
if (ret)
return ret;
return IIO_VAL_INT;
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
field = afe4403_channel_leds[chan->address];
ret = regmap_field_read(afe->fields[field], val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 800000;
return IIO_VAL_INT_PLUS_MICRO;
}
break;
default:
break;
}
return -EINVAL;
}
static int afe4403_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct afe4403_data *afe = iio_priv(indio_dev);
unsigned int field = afe4403_channel_leds[chan->address];
switch (chan->type) {
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
return regmap_field_write(afe->fields[field], val);
}
break;
default:
break;
}
return -EINVAL;
}
static const struct iio_info afe4403_iio_info = {
.attrs = &afe440x_attribute_group,
.read_raw = afe4403_read_raw,
.write_raw = afe4403_write_raw,
};
static irqreturn_t afe4403_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct afe4403_data *afe = iio_priv(indio_dev);
int ret, bit, i = 0;
u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
u8 rx[3];
/* Enable reading from the device */
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
goto err;
iio_for_each_active_channel(indio_dev, bit) {
ret = spi_write_then_read(afe->spi,
&afe4403_channel_values[bit], 1,
rx, sizeof(rx));
if (ret)
goto err;
afe->buffer[i++] = get_unaligned_be24(&rx[0]);
}
/* Disable reading from the device */
tx[3] = AFE440X_CONTROL0_WRITE;
ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
if (ret)
goto err;
iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
pf->timestamp);
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static void afe4403_regulator_disable(void *data)
{
struct regulator *regulator = data;
regulator_disable(regulator);
}
#define AFE4403_TIMING_PAIRS \
{ AFE440X_LED2STC, 0x000050 }, \
{ AFE440X_LED2ENDC, 0x0003e7 }, \
{ AFE440X_LED1LEDSTC, 0x0007d0 }, \
{ AFE440X_LED1LEDENDC, 0x000bb7 }, \
{ AFE440X_ALED2STC, 0x000438 }, \
{ AFE440X_ALED2ENDC, 0x0007cf }, \
{ AFE440X_LED1STC, 0x000820 }, \
{ AFE440X_LED1ENDC, 0x000bb7 }, \
{ AFE440X_LED2LEDSTC, 0x000000 }, \
{ AFE440X_LED2LEDENDC, 0x0003e7 }, \
{ AFE440X_ALED1STC, 0x000c08 }, \
{ AFE440X_ALED1ENDC, 0x000f9f }, \
{ AFE440X_LED2CONVST, 0x0003ef }, \
{ AFE440X_LED2CONVEND, 0x0007cf }, \
{ AFE440X_ALED2CONVST, 0x0007d7 }, \
{ AFE440X_ALED2CONVEND, 0x000bb7 }, \
{ AFE440X_LED1CONVST, 0x000bbf }, \
{ AFE440X_LED1CONVEND, 0x009c3f }, \
{ AFE440X_ALED1CONVST, 0x000fa7 }, \
{ AFE440X_ALED1CONVEND, 0x001387 }, \
{ AFE440X_ADCRSTSTCT0, 0x0003e8 }, \
{ AFE440X_ADCRSTENDCT0, 0x0003eb }, \
{ AFE440X_ADCRSTSTCT1, 0x0007d0 }, \
{ AFE440X_ADCRSTENDCT1, 0x0007d3 }, \
{ AFE440X_ADCRSTSTCT2, 0x000bb8 }, \
{ AFE440X_ADCRSTENDCT2, 0x000bbb }, \
{ AFE440X_ADCRSTSTCT3, 0x000fa0 }, \
{ AFE440X_ADCRSTENDCT3, 0x000fa3 }, \
{ AFE440X_PRPCOUNT, 0x009c3f }, \
{ AFE440X_PDNCYCLESTC, 0x001518 }, \
{ AFE440X_PDNCYCLEENDC, 0x00991f }
static const struct reg_sequence afe4403_reg_sequences[] = {
AFE4403_TIMING_PAIRS,
{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
{ AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
};
static const struct regmap_range afe4403_yes_ranges[] = {
regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
};
static const struct regmap_access_table afe4403_volatile_table = {
.yes_ranges = afe4403_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
};
static const struct regmap_config afe4403_regmap_config = {
.reg_bits = 8,
.val_bits = 24,
.max_register = AFE440X_PDNCYCLEENDC,
.cache_type = REGCACHE_MAPLE,
.volatile_table = &afe4403_volatile_table,
};
static const struct of_device_id afe4403_of_match[] = {
{ .compatible = "ti,afe4403", },
{ }
};
MODULE_DEVICE_TABLE(of, afe4403_of_match);
static int afe4403_suspend(struct device *dev)
{
struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
struct afe4403_data *afe = iio_priv(indio_dev);
int ret;
ret = regmap_set_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE);
if (ret)
return ret;
ret = regulator_disable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to disable regulator\n");
return ret;
}
return 0;
}
static int afe4403_resume(struct device *dev)
{
struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
struct afe4403_data *afe = iio_priv(indio_dev);
int ret;
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_clear_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE);
if (ret)
return ret;
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend,
afe4403_resume);
static int afe4403_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct iio_dev *indio_dev;
struct afe4403_data *afe;
int i, ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*afe));
if (!indio_dev)
return -ENOMEM;
afe = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
afe->spi = spi;
afe->irq = spi->irq;
afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
if (IS_ERR(afe->regmap)) {
dev_err(dev, "Unable to allocate register map\n");
return PTR_ERR(afe->regmap);
}
for (i = 0; i < F_MAX_FIELDS; i++) {
afe->fields[i] = devm_regmap_field_alloc(dev, afe->regmap,
afe4403_reg_fields[i]);
if (IS_ERR(afe->fields[i])) {
dev_err(dev, "Unable to allocate regmap fields\n");
return PTR_ERR(afe->fields[i]);
}
}
afe->regulator = devm_regulator_get(dev, "tx_sup");
if (IS_ERR(afe->regulator))
return dev_err_probe(dev, PTR_ERR(afe->regulator),
"Unable to get regulator\n");
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = devm_add_action_or_reset(dev, afe4403_regulator_disable, afe->regulator);
if (ret) {
dev_err(dev, "Unable to add regulator disable action\n");
return ret;
}
ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
AFE440X_CONTROL0_SW_RESET);
if (ret) {
dev_err(dev, "Unable to reset device\n");
return ret;
}
ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
ARRAY_SIZE(afe4403_reg_sequences));
if (ret) {
dev_err(dev, "Unable to set register defaults\n");
return ret;
}
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = afe4403_channels;
indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
indio_dev->name = AFE4403_DRIVER_NAME;
indio_dev->info = &afe4403_iio_info;
if (afe->irq > 0) {
afe->trig = devm_iio_trigger_alloc(dev,
"%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!afe->trig)
return -ENOMEM;
iio_trigger_set_drvdata(afe->trig, indio_dev);
ret = devm_iio_trigger_register(dev, afe->trig);
if (ret) {
dev_err(dev, "Unable to register IIO trigger\n");
return ret;
}
ret = devm_request_irq(dev, afe->irq,
iio_trigger_generic_data_rdy_poll,
IRQF_NO_THREAD, AFE4403_DRIVER_NAME,
afe->trig);
if (ret) {
dev_err(dev, "Unable to request IRQ\n");
return ret;
}
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
&iio_pollfunc_store_time,
afe4403_trigger_handler, NULL);
if (ret) {
dev_err(dev, "Unable to setup buffer\n");
return ret;
}
ret = devm_iio_device_register(dev, indio_dev);
if (ret) {
dev_err(dev, "Unable to register IIO device\n");
return ret;
}
return 0;
}
static const struct spi_device_id afe4403_ids[] = {
{ "afe4403", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, afe4403_ids);
static struct spi_driver afe4403_spi_driver = {
.driver = {
.name = AFE4403_DRIVER_NAME,
.of_match_table = afe4403_of_match,
.pm = pm_sleep_ptr(&afe4403_pm_ops),
},
.probe = afe4403_probe,
.id_table = afe4403_ids,
};
module_spi_driver(afe4403_spi_driver);
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
MODULE_LICENSE("GPL v2");
linux-7.2.3/drivers/iio/health/afe4404.c
+596
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// SPDX-License-Identifier: GPL-2.0-only
/*
* AFE4404 Heart Rate Monitors and Low-Cost Pulse Oximeters
*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include "afe440x.h"
#define AFE4404_DRIVER_NAME "afe4404"
/* AFE4404 registers */
#define AFE4404_TIA_GAIN_SEP 0x20
#define AFE4404_TIA_GAIN 0x21
#define AFE4404_PROG_TG_STC 0x34
#define AFE4404_PROG_TG_ENDC 0x35
#define AFE4404_LED3LEDSTC 0x36
#define AFE4404_LED3LEDENDC 0x37
#define AFE4404_CLKDIV_PRF 0x39
#define AFE4404_OFFDAC 0x3a
#define AFE4404_DEC 0x3d
#define AFE4404_AVG_LED2_ALED2VAL 0x3f
#define AFE4404_AVG_LED1_ALED1VAL 0x40
/* AFE4404 CONTROL2 register fields */
#define AFE440X_CONTROL2_OSC_ENABLE BIT(9)
enum afe4404_fields {
/* Gains */
F_TIA_GAIN_SEP, F_TIA_CF_SEP,
F_TIA_GAIN, TIA_CF,
/* LED Current */
F_ILED1, F_ILED2, F_ILED3,
/* Offset DAC */
F_OFFDAC_AMB2, F_OFFDAC_LED1, F_OFFDAC_AMB1, F_OFFDAC_LED2,
/* sentinel */
F_MAX_FIELDS
};
static const struct reg_field afe4404_reg_fields[] = {
/* Gains */
[F_TIA_GAIN_SEP] = REG_FIELD(AFE4404_TIA_GAIN_SEP, 0, 2),
[F_TIA_CF_SEP] = REG_FIELD(AFE4404_TIA_GAIN_SEP, 3, 5),
[F_TIA_GAIN] = REG_FIELD(AFE4404_TIA_GAIN, 0, 2),
[TIA_CF] = REG_FIELD(AFE4404_TIA_GAIN, 3, 5),
/* LED Current */
[F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 5),
[F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 6, 11),
[F_ILED3] = REG_FIELD(AFE440X_LEDCNTRL, 12, 17),
/* Offset DAC */
[F_OFFDAC_AMB2] = REG_FIELD(AFE4404_OFFDAC, 0, 4),
[F_OFFDAC_LED1] = REG_FIELD(AFE4404_OFFDAC, 5, 9),
[F_OFFDAC_AMB1] = REG_FIELD(AFE4404_OFFDAC, 10, 14),
[F_OFFDAC_LED2] = REG_FIELD(AFE4404_OFFDAC, 15, 19),
};
/**
* struct afe4404_data - AFE4404 device instance data
* @regmap: Register map of the device
* @fields: Register fields of the device
* @regulator: Pointer to the regulator for the IC
* @trig: IIO trigger for this device
* @irq: ADC_RDY line interrupt number
* @buffer: Used to construct a scan to push to the iio buffer.
*/
struct afe4404_data {
struct regmap *regmap;
struct regmap_field *fields[F_MAX_FIELDS];
struct regulator *regulator;
struct iio_trigger *trig;
int irq;
s32 buffer[10] __aligned(8);
};
enum afe4404_chan_id {
LED2 = 1,
ALED2,
LED1,
ALED1,
LED2_ALED2,
LED1_ALED1,
};
static const unsigned int afe4404_channel_values[] = {
[LED2] = AFE440X_LED2VAL,
[ALED2] = AFE440X_ALED2VAL,
[LED1] = AFE440X_LED1VAL,
[ALED1] = AFE440X_ALED1VAL,
[LED2_ALED2] = AFE440X_LED2_ALED2VAL,
[LED1_ALED1] = AFE440X_LED1_ALED1VAL,
};
static const unsigned int afe4404_channel_leds[] = {
[LED2] = F_ILED2,
[ALED2] = F_ILED3,
[LED1] = F_ILED1,
};
static const unsigned int afe4404_channel_offdacs[] = {
[LED2] = F_OFFDAC_LED2,
[ALED2] = F_OFFDAC_AMB2,
[LED1] = F_OFFDAC_LED1,
[ALED1] = F_OFFDAC_AMB1,
};
static const struct iio_chan_spec afe4404_channels[] = {
/* ADC values */
AFE440X_INTENSITY_CHAN(LED2, BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(ALED2, BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(LED1, BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(ALED1, BIT(IIO_CHAN_INFO_OFFSET)),
AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
/* LED current */
AFE440X_CURRENT_CHAN(LED2),
AFE440X_CURRENT_CHAN(ALED2),
AFE440X_CURRENT_CHAN(LED1),
};
static const struct afe440x_val_table afe4404_res_table[] = {
{ .integer = 500000, .fract = 0 },
{ .integer = 250000, .fract = 0 },
{ .integer = 100000, .fract = 0 },
{ .integer = 50000, .fract = 0 },
{ .integer = 25000, .fract = 0 },
{ .integer = 10000, .fract = 0 },
{ .integer = 1000000, .fract = 0 },
{ .integer = 2000000, .fract = 0 },
};
AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4404_res_table);
static const struct afe440x_val_table afe4404_cap_table[] = {
{ .integer = 0, .fract = 5000 },
{ .integer = 0, .fract = 2500 },
{ .integer = 0, .fract = 10000 },
{ .integer = 0, .fract = 7500 },
{ .integer = 0, .fract = 20000 },
{ .integer = 0, .fract = 17500 },
{ .integer = 0, .fract = 25000 },
{ .integer = 0, .fract = 22500 },
};
AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4404_cap_table);
static ssize_t afe440x_show_register(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4404_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
unsigned int reg_val;
int vals[2];
int ret;
ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
if (ret)
return ret;
if (reg_val >= afe440x_attr->table_size)
return -EINVAL;
vals[0] = afe440x_attr->val_table[reg_val].integer;
vals[1] = afe440x_attr->val_table[reg_val].fract;
return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
}
static ssize_t afe440x_store_register(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct afe4404_data *afe = iio_priv(indio_dev);
struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
int val, integer, fract, ret;
ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
if (ret)
return ret;
for (val = 0; val < afe440x_attr->table_size; val++)
if (afe440x_attr->val_table[val].integer == integer &&
afe440x_attr->val_table[val].fract == fract)
break;
if (val == afe440x_attr->table_size)
return -EINVAL;
ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
if (ret)
return ret;
return count;
}
static AFE440X_ATTR(in_intensity1_resistance, F_TIA_GAIN_SEP, afe4404_res_table);
static AFE440X_ATTR(in_intensity1_capacitance, F_TIA_CF_SEP, afe4404_cap_table);
static AFE440X_ATTR(in_intensity2_resistance, F_TIA_GAIN_SEP, afe4404_res_table);
static AFE440X_ATTR(in_intensity2_capacitance, F_TIA_CF_SEP, afe4404_cap_table);
static AFE440X_ATTR(in_intensity3_resistance, F_TIA_GAIN, afe4404_res_table);
static AFE440X_ATTR(in_intensity3_capacitance, TIA_CF, afe4404_cap_table);
static AFE440X_ATTR(in_intensity4_resistance, F_TIA_GAIN, afe4404_res_table);
static AFE440X_ATTR(in_intensity4_capacitance, TIA_CF, afe4404_cap_table);
static struct attribute *afe440x_attributes[] = {
&dev_attr_in_intensity_resistance_available.attr,
&dev_attr_in_intensity_capacitance_available.attr,
&afe440x_attr_in_intensity1_resistance.dev_attr.attr,
&afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
&afe440x_attr_in_intensity2_resistance.dev_attr.attr,
&afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
&afe440x_attr_in_intensity3_resistance.dev_attr.attr,
&afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
&afe440x_attr_in_intensity4_resistance.dev_attr.attr,
&afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
NULL
};
static const struct attribute_group afe440x_attribute_group = {
.attrs = afe440x_attributes
};
static int afe4404_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct afe4404_data *afe = iio_priv(indio_dev);
unsigned int value_reg, led_field, offdac_field;
int ret;
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_RAW:
value_reg = afe4404_channel_values[chan->address];
ret = regmap_read(afe->regmap, value_reg, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
offdac_field = afe4404_channel_offdacs[chan->address];
ret = regmap_field_read(afe->fields[offdac_field], val);
if (ret)
return ret;
return IIO_VAL_INT;
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
led_field = afe4404_channel_leds[chan->address];
ret = regmap_field_read(afe->fields[led_field], val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 800000;
return IIO_VAL_INT_PLUS_MICRO;
}
break;
default:
break;
}
return -EINVAL;
}
static int afe4404_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct afe4404_data *afe = iio_priv(indio_dev);
unsigned int led_field, offdac_field;
switch (chan->type) {
case IIO_INTENSITY:
switch (mask) {
case IIO_CHAN_INFO_OFFSET:
offdac_field = afe4404_channel_offdacs[chan->address];
return regmap_field_write(afe->fields[offdac_field], val);
}
break;
case IIO_CURRENT:
switch (mask) {
case IIO_CHAN_INFO_RAW:
led_field = afe4404_channel_leds[chan->address];
return regmap_field_write(afe->fields[led_field], val);
}
break;
default:
break;
}
return -EINVAL;
}
static const struct iio_info afe4404_iio_info = {
.attrs = &afe440x_attribute_group,
.read_raw = afe4404_read_raw,
.write_raw = afe4404_write_raw,
};
static irqreturn_t afe4404_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct afe4404_data *afe = iio_priv(indio_dev);
int ret, bit, i = 0;
iio_for_each_active_channel(indio_dev, bit) {
ret = regmap_read(afe->regmap, afe4404_channel_values[bit],
&afe->buffer[i++]);
if (ret)
goto err;
}
iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
pf->timestamp);
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static void afe4404_regulator_disable(void *data)
{
struct regulator *regulator = data;
regulator_disable(regulator);
}
/* Default timings from data-sheet */
#define AFE4404_TIMING_PAIRS \
{ AFE440X_PRPCOUNT, 39999 }, \
{ AFE440X_LED2LEDSTC, 0 }, \
{ AFE440X_LED2LEDENDC, 398 }, \
{ AFE440X_LED2STC, 80 }, \
{ AFE440X_LED2ENDC, 398 }, \
{ AFE440X_ADCRSTSTCT0, 5600 }, \
{ AFE440X_ADCRSTENDCT0, 5606 }, \
{ AFE440X_LED2CONVST, 5607 }, \
{ AFE440X_LED2CONVEND, 6066 }, \
{ AFE4404_LED3LEDSTC, 400 }, \
{ AFE4404_LED3LEDENDC, 798 }, \
{ AFE440X_ALED2STC, 480 }, \
{ AFE440X_ALED2ENDC, 798 }, \
{ AFE440X_ADCRSTSTCT1, 6068 }, \
{ AFE440X_ADCRSTENDCT1, 6074 }, \
{ AFE440X_ALED2CONVST, 6075 }, \
{ AFE440X_ALED2CONVEND, 6534 }, \
{ AFE440X_LED1LEDSTC, 800 }, \
{ AFE440X_LED1LEDENDC, 1198 }, \
{ AFE440X_LED1STC, 880 }, \
{ AFE440X_LED1ENDC, 1198 }, \
{ AFE440X_ADCRSTSTCT2, 6536 }, \
{ AFE440X_ADCRSTENDCT2, 6542 }, \
{ AFE440X_LED1CONVST, 6543 }, \
{ AFE440X_LED1CONVEND, 7003 }, \
{ AFE440X_ALED1STC, 1280 }, \
{ AFE440X_ALED1ENDC, 1598 }, \
{ AFE440X_ADCRSTSTCT3, 7005 }, \
{ AFE440X_ADCRSTENDCT3, 7011 }, \
{ AFE440X_ALED1CONVST, 7012 }, \
{ AFE440X_ALED1CONVEND, 7471 }, \
{ AFE440X_PDNCYCLESTC, 7671 }, \
{ AFE440X_PDNCYCLEENDC, 39199 }
static const struct reg_sequence afe4404_reg_sequences[] = {
AFE4404_TIMING_PAIRS,
{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
{ AFE4404_TIA_GAIN_SEP, AFE440X_TIAGAIN_ENSEPGAIN },
{ AFE440X_CONTROL2, AFE440X_CONTROL2_OSC_ENABLE },
};
static const struct regmap_range afe4404_yes_ranges[] = {
regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
regmap_reg_range(AFE4404_AVG_LED2_ALED2VAL, AFE4404_AVG_LED1_ALED1VAL),
};
static const struct regmap_access_table afe4404_volatile_table = {
.yes_ranges = afe4404_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(afe4404_yes_ranges),
};
static const struct regmap_config afe4404_regmap_config = {
.reg_bits = 8,
.val_bits = 24,
.max_register = AFE4404_AVG_LED1_ALED1VAL,
.cache_type = REGCACHE_MAPLE,
.volatile_table = &afe4404_volatile_table,
};
static const struct of_device_id afe4404_of_match[] = {
{ .compatible = "ti,afe4404", },
{ }
};
MODULE_DEVICE_TABLE(of, afe4404_of_match);
static int afe4404_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct afe4404_data *afe = iio_priv(indio_dev);
int ret;
ret = regmap_set_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE);
if (ret)
return ret;
ret = regulator_disable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to disable regulator\n");
return ret;
}
return 0;
}
static int afe4404_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct afe4404_data *afe = iio_priv(indio_dev);
int ret;
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_clear_bits(afe->regmap, AFE440X_CONTROL2,
AFE440X_CONTROL2_PDN_AFE);
if (ret)
return ret;
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(afe4404_pm_ops, afe4404_suspend,
afe4404_resume);
static int afe4404_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct afe4404_data *afe;
int i, ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*afe));
if (!indio_dev)
return -ENOMEM;
afe = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
afe->irq = client->irq;
afe->regmap = devm_regmap_init_i2c(client, &afe4404_regmap_config);
if (IS_ERR(afe->regmap)) {
dev_err(dev, "Unable to allocate register map\n");
return PTR_ERR(afe->regmap);
}
for (i = 0; i < F_MAX_FIELDS; i++) {
afe->fields[i] = devm_regmap_field_alloc(dev, afe->regmap,
afe4404_reg_fields[i]);
if (IS_ERR(afe->fields[i])) {
dev_err(dev, "Unable to allocate regmap fields\n");
return PTR_ERR(afe->fields[i]);
}
}
afe->regulator = devm_regulator_get(dev, "tx_sup");
if (IS_ERR(afe->regulator))
return dev_err_probe(dev, PTR_ERR(afe->regulator),
"Unable to get regulator\n");
ret = regulator_enable(afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = devm_add_action_or_reset(dev, afe4404_regulator_disable, afe->regulator);
if (ret) {
dev_err(dev, "Unable to enable regulator\n");
return ret;
}
ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
AFE440X_CONTROL0_SW_RESET);
if (ret) {
dev_err(dev, "Unable to reset device\n");
return ret;
}
ret = regmap_multi_reg_write(afe->regmap, afe4404_reg_sequences,
ARRAY_SIZE(afe4404_reg_sequences));
if (ret) {
dev_err(dev, "Unable to set register defaults\n");
return ret;
}
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = afe4404_channels;
indio_dev->num_channels = ARRAY_SIZE(afe4404_channels);
indio_dev->name = AFE4404_DRIVER_NAME;
indio_dev->info = &afe4404_iio_info;
if (afe->irq > 0) {
afe->trig = devm_iio_trigger_alloc(dev,
"%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!afe->trig)
return -ENOMEM;
iio_trigger_set_drvdata(afe->trig, indio_dev);
ret = devm_iio_trigger_register(dev, afe->trig);
if (ret) {
dev_err(dev, "Unable to register IIO trigger\n");
return ret;
}
ret = devm_request_irq(dev, afe->irq,
iio_trigger_generic_data_rdy_poll,
IRQF_NO_THREAD, AFE4404_DRIVER_NAME,
afe->trig);
if (ret) {
dev_err(dev, "Unable to request IRQ\n");
return ret;
}
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
&iio_pollfunc_store_time,
afe4404_trigger_handler, NULL);
if (ret) {
dev_err(dev, "Unable to setup buffer\n");
return ret;
}
ret = devm_iio_device_register(dev, indio_dev);
if (ret) {
dev_err(dev, "Unable to register IIO device\n");
return ret;
}
return 0;
}
static const struct i2c_device_id afe4404_ids[] = {
{ .name = "afe4404" },
{ }
};
MODULE_DEVICE_TABLE(i2c, afe4404_ids);
static struct i2c_driver afe4404_i2c_driver = {
.driver = {
.name = AFE4404_DRIVER_NAME,
.of_match_table = afe4404_of_match,
.pm = pm_sleep_ptr(&afe4404_pm_ops),
},
.probe = afe4404_probe,
.id_table = afe4404_ids,
};
module_i2c_driver(afe4404_i2c_driver);
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
MODULE_DESCRIPTION("TI AFE4404 Heart Rate Monitor and Pulse Oximeter AFE");
MODULE_LICENSE("GPL v2");
linux-7.2.3/drivers/iio/health/afe440x.h
+155
View File
@@ -0,0 +1,155 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AFE440X Heart Rate Monitors and Low-Cost Pulse Oximeters
*
* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
#ifndef _AFE440X_H
#define _AFE440X_H
/* AFE440X registers */
#define AFE440X_CONTROL0 0x00
#define AFE440X_LED2STC 0x01
#define AFE440X_LED2ENDC 0x02
#define AFE440X_LED1LEDSTC 0x03
#define AFE440X_LED1LEDENDC 0x04
#define AFE440X_ALED2STC 0x05
#define AFE440X_ALED2ENDC 0x06
#define AFE440X_LED1STC 0x07
#define AFE440X_LED1ENDC 0x08
#define AFE440X_LED2LEDSTC 0x09
#define AFE440X_LED2LEDENDC 0x0a
#define AFE440X_ALED1STC 0x0b
#define AFE440X_ALED1ENDC 0x0c
#define AFE440X_LED2CONVST 0x0d
#define AFE440X_LED2CONVEND 0x0e
#define AFE440X_ALED2CONVST 0x0f
#define AFE440X_ALED2CONVEND 0x10
#define AFE440X_LED1CONVST 0x11
#define AFE440X_LED1CONVEND 0x12
#define AFE440X_ALED1CONVST 0x13
#define AFE440X_ALED1CONVEND 0x14
#define AFE440X_ADCRSTSTCT0 0x15
#define AFE440X_ADCRSTENDCT0 0x16
#define AFE440X_ADCRSTSTCT1 0x17
#define AFE440X_ADCRSTENDCT1 0x18
#define AFE440X_ADCRSTSTCT2 0x19
#define AFE440X_ADCRSTENDCT2 0x1a
#define AFE440X_ADCRSTSTCT3 0x1b
#define AFE440X_ADCRSTENDCT3 0x1c
#define AFE440X_PRPCOUNT 0x1d
#define AFE440X_CONTROL1 0x1e
#define AFE440X_LEDCNTRL 0x22
#define AFE440X_CONTROL2 0x23
#define AFE440X_ALARM 0x29
#define AFE440X_LED2VAL 0x2a
#define AFE440X_ALED2VAL 0x2b
#define AFE440X_LED1VAL 0x2c
#define AFE440X_ALED1VAL 0x2d
#define AFE440X_LED2_ALED2VAL 0x2e
#define AFE440X_LED1_ALED1VAL 0x2f
#define AFE440X_CONTROL3 0x31
#define AFE440X_PDNCYCLESTC 0x32
#define AFE440X_PDNCYCLEENDC 0x33
/* CONTROL0 register fields */
#define AFE440X_CONTROL0_REG_READ BIT(0)
#define AFE440X_CONTROL0_TM_COUNT_RST BIT(1)
#define AFE440X_CONTROL0_SW_RESET BIT(3)
/* CONTROL1 register fields */
#define AFE440X_CONTROL1_TIMEREN BIT(8)
/* TIAGAIN register fields */
#define AFE440X_TIAGAIN_ENSEPGAIN BIT(15)
/* CONTROL2 register fields */
#define AFE440X_CONTROL2_PDN_AFE BIT(0)
#define AFE440X_CONTROL2_PDN_RX BIT(1)
#define AFE440X_CONTROL2_DYNAMIC4 BIT(3)
#define AFE440X_CONTROL2_DYNAMIC3 BIT(4)
#define AFE440X_CONTROL2_DYNAMIC2 BIT(14)
#define AFE440X_CONTROL2_DYNAMIC1 BIT(20)
/* CONTROL3 register fields */
#define AFE440X_CONTROL3_CLKDIV GENMASK(2, 0)
/* CONTROL0 values */
#define AFE440X_CONTROL0_WRITE 0x0
#define AFE440X_CONTROL0_READ 0x1
#define AFE440X_INTENSITY_CHAN(_index, _mask) \
{ \
.type = IIO_INTENSITY, \
.channel = _index, \
.address = _index, \
.scan_index = _index, \
.scan_type = { \
.sign = 's', \
.realbits = 24, \
.storagebits = 32, \
.endianness = IIO_CPU, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
_mask, \
.indexed = true, \
}
#define AFE440X_CURRENT_CHAN(_index) \
{ \
.type = IIO_CURRENT, \
.channel = _index, \
.address = _index, \
.scan_index = -1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.indexed = true, \
.output = true, \
}
struct afe440x_val_table {
int integer;
int fract;
};
#define AFE440X_TABLE_ATTR(_name, _table) \
static ssize_t _name ## _show(struct device *dev, \
struct device_attribute *attr, char *buf) \
{ \
ssize_t len = 0; \
int i; \
\
for (i = 0; i < ARRAY_SIZE(_table); i++) \
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06u ", \
_table[i].integer, \
_table[i].fract); \
\
buf[len - 1] = '\n'; \
\
return len; \
} \
static DEVICE_ATTR_RO(_name)
struct afe440x_attr {
struct device_attribute dev_attr;
unsigned int field;
const struct afe440x_val_table *val_table;
unsigned int table_size;
};
#define to_afe440x_attr(_dev_attr) \
container_of(_dev_attr, struct afe440x_attr, dev_attr)
#define AFE440X_ATTR(_name, _field, _table) \
struct afe440x_attr afe440x_attr_##_name = { \
.dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \
afe440x_show_register, \
afe440x_store_register), \
.field = _field, \
.val_table = _table, \
.table_size = ARRAY_SIZE(_table), \
}
#endif /* _AFE440X_H */
linux-7.2.3/drivers/iio/health/max30100.c
+534
View File
@@ -0,0 +1,534 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* max30100.c - Support for MAX30100 heart rate and pulse oximeter sensor
*
* Copyright (C) 2015, 2018
* Author: Matt Ranostay <matt.ranostay@konsulko.com>
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/bitfield.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/kfifo_buf.h>
#define MAX30100_DRV_NAME "max30100"
#define MAX30100_REG_INT_STATUS 0x00
#define MAX30100_REG_INT_STATUS_PWR_RDY BIT(0)
#define MAX30100_REG_INT_STATUS_SPO2_RDY BIT(4)
#define MAX30100_REG_INT_STATUS_HR_RDY BIT(5)
#define MAX30100_REG_INT_STATUS_FIFO_RDY BIT(7)
#define MAX30100_REG_INT_ENABLE 0x01
#define MAX30100_REG_INT_ENABLE_SPO2_EN BIT(0)
#define MAX30100_REG_INT_ENABLE_HR_EN BIT(1)
#define MAX30100_REG_INT_ENABLE_FIFO_EN BIT(3)
#define MAX30100_REG_INT_ENABLE_MASK 0xf0
#define MAX30100_REG_INT_ENABLE_MASK_SHIFT 4
#define MAX30100_REG_FIFO_WR_PTR 0x02
#define MAX30100_REG_FIFO_OVR_CTR 0x03
#define MAX30100_REG_FIFO_RD_PTR 0x04
#define MAX30100_REG_FIFO_DATA 0x05
#define MAX30100_REG_FIFO_DATA_ENTRY_COUNT 16
#define MAX30100_REG_FIFO_DATA_ENTRY_LEN 4
#define MAX30100_REG_MODE_CONFIG 0x06
#define MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN BIT(0)
#define MAX30100_REG_MODE_CONFIG_MODE_HR_EN BIT(1)
#define MAX30100_REG_MODE_CONFIG_MODE_MASK 0x03
#define MAX30100_REG_MODE_CONFIG_TEMP_EN BIT(3)
#define MAX30100_REG_MODE_CONFIG_PWR BIT(7)
#define MAX30100_REG_SPO2_CONFIG 0x07
#define MAX30100_REG_SPO2_CONFIG_PW_MASK GENMASK(1, 0)
#define MAX30100_REG_SPO2_CONFIG_200US 0x0
#define MAX30100_REG_SPO2_CONFIG_400US 0x1
#define MAX30100_REG_SPO2_CONFIG_800US 0x2
#define MAX30100_REG_SPO2_CONFIG_1600US 0x3
#define MAX30100_REG_SPO2_CONFIG_100HZ BIT(2)
#define MAX30100_REG_SPO2_CONFIG_HI_RES_EN BIT(6)
#define MAX30100_REG_LED_CONFIG 0x09
#define MAX30100_REG_LED_CONFIG_LED_MASK 0x0f
#define MAX30100_REG_LED_CONFIG_RED_LED_SHIFT 4
#define MAX30100_REG_LED_CONFIG_24MA 0x07
#define MAX30100_REG_LED_CONFIG_50MA 0x0f
#define MAX30100_REG_TEMP_INTEGER 0x16
#define MAX30100_REG_TEMP_FRACTION 0x17
struct max30100_data {
struct i2c_client *client;
struct iio_dev *indio_dev;
struct mutex lock;
struct regmap *regmap;
__be16 buffer[2]; /* 2 16-bit channels */
};
static bool max30100_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX30100_REG_INT_STATUS:
case MAX30100_REG_MODE_CONFIG:
case MAX30100_REG_FIFO_WR_PTR:
case MAX30100_REG_FIFO_OVR_CTR:
case MAX30100_REG_FIFO_RD_PTR:
case MAX30100_REG_FIFO_DATA:
case MAX30100_REG_TEMP_INTEGER:
case MAX30100_REG_TEMP_FRACTION:
return true;
default:
return false;
}
}
static const struct regmap_config max30100_regmap_config = {
.name = "max30100_regmap",
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX30100_REG_TEMP_FRACTION,
.cache_type = REGCACHE_FLAT,
.volatile_reg = max30100_is_volatile_reg,
};
static const unsigned int max30100_led_current_mapping[] = {
4400, 7600, 11000, 14200, 17400,
20800, 24000, 27100, 30600, 33800,
37000, 40200, 43600, 46800, 50000
};
static const unsigned long max30100_scan_masks[] = {0x3, 0};
static const struct iio_chan_spec max30100_channels[] = {
{
.type = IIO_INTENSITY,
.channel2 = IIO_MOD_LIGHT_IR,
.modified = 1,
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
},
{
.type = IIO_INTENSITY,
.channel2 = IIO_MOD_LIGHT_RED,
.modified = 1,
.scan_index = 1,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
},
{
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
},
};
static int max30100_set_powermode(struct max30100_data *data, bool state)
{
return regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
MAX30100_REG_MODE_CONFIG_PWR,
state ? 0 : MAX30100_REG_MODE_CONFIG_PWR);
}
static int max30100_clear_fifo(struct max30100_data *data)
{
int ret;
ret = regmap_write(data->regmap, MAX30100_REG_FIFO_WR_PTR, 0);
if (ret)
return ret;
ret = regmap_write(data->regmap, MAX30100_REG_FIFO_OVR_CTR, 0);
if (ret)
return ret;
return regmap_write(data->regmap, MAX30100_REG_FIFO_RD_PTR, 0);
}
static int max30100_buffer_postenable(struct iio_dev *indio_dev)
{
struct max30100_data *data = iio_priv(indio_dev);
int ret;
ret = max30100_set_powermode(data, true);
if (ret)
return ret;
return max30100_clear_fifo(data);
}
static int max30100_buffer_predisable(struct iio_dev *indio_dev)
{
struct max30100_data *data = iio_priv(indio_dev);
return max30100_set_powermode(data, false);
}
static const struct iio_buffer_setup_ops max30100_buffer_setup_ops = {
.postenable = max30100_buffer_postenable,
.predisable = max30100_buffer_predisable,
};
static inline int max30100_fifo_count(struct max30100_data *data)
{
unsigned int val;
int ret;
ret = regmap_read(data->regmap, MAX30100_REG_INT_STATUS, &val);
if (ret)
return ret;
/* FIFO is almost full */
if (val & MAX30100_REG_INT_STATUS_FIFO_RDY)
return MAX30100_REG_FIFO_DATA_ENTRY_COUNT - 1;
return 0;
}
static int max30100_read_measurement(struct max30100_data *data)
{
int ret;
ret = i2c_smbus_read_i2c_block_data(data->client,
MAX30100_REG_FIFO_DATA,
MAX30100_REG_FIFO_DATA_ENTRY_LEN,
(u8 *) &data->buffer);
return (ret == MAX30100_REG_FIFO_DATA_ENTRY_LEN) ? 0 : ret;
}
static irqreturn_t max30100_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct max30100_data *data = iio_priv(indio_dev);
int ret, cnt = 0;
mutex_lock(&data->lock);
while (cnt || (cnt = max30100_fifo_count(data)) > 0) {
ret = max30100_read_measurement(data);
if (ret)
break;
iio_push_to_buffers(data->indio_dev, data->buffer);
cnt--;
}
mutex_unlock(&data->lock);
return IRQ_HANDLED;
}
static int max30100_get_current_idx(unsigned int val, int *reg)
{
int idx;
/* LED turned off */
if (val == 0) {
*reg = 0;
return 0;
}
for (idx = 0; idx < ARRAY_SIZE(max30100_led_current_mapping); idx++) {
if (max30100_led_current_mapping[idx] == val) {
*reg = idx + 1;
return 0;
}
}
return -EINVAL;
}
static int max30100_led_init(struct max30100_data *data)
{
struct device *dev = &data->client->dev;
unsigned int val[2];
int reg, ret;
ret = device_property_read_u32_array(dev, "maxim,led-current-microamp",
(unsigned int *) &val, 2);
if (ret) {
/* Default to 24 mA RED LED, 50 mA IR LED */
reg = (MAX30100_REG_LED_CONFIG_24MA <<
MAX30100_REG_LED_CONFIG_RED_LED_SHIFT) |
MAX30100_REG_LED_CONFIG_50MA;
dev_warn(dev, "no led-current-microamp set");
return regmap_write(data->regmap, MAX30100_REG_LED_CONFIG, reg);
}
/* RED LED current */
ret = max30100_get_current_idx(val[0], &reg);
if (ret) {
dev_err(dev, "invalid RED current setting %d", val[0]);
return ret;
}
ret = regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
MAX30100_REG_LED_CONFIG_LED_MASK <<
MAX30100_REG_LED_CONFIG_RED_LED_SHIFT,
reg << MAX30100_REG_LED_CONFIG_RED_LED_SHIFT);
if (ret)
return ret;
/* IR LED current */
ret = max30100_get_current_idx(val[1], &reg);
if (ret) {
dev_err(dev, "invalid IR current setting %d", val[1]);
return ret;
}
return regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
MAX30100_REG_LED_CONFIG_LED_MASK, reg);
}
static int max30100_get_pulse_width(unsigned int pwidth_us)
{
switch (pwidth_us) {
case 200:
return MAX30100_REG_SPO2_CONFIG_200US;
case 400:
return MAX30100_REG_SPO2_CONFIG_400US;
case 800:
return MAX30100_REG_SPO2_CONFIG_800US;
case 1600:
return MAX30100_REG_SPO2_CONFIG_1600US;
default:
return -EINVAL;
}
}
static int max30100_chip_init(struct max30100_data *data)
{
int ret;
int pulse_width;
/* set default LED pulse-width to 1600 us */
unsigned int pulse_us = 1600;
struct device *dev = &data->client->dev;
/* setup LED current settings */
ret = max30100_led_init(data);
if (ret)
return ret;
/* Read LED pulse-width-us from DT */
device_property_read_u32(dev, "maxim,pulse-width-us", &pulse_us);
pulse_width = max30100_get_pulse_width(pulse_us);
if (pulse_width < 0)
return dev_err_probe(dev, pulse_width, "invalid LED pulse-width %uus\n", pulse_us);
/* enable hi-res SPO2 readings at 100Hz */
ret = regmap_write(data->regmap, MAX30100_REG_SPO2_CONFIG,
MAX30100_REG_SPO2_CONFIG_HI_RES_EN |
MAX30100_REG_SPO2_CONFIG_100HZ |
FIELD_PREP(MAX30100_REG_SPO2_CONFIG_PW_MASK, pulse_width));
if (ret)
return ret;
/* enable SPO2 mode */
ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
MAX30100_REG_MODE_CONFIG_MODE_MASK,
MAX30100_REG_MODE_CONFIG_MODE_HR_EN |
MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN);
if (ret)
return ret;
/* enable FIFO interrupt */
return regmap_update_bits(data->regmap, MAX30100_REG_INT_ENABLE,
MAX30100_REG_INT_ENABLE_MASK,
MAX30100_REG_INT_ENABLE_FIFO_EN
<< MAX30100_REG_INT_ENABLE_MASK_SHIFT);
}
static int max30100_read_temp(struct max30100_data *data, int *val)
{
int ret;
unsigned int reg;
ret = regmap_read(data->regmap, MAX30100_REG_TEMP_INTEGER, &reg);
if (ret < 0)
return ret;
*val = reg << 4;
ret = regmap_read(data->regmap, MAX30100_REG_TEMP_FRACTION, &reg);
if (ret < 0)
return ret;
*val |= reg & 0xf;
*val = sign_extend32(*val, 11);
return 0;
}
static int max30100_get_temp(struct max30100_data *data, int *val)
{
int ret;
/* start acquisition */
ret = regmap_set_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
MAX30100_REG_MODE_CONFIG_TEMP_EN);
if (ret)
return ret;
msleep(35);
return max30100_read_temp(data, val);
}
static int max30100_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max30100_data *data = iio_priv(indio_dev);
int ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
/*
* Temperature reading can only be acquired while engine
* is running
*/
if (!iio_device_try_claim_buffer_mode(indio_dev)) {
ret = -EAGAIN;
} else {
ret = max30100_get_temp(data, val);
if (!ret)
ret = IIO_VAL_INT;
iio_device_release_buffer_mode(indio_dev);
}
break;
case IIO_CHAN_INFO_SCALE:
*val = 1; /* 0.0625 */
*val2 = 16;
ret = IIO_VAL_FRACTIONAL;
break;
}
return ret;
}
static const struct iio_info max30100_info = {
.read_raw = max30100_read_raw,
};
static int max30100_probe(struct i2c_client *client)
{
struct max30100_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
indio_dev->name = MAX30100_DRV_NAME;
indio_dev->channels = max30100_channels;
indio_dev->info = &max30100_info;
indio_dev->num_channels = ARRAY_SIZE(max30100_channels);
indio_dev->available_scan_masks = max30100_scan_masks;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
&max30100_buffer_setup_ops);
if (ret)
return ret;
data = iio_priv(indio_dev);
data->indio_dev = indio_dev;
data->client = client;
mutex_init(&data->lock);
i2c_set_clientdata(client, indio_dev);
data->regmap = devm_regmap_init_i2c(client, &max30100_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "regmap initialization failed.\n");
return PTR_ERR(data->regmap);
}
max30100_set_powermode(data, false);
ret = max30100_chip_init(data);
if (ret)
return ret;
if (client->irq <= 0) {
dev_err(&client->dev, "no valid irq defined\n");
return -EINVAL;
}
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, max30100_interrupt_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max30100_irq", indio_dev);
if (ret) {
dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
return ret;
}
return iio_device_register(indio_dev);
}
static void max30100_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct max30100_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
max30100_set_powermode(data, false);
}
static const struct i2c_device_id max30100_id[] = {
{ .name = "max30100" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max30100_id);
static const struct of_device_id max30100_dt_ids[] = {
{ .compatible = "maxim,max30100" },
{ }
};
MODULE_DEVICE_TABLE(of, max30100_dt_ids);
static struct i2c_driver max30100_driver = {
.driver = {
.name = MAX30100_DRV_NAME,
.of_match_table = max30100_dt_ids,
},
.probe = max30100_probe,
.remove = max30100_remove,
.id_table = max30100_id,
};
module_i2c_driver(max30100_driver);
MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
MODULE_DESCRIPTION("MAX30100 heart rate and pulse oximeter sensor");
MODULE_LICENSE("GPL");
linux-7.2.3/drivers/iio/health/max30102.c
+626
View File
@@ -0,0 +1,626 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
*
* Copyright (C) 2017 Matt Ranostay <matt.ranostay@konsulko.com>
*
* Support for MAX30105 optical particle sensor
* Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
*
* 7-bit I2C chip address: 0x57
* TODO: proximity power saving feature
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/kfifo_buf.h>
#define MAX30102_DRV_NAME "max30102"
#define MAX30102_PART_NUMBER 0x15
enum max30102_chip_id {
max30102,
max30105,
};
enum max3012_led_idx {
MAX30102_LED_RED,
MAX30102_LED_IR,
MAX30105_LED_GREEN,
};
#define MAX30102_REG_INT_STATUS 0x00
#define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0)
#define MAX30102_REG_INT_STATUS_PROX_INT BIT(4)
#define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5)
#define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6)
#define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7)
#define MAX30102_REG_INT_ENABLE 0x02
#define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4)
#define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5)
#define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6)
#define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7)
#define MAX30102_REG_INT_ENABLE_MASK 0xf0
#define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4
#define MAX30102_REG_FIFO_WR_PTR 0x04
#define MAX30102_REG_FIFO_OVR_CTR 0x05
#define MAX30102_REG_FIFO_RD_PTR 0x06
#define MAX30102_REG_FIFO_DATA 0x07
#define MAX30102_REG_FIFO_DATA_BYTES 3
#define MAX30102_REG_FIFO_CONFIG 0x08
#define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1)
#define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5
#define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0)
#define MAX30102_REG_MODE_CONFIG 0x09
#define MAX30102_REG_MODE_CONFIG_MODE_NONE 0x00
#define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */
#define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */
#define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
#define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)
#define MAX30102_REG_MODE_CONFIG_PWR BIT(7)
#define MAX30102_REG_MODE_CONTROL_SLOT21 0x11 /* multi-LED control */
#define MAX30102_REG_MODE_CONTROL_SLOT43 0x12
#define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))
#define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT 4
#define MAX30102_REG_SPO2_CONFIG 0x0a
#define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03
#define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03
#define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07
#define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2
#define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0)
#define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5
#define MAX30102_REG_RED_LED_CONFIG 0x0c
#define MAX30102_REG_IR_LED_CONFIG 0x0d
#define MAX30105_REG_GREEN_LED_CONFIG 0x0e
#define MAX30102_REG_TEMP_CONFIG 0x21
#define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0)
#define MAX30102_REG_TEMP_INTEGER 0x1f
#define MAX30102_REG_TEMP_FRACTION 0x20
#define MAX30102_REG_REV_ID 0xfe
#define MAX30102_REG_PART_ID 0xff
struct max30102_data {
struct i2c_client *client;
struct iio_dev *indio_dev;
struct mutex lock;
struct regmap *regmap;
enum max30102_chip_id chip_id;
u8 buffer[12];
__be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
};
static const struct regmap_config max30102_regmap_config = {
.name = "max30102_regmap",
.reg_bits = 8,
.val_bits = 8,
};
static const unsigned long max30102_scan_masks[] = {
BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
0
};
static const unsigned long max30105_scan_masks[] = {
BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
BIT(MAX30105_LED_GREEN),
0
};
#define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
.type = IIO_INTENSITY, \
.channel2 = _mod, \
.modified = 1, \
.scan_index = _si, \
.scan_type = { \
.sign = 'u', \
.shift = 8, \
.realbits = 18, \
.storagebits = 32, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec max30102_channels[] = {
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
{
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
},
};
static const struct iio_chan_spec max30105_channels[] = {
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
{
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
},
};
static int max30102_set_power(struct max30102_data *data, bool en)
{
return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
MAX30102_REG_MODE_CONFIG_PWR,
en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
}
static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
{
u8 reg = mode;
if (!en)
reg |= MAX30102_REG_MODE_CONFIG_PWR;
return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
MAX30102_REG_MODE_CONFIG_PWR |
MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
}
#define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
static int max30102_buffer_postenable(struct iio_dev *indio_dev)
{
struct max30102_data *data = iio_priv(indio_dev);
int ret;
u8 reg;
switch (*indio_dev->active_scan_mask) {
case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
break;
case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
BIT(MAX30105_LED_GREEN):
ret = regmap_update_bits(data->regmap,
MAX30102_REG_MODE_CONTROL_SLOT21,
MAX30102_REG_MODE_CONTROL_SLOT_MASK,
MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
if (ret)
return ret;
ret = regmap_update_bits(data->regmap,
MAX30102_REG_MODE_CONTROL_SLOT43,
MAX30102_REG_MODE_CONTROL_SLOT_MASK,
MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
if (ret)
return ret;
reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
break;
default:
return -EINVAL;
}
return max30102_set_powermode(data, reg, true);
}
static int max30102_buffer_predisable(struct iio_dev *indio_dev)
{
struct max30102_data *data = iio_priv(indio_dev);
return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
false);
}
static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
.postenable = max30102_buffer_postenable,
.predisable = max30102_buffer_predisable,
};
static inline int max30102_fifo_count(struct max30102_data *data)
{
unsigned int val;
int ret;
ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
if (ret)
return ret;
/* FIFO has one sample slot left */
if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
return 1;
return 0;
}
#define MAX30102_COPY_DATA(i) \
memcpy(&data->processed_buffer[(i)], \
&buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
MAX30102_REG_FIFO_DATA_BYTES)
static int max30102_read_measurement(struct max30102_data *data,
unsigned int measurements)
{
int ret;
u8 *buffer = (u8 *) &data->buffer;
ret = i2c_smbus_read_i2c_block_data(data->client,
MAX30102_REG_FIFO_DATA,
measurements *
MAX30102_REG_FIFO_DATA_BYTES,
buffer);
switch (measurements) {
case 3:
MAX30102_COPY_DATA(2);
fallthrough;
case 2:
MAX30102_COPY_DATA(1);
fallthrough;
case 1:
MAX30102_COPY_DATA(0);
break;
default:
return -EINVAL;
}
return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
0 : -EINVAL;
}
static irqreturn_t max30102_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct max30102_data *data = iio_priv(indio_dev);
unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
iio_get_masklength(indio_dev));
int ret, cnt = 0;
mutex_lock(&data->lock);
while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
ret = max30102_read_measurement(data, measurements);
if (ret)
break;
iio_push_to_buffers(data->indio_dev, data->processed_buffer);
cnt--;
}
mutex_unlock(&data->lock);
return IRQ_HANDLED;
}
static int max30102_get_current_idx(unsigned int val, int *reg)
{
/* each step is 0.200 mA */
*reg = val / 200;
return *reg > 0xff ? -EINVAL : 0;
}
static int max30102_led_init(struct max30102_data *data)
{
struct device *dev = &data->client->dev;
unsigned int val;
int reg, ret;
ret = device_property_read_u32(dev, "maxim,red-led-current-microamp", &val);
if (ret) {
dev_info(dev, "no red-led-current-microamp set\n");
/* Default to 7 mA RED LED */
val = 7000;
}
ret = max30102_get_current_idx(val, &reg);
if (ret) {
dev_err(dev, "invalid RED LED current setting %d\n", val);
return ret;
}
ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
if (ret)
return ret;
if (data->chip_id == max30105) {
ret = device_property_read_u32(dev,
"maxim,green-led-current-microamp", &val);
if (ret) {
dev_info(dev, "no green-led-current-microamp set\n");
/* Default to 7 mA green LED */
val = 7000;
}
ret = max30102_get_current_idx(val, &reg);
if (ret) {
dev_err(dev, "invalid green LED current setting %d\n",
val);
return ret;
}
ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
reg);
if (ret)
return ret;
}
ret = device_property_read_u32(dev, "maxim,ir-led-current-microamp", &val);
if (ret) {
dev_info(dev, "no ir-led-current-microamp set\n");
/* Default to 7 mA IR LED */
val = 7000;
}
ret = max30102_get_current_idx(val, &reg);
if (ret) {
dev_err(dev, "invalid IR LED current setting %d\n", val);
return ret;
}
return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
}
static int max30102_chip_init(struct max30102_data *data)
{
int ret;
/* setup LED current settings */
ret = max30102_led_init(data);
if (ret)
return ret;
/* configure 18-bit HR + SpO2 readings at 400Hz */
ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
(MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
<< MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
(MAX30102_REG_SPO2_CONFIG_SR_400HZ
<< MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
if (ret)
return ret;
/* average 4 samples + generate FIFO interrupt */
ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
(MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
<< MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
MAX30102_REG_FIFO_CONFIG_AFULL);
if (ret)
return ret;
/* enable FIFO interrupt */
return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
MAX30102_REG_INT_ENABLE_MASK,
MAX30102_REG_INT_ENABLE_FIFO_EN);
}
static int max30102_read_temp(struct max30102_data *data, int *val)
{
int ret;
unsigned int reg;
ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
if (ret < 0)
return ret;
*val = reg << 4;
ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
if (ret < 0)
return ret;
*val |= reg & 0xf;
*val = sign_extend32(*val, 11);
return 0;
}
static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
{
int ret;
if (en) {
ret = max30102_set_power(data, true);
if (ret)
return ret;
}
/* start acquisition */
ret = regmap_set_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
MAX30102_REG_TEMP_CONFIG_TEMP_EN);
if (ret)
goto out;
msleep(35);
ret = max30102_read_temp(data, val);
out:
if (en)
max30102_set_power(data, false);
return ret;
}
static int max30102_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max30102_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW: {
/*
* Temperature reading can only be acquired when not in
* shutdown; leave shutdown briefly when buffer not running
*/
IIO_DEV_GUARD_CURRENT_MODE(indio_dev);
ret = max30102_get_temp(data, val, !iio_buffer_enabled(indio_dev));
if (ret)
return ret;
return IIO_VAL_INT;
}
case IIO_CHAN_INFO_SCALE:
*val = 1000; /* 62.5 */
*val2 = 16;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static const struct iio_info max30102_info = {
.read_raw = max30102_read_raw,
};
static int max30102_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct max30102_data *data;
struct iio_dev *indio_dev;
int ret;
unsigned int reg;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
indio_dev->name = MAX30102_DRV_NAME;
indio_dev->info = &max30102_info;
indio_dev->modes = INDIO_DIRECT_MODE;
data = iio_priv(indio_dev);
data->indio_dev = indio_dev;
data->client = client;
data->chip_id = id->driver_data;
mutex_init(&data->lock);
i2c_set_clientdata(client, indio_dev);
switch (data->chip_id) {
case max30105:
indio_dev->channels = max30105_channels;
indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
indio_dev->available_scan_masks = max30105_scan_masks;
break;
case max30102:
indio_dev->channels = max30102_channels;
indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
indio_dev->available_scan_masks = max30102_scan_masks;
break;
default:
return -ENODEV;
}
ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
&max30102_buffer_setup_ops);
if (ret)
return ret;
data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "regmap initialization failed\n");
return PTR_ERR(data->regmap);
}
/* check part ID */
ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
if (ret)
return ret;
if (reg != MAX30102_PART_NUMBER)
return -ENODEV;
/* show revision ID */
ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
if (ret)
return ret;
dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
/* clear mode setting, chip shutdown */
ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
false);
if (ret)
return ret;
ret = max30102_chip_init(data);
if (ret)
return ret;
if (client->irq <= 0) {
dev_err(&client->dev, "no valid irq defined\n");
return -EINVAL;
}
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, max30102_interrupt_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max30102_irq", indio_dev);
if (ret) {
dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
return ret;
}
return iio_device_register(indio_dev);
}
static void max30102_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct max30102_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
max30102_set_power(data, false);
}
static const struct i2c_device_id max30102_id[] = {
{ .name = "max30101", .driver_data = max30105 },
{ .name = "max30102", .driver_data = max30102 },
{ .name = "max30105", .driver_data = max30105 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max30102_id);
static const struct of_device_id max30102_dt_ids[] = {
{ .compatible = "maxim,max30101" },
{ .compatible = "maxim,max30102" },
{ .compatible = "maxim,max30105" },
{ }
};
MODULE_DEVICE_TABLE(of, max30102_dt_ids);
static struct i2c_driver max30102_driver = {
.driver = {
.name = MAX30102_DRV_NAME,
.of_match_table = max30102_dt_ids,
},
.probe = max30102_probe,
.remove = max30102_remove,
.id_table = max30102_id,
};
module_i2c_driver(max30102_driver);
MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
MODULE_LICENSE("GPL");