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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/media/platform/mediatek/jpeg/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
config VIDEO_MEDIATEK_JPEG
tristate "Mediatek JPEG Codec driver"
depends on V4L_MEM2MEM_DRIVERS
depends on MTK_IOMMU_V1 || MTK_IOMMU || COMPILE_TEST
depends on VIDEO_DEV
depends on ARCH_MEDIATEK || COMPILE_TEST
depends on MTK_SMI || (COMPILE_TEST && MTK_SMI=n)
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
help
Mediatek jpeg codec driver provides HW capability to decode
JPEG format
To compile this driver as a module, choose M here: the
module will be called mtk-jpeg
linux-7.2.3/drivers/media/platform/mediatek/jpeg/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o \
mtk-jpeg-enc-hw.o \
mtk-jpeg-dec-hw.o
mtk_jpeg-y := mtk_jpeg_core.o \
mtk_jpeg_dec_parse.o
mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
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linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
* Xia Jiang <xia.jiang@mediatek.com>
*/
#ifndef _MTK_JPEG_CORE_H
#define _MTK_JPEG_CORE_H
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fh.h>
#include <media/videobuf2-v4l2.h>
#include "mtk_jpeg_dec_hw.h"
#define MTK_JPEG_NAME "mtk-jpeg"
#define MTK_JPEG_FMT_FLAG_OUTPUT BIT(0)
#define MTK_JPEG_FMT_FLAG_CAPTURE BIT(1)
#define MTK_JPEG_MIN_WIDTH 32U
#define MTK_JPEG_MIN_HEIGHT 32U
#define MTK_JPEG_MAX_WIDTH 65535U
#define MTK_JPEG_MAX_HEIGHT 65535U
#define MTK_JPEG_DEFAULT_SIZEIMAGE (1 * 1024 * 1024)
#define MTK_JPEG_HW_TIMEOUT_MSEC 1000
#define MTK_JPEG_MAX_EXIF_SIZE (64 * 1024)
#define MTK_JPEG_ADDR_MASK GENMASK(1, 0)
/**
* enum mtk_jpeg_ctx_state - states of the context state machine
* @MTK_JPEG_INIT: current state is initialized
* @MTK_JPEG_RUNNING: current state is running
* @MTK_JPEG_SOURCE_CHANGE: current state is source resolution change
*/
enum mtk_jpeg_ctx_state {
MTK_JPEG_INIT = 0,
MTK_JPEG_RUNNING,
MTK_JPEG_SOURCE_CHANGE,
};
/**
* struct mtk_jpeg_variant - mtk jpeg driver variant
* @clks: clock names
* @num_clks: numbers of clock
* @formats: jpeg driver's internal color format
* @num_formats: number of formats
* @qops: the callback of jpeg vb2_ops
* @irq_handler: jpeg irq handler callback
* @hw_reset: jpeg hardware reset callback
* @m2m_ops: the callback of jpeg v4l2_m2m_ops
* @dev_name: jpeg device name
* @ioctl_ops: the callback of jpeg v4l2_ioctl_ops
* @out_q_default_fourcc: output queue default fourcc
* @cap_q_default_fourcc: capture queue default fourcc
* @multi_core: mark jpeg hw is multi_core or not
* @jpeg_worker: jpeg dec or enc worker
* @support_34bit: flag to check support for 34-bit DMA address
*/
struct mtk_jpeg_variant {
struct clk_bulk_data *clks;
int num_clks;
struct mtk_jpeg_fmt *formats;
int num_formats;
const struct vb2_ops *qops;
irqreturn_t (*irq_handler)(int irq, void *priv);
void (*hw_reset)(void __iomem *base);
const struct v4l2_m2m_ops *m2m_ops;
const char *dev_name;
const struct v4l2_ioctl_ops *ioctl_ops;
u32 out_q_default_fourcc;
u32 cap_q_default_fourcc;
bool multi_core;
void (*jpeg_worker)(struct work_struct *work);
bool support_34bit;
};
struct mtk_jpeg_src_buf {
u32 frame_num;
struct vb2_v4l2_buffer b;
struct list_head list;
u32 bs_size;
struct mtk_jpeg_dec_param dec_param;
struct mtk_jpeg_ctx *curr_ctx;
};
enum mtk_jpeg_hw_state {
MTK_JPEG_HW_IDLE = 0,
MTK_JPEG_HW_BUSY = 1,
};
struct mtk_jpeg_hw_param {
struct vb2_v4l2_buffer *src_buffer;
struct vb2_v4l2_buffer *dst_buffer;
struct mtk_jpeg_ctx *curr_ctx;
};
enum mtk_jpegenc_hw_id {
MTK_JPEGENC_HW0,
MTK_JPEGENC_HW1,
MTK_JPEGENC_HW_MAX,
};
enum mtk_jpegdec_hw_id {
MTK_JPEGDEC_HW0,
MTK_JPEGDEC_HW1,
MTK_JPEGDEC_HW2,
MTK_JPEGDEC_HW_MAX,
};
/**
* struct mtk_jpegenc_clk - Structure used to store vcodec clock information
* @clks: JPEG encode clock
* @clk_num: JPEG encode clock numbers
*/
struct mtk_jpegenc_clk {
struct clk_bulk_data *clks;
int clk_num;
};
/**
* struct mtk_jpegdec_clk - Structure used to store vcodec clock information
* @clks: JPEG decode clock
* @clk_num: JPEG decode clock numbers
*/
struct mtk_jpegdec_clk {
struct clk_bulk_data *clks;
int clk_num;
};
/**
* struct mtk_jpegenc_comp_dev - JPEG COREX abstraction
* @dev: JPEG device
* @plat_dev: platform device data
* @reg_base: JPEG registers mapping
* @master_dev: mtk_jpeg_dev device
* @venc_clk: jpeg encode clock
* @jpegenc_irq: jpeg encode irq num
* @job_timeout_work: encode timeout workqueue
* @hw_param: jpeg encode hw parameters
* @hw_state: record hw state
* @hw_lock: spinlock protecting the hw device resource
*/
struct mtk_jpegenc_comp_dev {
struct device *dev;
struct platform_device *plat_dev;
void __iomem *reg_base;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegenc_clk venc_clk;
int jpegenc_irq;
struct delayed_work job_timeout_work;
struct mtk_jpeg_hw_param hw_param;
enum mtk_jpeg_hw_state hw_state;
/* spinlock protecting the hw device resource */
spinlock_t hw_lock;
};
/**
* struct mtk_jpegdec_comp_dev - JPEG COREX abstraction
* @dev: JPEG device
* @plat_dev: platform device data
* @reg_base: JPEG registers mapping
* @master_dev: mtk_jpeg_dev device
* @jdec_clk: mtk_jpegdec_clk
* @jpegdec_irq: jpeg decode irq num
* @job_timeout_work: decode timeout workqueue
* @hw_param: jpeg decode hw parameters
* @hw_state: record hw state
* @hw_lock: spinlock protecting hw
*/
struct mtk_jpegdec_comp_dev {
struct device *dev;
struct platform_device *plat_dev;
void __iomem *reg_base;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegdec_clk jdec_clk;
int jpegdec_irq;
struct delayed_work job_timeout_work;
struct mtk_jpeg_hw_param hw_param;
enum mtk_jpeg_hw_state hw_state;
/* spinlock protecting the hw device resource */
spinlock_t hw_lock;
};
/**
* struct mtk_jpeg_dev - JPEG IP abstraction
* @lock: the mutex protecting this structure
* @hw_lock: spinlock protecting the hw device resource
* @workqueue: decode work queue
* @dev: JPEG device
* @v4l2_dev: v4l2 device for mem2mem mode
* @m2m_dev: v4l2 mem2mem device data
* @alloc_ctx: videobuf2 memory allocator's context
* @vdev: video device node for jpeg mem2mem mode
* @reg_base: JPEG registers mapping
* @job_timeout_work: IRQ timeout structure
* @variant: driver variant to be used
* @reg_encbase: jpg encode register base addr
* @enc_hw_dev: jpg encode hardware device
* @hw_wq: jpg wait queue
* @hw_rdy: jpg hw ready flag
* @reg_decbase: jpg decode register base addr
* @dec_hw_dev: jpg decode hardware device
* @hw_index: jpg hw index
*/
struct mtk_jpeg_dev {
struct mutex lock;
spinlock_t hw_lock;
struct workqueue_struct *workqueue;
struct device *dev;
struct v4l2_device v4l2_dev;
struct v4l2_m2m_dev *m2m_dev;
void *alloc_ctx;
struct video_device *vdev;
void __iomem *reg_base;
struct delayed_work job_timeout_work;
const struct mtk_jpeg_variant *variant;
void __iomem *reg_encbase[MTK_JPEGENC_HW_MAX];
struct mtk_jpegenc_comp_dev *enc_hw_dev[MTK_JPEGENC_HW_MAX];
wait_queue_head_t hw_wq;
atomic_t hw_rdy;
void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
atomic_t hw_index;
};
/**
* struct mtk_jpeg_fmt - driver's internal color format data
* @fourcc: the fourcc code, 0 if not applicable
* @hw_format: hardware format value
* @h_sample: horizontal sample count of plane in 4 * 4 pixel image
* @v_sample: vertical sample count of plane in 4 * 4 pixel image
* @colplanes: number of color planes (1 for packed formats)
* @h_align: horizontal alignment order (align to 2^h_align)
* @v_align: vertical alignment order (align to 2^v_align)
* @flags: flags describing format applicability
*/
struct mtk_jpeg_fmt {
u32 fourcc;
u32 hw_format;
int h_sample[VIDEO_MAX_PLANES];
int v_sample[VIDEO_MAX_PLANES];
int colplanes;
int h_align;
int v_align;
u32 flags;
};
/**
* struct mtk_jpeg_q_data - parameters of one queue
* @fmt: driver-specific format of this queue
* @pix_mp: multiplanar format
* @enc_crop_rect: jpeg encoder crop information
*/
struct mtk_jpeg_q_data {
struct mtk_jpeg_fmt *fmt;
struct v4l2_pix_format_mplane pix_mp;
struct v4l2_rect enc_crop_rect;
};
/**
* struct mtk_jpeg_ctx - the device context data
* @jpeg: JPEG IP device for this context
* @out_q: source (output) queue information
* @cap_q: destination queue information
* @fh: V4L2 file handle
* @state: state of the context
* @enable_exif: enable exif mode of jpeg encoder
* @enc_quality: jpeg encoder quality
* @restart_interval: jpeg encoder restart interval
* @ctrl_hdl: controls handler
* @jpeg_work: jpeg encoder workqueue
* @total_frame_num: encoded frame number
* @dst_done_queue: encoded frame buffer queue
* @done_queue_lock: encoded frame operation spinlock
* @last_done_frame_num: the last encoded frame number
*/
struct mtk_jpeg_ctx {
struct mtk_jpeg_dev *jpeg;
struct mtk_jpeg_q_data out_q;
struct mtk_jpeg_q_data cap_q;
struct v4l2_fh fh;
enum mtk_jpeg_ctx_state state;
bool enable_exif;
u8 enc_quality;
u8 restart_interval;
struct v4l2_ctrl_handler ctrl_hdl;
struct work_struct jpeg_work;
u32 total_frame_num;
struct list_head dst_done_queue;
/* spinlock protecting the encode done buffer */
spinlock_t done_queue_lock;
u32 last_done_frame_num;
};
#endif /* _MTK_JPEG_CORE_H */
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <media/media-device.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-event.h>
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_hw.h"
#define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
enum mtk_jpeg_color {
MTK_JPEG_COLOR_420 = 0x00221111,
MTK_JPEG_COLOR_422 = 0x00211111,
MTK_JPEG_COLOR_444 = 0x00111111,
MTK_JPEG_COLOR_422V = 0x00121111,
MTK_JPEG_COLOR_422X2 = 0x00412121,
MTK_JPEG_COLOR_422VX2 = 0x00222121,
MTK_JPEG_COLOR_400 = 0x00110000
};
static const struct of_device_id mtk_jpegdec_hw_ids[] = {
{
.compatible = "mediatek,mt8195-jpgdec-hw",
},
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
{
if (val & (align - 1)) {
pr_err("mtk-jpeg: write reg %x without %d align\n", reg, align);
return -1;
}
return 0;
}
static int mtk_jpeg_decide_format(struct mtk_jpeg_dec_param *param)
{
param->src_color = (param->sampling_w[0] << 20) |
(param->sampling_h[0] << 16) |
(param->sampling_w[1] << 12) |
(param->sampling_h[1] << 8) |
(param->sampling_w[2] << 4) |
(param->sampling_h[2]);
param->uv_brz_w = 0;
switch (param->src_color) {
case MTK_JPEG_COLOR_444:
param->uv_brz_w = 1;
param->dst_fourcc = V4L2_PIX_FMT_YUV422M;
break;
case MTK_JPEG_COLOR_422X2:
case MTK_JPEG_COLOR_422:
param->dst_fourcc = V4L2_PIX_FMT_YUV422M;
break;
case MTK_JPEG_COLOR_422V:
case MTK_JPEG_COLOR_422VX2:
param->uv_brz_w = 1;
param->dst_fourcc = V4L2_PIX_FMT_YUV420M;
break;
case MTK_JPEG_COLOR_420:
param->dst_fourcc = V4L2_PIX_FMT_YUV420M;
break;
case MTK_JPEG_COLOR_400:
param->dst_fourcc = V4L2_PIX_FMT_GREY;
break;
default:
param->dst_fourcc = 0;
return -1;
}
return 0;
}
static void mtk_jpeg_calc_mcu(struct mtk_jpeg_dec_param *param)
{
u32 factor_w, factor_h;
u32 i, comp, blk;
factor_w = 2 + param->sampling_w[0];
factor_h = 2 + param->sampling_h[0];
param->mcu_w = (param->pic_w + (1 << factor_w) - 1) >> factor_w;
param->mcu_h = (param->pic_h + (1 << factor_h) - 1) >> factor_h;
param->total_mcu = param->mcu_w * param->mcu_h;
param->unit_num = ((param->pic_w + 7) >> 3) * ((param->pic_h + 7) >> 3);
param->blk_num = 0;
for (i = 0; i < MTK_JPEG_COMP_MAX; i++) {
param->blk_comp[i] = 0;
if (i >= param->comp_num)
continue;
param->blk_comp[i] = param->sampling_w[i] *
param->sampling_h[i];
param->blk_num += param->blk_comp[i];
}
param->membership = 0;
for (i = 0, blk = 0, comp = 0; i < MTK_JPEG_BLOCK_MAX; i++) {
if (i < param->blk_num && comp < param->comp_num) {
u32 tmp;
tmp = (0x04 + (comp & 0x3));
param->membership |= tmp << (i * 3);
if (++blk == param->blk_comp[comp]) {
comp++;
blk = 0;
}
} else {
param->membership |= 7 << (i * 3);
}
}
}
static void mtk_jpeg_calc_dma_group(struct mtk_jpeg_dec_param *param)
{
u32 factor_mcu = 3;
if (param->src_color == MTK_JPEG_COLOR_444 &&
param->dst_fourcc == V4L2_PIX_FMT_YUV422M)
factor_mcu = 4;
else if (param->src_color == MTK_JPEG_COLOR_422V &&
param->dst_fourcc == V4L2_PIX_FMT_YUV420M)
factor_mcu = 4;
else if (param->src_color == MTK_JPEG_COLOR_422X2 &&
param->dst_fourcc == V4L2_PIX_FMT_YUV422M)
factor_mcu = 2;
else if (param->src_color == MTK_JPEG_COLOR_400 ||
(param->src_color & 0x0FFFF) == 0)
factor_mcu = 4;
param->dma_mcu = 1 << factor_mcu;
param->dma_group = param->mcu_w / param->dma_mcu;
param->dma_last_mcu = param->mcu_w % param->dma_mcu;
if (param->dma_last_mcu)
param->dma_group++;
else
param->dma_last_mcu = param->dma_mcu;
}
static int mtk_jpeg_calc_dst_size(struct mtk_jpeg_dec_param *param)
{
u32 i, padding_w;
u32 ds_row_h[3];
u32 brz_w[3];
brz_w[0] = 0;
brz_w[1] = param->uv_brz_w;
brz_w[2] = brz_w[1];
for (i = 0; i < param->comp_num; i++) {
if (brz_w[i] > 3)
return -1;
padding_w = param->mcu_w * MTK_JPEG_DCTSIZE *
param->sampling_w[i];
/* output format is 420/422 */
param->comp_w[i] = padding_w >> brz_w[i];
param->comp_w[i] = round_up(param->comp_w[i],
MTK_JPEG_DCTSIZE);
param->img_stride[i] = i ? round_up(param->comp_w[i], 16)
: round_up(param->comp_w[i], 32);
ds_row_h[i] = (MTK_JPEG_DCTSIZE * param->sampling_h[i]);
}
param->dec_w = param->img_stride[0];
param->dec_h = ds_row_h[0] * param->mcu_h;
for (i = 0; i < MTK_JPEG_COMP_MAX; i++) {
/* They must be equal in frame mode. */
param->mem_stride[i] = param->img_stride[i];
param->comp_size[i] = param->mem_stride[i] * ds_row_h[i] *
param->mcu_h;
}
param->y_size = param->comp_size[0];
param->uv_size = param->comp_size[1];
param->dec_size = param->y_size + (param->uv_size << 1);
return 0;
}
int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param)
{
if (mtk_jpeg_decide_format(param))
return -1;
mtk_jpeg_calc_mcu(param);
mtk_jpeg_calc_dma_group(param);
if (mtk_jpeg_calc_dst_size(param))
return -2;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_fill_param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
{
u32 ret;
ret = readl(base + JPGDEC_REG_INTERRUPT_STATUS) & BIT_INQST_MASK_ALLIRQ;
if (ret)
writel(ret, base + JPGDEC_REG_INTERRUPT_STATUS);
return ret;
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_get_int_status);
u32 mtk_jpeg_dec_enum_result(u32 irq_result)
{
if (irq_result & BIT_INQST_MASK_EOF)
return MTK_JPEG_DEC_RESULT_EOF_DONE;
if (irq_result & BIT_INQST_MASK_PAUSE)
return MTK_JPEG_DEC_RESULT_PAUSE;
if (irq_result & BIT_INQST_MASK_UNDERFLOW)
return MTK_JPEG_DEC_RESULT_UNDERFLOW;
if (irq_result & BIT_INQST_MASK_OVERFLOW)
return MTK_JPEG_DEC_RESULT_OVERFLOW;
if (irq_result & BIT_INQST_MASK_ERROR_BS)
return MTK_JPEG_DEC_RESULT_ERROR_BS;
return MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN;
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_enum_result);
void mtk_jpeg_dec_start(void __iomem *base)
{
writel(0, base + JPGDEC_REG_TRIG);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_start);
static void mtk_jpeg_dec_soft_reset(void __iomem *base)
{
writel(0x0000FFFF, base + JPGDEC_REG_INTERRUPT_STATUS);
writel(0x00, base + JPGDEC_REG_RESET);
writel(0x01, base + JPGDEC_REG_RESET);
}
static void mtk_jpeg_dec_hard_reset(void __iomem *base)
{
writel(0x00, base + JPGDEC_REG_RESET);
writel(0x10, base + JPGDEC_REG_RESET);
}
void mtk_jpeg_dec_reset(void __iomem *base)
{
mtk_jpeg_dec_soft_reset(base);
mtk_jpeg_dec_hard_reset(base);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset);
static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
{
u32 val;
val = (uvscale_h << 12) | (uvscale_w << 8) |
(yscale_h << 4) | yscale_w;
writel(val, base + JPGDEC_REG_BRZ_FACTOR);
}
static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, bool support_34bit,
dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
{
u32 val;
mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y);
writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR0_Y);
mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U);
writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR0_U);
mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V);
writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR0_V);
if (support_34bit) {
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));
writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT);
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));
writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT);
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));
writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT);
}
}
static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, bool support_34bit,
dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
{
u32 val;
writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR1_Y);
writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR1_U);
writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR1_V);
if (support_34bit) {
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));
writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT);
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));
writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT);
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));
writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT);
}
}
static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y,
u32 stride_uv)
{
writel((stride_y & 0xFFFF), base + JPGDEC_REG_STRIDE_Y);
writel((stride_uv & 0xFFFF), base + JPGDEC_REG_STRIDE_UV);
}
static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y,
u32 stride_uv)
{
writel((stride_y & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_Y);
writel((stride_uv & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_UV);
}
static void mtk_jpeg_dec_set_pause_mcu_idx(void __iomem *base, u32 idx)
{
writel(idx & 0x0003FFFFFF, base + JPGDEC_REG_PAUSE_MCU_NUM);
}
static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode)
{
writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);
}
static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, bool support_34bit, dma_addr_t ptr)
{
u32 val;
mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP);
writel(lower_32_bits(ptr), base + JPGDEC_REG_FILE_BRP);
if (support_34bit) {
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(ptr));
writel(val, base + JPGDEC_REG_FILE_BRP_EXT);
}
}
static void mtk_jpeg_dec_set_bs_info(void __iomem *base, bool support_34bit,
dma_addr_t addr, u32 size, u32 bitstream_size)
{
u32 val;
mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
writel(lower_32_bits(addr), base + JPGDEC_REG_FILE_ADDR);
if (support_34bit) {
val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr));
writel(val, base + JPGDEC_REG_FILE_ADDR_EXT);
}
writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
}
static void mtk_jpeg_dec_set_comp_id(void __iomem *base, u32 id_y, u32 id_u,
u32 id_v)
{
u32 val;
val = ((id_y & 0x00FF) << 24) | ((id_u & 0x00FF) << 16) |
((id_v & 0x00FF) << 8);
writel(val, base + JPGDEC_REG_COMP_ID);
}
static void mtk_jpeg_dec_set_total_mcu(void __iomem *base, u32 num)
{
writel(num - 1, base + JPGDEC_REG_TOTAL_MCU_NUM);
}
static void mtk_jpeg_dec_set_comp0_du(void __iomem *base, u32 num)
{
writel(num - 1, base + JPGDEC_REG_COMP0_DATA_UNIT_NUM);
}
static void mtk_jpeg_dec_set_du_membership(void __iomem *base, u32 member,
u32 gmc, u32 isgray)
{
if (isgray)
member = 0x3FFFFFFC;
member |= (isgray << 31) | (gmc << 30);
writel(member, base + JPGDEC_REG_DU_CTRL);
}
static void mtk_jpeg_dec_set_q_table(void __iomem *base, u32 id0, u32 id1,
u32 id2)
{
u32 val;
val = ((id0 & 0x0f) << 8) | ((id1 & 0x0f) << 4) | ((id2 & 0x0f) << 0);
writel(val, base + JPGDEC_REG_QT_ID);
}
static void mtk_jpeg_dec_set_dma_group(void __iomem *base, u32 mcu_group,
u32 group_num, u32 last_mcu)
{
u32 val;
val = (((mcu_group - 1) & 0x00FF) << 16) |
(((group_num - 1) & 0x007F) << 8) |
((last_mcu - 1) & 0x00FF);
writel(val, base + JPGDEC_REG_WDMA_CTRL);
}
static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
u32 y_w, u32 y_h, u32 u_w,
u32 u_h, u32 v_w, u32 v_h)
{
u32 val;
u32 y_wh = (MTK_JPEG_DUNUM_MASK(y_w) << 2) | MTK_JPEG_DUNUM_MASK(y_h);
u32 u_wh = (MTK_JPEG_DUNUM_MASK(u_w) << 2) | MTK_JPEG_DUNUM_MASK(u_h);
u32 v_wh = (MTK_JPEG_DUNUM_MASK(v_w) << 2) | MTK_JPEG_DUNUM_MASK(v_h);
if (comp_num == 1)
val = 0;
else
val = (y_wh << 8) | (u_wh << 4) | v_wh;
writel(val, base + JPGDEC_REG_DU_NUM);
}
void mtk_jpeg_dec_set_config(void __iomem *base,
bool support_34bits,
struct mtk_jpeg_dec_param *cfg,
u32 bitstream_size,
struct mtk_jpeg_bs *bs,
struct mtk_jpeg_fb *fb)
{
mtk_jpeg_dec_set_brz_factor(base, 0, 0, cfg->uv_brz_w, 0);
mtk_jpeg_dec_set_dec_mode(base, 0);
mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
mtk_jpeg_dec_set_bs_info(base, support_34bits, bs->str_addr, bs->size, bitstream_size);
mtk_jpeg_dec_set_bs_write_ptr(base, support_34bits, bs->end_addr);
mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
(cfg->comp_num == 1) ? 1 : 0);
mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
cfg->comp_id[2]);
mtk_jpeg_dec_set_q_table(base, cfg->qtbl_num[0],
cfg->qtbl_num[1], cfg->qtbl_num[2]);
mtk_jpeg_dec_set_sampling_factor(base, cfg->comp_num,
cfg->sampling_w[0],
cfg->sampling_h[0],
cfg->sampling_w[1],
cfg->sampling_h[1],
cfg->sampling_w[2],
cfg->sampling_h[2]);
mtk_jpeg_dec_set_mem_stride(base, cfg->mem_stride[0],
cfg->mem_stride[1]);
mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
cfg->img_stride[1]);
mtk_jpeg_dec_set_dst_bank0(base, support_34bits, fb->plane_addr[0],
fb->plane_addr[1], fb->plane_addr[2]);
mtk_jpeg_dec_set_dst_bank1(base, support_34bits, 0, 0, 0);
mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
cfg->dma_last_mcu);
mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
{
struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
struct vb2_v4l2_buffer *dst_buffer;
struct list_head *temp_entry;
struct list_head *pos = NULL;
struct mtk_jpeg_ctx *ctx;
unsigned long flags;
ctx = jpeg->hw_param.curr_ctx;
if (unlikely(!ctx)) {
dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
return;
}
dst_buffer = jpeg->hw_param.dst_buffer;
if (!dst_buffer) {
dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
return;
}
dst_done_buf = container_of(dst_buffer, struct mtk_jpeg_src_buf, b);
spin_lock_irqsave(&ctx->done_queue_lock, flags);
list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
while (!list_empty(&ctx->dst_done_queue) &&
(pos != &ctx->dst_done_queue)) {
list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
tmp_dst_done_buf = list_entry(pos,
struct mtk_jpeg_src_buf,
list);
if (tmp_dst_done_buf->frame_num ==
ctx->last_done_frame_num) {
list_del(&tmp_dst_done_buf->list);
v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
VB2_BUF_STATE_DONE);
ctx->last_done_frame_num++;
}
}
}
spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
}
static void mtk_jpegdec_timeout_work(struct work_struct *work)
{
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
struct mtk_jpegdec_comp_dev *cjpeg =
container_of(work, struct mtk_jpegdec_comp_dev,
job_timeout_work.work);
struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = cjpeg->hw_param.src_buffer;
dst_buf = cjpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
mtk_jpeg_dec_reset(cjpeg->reg_base);
clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
pm_runtime_put(cjpeg->dev);
cjpeg->hw_state = MTK_JPEG_HW_IDLE;
atomic_inc(&master_jpeg->hw_rdy);
wake_up(&master_jpeg->hw_wq);
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegdec_put_buf(cjpeg);
}
static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
{
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct mtk_jpeg_src_buf *jpeg_src_buf;
enum vb2_buffer_state buf_state;
struct mtk_jpeg_ctx *ctx;
u32 dec_irq_ret;
u32 irq_status;
int i;
struct mtk_jpegdec_comp_dev *jpeg = priv;
struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
cancel_delayed_work(&jpeg->job_timeout_work);
ctx = jpeg->hw_param.curr_ctx;
src_buf = jpeg->hw_param.src_buffer;
dst_buf = jpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
mtk_jpeg_dec_reset(jpeg->reg_base);
if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
dev_warn(jpeg->dev, "Jpg Dec occurs unknown Err.");
jpeg_src_buf =
container_of(src_buf, struct mtk_jpeg_src_buf, b);
for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&dst_buf->vb2_buf, i,
jpeg_src_buf->dec_param.comp_size[i]);
buf_state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegdec_put_buf(jpeg);
pm_runtime_put(ctx->jpeg->dev);
clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
jpeg->hw_state = MTK_JPEG_HW_IDLE;
wake_up(&master_jpeg->hw_wq);
atomic_inc(&master_jpeg->hw_rdy);
return IRQ_HANDLED;
}
static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
{
struct platform_device *pdev = dev->plat_dev;
int ret;
dev->jpegdec_irq = platform_get_irq(pdev, 0);
if (dev->jpegdec_irq < 0)
return dev->jpegdec_irq;
ret = devm_request_irq(&pdev->dev,
dev->jpegdec_irq,
mtk_jpegdec_hw_irq_handler,
0,
pdev->name, dev);
if (ret) {
dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
dev->jpegdec_irq, ret);
return ret;
}
return 0;
}
static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
{
struct mtk_jpegdec_clk *jpegdec_clk;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegdec_comp_dev *dev;
int ret, i;
struct device *decs = &pdev->dev;
if (!decs->parent)
return -EPROBE_DEFER;
master_dev = dev_get_drvdata(decs->parent);
if (!master_dev)
return -EPROBE_DEFER;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->plat_dev = pdev;
dev->dev = &pdev->dev;
spin_lock_init(&dev->hw_lock);
dev->hw_state = MTK_JPEG_HW_IDLE;
INIT_DELAYED_WORK(&dev->job_timeout_work,
mtk_jpegdec_timeout_work);
jpegdec_clk = &dev->jdec_clk;
jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
&jpegdec_clk->clks);
if (jpegdec_clk->clk_num < 0)
return dev_err_probe(&pdev->dev,
jpegdec_clk->clk_num,
"Failed to get jpegdec clock count.\n");
dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dev->reg_base))
return PTR_ERR(dev->reg_base);
ret = mtk_jpegdec_hw_init_irq(dev);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to register JPEGDEC irq handler.\n");
i = atomic_add_return(1, &master_dev->hw_index) - 1;
master_dev->dec_hw_dev[i] = dev;
master_dev->reg_decbase[i] = dev->reg_base;
dev->master_dev = master_dev;
platform_set_drvdata(pdev, dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static struct platform_driver mtk_jpegdec_hw_driver = {
.probe = mtk_jpegdec_hw_probe,
.driver = {
.name = "mtk-jpegdec-hw",
.of_match_table = mtk_jpegdec_hw_ids,
},
};
module_platform_driver(mtk_jpegdec_hw_driver);
MODULE_DESCRIPTION("MediaTek JPEG decode HW driver");
MODULE_LICENSE("GPL");
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
+82
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@@ -0,0 +1,82 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
* Xia Jiang <xia.jiang@mediatek.com>
*/
#ifndef _MTK_JPEG_DEC_HW_H
#define _MTK_JPEG_DEC_HW_H
#include <media/videobuf2-core.h>
#include "mtk_jpeg_dec_reg.h"
#define MTK_JPEG_COMP_MAX 3
enum {
MTK_JPEG_DEC_RESULT_EOF_DONE = 0,
MTK_JPEG_DEC_RESULT_PAUSE = 1,
MTK_JPEG_DEC_RESULT_UNDERFLOW = 2,
MTK_JPEG_DEC_RESULT_OVERFLOW = 3,
MTK_JPEG_DEC_RESULT_ERROR_BS = 4,
MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN = 6
};
struct mtk_jpeg_dec_param {
u32 pic_w;
u32 pic_h;
u32 dec_w;
u32 dec_h;
u32 src_color;
u32 dst_fourcc;
u32 mcu_w;
u32 mcu_h;
u32 total_mcu;
u32 unit_num;
u32 comp_num;
u32 comp_id[MTK_JPEG_COMP_MAX];
u32 sampling_w[MTK_JPEG_COMP_MAX];
u32 sampling_h[MTK_JPEG_COMP_MAX];
u32 qtbl_num[MTK_JPEG_COMP_MAX];
u32 blk_num;
u32 blk_comp[MTK_JPEG_COMP_MAX];
u32 membership;
u32 dma_mcu;
u32 dma_group;
u32 dma_last_mcu;
u32 img_stride[MTK_JPEG_COMP_MAX];
u32 mem_stride[MTK_JPEG_COMP_MAX];
u32 comp_w[MTK_JPEG_COMP_MAX];
u32 comp_size[MTK_JPEG_COMP_MAX];
u32 y_size;
u32 uv_size;
u32 dec_size;
u8 uv_brz_w;
};
struct mtk_jpeg_bs {
dma_addr_t str_addr;
dma_addr_t end_addr;
size_t size;
};
struct mtk_jpeg_fb {
dma_addr_t plane_addr[MTK_JPEG_COMP_MAX];
size_t size;
};
int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base);
u32 mtk_jpeg_dec_enum_result(u32 irq_result);
void mtk_jpeg_dec_set_config(void __iomem *base,
bool support_34bits,
struct mtk_jpeg_dec_param *cfg,
u32 bitstream_size,
struct mtk_jpeg_bs *bs,
struct mtk_jpeg_fb *fb);
void mtk_jpeg_dec_reset(void __iomem *dec_reg_base);
void mtk_jpeg_dec_start(void __iomem *dec_reg_base);
#endif /* _MTK_JPEG_HW_H */
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_parse.c
+147
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@@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*/
#include <linux/kernel.h>
#include <linux/videodev2.h>
#include <media/jpeg.h>
#include "mtk_jpeg_dec_parse.h"
struct mtk_jpeg_stream {
u8 *addr;
u32 size;
u32 curr;
};
static int read_byte(struct mtk_jpeg_stream *stream)
{
if (stream->curr >= stream->size)
return -1;
return stream->addr[stream->curr++];
}
static int read_word_be(struct mtk_jpeg_stream *stream, u32 *word)
{
u32 temp;
int byte;
byte = read_byte(stream);
if (byte == -1)
return -1;
temp = byte << 8;
byte = read_byte(stream);
if (byte == -1)
return -1;
*word = (u32)byte | temp;
return 0;
}
static void read_skip(struct mtk_jpeg_stream *stream, long len)
{
if (len <= 0)
return;
while (len--)
read_byte(stream);
}
static bool mtk_jpeg_do_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va,
u32 src_size)
{
bool notfound = true;
struct mtk_jpeg_stream stream;
stream.addr = src_addr_va;
stream.size = src_size;
stream.curr = 0;
while (notfound) {
int i, length, byte;
u32 word;
byte = read_byte(&stream);
if (byte == -1)
return false;
if (byte != 0xff)
continue;
do
byte = read_byte(&stream);
while (byte == 0xff);
if (byte == -1)
return false;
if (byte == 0)
continue;
length = 0;
switch (byte) {
case JPEG_MARKER_SOF0:
/* length */
if (read_word_be(&stream, &word))
break;
/* precision */
if (read_byte(&stream) == -1)
break;
if (read_word_be(&stream, &word))
break;
param->pic_h = word;
if (read_word_be(&stream, &word))
break;
param->pic_w = word;
param->comp_num = read_byte(&stream);
if (param->comp_num != 1 && param->comp_num != 3)
break;
for (i = 0; i < param->comp_num; i++) {
param->comp_id[i] = read_byte(&stream);
if (param->comp_id[i] == -1)
break;
/* sampling */
byte = read_byte(&stream);
if (byte == -1)
break;
param->sampling_w[i] = (byte >> 4) & 0x0F;
param->sampling_h[i] = byte & 0x0F;
param->qtbl_num[i] = read_byte(&stream);
if (param->qtbl_num[i] == -1)
break;
}
notfound = !(i == param->comp_num);
break;
case JPEG_MARKER_RST ... JPEG_MARKER_RST + 7:
case JPEG_MARKER_SOI:
case JPEG_MARKER_EOI:
case JPEG_MARKER_TEM:
break;
default:
if (read_word_be(&stream, &word))
break;
length = (long)word - 2;
read_skip(&stream, length);
break;
}
}
return !notfound;
}
bool mtk_jpeg_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va,
u32 src_size)
{
if (!mtk_jpeg_do_parse(param, src_addr_va, src_size))
return false;
if (mtk_jpeg_dec_fill_param(param))
return false;
return true;
}
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_parse.h
+17
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@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*/
#ifndef _MTK_JPEG_PARSE_H
#define _MTK_JPEG_PARSE_H
#include "mtk_jpeg_dec_hw.h"
bool mtk_jpeg_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va,
u32 src_size);
#endif /* _MTK_JPEG_PARSE_H */
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
+58
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@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*/
#ifndef _MTK_JPEG_REG_H
#define _MTK_JPEG_REG_H
#define MTK_JPEG_BLOCK_MAX 10
#define MTK_JPEG_DCTSIZE 8
#define BIT_INQST_MASK_ERROR_BS 0x20
#define BIT_INQST_MASK_PAUSE 0x10
#define BIT_INQST_MASK_OVERFLOW 0x04
#define BIT_INQST_MASK_UNDERFLOW 0x02
#define BIT_INQST_MASK_EOF 0x01
#define BIT_INQST_MASK_ALLIRQ 0x37
#define JPGDEC_REG_RESET 0x0090
#define JPGDEC_REG_BRZ_FACTOR 0x00f8
#define JPGDEC_REG_DU_NUM 0x00fc
#define JPGDEC_REG_DEST_ADDR0_Y 0x0140
#define JPGDEC_REG_DEST_ADDR0_U 0x0144
#define JPGDEC_REG_DEST_ADDR0_V 0x0148
#define JPGDEC_REG_DEST_ADDR1_Y 0x014c
#define JPGDEC_REG_DEST_ADDR1_U 0x0150
#define JPGDEC_REG_DEST_ADDR1_V 0x0154
#define JPGDEC_REG_STRIDE_Y 0x0158
#define JPGDEC_REG_STRIDE_UV 0x015c
#define JPGDEC_REG_IMG_STRIDE_Y 0x0160
#define JPGDEC_REG_IMG_STRIDE_UV 0x0164
#define JPGDEC_REG_WDMA_CTRL 0x016c
#define JPGDEC_REG_PAUSE_MCU_NUM 0x0170
#define JPGDEC_REG_OPERATION_MODE 0x017c
#define JPGDEC_REG_FILE_ADDR 0x0200
#define JPGDEC_REG_COMP_ID 0x020c
#define JPGDEC_REG_TOTAL_MCU_NUM 0x0210
#define JPGDEC_REG_COMP0_DATA_UNIT_NUM 0x0224
#define JPGDEC_REG_DU_CTRL 0x023c
#define JPGDEC_REG_TRIG 0x0240
#define JPGDEC_REG_FILE_BRP 0x0248
#define JPGDEC_REG_FILE_TOTAL_SIZE 0x024c
#define JPGDEC_REG_QT_ID 0x0270
#define JPGDEC_REG_INTERRUPT_STATUS 0x0274
#define JPGDEC_REG_STATUS 0x0278
#define JPGDEC_REG_BIT_STREAM_SIZE 0x0344
#define JPGDEC_REG_DEST_ADDR0_Y_EXT 0x0360
#define JPGDEC_REG_DEST_ADDR0_U_EXT 0x0364
#define JPGDEC_REG_DEST_ADDR0_V_EXT 0x0368
#define JPGDEC_REG_DEST_ADDR1_Y_EXT 0x036c
#define JPGDEC_REG_DEST_ADDR1_U_EXT 0x0370
#define JPGDEC_REG_DEST_ADDR1_V_EXT 0x0374
#define JPGDEC_REG_FILE_ADDR_EXT 0x0378
#define JPGDEC_REG_FILE_BRP_EXT 0x037c
#endif /* _MTK_JPEG_REG_H */
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+406
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@@ -0,0 +1,406 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Xia Jiang <xia.jiang@mediatek.com>
*
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <media/media-device.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-event.h>
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_enc_hw.h"
static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] = {
{.quality_param = 34, .hardware_value = JPEG_ENC_QUALITY_Q34},
{.quality_param = 39, .hardware_value = JPEG_ENC_QUALITY_Q39},
{.quality_param = 48, .hardware_value = JPEG_ENC_QUALITY_Q48},
{.quality_param = 60, .hardware_value = JPEG_ENC_QUALITY_Q60},
{.quality_param = 64, .hardware_value = JPEG_ENC_QUALITY_Q64},
{.quality_param = 68, .hardware_value = JPEG_ENC_QUALITY_Q68},
{.quality_param = 74, .hardware_value = JPEG_ENC_QUALITY_Q74},
{.quality_param = 80, .hardware_value = JPEG_ENC_QUALITY_Q80},
{.quality_param = 82, .hardware_value = JPEG_ENC_QUALITY_Q82},
{.quality_param = 84, .hardware_value = JPEG_ENC_QUALITY_Q84},
{.quality_param = 87, .hardware_value = JPEG_ENC_QUALITY_Q87},
{.quality_param = 90, .hardware_value = JPEG_ENC_QUALITY_Q90},
{.quality_param = 92, .hardware_value = JPEG_ENC_QUALITY_Q92},
{.quality_param = 95, .hardware_value = JPEG_ENC_QUALITY_Q95},
{.quality_param = 97, .hardware_value = JPEG_ENC_QUALITY_Q97},
};
static const struct of_device_id mtk_jpegenc_drv_ids[] = {
{
.compatible = "mediatek,mt8195-jpgenc-hw",
},
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
void mtk_jpeg_enc_reset(void __iomem *base)
{
writel(0, base + JPEG_ENC_RSTB);
writel(JPEG_ENC_RESET_BIT, base + JPEG_ENC_RSTB);
writel(0, base + JPEG_ENC_CODEC_SEL);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_reset);
u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit)
{
return (readl(base + JPEG_ENC_DMA_ADDR0) << ((support_34bit) ? 2 : 0)) -
readl(base + JPEG_ENC_DST_ADDR0);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_get_file_size);
void mtk_jpeg_enc_start(void __iomem *base)
{
u32 value;
value = readl(base + JPEG_ENC_CTRL);
value |= JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT;
writel(value, base + JPEG_ENC_CTRL);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_start);
void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *src_buf)
{
int i;
dma_addr_t dma_addr;
u32 addr_ext;
bool support_34bit = ctx->jpeg->variant->support_34bit;
for (i = 0; i < src_buf->num_planes; i++) {
dma_addr = vb2_dma_contig_plane_dma_addr(src_buf, i) +
src_buf->planes[i].data_offset;
if (i == 0)
writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_LUMA_ADDR);
else
writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_CHROMA_ADDR);
if (support_34bit) {
addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr));
if (i == 0)
writel(addr_ext, base + JPEG_ENC_SRC_LUMA_ADDR_EXT);
else
writel(addr_ext, base + JPEG_ENC_SRC_CHRO_ADDR_EXT);
}
}
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_src);
void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *dst_buf)
{
dma_addr_t dma_addr;
size_t size;
u32 dma_addr_offset;
u32 dma_addr_offsetmask;
u32 addr_ext;
bool support_34bit = ctx->jpeg->variant->support_34bit;
dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
dma_addr_offset = ctx->enable_exif ? MTK_JPEG_MAX_EXIF_SIZE : 0;
dma_addr_offsetmask = dma_addr & JPEG_ENC_DST_ADDR_OFFSET_MASK;
size = vb2_plane_size(dst_buf, 0);
writel(dma_addr_offset & ~0xf, base + JPEG_ENC_OFFSET_ADDR);
writel(dma_addr_offsetmask & 0xf, base + JPEG_ENC_BYTE_OFFSET_MASK);
writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0);
writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0);
if (support_34bit) {
addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr));
writel(addr_ext, base + JPEG_ENC_DEST_ADDR0_EXT);
writel(addr_ext + size, base + JPEG_ENC_STALL_ADDR0_EXT);
}
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_dst);
void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx, void __iomem *base)
{
u32 value;
u32 width = ctx->out_q.enc_crop_rect.width;
u32 height = ctx->out_q.enc_crop_rect.height;
u32 enc_format = ctx->out_q.fmt->fourcc;
u32 bytesperline = ctx->out_q.pix_mp.plane_fmt[0].bytesperline;
u32 blk_num;
u32 img_stride;
u32 mem_stride;
u32 i, enc_quality;
u32 nr_enc_quality = ARRAY_SIZE(mtk_jpeg_enc_quality);
value = width << 16 | height;
writel(value, base + JPEG_ENC_IMG_SIZE);
if (enc_format == V4L2_PIX_FMT_NV12M ||
enc_format == V4L2_PIX_FMT_NV21M)
/*
* Total 8 x 8 block number of luma and chroma.
* The number of blocks is counted from 0.
*/
blk_num = DIV_ROUND_UP(width, 16) *
DIV_ROUND_UP(height, 16) * 6 - 1;
else
blk_num = DIV_ROUND_UP(width, 16) *
DIV_ROUND_UP(height, 8) * 4 - 1;
writel(blk_num, base + JPEG_ENC_BLK_NUM);
if (enc_format == V4L2_PIX_FMT_NV12M ||
enc_format == V4L2_PIX_FMT_NV21M) {
/* 4:2:0 */
img_stride = round_up(width, 16);
mem_stride = bytesperline;
} else {
/* 4:2:2 */
img_stride = round_up(width * 2, 32);
mem_stride = img_stride;
}
writel(img_stride, base + JPEG_ENC_IMG_STRIDE);
writel(mem_stride, base + JPEG_ENC_STRIDE);
enc_quality = mtk_jpeg_enc_quality[nr_enc_quality - 1].hardware_value;
for (i = 0; i < nr_enc_quality; i++) {
if (ctx->enc_quality <= mtk_jpeg_enc_quality[i].quality_param) {
enc_quality = mtk_jpeg_enc_quality[i].hardware_value;
break;
}
}
writel(enc_quality, base + JPEG_ENC_QUALITY);
value = readl(base + JPEG_ENC_CTRL);
value &= ~JPEG_ENC_CTRL_YUV_FORMAT_MASK;
value |= (ctx->out_q.fmt->hw_format & 3) << 3;
if (ctx->enable_exif)
value |= JPEG_ENC_CTRL_FILE_FORMAT_BIT;
else
value &= ~JPEG_ENC_CTRL_FILE_FORMAT_BIT;
if (ctx->restart_interval)
value |= JPEG_ENC_CTRL_RESTART_EN_BIT;
else
value &= ~JPEG_ENC_CTRL_RESTART_EN_BIT;
writel(value, base + JPEG_ENC_CTRL);
writel(ctx->restart_interval, base + JPEG_ENC_RST_MCU_NUM);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_params);
static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
{
struct mtk_jpeg_ctx *ctx;
struct vb2_v4l2_buffer *dst_buffer;
struct list_head *temp_entry;
struct list_head *pos = NULL;
struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
unsigned long flags;
ctx = jpeg->hw_param.curr_ctx;
if (!ctx) {
dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
return;
}
dst_buffer = jpeg->hw_param.dst_buffer;
if (!dst_buffer) {
dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
return;
}
dst_done_buf = container_of(dst_buffer,
struct mtk_jpeg_src_buf, b);
spin_lock_irqsave(&ctx->done_queue_lock, flags);
list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
while (!list_empty(&ctx->dst_done_queue) &&
(pos != &ctx->dst_done_queue)) {
list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
tmp_dst_done_buf = list_entry(pos,
struct mtk_jpeg_src_buf,
list);
if (tmp_dst_done_buf->frame_num ==
ctx->last_done_frame_num) {
list_del(&tmp_dst_done_buf->list);
v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
VB2_BUF_STATE_DONE);
ctx->last_done_frame_num++;
}
}
}
spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
}
static void mtk_jpegenc_timeout_work(struct work_struct *work)
{
struct delayed_work *dly_work = to_delayed_work(work);
struct mtk_jpegenc_comp_dev *cjpeg =
container_of(dly_work,
struct mtk_jpegenc_comp_dev,
job_timeout_work);
struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = cjpeg->hw_param.src_buffer;
dst_buf = cjpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
mtk_jpeg_enc_reset(cjpeg->reg_base);
clk_disable_unprepare(cjpeg->venc_clk.clks->clk);
pm_runtime_put(cjpeg->dev);
cjpeg->hw_state = MTK_JPEG_HW_IDLE;
atomic_inc(&master_jpeg->hw_rdy);
wake_up(&master_jpeg->hw_wq);
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegenc_put_buf(cjpeg);
}
static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
{
struct vb2_v4l2_buffer *src_buf, *dst_buf;
enum vb2_buffer_state buf_state;
struct mtk_jpeg_ctx *ctx;
u32 result_size;
u32 irq_status;
struct mtk_jpegenc_comp_dev *jpeg = priv;
struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
cancel_delayed_work(&jpeg->job_timeout_work);
ctx = jpeg->hw_param.curr_ctx;
src_buf = jpeg->hw_param.src_buffer;
dst_buf = jpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
irq_status = readl(jpeg->reg_base + JPEG_ENC_INT_STS) &
JPEG_ENC_INT_STATUS_MASK_ALLIRQ;
if (irq_status)
writel(0, jpeg->reg_base + JPEG_ENC_INT_STS);
if (!(irq_status & JPEG_ENC_INT_STATUS_DONE))
dev_warn(jpeg->dev, "Jpg Enc occurs unknown Err.");
result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,
ctx->jpeg->variant->support_34bit);
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
buf_state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegenc_put_buf(jpeg);
pm_runtime_put(ctx->jpeg->dev);
clk_disable_unprepare(jpeg->venc_clk.clks->clk);
jpeg->hw_state = MTK_JPEG_HW_IDLE;
wake_up(&master_jpeg->hw_wq);
atomic_inc(&master_jpeg->hw_rdy);
return IRQ_HANDLED;
}
static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev)
{
struct platform_device *pdev = dev->plat_dev;
int ret;
dev->jpegenc_irq = platform_get_irq(pdev, 0);
if (dev->jpegenc_irq < 0)
return dev->jpegenc_irq;
ret = devm_request_irq(&pdev->dev,
dev->jpegenc_irq,
mtk_jpegenc_hw_irq_handler,
0,
pdev->name, dev);
if (ret) {
dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
dev->jpegenc_irq, ret);
return ret;
}
return 0;
}
static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
{
struct mtk_jpegenc_clk *jpegenc_clk;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegenc_comp_dev *dev;
int ret, i;
struct device *decs = &pdev->dev;
if (!decs->parent)
return -EPROBE_DEFER;
master_dev = dev_get_drvdata(decs->parent);
if (!master_dev)
return -EPROBE_DEFER;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->plat_dev = pdev;
dev->dev = &pdev->dev;
spin_lock_init(&dev->hw_lock);
dev->hw_state = MTK_JPEG_HW_IDLE;
INIT_DELAYED_WORK(&dev->job_timeout_work,
mtk_jpegenc_timeout_work);
jpegenc_clk = &dev->venc_clk;
jpegenc_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
&jpegenc_clk->clks);
if (jpegenc_clk->clk_num < 0)
return dev_err_probe(&pdev->dev, jpegenc_clk->clk_num,
"Failed to get jpegenc clock count\n");
dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dev->reg_base))
return PTR_ERR(dev->reg_base);
ret = mtk_jpegenc_hw_init_irq(dev);
if (ret)
return ret;
i = atomic_add_return(1, &master_dev->hw_index) - 1;
master_dev->enc_hw_dev[i] = dev;
master_dev->reg_encbase[i] = dev->reg_base;
dev->master_dev = master_dev;
platform_set_drvdata(pdev, dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static struct platform_driver mtk_jpegenc_hw_driver = {
.probe = mtk_jpegenc_hw_probe,
.driver = {
.name = "mtk-jpegenc-hw",
.of_match_table = mtk_jpegenc_drv_ids,
},
};
module_platform_driver(mtk_jpegenc_hw_driver);
MODULE_DESCRIPTION("MediaTek JPEG encode HW driver");
MODULE_LICENSE("GPL");
linux-7.2.3/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
+96
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@@ -0,0 +1,96 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Xia Jiang <xia.jiang@mediatek.com>
*
*/
#ifndef _MTK_JPEG_ENC_HW_H
#define _MTK_JPEG_ENC_HW_H
#include <media/videobuf2-core.h>
#include "mtk_jpeg_core.h"
#define JPEG_ENC_INT_STATUS_DONE BIT(0)
#define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
#define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
#define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
#define JPEG_ENC_CTRL_RESTART_EN_BIT BIT(10)
#define JPEG_ENC_CTRL_FILE_FORMAT_BIT BIT(5)
#define JPEG_ENC_CTRL_INT_EN_BIT BIT(2)
#define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
#define JPEG_ENC_RESET_BIT BIT(0)
#define JPEG_ENC_YUV_FORMAT_YUYV 0
#define JPEG_ENC_YUV_FORMAT_YVYU 1
#define JPEG_ENC_YUV_FORMAT_NV12 2
#define JEPG_ENC_YUV_FORMAT_NV21 3
#define JPEG_ENC_QUALITY_Q60 0x0
#define JPEG_ENC_QUALITY_Q80 0x1
#define JPEG_ENC_QUALITY_Q90 0x2
#define JPEG_ENC_QUALITY_Q95 0x3
#define JPEG_ENC_QUALITY_Q39 0x4
#define JPEG_ENC_QUALITY_Q68 0x5
#define JPEG_ENC_QUALITY_Q84 0x6
#define JPEG_ENC_QUALITY_Q92 0x7
#define JPEG_ENC_QUALITY_Q48 0x8
#define JPEG_ENC_QUALITY_Q74 0xa
#define JPEG_ENC_QUALITY_Q87 0xb
#define JPEG_ENC_QUALITY_Q34 0xc
#define JPEG_ENC_QUALITY_Q64 0xe
#define JPEG_ENC_QUALITY_Q82 0xf
#define JPEG_ENC_QUALITY_Q97 0x10
#define JPEG_ENC_RSTB 0x100
#define JPEG_ENC_CTRL 0x104
#define JPEG_ENC_QUALITY 0x108
#define JPEG_ENC_BLK_NUM 0x10C
#define JPEG_ENC_BLK_CNT 0x110
#define JPEG_ENC_INT_STS 0x11c
#define JPEG_ENC_DST_ADDR0 0x120
#define JPEG_ENC_DMA_ADDR0 0x124
#define JPEG_ENC_STALL_ADDR0 0x128
#define JPEG_ENC_OFFSET_ADDR 0x138
#define JPEG_ENC_RST_MCU_NUM 0x150
#define JPEG_ENC_IMG_SIZE 0x154
#define JPEG_ENC_DEBUG_INFO0 0x160
#define JPEG_ENC_DEBUG_INFO1 0x164
#define JPEG_ENC_TOTAL_CYCLE 0x168
#define JPEG_ENC_BYTE_OFFSET_MASK 0x16c
#define JPEG_ENC_SRC_LUMA_ADDR 0x170
#define JPEG_ENC_SRC_CHROMA_ADDR 0x174
#define JPEG_ENC_STRIDE 0x178
#define JPEG_ENC_IMG_STRIDE 0x17c
#define JPEG_ENC_DCM_CTRL 0x300
#define JPEG_ENC_CODEC_SEL 0x314
#define JPEG_ENC_ULTRA_THRES 0x318
#define JPEG_ENC_SRC_LUMA_ADDR_EXT 0x584
#define JPEG_ENC_SRC_CHRO_ADDR_EXT 0x588
#define JPEG_ENC_Q_TBL_ADDR_EXT 0x58C
#define JPEG_ENC_DEST_ADDR0_EXT 0x590
#define JPEG_ENC_STALL_ADDR0_EXT 0x594
/**
* struct mtk_jpeg_enc_qlt - JPEG encoder quality data
* @quality_param: quality value
* @hardware_value: hardware value of quality
*/
struct mtk_jpeg_enc_qlt {
u8 quality_param;
u8 hardware_value;
};
void mtk_jpeg_enc_reset(void __iomem *base);
u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit);
void mtk_jpeg_enc_start(void __iomem *enc_reg_base);
void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *src_buf);
void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *dst_buf);
void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx, void __iomem *base);
#endif /* _MTK_JPEG_ENC_HW_H */