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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/media/platform/ti/davinci/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
config VIDEO_DAVINCI_VPIF_DISPLAY
tristate "TI DaVinci VPIF V4L2-Display driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF2_DMA_CONTIG
select VIDEO_ADV7343 if MEDIA_SUBDRV_AUTOSELECT
select VIDEO_THS7303 if MEDIA_SUBDRV_AUTOSELECT
help
Enables Davinci VPIF module used for display devices.
This module is used for display on TI DM6467/DA850/OMAPL138
SoCs.
To compile this driver as a module, choose M here. There will
be two modules called vpif.ko and vpif_display.ko
config VIDEO_DAVINCI_VPIF_CAPTURE
tristate "TI DaVinci VPIF video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF2_DMA_CONTIG
select V4L2_FWNODE
help
Enables Davinci VPIF module used for capture devices.
This module is used for capture on TI DM6467/DA850/OMAPL138
SoCs.
To compile this driver as a module, choose M here. There will
be two modules called vpif.ko and vpif_capture.ko
linux-7.2.3/drivers/media/platform/ti/davinci/Makefile
+9
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# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the davinci video device drivers.
#
#VPIF Display driver
obj-$(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY) += vpif.o vpif_display.o
#VPIF Capture driver
obj-$(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE) += vpif.o vpif_capture.o
linux-7.2.3/drivers/media/platform/ti/davinci/vpif.c
+609
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/*
* vpif - Video Port Interface driver
* VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
* that receiving video byte stream and two channels(2, 3) for video output.
* The hardware supports SDTV, HDTV formats, raw data capture.
* Currently, the driver supports NTSC and PAL standards.
*
* Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed .as is. WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/of_graph.h>
#include "vpif.h"
MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
MODULE_LICENSE("GPL");
#define VPIF_DRIVER_NAME "vpif"
MODULE_ALIAS("platform:" VPIF_DRIVER_NAME);
#define VPIF_CH0_MAX_MODES 22
#define VPIF_CH1_MAX_MODES 2
#define VPIF_CH2_MAX_MODES 15
#define VPIF_CH3_MAX_MODES 2
struct vpif_data {
struct platform_device *capture;
struct platform_device *display;
};
DEFINE_SPINLOCK(vpif_lock);
EXPORT_SYMBOL_GPL(vpif_lock);
void __iomem *vpif_base;
EXPORT_SYMBOL_GPL(vpif_base);
/*
* vpif_ch_params: video standard configuration parameters for vpif
*
* The table must include all presets from supported subdevices.
*/
const struct vpif_channel_config_params vpif_ch_params[] = {
/* HDTV formats */
{
.name = "480p59_94",
.width = 720,
.height = 480,
.frm_fmt = 1,
.ycmux_mode = 0,
.eav2sav = 138-8,
.sav2eav = 720,
.l1 = 1,
.l3 = 43,
.l5 = 523,
.vsize = 525,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
},
{
.name = "576p50",
.width = 720,
.height = 576,
.frm_fmt = 1,
.ycmux_mode = 0,
.eav2sav = 144-8,
.sav2eav = 720,
.l1 = 1,
.l3 = 45,
.l5 = 621,
.vsize = 625,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_720X576P50,
},
{
.name = "720p50",
.width = 1280,
.height = 720,
.frm_fmt = 1,
.ycmux_mode = 0,
.eav2sav = 700-8,
.sav2eav = 1280,
.l1 = 1,
.l3 = 26,
.l5 = 746,
.vsize = 750,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_1280X720P50,
},
{
.name = "720p60",
.width = 1280,
.height = 720,
.frm_fmt = 1,
.ycmux_mode = 0,
.eav2sav = 370 - 8,
.sav2eav = 1280,
.l1 = 1,
.l3 = 26,
.l5 = 746,
.vsize = 750,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_1280X720P60,
},
{
.name = "1080I50",
.width = 1920,
.height = 1080,
.frm_fmt = 0,
.ycmux_mode = 0,
.eav2sav = 720 - 8,
.sav2eav = 1920,
.l1 = 1,
.l3 = 21,
.l5 = 561,
.l7 = 563,
.l9 = 584,
.l11 = 1124,
.vsize = 1125,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
},
{
.name = "1080I60",
.width = 1920,
.height = 1080,
.frm_fmt = 0,
.ycmux_mode = 0,
.eav2sav = 280 - 8,
.sav2eav = 1920,
.l1 = 1,
.l3 = 21,
.l5 = 561,
.l7 = 563,
.l9 = 584,
.l11 = 1124,
.vsize = 1125,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
},
{
.name = "1080p60",
.width = 1920,
.height = 1080,
.frm_fmt = 1,
.ycmux_mode = 0,
.eav2sav = 280 - 8,
.sav2eav = 1920,
.l1 = 1,
.l3 = 42,
.l5 = 1122,
.vsize = 1125,
.capture_format = 0,
.vbi_supported = 0,
.hd_sd = 1,
.dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
},
/* SDTV formats */
{
.name = "NTSC_M",
.width = 720,
.height = 480,
.frm_fmt = 0,
.ycmux_mode = 1,
.eav2sav = 268,
.sav2eav = 1440,
.l1 = 1,
.l3 = 23,
.l5 = 263,
.l7 = 266,
.l9 = 286,
.l11 = 525,
.vsize = 525,
.capture_format = 0,
.vbi_supported = 1,
.hd_sd = 0,
.stdid = V4L2_STD_525_60,
},
{
.name = "PAL_BDGHIK",
.width = 720,
.height = 576,
.frm_fmt = 0,
.ycmux_mode = 1,
.eav2sav = 280,
.sav2eav = 1440,
.l1 = 1,
.l3 = 23,
.l5 = 311,
.l7 = 313,
.l9 = 336,
.l11 = 624,
.vsize = 625,
.capture_format = 0,
.vbi_supported = 1,
.hd_sd = 0,
.stdid = V4L2_STD_625_50,
},
};
EXPORT_SYMBOL_GPL(vpif_ch_params);
const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);
EXPORT_SYMBOL_GPL(vpif_ch_params_count);
static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
{
if (val)
vpif_set_bit(reg, bit);
else
vpif_clr_bit(reg, bit);
}
/* This structure is used to keep track of VPIF size register's offsets */
struct vpif_registers {
u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
u32 vanc1_size, width_mask, len_mask;
u8 max_modes;
};
static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
/* Channel0 */
{
VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
VPIF_CH0_MAX_MODES,
},
/* Channel1 */
{
VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
VPIF_CH1_MAX_MODES,
},
/* Channel2 */
{
VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
VPIF_CH2_MAX_MODES
},
/* Channel3 */
{
VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
VPIF_CH3_MAX_MODES
},
};
/* vpif_set_mode_info:
* This function is used to set horizontal and vertical config parameters
* As per the standard in the channel, configure the values of L1, L3,
* L5, L7 L9, L11 in VPIF Register , also write width and height
*/
static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
u8 channel_id, u8 config_channel_id)
{
u32 value;
value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
regw(value, vpifregs[channel_id].h_cfg);
value = (config->l1 & vpifregs[config_channel_id].len_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->l3 & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg_00);
value = (config->l5 & vpifregs[config_channel_id].len_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->l7 & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg_01);
value = (config->l9 & vpifregs[config_channel_id].len_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->l11 & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg_02);
value = (config->vsize & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg);
}
/* config_vpif_params
* Function to set the parameters of a channel
* Mainly modifies the channel ciontrol register
* It sets frame format, yc mux mode
*/
static void config_vpif_params(struct vpif_params *vpifparams,
u8 channel_id, u8 found)
{
const struct vpif_channel_config_params *config = &vpifparams->std_info;
u32 value, ch_nip, reg;
u8 start, end;
int i;
start = channel_id;
end = channel_id + found;
for (i = start; i < end; i++) {
reg = vpifregs[i].ch_ctrl;
if (channel_id < 2)
ch_nip = VPIF_CAPTURE_CH_NIP;
else
ch_nip = VPIF_DISPLAY_CH_NIP;
vpif_wr_bit(reg, ch_nip, config->frm_fmt);
vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
vpifparams->video_params.storage_mode);
/* Set raster scanning SDR Format */
vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
if (channel_id > 1) /* Set the Pixel enable bit */
vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
else if (config->capture_format) {
/* Set the polarity of various pins */
vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
vpifparams->iface.fid_pol);
vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
vpifparams->iface.vd_pol);
vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
vpifparams->iface.hd_pol);
value = regr(reg);
/* Set data width */
value &= ~(0x3u <<
VPIF_CH_DATA_WIDTH_BIT);
value |= ((vpifparams->params.data_sz) <<
VPIF_CH_DATA_WIDTH_BIT);
regw(value, reg);
}
/* Write the pitch in the driver */
regw((vpifparams->video_params.hpitch),
vpifregs[i].line_offset);
}
}
/* vpif_set_video_params
* This function is used to set video parameters in VPIF register
*/
int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
{
const struct vpif_channel_config_params *config = &vpifparams->std_info;
int found = 1;
vpif_set_mode_info(config, channel_id, channel_id);
if (!config->ycmux_mode) {
/* YC are on separate channels (HDTV formats) */
vpif_set_mode_info(config, channel_id + 1, channel_id);
found = 2;
}
config_vpif_params(vpifparams, channel_id, found);
regw(0x80, VPIF_REQ_SIZE);
regw(0x01, VPIF_EMULATION_CTRL);
return found;
}
EXPORT_SYMBOL(vpif_set_video_params);
void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
u8 channel_id)
{
u32 value;
value = 0x3F8 & (vbiparams->hstart0);
value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
regw(value, vpifregs[channel_id].vanc0_strt);
value = 0x3F8 & (vbiparams->hstart1);
value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
regw(value, vpifregs[channel_id].vanc1_strt);
value = 0x3F8 & (vbiparams->hsize0);
value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
regw(value, vpifregs[channel_id].vanc0_size);
value = 0x3F8 & (vbiparams->hsize1);
value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
regw(value, vpifregs[channel_id].vanc1_size);
}
EXPORT_SYMBOL(vpif_set_vbi_display_params);
int vpif_channel_getfid(u8 channel_id)
{
return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
>> VPIF_CH_FID_SHIFT;
}
EXPORT_SYMBOL(vpif_channel_getfid);
static void vpif_pdev_release(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
kfree(pdev);
}
static int vpif_probe(struct platform_device *pdev)
{
static struct resource res_irq;
struct platform_device *pdev_capture, *pdev_display;
struct device_node *endpoint = NULL;
struct vpif_data *data;
int ret;
int irq;
vpif_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(vpif_base))
return PTR_ERR(vpif_base);
data = kzalloc_obj(*data);
if (!data)
return -ENOMEM;
platform_set_drvdata(pdev, data);
pm_runtime_enable(&pdev->dev);
pm_runtime_get(&pdev->dev);
/*
* If VPIF Node has endpoints, assume "new" DT support,
* where capture and display drivers don't have DT nodes
* so their devices need to be registered manually here
* for their legacy platform_drivers to work.
*/
endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 0, -1);
if (!endpoint)
return 0;
of_node_put(endpoint);
/*
* For DT platforms, manually create platform_devices for
* capture/display drivers.
*/
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto err_put_rpm;
}
res_irq = DEFINE_RES_IRQ_NAMED(irq, of_node_full_name(pdev->dev.of_node));
res_irq.flags |= irq_get_trigger_type(irq);
pdev_capture = kzalloc_obj(*pdev_capture);
if (!pdev_capture) {
ret = -ENOMEM;
goto err_put_rpm;
}
pdev_capture->name = "vpif_capture";
pdev_capture->id = -1;
pdev_capture->resource = &res_irq;
pdev_capture->num_resources = 1;
pdev_capture->dev.dma_mask = pdev->dev.dma_mask;
pdev_capture->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
pdev_capture->dev.parent = &pdev->dev;
pdev_capture->dev.release = vpif_pdev_release;
ret = platform_device_register(pdev_capture);
if (ret)
goto err_put_pdev_capture;
pdev_display = kzalloc_obj(*pdev_display);
if (!pdev_display) {
ret = -ENOMEM;
goto err_del_pdev_capture;
}
pdev_display->name = "vpif_display";
pdev_display->id = -1;
pdev_display->resource = &res_irq;
pdev_display->num_resources = 1;
pdev_display->dev.dma_mask = pdev->dev.dma_mask;
pdev_display->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
pdev_display->dev.parent = &pdev->dev;
pdev_display->dev.release = vpif_pdev_release;
ret = platform_device_register(pdev_display);
if (ret)
goto err_put_pdev_display;
data->capture = pdev_capture;
data->display = pdev_display;
return 0;
err_put_pdev_display:
platform_device_put(pdev_display);
err_del_pdev_capture:
platform_device_del(pdev_capture);
err_put_pdev_capture:
platform_device_put(pdev_capture);
err_put_rpm:
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
kfree(data);
return ret;
}
static void vpif_remove(struct platform_device *pdev)
{
struct vpif_data *data = platform_get_drvdata(pdev);
if (data->capture)
platform_device_unregister(data->capture);
if (data->display)
platform_device_unregister(data->display);
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
kfree(data);
}
#ifdef CONFIG_PM
static int vpif_suspend(struct device *dev)
{
pm_runtime_put(dev);
return 0;
}
static int vpif_resume(struct device *dev)
{
pm_runtime_get(dev);
return 0;
}
static const struct dev_pm_ops vpif_pm = {
.suspend = vpif_suspend,
.resume = vpif_resume,
};
#define vpif_pm_ops (&vpif_pm)
#else
#define vpif_pm_ops NULL
#endif
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id vpif_of_match[] = {
{ .compatible = "ti,da850-vpif", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, vpif_of_match);
#endif
static struct platform_driver vpif_driver = {
.driver = {
.of_match_table = of_match_ptr(vpif_of_match),
.name = VPIF_DRIVER_NAME,
.pm = vpif_pm_ops,
},
.remove = vpif_remove,
.probe = vpif_probe,
};
static void vpif_exit(void)
{
platform_driver_unregister(&vpif_driver);
}
static int __init vpif_init(void)
{
return platform_driver_register(&vpif_driver);
}
subsys_initcall(vpif_init);
module_exit(vpif_exit);
linux-7.2.3/drivers/media/platform/ti/davinci/vpif.h
+679
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@@ -0,0 +1,679 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* VPIF header file
*
* Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef VPIF_H
#define VPIF_H
#include <linux/io.h>
#include <linux/videodev2.h>
#include <media/davinci/vpif_types.h>
/* Maximum channel allowed */
#define VPIF_NUM_CHANNELS (4)
#define VPIF_CAPTURE_NUM_CHANNELS (2)
#define VPIF_DISPLAY_NUM_CHANNELS (2)
/* Macros to read/write registers */
extern void __iomem *vpif_base;
extern spinlock_t vpif_lock;
#define regr(reg) readl((reg) + vpif_base)
#define regw(value, reg) writel(value, (reg + vpif_base))
/* Register Address Offsets */
#define VPIF_PID (0x0000)
#define VPIF_CH0_CTRL (0x0004)
#define VPIF_CH1_CTRL (0x0008)
#define VPIF_CH2_CTRL (0x000C)
#define VPIF_CH3_CTRL (0x0010)
#define VPIF_INTEN (0x0020)
#define VPIF_INTEN_SET (0x0024)
#define VPIF_INTEN_CLR (0x0028)
#define VPIF_STATUS (0x002C)
#define VPIF_STATUS_CLR (0x0030)
#define VPIF_EMULATION_CTRL (0x0034)
#define VPIF_REQ_SIZE (0x0038)
#define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040)
#define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044)
#define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048)
#define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c)
#define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050)
#define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054)
#define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058)
#define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c)
#define VPIF_CH0_SP_CFG (0x0060)
#define VPIF_CH0_IMG_ADD_OFST (0x0064)
#define VPIF_CH0_HANC_ADD_OFST (0x0068)
#define VPIF_CH0_H_CFG (0x006c)
#define VPIF_CH0_V_CFG_00 (0x0070)
#define VPIF_CH0_V_CFG_01 (0x0074)
#define VPIF_CH0_V_CFG_02 (0x0078)
#define VPIF_CH0_V_CFG_03 (0x007c)
#define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080)
#define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084)
#define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088)
#define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c)
#define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090)
#define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094)
#define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098)
#define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c)
#define VPIF_CH1_SP_CFG (0x00a0)
#define VPIF_CH1_IMG_ADD_OFST (0x00a4)
#define VPIF_CH1_HANC_ADD_OFST (0x00a8)
#define VPIF_CH1_H_CFG (0x00ac)
#define VPIF_CH1_V_CFG_00 (0x00b0)
#define VPIF_CH1_V_CFG_01 (0x00b4)
#define VPIF_CH1_V_CFG_02 (0x00b8)
#define VPIF_CH1_V_CFG_03 (0x00bc)
#define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0)
#define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4)
#define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8)
#define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc)
#define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0)
#define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4)
#define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8)
#define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc)
#define VPIF_CH2_SP_CFG (0x00e0)
#define VPIF_CH2_IMG_ADD_OFST (0x00e4)
#define VPIF_CH2_HANC_ADD_OFST (0x00e8)
#define VPIF_CH2_H_CFG (0x00ec)
#define VPIF_CH2_V_CFG_00 (0x00f0)
#define VPIF_CH2_V_CFG_01 (0x00f4)
#define VPIF_CH2_V_CFG_02 (0x00f8)
#define VPIF_CH2_V_CFG_03 (0x00fc)
#define VPIF_CH2_HANC0_STRT (0x0100)
#define VPIF_CH2_HANC0_SIZE (0x0104)
#define VPIF_CH2_HANC1_STRT (0x0108)
#define VPIF_CH2_HANC1_SIZE (0x010c)
#define VPIF_CH2_VANC0_STRT (0x0110)
#define VPIF_CH2_VANC0_SIZE (0x0114)
#define VPIF_CH2_VANC1_STRT (0x0118)
#define VPIF_CH2_VANC1_SIZE (0x011c)
#define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140)
#define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144)
#define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148)
#define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c)
#define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150)
#define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154)
#define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158)
#define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c)
#define VPIF_CH3_SP_CFG (0x0160)
#define VPIF_CH3_IMG_ADD_OFST (0x0164)
#define VPIF_CH3_HANC_ADD_OFST (0x0168)
#define VPIF_CH3_H_CFG (0x016c)
#define VPIF_CH3_V_CFG_00 (0x0170)
#define VPIF_CH3_V_CFG_01 (0x0174)
#define VPIF_CH3_V_CFG_02 (0x0178)
#define VPIF_CH3_V_CFG_03 (0x017c)
#define VPIF_CH3_HANC0_STRT (0x0180)
#define VPIF_CH3_HANC0_SIZE (0x0184)
#define VPIF_CH3_HANC1_STRT (0x0188)
#define VPIF_CH3_HANC1_SIZE (0x018c)
#define VPIF_CH3_VANC0_STRT (0x0190)
#define VPIF_CH3_VANC0_SIZE (0x0194)
#define VPIF_CH3_VANC1_STRT (0x0198)
#define VPIF_CH3_VANC1_SIZE (0x019c)
#define VPIF_IODFT_CTRL (0x01c0)
/* Functions for bit Manipulation */
static inline void vpif_set_bit(u32 reg, u32 bit)
{
regw((regr(reg)) | (0x01 << bit), reg);
}
static inline void vpif_clr_bit(u32 reg, u32 bit)
{
regw(((regr(reg)) & ~(0x01 << bit)), reg);
}
/* Macro for Generating mask */
#ifdef GENERATE_MASK
#undef GENERATE_MASK
#endif
#define GENERATE_MASK(bits, pos) \
((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
/* Bit positions in the channel control registers */
#define VPIF_CH_DATA_MODE_BIT (2)
#define VPIF_CH_YC_MUX_BIT (3)
#define VPIF_CH_SDR_FMT_BIT (4)
#define VPIF_CH_HANC_EN_BIT (8)
#define VPIF_CH_VANC_EN_BIT (9)
#define VPIF_CAPTURE_CH_NIP (10)
#define VPIF_DISPLAY_CH_NIP (11)
#define VPIF_DISPLAY_PIX_EN_BIT (10)
#define VPIF_CH_INPUT_FIELD_FRAME_BIT (12)
#define VPIF_CH_FID_POLARITY_BIT (15)
#define VPIF_CH_V_VALID_POLARITY_BIT (14)
#define VPIF_CH_H_VALID_POLARITY_BIT (13)
#define VPIF_CH_DATA_WIDTH_BIT (28)
#define VPIF_CH_CLK_EDGE_CTRL_BIT (31)
/* Mask various length */
#define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0)
#define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0)
#define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0)
#define VPIF_CH_LEN_SHIFT (16)
/* VPIF masks for registers */
#define VPIF_REQ_SIZE_MASK (0x1ff)
/* bit posotion of interrupt vpif_ch_intr register */
#define VPIF_INTEN_FRAME_CH0 (0x00000001)
#define VPIF_INTEN_FRAME_CH1 (0x00000002)
#define VPIF_INTEN_FRAME_CH2 (0x00000004)
#define VPIF_INTEN_FRAME_CH3 (0x00000008)
/* bit position of clock and channel enable in vpif_chn_ctrl register */
#define VPIF_CH0_CLK_EN (0x00000002)
#define VPIF_CH0_EN (0x00000001)
#define VPIF_CH1_CLK_EN (0x00000002)
#define VPIF_CH1_EN (0x00000001)
#define VPIF_CH2_CLK_EN (0x00000002)
#define VPIF_CH2_EN (0x00000001)
#define VPIF_CH3_CLK_EN (0x00000002)
#define VPIF_CH3_EN (0x00000001)
#define VPIF_CH_CLK_EN (0x00000002)
#define VPIF_CH_EN (0x00000001)
#define VPIF_INT_TOP (0x00)
#define VPIF_INT_BOTTOM (0x01)
#define VPIF_INT_BOTH (0x02)
#define VPIF_CH0_INT_CTRL_SHIFT (6)
#define VPIF_CH1_INT_CTRL_SHIFT (6)
#define VPIF_CH2_INT_CTRL_SHIFT (6)
#define VPIF_CH3_INT_CTRL_SHIFT (6)
#define VPIF_CH_INT_CTRL_SHIFT (6)
#define VPIF_CH2_CLIP_ANC_EN 14
#define VPIF_CH2_CLIP_ACTIVE_EN 13
#define VPIF_CH3_CLIP_ANC_EN 14
#define VPIF_CH3_CLIP_ACTIVE_EN 13
/* enabled interrupt on both the fields on vpid_ch0_ctrl register */
#define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
(VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL))
/* enabled interrupt on both the fields on vpid_ch1_ctrl register */
#define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
(VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL))
/* enabled interrupt on both the fields on vpid_ch0_ctrl register */
#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
(VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL))
/* enabled interrupt on both the fields on vpid_ch1_ctrl register */
#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
(VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL))
#define VPIF_CH_FID_MASK (0x20)
#define VPIF_CH_FID_SHIFT (5)
#define VPIF_NTSC_VBI_START_FIELD0 (1)
#define VPIF_NTSC_VBI_START_FIELD1 (263)
#define VPIF_PAL_VBI_START_FIELD0 (624)
#define VPIF_PAL_VBI_START_FIELD1 (311)
#define VPIF_NTSC_HBI_START_FIELD0 (1)
#define VPIF_NTSC_HBI_START_FIELD1 (263)
#define VPIF_PAL_HBI_START_FIELD0 (624)
#define VPIF_PAL_HBI_START_FIELD1 (311)
#define VPIF_NTSC_VBI_COUNT_FIELD0 (20)
#define VPIF_NTSC_VBI_COUNT_FIELD1 (19)
#define VPIF_PAL_VBI_COUNT_FIELD0 (24)
#define VPIF_PAL_VBI_COUNT_FIELD1 (25)
#define VPIF_NTSC_HBI_COUNT_FIELD0 (263)
#define VPIF_NTSC_HBI_COUNT_FIELD1 (262)
#define VPIF_PAL_HBI_COUNT_FIELD0 (312)
#define VPIF_PAL_HBI_COUNT_FIELD1 (313)
#define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720)
#define VPIF_PAL_VBI_SAMPLES_PER_LINE (720)
#define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268)
#define VPIF_PAL_HBI_SAMPLES_PER_LINE (280)
#define VPIF_CH_VANC_EN (0x20)
#define VPIF_DMA_REQ_SIZE (0x080)
#define VPIF_EMULATION_DISABLE (0x01)
extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS];
/* inline function to enable/disable channel0 */
static inline void enable_channel0(int enable)
{
if (enable)
regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);
else
regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);
}
/* inline function to enable/disable channel1 */
static inline void enable_channel1(int enable)
{
if (enable)
regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);
else
regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);
}
/* inline function to enable interrupt for channel0 */
static inline void channel0_intr_enable(int enable)
{
unsigned long flags;
spin_lock_irqsave(&vpif_lock, flags);
if (enable) {
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
VPIF_INTEN_SET);
} else {
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
VPIF_INTEN_SET);
}
spin_unlock_irqrestore(&vpif_lock, flags);
}
/* inline function to enable interrupt for channel1 */
static inline void channel1_intr_enable(int enable)
{
unsigned long flags;
spin_lock_irqsave(&vpif_lock, flags);
if (enable) {
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
VPIF_INTEN_SET);
} else {
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
VPIF_INTEN_SET);
}
spin_unlock_irqrestore(&vpif_lock, flags);
}
/* inline function to set buffer addresses in case of Y/C non mux mode */
static inline void ch0_set_video_buf_addr_yc_nmux(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
}
/* inline function to set buffer addresses in VPIF registers for video data */
static inline void ch0_set_video_buf_addr(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA);
regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA);
}
static inline void ch1_set_video_buf_addr(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA);
regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA);
regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
}
static inline void ch0_set_vbi_addr(unsigned long top_vbi,
unsigned long btm_vbi, unsigned long a, unsigned long b)
{
regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC);
regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC);
}
static inline void ch0_set_hbi_addr(unsigned long top_vbi,
unsigned long btm_vbi, unsigned long a, unsigned long b)
{
regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC);
regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC);
}
static inline void ch1_set_vbi_addr(unsigned long top_vbi,
unsigned long btm_vbi, unsigned long a, unsigned long b)
{
regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC);
regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC);
}
static inline void ch1_set_hbi_addr(unsigned long top_vbi,
unsigned long btm_vbi, unsigned long a, unsigned long b)
{
regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC);
regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC);
}
/* Inline function to enable raw vbi in the given channel */
static inline void disable_raw_feature(u8 channel_id, u8 index)
{
u32 ctrl_reg;
if (0 == channel_id)
ctrl_reg = VPIF_CH0_CTRL;
else
ctrl_reg = VPIF_CH1_CTRL;
if (1 == index)
vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
else
vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
}
static inline void enable_raw_feature(u8 channel_id, u8 index)
{
u32 ctrl_reg;
if (0 == channel_id)
ctrl_reg = VPIF_CH0_CTRL;
else
ctrl_reg = VPIF_CH1_CTRL;
if (1 == index)
vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
else
vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
}
/* inline function to enable/disable channel2 */
static inline void enable_channel2(int enable)
{
if (enable) {
regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);
} else {
regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);
}
}
/* inline function to enable/disable channel3 */
static inline void enable_channel3(int enable)
{
if (enable) {
regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);
} else {
regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);
}
}
/* inline function to enable interrupt for channel2 */
static inline void channel2_intr_enable(int enable)
{
unsigned long flags;
spin_lock_irqsave(&vpif_lock, flags);
if (enable) {
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
VPIF_INTEN_SET);
} else {
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
VPIF_INTEN_SET);
}
spin_unlock_irqrestore(&vpif_lock, flags);
}
/* inline function to enable interrupt for channel3 */
static inline void channel3_intr_enable(int enable)
{
unsigned long flags;
spin_lock_irqsave(&vpif_lock, flags);
if (enable) {
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
VPIF_INTEN_SET);
} else {
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
VPIF_INTEN_SET);
}
spin_unlock_irqrestore(&vpif_lock, flags);
}
/* inline function to enable raw vbi data for channel2 */
static inline void channel2_raw_enable(int enable, u8 index)
{
u32 mask;
if (1 == index)
mask = VPIF_CH_VANC_EN_BIT;
else
mask = VPIF_CH_HANC_EN_BIT;
if (enable)
vpif_set_bit(VPIF_CH2_CTRL, mask);
else
vpif_clr_bit(VPIF_CH2_CTRL, mask);
}
/* inline function to enable raw vbi data for channel3*/
static inline void channel3_raw_enable(int enable, u8 index)
{
u32 mask;
if (1 == index)
mask = VPIF_CH_VANC_EN_BIT;
else
mask = VPIF_CH_HANC_EN_BIT;
if (enable)
vpif_set_bit(VPIF_CH3_CTRL, mask);
else
vpif_clr_bit(VPIF_CH3_CTRL, mask);
}
/* function to enable clipping (for both active and blanking regions) on ch 2 */
static inline void channel2_clipping_enable(int enable)
{
if (enable) {
vpif_set_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ANC_EN);
vpif_set_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ACTIVE_EN);
} else {
vpif_clr_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ANC_EN);
vpif_clr_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ACTIVE_EN);
}
}
/* function to enable clipping (for both active and blanking regions) on ch 3 */
static inline void channel3_clipping_enable(int enable)
{
if (enable) {
vpif_set_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ANC_EN);
vpif_set_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ACTIVE_EN);
} else {
vpif_clr_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ANC_EN);
vpif_clr_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ACTIVE_EN);
}
}
/* inline function to set buffer addresses in case of Y/C non mux mode */
static inline void ch2_set_video_buf_addr_yc_nmux(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
}
/* inline function to set buffer addresses in VPIF registers for video data */
static inline void ch2_set_video_buf_addr(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA);
regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA);
}
static inline void ch3_set_video_buf_addr(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA);
regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA);
regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
}
/* inline function to set buffer addresses in VPIF registers for vbi data */
static inline void ch2_set_vbi_addr(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC);
regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC);
}
static inline void ch3_set_vbi_addr(unsigned long top_strt_luma,
unsigned long btm_strt_luma,
unsigned long top_strt_chroma,
unsigned long btm_strt_chroma)
{
regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC);
regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC);
}
static inline int vpif_intr_status(int channel)
{
int status = 0;
int mask;
if (channel < 0 || channel > 3)
return 0;
mask = 1 << channel;
status = regr(VPIF_STATUS) & mask;
regw(status, VPIF_STATUS_CLR);
return status;
}
#define VPIF_MAX_NAME (30)
/* This structure will store size parameters as per the mode selected by user */
struct vpif_channel_config_params {
char name[VPIF_MAX_NAME]; /* Name of the mode */
u16 width; /* Indicates width of the image */
u16 height; /* Indicates height of the image */
u8 frm_fmt; /* Interlaced (0) or progressive (1) */
u8 ycmux_mode; /* This mode requires one (0) or two (1)
channels */
u16 eav2sav; /* length of eav 2 sav */
u16 sav2eav; /* length of sav 2 eav */
u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */
u16 vsize; /* Vertical size of the image */
u8 capture_format; /* Indicates whether capture format
* is in BT or in CCD/CMOS */
u8 vbi_supported; /* Indicates whether this mode
* supports capturing vbi or not */
u8 hd_sd; /* HDTV (1) or SDTV (0) format */
v4l2_std_id stdid; /* SDTV format */
struct v4l2_dv_timings dv_timings; /* HDTV format */
};
extern const unsigned int vpif_ch_params_count;
extern const struct vpif_channel_config_params vpif_ch_params[];
struct vpif_video_params;
struct vpif_params;
struct vpif_vbi_params;
int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id);
void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
u8 channel_id);
int vpif_channel_getfid(u8 channel_id);
enum data_size {
_8BITS = 0,
_10BITS,
_12BITS,
};
/* Structure for vpif parameters for raw vbi data */
struct vpif_vbi_params {
__u32 hstart0; /* Horizontal start of raw vbi data for first field */
__u32 vstart0; /* Vertical start of raw vbi data for first field */
__u32 hsize0; /* Horizontal size of raw vbi data for first field */
__u32 vsize0; /* Vertical size of raw vbi data for first field */
__u32 hstart1; /* Horizontal start of raw vbi data for second field */
__u32 vstart1; /* Vertical start of raw vbi data for second field */
__u32 hsize1; /* Horizontal size of raw vbi data for second field */
__u32 vsize1; /* Vertical size of raw vbi data for second field */
};
/* structure for vpif parameters */
struct vpif_video_params {
__u8 storage_mode; /* Indicates field or frame mode */
unsigned long hpitch;
v4l2_std_id stdid;
};
struct vpif_params {
struct vpif_interface iface;
struct vpif_video_params video_params;
struct vpif_channel_config_params std_info;
union param {
struct vpif_vbi_params vbi_params;
enum data_size data_sz;
} params;
};
#endif /* End of #ifndef VPIF_H */
linux-7.2.3/drivers/media/platform/ti/davinci/vpif_capture.c
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linux-7.2.3/drivers/media/platform/ti/davinci/vpif_capture.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009 Texas Instruments Inc
*/
#ifndef VPIF_CAPTURE_H
#define VPIF_CAPTURE_H
/* Header files */
#include <media/videobuf2-dma-contig.h>
#include <media/v4l2-device.h>
#include "vpif.h"
/* Macros */
#define VPIF_CAPTURE_VERSION "0.0.2"
#define VPIF_VALID_FIELD(field) (((V4L2_FIELD_ANY == field) || \
(V4L2_FIELD_NONE == field)) || \
(((V4L2_FIELD_INTERLACED == field) || \
(V4L2_FIELD_SEQ_TB == field)) || \
(V4L2_FIELD_SEQ_BT == field)))
#define VPIF_CAPTURE_MAX_DEVICES 2
#define VPIF_VIDEO_INDEX 0
#define VPIF_NUMBER_OF_OBJECTS 1
/* Enumerated data type to give id to each device per channel */
enum vpif_channel_id {
VPIF_CHANNEL0_VIDEO = 0,
VPIF_CHANNEL1_VIDEO,
};
struct video_obj {
enum v4l2_field buf_field;
/* Currently selected or default standard */
v4l2_std_id stdid;
struct v4l2_dv_timings dv_timings;
};
struct vpif_cap_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
};
struct common_obj {
/* Pointer pointing to current v4l2_buffer */
struct vpif_cap_buffer *cur_frm;
/* Pointer pointing to current v4l2_buffer */
struct vpif_cap_buffer *next_frm;
/* Used to store pixel format */
struct v4l2_format fmt;
/* Buffer queue used in vb2 */
struct vb2_queue buffer_queue;
/* Queue of filled frames */
struct list_head dma_queue;
/* Protects the dma_queue field */
spinlock_t irqlock;
/* lock used to access this structure */
struct mutex lock;
/* Function pointer to set the addresses */
void (*set_addr) (unsigned long, unsigned long, unsigned long,
unsigned long);
/* offset where Y top starts from the starting of the buffer */
u32 ytop_off;
/* offset where Y bottom starts from the starting of the buffer */
u32 ybtm_off;
/* offset where C top starts from the starting of the buffer */
u32 ctop_off;
/* offset where C bottom starts from the starting of the buffer */
u32 cbtm_off;
/* Indicates width of the image data */
u32 width;
/* Indicates height of the image data */
u32 height;
};
struct channel_obj {
/* Identifies video device for this channel */
struct video_device video_dev;
/* Indicates id of the field which is being displayed */
u32 field_id;
/* flag to indicate whether decoder is initialized */
u8 initialized;
/* Identifies channel */
enum vpif_channel_id channel_id;
/* Current input */
u32 input_idx;
/* subdev corresponding to the current input, may be NULL */
struct v4l2_subdev *sd;
/* vpif configuration params */
struct vpif_params vpifparams;
/* common object array */
struct common_obj common[VPIF_NUMBER_OF_OBJECTS];
/* video object */
struct video_obj video;
};
struct vpif_device {
struct v4l2_device v4l2_dev;
struct channel_obj *dev[VPIF_CAPTURE_NUM_CHANNELS];
struct v4l2_subdev **sd;
struct v4l2_async_notifier notifier;
struct vpif_capture_config *config;
};
#endif /* VPIF_CAPTURE_H */
linux-7.2.3/drivers/media/platform/ti/davinci/vpif_display.c
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linux-7.2.3/drivers/media/platform/ti/davinci/vpif_display.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* VPIF display header file
*
* Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef VPIF_DISPLAY_H
#define VPIF_DISPLAY_H
/* Header files */
#include <media/videobuf2-dma-contig.h>
#include <media/v4l2-device.h>
#include "vpif.h"
/* Macros */
#define VPIF_DISPLAY_VERSION "0.0.2"
#define VPIF_VALID_FIELD(field) \
(((V4L2_FIELD_ANY == field) || (V4L2_FIELD_NONE == field)) || \
(((V4L2_FIELD_INTERLACED == field) || (V4L2_FIELD_SEQ_TB == field)) || \
(V4L2_FIELD_SEQ_BT == field)))
#define VPIF_DISPLAY_MAX_DEVICES (2)
#define VPIF_SLICED_BUF_SIZE (256)
#define VPIF_SLICED_MAX_SERVICES (3)
#define VPIF_VIDEO_INDEX (0)
#define VPIF_VBI_INDEX (1)
#define VPIF_HBI_INDEX (2)
/* Setting it to 1 as HBI/VBI support yet to be added , else 3*/
#define VPIF_NUMOBJECTS (1)
/* Macros */
#define ISALIGNED(a) (0 == ((a) & 7))
/* enumerated data types */
/* Enumerated data type to give id to each device per channel */
enum vpif_channel_id {
VPIF_CHANNEL2_VIDEO = 0, /* Channel2 Video */
VPIF_CHANNEL3_VIDEO, /* Channel3 Video */
};
/* structures */
struct video_obj {
enum v4l2_field buf_field;
u32 latest_only; /* indicate whether to return
* most recent displayed frame only */
v4l2_std_id stdid; /* Currently selected or default
* standard */
struct v4l2_dv_timings dv_timings;
};
struct vpif_disp_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
};
struct common_obj {
struct vpif_disp_buffer *cur_frm; /* Pointer pointing to current
* vb2_buffer */
struct vpif_disp_buffer *next_frm; /* Pointer pointing to next
* vb2_buffer */
struct v4l2_format fmt; /* Used to store the format */
struct vb2_queue buffer_queue; /* Buffer queue used in vb2 */
struct list_head dma_queue; /* Queue of filled frames */
spinlock_t irqlock; /* Used for video buffer
* handling */
/* channel specific parameters */
struct mutex lock; /* lock used to access this
* structure */
u32 ytop_off; /* offset of Y top from the
* starting of the buffer */
u32 ybtm_off; /* offset of Y bottom from the
* starting of the buffer */
u32 ctop_off; /* offset of C top from the
* starting of the buffer */
u32 cbtm_off; /* offset of C bottom from the
* starting of the buffer */
/* Function pointer to set the addresses */
void (*set_addr)(unsigned long, unsigned long,
unsigned long, unsigned long);
u32 height;
u32 width;
};
struct channel_obj {
/* V4l2 specific parameters */
struct video_device video_dev; /* Identifies video device for
* this channel */
u32 field_id; /* Indicates id of the field
* which is being displayed */
u8 initialized; /* flag to indicate whether
* encoder is initialized */
u32 output_idx; /* Current output index */
struct v4l2_subdev *sd; /* Current output subdev(may be NULL) */
enum vpif_channel_id channel_id;/* Identifies channel */
struct vpif_params vpifparams;
struct common_obj common[VPIF_NUMOBJECTS];
struct video_obj video;
};
/* vpif device structure */
struct vpif_device {
struct v4l2_device v4l2_dev;
struct channel_obj *dev[VPIF_DISPLAY_NUM_CHANNELS];
struct v4l2_subdev **sd;
struct vpif_display_config *config;
};
#endif /* VPIF_DISPLAY_H */