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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/net/can/ctucanfd/Kconfig
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config CAN_CTUCANFD
tristate "CTU CAN-FD IP core" if COMPILE_TEST
help
This driver adds support for the CTU CAN FD open-source IP core.
More documentation and core sources at project page
(https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core).
The core integration to Xilinx Zynq system as platform driver
is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
Implementation on Intel FPGA-based PCI Express board is available
from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
Guidepost CTU FEE CAN bus projects page https://canbus.pages.fel.cvut.cz/ .
config CAN_CTUCANFD_PCI
tristate "CTU CAN-FD IP core PCI/PCIe driver"
depends on PCI
select CAN_CTUCANFD
help
This driver adds PCI/PCIe support for CTU CAN-FD IP core.
The project providing FPGA design for Intel EP4CGX15 based DB4CGX15
PCIe board with PiKRON.com designed transceiver riser shield is available
at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd .
config CAN_CTUCANFD_PLATFORM
tristate "CTU CAN-FD IP core platform (FPGA, SoC) driver"
depends on HAS_IOMEM && OF
select CAN_CTUCANFD
help
The core has been tested together with OpenCores SJA1000
modified to be CAN FD frames tolerant on MicroZed Zynq based
MZ_APO education kits designed by Petr Porazil from PiKRON.com
company. FPGA design https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top.
The kit description at the Computer Architectures course pages
https://cw.fel.cvut.cz/wiki/courses/b35apo/documentation/mz_apo/start .
linux-7.2.3/drivers/net/can/ctucanfd/Makefile
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Makefile for the CTU CAN-FD IP module drivers
#
obj-$(CONFIG_CAN_CTUCANFD) := ctucanfd.o
ctucanfd-y := ctucanfd_base.o
obj-$(CONFIG_CAN_CTUCANFD_PCI) += ctucanfd_pci.o
obj-$(CONFIG_CAN_CTUCANFD_PLATFORM) += ctucanfd_platform.o
linux-7.2.3/drivers/net/can/ctucanfd/ctucanfd.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*******************************************************************************
*
* CTU CAN FD IP Core
*
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
* Czech Technical University (http://www.cvut.cz/)
******************************************************************************/
#ifndef __CTUCANFD__
#define __CTUCANFD__
#include <linux/netdevice.h>
#include <linux/can/dev.h>
#include <linux/list.h>
enum ctu_can_fd_can_registers;
struct ctucan_priv {
struct can_priv can; /* must be first member! */
void __iomem *mem_base;
u32 (*read_reg)(struct ctucan_priv *priv,
enum ctu_can_fd_can_registers reg);
void (*write_reg)(struct ctucan_priv *priv,
enum ctu_can_fd_can_registers reg, u32 val);
unsigned int txb_head;
unsigned int txb_tail;
u32 txb_prio;
unsigned int ntxbufs;
spinlock_t tx_lock; /* spinlock to serialize allocation and processing of TX buffers */
struct napi_struct napi;
struct device *dev;
struct clk *can_clk;
int irq_flags;
unsigned long drv_flags;
u32 rxfrm_first_word;
struct list_head peers_on_pdev;
};
/**
* ctucan_probe_common - Device type independent registration call
*
* This function does all the memory allocation and registration for the CAN
* device.
*
* @dev: Handle to the generic device structure
* @addr: Base address of CTU CAN FD core address
* @irq: Interrupt number
* @ntxbufs: Number of implemented Tx buffers
* @can_clk_rate: Clock rate, if 0 then clock are taken from device node
* @pm_enable_call: Whether pm_runtime_enable should be called
* @set_drvdata_fnc: Function to set network driver data for physical device
*
* Return: 0 on success and failure value on error
*/
int ctucan_probe_common(struct device *dev, void __iomem *addr,
int irq, unsigned int ntxbufs,
unsigned long can_clk_rate,
int pm_enable_call,
void (*set_drvdata_fnc)(struct device *dev,
struct net_device *ndev));
int ctucan_suspend(struct device *dev) __maybe_unused;
int ctucan_resume(struct device *dev) __maybe_unused;
#endif /*__CTUCANFD__*/
linux-7.2.3/drivers/net/can/ctucanfd/ctucanfd_base.c
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linux-7.2.3/drivers/net/can/ctucanfd/ctucanfd_kframe.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*******************************************************************************
*
* CTU CAN FD IP Core
*
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
* Czech Technical University (http://www.cvut.cz/)
******************************************************************************/
/* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
#define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
#include <linux/bits.h>
/* CAN_Frame_format memory map */
enum ctu_can_fd_can_frame_format {
CTUCANFD_FRAME_FORMAT_W = 0x0,
CTUCANFD_IDENTIFIER_W = 0x4,
CTUCANFD_TIMESTAMP_L_W = 0x8,
CTUCANFD_TIMESTAMP_U_W = 0xc,
CTUCANFD_DATA_1_4_W = 0x10,
CTUCANFD_DATA_5_8_W = 0x14,
CTUCANFD_DATA_61_64_W = 0x4c,
};
/* CAN_FD_Frame_format memory region */
/* FRAME_FORMAT_W registers */
#define REG_FRAME_FORMAT_W_DLC GENMASK(3, 0)
#define REG_FRAME_FORMAT_W_RTR BIT(5)
#define REG_FRAME_FORMAT_W_IDE BIT(6)
#define REG_FRAME_FORMAT_W_FDF BIT(7)
#define REG_FRAME_FORMAT_W_BRS BIT(9)
#define REG_FRAME_FORMAT_W_ESI_RSV BIT(10)
#define REG_FRAME_FORMAT_W_RWCNT GENMASK(15, 11)
/* IDENTIFIER_W registers */
#define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK(17, 0)
#define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK(28, 18)
/* TIMESTAMP_L_W registers */
#define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK(31, 0)
/* TIMESTAMP_U_W registers */
#define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK(31, 0)
/* DATA_1_4_W registers */
#define REG_DATA_1_4_W_DATA_1 GENMASK(7, 0)
#define REG_DATA_1_4_W_DATA_2 GENMASK(15, 8)
#define REG_DATA_1_4_W_DATA_3 GENMASK(23, 16)
#define REG_DATA_1_4_W_DATA_4 GENMASK(31, 24)
/* DATA_5_8_W registers */
#define REG_DATA_5_8_W_DATA_5 GENMASK(7, 0)
#define REG_DATA_5_8_W_DATA_6 GENMASK(15, 8)
#define REG_DATA_5_8_W_DATA_7 GENMASK(23, 16)
#define REG_DATA_5_8_W_DATA_8 GENMASK(31, 24)
/* DATA_61_64_W registers */
#define REG_DATA_61_64_W_DATA_61 GENMASK(7, 0)
#define REG_DATA_61_64_W_DATA_62 GENMASK(15, 8)
#define REG_DATA_61_64_W_DATA_63 GENMASK(23, 16)
#define REG_DATA_61_64_W_DATA_64 GENMASK(31, 24)
#endif
linux-7.2.3/drivers/net/can/ctucanfd/ctucanfd_kregs.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*******************************************************************************
*
* CTU CAN FD IP Core
*
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
* Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
* Czech Technical University (http://www.cvut.cz/)
******************************************************************************/
/* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
#define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
#include <linux/bits.h>
/* CAN_Registers memory map */
enum ctu_can_fd_can_registers {
CTUCANFD_DEVICE_ID = 0x0,
CTUCANFD_VERSION = 0x2,
CTUCANFD_MODE = 0x4,
CTUCANFD_SETTINGS = 0x6,
CTUCANFD_STATUS = 0x8,
CTUCANFD_COMMAND = 0xc,
CTUCANFD_INT_STAT = 0x10,
CTUCANFD_INT_ENA_SET = 0x14,
CTUCANFD_INT_ENA_CLR = 0x18,
CTUCANFD_INT_MASK_SET = 0x1c,
CTUCANFD_INT_MASK_CLR = 0x20,
CTUCANFD_BTR = 0x24,
CTUCANFD_BTR_FD = 0x28,
CTUCANFD_EWL = 0x2c,
CTUCANFD_ERP = 0x2d,
CTUCANFD_FAULT_STATE = 0x2e,
CTUCANFD_REC = 0x30,
CTUCANFD_TEC = 0x32,
CTUCANFD_ERR_NORM = 0x34,
CTUCANFD_ERR_FD = 0x36,
CTUCANFD_CTR_PRES = 0x38,
CTUCANFD_FILTER_A_MASK = 0x3c,
CTUCANFD_FILTER_A_VAL = 0x40,
CTUCANFD_FILTER_B_MASK = 0x44,
CTUCANFD_FILTER_B_VAL = 0x48,
CTUCANFD_FILTER_C_MASK = 0x4c,
CTUCANFD_FILTER_C_VAL = 0x50,
CTUCANFD_FILTER_RAN_LOW = 0x54,
CTUCANFD_FILTER_RAN_HIGH = 0x58,
CTUCANFD_FILTER_CONTROL = 0x5c,
CTUCANFD_FILTER_STATUS = 0x5e,
CTUCANFD_RX_MEM_INFO = 0x60,
CTUCANFD_RX_POINTERS = 0x64,
CTUCANFD_RX_STATUS = 0x68,
CTUCANFD_RX_SETTINGS = 0x6a,
CTUCANFD_RX_DATA = 0x6c,
CTUCANFD_TX_STATUS = 0x70,
CTUCANFD_TX_COMMAND = 0x74,
CTUCANFD_TXTB_INFO = 0x76,
CTUCANFD_TX_PRIORITY = 0x78,
CTUCANFD_ERR_CAPT = 0x7c,
CTUCANFD_RETR_CTR = 0x7d,
CTUCANFD_ALC = 0x7e,
CTUCANFD_TS_INFO = 0x7f,
CTUCANFD_TRV_DELAY = 0x80,
CTUCANFD_SSP_CFG = 0x82,
CTUCANFD_RX_FR_CTR = 0x84,
CTUCANFD_TX_FR_CTR = 0x88,
CTUCANFD_DEBUG_REGISTER = 0x8c,
CTUCANFD_YOLO_REG = 0x90,
CTUCANFD_TIMESTAMP_LOW = 0x94,
CTUCANFD_TIMESTAMP_HIGH = 0x98,
CTUCANFD_TXTB1_DATA_1 = 0x100,
CTUCANFD_TXTB1_DATA_2 = 0x104,
CTUCANFD_TXTB1_DATA_20 = 0x14c,
CTUCANFD_TXTB2_DATA_1 = 0x200,
CTUCANFD_TXTB2_DATA_2 = 0x204,
CTUCANFD_TXTB2_DATA_20 = 0x24c,
CTUCANFD_TXTB3_DATA_1 = 0x300,
CTUCANFD_TXTB3_DATA_2 = 0x304,
CTUCANFD_TXTB3_DATA_20 = 0x34c,
CTUCANFD_TXTB4_DATA_1 = 0x400,
CTUCANFD_TXTB4_DATA_2 = 0x404,
CTUCANFD_TXTB4_DATA_20 = 0x44c,
};
/* Control_registers memory region */
/* DEVICE_ID VERSION registers */
#define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
#define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
#define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
/* MODE SETTINGS registers */
#define REG_MODE_RST BIT(0)
#define REG_MODE_BMM BIT(1)
#define REG_MODE_STM BIT(2)
#define REG_MODE_AFM BIT(3)
#define REG_MODE_FDE BIT(4)
#define REG_MODE_TTTM BIT(5)
#define REG_MODE_ROM BIT(6)
#define REG_MODE_ACF BIT(7)
#define REG_MODE_TSTM BIT(8)
#define REG_MODE_RXBAM BIT(9)
#define REG_MODE_SAM BIT(11)
#define REG_MODE_RTRLE BIT(16)
#define REG_MODE_RTRTH GENMASK(20, 17)
#define REG_MODE_ILBP BIT(21)
#define REG_MODE_ENA BIT(22)
#define REG_MODE_NISOFD BIT(23)
#define REG_MODE_PEX BIT(24)
#define REG_MODE_TBFBO BIT(25)
#define REG_MODE_FDRF BIT(26)
/* STATUS registers */
#define REG_STATUS_RXNE BIT(0)
#define REG_STATUS_DOR BIT(1)
#define REG_STATUS_TXNF BIT(2)
#define REG_STATUS_EFT BIT(3)
#define REG_STATUS_RXS BIT(4)
#define REG_STATUS_TXS BIT(5)
#define REG_STATUS_EWL BIT(6)
#define REG_STATUS_IDLE BIT(7)
#define REG_STATUS_PEXS BIT(8)
#define REG_STATUS_STCNT BIT(16)
/* COMMAND registers */
#define REG_COMMAND_RXRPMV BIT(1)
#define REG_COMMAND_RRB BIT(2)
#define REG_COMMAND_CDO BIT(3)
#define REG_COMMAND_ERCRST BIT(4)
#define REG_COMMAND_RXFCRST BIT(5)
#define REG_COMMAND_TXFCRST BIT(6)
#define REG_COMMAND_CPEXS BIT(7)
/* INT_STAT registers */
#define REG_INT_STAT_RXI BIT(0)
#define REG_INT_STAT_TXI BIT(1)
#define REG_INT_STAT_EWLI BIT(2)
#define REG_INT_STAT_DOI BIT(3)
#define REG_INT_STAT_FCSI BIT(4)
#define REG_INT_STAT_ALI BIT(5)
#define REG_INT_STAT_BEI BIT(6)
#define REG_INT_STAT_OFI BIT(7)
#define REG_INT_STAT_RXFI BIT(8)
#define REG_INT_STAT_BSI BIT(9)
#define REG_INT_STAT_RBNEI BIT(10)
#define REG_INT_STAT_TXBHCI BIT(11)
/* INT_ENA_SET registers */
#define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
/* INT_ENA_CLR registers */
#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
/* INT_MASK_SET registers */
#define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
/* INT_MASK_CLR registers */
#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
/* BTR registers */
#define REG_BTR_PROP GENMASK(6, 0)
#define REG_BTR_PH1 GENMASK(12, 7)
#define REG_BTR_PH2 GENMASK(18, 13)
#define REG_BTR_BRP GENMASK(26, 19)
#define REG_BTR_SJW GENMASK(31, 27)
/* BTR_FD registers */
#define REG_BTR_FD_PROP_FD GENMASK(5, 0)
#define REG_BTR_FD_PH1_FD GENMASK(11, 7)
#define REG_BTR_FD_PH2_FD GENMASK(17, 13)
#define REG_BTR_FD_BRP_FD GENMASK(26, 19)
#define REG_BTR_FD_SJW_FD GENMASK(31, 27)
/* EWL ERP FAULT_STATE registers */
#define REG_EWL_EW_LIMIT GENMASK(7, 0)
#define REG_EWL_ERP_LIMIT GENMASK(15, 8)
#define REG_EWL_ERA BIT(16)
#define REG_EWL_ERP BIT(17)
#define REG_EWL_BOF BIT(18)
/* REC TEC registers */
#define REG_REC_REC_VAL GENMASK(8, 0)
#define REG_REC_TEC_VAL GENMASK(24, 16)
/* ERR_NORM ERR_FD registers */
#define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
#define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
/* CTR_PRES registers */
#define REG_CTR_PRES_CTPV GENMASK(8, 0)
#define REG_CTR_PRES_PTX BIT(9)
#define REG_CTR_PRES_PRX BIT(10)
#define REG_CTR_PRES_ENORM BIT(11)
#define REG_CTR_PRES_EFD BIT(12)
/* FILTER_A_MASK registers */
#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
/* FILTER_A_VAL registers */
#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
/* FILTER_B_MASK registers */
#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
/* FILTER_B_VAL registers */
#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
/* FILTER_C_MASK registers */
#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
/* FILTER_C_VAL registers */
#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
/* FILTER_RAN_LOW registers */
#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
/* FILTER_RAN_HIGH registers */
#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
/* FILTER_CONTROL FILTER_STATUS registers */
#define REG_FILTER_CONTROL_FANB BIT(0)
#define REG_FILTER_CONTROL_FANE BIT(1)
#define REG_FILTER_CONTROL_FAFB BIT(2)
#define REG_FILTER_CONTROL_FAFE BIT(3)
#define REG_FILTER_CONTROL_FBNB BIT(4)
#define REG_FILTER_CONTROL_FBNE BIT(5)
#define REG_FILTER_CONTROL_FBFB BIT(6)
#define REG_FILTER_CONTROL_FBFE BIT(7)
#define REG_FILTER_CONTROL_FCNB BIT(8)
#define REG_FILTER_CONTROL_FCNE BIT(9)
#define REG_FILTER_CONTROL_FCFB BIT(10)
#define REG_FILTER_CONTROL_FCFE BIT(11)
#define REG_FILTER_CONTROL_FRNB BIT(12)
#define REG_FILTER_CONTROL_FRNE BIT(13)
#define REG_FILTER_CONTROL_FRFB BIT(14)
#define REG_FILTER_CONTROL_FRFE BIT(15)
#define REG_FILTER_CONTROL_SFA BIT(16)
#define REG_FILTER_CONTROL_SFB BIT(17)
#define REG_FILTER_CONTROL_SFC BIT(18)
#define REG_FILTER_CONTROL_SFR BIT(19)
/* RX_MEM_INFO registers */
#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
/* RX_POINTERS registers */
#define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
#define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
/* RX_STATUS RX_SETTINGS registers */
#define REG_RX_STATUS_RXE BIT(0)
#define REG_RX_STATUS_RXF BIT(1)
#define REG_RX_STATUS_RXMOF BIT(2)
#define REG_RX_STATUS_RXFRC GENMASK(14, 4)
#define REG_RX_STATUS_RTSOP BIT(16)
/* RX_DATA registers */
#define REG_RX_DATA_RX_DATA GENMASK(31, 0)
/* TX_STATUS registers */
#define REG_TX_STATUS_TX1S GENMASK(3, 0)
#define REG_TX_STATUS_TX2S GENMASK(7, 4)
#define REG_TX_STATUS_TX3S GENMASK(11, 8)
#define REG_TX_STATUS_TX4S GENMASK(15, 12)
#define REG_TX_STATUS_TX5S GENMASK(19, 16)
#define REG_TX_STATUS_TX6S GENMASK(23, 20)
#define REG_TX_STATUS_TX7S GENMASK(27, 24)
#define REG_TX_STATUS_TX8S GENMASK(31, 28)
/* TX_COMMAND TXTB_INFO registers */
#define REG_TX_COMMAND_TXCE BIT(0)
#define REG_TX_COMMAND_TXCR BIT(1)
#define REG_TX_COMMAND_TXCA BIT(2)
#define REG_TX_COMMAND_TXB1 BIT(8)
#define REG_TX_COMMAND_TXB2 BIT(9)
#define REG_TX_COMMAND_TXB3 BIT(10)
#define REG_TX_COMMAND_TXB4 BIT(11)
#define REG_TX_COMMAND_TXB5 BIT(12)
#define REG_TX_COMMAND_TXB6 BIT(13)
#define REG_TX_COMMAND_TXB7 BIT(14)
#define REG_TX_COMMAND_TXB8 BIT(15)
#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16)
/* TX_PRIORITY registers */
#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
#define REG_TX_PRIORITY_TXT5P GENMASK(18, 16)
#define REG_TX_PRIORITY_TXT6P GENMASK(22, 20)
#define REG_TX_PRIORITY_TXT7P GENMASK(26, 24)
#define REG_TX_PRIORITY_TXT8P GENMASK(30, 28)
/* ERR_CAPT RETR_CTR ALC TS_INFO registers */
#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)
#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
#define REG_ERR_CAPT_TS_BITS GENMASK(29, 24)
/* TRV_DELAY SSP_CFG registers */
#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
#define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
#define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
/* RX_FR_CTR registers */
#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
/* TX_FR_CTR registers */
#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
/* DEBUG_REGISTER registers */
#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
#define REG_DEBUG_REGISTER_PC_ARB BIT(6)
#define REG_DEBUG_REGISTER_PC_CON BIT(7)
#define REG_DEBUG_REGISTER_PC_DAT BIT(8)
#define REG_DEBUG_REGISTER_PC_STC BIT(9)
#define REG_DEBUG_REGISTER_PC_CRC BIT(10)
#define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
#define REG_DEBUG_REGISTER_PC_ACK BIT(12)
#define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
#define REG_DEBUG_REGISTER_PC_EOF BIT(14)
#define REG_DEBUG_REGISTER_PC_INT BIT(15)
#define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
#define REG_DEBUG_REGISTER_PC_OVR BIT(17)
#define REG_DEBUG_REGISTER_PC_SOF BIT(18)
/* YOLO_REG registers */
#define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
/* TIMESTAMP_LOW registers */
#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
/* TIMESTAMP_HIGH registers */
#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)
#endif
linux-7.2.3/drivers/net/can/ctucanfd/ctucanfd_pci.c
+283
View File
@@ -0,0 +1,283 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*******************************************************************************
*
* CTU CAN FD IP Core
*
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
* Czech Technical University (http://www.cvut.cz/)
******************************************************************************/
#include <linux/module.h>
#include <linux/pci.h>
#include "ctucanfd.h"
#ifndef PCI_VENDOR_ID_TEDIA
#define PCI_VENDOR_ID_TEDIA 0x1760
#endif
#ifndef PCI_DEVICE_ID_TEDIA_CTUCAN_VER21
#define PCI_DEVICE_ID_TEDIA_CTUCAN_VER21 0xff00
#endif
#define CTUCAN_BAR0_CTUCAN_ID 0x0000
#define CTUCAN_BAR0_CRA_BASE 0x4000
#define CYCLONE_IV_CRA_A2P_IE (0x0050)
#define CTUCAN_WITHOUT_CTUCAN_ID 0
#define CTUCAN_WITH_CTUCAN_ID 1
struct ctucan_pci_board_data {
void __iomem *bar0_base;
void __iomem *cra_base;
void __iomem *bar1_base;
struct list_head ndev_list_head;
int use_msi;
};
static struct ctucan_pci_board_data *ctucan_pci_get_bdata(struct pci_dev *pdev)
{
return (struct ctucan_pci_board_data *)pci_get_drvdata(pdev);
}
static void ctucan_pci_set_drvdata(struct device *dev,
struct net_device *ndev)
{
struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
struct ctucan_priv *priv = netdev_priv(ndev);
struct ctucan_pci_board_data *bdata = ctucan_pci_get_bdata(pdev);
list_add(&priv->peers_on_pdev, &bdata->ndev_list_head);
priv->irq_flags = IRQF_SHARED;
}
/**
* ctucan_pci_probe - PCI registration call
* @pdev: Handle to the pci device structure
* @ent: Pointer to the entry from ctucan_pci_tbl
*
* This function does all the memory allocation and registration for the CAN
* device.
*
* Return: 0 on success and failure value on error
*/
static int ctucan_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct device *dev = &pdev->dev;
unsigned long driver_data = ent->driver_data;
struct ctucan_pci_board_data *bdata;
void __iomem *addr;
void __iomem *cra_addr;
void __iomem *bar0_base;
u32 cra_a2p_ie;
u32 ctucan_id = 0;
int ret;
unsigned int ntxbufs;
unsigned int num_cores = 1;
unsigned int core_i = 0;
int irq;
int msi_ok = 0;
ret = pci_enable_device(pdev);
if (ret) {
dev_err(dev, "pci_enable_device FAILED\n");
goto err;
}
ret = pci_request_regions(pdev, KBUILD_MODNAME);
if (ret) {
dev_err(dev, "pci_request_regions FAILED\n");
goto err_disable_device;
}
ret = pci_enable_msi(pdev);
if (!ret) {
dev_info(dev, "MSI enabled\n");
pci_set_master(pdev);
msi_ok = 1;
}
dev_info(dev, "ctucan BAR0 0x%08llx 0x%08llx\n",
(long long)pci_resource_start(pdev, 0),
(long long)pci_resource_len(pdev, 0));
dev_info(dev, "ctucan BAR1 0x%08llx 0x%08llx\n",
(long long)pci_resource_start(pdev, 1),
(long long)pci_resource_len(pdev, 1));
addr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
if (!addr) {
dev_err(dev, "PCI BAR 1 cannot be mapped\n");
ret = -ENOMEM;
goto err_release_regions;
}
/* Cyclone IV PCI Express Control Registers Area */
bar0_base = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
if (!bar0_base) {
dev_err(dev, "PCI BAR 0 cannot be mapped\n");
ret = -EIO;
goto err_pci_iounmap_bar1;
}
if (driver_data == CTUCAN_WITHOUT_CTUCAN_ID) {
cra_addr = bar0_base;
num_cores = 2;
} else {
cra_addr = bar0_base + CTUCAN_BAR0_CRA_BASE;
ctucan_id = ioread32(bar0_base + CTUCAN_BAR0_CTUCAN_ID);
dev_info(dev, "ctucan_id 0x%08lx\n", (unsigned long)ctucan_id);
num_cores = ctucan_id & 0xf;
}
irq = pdev->irq;
ntxbufs = 4;
bdata = kzalloc_obj(*bdata);
if (!bdata) {
ret = -ENOMEM;
goto err_pci_iounmap_bar0;
}
INIT_LIST_HEAD(&bdata->ndev_list_head);
bdata->bar0_base = bar0_base;
bdata->cra_base = cra_addr;
bdata->bar1_base = addr;
bdata->use_msi = msi_ok;
pci_set_drvdata(pdev, bdata);
ret = ctucan_probe_common(dev, addr, irq, ntxbufs, 100000000,
0, ctucan_pci_set_drvdata);
if (ret < 0)
goto err_free_board;
core_i++;
while (core_i < num_cores) {
addr += 0x4000;
ret = ctucan_probe_common(dev, addr, irq, ntxbufs, 100000000,
0, ctucan_pci_set_drvdata);
if (ret < 0) {
dev_info(dev, "CTU CAN FD core %d initialization failed\n",
core_i);
break;
}
core_i++;
}
/* enable interrupt in
* Avalon-MM to PCI Express Interrupt Enable Register
*/
cra_a2p_ie = ioread32(cra_addr + CYCLONE_IV_CRA_A2P_IE);
dev_info(dev, "cra_a2p_ie 0x%08x\n", cra_a2p_ie);
cra_a2p_ie |= 1;
iowrite32(cra_a2p_ie, cra_addr + CYCLONE_IV_CRA_A2P_IE);
cra_a2p_ie = ioread32(cra_addr + CYCLONE_IV_CRA_A2P_IE);
dev_info(dev, "cra_a2p_ie 0x%08x\n", cra_a2p_ie);
return 0;
err_free_board:
pci_set_drvdata(pdev, NULL);
kfree(bdata);
err_pci_iounmap_bar0:
pci_iounmap(pdev, bar0_base);
err_pci_iounmap_bar1:
pci_iounmap(pdev, addr);
err_release_regions:
if (msi_ok)
pci_disable_msi(pdev);
pci_release_regions(pdev);
err_disable_device:
pci_disable_device(pdev);
err:
return ret;
}
/**
* ctucan_pci_remove - Unregister the device after releasing the resources
* @pdev: Handle to the pci device structure
*
* This function frees all the resources allocated to the device.
* Return: 0 always
*/
static void ctucan_pci_remove(struct pci_dev *pdev)
{
struct net_device *ndev;
struct ctucan_priv *priv = NULL;
struct ctucan_pci_board_data *bdata = ctucan_pci_get_bdata(pdev);
dev_dbg(&pdev->dev, "ctucan_remove");
if (!bdata) {
dev_err(&pdev->dev, "%s: no list of devices\n", __func__);
return;
}
/* disable interrupt in
* Avalon-MM to PCI Express Interrupt Enable Register
*/
if (bdata->cra_base)
iowrite32(0, bdata->cra_base + CYCLONE_IV_CRA_A2P_IE);
while ((priv = list_first_entry_or_null(&bdata->ndev_list_head, struct ctucan_priv,
peers_on_pdev)) != NULL) {
ndev = priv->can.dev;
unregister_candev(ndev);
netif_napi_del(&priv->napi);
list_del_init(&priv->peers_on_pdev);
free_candev(ndev);
}
pci_iounmap(pdev, bdata->bar1_base);
if (bdata->use_msi)
pci_disable_msi(pdev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_iounmap(pdev, bdata->bar0_base);
pci_set_drvdata(pdev, NULL);
kfree(bdata);
}
static SIMPLE_DEV_PM_OPS(ctucan_pci_pm_ops, ctucan_suspend, ctucan_resume);
static const struct pci_device_id ctucan_pci_tbl[] = {
{PCI_DEVICE_DATA(TEDIA, CTUCAN_VER21,
CTUCAN_WITH_CTUCAN_ID)},
{},
};
MODULE_DEVICE_TABLE(pci, ctucan_pci_tbl);
static struct pci_driver ctucan_pci_driver = {
.name = KBUILD_MODNAME,
.id_table = ctucan_pci_tbl,
.probe = ctucan_pci_probe,
.remove = ctucan_pci_remove,
.driver.pm = &ctucan_pci_pm_ops,
};
module_pci_driver(ctucan_pci_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Pavel Pisa <pisa@cmp.felk.cvut.cz>");
MODULE_DESCRIPTION("CTU CAN FD for PCI bus");
linux-7.2.3/drivers/net/can/ctucanfd/ctucanfd_platform.c
+126
View File
@@ -0,0 +1,126 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*******************************************************************************
*
* CTU CAN FD IP Core
*
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
* Czech Technical University (http://www.cvut.cz/)
******************************************************************************/
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include "ctucanfd.h"
#define DRV_NAME "ctucanfd"
static void ctucan_platform_set_drvdata(struct device *dev,
struct net_device *ndev)
{
struct platform_device *pdev = container_of(dev, struct platform_device,
dev);
platform_set_drvdata(pdev, ndev);
}
/**
* ctucan_platform_probe - Platform registration call
* @pdev: Handle to the platform device structure
*
* This function does all the memory allocation and registration for the CAN
* device.
*
* Return: 0 on success and failure value on error
*/
static int ctucan_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
void __iomem *addr;
int ret;
unsigned int ntxbufs;
int irq;
/* Get the virtual base address for the device */
addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(addr)) {
ret = PTR_ERR(addr);
goto err;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto err;
}
/* Number of tx bufs might be change in HW for future. If so,
* it will be passed as property via device tree
*/
ntxbufs = 4;
ret = ctucan_probe_common(dev, addr, irq, ntxbufs, 0,
1, ctucan_platform_set_drvdata);
if (ret < 0)
platform_set_drvdata(pdev, NULL);
err:
return ret;
}
/**
* ctucan_platform_remove - Unregister the device after releasing the resources
* @pdev: Handle to the platform device structure
*
* This function frees all the resources allocated to the device.
* Return: 0 always
*/
static void ctucan_platform_remove(struct platform_device *pdev)
{
struct net_device *ndev = platform_get_drvdata(pdev);
struct ctucan_priv *priv = netdev_priv(ndev);
netdev_dbg(ndev, "ctucan_remove");
unregister_candev(ndev);
pm_runtime_disable(&pdev->dev);
netif_napi_del(&priv->napi);
free_candev(ndev);
}
static SIMPLE_DEV_PM_OPS(ctucan_platform_pm_ops, ctucan_suspend, ctucan_resume);
/* Match table for OF platform binding */
static const struct of_device_id ctucan_of_match[] = {
{ .compatible = "ctu,ctucanfd-2", },
{ .compatible = "ctu,ctucanfd", },
{ /* end of list */ },
};
MODULE_DEVICE_TABLE(of, ctucan_of_match);
static struct platform_driver ctucanfd_driver = {
.probe = ctucan_platform_probe,
.remove = ctucan_platform_remove,
.driver = {
.name = DRV_NAME,
.pm = &ctucan_platform_pm_ops,
.of_match_table = ctucan_of_match,
},
};
module_platform_driver(ctucanfd_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Martin Jerabek");
MODULE_DESCRIPTION("CTU CAN FD for platform");