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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for Broadcom 10-Gigabit ethernet driver
#
obj-$(CONFIG_BNX2X) += bnx2x.o
bnx2x-y := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o bnx2x_sp.o bnx2x_self_test.o
bnx2x-$(CONFIG_BNX2X_SRIOV) += bnx2x_vfpf.o bnx2x_sriov.o
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.h
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/* bnx2x_dcb.h: QLogic Everest network driver.
*
* Copyright 2009-2013 Broadcom Corporation
* Copyright 2014 QLogic Corporation
* All rights reserved
*
* Unless you and QLogic execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other QLogic software provided under a
* license other than the GPL, without QLogic's express prior written
* consent.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Dmitry Kravkov
*
*/
#ifndef BNX2X_DCB_H
#define BNX2X_DCB_H
#include "bnx2x_hsi.h"
#define LLFC_DRIVER_TRAFFIC_TYPE_MAX 3 /* NW, iSCSI, FCoE */
struct bnx2x_dcbx_app_params {
u32 enabled;
u32 traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
};
#define DCBX_COS_MAX_NUM_E2 DCBX_E2E3_MAX_NUM_COS
/* bnx2x currently limits numbers of supported COSes to 3 to be extended to 6 */
#define BNX2X_MAX_COS_SUPPORT 3
#define DCBX_COS_MAX_NUM_E3B0 BNX2X_MAX_COS_SUPPORT
#define DCBX_COS_MAX_NUM BNX2X_MAX_COS_SUPPORT
struct bnx2x_dcbx_cos_params {
u32 bw_tbl;
u32 pri_bitmask;
/*
* strict priority: valid values are 0..5; 0 is highest priority.
* There can't be two COSes with the same priority.
*/
u8 strict;
#define BNX2X_DCBX_STRICT_INVALID DCBX_COS_MAX_NUM
#define BNX2X_DCBX_STRICT_COS_HIGHEST 0
#define BNX2X_DCBX_STRICT_COS_NEXT_LOWER_PRI(sp) ((sp) + 1)
u8 pauseable;
};
struct bnx2x_dcbx_pg_params {
u32 enabled;
u8 num_of_cos; /* valid COS entries */
struct bnx2x_dcbx_cos_params cos_params[DCBX_COS_MAX_NUM];
};
struct bnx2x_dcbx_pfc_params {
u32 enabled;
u32 priority_non_pauseable_mask;
};
struct bnx2x_dcbx_port_params {
struct bnx2x_dcbx_pfc_params pfc;
struct bnx2x_dcbx_pg_params ets;
struct bnx2x_dcbx_app_params app;
};
#define BNX2X_DCBX_CONFIG_INV_VALUE (0xFFFFFFFF)
#define BNX2X_DCBX_OVERWRITE_SETTINGS_DISABLE 0
#define BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE 1
#define BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID (BNX2X_DCBX_CONFIG_INV_VALUE)
#define BNX2X_IS_ETS_ENABLED(bp) ((bp)->dcb_state == BNX2X_DCB_STATE_ON &&\
(bp)->dcbx_port_params.ets.enabled)
struct bnx2x_config_lldp_params {
u32 overwrite_settings;
u32 msg_tx_hold;
u32 msg_fast_tx;
u32 tx_credit_max;
u32 msg_tx_interval;
u32 tx_fast;
};
struct bnx2x_admin_priority_app_table {
u32 valid;
u32 priority;
#define INVALID_TRAFFIC_TYPE_PRIORITY (0xFFFFFFFF)
u32 traffic_type;
#define TRAFFIC_TYPE_ETH 0
#define TRAFFIC_TYPE_PORT 1
u32 app_id;
};
#define DCBX_CONFIG_MAX_APP_PROTOCOL 4
struct bnx2x_config_dcbx_params {
u32 overwrite_settings;
u32 admin_dcbx_version;
u32 admin_ets_enable;
u32 admin_pfc_enable;
u32 admin_tc_supported_tx_enable;
u32 admin_ets_configuration_tx_enable;
u32 admin_ets_recommendation_tx_enable;
u32 admin_pfc_tx_enable;
u32 admin_application_priority_tx_enable;
u32 admin_ets_willing;
u32 admin_ets_reco_valid;
u32 admin_pfc_willing;
u32 admin_app_priority_willing;
u32 admin_configuration_bw_precentage[8];
u32 admin_configuration_ets_pg[8];
u32 admin_recommendation_bw_precentage[8];
u32 admin_recommendation_ets_pg[8];
u32 admin_pfc_bitmap;
struct bnx2x_admin_priority_app_table
admin_priority_app_table[DCBX_CONFIG_MAX_APP_PROTOCOL];
u32 admin_default_priority;
};
#define GET_FLAGS(flags, bits) ((flags) & (bits))
#define SET_FLAGS(flags, bits) ((flags) |= (bits))
#define RESET_FLAGS(flags, bits) ((flags) &= ~(bits))
enum {
DCBX_READ_LOCAL_MIB,
DCBX_READ_REMOTE_MIB
};
#define ETH_TYPE_FCOE (0x8906)
#define TCP_PORT_ISCSI (0xCBC)
#define PFC_VALUE_FRAME_SIZE (512)
#define PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA(mega_speed) \
((1000 * PFC_VALUE_FRAME_SIZE)/(mega_speed))
#define PFC_BRB1_REG_HIGH_LLFC_LOW_THRESHOLD 130
#define PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD 170
struct cos_entry_help_data {
u32 pri_join_mask;
u32 cos_bw;
u8 strict;
bool pausable;
};
struct cos_help_data {
struct cos_entry_help_data data[DCBX_COS_MAX_NUM];
u8 num_of_cos;
};
#define DCBX_ILLEGAL_PG (0xFF)
#define DCBX_PFC_PRI_MASK (0xFF)
#define DCBX_STRICT_PRIORITY (15)
#define DCBX_INVALID_COS_BW (0xFFFFFFFF)
#define DCBX_PFC_PRI_NON_PAUSE_MASK(bp) \
((bp)->dcbx_port_params.pfc.priority_non_pauseable_mask)
#define DCBX_PFC_PRI_PAUSE_MASK(bp) \
((u8)~DCBX_PFC_PRI_NON_PAUSE_MASK(bp))
#define DCBX_PFC_PRI_GET_PAUSE(bp, pg_pri) \
((pg_pri) & (DCBX_PFC_PRI_PAUSE_MASK(bp)))
#define DCBX_PFC_PRI_GET_NON_PAUSE(bp, pg_pri) \
(DCBX_PFC_PRI_NON_PAUSE_MASK(bp) & (pg_pri))
#define DCBX_IS_PFC_PRI_SOME_PAUSE(bp, pg_pri) \
(0 != DCBX_PFC_PRI_GET_PAUSE(bp, pg_pri))
#define IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pg_pri) \
(pg_pri == DCBX_PFC_PRI_GET_PAUSE((bp), (pg_pri)))
#define IS_DCBX_PFC_PRI_ONLY_NON_PAUSE(bp, pg_pri)\
((pg_pri) == DCBX_PFC_PRI_GET_NON_PAUSE((bp), (pg_pri)))
#define IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pg_pri) \
(!(IS_DCBX_PFC_PRI_ONLY_NON_PAUSE((bp), (pg_pri)) || \
IS_DCBX_PFC_PRI_ONLY_PAUSE((bp), (pg_pri))))
struct pg_entry_help_data {
u8 num_of_dif_pri;
u8 pg;
u32 pg_priority;
};
struct pg_help_data {
struct pg_entry_help_data data[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
u8 num_of_pg;
};
/* forward DCB/PFC related declarations */
struct bnx2x;
void bnx2x_dcbx_update(struct work_struct *work);
void bnx2x_dcbx_init_params(struct bnx2x *bp);
void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on, u32 dcbx_enabled);
enum {
BNX2X_DCBX_STATE_NEG_RECEIVED = 0x1,
BNX2X_DCBX_STATE_TX_PAUSED,
BNX2X_DCBX_STATE_TX_RELEASED
};
void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state);
void bnx2x_dcbx_pmf_update(struct bnx2x *bp);
/* DCB netlink */
#ifdef BCM_DCBNL
extern const struct dcbnl_rtnl_ops bnx2x_dcbnl_ops;
int bnx2x_dcbnl_update_applist(struct bnx2x *bp, bool delall);
#endif /* BCM_DCBNL */
int bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp);
int bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp);
#endif /* BNX2X_DCB_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dump.h
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
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/* bnx2x_fw_defs.h: Qlogic Everest network driver.
*
* Copyright (c) 2007-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*/
#ifndef BNX2X_FW_DEFS_H
#define BNX2X_FW_DEFS_H
#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[151].base + ((assertListEntry) * IRO[151].m1))
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
(IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
IRO[157].m2))
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
(IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
IRO[158].m2))
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
(IRO[163].base + ((funcId) * IRO[163].m1))
#define CSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[153].base + ((funcId) * IRO[153].m1))
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
(IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
(IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
* IRO[142].m2) + ((sbId) * IRO[142].m3))
#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
(IRO[324].base + ((pfId) * IRO[324].m1))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
(IRO[325].base + ((pfId) * IRO[325].m1))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
(IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
(IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
(IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
(IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
(IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
(IRO[322].base + ((pfId) * IRO[322].m1) + ((iscsiEqId) * IRO[322].m2))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
(IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
(IRO[323].base + ((pfId) * IRO[323].m1))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[315].base + ((pfId) * IRO[315].m1))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[314].base + ((pfId) * IRO[314].m1))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[313].base + ((pfId) * IRO[313].m1))
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[155].base + ((funcId) * IRO[155].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
(IRO[146].base + ((pfId) * IRO[146].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
(IRO[147].base + ((pfId) * IRO[147].m1))
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
(IRO[145].base + ((pfId) * IRO[145].m1))
#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
(IRO[148].base + ((pfId) * IRO[148].m1))
#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
(IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
(IRO[137].base + ((sbId) * IRO[137].m1))
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
(IRO[138].base + ((sbId) * IRO[138].m1))
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
(IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
(IRO[136].base + ((sbId) * IRO[136].m1))
#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
(IRO[141].base + ((sbId) * IRO[141].m1))
#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
(IRO[159].base + ((vfId) * IRO[159].m1))
#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
(IRO[160].base + ((vfId) * IRO[160].m1))
#define CSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[154].base + ((funcId) * IRO[154].m1))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
(IRO[207].base + ((pfId) * IRO[207].m1))
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
(IRO[205].base + ((pfId) * IRO[205].m1))
#define TSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[107].base + ((funcId) * IRO[107].m1))
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
(IRO[279].base + ((pfId) * IRO[279].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
(IRO[280].base + ((pfId) * IRO[280].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
(IRO[281].base + ((pfId) * IRO[281].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
(IRO[282].base + ((pfId) * IRO[282].m1))
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[278].base + ((pfId) * IRO[278].m1))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[277].base + ((pfId) * IRO[277].m1))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[276].base + ((pfId) * IRO[276].m1))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
(IRO[275].base + ((pfId) * IRO[275].m1))
#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
(IRO[285].base + ((pfId) * IRO[285].m1))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
(IRO[271].base + ((pfId) * IRO[271].m1))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
(IRO[272].base + ((pfId) * IRO[272].m1))
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
(IRO[273].base + ((pfId) * IRO[273].m1))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
(IRO[274].base + ((pfId) * IRO[274].m1))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
(IRO[206].base + ((pfId) * IRO[206].m1))
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[109].base + ((funcId) * IRO[109].m1))
#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
(IRO[224].base + ((pfId) * IRO[224].m1))
#define TSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[108].base + ((funcId) * IRO[108].m1))
#define USTORM_AGG_DATA_OFFSET (IRO[213].base)
#define USTORM_AGG_DATA_SIZE (IRO[213].size)
#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[180].base + ((assertListEntry) * IRO[180].m1))
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
(IRO[187].base + ((portId) * IRO[187].m1))
#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
(IRO[326].base + ((pfId) * IRO[326].m1))
#define USTORM_FUNC_EN_OFFSET(funcId) \
(IRO[182].base + ((funcId) * IRO[182].m1))
#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
(IRO[290].base + ((pfId) * IRO[290].m1))
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
(IRO[291].base + ((pfId) * IRO[291].m1))
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
(IRO[295].base + ((pfId) * IRO[295].m1))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
(IRO[292].base + ((pfId) * IRO[292].m1))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[288].base + ((pfId) * IRO[288].m1))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[287].base + ((pfId) * IRO[287].m1))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[286].base + ((pfId) * IRO[286].m1))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
(IRO[289].base + ((pfId) * IRO[289].m1))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
(IRO[293].base + ((pfId) * IRO[293].m1))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
(IRO[294].base + ((pfId) * IRO[294].m1))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
(IRO[186].base + ((pfId) * IRO[186].m1))
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[184].base + ((funcId) * IRO[184].m1))
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
(IRO[216].base + ((portId) * IRO[216].m1) + ((clientId) * \
IRO[216].m2))
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
(IRO[217].base + ((qzoneId) * IRO[217].m1))
#define USTORM_TPA_BTR_OFFSET (IRO[214].base)
#define USTORM_TPA_BTR_SIZE (IRO[214].size)
#define USTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[183].base + ((funcId) * IRO[183].m1))
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[50].base + ((assertListEntry) * IRO[50].m1))
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \
(IRO[43].base + ((portId) * IRO[43].m1))
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \
(IRO[45].base + ((pfId) * IRO[45].m1))
#define XSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[47].base + ((funcId) * IRO[47].m1))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
(IRO[303].base + ((pfId) * IRO[303].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
(IRO[306].base + ((pfId) * IRO[306].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
(IRO[307].base + ((pfId) * IRO[307].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
(IRO[308].base + ((pfId) * IRO[308].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
(IRO[309].base + ((pfId) * IRO[309].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
(IRO[310].base + ((pfId) * IRO[310].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
(IRO[311].base + ((pfId) * IRO[311].m1))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
(IRO[312].base + ((pfId) * IRO[312].m1))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[302].base + ((pfId) * IRO[302].m1))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[301].base + ((pfId) * IRO[301].m1))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[300].base + ((pfId) * IRO[300].m1))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
(IRO[305].base + ((pfId) * IRO[305].m1))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
(IRO[304].base + ((pfId) * IRO[304].m1))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
(IRO[299].base + ((pfId) * IRO[299].m1))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
(IRO[298].base + ((pfId) * IRO[298].m1))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
(IRO[297].base + ((pfId) * IRO[297].m1))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
(IRO[296].base + ((pfId) * IRO[296].m1))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
(IRO[44].base + ((pfId) * IRO[44].m1))
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[49].base + ((funcId) * IRO[49].m1))
#define XSTORM_SPQ_DATA_OFFSET(funcId) \
(IRO[32].base + ((funcId) * IRO[32].m1))
#define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \
(IRO[30].base + ((funcId) * IRO[30].m1))
#define XSTORM_SPQ_PROD_OFFSET(funcId) \
(IRO[31].base + ((funcId) * IRO[31].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
(IRO[218].base + ((portId) * IRO[218].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
(IRO[219].base + ((portId) * IRO[219].m1))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
(IRO[221].base + (((pfId)>>1) * IRO[221].m1) + (((pfId)&1) * \
IRO[221].m2))
#define XSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[48].base + ((funcId) * IRO[48].m1))
#define XSTORM_ETH_FUNCTION_INFO_FP_HSI_VALID_E2_OFFSET(fid) \
(IRO[386].base + ((fid) * IRO[386].m1))
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
/* eth hsi version */
#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
/* Ethernet Ring parameters */
#define X_ETH_LOCAL_RING_SIZE 13
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
#define U_ETH_NUM_OF_SGES_TO_FETCH 8
#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE 8
#define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8
/* The fw will padd the buffer with this value, so the IP header \
will be align to 4 Byte */
#define IP_HEADER_ALIGNMENT_PADDING 2
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
#define U_ETH_UNDEFINED_Q 0xFF
#define T_ETH_INDIRECTION_TABLE_SIZE 128
#define T_ETH_RSS_KEY 10
#define ETH_NUM_OF_RSS_ENGINES_E2 72
#define FILTER_RULES_COUNT 16
#define MULTICAST_RULES_COUNT 16
#define CLASSIFY_RULES_COUNT 16
/*The CRC32 seed, that is used for the hash(reduction) multicast address */
#define ETH_CRC32_HASH_SEED 0x00000000
#define ETH_CRC32_HASH_BIT_SIZE (8)
#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
/* Maximal L2 clients supported */
#define ETH_MAX_RX_CLIENTS_E1 18
#define ETH_MAX_RX_CLIENTS_E1H 28
#define ETH_MAX_RX_CLIENTS_E2 152
/* Maximal statistics client Ids */
#define MAX_STAT_COUNTER_ID_E1 36
#define MAX_STAT_COUNTER_ID_E1H 56
#define MAX_STAT_COUNTER_ID_E2 140
#define MAX_MAC_CREDIT_E1 192 /* Per Chip */
#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
#define MAX_MAC_CREDIT_E2 272 /* Per Path */
#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
/* Maximal aggregation queues supported */
#define ETH_MAX_AGGREGATION_QUEUES_E1 32
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
#define ETH_NUM_OF_MCAST_BINS 256
#define ETH_NUM_OF_MCAST_ENGINES_E2 72
#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
#define ETH_MIN_RX_CQES_WITH_TPA_E1 \
(ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
#define DISABLE_STATISTIC_COUNTER_ID_VALUE 0
/* This file defines HSI constants common to all microcode flows */
#define PROTOCOL_STATE_BIT_OFFSET 6
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
/* microcode fixed page size 4K (chains and ring segments) */
#define MC_PAGE_SIZE 4096
/* Number of indices per slow-path SB */
#define HC_SP_SB_MAX_INDICES 16
/* Number of indices per SB */
#define HC_SB_MAX_INDICES_E1X 8
#define HC_SB_MAX_INDICES_E2 8
#define HC_SB_MAX_SB_E1X 32
#define HC_SB_MAX_SB_E2 136
#define HC_SP_SB_ID 0xde
#define HC_SB_MAX_SM 2
#define HC_SB_MAX_DYNAMIC_INDICES 4
/* max number of slow path commands per port */
#define MAX_RAMRODS_PER_PORT 8
/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
#define TIMERS_TICK_SIZE_CHIP (1e-3)
#define TSEMI_CLK1_RESUL_CHIP (1e-3)
#define XSEMI_CLK1_RESUL_CHIP (1e-3)
#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
#define XSTORM_IP_ID_ROLL_HALF 0x8000
#define XSTORM_IP_ID_ROLL_ALL 0
#define FW_LOG_LIST_SIZE 50
#define NUM_OF_SAFC_BITS 16
#define MAX_COS_NUMBER 4
#define MAX_TRAFFIC_TYPES 8
#define MAX_PFC_PRIORITIES 8
#define MAX_VLAN_PRIORITIES 8
/* used by array traffic_type_to_priority[] to mark traffic type \
that is not mapped to priority*/
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
#define C_ERES_PER_PAGE \
(PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
#define STATS_QUERY_CMD_COUNT 16
#define AFEX_LIST_TABLE_SIZE 4096
#define INVALID_VNIC_ID 0xFF
#define UNDEF_IRO 0x80000000
/* used for defining the amount of FCoE tasks supported for PF */
#define MAX_FCOE_FUNCS_PER_ENGINE 2
#define MAX_NUM_FCOE_TASKS_PER_ENGINE 4096
#endif /* BNX2X_FW_DEFS_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_file_hdr.h
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/* bnx2x_fw_file_hdr.h: FW binary file header structure.
*
* Copyright (c) 2007-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Vladislav Zolotarov
* Based on the original idea of John Wright <john.wright@hp.com>.
*/
#ifndef BNX2X_INIT_FILE_HDR_H
#define BNX2X_INIT_FILE_HDR_H
struct bnx2x_fw_file_section {
__be32 len;
__be32 offset;
};
struct bnx2x_fw_file_hdr {
struct bnx2x_fw_file_section init_ops;
struct bnx2x_fw_file_section init_ops_offsets;
struct bnx2x_fw_file_section init_data;
struct bnx2x_fw_file_section tsem_int_table_data;
struct bnx2x_fw_file_section tsem_pram_data;
struct bnx2x_fw_file_section usem_int_table_data;
struct bnx2x_fw_file_section usem_pram_data;
struct bnx2x_fw_file_section csem_int_table_data;
struct bnx2x_fw_file_section csem_pram_data;
struct bnx2x_fw_file_section xsem_int_table_data;
struct bnx2x_fw_file_section xsem_pram_data;
struct bnx2x_fw_file_section iro_arr;
struct bnx2x_fw_file_section fw_version;
};
#endif /* BNX2X_INIT_FILE_HDR_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
+6048
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
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/* bnx2x_init.h: Qlogic Everest network driver.
* Structures and macroes needed during the initialization.
*
* Copyright (c) 2007-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Eliezer Tamir
* Modified by: Vladislav Zolotarov
*/
#ifndef BNX2X_INIT_H
#define BNX2X_INIT_H
/* Init operation types and structures */
enum {
OP_RD = 0x1, /* read a single register */
OP_WR, /* write a single register */
OP_SW, /* copy a string to the device */
OP_ZR, /* clear memory */
OP_ZP, /* unzip then copy with DMAE */
OP_WR_64, /* write 64 bit pattern */
OP_WB, /* copy a string using DMAE */
OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
/* Skip the following ops if all of the init modes don't match */
OP_IF_MODE_OR,
/* Skip the following ops if any of the init modes don't match */
OP_IF_MODE_AND,
OP_MAX
};
enum {
STAGE_START,
STAGE_END,
};
/* Returns the index of start or end of a specific block stage in ops array*/
#define BLOCK_OPS_IDX(block, stage, end) \
(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
/* structs for the various opcodes */
struct raw_op {
u32 op:8;
u32 offset:24;
u32 raw_data;
};
struct op_read {
u32 op:8;
u32 offset:24;
u32 val;
};
struct op_write {
u32 op:8;
u32 offset:24;
u32 val;
};
struct op_arr_write {
u32 op:8;
u32 offset:24;
#ifdef __BIG_ENDIAN
u16 data_len;
u16 data_off;
#else /* __LITTLE_ENDIAN */
u16 data_off;
u16 data_len;
#endif
};
struct op_zero {
u32 op:8;
u32 offset:24;
u32 len;
};
struct op_if_mode {
u32 op:8;
u32 cmd_offset:24;
u32 mode_bit_map;
};
union init_op {
struct op_read read;
struct op_write write;
struct op_arr_write arr_wr;
struct op_zero zero;
struct raw_op raw;
struct op_if_mode if_mode;
};
/* Init Phases */
enum {
PHASE_COMMON,
PHASE_PORT0,
PHASE_PORT1,
PHASE_PF0,
PHASE_PF1,
PHASE_PF2,
PHASE_PF3,
PHASE_PF4,
PHASE_PF5,
PHASE_PF6,
PHASE_PF7,
NUM_OF_INIT_PHASES
};
/* Init Modes */
enum {
MODE_ASIC = 0x00000001,
MODE_FPGA = 0x00000002,
MODE_EMUL = 0x00000004,
MODE_E2 = 0x00000008,
MODE_E3 = 0x00000010,
MODE_PORT2 = 0x00000020,
MODE_PORT4 = 0x00000040,
MODE_SF = 0x00000080,
MODE_MF = 0x00000100,
MODE_MF_SD = 0x00000200,
MODE_MF_SI = 0x00000400,
MODE_MF_AFEX = 0x00000800,
MODE_E3_A0 = 0x00001000,
MODE_E3_B0 = 0x00002000,
MODE_COS3 = 0x00004000,
MODE_COS6 = 0x00008000,
MODE_LITTLE_ENDIAN = 0x00010000,
MODE_BIG_ENDIAN = 0x00020000,
};
/* Init Blocks */
enum {
BLOCK_ATC,
BLOCK_BRB1,
BLOCK_CCM,
BLOCK_CDU,
BLOCK_CFC,
BLOCK_CSDM,
BLOCK_CSEM,
BLOCK_DBG,
BLOCK_DMAE,
BLOCK_DORQ,
BLOCK_HC,
BLOCK_IGU,
BLOCK_MISC,
BLOCK_NIG,
BLOCK_PBF,
BLOCK_PGLUE_B,
BLOCK_PRS,
BLOCK_PXP2,
BLOCK_PXP,
BLOCK_QM,
BLOCK_SRC,
BLOCK_TCM,
BLOCK_TM,
BLOCK_TSDM,
BLOCK_TSEM,
BLOCK_UCM,
BLOCK_UPB,
BLOCK_USDM,
BLOCK_USEM,
BLOCK_XCM,
BLOCK_XPB,
BLOCK_XSDM,
BLOCK_XSEM,
BLOCK_MISC_AEU,
NUM_OF_INIT_BLOCKS
};
/* QM queue numbers */
#define BNX2X_ETH_Q 0
#define BNX2X_TOE_Q 3
#define BNX2X_TOE_ACK_Q 6
#define BNX2X_ISCSI_Q 9
#define BNX2X_ISCSI_ACK_Q 11
#define BNX2X_FCOE_Q 10
/* Vnics per mode */
#define BNX2X_PORT2_MODE_NUM_VNICS 4
#define BNX2X_PORT4_MODE_NUM_VNICS 2
/* COS offset for port1 in E3 B0 4port mode */
#define BNX2X_E3B0_PORT1_COS_OFFSET 3
/* QM Register addresses */
#define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
#define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
#define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
/* extracts the QM queue number for the specified port and vnic */
#define BNX2X_PF_Q_NUM(q_num, port, vnic)\
((((port) << 1) | (vnic)) * 16 + (q_num))
/* Maps the specified queue to the specified COS */
static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)
{
/* find current COS mapping */
u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
/* check if queue->COS mapping has changed */
if (curr_cos != new_cos) {
u32 num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
u32 reg_addr, reg_bit_map, vnic;
/* update parameters for 4port mode */
if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
if (BP_PORT(bp)) {
curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
}
}
/* change queue mapping for each VNIC */
for (vnic = 0; vnic < num_vnics; vnic++) {
u32 pf_q_num =
BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
u32 q_bit_map = 1 << (pf_q_num & 0x1f);
/* overwrite queue->VOQ mapping */
REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
/* clear queue bit from current COS bit map */
reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
reg_bit_map = REG_RD(bp, reg_addr);
REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
/* set queue bit in new COS bit map */
reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
reg_bit_map = REG_RD(bp, reg_addr);
REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
/* set/clear queue bit in command-queue bit map
* (E2/E3A0 only, valid COS values are 0/1)
*/
if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
reg_bit_map = REG_RD(bp, reg_addr);
q_bit_map = 1 << (2 * (pf_q_num & 0xf));
reg_bit_map = new_cos ?
(reg_bit_map | q_bit_map) :
(reg_bit_map & (~q_bit_map));
REG_WR(bp, reg_addr, reg_bit_map);
}
}
}
}
/* Configures the QM according to the specified per-traffic-type COSes */
static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,
struct priority_cos *traffic_cos)
{
bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
if (mode != STATIC_COS) {
/* required only in backward compatible COS mode */
bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
}
}
/* congestion management port init api description
* the api works as follows:
* the driver should pass the cmng_init_input struct, the port_init function
* will prepare the required internal ram structure which will be passed back
* to the driver (cmng_init) that will write it into the internal ram.
*
* IMPORTANT REMARKS:
* 1. the cmng_init struct does not represent the contiguous internal ram
* structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
* offset in order to write the port sub struct and the
* PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
* words - don't use memcpy!).
* 2. although the cmng_init struct is filled for the maximal vnic number
* possible, the driver should only write the valid vnics into the internal
* ram according to the appropriate port mode.
*/
/* CMNG constants, as derived from system spec calculations */
/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
#define DEF_MIN_RATE 100
/* resolution of the rate shaping timer - 400 usec */
#define RS_PERIODIC_TIMEOUT_USEC 400
/* number of bytes in single QM arbitration cycle -
* coefficient for calculating the fairness timer
*/
#define QM_ARB_BYTES 160000
/* resolution of Min algorithm 1:100 */
#define MIN_RES 100
/* how many bytes above threshold for
* the minimal credit of Min algorithm
*/
#define MIN_ABOVE_THRESH 32768
/* Fairness algorithm integration time coefficient -
* for calculating the actual Tfair
*/
#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
/* Memory of fairness algorithm - 2 cycles */
#define FAIR_MEM 2
#define SAFC_TIMEOUT_USEC 52
#define SDM_TICKS 4
static inline void bnx2x_init_max(const struct cmng_init_input *input_data,
u32 r_param, struct cmng_init *ram_data)
{
u32 vnic;
struct cmng_vnic *vdata = &ram_data->vnic;
struct cmng_struct_per_port *pdata = &ram_data->port;
/* rate shaping per-port variables
* 100 micro seconds in SDM ticks = 25
* since each tick is 4 microSeconds
*/
pdata->rs_vars.rs_periodic_timeout =
RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
/* this is the threshold below which no timer arming will occur.
* 1.25 coefficient is for the threshold to be a little bigger
* then the real time to compensate for timer in-accuracy
*/
pdata->rs_vars.rs_threshold =
(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
/* rate shaping per-vnic variables */
for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
/* global vnic counter */
vdata->vnic_max_rate[vnic].vn_counter.rate =
input_data->vnic_max_rate[vnic];
/* maximal Mbps for this vnic
* the quota in each timer period - number of bytes
* transmitted in this period
*/
vdata->vnic_max_rate[vnic].vn_counter.quota =
RS_PERIODIC_TIMEOUT_USEC *
(u32)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
}
}
static inline void bnx2x_init_min(const struct cmng_init_input *input_data,
u32 r_param, struct cmng_init *ram_data)
{
u32 vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
struct cmng_vnic *vdata = &ram_data->vnic;
struct cmng_struct_per_port *pdata = &ram_data->port;
/* this is the resolution of the fairness timer */
fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
/* fairness per-port variables
* for 10G it is 1000usec. for 1G it is 10000usec.
*/
tFair = T_FAIR_COEF / input_data->port_rate;
/* this is the threshold below which we won't arm the timer anymore */
pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
/* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
* to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
*/
pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
/* since each tick is 4 microSeconds */
pdata->fair_vars.fairness_timeout =
fair_periodic_timeout_usec / SDM_TICKS;
/* calculate sum of weights */
vnicWeightSum = 0;
for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++)
vnicWeightSum += input_data->vnic_min_rate[vnic];
/* global vnic counter */
if (vnicWeightSum > 0) {
/* fairness per-vnic variables */
for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
/* this is the credit for each period of the fairness
* algorithm - number of bytes in T_FAIR (this vnic
* share of the port rate)
*/
vdata->vnic_min_rate[vnic].vn_credit_delta =
(u32)input_data->vnic_min_rate[vnic] * 100 *
(T_FAIR_COEF / (8 * 100 * vnicWeightSum));
if (vdata->vnic_min_rate[vnic].vn_credit_delta <
pdata->fair_vars.fair_threshold +
MIN_ABOVE_THRESH) {
vdata->vnic_min_rate[vnic].vn_credit_delta =
pdata->fair_vars.fair_threshold +
MIN_ABOVE_THRESH;
}
}
}
}
static inline void bnx2x_init_fw_wrr(const struct cmng_init_input *input_data,
u32 r_param, struct cmng_init *ram_data)
{
u32 vnic, cos;
u32 cosWeightSum = 0;
struct cmng_vnic *vdata = &ram_data->vnic;
struct cmng_struct_per_port *pdata = &ram_data->port;
for (cos = 0; cos < MAX_COS_NUMBER; cos++)
cosWeightSum += input_data->cos_min_rate[cos];
if (cosWeightSum > 0) {
for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
/* Since cos and vnic shouldn't work together the rate
* to divide between the coses is the port rate.
*/
u32 *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
/* this is the credit for each period of
* the fairness algorithm - number of bytes
* in T_FAIR (this cos share of the vnic rate)
*/
ccd[cos] =
(u32)input_data->cos_min_rate[cos] * 100 *
(T_FAIR_COEF / (8 * 100 * cosWeightSum));
if (ccd[cos] < pdata->fair_vars.fair_threshold
+ MIN_ABOVE_THRESH) {
ccd[cos] =
pdata->fair_vars.fair_threshold +
MIN_ABOVE_THRESH;
}
}
}
}
}
static inline void bnx2x_init_safc(const struct cmng_init_input *input_data,
struct cmng_init *ram_data)
{
/* in microSeconds */
ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
}
/* Congestion management port init */
static inline void bnx2x_init_cmng(const struct cmng_init_input *input_data,
struct cmng_init *ram_data)
{
u32 r_param;
memset(ram_data, 0, sizeof(struct cmng_init));
ram_data->port.flags = input_data->flags;
/* number of bytes transmitted in a rate of 10Gbps
* in one usec = 1.25KB.
*/
r_param = BITS_TO_BYTES(input_data->port_rate);
bnx2x_init_max(input_data, r_param, ram_data);
bnx2x_init_min(input_data, r_param, ram_data);
bnx2x_init_fw_wrr(input_data, r_param, ram_data);
bnx2x_init_safc(input_data, ram_data);
}
/* Returns the index of start or end of a specific block stage in ops array */
#define BLOCK_OPS_IDX(block, stage, end) \
(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
#define INITOP_SET 0 /* set the HW directly */
#define INITOP_CLEAR 1 /* clear the HW directly */
#define INITOP_INIT 2 /* set the init-value array */
/****************************************************************************
* ILT management
****************************************************************************/
struct ilt_line {
dma_addr_t page_mapping;
void *page;
u32 size;
};
struct ilt_client_info {
u32 page_size;
u16 start;
u16 end;
u16 client_num;
u16 flags;
#define ILT_CLIENT_SKIP_INIT 0x1
#define ILT_CLIENT_SKIP_MEM 0x2
};
struct bnx2x_ilt {
u32 start_line;
struct ilt_line *lines;
struct ilt_client_info clients[4];
#define ILT_CLIENT_CDU 0
#define ILT_CLIENT_QM 1
#define ILT_CLIENT_SRC 2
#define ILT_CLIENT_TM 3
};
/****************************************************************************
* SRC configuration
****************************************************************************/
struct src_ent {
u8 opaque[56];
u64 next;
};
/****************************************************************************
* Parity configuration
****************************************************************************/
#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK, \
block##_REG_##block##_PRTY_STS_CLR, \
en_mask, {m1, m1h, m2, m3}, #block \
}
#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_0, \
block##_REG_##block##_PRTY_STS_CLR_0, \
en_mask, {m1, m1h, m2, m3}, #block"_0" \
}
#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_1, \
block##_REG_##block##_PRTY_STS_CLR_1, \
en_mask, {m1, m1h, m2, m3}, #block"_1" \
}
static const struct {
u32 mask_addr;
u32 sts_clr_addr;
u32 en_mask; /* Mask to enable parity attentions */
struct {
u32 e1; /* 57710 */
u32 e1h; /* 57711 */
u32 e2; /* 57712 */
u32 e3; /* 578xx */
} reg_mask; /* Register mask (all valid bits) */
char name[8]; /* Block's longest name is 7 characters long
* (name + suffix)
*/
} bnx2x_blocks_parity_data[] = {
/* bit 19 masked */
/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
/* bit 5,18,20-31 */
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
/* bit 5 */
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
* want to handle "system kill" flow at the moment.
*/
BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
0x7ffffff),
BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
{0xf, 0xf, 0xf, 0xf}, "UPB"},
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
{0xf, 0xf, 0xf, 0xf}, "XPB"},
BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
};
/* [28] MCP Latched rom_parity
* [29] MCP Latched ump_rx_parity
* [30] MCP Latched ump_tx_parity
* [31] MCP Latched scpad_parity
*/
#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
(MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
/* Below registers control the MCP parity attention output. When
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
* enabled, when cleared - disabled.
*/
static const struct {
u32 addr;
u32 bits;
} mcp_attn_ctl_regs[] = {
{ MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
MISC_AEU_ENABLE_MCP_PRTY_BITS },
{ MISC_REG_AEU_ENABLE4_NIG_0,
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
{ MISC_REG_AEU_ENABLE4_PXP_0,
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
{ MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
MISC_AEU_ENABLE_MCP_PRTY_BITS },
{ MISC_REG_AEU_ENABLE4_NIG_1,
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
{ MISC_REG_AEU_ENABLE4_PXP_1,
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
};
static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
{
int i;
u32 reg_val;
for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
if (enable)
reg_val |= mcp_attn_ctl_regs[i].bits;
else
reg_val &= ~mcp_attn_ctl_regs[i].bits;
REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
}
}
static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
{
if (CHIP_IS_E1(bp))
return bnx2x_blocks_parity_data[idx].reg_mask.e1;
else if (CHIP_IS_E1H(bp))
return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
else if (CHIP_IS_E2(bp))
return bnx2x_blocks_parity_data[idx].reg_mask.e2;
else /* CHIP_IS_E3 */
return bnx2x_blocks_parity_data[idx].reg_mask.e3;
}
static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
{
int i;
for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
if (dis_mask) {
REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
dis_mask);
DP(NETIF_MSG_HW, "Setting parity mask "
"for %s to\t\t0x%x\n",
bnx2x_blocks_parity_data[i].name, dis_mask);
}
}
/* Disable MCP parity attentions */
bnx2x_set_mcp_parity(bp, false);
}
/* Clear the parity error status registers. */
static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
{
int i;
u32 reg_val, mcp_aeu_bits =
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
/* Clear SEM_FAST parities */
REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
if (reg_mask) {
reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
sts_clr_addr);
if (reg_val & reg_mask)
DP(NETIF_MSG_HW,
"Parity errors in %s: 0x%x\n",
bnx2x_blocks_parity_data[i].name,
reg_val & reg_mask);
}
}
/* Check if there were parity attentions in MCP */
reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
if (reg_val & mcp_aeu_bits)
DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
reg_val & mcp_aeu_bits);
/* Clear parity attentions in MCP:
* [7] clears Latched rom_parity
* [8] clears Latched ump_rx_parity
* [9] clears Latched ump_tx_parity
* [10] clears Latched scpad_parity (both ports)
*/
REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
}
static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
{
int i;
for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
if (reg_mask)
REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
bnx2x_blocks_parity_data[i].en_mask & reg_mask);
}
/* Enable MCP parity attentions */
bnx2x_set_mcp_parity(bp, true);
}
#endif /* BNX2X_INIT_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h
+938
View File
@@ -0,0 +1,938 @@
/* bnx2x_init_ops.h: Qlogic Everest network driver.
* Static functions needed during the initialization.
* This file is "included" in bnx2x_main.c.
*
* Copyright (c) 2007-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Vladislav Zolotarov
*/
#ifndef BNX2X_INIT_OPS_H
#define BNX2X_INIT_OPS_H
#ifndef BP_ILT
#define BP_ILT(bp) NULL
#endif
#ifndef BP_FUNC
#define BP_FUNC(bp) 0
#endif
#ifndef BP_PORT
#define BP_PORT(bp) 0
#endif
#ifndef BNX2X_ILT_FREE
#define BNX2X_ILT_FREE(x, y, sz)
#endif
#ifndef BNX2X_ILT_ZALLOC
#define BNX2X_ILT_ZALLOC(x, y, sz)
#endif
#ifndef ILOG2
#define ILOG2(x) x
#endif
static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
dma_addr_t phys_addr, u32 addr,
u32 len);
static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr,
const u32 *data, u32 len)
{
u32 i;
for (i = 0; i < len; i++)
REG_WR(bp, addr + i*4, data[i]);
}
static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr,
const u32 *data, u32 len)
{
u32 i;
for (i = 0; i < len; i++)
bnx2x_reg_wr_ind(bp, addr + i*4, data[i]);
}
static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len,
u8 wb)
{
if (bp->dmae_ready)
bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
/* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
else if (wb && CHIP_IS_E1(bp))
bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
else
bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
}
static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill,
u32 len, u8 wb)
{
u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
u32 buf_len32 = buf_len/4;
u32 i;
memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
for (i = 0; i < len; i += buf_len32) {
u32 cur_len = min(buf_len32, len - i);
bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb);
}
}
static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
{
if (bp->dmae_ready)
bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
/* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
else if (CHIP_IS_E1(bp))
bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
else
bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
}
static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr,
const u32 *data, u32 len64)
{
u32 buf_len32 = FW_BUF_SIZE/4;
u32 len = len64*2;
u64 data64 = 0;
u32 i;
/* 64 bit value is in a blob: first low DWORD, then high DWORD */
data64 = HILO_U64((*(data + 1)), (*data));
len64 = min((u32)(FW_BUF_SIZE/8), len64);
for (i = 0; i < len64; i++) {
u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
*pdata = data64;
}
for (i = 0; i < len; i += buf_len32) {
u32 cur_len = min(buf_len32, len - i);
bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len);
}
}
/*********************************************************
There are different blobs for each PRAM section.
In addition, each blob write operation is divided into a few operations
in order to decrease the amount of phys. contiguous buffer needed.
Thus, when we select a blob the address may be with some offset
from the beginning of PRAM section.
The same holds for the INT_TABLE sections.
**********************************************************/
#define IF_IS_INT_TABLE_ADDR(base, addr) \
if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
#define IF_IS_PRAM_ADDR(base, addr) \
if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr,
const u8 *data)
{
IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
data = INIT_TSEM_INT_TABLE_DATA(bp);
else
IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
data = INIT_CSEM_INT_TABLE_DATA(bp);
else
IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
data = INIT_USEM_INT_TABLE_DATA(bp);
else
IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
data = INIT_XSEM_INT_TABLE_DATA(bp);
else
IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
data = INIT_TSEM_PRAM_DATA(bp);
else
IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
data = INIT_CSEM_PRAM_DATA(bp);
else
IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
data = INIT_USEM_PRAM_DATA(bp);
else
IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
data = INIT_XSEM_PRAM_DATA(bp);
return data;
}
static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr,
const u32 *data, u32 len)
{
if (bp->dmae_ready)
VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
/* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
else if (CHIP_IS_E1(bp))
bnx2x_init_ind_wr(bp, addr, data, len);
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
else
bnx2x_init_str_wr(bp, addr, data, len);
}
static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo,
u32 val_hi)
{
u32 wb_write[2];
wb_write[0] = val_lo;
wb_write[1] = val_hi;
REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
}
static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len,
u32 blob_off)
{
const u8 *data = NULL;
int rc;
u32 i;
data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
rc = bnx2x_gunzip(bp, data, len);
if (rc)
return;
/* gunzip_outlen is in dwords */
len = GUNZIP_OUTLEN(bp);
for (i = 0; i < len; i++)
((u32 *)GUNZIP_BUF(bp))[i] = (__force u32)
cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
bnx2x_write_big_buf_wb(bp, addr, len);
}
static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
{
u16 op_start =
INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
STAGE_START)];
u16 op_end =
INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
STAGE_END)];
const union init_op *op;
u32 op_idx, op_type, addr, len;
const u32 *data, *data_base;
/* If empty block */
if (op_start == op_end)
return;
data_base = INIT_DATA(bp);
for (op_idx = op_start; op_idx < op_end; op_idx++) {
op = (const union init_op *)&(INIT_OPS(bp)[op_idx]);
/* Get generic data */
op_type = op->raw.op;
addr = op->raw.offset;
/* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
* OP_WR64 (we assume that op_arr_write and op_write have the
* same structure).
*/
len = op->arr_wr.data_len;
data = data_base + op->arr_wr.data_off;
switch (op_type) {
case OP_RD:
REG_RD(bp, addr);
break;
case OP_WR:
REG_WR(bp, addr, op->write.val);
break;
case OP_SW:
bnx2x_init_str_wr(bp, addr, data, len);
break;
case OP_WB:
bnx2x_init_wr_wb(bp, addr, data, len);
break;
case OP_ZR:
bnx2x_init_fill(bp, addr, 0, op->zero.len, 0);
break;
case OP_WB_ZR:
bnx2x_init_fill(bp, addr, 0, op->zero.len, 1);
break;
case OP_ZP:
bnx2x_init_wr_zp(bp, addr, len,
op->arr_wr.data_off);
break;
case OP_WR_64:
bnx2x_init_wr_64(bp, addr, data, len);
break;
case OP_IF_MODE_AND:
/* if any of the flags doesn't match, skip the
* conditional block.
*/
if ((INIT_MODE_FLAGS(bp) &
op->if_mode.mode_bit_map) !=
op->if_mode.mode_bit_map)
op_idx += op->if_mode.cmd_offset;
break;
case OP_IF_MODE_OR:
/* if all the flags don't match, skip the conditional
* block.
*/
if ((INIT_MODE_FLAGS(bp) &
op->if_mode.mode_bit_map) == 0)
op_idx += op->if_mode.cmd_offset;
break;
default:
/* Should never get here! */
break;
}
}
}
/****************************************************************************
* PXP Arbiter
****************************************************************************/
/*
* This code configures the PCI read/write arbiter
* which implements a weighted round robin
* between the virtual queues in the chip.
*
* The values were derived for each PCI max payload and max request size.
* since max payload and max request size are only known at run time,
* this is done as a separate init stage.
*/
#define NUM_WR_Q 13
#define NUM_RD_Q 29
#define MAX_RD_ORD 3
#define MAX_WR_ORD 2
/* configuration for one arbiter queue */
struct arb_line {
int l;
int add;
int ubound;
};
/* derived configuration for each read queue for each max request size */
static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
};
/* derived configuration for each write queue for each max request size */
static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
};
/* register addresses for read queues */
static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
PXP2_REG_RQ_BW_RD_UBOUND0},
{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
PXP2_REG_PSWRQ_BW_UB1},
{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
PXP2_REG_PSWRQ_BW_UB2},
{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
PXP2_REG_PSWRQ_BW_UB3},
{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
PXP2_REG_RQ_BW_RD_UBOUND4},
{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
PXP2_REG_RQ_BW_RD_UBOUND5},
{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
PXP2_REG_PSWRQ_BW_UB6},
{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
PXP2_REG_PSWRQ_BW_UB7},
{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
PXP2_REG_PSWRQ_BW_UB8},
/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
PXP2_REG_PSWRQ_BW_UB9},
{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
PXP2_REG_PSWRQ_BW_UB10},
{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
PXP2_REG_PSWRQ_BW_UB11},
{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
PXP2_REG_RQ_BW_RD_UBOUND12},
{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
PXP2_REG_RQ_BW_RD_UBOUND13},
{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
PXP2_REG_RQ_BW_RD_UBOUND14},
{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
PXP2_REG_RQ_BW_RD_UBOUND15},
{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
PXP2_REG_RQ_BW_RD_UBOUND16},
{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
PXP2_REG_RQ_BW_RD_UBOUND17},
{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
PXP2_REG_RQ_BW_RD_UBOUND18},
/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
PXP2_REG_RQ_BW_RD_UBOUND19},
{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
PXP2_REG_RQ_BW_RD_UBOUND20},
{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
PXP2_REG_RQ_BW_RD_UBOUND22},
{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
PXP2_REG_RQ_BW_RD_UBOUND23},
{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
PXP2_REG_RQ_BW_RD_UBOUND24},
{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
PXP2_REG_RQ_BW_RD_UBOUND25},
{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
PXP2_REG_RQ_BW_RD_UBOUND26},
{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
PXP2_REG_RQ_BW_RD_UBOUND27},
{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
PXP2_REG_PSWRQ_BW_UB28}
};
/* register addresses for write queues */
static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
PXP2_REG_PSWRQ_BW_UB1},
{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
PXP2_REG_PSWRQ_BW_UB2},
{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
PXP2_REG_PSWRQ_BW_UB3},
{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
PXP2_REG_PSWRQ_BW_UB6},
{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
PXP2_REG_PSWRQ_BW_UB7},
{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
PXP2_REG_PSWRQ_BW_UB8},
{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
PXP2_REG_PSWRQ_BW_UB9},
{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
PXP2_REG_PSWRQ_BW_UB10},
{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
PXP2_REG_PSWRQ_BW_UB11},
/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
PXP2_REG_PSWRQ_BW_UB28},
{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
PXP2_REG_RQ_BW_WR_UBOUND29},
{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
PXP2_REG_RQ_BW_WR_UBOUND30}
};
static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order,
int w_order)
{
u32 val, i;
if (r_order > MAX_RD_ORD) {
DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
r_order, MAX_RD_ORD);
r_order = MAX_RD_ORD;
}
if (w_order > MAX_WR_ORD) {
DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
w_order, MAX_WR_ORD);
w_order = MAX_WR_ORD;
}
if (CHIP_REV_IS_FPGA(bp)) {
DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
w_order = 0;
}
DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
for (i = 0; i < NUM_RD_Q-1; i++) {
REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
REG_WR(bp, read_arb_addr[i].add,
read_arb_data[i][r_order].add);
REG_WR(bp, read_arb_addr[i].ubound,
read_arb_data[i][r_order].ubound);
}
for (i = 0; i < NUM_WR_Q-1; i++) {
if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
(write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
REG_WR(bp, write_arb_addr[i].l,
write_arb_data[i][w_order].l);
REG_WR(bp, write_arb_addr[i].add,
write_arb_data[i][w_order].add);
REG_WR(bp, write_arb_addr[i].ubound,
write_arb_data[i][w_order].ubound);
} else {
val = REG_RD(bp, write_arb_addr[i].l);
REG_WR(bp, write_arb_addr[i].l,
val | (write_arb_data[i][w_order].l << 10));
val = REG_RD(bp, write_arb_addr[i].add);
REG_WR(bp, write_arb_addr[i].add,
val | (write_arb_data[i][w_order].add << 10));
val = REG_RD(bp, write_arb_addr[i].ubound);
REG_WR(bp, write_arb_addr[i].ubound,
val | (write_arb_data[i][w_order].ubound << 7));
}
}
val = write_arb_data[NUM_WR_Q-1][w_order].add;
val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
val = read_arb_data[NUM_RD_Q-1][r_order].add;
val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD))
REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
if (CHIP_IS_E3(bp))
REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
else if (CHIP_IS_E2(bp))
REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
else
REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
if (!CHIP_IS_E1(bp)) {
/* MPS w_order optimal TH presently TH
* 128 0 0 2
* 256 1 1 3
* >=512 2 2 3
*/
/* DMAE is special */
if (!CHIP_IS_E1H(bp)) {
/* E2 can use optimal TH */
val = w_order;
REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val);
} else {
val = ((w_order == 0) ? 2 : 3);
REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2);
}
REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
}
/* Validate number of tags suppoted by device */
#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
val &= 0xFF;
if (val <= 0x20)
REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
}
/****************************************************************************
* ILT management
****************************************************************************/
/*
* This codes hides the low level HW interaction for ILT management and
* configuration. The API consists of a shadow ILT table which is set by the
* driver and a set of routines to use it to configure the HW.
*
*/
/* ILT HW init operations */
/* ILT memory management operations */
#define ILT_MEMOP_ALLOC 0
#define ILT_MEMOP_FREE 1
/* the phys address is shifted right 12 bits and has an added
* 1=valid bit added to the 53rd bit
* then since this is a wide register(TM)
* we split it into two 32 bit writes
*/
#define ILT_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
#define ILT_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
#define ILT_RANGE(f, l) (((l) << 10) | f)
static int bnx2x_ilt_line_mem_op(struct bnx2x *bp,
struct ilt_line *line, u32 size, u8 memop)
{
if (memop == ILT_MEMOP_FREE) {
BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
return 0;
}
BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
if (!line->page)
return -1;
line->size = size;
return 0;
}
static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num,
u8 memop)
{
int i, rc;
struct bnx2x_ilt *ilt = BP_ILT(bp);
struct ilt_client_info *ilt_cli;
if (!ilt || !ilt->lines)
return -1;
ilt_cli = &ilt->clients[cli_num];
if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
return 0;
for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
ilt_cli->page_size, memop);
}
return rc;
}
static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, u8 memop)
{
int rc = 0;
if (CONFIGURE_NIC_MODE(bp))
rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
if (!rc)
rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
return rc;
}
static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop)
{
int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
if (!rc)
rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
if (!rc && CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
return rc;
}
static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
dma_addr_t page_mapping)
{
u32 reg;
if (CHIP_IS_E1(bp))
reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
else
reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
}
static void bnx2x_ilt_line_init_op(struct bnx2x *bp,
struct bnx2x_ilt *ilt, int idx, u8 initop)
{
dma_addr_t null_mapping;
int abs_idx = ilt->start_line + idx;
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
case INITOP_SET:
bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
break;
case INITOP_CLEAR:
null_mapping = 0;
bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
break;
}
}
static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
struct ilt_client_info *ilt_cli,
u32 ilt_start, u8 initop)
{
u32 start_reg = 0;
u32 end_reg = 0;
/* The boundary is either SET or INIT,
CLEAR => SET and for now SET ~~ INIT */
/* find the appropriate regs */
if (CHIP_IS_E1(bp)) {
switch (ilt_cli->client_num) {
case ILT_CLIENT_CDU:
start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
break;
case ILT_CLIENT_QM:
start_reg = PXP2_REG_PSWRQ_QM0_L2P;
break;
case ILT_CLIENT_SRC:
start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
break;
case ILT_CLIENT_TM:
start_reg = PXP2_REG_PSWRQ_TM0_L2P;
break;
}
REG_WR(bp, start_reg + BP_FUNC(bp)*4,
ILT_RANGE((ilt_start + ilt_cli->start),
(ilt_start + ilt_cli->end)));
} else {
switch (ilt_cli->client_num) {
case ILT_CLIENT_CDU:
start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
break;
case ILT_CLIENT_QM:
start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
end_reg = PXP2_REG_RQ_QM_LAST_ILT;
break;
case ILT_CLIENT_SRC:
start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
break;
case ILT_CLIENT_TM:
start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
end_reg = PXP2_REG_RQ_TM_LAST_ILT;
break;
}
REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
}
}
static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp,
struct bnx2x_ilt *ilt,
struct ilt_client_info *ilt_cli,
u8 initop)
{
int i;
if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
return;
for (i = ilt_cli->start; i <= ilt_cli->end; i++)
bnx2x_ilt_line_init_op(bp, ilt, i, initop);
/* init/clear the ILT boundries */
bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
}
static void bnx2x_ilt_client_init_op(struct bnx2x *bp,
struct ilt_client_info *ilt_cli, u8 initop)
{
struct bnx2x_ilt *ilt = BP_ILT(bp);
bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
}
static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
int cli_num, u8 initop)
{
struct bnx2x_ilt *ilt = BP_ILT(bp);
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
}
static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, u8 initop)
{
if (CONFIGURE_NIC_MODE(bp))
bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
}
static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop)
{
bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
if (CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
}
static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
u32 psz_reg, u8 initop)
{
struct bnx2x_ilt *ilt = BP_ILT(bp);
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
return;
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
case INITOP_SET:
REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
break;
case INITOP_CLEAR:
break;
}
}
/*
* called during init common stage, ilt clients should be initialized
* prioir to calling this function
*/
static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop)
{
bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
PXP2_REG_RQ_CDU_P_SIZE, initop);
bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
PXP2_REG_RQ_QM_P_SIZE, initop);
bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
PXP2_REG_RQ_SRC_P_SIZE, initop);
bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
PXP2_REG_RQ_TM_P_SIZE, initop);
}
/****************************************************************************
* QM initializations
****************************************************************************/
#define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
#define QM_INIT_MIN_CID_COUNT 31
#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
/* called during init port stage */
static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
u8 initop)
{
int port = BP_PORT(bp);
if (QM_INIT(qm_cid_count)) {
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
case INITOP_SET:
REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
qm_cid_count/16 - 1);
break;
case INITOP_CLEAR:
break;
}
}
}
static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count,
u32 base_reg, u32 reg)
{
int i;
u32 wb_data[2] = {0, 0};
for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
REG_WR(bp, base_reg + i*4,
qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
bnx2x_init_wr_wb(bp, reg + i*8, wb_data, 2);
}
}
/* called during init common stage */
static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
u8 initop)
{
if (!QM_INIT(qm_cid_count))
return;
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
case INITOP_SET:
bnx2x_qm_set_ptr_table(bp, qm_cid_count,
QM_REG_BASEADDR, QM_REG_PTRTBL);
if (CHIP_IS_E1H(bp))
bnx2x_qm_set_ptr_table(bp, qm_cid_count,
QM_REG_BASEADDR_EXT_A,
QM_REG_PTRTBL_EXT_A);
break;
case INITOP_CLEAR:
break;
}
}
/****************************************************************************
* SRC initializations
****************************************************************************/
/* called during init func stage */
static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
dma_addr_t t2_mapping, int src_cid_count)
{
int i;
int port = BP_PORT(bp);
/* Initialize T2 */
for (i = 0; i < src_cid_count-1; i++)
t2[i].next = (u64)(t2_mapping +
(i+1)*sizeof(struct src_ent));
/* tell the searcher where the T2 table is */
REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
U64_LO(t2_mapping), U64_HI(t2_mapping));
bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
U64_LO((u64)t2_mapping +
(src_cid_count-1) * sizeof(struct src_ent)),
U64_HI((u64)t2_mapping +
(src_cid_count-1) * sizeof(struct src_ent)));
}
#endif /* BNX2X_INIT_OPS_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+14065
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
+547
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@@ -0,0 +1,547 @@
/* Copyright 2008-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* Unless you and QLogic execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available
* at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Qlogic software provided under a
* license other than the GPL, without Qlogic's express prior written
* consent.
*
* Written by Yaniv Rosner
*
*/
#ifndef BNX2X_LINK_H
#define BNX2X_LINK_H
/***********************************************************/
/* Defines */
/***********************************************************/
#define DEFAULT_PHY_DEV_ADDR 3
#define E2_DEFAULT_PHY_DEV_ADDR 5
#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
#define NET_SERDES_IF_XFI 1
#define NET_SERDES_IF_SFI 2
#define NET_SERDES_IF_KR 3
#define NET_SERDES_IF_DXGXS 4
#define SPEED_AUTO_NEG 0
#define SPEED_20000 20000
#define I2C_DEV_ADDR_A0 0xa0
#define I2C_DEV_ADDR_A2 0xa2
#define SFP_EEPROM_PAGE_SIZE 16
#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
#define SFP_EEPROM_VENDOR_NAME_SIZE 16
#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
#define SFP_EEPROM_VENDOR_OUI_SIZE 3
#define SFP_EEPROM_PART_NO_ADDR 0x28
#define SFP_EEPROM_PART_NO_SIZE 16
#define SFP_EEPROM_REVISION_ADDR 0x38
#define SFP_EEPROM_REVISION_SIZE 4
#define SFP_EEPROM_SERIAL_ADDR 0x44
#define SFP_EEPROM_SERIAL_SIZE 16
#define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
#define SFP_EEPROM_DATE_SIZE 6
#define SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
#define SFP_EEPROM_DIAG_TYPE_SIZE 1
#define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
#define SFP_EEPROM_DDM_IMPLEMENTED (1<<6)
#define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
#define SFP_EEPROM_SFF_8472_COMP_SIZE 1
#define SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
#define SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
#define PWR_FLT_ERR_MSG_LEN 250
#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
/* Single Media board contains single external phy */
#define SINGLE_MEDIA(params) (params->num_phys == 2)
/* Dual Media board contains two external phy with different media */
#define DUAL_MEDIA(params) (params->num_phys == 3)
#define FW_PARAM_PHY_ADDR_MASK 0x000000FF
#define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
#define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
#define FW_PARAM_MDIO_CTRL_OFFSET 16
#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
FW_PARAM_PHY_ADDR_MASK)
#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
FW_PARAM_PHY_TYPE_MASK)
#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
FW_PARAM_MDIO_CTRL_MASK) >> \
FW_PARAM_MDIO_CTRL_OFFSET)
#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
#define BMAC_CONTROL_RX_ENABLE 2
/***********************************************************/
/* Structs */
/***********************************************************/
#define INT_PHY 0
#define EXT_PHY1 1
#define EXT_PHY2 2
#define MAX_PHYS 3
/* Same configuration is shared between the XGXS and the first external phy */
#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
0 : (_phy_idx - 1))
/***********************************************************/
/* bnx2x_phy struct */
/* Defines the required arguments and function per phy */
/***********************************************************/
struct link_vars;
struct link_params;
struct bnx2x_phy;
typedef void (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
struct link_vars *vars);
typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
struct link_vars *vars);
typedef void (*link_reset_t)(struct bnx2x_phy *phy,
struct link_params *params);
typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
struct link_params *params);
typedef int (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
struct link_params *params, u8 mode);
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
struct link_params *params, u32 action);
struct bnx2x_reg_set {
u8 devad;
u16 reg;
u16 val;
};
struct bnx2x_phy {
u32 type;
/* Loaded during init */
u8 addr;
u8 def_md_devad;
u16 flags;
/* No Over-Current detection */
#define FLAGS_NOC (1<<1)
/* Fan failure detection required */
#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
/* Initialize first the XGXS and only then the phy itself */
#define FLAGS_INIT_XGXS_FIRST (1<<3)
#define FLAGS_WC_DUAL_MODE (1<<4)
#define FLAGS_4_PORT_MODE (1<<5)
#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
#define FLAGS_SFP_NOT_APPROVED (1<<7)
#define FLAGS_MDC_MDIO_WA (1<<8)
#define FLAGS_DUMMY_READ (1<<9)
#define FLAGS_MDC_MDIO_WA_B0 (1<<10)
#define FLAGS_TX_ERROR_CHECK (1<<12)
#define FLAGS_EEE (1<<13)
#define FLAGS_MDC_MDIO_WA_G (1<<15)
/* preemphasis values for the rx side */
u16 rx_preemphasis[4];
/* preemphasis values for the tx side */
u16 tx_preemphasis[4];
/* EMAC address for access MDIO */
u32 mdio_ctrl;
u32 supported;
u32 media_type;
#define ETH_PHY_UNSPECIFIED 0x0
#define ETH_PHY_SFPP_10G_FIBER 0x1
#define ETH_PHY_XFP_FIBER 0x2
#define ETH_PHY_DA_TWINAX 0x3
#define ETH_PHY_BASE_T 0x4
#define ETH_PHY_SFP_1G_FIBER 0x5
#define ETH_PHY_KR 0xf0
#define ETH_PHY_CX4 0xf1
#define ETH_PHY_NOT_PRESENT 0xff
/* The address in which version is located*/
u32 ver_addr;
u16 req_flow_ctrl;
u16 req_line_speed;
u32 speed_cap_mask;
u16 req_duplex;
u16 rsrv;
/* Called per phy/port init, and it configures LASI, speed, autoneg,
duplex, flow control negotiation, etc. */
config_init_t config_init;
/* Called due to interrupt. It determines the link, speed */
read_status_t read_status;
/* Called when driver is unloading. Should reset the phy */
link_reset_t link_reset;
/* Set the loopback configuration for the phy */
config_loopback_t config_loopback;
/* Format the given raw number into str up to len */
format_fw_ver_t format_fw_ver;
/* Reset the phy (both ports) */
hw_reset_t hw_reset;
/* Set link led mode (on/off/oper)*/
set_link_led_t set_link_led;
/* PHY Specific tasks */
phy_specific_func_t phy_specific_func;
#define DISABLE_TX 1
#define ENABLE_TX 2
#define PHY_INIT 3
};
/* Inputs parameters to the CLC */
struct link_params {
u8 port;
/* Default / User Configuration */
u8 loopback_mode;
#define LOOPBACK_NONE 0
#define LOOPBACK_EMAC 1
#define LOOPBACK_BMAC 2
#define LOOPBACK_XGXS 3
#define LOOPBACK_EXT_PHY 4
#define LOOPBACK_EXT 5
#define LOOPBACK_UMAC 6
#define LOOPBACK_XMAC 7
/* Device parameters */
u8 mac_addr[6];
u16 req_duplex[LINK_CONFIG_SIZE];
u16 req_flow_ctrl[LINK_CONFIG_SIZE];
u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
/* shmem parameters */
u32 shmem_base;
u32 shmem2_base;
u32 speed_cap_mask[LINK_CONFIG_SIZE];
u32 switch_cfg;
#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
u32 lane_config;
/* Phy register parameter */
u32 chip_id;
/* features */
u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
#define FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
#define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
#define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
#define FEATURE_CONFIG_MT_SUPPORT (1<<13)
#define FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
/* Will be populated during common init */
struct bnx2x_phy phy[MAX_PHYS];
/* Will be populated during common init */
u8 num_phys;
u8 rsrv;
/* Used to configure the EEE Tx LPI timer, has several modes of
* operation, according to bits 29:28 -
* 2'b00: Timer will be configured by nvram, output will be the value
* from nvram.
* 2'b01: Timer will be configured by nvram, output will be in
* microseconds.
* 2'b10: bits 1:0 contain an nvram value which will be used instead
* of the one located in the nvram. Output will be that value.
* 2'b11: bits 19:0 contain the idle timer in microseconds; output
* will be in microseconds.
* Bits 31:30 should be 2'b11 in order for EEE to be enabled.
*/
u32 eee_mode;
#define EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
#define EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
#define EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
#define EEE_MODE_NVRAM_MASK (0x3)
#define EEE_MODE_TIMER_MASK (0xfffff)
#define EEE_MODE_OUTPUT_TIME (1<<28)
#define EEE_MODE_OVERRIDE_NVRAM (1<<29)
#define EEE_MODE_ENABLE_LPI (1<<30)
#define EEE_MODE_ADV_LPI (1<<31)
u16 hw_led_mode; /* part of the hw_config read from the shmem */
u32 multi_phy_config;
/* Device pointer passed to all callback functions */
struct bnx2x *bp;
u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
req_flow_ctrl is set to AUTO */
u16 link_flags;
#define LINK_FLAGS_INT_DISABLED (1<<0)
#define PHY_INITIALIZED (1<<1)
u32 lfa_base;
/* The same definitions as the shmem2 parameter */
u32 link_attr_sync;
};
/* Output parameters */
struct link_vars {
u8 phy_flags;
#define PHY_XGXS_FLAG (1<<0)
#define PHY_SGMII_FLAG (1<<1)
#define PHY_PHYSICAL_LINK_FLAG (1<<2)
#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
#define PHY_OVER_CURRENT_FLAG (1<<4)
#define PHY_SFP_TX_FAULT_FLAG (1<<5)
u8 mac_type;
#define MAC_TYPE_NONE 0
#define MAC_TYPE_EMAC 1
#define MAC_TYPE_BMAC 2
#define MAC_TYPE_UMAC 3
#define MAC_TYPE_XMAC 4
u8 phy_link_up; /* internal phy link indication */
u8 link_up;
u16 line_speed;
u16 duplex;
u16 flow_ctrl;
u16 ieee_fc;
/* The same definitions as the shmem parameter */
u32 link_status;
u32 eee_status;
u8 fault_detected;
u8 check_kr2_recovery_cnt;
#define CHECK_KR2_RECOVERY_CNT 5
u16 periodic_flags;
#define PERIODIC_FLAGS_LINK_EVENT 0x0001
u32 aeu_int_mask;
u8 rx_tx_asic_rst;
u8 turn_to_run_wc_rt;
u16 rsrv2;
};
/***********************************************************/
/* Functions */
/***********************************************************/
int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
/* Reset the link. Should be called when driver or interface goes down
Before calling phy firmware upgrade, the reset_ext_phy should be set
to 0 */
int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
u8 reset_ext_phy);
int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
/* bnx2x_link_update should be called upon link interrupt */
int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
/* use the following phy functions to read/write from external_phy
In order to use it to read/write internal phy registers, use
DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
the register */
int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
u8 devad, u16 reg, u16 *ret_val);
int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
u8 devad, u16 reg, u16 val);
/* Reads the link_status from the shmem,
and update the link vars accordingly */
void bnx2x_link_status_update(struct link_params *input,
struct link_vars *output);
/* returns string representing the fw_version of the external phy */
int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
u16 len);
/* Set/Unset the led
Basically, the CLC takes care of the led for the link, but in case one needs
to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
blink the led, and LED_MODE_OFF to set the led off.*/
int bnx2x_set_led(struct link_params *params,
struct link_vars *vars, u8 mode, u32 speed);
#define LED_MODE_OFF 0
#define LED_MODE_ON 1
#define LED_MODE_OPER 2
#define LED_MODE_FRONT_PANEL_OFF 3
/* bnx2x_handle_module_detect_int should be called upon module detection
interrupt */
void bnx2x_handle_module_detect_int(struct link_params *params);
/* Get the actual link status. In case it returns 0, link is up,
otherwise link is down*/
int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
u8 is_serdes);
/* One-time initialization for external phy after power up */
int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
u32 shmem2_base_path[], u32 chip_id);
/* Reset the external PHY using GPIO */
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
/* Reset the external of SFX7101 */
void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
struct link_params *params, u8 dev_addr,
u16 addr, u16 byte_cnt, u8 *o_buf);
void bnx2x_hw_reset_phy(struct link_params *params);
/* Check swap bit and adjust PHY order */
u32 bnx2x_phy_selection(struct link_params *params);
/* Probe the phys on board, and populate them in "params" */
int bnx2x_phy_probe(struct link_params *params);
/* Checks if fan failure detection is required on one of the phys on board */
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
u32 shmem2_base, u8 port);
/* Open / close the gate between the NIG and the BRB */
void bnx2x_set_rx_filter(struct link_params *params, u8 en);
/* DCBX structs */
/* Number of maximum COS per chip */
#define DCBX_E2E3_MAX_NUM_COS (2)
#define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
#define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
#define DCBX_E3B0_MAX_NUM_COS ( \
MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
DCBX_E3B0_MAX_NUM_COS_PORT1))
#define DCBX_MAX_NUM_COS ( \
MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
DCBX_E2E3_MAX_NUM_COS))
/* PFC port configuration params */
struct bnx2x_nig_brb_pfc_port_params {
/* NIG */
u32 pause_enable;
u32 llfc_out_en;
u32 llfc_enable;
u32 pkt_priority_to_cos;
u8 num_of_rx_cos_priority_mask;
u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
u32 llfc_high_priority_classes;
u32 llfc_low_priority_classes;
};
/* ETS port configuration params */
struct bnx2x_ets_bw_params {
u8 bw;
};
struct bnx2x_ets_sp_params {
/**
* valid values are 0 - 5. 0 is highest strict priority.
* There can't be two COS's with the same pri.
*/
u8 pri;
};
enum bnx2x_cos_state {
bnx2x_cos_state_strict = 0,
bnx2x_cos_state_bw = 1,
};
struct bnx2x_ets_cos_params {
enum bnx2x_cos_state state ;
union {
struct bnx2x_ets_bw_params bw_params;
struct bnx2x_ets_sp_params sp_params;
} params;
};
struct bnx2x_ets_params {
u8 num_of_cos; /* Number of valid COS entries*/
struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
};
/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
* when link is already up
*/
int bnx2x_update_pfc(struct link_params *params,
struct link_vars *vars,
struct bnx2x_nig_brb_pfc_port_params *pfc_params);
/* Used to configure the ETS to disable */
int bnx2x_ets_disabled(struct link_params *params,
struct link_vars *vars);
/* Used to configure the ETS to BW limited */
void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
const u32 cos1_bw);
/* Used to configure the ETS to strict */
int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
/* Configure the COS to ETS according to BW and SP settings.*/
int bnx2x_ets_e3b0_config(const struct link_params *params,
const struct link_vars *vars,
struct bnx2x_ets_params *ets_params);
void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
u32 chip_id, u32 shmem_base, u32 shmem2_base,
u8 port);
void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
#endif /* BNX2X_LINK_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_mfw_req.h
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/* bnx2x_mfw_req.h: Qlogic Everest network driver.
*
* Copyright (c) 2012-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*/
#ifndef BNX2X_MFW_REQ_H
#define BNX2X_MFW_REQ_H
#define PORT_0 0
#define PORT_1 1
#define PORT_MAX 2
#define NVM_PATH_MAX 2
/* FCoE capabilities required from the driver */
struct fcoe_capabilities {
u32 capability1;
/* Maximum number of I/Os per connection */
#define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
#define FCOE_IOS_PER_CONNECTION_SHIFT 0
/* Maximum number of Logins per port */
#define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
#define FCOE_LOGINS_PER_PORT_SHIFT 16
u32 capability2;
/* Maximum number of exchanges */
#define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
#define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
/* Maximum NPIV WWN per port */
#define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
#define FCOE_NPIV_WWN_PER_PORT_SHIFT 16
u32 capability3;
/* Maximum number of targets supported */
#define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff
#define FCOE_TARGETS_SUPPORTED_SHIFT 0
/* Maximum number of outstanding commands across all connections */
#define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000
#define FCOE_OUTSTANDING_COMMANDS_SHIFT 16
u32 capability4;
#define FCOE_CAPABILITY4_STATEFUL 0x00000001
#define FCOE_CAPABILITY4_STATELESS 0x00000002
#define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID 0x00000004
};
struct glob_ncsi_oem_data {
u32 driver_version;
u32 unused[3];
struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
};
/* current drv_info version */
#define DRV_INFO_CUR_VER 2
/* drv_info op codes supported */
enum drv_info_opcode {
ETH_STATS_OPCODE,
FCOE_STATS_OPCODE,
ISCSI_STATS_OPCODE
};
#define ETH_STAT_INFO_VERSION_LEN 12
/* Per PCI Function Ethernet Statistics required from the driver */
struct eth_stats_info {
/* Function's Driver Version. padded to 12 */
u8 version[ETH_STAT_INFO_VERSION_LEN];
/* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
u8 mac_local[8];
u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */
u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */
u32 mtu_size; /* MTU Size. Note : Negotiated MTU */
u32 feature_flags; /* Feature_Flags. */
#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
#define FEATURE_ETH_LSO_MASK 0x02
#define FEATURE_ETH_BOOTMODE_MASK 0x1C
#define FEATURE_ETH_BOOTMODE_SHIFT 2
#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
#define FEATURE_ETH_TOE_MASK 0x20
u32 lso_max_size; /* LSO MaxOffloadSize. */
u32 lso_min_seg_cnt; /* LSO MinSegmentCount. */
/* Num Offloaded Connections TCP_IPv4. */
u32 ipv4_ofld_cnt;
/* Num Offloaded Connections TCP_IPv6. */
u32 ipv6_ofld_cnt;
u32 promiscuous_mode; /* Promiscuous Mode. non-zero true */
u32 txq_size; /* TX Descriptors Queue Size */
u32 rxq_size; /* RX Descriptors Queue Size */
/* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
u32 txq_avg_depth;
/* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
u32 rxq_avg_depth;
/* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
u32 iov_offload;
/* Number of NetQueue/VMQ Config'd. */
u32 netq_cnt;
u32 vf_cnt; /* Num VF assigned to this PF. */
};
/* Per PCI Function FCOE Statistics required from the driver */
struct fcoe_stats_info {
u8 version[12]; /* Function's Driver Version. */
u8 mac_local[8]; /* Locally Admin Addr. */
u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */
u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */
/* QoS Priority (per 802.1p). 0-7255 */
u32 qos_priority;
u32 txq_size; /* FCoE TX Descriptors Queue Size. */
u32 rxq_size; /* FCoE RX Descriptors Queue Size. */
/* FCoE TX Descriptor Queue Avg Depth. */
u32 txq_avg_depth;
/* FCoE RX Descriptors Queue Avg Depth. */
u32 rxq_avg_depth;
u32 rx_frames_lo; /* FCoE RX Frames received. */
u32 rx_frames_hi; /* FCoE RX Frames received. */
u32 rx_bytes_lo; /* FCoE RX Bytes received. */
u32 rx_bytes_hi; /* FCoE RX Bytes received. */
u32 tx_frames_lo; /* FCoE TX Frames sent. */
u32 tx_frames_hi; /* FCoE TX Frames sent. */
u32 tx_bytes_lo; /* FCoE TX Bytes sent. */
u32 tx_bytes_hi; /* FCoE TX Bytes sent. */
};
/* Per PCI Function iSCSI Statistics required from the driver*/
struct iscsi_stats_info {
u8 version[12]; /* Function's Driver Version. */
u8 mac_local[8]; /* Locally Admin iSCSI MAC Addr. */
u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */
/* QoS Priority (per 802.1p). 0-7255 */
u32 qos_priority;
u8 initiator_name[64]; /* iSCSI Boot Initiator Node name. */
u8 ww_port_name[64]; /* iSCSI World wide port name */
u8 boot_target_name[64];/* iSCSI Boot Target Name. */
u8 boot_target_ip[16]; /* iSCSI Boot Target IP. */
u32 boot_target_portal; /* iSCSI Boot Target Portal. */
u8 boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */
u32 max_frame_size; /* Max Frame Size. bytes */
u32 txq_size; /* PDU TX Descriptors Queue Size. */
u32 rxq_size; /* PDU RX Descriptors Queue Size. */
u32 txq_avg_depth; /* PDU TX Descriptor Queue Avg Depth. */
u32 rxq_avg_depth; /* PDU RX Descriptors Queue Avg Depth. */
u32 rx_pdus_lo; /* iSCSI PDUs received. */
u32 rx_pdus_hi; /* iSCSI PDUs received. */
u32 rx_bytes_lo; /* iSCSI RX Bytes received. */
u32 rx_bytes_hi; /* iSCSI RX Bytes received. */
u32 tx_pdus_lo; /* iSCSI PDUs sent. */
u32 tx_pdus_hi; /* iSCSI PDUs sent. */
u32 tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */
u32 tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */
u32 pcp_prior_map_tbl; /* C-PCP to S-PCP Priority MapTable.
* 9 nibbles, the position of each nibble
* represents the C-PCP value, the value
* of the nibble = S-PCP value.
*/
};
union drv_info_to_mcp {
struct eth_stats_info ether_stat;
struct fcoe_stats_info fcoe_stat;
struct iscsi_stats_info iscsi_stat;
};
#endif /* BNX2X_MFW_REQ_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_self_test.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
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linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
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/* bnx2x_sriov.h: QLogic Everest network driver.
*
* Copyright 2009-2013 Broadcom Corporation
* Copyright 2014 QLogic Corporation
* All rights reserved
*
* Unless you and QLogic execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other QLogic software provided under a
* license other than the GPL, without QLogic's express prior written
* consent.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Shmulik Ravid
* Ariel Elior <ariel.elior@qlogic.com>
*/
#ifndef BNX2X_SRIOV_H
#define BNX2X_SRIOV_H
#include "bnx2x_vfpf.h"
#include "bnx2x.h"
enum sample_bulletin_result {
PFVF_BULLETIN_UNCHANGED,
PFVF_BULLETIN_UPDATED,
PFVF_BULLETIN_CRC_ERR
};
#ifdef CONFIG_BNX2X_SRIOV
extern struct workqueue_struct *bnx2x_iov_wq;
/* The bnx2x device structure holds vfdb structure described below.
* The VF array is indexed by the relative vfid.
*/
#define BNX2X_VF_MAX_QUEUES 16
#define BNX2X_VF_MAX_TPA_AGG_QUEUES 8
struct bnx2x_sriov {
u32 first_vf_in_pf;
/* standard SRIOV capability fields, mostly for debugging */
int pos; /* capability position */
int nres; /* number of resources */
u32 cap; /* SR-IOV Capabilities */
u16 ctrl; /* SR-IOV Control */
u16 total; /* total VFs associated with the PF */
u16 initial; /* initial VFs associated with the PF */
u16 nr_virtfn; /* number of VFs available */
u16 offset; /* first VF Routing ID offset */
u16 stride; /* following VF stride */
u32 pgsz; /* page size for BAR alignment */
u8 link; /* Function Dependency Link */
};
/* bars */
struct bnx2x_vf_bar {
u64 bar;
u32 size;
};
struct bnx2x_vf_bar_info {
struct bnx2x_vf_bar bars[PCI_SRIOV_NUM_BARS];
u8 nr_bars;
};
/* vf queue (used both for rx or tx) */
struct bnx2x_vf_queue {
struct eth_context *cxt;
/* MACs object */
struct bnx2x_vlan_mac_obj mac_obj;
/* VLANs object */
struct bnx2x_vlan_mac_obj vlan_obj;
/* VLAN-MACs object */
struct bnx2x_vlan_mac_obj vlan_mac_obj;
unsigned long accept_flags; /* last accept flags configured */
/* Queue Slow-path State object */
struct bnx2x_queue_sp_obj sp_obj;
u32 cid;
u16 index;
u16 sb_idx;
bool is_leading;
bool sp_initialized;
};
/* struct bnx2x_vf_queue_construct_params - prepare queue construction
* parameters: q-init, q-setup and SB index
*/
struct bnx2x_vf_queue_construct_params {
struct bnx2x_queue_state_params qstate;
struct bnx2x_queue_setup_params prep_qsetup;
};
/* forward */
struct bnx2x_virtf;
/* VFOP definitions */
struct bnx2x_vf_mac_vlan_filter {
int type;
#define BNX2X_VF_FILTER_MAC BIT(0)
#define BNX2X_VF_FILTER_VLAN BIT(1)
#define BNX2X_VF_FILTER_VLAN_MAC \
(BNX2X_VF_FILTER_MAC | BNX2X_VF_FILTER_VLAN) /*shortcut*/
bool add;
bool applied;
u8 *mac;
u16 vid;
};
struct bnx2x_vf_mac_vlan_filters {
int count;
struct bnx2x_vf_mac_vlan_filter filters[];
};
/* vf context */
struct bnx2x_virtf {
u16 cfg_flags;
#define VF_CFG_STATS_COALESCE 0x1
#define VF_CFG_EXT_BULLETIN 0x2
#define VF_CFG_VLAN_FILTER 0x4
u8 link_cfg; /* IFLA_VF_LINK_STATE_AUTO
* IFLA_VF_LINK_STATE_ENABLE
* IFLA_VF_LINK_STATE_DISABLE
*/
u8 state;
#define VF_FREE 0 /* VF ready to be acquired holds no resc */
#define VF_ACQUIRED 1 /* VF acquired, but not initialized */
#define VF_ENABLED 2 /* VF Enabled */
#define VF_RESET 3 /* VF FLR'd, pending cleanup */
#define VF_LOST 4 /* Recovery while VFs are loaded */
bool flr_clnup_stage; /* true during flr cleanup */
bool malicious; /* true if FW indicated so, until FLR */
/* 1(true) if spoof check is enabled */
u8 spoofchk;
/* dma */
dma_addr_t fw_stat_map;
u16 stats_stride;
dma_addr_t bulletin_map;
/* Allocated resources counters. Before the VF is acquired, the
* counters hold the following values:
*
* - xxq_count = 0 as the queues memory is not allocated yet.
*
* - sb_count = The number of status blocks configured for this VF in
* the IGU CAM. Initially read during probe.
*
* - xx_rules_count = The number of rules statically and equally
* allocated for each VF, during PF load.
*/
struct vf_pf_resc_request alloc_resc;
#define vf_rxq_count(vf) ((vf)->alloc_resc.num_rxqs)
#define vf_txq_count(vf) ((vf)->alloc_resc.num_txqs)
#define vf_sb_count(vf) ((vf)->alloc_resc.num_sbs)
#define vf_mac_rules_cnt(vf) ((vf)->alloc_resc.num_mac_filters)
#define vf_vlan_rules_cnt(vf) ((vf)->alloc_resc.num_vlan_filters)
#define vf_mc_rules_cnt(vf) ((vf)->alloc_resc.num_mc_filters)
u8 sb_count; /* actual number of SBs */
u8 igu_base_id; /* base igu status block id */
struct bnx2x_vf_queue *vfqs;
#define LEADING_IDX 0
#define bnx2x_vfq_is_leading(vfq) ((vfq)->index == LEADING_IDX)
#define bnx2x_vfq(vf, nr, var) ((vf)->vfqs[(nr)].var)
#define bnx2x_leading_vfq(vf, var) ((vf)->vfqs[LEADING_IDX].var)
u8 index; /* index in the vf array */
u8 abs_vfid;
u8 sp_cl_id;
u32 error; /* 0 means all's-well */
/* BDF */
unsigned int domain;
unsigned int bus;
unsigned int devfn;
/* bars */
struct bnx2x_vf_bar bars[PCI_SRIOV_NUM_BARS];
/* set-mac ramrod state 1-pending, 0-done */
unsigned long filter_state;
/* leading rss client id ~~ the client id of the first rxq, must be
* set for each txq.
*/
int leading_rss;
/* MCAST object */
struct bnx2x_mcast_obj mcast_obj;
/* RSS configuration object */
struct bnx2x_rss_config_obj rss_conf_obj;
/* slow-path operations */
struct mutex op_mutex; /* one vfop at a time mutex */
enum channel_tlvs op_current;
u8 fp_hsi;
struct bnx2x_credit_pool_obj vf_vlans_pool;
struct bnx2x_credit_pool_obj vf_macs_pool;
};
#define BNX2X_NR_VIRTFN(bp) ((bp)->vfdb->sriov.nr_virtfn)
#define for_each_vf(bp, var) \
for ((var) = 0; (var) < BNX2X_NR_VIRTFN(bp); (var)++)
#define for_each_vfq(vf, var) \
for ((var) = 0; (var) < vf_rxq_count(vf); (var)++)
#define for_each_vf_sb(vf, var) \
for ((var) = 0; (var) < vf_sb_count(vf); (var)++)
#define is_vf_multi(vf) (vf_rxq_count(vf) > 1)
#define HW_VF_HANDLE(bp, abs_vfid) \
(u16)(BP_ABS_FUNC((bp)) | (1<<3) | ((u16)(abs_vfid) << 4))
#define FW_PF_MAX_HANDLE 8
#define FW_VF_HANDLE(abs_vfid) \
(abs_vfid + FW_PF_MAX_HANDLE)
#define GET_NUM_VFS_PER_PATH(bp) 64 /* use max possible value */
#define GET_NUM_VFS_PER_PF(bp) ((bp)->vfdb ? (bp)->vfdb->sriov.total \
: 0)
#define VF_MAC_CREDIT_CNT 1
#define VF_VLAN_CREDIT_CNT 2 /* VLAN0 + 'real' VLAN */
/* locking and unlocking the channel mutex */
void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
enum channel_tlvs tlv);
void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
enum channel_tlvs expected_tlv);
/* VF mail box (aka vf-pf channel) */
/* a container for the bi-directional vf<-->pf messages.
* The actual response will be placed according to the offset parameter
* provided in the request
*/
#define MBX_MSG_ALIGN 8
#define MBX_MSG_ALIGNED_SIZE (roundup(sizeof(struct bnx2x_vf_mbx_msg), \
MBX_MSG_ALIGN))
struct bnx2x_vf_mbx_msg {
union vfpf_tlvs req;
union pfvf_tlvs resp;
};
struct bnx2x_vf_mbx {
struct bnx2x_vf_mbx_msg *msg;
dma_addr_t msg_mapping;
/* VF GPA address */
u32 vf_addr_lo;
u32 vf_addr_hi;
struct vfpf_first_tlv first_tlv; /* saved VF request header */
};
struct bnx2x_vf_sp {
union {
struct eth_classify_rules_ramrod_data e2;
} mac_rdata;
union {
struct eth_classify_rules_ramrod_data e2;
} vlan_rdata;
union {
struct eth_classify_rules_ramrod_data e2;
} vlan_mac_rdata;
union {
struct eth_filter_rules_ramrod_data e2;
} rx_mode_rdata;
union {
struct eth_multicast_rules_ramrod_data e2;
} mcast_rdata;
union {
struct client_init_ramrod_data init_data;
struct client_update_ramrod_data update_data;
} q_data;
union {
struct eth_rss_update_ramrod_data e2;
} rss_rdata;
};
struct hw_dma {
void *addr;
dma_addr_t mapping;
size_t size;
};
struct bnx2x_vfdb {
#define BP_VFDB(bp) ((bp)->vfdb)
/* vf array */
struct bnx2x_virtf *vfs;
#define BP_VF(bp, idx) ((BP_VFDB(bp) && (bp)->vfdb->vfs) ? \
&((bp)->vfdb->vfs[idx]) : NULL)
#define bnx2x_vf(bp, idx, var) ((bp)->vfdb->vfs[idx].var)
/* queue array - for all vfs */
struct bnx2x_vf_queue *vfqs;
/* vf HW contexts */
struct hw_dma context[BNX2X_VF_CIDS/ILT_PAGE_CIDS];
#define BP_VF_CXT_PAGE(bp, i) (&(bp)->vfdb->context[i])
/* SR-IOV information */
struct bnx2x_sriov sriov;
struct hw_dma mbx_dma;
#define BP_VF_MBX_DMA(bp) (&((bp)->vfdb->mbx_dma))
struct bnx2x_vf_mbx mbxs[BNX2X_MAX_NUM_OF_VFS];
#define BP_VF_MBX(bp, vfid) (&((bp)->vfdb->mbxs[vfid]))
struct hw_dma bulletin_dma;
#define BP_VF_BULLETIN_DMA(bp) (&((bp)->vfdb->bulletin_dma))
#define BP_VF_BULLETIN(bp, vf) \
(((struct pf_vf_bulletin_content *)(BP_VF_BULLETIN_DMA(bp)->addr)) \
+ (vf))
struct hw_dma sp_dma;
#define bnx2x_vf_sp(bp, vf, field) ((bp)->vfdb->sp_dma.addr + \
(vf)->index * sizeof(struct bnx2x_vf_sp) + \
offsetof(struct bnx2x_vf_sp, field))
#define bnx2x_vf_sp_map(bp, vf, field) ((bp)->vfdb->sp_dma.mapping + \
(vf)->index * sizeof(struct bnx2x_vf_sp) + \
offsetof(struct bnx2x_vf_sp, field))
#define FLRD_VFS_DWORDS (BNX2X_MAX_NUM_OF_VFS / 32)
u32 flrd_vfs[FLRD_VFS_DWORDS];
/* the number of msix vectors belonging to this PF designated for VFs */
u16 vf_sbs_pool;
u16 first_vf_igu_entry;
/* sp_rtnl synchronization */
struct mutex event_mutex;
u64 event_occur;
/* bulletin board update synchronization */
struct mutex bulletin_mutex;
};
/* queue access */
static inline struct bnx2x_vf_queue *vfq_get(struct bnx2x_virtf *vf, u8 index)
{
return &(vf->vfqs[index]);
}
/* FW ids */
static inline u8 vf_igu_sb(struct bnx2x_virtf *vf, u16 sb_idx)
{
return vf->igu_base_id + sb_idx;
}
static inline u8 vf_hc_qzone(struct bnx2x_virtf *vf, u16 sb_idx)
{
return vf_igu_sb(vf, sb_idx);
}
static u8 vfq_cl_id(struct bnx2x_virtf *vf, struct bnx2x_vf_queue *q)
{
return vf->igu_base_id + q->index;
}
static inline u8 vfq_stat_id(struct bnx2x_virtf *vf, struct bnx2x_vf_queue *q)
{
if (vf->cfg_flags & VF_CFG_STATS_COALESCE)
return vf->leading_rss;
else
return vfq_cl_id(vf, q);
}
static inline u8 vfq_qzone_id(struct bnx2x_virtf *vf, struct bnx2x_vf_queue *q)
{
return vfq_cl_id(vf, q);
}
/* global iov routines */
int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line);
int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, int num_vfs_param);
void bnx2x_iov_remove_one(struct bnx2x *bp);
void bnx2x_iov_free_mem(struct bnx2x *bp);
int bnx2x_iov_alloc_mem(struct bnx2x *bp);
int bnx2x_iov_nic_init(struct bnx2x *bp);
int bnx2x_iov_chip_cleanup(struct bnx2x *bp);
void bnx2x_iov_init_dq(struct bnx2x *bp);
void bnx2x_iov_init_dmae(struct bnx2x *bp);
void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
struct bnx2x_queue_sp_obj **q_obj);
int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem);
void bnx2x_iov_adjust_stats_req(struct bnx2x *bp);
void bnx2x_iov_storm_stats_update(struct bnx2x *bp);
/* global vf mailbox routines */
void bnx2x_vf_mbx(struct bnx2x *bp);
void bnx2x_vf_mbx_schedule(struct bnx2x *bp,
struct vf_pf_event_data *vfpf_event);
void bnx2x_vf_enable_mbx(struct bnx2x *bp, u8 abs_vfid);
/* CORE VF API */
typedef u8 bnx2x_mac_addr_t[ETH_ALEN];
/* acquire */
int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf,
struct vf_pf_resc_request *resc);
/* init */
int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf,
dma_addr_t *sb_map);
/* VFOP queue construction helpers */
void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
struct bnx2x_queue_init_params *init_params,
struct bnx2x_queue_setup_params *setup_params,
u16 q_idx, u16 sb_idx);
void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf,
struct bnx2x_queue_init_params *init_params,
struct bnx2x_queue_setup_params *setup_params,
u16 q_idx, u16 sb_idx);
void bnx2x_vfop_qctor_prep(struct bnx2x *bp,
struct bnx2x_virtf *vf,
struct bnx2x_vf_queue *q,
struct bnx2x_vf_queue_construct_params *p,
unsigned long q_type);
int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf,
struct bnx2x_vf_mac_vlan_filters *filters,
int qid, bool drv_only);
int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid,
struct bnx2x_vf_queue_construct_params *qctor);
int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid);
int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf,
bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only);
int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf,
int qid, unsigned long accept_flags);
int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf);
int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf);
int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
struct bnx2x_config_rss_params *rss);
int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
struct vfpf_tpa_tlv *tlv,
struct bnx2x_queue_update_tpa_params *params);
/* VF release ~ VF close + VF release-resources
*
* Release is the ultimate SW shutdown and is called whenever an
* irrecoverable error is encountered.
*/
int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf);
int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid);
u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf);
/* FLR routines */
/* VF FLR helpers */
int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid);
void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid);
/* Handles an FLR (or VF_DISABLE) notification form the MCP */
void bnx2x_vf_handle_flr_event(struct bnx2x *bp);
bool bnx2x_tlv_supported(u16 tlvtype);
u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin);
int bnx2x_post_vf_bulletin(struct bnx2x *bp, int vf);
void bnx2x_vf_bulletin_finalize(struct pf_vf_bulletin_content *bulletin,
bool support_long);
enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp);
/* VF side vfpf channel functions */
int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count);
int bnx2x_vfpf_release(struct bnx2x *bp);
int bnx2x_vfpf_init(struct bnx2x *bp);
void bnx2x_vfpf_close_vf(struct bnx2x *bp);
int bnx2x_vfpf_setup_q(struct bnx2x *bp, struct bnx2x_fastpath *fp,
bool is_leading);
int bnx2x_vfpf_config_mac(struct bnx2x *bp, const u8 *addr, u8 vf_qid,
bool set);
int bnx2x_vfpf_config_rss(struct bnx2x *bp,
struct bnx2x_config_rss_params *params);
int bnx2x_vfpf_set_mcast(struct net_device *dev);
int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp);
static inline void bnx2x_vf_fill_fw_str(struct bnx2x *bp, char *buf,
size_t buf_len)
{
strscpy(buf, bp->acquire_resp.pfdev_info.fw_ver, buf_len);
}
static inline int bnx2x_vf_ustorm_prods_offset(struct bnx2x *bp,
struct bnx2x_fastpath *fp)
{
return PXP_VF_ADDR_USDM_QUEUES_START +
bp->acquire_resp.resc.hw_qid[fp->index] *
sizeof(struct ustorm_queue_zone_data);
}
enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp);
void bnx2x_timer_sriov(struct bnx2x *bp);
void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp);
void bnx2x_vf_pci_dealloc(struct bnx2x *bp);
int bnx2x_vf_pci_alloc(struct bnx2x *bp);
int bnx2x_enable_sriov(struct bnx2x *bp);
void bnx2x_disable_sriov(struct bnx2x *bp);
static inline int bnx2x_vf_headroom(struct bnx2x *bp)
{
return bp->vfdb->sriov.nr_virtfn * BNX2X_CIDS_PER_VF;
}
void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp);
int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs);
void bnx2x_iov_channel_down(struct bnx2x *bp);
void bnx2x_iov_task(struct work_struct *work);
void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag);
void bnx2x_iov_link_update(struct bnx2x *bp);
int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx);
int bnx2x_set_vf_link_state(struct net_device *dev, int vf, int link_state);
int bnx2x_vfpf_update_vlan(struct bnx2x *bp, u16 vid, u8 vf_qid, bool add);
#else /* CONFIG_BNX2X_SRIOV */
#define GET_NUM_VFS_PER_PATH(bp) 0
#define GET_NUM_VFS_PER_PF(bp) 0
#define VF_MAC_CREDIT_CNT 0
#define VF_VLAN_CREDIT_CNT 0
static inline void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
struct bnx2x_queue_sp_obj **q_obj) {}
static inline void bnx2x_vf_handle_flr_event(struct bnx2x *bp) {}
static inline int bnx2x_iov_eq_sp_event(struct bnx2x *bp,
union event_ring_elem *elem) {return 1; }
static inline void bnx2x_vf_mbx(struct bnx2x *bp) {}
static inline void bnx2x_vf_mbx_schedule(struct bnx2x *bp,
struct vf_pf_event_data *vfpf_event) {}
static inline int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) {return line; }
static inline void bnx2x_iov_init_dq(struct bnx2x *bp) {}
static inline int bnx2x_iov_alloc_mem(struct bnx2x *bp) {return 0; }
static inline void bnx2x_iov_free_mem(struct bnx2x *bp) {}
static inline int bnx2x_iov_chip_cleanup(struct bnx2x *bp) {return 0; }
static inline void bnx2x_iov_init_dmae(struct bnx2x *bp) {}
static inline int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
int num_vfs_param) {return 0; }
static inline void bnx2x_iov_remove_one(struct bnx2x *bp) {}
static inline int bnx2x_enable_sriov(struct bnx2x *bp) {return 0; }
static inline void bnx2x_disable_sriov(struct bnx2x *bp) {}
static inline int bnx2x_vfpf_acquire(struct bnx2x *bp,
u8 tx_count, u8 rx_count) {return 0; }
static inline int bnx2x_vfpf_release(struct bnx2x *bp) {return 0; }
static inline int bnx2x_vfpf_init(struct bnx2x *bp) {return 0; }
static inline void bnx2x_vfpf_close_vf(struct bnx2x *bp) {}
static inline int bnx2x_vfpf_setup_q(struct bnx2x *bp, struct bnx2x_fastpath *fp, bool is_leading) {return 0; }
static inline int bnx2x_vfpf_config_mac(struct bnx2x *bp, const u8 *addr,
u8 vf_qid, bool set) {return 0; }
static inline int bnx2x_vfpf_config_rss(struct bnx2x *bp,
struct bnx2x_config_rss_params *params) {return 0; }
static inline int bnx2x_vfpf_set_mcast(struct net_device *dev) {return 0; }
static inline int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp) {return 0; }
static inline int bnx2x_iov_nic_init(struct bnx2x *bp) {return 0; }
static inline int bnx2x_vf_headroom(struct bnx2x *bp) {return 0; }
static inline void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) {}
static inline void bnx2x_vf_fill_fw_str(struct bnx2x *bp, char *buf,
size_t buf_len) {}
static inline int bnx2x_vf_ustorm_prods_offset(struct bnx2x *bp,
struct bnx2x_fastpath *fp) {return 0; }
static inline enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
{
return PFVF_BULLETIN_UNCHANGED;
}
static inline void bnx2x_timer_sriov(struct bnx2x *bp) {}
static inline void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp)
{
return NULL;
}
static inline void bnx2x_vf_pci_dealloc(struct bnx2x *bp) {}
static inline int bnx2x_vf_pci_alloc(struct bnx2x *bp) {return 0; }
static inline void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) {}
static inline int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs) {return 0; }
static inline void bnx2x_iov_channel_down(struct bnx2x *bp) {}
static inline void bnx2x_iov_task(struct work_struct *work) {}
static inline void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) {}
static inline void bnx2x_iov_link_update(struct bnx2x *bp) {}
static inline int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) {return 0; }
static inline int bnx2x_set_vf_link_state(struct net_device *dev, int vf,
int link_state) {return 0; }
struct pf_vf_bulletin_content;
static inline void bnx2x_vf_bulletin_finalize(struct pf_vf_bulletin_content *bulletin,
bool support_long) {}
static inline int bnx2x_vfpf_update_vlan(struct bnx2x *bp, u16 vid, u8 vf_qid, bool add) {return 0; }
#endif /* CONFIG_BNX2X_SRIOV */
#endif /* bnx2x_sriov.h */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
+2005
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.h
+566
View File
@@ -0,0 +1,566 @@
/* bnx2x_stats.h: QLogic Everest network driver.
*
* Copyright (c) 2007-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Eliezer Tamir
* Based on code from Michael Chan's bnx2 driver
* UDP CSUM errata workaround by Arik Gendelman
* Slowpath and fastpath rework by Vladislav Zolotarov
* Statistics and Link management by Yitchak Gertner
*
*/
#ifndef BNX2X_STATS_H
#define BNX2X_STATS_H
#include <linux/types.h>
struct nig_stats {
u32 brb_discard;
u32 brb_packet;
u32 brb_truncate;
u32 flow_ctrl_discard;
u32 flow_ctrl_octets;
u32 flow_ctrl_packet;
u32 mng_discard;
u32 mng_octet_inp;
u32 mng_octet_out;
u32 mng_packet_inp;
u32 mng_packet_out;
u32 pbf_octets;
u32 pbf_packet;
u32 safc_inp;
struct_group(egress_mac_pkt0,
u32 egress_mac_pkt0_lo;
u32 egress_mac_pkt0_hi;
);
struct_group(egress_mac_pkt1,
u32 egress_mac_pkt1_lo;
u32 egress_mac_pkt1_hi;
);
};
enum bnx2x_stats_event {
STATS_EVENT_PMF = 0,
STATS_EVENT_LINK_UP,
STATS_EVENT_UPDATE,
STATS_EVENT_STOP,
STATS_EVENT_MAX
};
enum bnx2x_stats_state {
STATS_STATE_DISABLED = 0,
STATS_STATE_ENABLED,
STATS_STATE_MAX
};
struct bnx2x_eth_stats {
u32 total_bytes_received_hi;
u32 total_bytes_received_lo;
u32 total_bytes_transmitted_hi;
u32 total_bytes_transmitted_lo;
u32 total_unicast_packets_received_hi;
u32 total_unicast_packets_received_lo;
u32 total_multicast_packets_received_hi;
u32 total_multicast_packets_received_lo;
u32 total_broadcast_packets_received_hi;
u32 total_broadcast_packets_received_lo;
u32 total_unicast_packets_transmitted_hi;
u32 total_unicast_packets_transmitted_lo;
u32 total_multicast_packets_transmitted_hi;
u32 total_multicast_packets_transmitted_lo;
u32 total_broadcast_packets_transmitted_hi;
u32 total_broadcast_packets_transmitted_lo;
u32 valid_bytes_received_hi;
u32 valid_bytes_received_lo;
u32 error_bytes_received_hi;
u32 error_bytes_received_lo;
u32 etherstatsoverrsizepkts_hi;
u32 etherstatsoverrsizepkts_lo;
u32 no_buff_discard_hi;
u32 no_buff_discard_lo;
struct_group(shared,
u32 rx_stat_ifhcinbadoctets_hi;
u32 rx_stat_ifhcinbadoctets_lo;
u32 tx_stat_ifhcoutbadoctets_hi;
u32 tx_stat_ifhcoutbadoctets_lo;
u32 rx_stat_dot3statsfcserrors_hi;
u32 rx_stat_dot3statsfcserrors_lo;
u32 rx_stat_dot3statsalignmenterrors_hi;
u32 rx_stat_dot3statsalignmenterrors_lo;
u32 rx_stat_dot3statscarriersenseerrors_hi;
u32 rx_stat_dot3statscarriersenseerrors_lo;
u32 rx_stat_falsecarriererrors_hi;
u32 rx_stat_falsecarriererrors_lo;
u32 rx_stat_etherstatsundersizepkts_hi;
u32 rx_stat_etherstatsundersizepkts_lo;
u32 rx_stat_dot3statsframestoolong_hi;
u32 rx_stat_dot3statsframestoolong_lo;
u32 rx_stat_etherstatsfragments_hi;
u32 rx_stat_etherstatsfragments_lo;
u32 rx_stat_etherstatsjabbers_hi;
u32 rx_stat_etherstatsjabbers_lo;
u32 rx_stat_maccontrolframesreceived_hi;
u32 rx_stat_maccontrolframesreceived_lo;
u32 rx_stat_bmac_xpf_hi;
u32 rx_stat_bmac_xpf_lo;
u32 rx_stat_bmac_xcf_hi;
u32 rx_stat_bmac_xcf_lo;
u32 rx_stat_xoffstateentered_hi;
u32 rx_stat_xoffstateentered_lo;
u32 rx_stat_xonpauseframesreceived_hi;
u32 rx_stat_xonpauseframesreceived_lo;
u32 rx_stat_xoffpauseframesreceived_hi;
u32 rx_stat_xoffpauseframesreceived_lo;
u32 tx_stat_outxonsent_hi;
u32 tx_stat_outxonsent_lo;
u32 tx_stat_outxoffsent_hi;
u32 tx_stat_outxoffsent_lo;
u32 tx_stat_flowcontroldone_hi;
u32 tx_stat_flowcontroldone_lo;
u32 tx_stat_etherstatscollisions_hi;
u32 tx_stat_etherstatscollisions_lo;
u32 tx_stat_dot3statssinglecollisionframes_hi;
u32 tx_stat_dot3statssinglecollisionframes_lo;
u32 tx_stat_dot3statsmultiplecollisionframes_hi;
u32 tx_stat_dot3statsmultiplecollisionframes_lo;
u32 tx_stat_dot3statsdeferredtransmissions_hi;
u32 tx_stat_dot3statsdeferredtransmissions_lo;
u32 tx_stat_dot3statsexcessivecollisions_hi;
u32 tx_stat_dot3statsexcessivecollisions_lo;
u32 tx_stat_dot3statslatecollisions_hi;
u32 tx_stat_dot3statslatecollisions_lo;
u32 tx_stat_etherstatspkts64octets_hi;
u32 tx_stat_etherstatspkts64octets_lo;
u32 tx_stat_etherstatspkts65octetsto127octets_hi;
u32 tx_stat_etherstatspkts65octetsto127octets_lo;
u32 tx_stat_etherstatspkts128octetsto255octets_hi;
u32 tx_stat_etherstatspkts128octetsto255octets_lo;
u32 tx_stat_etherstatspkts256octetsto511octets_hi;
u32 tx_stat_etherstatspkts256octetsto511octets_lo;
u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
u32 tx_stat_etherstatspktsover1522octets_hi;
u32 tx_stat_etherstatspktsover1522octets_lo;
u32 tx_stat_bmac_2047_hi;
u32 tx_stat_bmac_2047_lo;
u32 tx_stat_bmac_4095_hi;
u32 tx_stat_bmac_4095_lo;
u32 tx_stat_bmac_9216_hi;
u32 tx_stat_bmac_9216_lo;
u32 tx_stat_bmac_16383_hi;
u32 tx_stat_bmac_16383_lo;
u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
u32 tx_stat_bmac_ufl_hi;
u32 tx_stat_bmac_ufl_lo;
);
u32 pause_frames_received_hi;
u32 pause_frames_received_lo;
u32 pause_frames_sent_hi;
u32 pause_frames_sent_lo;
u32 etherstatspkts1024octetsto1522octets_hi;
u32 etherstatspkts1024octetsto1522octets_lo;
u32 etherstatspktsover1522octets_hi;
u32 etherstatspktsover1522octets_lo;
u32 brb_drop_hi;
u32 brb_drop_lo;
u32 brb_truncate_hi;
u32 brb_truncate_lo;
u32 mac_filter_discard;
u32 mf_tag_discard;
u32 brb_truncate_discard;
u32 mac_discard;
u32 driver_xoff;
u32 rx_err_discard_pkt;
u32 rx_skb_alloc_failed;
u32 hw_csum_err;
u32 nig_timer_max;
/* TPA */
u32 total_tpa_aggregations_hi;
u32 total_tpa_aggregations_lo;
u32 total_tpa_aggregated_frames_hi;
u32 total_tpa_aggregated_frames_lo;
u32 total_tpa_bytes_hi;
u32 total_tpa_bytes_lo;
/* PFC */
u32 pfc_frames_received_hi;
u32 pfc_frames_received_lo;
u32 pfc_frames_sent_hi;
u32 pfc_frames_sent_lo;
/* Recovery */
u32 recoverable_error;
u32 unrecoverable_error;
u32 driver_filtered_tx_pkt;
/* src: Clear-on-Read register; Will not survive PMF Migration */
u32 eee_tx_lpi;
/* PTP */
u32 ptp_skip_tx_ts;
};
struct bnx2x_eth_q_stats {
u32 total_unicast_bytes_received_hi;
u32 total_unicast_bytes_received_lo;
u32 total_broadcast_bytes_received_hi;
u32 total_broadcast_bytes_received_lo;
u32 total_multicast_bytes_received_hi;
u32 total_multicast_bytes_received_lo;
u32 total_bytes_received_hi;
u32 total_bytes_received_lo;
u32 total_unicast_bytes_transmitted_hi;
u32 total_unicast_bytes_transmitted_lo;
u32 total_broadcast_bytes_transmitted_hi;
u32 total_broadcast_bytes_transmitted_lo;
u32 total_multicast_bytes_transmitted_hi;
u32 total_multicast_bytes_transmitted_lo;
u32 total_bytes_transmitted_hi;
u32 total_bytes_transmitted_lo;
u32 total_unicast_packets_received_hi;
u32 total_unicast_packets_received_lo;
u32 total_multicast_packets_received_hi;
u32 total_multicast_packets_received_lo;
u32 total_broadcast_packets_received_hi;
u32 total_broadcast_packets_received_lo;
u32 total_unicast_packets_transmitted_hi;
u32 total_unicast_packets_transmitted_lo;
u32 total_multicast_packets_transmitted_hi;
u32 total_multicast_packets_transmitted_lo;
u32 total_broadcast_packets_transmitted_hi;
u32 total_broadcast_packets_transmitted_lo;
u32 valid_bytes_received_hi;
u32 valid_bytes_received_lo;
u32 etherstatsoverrsizepkts_hi;
u32 etherstatsoverrsizepkts_lo;
u32 no_buff_discard_hi;
u32 no_buff_discard_lo;
u32 driver_xoff;
u32 rx_err_discard_pkt;
u32 rx_skb_alloc_failed;
u32 hw_csum_err;
u32 total_packets_received_checksum_discarded_hi;
u32 total_packets_received_checksum_discarded_lo;
u32 total_packets_received_ttl0_discarded_hi;
u32 total_packets_received_ttl0_discarded_lo;
u32 total_transmitted_dropped_packets_error_hi;
u32 total_transmitted_dropped_packets_error_lo;
/* TPA */
u32 total_tpa_aggregations_hi;
u32 total_tpa_aggregations_lo;
u32 total_tpa_aggregated_frames_hi;
u32 total_tpa_aggregated_frames_lo;
u32 total_tpa_bytes_hi;
u32 total_tpa_bytes_lo;
u32 driver_filtered_tx_pkt;
};
struct bnx2x_eth_stats_old {
u32 rx_stat_dot3statsframestoolong_hi;
u32 rx_stat_dot3statsframestoolong_lo;
};
struct bnx2x_eth_q_stats_old {
/* Fields to perserve over fw reset*/
u32 total_unicast_bytes_received_hi;
u32 total_unicast_bytes_received_lo;
u32 total_broadcast_bytes_received_hi;
u32 total_broadcast_bytes_received_lo;
u32 total_multicast_bytes_received_hi;
u32 total_multicast_bytes_received_lo;
u32 total_unicast_bytes_transmitted_hi;
u32 total_unicast_bytes_transmitted_lo;
u32 total_broadcast_bytes_transmitted_hi;
u32 total_broadcast_bytes_transmitted_lo;
u32 total_multicast_bytes_transmitted_hi;
u32 total_multicast_bytes_transmitted_lo;
u32 total_tpa_bytes_hi;
u32 total_tpa_bytes_lo;
/* Fields to perserve last of */
u32 total_bytes_received_hi;
u32 total_bytes_received_lo;
u32 total_bytes_transmitted_hi;
u32 total_bytes_transmitted_lo;
u32 total_unicast_packets_received_hi;
u32 total_unicast_packets_received_lo;
u32 total_multicast_packets_received_hi;
u32 total_multicast_packets_received_lo;
u32 total_broadcast_packets_received_hi;
u32 total_broadcast_packets_received_lo;
u32 total_unicast_packets_transmitted_hi;
u32 total_unicast_packets_transmitted_lo;
u32 total_multicast_packets_transmitted_hi;
u32 total_multicast_packets_transmitted_lo;
u32 total_broadcast_packets_transmitted_hi;
u32 total_broadcast_packets_transmitted_lo;
u32 valid_bytes_received_hi;
u32 valid_bytes_received_lo;
u32 total_tpa_bytes_hi_old;
u32 total_tpa_bytes_lo_old;
u32 driver_xoff_old;
u32 rx_err_discard_pkt_old;
u32 rx_skb_alloc_failed_old;
u32 hw_csum_err_old;
u32 driver_filtered_tx_pkt_old;
};
struct bnx2x_net_stats_old {
u32 rx_dropped;
};
struct bnx2x_fw_port_stats_old {
u32 mac_filter_discard;
u32 mf_tag_discard;
u32 brb_truncate_discard;
u32 mac_discard;
};
/****************************************************************************
* Macros
****************************************************************************/
/* sum[hi:lo] += add[hi:lo] */
#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
do { \
s_lo += a_lo; \
s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
} while (0)
#define LE32_0 ((__force __le32) 0)
#define LE16_0 ((__force __le16) 0)
/* The _force is for cases where high value is 0 */
#define ADD_64_LE(s_hi, a_hi_le, s_lo, a_lo_le) \
ADD_64(s_hi, le32_to_cpu(a_hi_le), \
s_lo, le32_to_cpu(a_lo_le))
#define ADD_64_LE16(s_hi, a_hi_le, s_lo, a_lo_le) \
ADD_64(s_hi, le16_to_cpu(a_hi_le), \
s_lo, le16_to_cpu(a_lo_le))
/* difference = minuend - subtrahend */
#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
do { \
if (m_lo < s_lo) { \
/* underflow */ \
d_hi = m_hi - s_hi; \
if (d_hi > 0) { \
/* we can 'loan' 1 */ \
d_hi--; \
d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
} else { \
/* m_hi <= s_hi */ \
d_hi = 0; \
d_lo = 0; \
} \
} else { \
/* m_lo >= s_lo */ \
if (m_hi < s_hi) { \
d_hi = 0; \
d_lo = 0; \
} else { \
/* m_hi >= s_hi */ \
d_hi = m_hi - s_hi; \
d_lo = m_lo - s_lo; \
} \
} \
} while (0)
#define UPDATE_STAT64(s, t) \
do { \
DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
pstats->mac_stx[0].t##_hi = new->s##_hi; \
pstats->mac_stx[0].t##_lo = new->s##_lo; \
ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
pstats->mac_stx[1].t##_lo, diff.lo); \
} while (0)
#define UPDATE_STAT64_NIG(s, t) \
do { \
DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
diff.lo, new->s##_lo, old->s##_lo); \
ADD_64(estats->t##_hi, diff.hi, \
estats->t##_lo, diff.lo); \
} while (0)
/* sum[hi:lo] += add */
#define ADD_EXTEND_64(s_hi, s_lo, a) \
do { \
s_lo += a; \
s_hi += (s_lo < a) ? 1 : 0; \
} while (0)
#define ADD_STAT64(diff, t) \
do { \
ADD_64(pstats->mac_stx[1].t##_hi, new->diff##_hi, \
pstats->mac_stx[1].t##_lo, new->diff##_lo); \
} while (0)
#define UPDATE_EXTEND_STAT(s) \
do { \
ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
pstats->mac_stx[1].s##_lo, \
new->s); \
} while (0)
#define UPDATE_EXTEND_TSTAT_X(s, t, size) \
do { \
diff = le##size##_to_cpu(tclient->s) - \
le##size##_to_cpu(old_tclient->s); \
old_tclient->s = tclient->s; \
ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
} while (0)
#define UPDATE_EXTEND_TSTAT(s, t) UPDATE_EXTEND_TSTAT_X(s, t, 32)
#define UPDATE_EXTEND_E_TSTAT(s, t, size) \
do { \
UPDATE_EXTEND_TSTAT_X(s, t, size); \
ADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \
} while (0)
#define UPDATE_EXTEND_USTAT(s, t) \
do { \
diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
old_uclient->s = uclient->s; \
ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
} while (0)
#define UPDATE_EXTEND_E_USTAT(s, t) \
do { \
UPDATE_EXTEND_USTAT(s, t); \
ADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \
} while (0)
#define UPDATE_EXTEND_XSTAT(s, t) \
do { \
diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
old_xclient->s = xclient->s; \
ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
} while (0)
#define UPDATE_QSTAT(s, t) \
do { \
qstats->t##_lo = qstats_old->t##_lo + le32_to_cpu(s.lo); \
qstats->t##_hi = qstats_old->t##_hi + le32_to_cpu(s.hi) \
+ ((qstats->t##_lo < qstats_old->t##_lo) ? 1 : 0); \
} while (0)
#define UPDATE_QSTAT_OLD(f) \
do { \
qstats_old->f = qstats->f; \
} while (0)
#define UPDATE_ESTAT_QSTAT_64(s) \
do { \
ADD_64(estats->s##_hi, qstats->s##_hi, \
estats->s##_lo, qstats->s##_lo); \
SUB_64(estats->s##_hi, qstats_old->s##_hi_old, \
estats->s##_lo, qstats_old->s##_lo_old); \
qstats_old->s##_hi_old = qstats->s##_hi; \
qstats_old->s##_lo_old = qstats->s##_lo; \
} while (0)
#define UPDATE_ESTAT_QSTAT(s) \
do { \
estats->s += qstats->s; \
estats->s -= qstats_old->s##_old; \
qstats_old->s##_old = qstats->s; \
} while (0)
#define UPDATE_FSTAT_QSTAT(s) \
do { \
ADD_64(fstats->s##_hi, qstats->s##_hi, \
fstats->s##_lo, qstats->s##_lo); \
SUB_64(fstats->s##_hi, qstats_old->s##_hi, \
fstats->s##_lo, qstats_old->s##_lo); \
estats->s##_hi = fstats->s##_hi; \
estats->s##_lo = fstats->s##_lo; \
qstats_old->s##_hi = qstats->s##_hi; \
qstats_old->s##_lo = qstats->s##_lo; \
} while (0)
#define UPDATE_FW_STAT(s) \
do { \
estats->s = le32_to_cpu(tport->s) + fwstats->s; \
} while (0)
#define UPDATE_FW_STAT_OLD(f) \
do { \
fwstats->f = estats->f; \
} while (0)
#define UPDATE_ESTAT(s, t) \
do { \
SUB_64(estats->s##_hi, estats_old->t##_hi, \
estats->s##_lo, estats_old->t##_lo); \
ADD_64(estats->s##_hi, estats->t##_hi, \
estats->s##_lo, estats->t##_lo); \
estats_old->t##_hi = estats->t##_hi; \
estats_old->t##_lo = estats->t##_lo; \
} while (0)
/* minuend -= subtrahend */
#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
do { \
DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
} while (0)
/* minuend[hi:lo] -= subtrahend */
#define SUB_EXTEND_64(m_hi, m_lo, s) \
do { \
SUB_64(m_hi, 0, m_lo, s); \
} while (0)
#define SUB_EXTEND_USTAT(s, t) \
do { \
diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
} while (0)
/* forward */
struct bnx2x;
void bnx2x_memset_stats(struct bnx2x *bp);
void bnx2x_stats_init(struct bnx2x *bp);
void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
int bnx2x_stats_safe_exec(struct bnx2x *bp,
void (func_to_exec)(void *cookie),
void *cookie);
/**
* bnx2x_save_statistics - save statistics when unloading.
*
* @bp: driver handle
*/
void bnx2x_save_statistics(struct bnx2x *bp);
void bnx2x_afex_collect_stats(struct bnx2x *bp, void *void_afex_stats,
u32 stats_type);
#endif /* BNX2X_STATS_H */
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
+2313
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.h
+473
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@@ -0,0 +1,473 @@
/* bnx2x_vfpf.h: Qlogic Everest network driver.
*
* Copyright (c) 2011-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* Unless you and Qlogic execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the “GPL”),
* available at http://www.gnu.org/licenses/gpl-2.0.html, with the following
* added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions
* of the license of that module. An independent module is a module which is
* not derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
* Written by: Ariel Elior <ariel.elior@qlogic.com>
*/
#ifndef VF_PF_IF_H
#define VF_PF_IF_H
#ifdef CONFIG_BNX2X_SRIOV
/* Common definitions for all HVs */
struct vf_pf_resc_request {
u8 num_rxqs;
u8 num_txqs;
u8 num_sbs;
u8 num_mac_filters;
u8 num_vlan_filters;
u8 num_mc_filters; /* No limit so superfluous */
};
struct hw_sb_info {
u8 hw_sb_id; /* aka absolute igu id, used to ack the sb */
u8 sb_qid; /* used to update DHC for sb */
};
/* HW VF-PF channel definitions
* A.K.A VF-PF mailbox
*/
#define TLV_BUFFER_SIZE 1024
#define PF_VF_BULLETIN_SIZE 512
#define VFPF_QUEUE_FLG_TPA 0x0001
#define VFPF_QUEUE_FLG_TPA_IPV6 0x0002
#define VFPF_QUEUE_FLG_TPA_GRO 0x0004
#define VFPF_QUEUE_FLG_CACHE_ALIGN 0x0008
#define VFPF_QUEUE_FLG_STATS 0x0010
#define VFPF_QUEUE_FLG_OV 0x0020
#define VFPF_QUEUE_FLG_VLAN 0x0040
#define VFPF_QUEUE_FLG_COS 0x0080
#define VFPF_QUEUE_FLG_HC 0x0100
#define VFPF_QUEUE_FLG_DHC 0x0200
#define VFPF_QUEUE_FLG_LEADING_RSS 0x0400
#define VFPF_QUEUE_DROP_IP_CS_ERR (1 << 0)
#define VFPF_QUEUE_DROP_TCP_CS_ERR (1 << 1)
#define VFPF_QUEUE_DROP_TTL0 (1 << 2)
#define VFPF_QUEUE_DROP_UDP_CS_ERR (1 << 3)
#define VFPF_RX_MASK_ACCEPT_NONE 0x00000000
#define VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST 0x00000001
#define VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST 0x00000002
#define VFPF_RX_MASK_ACCEPT_ALL_UNICAST 0x00000004
#define VFPF_RX_MASK_ACCEPT_ALL_MULTICAST 0x00000008
#define VFPF_RX_MASK_ACCEPT_BROADCAST 0x00000010
#define VFPF_RX_MASK_ACCEPT_ANY_VLAN 0x00000020
#define BULLETIN_CONTENT_SIZE (sizeof(struct pf_vf_bulletin_content))
#define BULLETIN_CONTENT_LEGACY_SIZE (32)
#define BULLETIN_ATTEMPTS 5 /* crc failures before throwing towel */
#define BULLETIN_CRC_SEED 0
enum {
PFVF_STATUS_WAITING = 0,
PFVF_STATUS_SUCCESS,
PFVF_STATUS_FAILURE,
PFVF_STATUS_NOT_SUPPORTED,
PFVF_STATUS_NO_RESOURCE
};
/* vf pf channel tlvs */
/* general tlv header (used for both vf->pf request and pf->vf response) */
struct channel_tlv {
u16 type;
u16 length;
};
/* header of first vf->pf tlv carries the offset used to calculate response
* buffer address
*/
struct vfpf_first_tlv {
struct channel_tlv tl;
u32 resp_msg_offset;
};
/* header of pf->vf tlvs, carries the status of handling the request */
struct pfvf_tlv {
struct channel_tlv tl;
u8 status;
u8 padding[3];
};
/* response tlv used for most tlvs */
struct pfvf_general_resp_tlv {
struct pfvf_tlv hdr;
};
/* used to terminate and pad a tlv list */
struct channel_list_end_tlv {
struct channel_tlv tl;
u8 padding[4];
};
/* Acquire */
struct vfpf_acquire_tlv {
struct vfpf_first_tlv first_tlv;
struct vf_pf_vfdev_info {
/* the following fields are for debug purposes */
u8 vf_id; /* ME register value */
u8 vf_os; /* e.g. Linux, W2K8 */
#define VF_OS_SUBVERSION_MASK (0x1f)
#define VF_OS_MASK (0xe0)
#define VF_OS_SHIFT (5)
#define VF_OS_UNDEFINED (0 << VF_OS_SHIFT)
#define VF_OS_WINDOWS (1 << VF_OS_SHIFT)
u8 fp_hsi_ver;
u8 caps;
#define VF_CAP_SUPPORT_EXT_BULLETIN (1 << 0)
#define VF_CAP_SUPPORT_VLAN_FILTER (1 << 1)
} vfdev_info;
struct vf_pf_resc_request resc_request;
aligned_u64 bulletin_addr;
};
/* simple operation request on queue */
struct vfpf_q_op_tlv {
struct vfpf_first_tlv first_tlv;
u8 vf_qid;
u8 padding[3];
};
/* receive side scaling tlv */
struct vfpf_rss_tlv {
struct vfpf_first_tlv first_tlv;
u32 rss_flags;
#define VFPF_RSS_MODE_DISABLED (1 << 0)
#define VFPF_RSS_MODE_REGULAR (1 << 1)
#define VFPF_RSS_SET_SRCH (1 << 2)
#define VFPF_RSS_IPV4 (1 << 3)
#define VFPF_RSS_IPV4_TCP (1 << 4)
#define VFPF_RSS_IPV4_UDP (1 << 5)
#define VFPF_RSS_IPV6 (1 << 6)
#define VFPF_RSS_IPV6_TCP (1 << 7)
#define VFPF_RSS_IPV6_UDP (1 << 8)
u8 rss_result_mask;
u8 ind_table_size;
u8 rss_key_size;
u8 padding;
u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
u32 rss_key[T_ETH_RSS_KEY]; /* hash values */
};
/* acquire response tlv - carries the allocated resources */
struct pfvf_acquire_resp_tlv {
struct pfvf_tlv hdr;
struct pf_vf_pfdev_info {
u32 chip_num;
u32 pf_cap;
#define PFVF_CAP_RSS 0x00000001
#define PFVF_CAP_DHC 0x00000002
#define PFVF_CAP_TPA 0x00000004
#define PFVF_CAP_TPA_UPDATE 0x00000008
#define PFVF_CAP_VLAN_FILTER 0x00000010
char fw_ver[32];
u16 db_size;
u8 indices_per_sb;
u8 padding;
} pfdev_info;
struct pf_vf_resc {
/* in case of status NO_RESOURCE in message hdr, pf will fill
* this struct with suggested amount of resources for next
* acquire request
*/
#define PFVF_MAX_QUEUES_PER_VF 16
#define PFVF_MAX_SBS_PER_VF 16
struct hw_sb_info hw_sbs[PFVF_MAX_SBS_PER_VF];
u8 hw_qid[PFVF_MAX_QUEUES_PER_VF];
u8 num_rxqs;
u8 num_txqs;
u8 num_sbs;
u8 num_mac_filters;
u8 num_vlan_filters;
u8 num_mc_filters;
u8 permanent_mac_addr[ETH_ALEN];
u8 current_mac_addr[ETH_ALEN];
u8 padding[2];
} resc;
};
struct vfpf_port_phys_id_resp_tlv {
struct channel_tlv tl;
u8 id[ETH_ALEN];
u8 padding[2];
};
struct vfpf_fp_hsi_resp_tlv {
struct channel_tlv tl;
u8 is_supported;
u8 padding[3];
};
#define VFPF_INIT_FLG_STATS_COALESCE (1 << 0) /* when set the VFs queues
* stats will be coalesced on
* the leading RSS queue
*/
/* Init VF */
struct vfpf_init_tlv {
struct vfpf_first_tlv first_tlv;
aligned_u64 sb_addr[PFVF_MAX_SBS_PER_VF]; /* vf_sb based */
aligned_u64 spq_addr;
aligned_u64 stats_addr;
u16 stats_stride;
u32 flags;
u32 padding[2];
};
/* Setup Queue */
struct vfpf_setup_q_tlv {
struct vfpf_first_tlv first_tlv;
struct vf_pf_rxq_params {
/* physical addresses */
aligned_u64 rcq_addr;
aligned_u64 rcq_np_addr;
aligned_u64 rxq_addr;
aligned_u64 sge_addr;
/* sb + hc info */
u8 vf_sb; /* index in hw_sbs[] */
u8 sb_index; /* Index in the SB */
u16 hc_rate; /* desired interrupts per sec. */
/* valid iff VFPF_QUEUE_FLG_HC */
/* rx buffer info */
u16 mtu;
u16 buf_sz;
u16 flags; /* VFPF_QUEUE_FLG_X flags */
u16 stat_id; /* valid iff VFPF_QUEUE_FLG_STATS */
/* valid iff VFPF_QUEUE_FLG_TPA */
u16 sge_buf_sz;
u16 tpa_agg_sz;
u8 max_sge_pkt;
u8 drop_flags; /* VFPF_QUEUE_DROP_X, for Linux VMs
* all the flags are turned off
*/
u8 cache_line_log; /* VFPF_QUEUE_FLG_CACHE_ALIGN */
u8 padding;
} rxq;
struct vf_pf_txq_params {
/* physical addresses */
aligned_u64 txq_addr;
/* sb + hc info */
u8 vf_sb; /* index in hw_sbs[] */
u8 sb_index; /* Index in the SB */
u16 hc_rate; /* desired interrupts per sec. */
/* valid iff VFPF_QUEUE_FLG_HC */
u32 flags; /* VFPF_QUEUE_FLG_X flags */
u16 stat_id; /* valid iff VFPF_QUEUE_FLG_STATS */
u8 traffic_type; /* see in setup_context() */
u8 padding;
} txq;
u8 vf_qid; /* index in hw_qid[] */
u8 param_valid;
#define VFPF_RXQ_VALID 0x01
#define VFPF_TXQ_VALID 0x02
u8 padding[2];
};
/* Set Queue Filters */
struct vfpf_q_mac_vlan_filter {
u32 flags;
#define VFPF_Q_FILTER_DEST_MAC_VALID 0x01
#define VFPF_Q_FILTER_VLAN_TAG_VALID 0x02
#define VFPF_Q_FILTER_SET 0x100 /* set/clear */
u8 mac[ETH_ALEN];
u16 vlan_tag;
};
/* configure queue filters */
struct vfpf_set_q_filters_tlv {
struct vfpf_first_tlv first_tlv;
u32 flags;
#define VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED 0x01
#define VFPF_SET_Q_FILTERS_MULTICAST_CHANGED 0x02
#define VFPF_SET_Q_FILTERS_RX_MASK_CHANGED 0x04
u8 vf_qid; /* index in hw_qid[] */
u8 n_mac_vlan_filters;
u8 n_multicast;
u8 padding;
#define PFVF_MAX_MAC_FILTERS 16
#define PFVF_MAX_VLAN_FILTERS 16
#define PFVF_MAX_FILTERS (PFVF_MAX_MAC_FILTERS +\
PFVF_MAX_VLAN_FILTERS)
struct vfpf_q_mac_vlan_filter filters[PFVF_MAX_FILTERS];
#define PFVF_MAX_MULTICAST_PER_VF 32
u8 multicast[PFVF_MAX_MULTICAST_PER_VF][ETH_ALEN];
u32 rx_mask; /* see mask constants at the top of the file */
};
struct vfpf_tpa_tlv {
struct vfpf_first_tlv first_tlv;
struct vf_pf_tpa_client_info {
aligned_u64 sge_addr[PFVF_MAX_QUEUES_PER_VF];
u8 update_ipv4;
u8 update_ipv6;
u8 max_tpa_queues;
u8 max_sges_for_packet;
u8 complete_on_both_clients;
u8 dont_verify_thr;
u8 tpa_mode;
u16 sge_buff_size;
u16 max_agg_size;
u16 sge_pause_thr_low;
u16 sge_pause_thr_high;
} tpa_client_info;
};
/* close VF (disable VF) */
struct vfpf_close_tlv {
struct vfpf_first_tlv first_tlv;
u16 vf_id; /* for debug */
u8 padding[2];
};
/* release the VF's acquired resources */
struct vfpf_release_tlv {
struct vfpf_first_tlv first_tlv;
u16 vf_id;
u8 padding[2];
};
struct tlv_buffer_size {
u8 tlv_buffer[TLV_BUFFER_SIZE];
};
union vfpf_tlvs {
struct vfpf_first_tlv first_tlv;
struct vfpf_acquire_tlv acquire;
struct vfpf_init_tlv init;
struct vfpf_close_tlv close;
struct vfpf_q_op_tlv q_op;
struct vfpf_setup_q_tlv setup_q;
struct vfpf_set_q_filters_tlv set_q_filters;
struct vfpf_release_tlv release;
struct vfpf_rss_tlv update_rss;
struct vfpf_tpa_tlv update_tpa;
struct channel_list_end_tlv list_end;
struct tlv_buffer_size tlv_buf_size;
};
union pfvf_tlvs {
struct pfvf_general_resp_tlv general_resp;
struct pfvf_acquire_resp_tlv acquire_resp;
struct channel_list_end_tlv list_end;
struct tlv_buffer_size tlv_buf_size;
};
/* This is a structure which is allocated in the VF, which the PF may update
* when it deems it necessary to do so. The bulletin board is sampled
* periodically by the VF. A copy per VF is maintained in the PF (to prevent
* loss of data upon multiple updates (or the need for read modify write)).
*/
struct pf_vf_bulletin_size {
u8 size[PF_VF_BULLETIN_SIZE];
};
struct pf_vf_bulletin_content {
u32 crc; /* crc of structure to ensure is not in
* mid-update
*/
u16 version;
u16 length;
aligned_u64 valid_bitmap; /* bitmap indicating which fields
* hold valid values
*/
#define MAC_ADDR_VALID 0 /* alert the vf that a new mac address
* is available for it
*/
#define VLAN_VALID 1 /* when set, the vf should not access
* the vfpf channel
*/
#define CHANNEL_DOWN 2 /* vfpf channel is disabled. VFs are not
* to attempt to send messages on the
* channel after this bit is set
*/
#define LINK_VALID 3 /* alert the VF thet a new link status
* update is available for it
*/
u8 mac[ETH_ALEN];
u8 mac_padding[2];
u16 vlan;
u8 vlan_padding[6];
u16 link_speed; /* Effective line speed */
u8 link_speed_padding[6];
u32 link_flags; /* VFPF_LINK_REPORT_XXX flags */
#define VFPF_LINK_REPORT_LINK_DOWN (1 << 0)
#define VFPF_LINK_REPORT_FULL_DUPLEX (1 << 1)
#define VFPF_LINK_REPORT_RX_FC_ON (1 << 2)
#define VFPF_LINK_REPORT_TX_FC_ON (1 << 3)
u8 link_flags_padding[4];
};
union pf_vf_bulletin {
struct pf_vf_bulletin_content content;
struct pf_vf_bulletin_size size;
};
#define MAX_TLVS_IN_LIST 50
enum channel_tlvs {
CHANNEL_TLV_NONE,
CHANNEL_TLV_ACQUIRE,
CHANNEL_TLV_INIT,
CHANNEL_TLV_SETUP_Q,
CHANNEL_TLV_SET_Q_FILTERS,
CHANNEL_TLV_ACTIVATE_Q,
CHANNEL_TLV_DEACTIVATE_Q,
CHANNEL_TLV_TEARDOWN_Q,
CHANNEL_TLV_CLOSE,
CHANNEL_TLV_RELEASE,
CHANNEL_TLV_UPDATE_RSS_DEPRECATED,
CHANNEL_TLV_PF_RELEASE_VF,
CHANNEL_TLV_LIST_END,
CHANNEL_TLV_FLR,
CHANNEL_TLV_PF_SET_MAC,
CHANNEL_TLV_PF_SET_VLAN,
CHANNEL_TLV_UPDATE_RSS,
CHANNEL_TLV_PHYS_PORT_ID,
CHANNEL_TLV_UPDATE_TPA,
CHANNEL_TLV_FP_HSI_SUPPORT,
CHANNEL_TLV_MAX
};
#endif /* CONFIG_BNX2X_SRIOV */
#endif /* VF_PF_IF_H */