lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/Kconfig
+43
View File
@@ -0,0 +1,43 @@
# SPDX-License-Identifier: GPL-2.0-only
config FSL_DPAA2_ETH
tristate "Freescale DPAA2 Ethernet"
depends on FSL_MC_BUS && FSL_MC_DPIO
select PHYLINK
select PCS_LYNX
select FSL_XGMAC_MDIO
select NET_DEVLINK
help
This is the DPAA2 Ethernet driver supporting Freescale SoCs
with DPAA2 (DataPath Acceleration Architecture v2).
The driver manages network objects discovered on the Freescale
MC bus.
if FSL_DPAA2_ETH
config FSL_DPAA2_ETH_DCB
bool "Data Center Bridging (DCB) Support"
default n
depends on DCB
help
Enable Priority-Based Flow Control (PFC) support for DPAA2 Ethernet
devices.
endif
config FSL_DPAA2_PTP_CLOCK
tristate "Freescale DPAA2 PTP Clock"
depends on FSL_DPAA2_ETH && PTP_1588_CLOCK_QORIQ
default y
help
This driver adds support for using the DPAA2 1588 timer module
as a PTP clock.
config FSL_DPAA2_SWITCH
tristate "Freescale DPAA2 Ethernet Switch"
depends on BRIDGE || BRIDGE=n
depends on NET_SWITCHDEV
depends on FSL_MC_BUS && FSL_MC_DPIO
select PHYLINK
select PCS_LYNX
select FSL_XGMAC_MDIO
help
Driver for Freescale DPAA2 Ethernet Switch. This driver manages
switch objects discovered on the Freeescale MC bus.
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/Makefile
+18
View File
@@ -0,0 +1,18 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Freescale DPAA2 Ethernet controller
#
obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o fsl-dpaa2-mac.o
obj-$(CONFIG_FSL_DPAA2_PTP_CLOCK) += fsl-dpaa2-ptp.o
obj-$(CONFIG_FSL_DPAA2_SWITCH) += fsl-dpaa2-switch.o fsl-dpaa2-mac.o
fsl-dpaa2-eth-objs := dpaa2-eth.o dpaa2-ethtool.o dpni.o dpaa2-eth-devlink.o dpaa2-xsk.o
fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_DCB} += dpaa2-eth-dcb.o
fsl-dpaa2-eth-${CONFIG_DEBUG_FS} += dpaa2-eth-debugfs.o
fsl-dpaa2-ptp-objs := dpaa2-ptp.o dprtc.o
fsl-dpaa2-switch-objs := dpaa2-switch.o dpaa2-switch-ethtool.o dpsw.o dpaa2-switch-flower.o
fsl-dpaa2-mac-objs += dpaa2-mac.o dpmac.o
# Needed by the tracing framework
CFLAGS_dpaa2-eth.o := -I$(src)
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-dcb.c
+150
View File
@@ -0,0 +1,150 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2020 NXP */
#include "dpaa2-eth.h"
static int dpaa2_eth_dcbnl_ieee_getpfc(struct net_device *net_dev,
struct ieee_pfc *pfc)
{
struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
if (!(priv->link_state.options & DPNI_LINK_OPT_PFC_PAUSE))
return 0;
memcpy(pfc, &priv->pfc, sizeof(priv->pfc));
pfc->pfc_cap = dpaa2_eth_tc_count(priv);
return 0;
}
static inline bool dpaa2_eth_is_prio_enabled(u8 pfc_en, u8 tc)
{
return !!(pfc_en & (1 << tc));
}
static int dpaa2_eth_set_pfc_cn(struct dpaa2_eth_priv *priv, u8 pfc_en)
{
struct dpni_congestion_notification_cfg cfg = {0};
int i, err;
cfg.notification_mode = DPNI_CONG_OPT_FLOW_CONTROL;
cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
cfg.message_iova = 0ULL;
cfg.message_ctx = 0ULL;
for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
if (dpaa2_eth_is_prio_enabled(pfc_en, i)) {
cfg.threshold_entry = DPAA2_ETH_CN_THRESH_ENTRY(priv);
cfg.threshold_exit = DPAA2_ETH_CN_THRESH_EXIT(priv);
} else {
/* For priorities not set in the pfc_en mask, we leave
* the congestion thresholds at zero, which effectively
* disables generation of PFC frames for them
*/
cfg.threshold_entry = 0;
cfg.threshold_exit = 0;
}
err = dpni_set_congestion_notification(priv->mc_io, 0,
priv->mc_token,
DPNI_QUEUE_RX, i, &cfg);
if (err) {
netdev_err(priv->net_dev,
"dpni_set_congestion_notification failed\n");
return err;
}
}
return 0;
}
static int dpaa2_eth_dcbnl_ieee_setpfc(struct net_device *net_dev,
struct ieee_pfc *pfc)
{
struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
struct dpni_link_cfg link_cfg = {0};
bool tx_pause;
int err;
if (pfc->mbc || pfc->delay)
return -EOPNOTSUPP;
/* If same PFC enabled mask, nothing to do */
if (priv->pfc.pfc_en == pfc->pfc_en)
return 0;
/* We allow PFC configuration even if it won't have any effect until
* general pause frames are enabled
*/
tx_pause = dpaa2_eth_tx_pause_enabled(priv->link_state.options);
if (!dpaa2_eth_rx_pause_enabled(priv->link_state.options) || !tx_pause)
netdev_warn(net_dev, "Pause support must be enabled in order for PFC to work!\n");
link_cfg.rate = priv->link_state.rate;
link_cfg.options = priv->link_state.options;
if (pfc->pfc_en)
link_cfg.options |= DPNI_LINK_OPT_PFC_PAUSE;
else
link_cfg.options &= ~DPNI_LINK_OPT_PFC_PAUSE;
err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
if (err) {
netdev_err(net_dev, "dpni_set_link_cfg failed\n");
return err;
}
/* Configure congestion notifications for the enabled priorities */
err = dpaa2_eth_set_pfc_cn(priv, pfc->pfc_en);
if (err)
return err;
memcpy(&priv->pfc, pfc, sizeof(priv->pfc));
priv->pfc_enabled = !!pfc->pfc_en;
dpaa2_eth_set_rx_taildrop(priv, tx_pause, priv->pfc_enabled);
return 0;
}
static u8 dpaa2_eth_dcbnl_getdcbx(struct net_device *net_dev)
{
struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
return priv->dcbx_mode;
}
static u8 dpaa2_eth_dcbnl_setdcbx(struct net_device *net_dev, u8 mode)
{
struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
return (mode != (priv->dcbx_mode)) ? 1 : 0;
}
static u8 dpaa2_eth_dcbnl_getcap(struct net_device *net_dev, int capid, u8 *cap)
{
struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
switch (capid) {
case DCB_CAP_ATTR_PFC:
*cap = true;
break;
case DCB_CAP_ATTR_PFC_TCS:
*cap = 1 << (dpaa2_eth_tc_count(priv) - 1);
break;
case DCB_CAP_ATTR_DCBX:
*cap = priv->dcbx_mode;
break;
default:
*cap = false;
break;
}
return 0;
}
const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops = {
.ieee_getpfc = dpaa2_eth_dcbnl_ieee_getpfc,
.ieee_setpfc = dpaa2_eth_dcbnl_ieee_setpfc,
.getdcbx = dpaa2_eth_dcbnl_getdcbx,
.setdcbx = dpaa2_eth_dcbnl_setdcbx,
.getcap = dpaa2_eth_dcbnl_getcap,
};
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-debugfs.c
+207
View File
@@ -0,0 +1,207 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2015 Freescale Semiconductor Inc.
* Copyright 2018-2019 NXP
*/
#include <linux/module.h>
#include <linux/debugfs.h>
#include "dpaa2-eth.h"
#include "dpaa2-eth-debugfs.h"
#define DPAA2_ETH_DBG_ROOT "dpaa2-eth"
static struct dentry *dpaa2_dbg_root;
static int dpaa2_dbg_cpu_show(struct seq_file *file, void *offset)
{
struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
struct rtnl_link_stats64 *stats;
struct dpaa2_eth_drv_stats *extras;
int i;
seq_printf(file, "Per-CPU stats for %s\n", priv->net_dev->name);
seq_printf(file, "%s%16s%16s%16s%16s%16s%16s%16s%16s%16s\n",
"CPU", "Rx", "Rx Err", "Rx SG", "Tx", "Tx Err", "Tx conf",
"Tx SG", "Tx converted to SG", "Enq busy");
for_each_online_cpu(i) {
stats = per_cpu_ptr(priv->percpu_stats, i);
extras = per_cpu_ptr(priv->percpu_extras, i);
seq_printf(file, "%3d%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu\n",
i,
stats->rx_packets,
stats->rx_errors,
extras->rx_sg_frames,
stats->tx_packets,
stats->tx_errors,
extras->tx_conf_frames,
extras->tx_sg_frames,
extras->tx_converted_sg_frames,
extras->tx_portal_busy);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(dpaa2_dbg_cpu);
static char *fq_type_to_str(struct dpaa2_eth_fq *fq)
{
switch (fq->type) {
case DPAA2_RX_FQ:
return "Rx";
case DPAA2_TX_CONF_FQ:
return "Tx conf";
default:
return "N/A";
}
}
static int dpaa2_dbg_fqs_show(struct seq_file *file, void *offset)
{
struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
struct dpaa2_eth_fq *fq;
u32 fcnt, bcnt;
int i, err;
seq_printf(file, "FQ stats for %s:\n", priv->net_dev->name);
seq_printf(file, "%s%16s%16s%16s%16s%16s\n",
"VFQID", "CPU", "TC", "Type", "Frames", "Pending frames");
for (i = 0; i < priv->num_fqs; i++) {
fq = &priv->fq[i];
err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
if (err)
fcnt = 0;
/* Skip FQs with no traffic */
if (!fq->stats.frames && !fcnt)
continue;
seq_printf(file, "%5d%16d%16d%16s%16llu%16u\n",
fq->fqid,
fq->target_cpu,
fq->tc,
fq_type_to_str(fq),
fq->stats.frames,
fcnt);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(dpaa2_dbg_fqs);
static int dpaa2_dbg_ch_show(struct seq_file *file, void *offset)
{
struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
struct dpaa2_eth_channel *ch;
int i;
seq_printf(file, "Channel stats for %s:\n", priv->net_dev->name);
seq_printf(file, "%s %5s%16s%16s%16s%16s%16s%16s\n",
"IDX", "CHID", "CPU", "Deq busy", "Frames", "CDANs",
"Avg Frm/CDAN", "Buf count");
for (i = 0; i < priv->num_channels; i++) {
ch = priv->channel[i];
seq_printf(file, "%3s%d%6d%16d%16llu%16llu%16llu%16llu%16d\n",
"CH#", i, ch->ch_id,
ch->nctx.desired_cpu,
ch->stats.dequeue_portal_busy,
ch->stats.frames,
ch->stats.cdan,
div64_u64(ch->stats.frames, ch->stats.cdan),
ch->buf_count);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(dpaa2_dbg_ch);
static int dpaa2_dbg_bp_show(struct seq_file *file, void *offset)
{
struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
int i, j, num_queues, buf_cnt;
struct dpaa2_eth_bp *bp;
char ch_name[10];
int err;
/* Print out the header */
seq_printf(file, "Buffer pool info for %s:\n", priv->net_dev->name);
seq_printf(file, "%s %10s%15s", "IDX", "BPID", "Buf count");
num_queues = dpaa2_eth_queue_count(priv);
for (i = 0; i < num_queues; i++) {
snprintf(ch_name, sizeof(ch_name), "CH#%d", i);
seq_printf(file, "%10s", ch_name);
}
seq_printf(file, "\n");
/* For each buffer pool, print out its BPID, the number of buffers in
* that buffer pool and the channels which are using it.
*/
for (i = 0; i < priv->num_bps; i++) {
bp = priv->bp[i];
err = dpaa2_io_query_bp_count(NULL, bp->bpid, &buf_cnt);
if (err) {
netdev_warn(priv->net_dev, "Buffer count query error %d\n", err);
return err;
}
seq_printf(file, "%3s%d%10d%15d", "BP#", i, bp->bpid, buf_cnt);
for (j = 0; j < num_queues; j++) {
if (priv->channel[j]->bp == bp)
seq_printf(file, "%10s", "x");
else
seq_printf(file, "%10s", "");
}
seq_printf(file, "\n");
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(dpaa2_dbg_bp);
void dpaa2_dbg_add(struct dpaa2_eth_priv *priv)
{
struct fsl_mc_device *dpni_dev;
struct dentry *dir;
char name[10];
/* Create a directory for the interface */
dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent);
snprintf(name, 10, "dpni.%d", dpni_dev->obj_desc.id);
dir = debugfs_create_dir(name, dpaa2_dbg_root);
priv->dbg.dir = dir;
/* per-cpu stats file */
debugfs_create_file("cpu_stats", 0444, dir, priv, &dpaa2_dbg_cpu_fops);
/* per-fq stats file */
debugfs_create_file("fq_stats", 0444, dir, priv, &dpaa2_dbg_fqs_fops);
/* per-fq stats file */
debugfs_create_file("ch_stats", 0444, dir, priv, &dpaa2_dbg_ch_fops);
/* per buffer pool stats file */
debugfs_create_file("bp_stats", 0444, dir, priv, &dpaa2_dbg_bp_fops);
}
void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv)
{
debugfs_remove_recursive(priv->dbg.dir);
}
void dpaa2_eth_dbg_init(void)
{
dpaa2_dbg_root = debugfs_create_dir(DPAA2_ETH_DBG_ROOT, NULL);
pr_debug("DPAA2-ETH: debugfs created\n");
}
void dpaa2_eth_dbg_exit(void)
{
debugfs_remove(dpaa2_dbg_root);
}
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-debugfs.h
+28
View File
@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2015 Freescale Semiconductor Inc.
* Copyright 2018-2019 NXP
*/
#ifndef DPAA2_ETH_DEBUGFS_H
#define DPAA2_ETH_DEBUGFS_H
#include <linux/dcache.h>
struct dpaa2_eth_priv;
struct dpaa2_debugfs {
struct dentry *dir;
};
#ifdef CONFIG_DEBUG_FS
void dpaa2_eth_dbg_init(void);
void dpaa2_eth_dbg_exit(void);
void dpaa2_dbg_add(struct dpaa2_eth_priv *priv);
void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv);
#else
static inline void dpaa2_eth_dbg_init(void) {}
static inline void dpaa2_eth_dbg_exit(void) {}
static inline void dpaa2_dbg_add(struct dpaa2_eth_priv *priv) {}
static inline void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv) {}
#endif /* CONFIG_DEBUG_FS */
#endif /* DPAA2_ETH_DEBUGFS_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-devlink.c
+288
View File
@@ -0,0 +1,288 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
#include "dpaa2-eth.h"
/* Copyright 2020 NXP
*/
#define DPAA2_ETH_TRAP_DROP(_id, _group_id) \
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
DEVLINK_TRAP_GROUP_GENERIC_ID_##_group_id, 0)
static const struct devlink_trap_group dpaa2_eth_trap_groups_arr[] = {
DEVLINK_TRAP_GROUP_GENERIC(PARSER_ERROR_DROPS, 0),
};
static const struct devlink_trap dpaa2_eth_traps_arr[] = {
DPAA2_ETH_TRAP_DROP(VXLAN_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(LLC_SNAP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(VLAN_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(PPPOE_PPP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(MPLS_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(ARP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(IP_1_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(IP_N_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(GRE_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(UDP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(TCP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(IPSEC_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(SCTP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(DCCP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(GTP_PARSING, PARSER_ERROR_DROPS),
DPAA2_ETH_TRAP_DROP(ESP_PARSING, PARSER_ERROR_DROPS),
};
static int dpaa2_eth_dl_info_get(struct devlink *devlink,
struct devlink_info_req *req,
struct netlink_ext_ack *extack)
{
struct dpaa2_eth_devlink_priv *dl_priv = devlink_priv(devlink);
struct dpaa2_eth_priv *priv = dl_priv->dpaa2_priv;
char buf[10];
scnprintf(buf, 10, "%d.%d", priv->dpni_ver_major, priv->dpni_ver_minor);
return devlink_info_version_running_put(req, "dpni", buf);
}
static struct dpaa2_eth_trap_item *
dpaa2_eth_dl_trap_item_lookup(struct dpaa2_eth_priv *priv, u16 trap_id)
{
struct dpaa2_eth_trap_data *dpaa2_eth_trap_data = priv->trap_data;
int i;
for (i = 0; i < ARRAY_SIZE(dpaa2_eth_traps_arr); i++) {
if (dpaa2_eth_traps_arr[i].id == trap_id)
return &dpaa2_eth_trap_data->trap_items_arr[i];
}
return NULL;
}
struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
struct dpaa2_fapr *fapr)
{
static const struct dpaa2_faf_error_bit {
int position;
enum devlink_trap_generic_id trap_id;
} faf_bits[] = {
{ .position = 5, .trap_id = DEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING },
{ .position = 20, .trap_id = DEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING },
{ .position = 24, .trap_id = DEVLINK_TRAP_GENERIC_ID_VLAN_PARSING },
{ .position = 26, .trap_id = DEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING },
{ .position = 29, .trap_id = DEVLINK_TRAP_GENERIC_ID_MPLS_PARSING },
{ .position = 31, .trap_id = DEVLINK_TRAP_GENERIC_ID_ARP_PARSING },
{ .position = 52, .trap_id = DEVLINK_TRAP_GENERIC_ID_IP_1_PARSING },
{ .position = 61, .trap_id = DEVLINK_TRAP_GENERIC_ID_IP_N_PARSING },
{ .position = 67, .trap_id = DEVLINK_TRAP_GENERIC_ID_GRE_PARSING },
{ .position = 71, .trap_id = DEVLINK_TRAP_GENERIC_ID_UDP_PARSING },
{ .position = 76, .trap_id = DEVLINK_TRAP_GENERIC_ID_TCP_PARSING },
{ .position = 80, .trap_id = DEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING },
{ .position = 82, .trap_id = DEVLINK_TRAP_GENERIC_ID_SCTP_PARSING },
{ .position = 84, .trap_id = DEVLINK_TRAP_GENERIC_ID_DCCP_PARSING },
{ .position = 88, .trap_id = DEVLINK_TRAP_GENERIC_ID_GTP_PARSING },
{ .position = 90, .trap_id = DEVLINK_TRAP_GENERIC_ID_ESP_PARSING },
};
u64 faf_word;
u64 mask;
int i;
for (i = 0; i < ARRAY_SIZE(faf_bits); i++) {
if (faf_bits[i].position < 32) {
/* Low part of FAF.
* position ranges from 31 to 0, mask from 0 to 31.
*/
mask = 1ull << (31 - faf_bits[i].position);
faf_word = __le32_to_cpu(fapr->faf_lo);
} else {
/* High part of FAF.
* position ranges from 95 to 32, mask from 0 to 63.
*/
mask = 1ull << (63 - (faf_bits[i].position - 32));
faf_word = __le64_to_cpu(fapr->faf_hi);
}
if (faf_word & mask)
return dpaa2_eth_dl_trap_item_lookup(priv, faf_bits[i].trap_id);
}
return NULL;
}
static int dpaa2_eth_dl_trap_init(struct devlink *devlink,
const struct devlink_trap *trap,
void *trap_ctx)
{
struct dpaa2_eth_devlink_priv *dl_priv = devlink_priv(devlink);
struct dpaa2_eth_priv *priv = dl_priv->dpaa2_priv;
struct dpaa2_eth_trap_item *dpaa2_eth_trap_item;
dpaa2_eth_trap_item = dpaa2_eth_dl_trap_item_lookup(priv, trap->id);
if (WARN_ON(!dpaa2_eth_trap_item))
return -ENOENT;
dpaa2_eth_trap_item->trap_ctx = trap_ctx;
return 0;
}
static int dpaa2_eth_dl_trap_action_set(struct devlink *devlink,
const struct devlink_trap *trap,
enum devlink_trap_action action,
struct netlink_ext_ack *extack)
{
/* No support for changing the action of an independent packet trap,
* only per trap group - parser error drops
*/
NL_SET_ERR_MSG_MOD(extack,
"Cannot change trap action independently of group");
return -EOPNOTSUPP;
}
static int dpaa2_eth_dl_trap_group_action_set(struct devlink *devlink,
const struct devlink_trap_group *group,
enum devlink_trap_action action,
struct netlink_ext_ack *extack)
{
struct dpaa2_eth_devlink_priv *dl_priv = devlink_priv(devlink);
struct dpaa2_eth_priv *priv = dl_priv->dpaa2_priv;
struct net_device *net_dev = priv->net_dev;
struct device *dev = net_dev->dev.parent;
struct dpni_error_cfg err_cfg = {0};
int err;
if (group->id != DEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS)
return -EOPNOTSUPP;
/* Configure handling of frames marked as errors from the parser */
err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
err_cfg.set_frame_annotation = 1;
switch (action) {
case DEVLINK_TRAP_ACTION_DROP:
err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
break;
case DEVLINK_TRAP_ACTION_TRAP:
err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
break;
default:
return -EOPNOTSUPP;
}
err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token, &err_cfg);
if (err) {
dev_err(dev, "dpni_set_errors_behavior failed\n");
return err;
}
return 0;
}
static const struct devlink_ops dpaa2_eth_devlink_ops = {
.info_get = dpaa2_eth_dl_info_get,
.trap_init = dpaa2_eth_dl_trap_init,
.trap_action_set = dpaa2_eth_dl_trap_action_set,
.trap_group_action_set = dpaa2_eth_dl_trap_group_action_set,
};
int dpaa2_eth_dl_alloc(struct dpaa2_eth_priv *priv)
{
struct net_device *net_dev = priv->net_dev;
struct device *dev = net_dev->dev.parent;
struct dpaa2_eth_devlink_priv *dl_priv;
priv->devlink =
devlink_alloc(&dpaa2_eth_devlink_ops, sizeof(*dl_priv), dev);
if (!priv->devlink) {
dev_err(dev, "devlink_alloc failed\n");
return -ENOMEM;
}
dl_priv = devlink_priv(priv->devlink);
dl_priv->dpaa2_priv = priv;
return 0;
}
void dpaa2_eth_dl_free(struct dpaa2_eth_priv *priv)
{
devlink_free(priv->devlink);
}
void dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv)
{
devlink_register(priv->devlink);
}
void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv)
{
devlink_unregister(priv->devlink);
}
int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv)
{
struct devlink_port *devlink_port = &priv->devlink_port;
struct devlink_port_attrs attrs = {};
attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL;
devlink_port_attrs_set(devlink_port, &attrs);
return devlink_port_register(priv->devlink, devlink_port, 0);
}
void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv)
{
struct devlink_port *devlink_port = &priv->devlink_port;
devlink_port_unregister(devlink_port);
}
int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv)
{
struct dpaa2_eth_trap_data *dpaa2_eth_trap_data;
struct net_device *net_dev = priv->net_dev;
struct device *dev = net_dev->dev.parent;
int err;
dpaa2_eth_trap_data = kzalloc_obj(*dpaa2_eth_trap_data);
if (!dpaa2_eth_trap_data)
return -ENOMEM;
priv->trap_data = dpaa2_eth_trap_data;
dpaa2_eth_trap_data->trap_items_arr = kzalloc_objs(struct dpaa2_eth_trap_item,
ARRAY_SIZE(dpaa2_eth_traps_arr));
if (!dpaa2_eth_trap_data->trap_items_arr) {
err = -ENOMEM;
goto trap_data_free;
}
err = devlink_trap_groups_register(priv->devlink, dpaa2_eth_trap_groups_arr,
ARRAY_SIZE(dpaa2_eth_trap_groups_arr));
if (err) {
dev_err(dev, "devlink_trap_groups_register() = %d\n", err);
goto trap_items_arr_free;
}
err = devlink_traps_register(priv->devlink, dpaa2_eth_traps_arr,
ARRAY_SIZE(dpaa2_eth_traps_arr), priv);
if (err) {
dev_err(dev, "devlink_traps_register() = %d\n", err);
goto trap_groups_unregiser;
}
return 0;
trap_groups_unregiser:
devlink_trap_groups_unregister(priv->devlink, dpaa2_eth_trap_groups_arr,
ARRAY_SIZE(dpaa2_eth_trap_groups_arr));
trap_items_arr_free:
kfree(dpaa2_eth_trap_data->trap_items_arr);
trap_data_free:
kfree(dpaa2_eth_trap_data);
priv->trap_data = NULL;
return err;
}
void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv)
{
devlink_traps_unregister(priv->devlink, dpaa2_eth_traps_arr,
ARRAY_SIZE(dpaa2_eth_traps_arr));
devlink_trap_groups_unregister(priv->devlink, dpaa2_eth_trap_groups_arr,
ARRAY_SIZE(dpaa2_eth_trap_groups_arr));
kfree(priv->trap_data->trap_items_arr);
kfree(priv->trap_data);
}
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-trace.h
+197
View File
@@ -0,0 +1,197 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2014-2015 Freescale Semiconductor Inc.
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM dpaa2_eth
#if !defined(_DPAA2_ETH_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
#define _DPAA2_ETH_TRACE_H
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/tracepoint.h>
#define TR_FMT "[%s] fd: addr=0x%llx, len=%u, off=%u"
/* trace_printk format for raw buffer event class */
#define TR_BUF_FMT "[%s] vaddr=%p size=%zu dma_addr=%pad map_size=%zu bpid=%d"
/* This is used to declare a class of events.
* individual events of this type will be defined below.
*/
/* Store details about a frame descriptor */
DECLARE_EVENT_CLASS(dpaa2_eth_fd,
/* Trace function prototype */
TP_PROTO(struct net_device *netdev,
const struct dpaa2_fd *fd),
/* Repeat argument list here */
TP_ARGS(netdev, fd),
/* A structure containing the relevant information we want
* to record. Declare name and type for each normal element,
* name, type and size for arrays. Use __string for variable
* length strings.
*/
TP_STRUCT__entry(
__field(u64, fd_addr)
__field(u32, fd_len)
__field(u16, fd_offset)
__string(name, netdev->name)
),
/* The function that assigns values to the above declared
* fields
*/
TP_fast_assign(
__entry->fd_addr = dpaa2_fd_get_addr(fd);
__entry->fd_len = dpaa2_fd_get_len(fd);
__entry->fd_offset = dpaa2_fd_get_offset(fd);
__assign_str(name);
),
/* This is what gets printed when the trace event is
* triggered.
*/
TP_printk(TR_FMT,
__get_str(name),
__entry->fd_addr,
__entry->fd_len,
__entry->fd_offset)
);
/* Now declare events of the above type. Format is:
* DEFINE_EVENT(class, name, proto, args), with proto and args same as for class
*/
/* Tx (egress) fd */
DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_fd,
TP_PROTO(struct net_device *netdev,
const struct dpaa2_fd *fd),
TP_ARGS(netdev, fd)
);
/* Tx (egress) XSK fd */
DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_xsk_fd,
TP_PROTO(struct net_device *netdev,
const struct dpaa2_fd *fd),
TP_ARGS(netdev, fd)
);
/* Rx fd */
DEFINE_EVENT(dpaa2_eth_fd, dpaa2_rx_fd,
TP_PROTO(struct net_device *netdev,
const struct dpaa2_fd *fd),
TP_ARGS(netdev, fd)
);
/* Rx XSK fd */
DEFINE_EVENT(dpaa2_eth_fd, dpaa2_rx_xsk_fd,
TP_PROTO(struct net_device *netdev,
const struct dpaa2_fd *fd),
TP_ARGS(netdev, fd)
);
/* Tx confirmation fd */
DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_conf_fd,
TP_PROTO(struct net_device *netdev,
const struct dpaa2_fd *fd),
TP_ARGS(netdev, fd)
);
/* Log data about raw buffers. Useful for tracing DPBP content. */
DECLARE_EVENT_CLASS(dpaa2_eth_buf,
/* Trace function prototype */
TP_PROTO(struct net_device *netdev,
/* virtual address and size */
void *vaddr,
size_t size,
/* dma map address and size */
dma_addr_t dma_addr,
size_t map_size,
/* buffer pool id, if relevant */
u16 bpid),
/* Repeat argument list here */
TP_ARGS(netdev, vaddr, size, dma_addr, map_size, bpid),
/* A structure containing the relevant information we want
* to record. Declare name and type for each normal element,
* name, type and size for arrays. Use __string for variable
* length strings.
*/
TP_STRUCT__entry(
__field(void *, vaddr)
__field(size_t, size)
__field(dma_addr_t, dma_addr)
__field(size_t, map_size)
__field(u16, bpid)
__string(name, netdev->name)
),
/* The function that assigns values to the above declared
* fields
*/
TP_fast_assign(
__entry->vaddr = vaddr;
__entry->size = size;
__entry->dma_addr = dma_addr;
__entry->map_size = map_size;
__entry->bpid = bpid;
__assign_str(name);
),
/* This is what gets printed when the trace event is
* triggered.
*/
TP_printk(TR_BUF_FMT,
__get_str(name),
__entry->vaddr,
__entry->size,
&__entry->dma_addr,
__entry->map_size,
__entry->bpid)
);
/* Main memory buff seeding */
DEFINE_EVENT(dpaa2_eth_buf, dpaa2_eth_buf_seed,
TP_PROTO(struct net_device *netdev,
void *vaddr,
size_t size,
dma_addr_t dma_addr,
size_t map_size,
u16 bpid),
TP_ARGS(netdev, vaddr, size, dma_addr, map_size, bpid)
);
/* UMEM buff seeding on AF_XDP fast path */
DEFINE_EVENT(dpaa2_eth_buf, dpaa2_xsk_buf_seed,
TP_PROTO(struct net_device *netdev,
void *vaddr,
size_t size,
dma_addr_t dma_addr,
size_t map_size,
u16 bpid),
TP_ARGS(netdev, vaddr, size, dma_addr, map_size, bpid)
);
/* If only one event of a certain type needs to be declared, use TRACE_EVENT().
* The syntax is the same as for DECLARE_EVENT_CLASS().
*/
#endif /* _DPAA2_ETH_TRACE_H */
/* This must be outside ifdef _DPAA2_ETH_TRACE_H */
#undef TRACE_INCLUDE_PATH
#define TRACE_INCLUDE_PATH .
#undef TRACE_INCLUDE_FILE
#define TRACE_INCLUDE_FILE dpaa2-eth-trace
#include <trace/define_trace.h>
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
+5168
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h
+861
View File
@@ -0,0 +1,861 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2016-2022 NXP
*/
#ifndef __DPAA2_ETH_H
#define __DPAA2_ETH_H
#include <linux/dcbnl.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#include <linux/fsl/mc.h>
#include <linux/net_tstamp.h>
#include <net/devlink.h>
#include <net/xdp.h>
#include <soc/fsl/dpaa2-io.h>
#include <soc/fsl/dpaa2-fd.h>
#include "dpni.h"
#include "dpni-cmd.h"
#include "dpaa2-eth-trace.h"
#include "dpaa2-eth-debugfs.h"
#include "dpaa2-mac.h"
#define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
#define DPAA2_ETH_STORE_SIZE 16
/* Maximum number of scatter-gather entries in an ingress frame,
* considering the maximum receive frame size is 64K
*/
#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
/* Maximum acceptable MTU value. It is in direct relation with the hardware
* enforced Max Frame Length (currently 10k).
*/
#define DPAA2_ETH_MFL (10 * 1024)
#define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
/* Convert L3 MTU to L2 MFL */
#define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
/* Set the taildrop threshold (in bytes) to allow the enqueue of a large
* enough number of jumbo frames in the Rx queues (length of the current
* frame is not taken into account when making the taildrop decision)
*/
#define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024)
/* Maximum burst size value for Tx shaping */
#define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
/* Maximum number of Tx confirmation frames to be processed
* in a single NAPI call
*/
#define DPAA2_ETH_TXCONF_PER_NAPI 256
/* Maximum number of Tx frames to be processed in a single NAPI
* call when AF_XDP is running. Bind it to DPAA2_ETH_TXCONF_PER_NAPI
* to maximize the throughput.
*/
#define DPAA2_ETH_TX_ZC_PER_NAPI DPAA2_ETH_TXCONF_PER_NAPI
/* Buffer qouta per channel. We want to keep in check number of ingress frames
* in flight: for small sized frames, congestion group taildrop may kick in
* first; for large sizes, Rx FQ taildrop threshold will ensure only a
* reasonable number of frames will be pending at any given time.
* Ingress frame drop due to buffer pool depletion should be a corner case only
*/
#define DPAA2_ETH_NUM_BUFS 1280
#define DPAA2_ETH_REFILL_THRESH \
(DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
/* Congestion group taildrop threshold: number of frames allowed to accumulate
* at any moment in a group of Rx queues belonging to the same traffic class.
* Choose value such that we don't risk depleting the buffer pool before the
* taildrop kicks in
*/
#define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \
(1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
/* Congestion group notification threshold: when this many frames accumulate
* on the Rx queues belonging to the same TC, the MAC is instructed to send
* PFC frames for that TC.
* When number of pending frames drops below exit threshold transmission of
* PFC frames is stopped.
*/
#define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
(DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
#define DPAA2_ETH_CN_THRESH_EXIT(priv) \
(DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
/* Maximum number of buffers that can be acquired/released through a single
* QBMan command
*/
#define DPAA2_ETH_BUFS_PER_CMD 7
/* Hardware requires alignment for ingress/egress buffer addresses */
#define DPAA2_ETH_TX_BUF_ALIGN 64
#define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
#define DPAA2_ETH_RX_BUF_TAILROOM \
SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
#define DPAA2_ETH_RX_BUF_SIZE \
(DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
/* Hardware annotation area in RX/TX buffers */
#define DPAA2_ETH_RX_HWA_SIZE 64
#define DPAA2_ETH_TX_HWA_SIZE 128
/* PTP nominal frequency 1GHz */
#define DPAA2_PTP_CLK_PERIOD_NS 1
/* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
* to 256B. For newer revisions, the requirement is only for 64B alignment
*/
#define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
#define DPAA2_ETH_RX_BUF_ALIGN 64
/* The firmware allows assigning multiple buffer pools to a single DPNI -
* maximum 8 DPBP objects. By default, only the first DPBP (idx 0) is used for
* all queues. Thus, when enabling AF_XDP we must accommodate up to 9 DPBPs
* object: the default and 8 other distinct buffer pools, one for each queue.
*/
#define DPAA2_ETH_DEFAULT_BP_IDX 0
#define DPAA2_ETH_MAX_BPS 9
/* We are accommodating a skb backpointer and some S/G info
* in the frame's software annotation. The hardware
* options are either 0 or 64, so we choose the latter.
*/
#define DPAA2_ETH_SWA_SIZE 64
/* We store different information in the software annotation area of a Tx frame
* based on what type of frame it is
*/
enum dpaa2_eth_swa_type {
DPAA2_ETH_SWA_SINGLE,
DPAA2_ETH_SWA_SG,
DPAA2_ETH_SWA_XDP,
DPAA2_ETH_SWA_XSK,
DPAA2_ETH_SWA_SW_TSO,
};
/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
struct dpaa2_eth_swa {
enum dpaa2_eth_swa_type type;
union {
struct {
struct sk_buff *skb;
int sgt_size;
} single;
struct {
struct sk_buff *skb;
struct scatterlist *scl;
int num_sg;
int sgt_size;
} sg;
struct {
int dma_size;
struct xdp_frame *xdpf;
} xdp;
struct {
struct xdp_buff *xdp_buff;
int sgt_size;
} xsk;
struct {
struct sk_buff *skb;
int num_sg;
int sgt_size;
int is_last_fd;
} tso;
};
};
/* Annotation valid bits in FD FRC */
#define DPAA2_FD_FRC_FASV 0x8000
#define DPAA2_FD_FRC_FAEADV 0x4000
#define DPAA2_FD_FRC_FAPRV 0x2000
#define DPAA2_FD_FRC_FAIADV 0x1000
#define DPAA2_FD_FRC_FASWOV 0x0800
#define DPAA2_FD_FRC_FAICFDV 0x0400
/* Error bits in FD CTRL */
#define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
#define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
FD_CTRL_SBE | \
FD_CTRL_FSE | \
FD_CTRL_FAERR)
/* Annotation bits in FD CTRL */
#define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
/* Frame annotation status */
struct dpaa2_fas {
u8 reserved;
u8 ppid;
__le16 ifpid;
__le32 status;
};
/* Frame annotation status word is located in the first 8 bytes
* of the buffer's hardware annoatation area
*/
#define DPAA2_FAS_OFFSET 0
#define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
/* Timestamp is located in the next 8 bytes of the buffer's
* hardware annotation area
*/
#define DPAA2_TS_OFFSET 0x8
/* Frame annotation parse results */
struct dpaa2_fapr {
/* 64-bit word 1 */
__le32 faf_lo;
__le16 faf_ext;
__le16 nxt_hdr;
/* 64-bit word 2 */
__le64 faf_hi;
/* 64-bit word 3 */
u8 last_ethertype_offset;
u8 vlan_tci_offset_n;
u8 vlan_tci_offset_1;
u8 llc_snap_offset;
u8 eth_offset;
u8 ip1_pid_offset;
u8 shim_offset_2;
u8 shim_offset_1;
/* 64-bit word 4 */
u8 l5_offset;
u8 l4_offset;
u8 gre_offset;
u8 l3_offset_n;
u8 l3_offset_1;
u8 mpls_offset_n;
u8 mpls_offset_1;
u8 pppoe_offset;
/* 64-bit word 5 */
__le16 running_sum;
__le16 gross_running_sum;
u8 ipv6_frag_offset;
u8 nxt_hdr_offset;
u8 routing_hdr_offset_2;
u8 routing_hdr_offset_1;
/* 64-bit word 6 */
u8 reserved[5]; /* Soft-parsing context */
u8 ip_proto_offset_n;
u8 nxt_hdr_frag_offset;
u8 parse_error_code;
};
#define DPAA2_FAPR_OFFSET 0x10
#define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr))
/* Frame annotation egress action descriptor */
#define DPAA2_FAEAD_OFFSET 0x58
struct dpaa2_faead {
__le32 conf_fqid;
__le32 ctrl;
};
#define DPAA2_FAEAD_A2V 0x20000000
#define DPAA2_FAEAD_A4V 0x08000000
#define DPAA2_FAEAD_UPDV 0x00001000
#define DPAA2_FAEAD_EBDDV 0x00002000
#define DPAA2_FAEAD_UPD 0x00000010
struct ptp_tstamp {
u16 sec_msb;
u32 sec_lsb;
u32 nsec;
};
static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
{
u64 sec, nsec;
sec = ns;
nsec = do_div(sec, 1000000000);
tstamp->sec_lsb = sec & 0xFFFFFFFF;
tstamp->sec_msb = (sec >> 32) & 0xFFFF;
tstamp->nsec = nsec;
}
/* Accessors for the hardware annotation fields that we use */
static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
{
return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
}
static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
{
return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
}
static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
{
return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
}
static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
{
return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
}
static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
{
return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
}
/* Error and status bits in the frame annotation status word */
/* Debug frame, otherwise supposed to be discarded */
#define DPAA2_FAS_DISC 0x80000000
/* MACSEC frame */
#define DPAA2_FAS_MS 0x40000000
#define DPAA2_FAS_PTP 0x08000000
/* Ethernet multicast frame */
#define DPAA2_FAS_MC 0x04000000
/* Ethernet broadcast frame */
#define DPAA2_FAS_BC 0x02000000
#define DPAA2_FAS_KSE 0x00040000
#define DPAA2_FAS_EOFHE 0x00020000
#define DPAA2_FAS_MNLE 0x00010000
#define DPAA2_FAS_TIDE 0x00008000
#define DPAA2_FAS_PIEE 0x00004000
/* Frame length error */
#define DPAA2_FAS_FLE 0x00002000
/* Frame physical error */
#define DPAA2_FAS_FPE 0x00001000
#define DPAA2_FAS_PTE 0x00000080
#define DPAA2_FAS_ISP 0x00000040
#define DPAA2_FAS_PHE 0x00000020
#define DPAA2_FAS_BLE 0x00000010
/* L3 csum validation performed */
#define DPAA2_FAS_L3CV 0x00000008
/* L3 csum error */
#define DPAA2_FAS_L3CE 0x00000004
/* L4 csum validation performed */
#define DPAA2_FAS_L4CV 0x00000002
/* L4 csum error */
#define DPAA2_FAS_L4CE 0x00000001
/* Possible errors on the ingress path */
#define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
DPAA2_FAS_EOFHE | \
DPAA2_FAS_MNLE | \
DPAA2_FAS_TIDE | \
DPAA2_FAS_PIEE | \
DPAA2_FAS_FLE | \
DPAA2_FAS_FPE | \
DPAA2_FAS_PTE | \
DPAA2_FAS_ISP | \
DPAA2_FAS_PHE | \
DPAA2_FAS_BLE | \
DPAA2_FAS_L3CE | \
DPAA2_FAS_L4CE)
/* Time in milliseconds between link state updates */
#define DPAA2_ETH_LINK_STATE_REFRESH 1000
/* Number of times to retry a frame enqueue before giving up.
* Value determined empirically, in order to minimize the number
* of frames dropped on Tx
*/
#define DPAA2_ETH_ENQUEUE_RETRIES 10
/* Number of times to retry DPIO portal operations while waiting
* for portal to finish executing current command and become
* available. We want to avoid being stuck in a while loop in case
* hardware becomes unresponsive, but not give up too easily if
* the portal really is busy for valid reasons
*/
#define DPAA2_ETH_SWP_BUSY_RETRIES 1000
/* Driver statistics, other than those in struct rtnl_link_stats64.
* These are usually collected per-CPU and aggregated by ethtool.
*/
struct dpaa2_eth_drv_stats {
__u64 tx_conf_frames;
__u64 tx_conf_bytes;
__u64 tx_sg_frames;
__u64 tx_sg_bytes;
__u64 tx_tso_frames;
__u64 tx_tso_bytes;
__u64 rx_sg_frames;
__u64 rx_sg_bytes;
/* Linear skbs sent as a S/G FD due to insufficient headroom */
__u64 tx_converted_sg_frames;
__u64 tx_converted_sg_bytes;
/* Enqueues retried due to portal busy */
__u64 tx_portal_busy;
};
/* Per-FQ statistics */
struct dpaa2_eth_fq_stats {
/* Number of frames received on this queue */
__u64 frames;
};
/* Per-channel statistics */
struct dpaa2_eth_ch_stats {
/* Volatile dequeues retried due to portal busy */
__u64 dequeue_portal_busy;
/* Pull errors */
__u64 pull_err;
/* Number of CDANs; useful to estimate avg NAPI len */
__u64 cdan;
/* XDP counters */
__u64 xdp_drop;
__u64 xdp_tx;
__u64 xdp_tx_err;
__u64 xdp_redirect;
/* Must be last, does not show up in ethtool stats */
__u64 frames;
__u64 frames_per_cdan;
__u64 bytes_per_cdan;
};
#define DPAA2_ETH_CH_STATS 7
/* Maximum number of queues associated with a DPNI */
#define DPAA2_ETH_MAX_TCS 8
#define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16
#define DPAA2_ETH_MAX_RX_QUEUES \
(DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
#define DPAA2_ETH_MAX_TX_QUEUES 16
#define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
DPAA2_ETH_MAX_TX_QUEUES + \
DPAA2_ETH_MAX_RX_ERR_QUEUES)
#define DPAA2_ETH_MAX_NETDEV_QUEUES \
(DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
#define DPAA2_ETH_MAX_DPCONS 16
enum dpaa2_eth_fq_type {
DPAA2_RX_FQ = 0,
DPAA2_TX_CONF_FQ,
DPAA2_RX_ERR_FQ
};
struct dpaa2_eth_priv;
struct dpaa2_eth_channel;
struct dpaa2_eth_fq;
struct dpaa2_eth_xdp_fds {
struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
ssize_t num;
};
typedef void dpaa2_eth_consume_cb_t(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
struct dpaa2_eth_fq *fq);
struct dpaa2_eth_fq {
u32 fqid;
u32 tx_qdbin;
u32 tx_fqid[DPAA2_ETH_MAX_TCS];
u16 flowid;
u8 tc;
int target_cpu;
u32 dq_frames;
u32 dq_bytes;
struct dpaa2_eth_channel *channel;
enum dpaa2_eth_fq_type type;
dpaa2_eth_consume_cb_t *consume;
struct dpaa2_eth_fq_stats stats;
struct dpaa2_eth_xdp_fds xdp_redirect_fds;
struct dpaa2_eth_xdp_fds xdp_tx_fds;
};
struct dpaa2_eth_ch_xdp {
struct bpf_prog *prog;
unsigned int res;
};
struct dpaa2_eth_bp {
struct fsl_mc_device *dev;
int bpid;
};
struct dpaa2_eth_channel {
struct dpaa2_io_notification_ctx nctx;
struct fsl_mc_device *dpcon;
int dpcon_id;
int ch_id;
struct napi_struct napi;
struct dpaa2_io *dpio;
struct dpaa2_io_store *store;
struct dpaa2_eth_priv *priv;
int buf_count;
struct dpaa2_eth_ch_stats stats;
struct dpaa2_eth_ch_xdp xdp;
struct xdp_rxq_info xdp_rxq;
struct list_head *rx_list;
/* Buffers to be recycled back in the buffer pool */
u64 recycled_bufs[DPAA2_ETH_BUFS_PER_CMD];
int recycled_bufs_cnt;
bool xsk_zc;
int xsk_tx_pkts_sent;
struct xsk_buff_pool *xsk_pool;
struct dpaa2_eth_bp *bp;
};
struct dpaa2_eth_dist_fields {
u64 rxnfc_field;
enum net_prot cls_prot;
int cls_field;
int size;
u64 id;
};
struct dpaa2_eth_cls_rule {
struct ethtool_rx_flow_spec fs;
u8 in_use;
};
#define DPAA2_ETH_SGT_CACHE_SIZE 256
struct dpaa2_eth_sgt_cache {
void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
u16 count;
};
struct dpaa2_eth_trap_item {
void *trap_ctx;
};
struct dpaa2_eth_trap_data {
struct dpaa2_eth_trap_item *trap_items_arr;
struct dpaa2_eth_priv *priv;
};
#define DPAA2_ETH_SG_ENTRIES_MAX (PAGE_SIZE / sizeof(struct scatterlist))
#define DPAA2_ETH_DEFAULT_COPYBREAK 512
#define DPAA2_ETH_ENQUEUE_MAX_FDS 256
struct dpaa2_eth_fds {
struct dpaa2_fd array[DPAA2_ETH_ENQUEUE_MAX_FDS];
};
/* Driver private data */
struct dpaa2_eth_priv {
struct net_device *net_dev;
u8 num_fqs;
struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
int (*enqueue)(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_fq *fq,
struct dpaa2_fd *fd, u8 prio,
u32 num_frames,
int *frames_enqueued);
u8 num_channels;
struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
unsigned long features;
struct dpni_attr dpni_attrs;
u16 dpni_ver_major;
u16 dpni_ver_minor;
u16 tx_data_offset;
void __iomem *onestep_reg_base;
u8 ptp_correction_off;
void (*dpaa2_set_onestep_params_cb)(struct dpaa2_eth_priv *priv,
u32 offset, u8 udp);
u16 rx_buf_size;
struct iommu_domain *iommu_domain;
enum hwtstamp_tx_types tx_tstamp_type; /* Tx timestamping type */
bool rx_tstamp; /* Rx timestamping enabled */
/* Buffer pool management */
struct dpaa2_eth_bp *bp[DPAA2_ETH_MAX_BPS];
int num_bps;
u16 tx_qdid;
struct fsl_mc_io *mc_io;
/* Cores which have an affine DPIO/DPCON.
* This is the cpu set on which Rx and Tx conf frames are processed
*/
struct cpumask dpio_cpumask;
/* Standard statistics */
struct rtnl_link_stats64 __percpu *percpu_stats;
/* Extra stats, in addition to the ones known by the kernel */
struct dpaa2_eth_drv_stats __percpu *percpu_extras;
u16 mc_token;
u8 rx_fqtd_enabled;
u8 rx_cgtd_enabled;
struct dpni_link_state link_state;
bool do_link_poll;
struct task_struct *poll_thread;
/* enabled ethtool hashing bits */
u64 rx_hash_fields;
u64 rx_cls_fields;
struct dpaa2_eth_cls_rule *cls_rules;
u8 rx_cls_enabled;
u8 vlan_cls_enabled;
u8 pfc_enabled;
#ifdef CONFIG_FSL_DPAA2_ETH_DCB
u8 dcbx_mode;
struct ieee_pfc pfc;
#endif
struct bpf_prog *xdp_prog;
#ifdef CONFIG_DEBUG_FS
struct dpaa2_debugfs dbg;
#endif
struct dpaa2_mac *mac;
/* Serializes changes to priv->mac */
struct mutex mac_lock;
struct workqueue_struct *dpaa2_ptp_wq;
struct work_struct tx_onestep_tstamp;
struct sk_buff_head tx_skbs;
/* The one-step timestamping configuration on hardware
* registers could only be done when no one-step
* timestamping frames are in flight. So we use a mutex
* lock here to make sure the lock is released by last
* one-step timestamping packet through TX confirmation
* queue before transmit current packet.
*/
struct mutex onestep_tstamp_lock;
struct devlink *devlink;
struct dpaa2_eth_trap_data *trap_data;
struct devlink_port devlink_port;
u32 rx_copybreak;
struct dpaa2_eth_fds __percpu *fd;
};
struct dpaa2_eth_devlink_priv {
struct dpaa2_eth_priv *dpaa2_priv;
};
#define TX_TSTAMP 0x1
#define TX_TSTAMP_ONESTEP_SYNC 0x2
#define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
| RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
| RXH_L4_B_2_3)
/* default Rx hash options, set during probing */
#define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
RXH_L4_B_0_1 | RXH_L4_B_2_3)
#define dpaa2_eth_hash_enabled(priv) \
((priv)->dpni_attrs.num_queues > 1)
/* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
#define DPAA2_CLASSIFIER_DMA_SIZE 256
extern const struct ethtool_ops dpaa2_ethtool_ops;
extern int dpaa2_phc_index;
extern struct ptp_qoriq *dpaa2_ptp;
static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
u16 ver_major, u16 ver_minor)
{
if (priv->dpni_ver_major == ver_major)
return priv->dpni_ver_minor - ver_minor;
return priv->dpni_ver_major - ver_major;
}
/* Minimum firmware version that supports a more flexible API
* for configuring the Rx flow hash key
*/
#define DPNI_RX_DIST_KEY_VER_MAJOR 7
#define DPNI_RX_DIST_KEY_VER_MINOR 5
#define dpaa2_eth_has_legacy_dist(priv) \
(dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
DPNI_RX_DIST_KEY_VER_MINOR) < 0)
#define dpaa2_eth_fs_enabled(priv) \
(!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
#define dpaa2_eth_fs_mask_enabled(priv) \
((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
#define dpaa2_eth_fs_count(priv) \
((priv)->dpni_attrs.fs_entries)
#define dpaa2_eth_tc_count(priv) \
((priv)->dpni_attrs.num_tcs)
/* We have exactly one {Rx, Tx conf} queue per channel */
#define dpaa2_eth_queue_count(priv) \
((priv)->num_channels)
enum dpaa2_eth_rx_dist {
DPAA2_ETH_RX_DIST_HASH,
DPAA2_ETH_RX_DIST_CLS
};
/* Unique IDs for the supported Rx classification header fields */
#define DPAA2_ETH_DIST_ETHDST BIT(0)
#define DPAA2_ETH_DIST_ETHSRC BIT(1)
#define DPAA2_ETH_DIST_ETHTYPE BIT(2)
#define DPAA2_ETH_DIST_VLAN BIT(3)
#define DPAA2_ETH_DIST_IPSRC BIT(4)
#define DPAA2_ETH_DIST_IPDST BIT(5)
#define DPAA2_ETH_DIST_IPPROTO BIT(6)
#define DPAA2_ETH_DIST_L4SRC BIT(7)
#define DPAA2_ETH_DIST_L4DST BIT(8)
#define DPAA2_ETH_DIST_ALL (~0ULL)
#define DPNI_PTP_ONESTEP_VER_MAJOR 8
#define DPNI_PTP_ONESTEP_VER_MINOR 2
#define DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT BIT(0)
#define DPAA2_PTP_SINGLE_STEP_ENABLE BIT(31)
#define DPAA2_PTP_SINGLE_STEP_CH BIT(7)
#define DPAA2_PTP_SINGLE_CORRECTION_OFF(v) ((v) << 8)
#define DPNI_PAUSE_VER_MAJOR 7
#define DPNI_PAUSE_VER_MINOR 13
#define dpaa2_eth_has_pause_support(priv) \
(dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
DPNI_PAUSE_VER_MINOR) >= 0)
static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
{
return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
!!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
}
static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
{
return !!(link_options & DPNI_LINK_OPT_PAUSE);
}
static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
{
unsigned int headroom = DPAA2_ETH_SWA_SIZE + DPAA2_ETH_TX_BUF_ALIGN;
/* If we don't have an skb (e.g. XDP buffer), we only need space for
* the software annotation area
*/
if (!skb)
return headroom;
/* For non-linear skbs we have no headroom requirement, as we build a
* SG frame with a newly allocated SGT buffer
*/
if (skb_is_nonlinear(skb))
return 0;
/* If we have Tx timestamping, need 128B hardware annotation */
if (skb->cb[0])
headroom += DPAA2_ETH_TX_HWA_SIZE;
return headroom;
}
/* Extra headroom space requested to hardware, in order to make sure there's
* no realloc'ing in forwarding scenarios
*/
static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
{
return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
}
static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv)
{
lockdep_assert_held(&priv->mac_lock);
return dpaa2_mac_is_type_phy(priv->mac);
}
static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv)
{
lockdep_assert_held(&priv->mac_lock);
return priv->mac ? true : false;
}
int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
int dpaa2_eth_cls_key_size(u64 key);
int dpaa2_eth_cls_fld_off(int prot, int field);
void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
bool tx_pause, bool pfc);
extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
int dpaa2_eth_dl_alloc(struct dpaa2_eth_priv *priv);
void dpaa2_eth_dl_free(struct dpaa2_eth_priv *priv);
void dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
struct dpaa2_fapr *fapr);
struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv);
void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv, struct dpaa2_eth_bp *bp);
struct sk_buff *dpaa2_eth_alloc_skb(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd, u32 fd_length,
void *fd_vaddr);
void dpaa2_eth_receive_skb(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd, void *vaddr,
struct dpaa2_eth_fq *fq,
struct rtnl_link_stats64 *percpu_stats,
struct sk_buff *skb);
void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
struct dpaa2_eth_fq *fq);
struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv);
void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_bp *bp);
void *dpaa2_iova_to_virt(struct iommu_domain *domain, dma_addr_t iova_addr);
void dpaa2_eth_recycle_buf(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
dma_addr_t addr);
void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_fd *fd,
void *buf_start, u16 queue_id);
int dpaa2_xsk_wakeup(struct net_device *dev, u32 qid, u32 flags);
int dpaa2_xsk_setup_pool(struct net_device *dev, struct xsk_buff_pool *pool, u16 qid);
void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_eth_fq *fq,
const struct dpaa2_fd *fd, bool in_napi);
bool dpaa2_xsk_tx(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch);
/* SGT (Scatter-Gather Table) cache management */
void *dpaa2_eth_sgt_get(struct dpaa2_eth_priv *priv);
void dpaa2_eth_sgt_recycle(struct dpaa2_eth_priv *priv, void *sgt_buf);
#endif /* __DPAA2_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
+1024
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+939
View File
@@ -0,0 +1,939 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2019, 2024-2026 NXP */
#include <linux/acpi.h>
#include <linux/pcs-lynx.h>
#include <linux/phy/phy.h>
#include <linux/property.h>
#include "dpaa2-eth.h"
#include "dpaa2-mac.h"
#define phylink_to_dpaa2_mac(config) \
container_of((config), struct dpaa2_mac, phylink_config)
#define DPMAC_PROTOCOL_CHANGE_VER_MAJOR 4
#define DPMAC_PROTOCOL_CHANGE_VER_MINOR 8
#define DPMAC_STATS_BUNDLE_VER_MAJOR 4
#define DPMAC_STATS_BUNDLE_VER_MINOR 10
#define DPMAC_STANDARD_STATS_VER_MAJOR 4
#define DPMAC_STANDARD_STATS_VER_MINOR 11
#define DPAA2_MAC_FEATURE_PROTOCOL_CHANGE BIT(0)
#define DPAA2_MAC_FEATURE_STATS_BUNDLE BIT(1)
#define DPAA2_MAC_FEATURE_STANDARD_STATS BIT(2)
struct dpmac_counter {
enum dpmac_counter_id id;
size_t offset;
const char *name;
};
#define DPMAC_COUNTER(counter_id, struct_name, struct_offset) \
{ \
.id = counter_id, \
.offset = offsetof(struct_name, struct_offset), \
}
#define DPMAC_UNSTRUCTURED_COUNTER(counter_id, counter_name) \
{ \
.id = counter_id, \
.name = counter_name, \
}
#define DPMAC_RMON_COUNTER(counter_id, struct_offset) \
DPMAC_COUNTER(counter_id, struct ethtool_rmon_stats, struct_offset)
#define DPMAC_PAUSE_COUNTER(counter_id, struct_offset) \
DPMAC_COUNTER(counter_id, struct ethtool_pause_stats, struct_offset)
#define DPMAC_CTRL_COUNTER(counter_id, struct_offset) \
DPMAC_COUNTER(counter_id, struct ethtool_eth_ctrl_stats, struct_offset)
#define DPMAC_MAC_COUNTER(counter_id, struct_offset) \
DPMAC_COUNTER(counter_id, struct ethtool_eth_mac_stats, struct_offset)
static const struct dpmac_counter dpaa2_mac_ethtool_stats[] = {
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_ALL_FRAME, "[mac] rx all frames"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_GOOD_FRAME, "[mac] rx frames ok"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_ERR_FRAME, "[mac] rx frame errors"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_DISCARD, "[mac] rx frame discards"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_UCAST_FRAME, "[mac] rx u-cast"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_BCAST_FRAME, "[mac] rx b-cast"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_MCAST_FRAME, "[mac] rx m-cast"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_64, "[mac] rx 64 bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_127, "[mac] rx 65-127 bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_255, "[mac] rx 128-255 bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_511, "[mac] rx 256-511 bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_1023, "[mac] rx 512-1023 bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_1518, "[mac] rx 1024-1518 bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAME_1519_MAX, "[mac] rx 1519-max bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_FRAG, "[mac] rx frags"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_JABBER, "[mac] rx jabber"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_ALIGN_ERR, "[mac] rx align errors"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_OVERSIZED, "[mac] rx oversized"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_VALID_PAUSE_FRAME, "[mac] rx pause"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_ING_BYTE, "[mac] rx bytes"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_GOOD_FRAME, "[mac] tx frames ok"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_UCAST_FRAME, "[mac] tx u-cast"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_MCAST_FRAME, "[mac] tx m-cast"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_BCAST_FRAME, "[mac] tx b-cast"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_ERR_FRAME, "[mac] tx frame errors"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_UNDERSIZED, "[mac] tx undersized"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_VALID_PAUSE_FRAME, "[mac] tx b-pause"),
DPMAC_UNSTRUCTURED_COUNTER(DPMAC_CNT_EGR_BYTE, "[mac] tx bytes"),
};
#define DPAA2_MAC_NUM_ETHTOOL_STATS ARRAY_SIZE(dpaa2_mac_ethtool_stats)
static const struct dpmac_counter dpaa2_mac_rmon_stats[] = {
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_64, hist[0]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_127, hist[1]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_255, hist[2]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_511, hist[3]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_1023, hist[4]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_1518, hist[5]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAME_1519_MAX, hist[6]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_64, hist_tx[0]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_127, hist_tx[1]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_255, hist_tx[2]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_511, hist_tx[3]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_1023, hist_tx[4]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_1518, hist_tx[5]),
DPMAC_RMON_COUNTER(DPMAC_CNT_EGR_FRAME_1519_MAX, hist_tx[6]),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_UNDERSIZED, undersize_pkts),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_OVERSIZED, oversize_pkts),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_FRAG, fragments),
DPMAC_RMON_COUNTER(DPMAC_CNT_ING_JABBER, jabbers),
};
#define DPAA2_MAC_NUM_RMON_STATS ARRAY_SIZE(dpaa2_mac_rmon_stats)
static const struct dpmac_counter dpaa2_mac_pause_stats[] = {
DPMAC_PAUSE_COUNTER(DPMAC_CNT_ING_VALID_PAUSE_FRAME, rx_pause_frames),
DPMAC_PAUSE_COUNTER(DPMAC_CNT_EGR_VALID_PAUSE_FRAME, tx_pause_frames),
};
#define DPAA2_MAC_NUM_PAUSE_STATS ARRAY_SIZE(dpaa2_mac_pause_stats)
static const struct dpmac_counter dpaa2_mac_eth_ctrl_stats[] = {
DPMAC_CTRL_COUNTER(DPMAC_CNT_ING_CONTROL_FRAME, MACControlFramesReceived),
DPMAC_CTRL_COUNTER(DPMAC_CNT_EGR_CONTROL_FRAME, MACControlFramesTransmitted),
};
#define DPAA2_MAC_NUM_ETH_CTRL_STATS ARRAY_SIZE(dpaa2_mac_eth_ctrl_stats)
static const struct dpmac_counter dpaa2_mac_eth_mac_stats[] = {
DPMAC_MAC_COUNTER(DPMAC_CNT_EGR_GOOD_FRAME, FramesTransmittedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_GOOD_FRAME, FramesReceivedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_FCS_ERR, FrameCheckSequenceErrors),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_ALIGN_ERR, AlignmentErrors),
DPMAC_MAC_COUNTER(DPMAC_CNT_EGR_ALL_BYTE, OctetsTransmittedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_EGR_ERR_FRAME, FramesLostDueToIntMACXmitError),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_ALL_BYTE, OctetsReceivedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_FRAME_DISCARD_NOT_TRUNC, FramesLostDueToIntMACRcvError),
DPMAC_MAC_COUNTER(DPMAC_CNT_EGR_MCAST_FRAME, MulticastFramesXmittedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_EGR_BCAST_FRAME, BroadcastFramesXmittedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_MCAST_FRAME, MulticastFramesReceivedOK),
DPMAC_MAC_COUNTER(DPMAC_CNT_ING_BCAST_FRAME, BroadcastFramesReceivedOK),
};
#define DPAA2_MAC_NUM_ETH_MAC_STATS ARRAY_SIZE(dpaa2_mac_eth_mac_stats)
static void dpaa2_mac_setup_stats(struct dpaa2_mac *mac,
struct dpaa2_mac_stats *stats,
size_t num_stats,
const struct dpmac_counter *counters)
{
struct device *dev = mac->net_dev->dev.parent;
size_t size_idx, size_values;
__le32 *cnt_idx;
size_idx = num_stats * sizeof(u32);
stats->idx_dma_mem = dma_alloc_noncoherent(dev, size_idx,
&stats->idx_iova,
DMA_TO_DEVICE,
GFP_KERNEL);
if (!stats->idx_dma_mem)
goto out;
size_values = num_stats * sizeof(u64);
stats->values_dma_mem = dma_alloc_noncoherent(dev, size_values,
&stats->values_iova,
DMA_FROM_DEVICE,
GFP_KERNEL);
if (!stats->values_dma_mem)
goto err_alloc_values;
cnt_idx = stats->idx_dma_mem;
for (size_t i = 0; i < num_stats; i++)
*cnt_idx++ = cpu_to_le32((u32)(counters[i].id));
dma_sync_single_for_device(dev, stats->idx_iova, size_idx,
DMA_TO_DEVICE);
return;
err_alloc_values:
dma_free_noncoherent(dev, num_stats * sizeof(u32), stats->idx_dma_mem,
stats->idx_iova, DMA_TO_DEVICE);
out:
stats->idx_dma_mem = NULL;
stats->values_dma_mem = NULL;
}
static void dpaa2_mac_clear_stats(struct dpaa2_mac *mac,
struct dpaa2_mac_stats *stats,
size_t num_stats)
{
struct device *dev = mac->net_dev->dev.parent;
if (stats->idx_dma_mem) {
dma_free_noncoherent(dev, num_stats * sizeof(u32),
stats->idx_dma_mem,
stats->idx_iova, DMA_TO_DEVICE);
stats->idx_dma_mem = NULL;
}
if (stats->values_dma_mem) {
dma_free_noncoherent(dev, num_stats * sizeof(u64),
stats->values_dma_mem,
stats->values_iova, DMA_FROM_DEVICE);
stats->values_dma_mem = NULL;
}
}
static int dpaa2_mac_cmp_ver(struct dpaa2_mac *mac,
u16 ver_major, u16 ver_minor)
{
if (mac->ver_major == ver_major)
return mac->ver_minor - ver_minor;
return mac->ver_major - ver_major;
}
static void dpaa2_mac_detect_features(struct dpaa2_mac *mac)
{
mac->features = 0;
if (dpaa2_mac_cmp_ver(mac, DPMAC_PROTOCOL_CHANGE_VER_MAJOR,
DPMAC_PROTOCOL_CHANGE_VER_MINOR) >= 0)
mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE;
if (dpaa2_mac_cmp_ver(mac, DPMAC_STATS_BUNDLE_VER_MAJOR,
DPMAC_STATS_BUNDLE_VER_MINOR) >= 0)
mac->features |= DPAA2_MAC_FEATURE_STATS_BUNDLE;
if (dpaa2_mac_cmp_ver(mac, DPMAC_STANDARD_STATS_VER_MAJOR,
DPMAC_STANDARD_STATS_VER_MINOR) >= 0)
mac->features |= DPAA2_MAC_FEATURE_STANDARD_STATS;
}
static int phy_mode(enum dpmac_eth_if eth_if, phy_interface_t *if_mode)
{
*if_mode = PHY_INTERFACE_MODE_NA;
switch (eth_if) {
case DPMAC_ETH_IF_RGMII:
*if_mode = PHY_INTERFACE_MODE_RGMII;
break;
case DPMAC_ETH_IF_USXGMII:
*if_mode = PHY_INTERFACE_MODE_USXGMII;
break;
case DPMAC_ETH_IF_QSGMII:
*if_mode = PHY_INTERFACE_MODE_QSGMII;
break;
case DPMAC_ETH_IF_SGMII:
*if_mode = PHY_INTERFACE_MODE_SGMII;
break;
case DPMAC_ETH_IF_XFI:
*if_mode = PHY_INTERFACE_MODE_10GBASER;
break;
case DPMAC_ETH_IF_CAUI:
*if_mode = PHY_INTERFACE_MODE_25GBASER;
break;
default:
return -EINVAL;
}
return 0;
}
static enum dpmac_eth_if dpmac_eth_if_mode(phy_interface_t if_mode)
{
switch (if_mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
return DPMAC_ETH_IF_RGMII;
case PHY_INTERFACE_MODE_USXGMII:
return DPMAC_ETH_IF_USXGMII;
case PHY_INTERFACE_MODE_QSGMII:
return DPMAC_ETH_IF_QSGMII;
case PHY_INTERFACE_MODE_SGMII:
return DPMAC_ETH_IF_SGMII;
case PHY_INTERFACE_MODE_10GBASER:
return DPMAC_ETH_IF_XFI;
case PHY_INTERFACE_MODE_1000BASEX:
return DPMAC_ETH_IF_1000BASEX;
case PHY_INTERFACE_MODE_25GBASER:
return DPMAC_ETH_IF_CAUI;
default:
return DPMAC_ETH_IF_MII;
}
}
static struct fwnode_handle *dpaa2_mac_get_node(struct device *dev,
u16 dpmac_id)
{
struct fwnode_handle *fwnode, *parent = NULL, *child = NULL;
struct device_node *dpmacs = NULL;
int err;
u32 id;
fwnode = dev_fwnode(dev->parent);
if (is_of_node(fwnode)) {
dpmacs = of_find_node_by_name(NULL, "dpmacs");
if (!dpmacs)
return NULL;
parent = of_fwnode_handle(dpmacs);
} else if (is_acpi_node(fwnode)) {
parent = fwnode;
} else {
/* The root dprc device didn't yet get to finalize it's probe,
* thus the fwnode field is not yet set. Defer probe if we are
* facing this situation.
*/
dev_dbg(dev, "dprc not finished probing\n");
return ERR_PTR(-EPROBE_DEFER);
}
fwnode_for_each_child_node(parent, child) {
err = -EINVAL;
if (is_acpi_device_node(child))
err = acpi_get_local_address(ACPI_HANDLE_FWNODE(child), &id);
else if (is_of_node(child))
err = of_property_read_u32(to_of_node(child), "reg", &id);
if (err)
continue;
if (id == dpmac_id) {
of_node_put(dpmacs);
return child;
}
}
of_node_put(dpmacs);
return NULL;
}
static int dpaa2_mac_get_if_mode(struct fwnode_handle *dpmac_node,
struct dpmac_attr attr)
{
phy_interface_t if_mode;
int err;
err = fwnode_get_phy_mode(dpmac_node);
if (err > 0)
return err;
err = phy_mode(attr.eth_if, &if_mode);
if (!err)
return if_mode;
return err;
}
static struct phylink_pcs *dpaa2_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
return mac->pcs;
}
static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
const struct phylink_link_state *state)
{
struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
struct dpmac_link_state *dpmac_state = &mac->state;
int err;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
state->advertising))
dpmac_state->options |= DPMAC_LINK_OPT_AUTONEG;
else
dpmac_state->options &= ~DPMAC_LINK_OPT_AUTONEG;
err = dpmac_set_link_state(mac->mc_io, 0,
mac->mc_dev->mc_handle, dpmac_state);
if (err)
netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n",
__func__, err);
if (!mac->serdes_phy)
return;
/* This happens only if we support changing of protocol at runtime */
err = dpmac_set_protocol(mac->mc_io, 0, mac->mc_dev->mc_handle,
dpmac_eth_if_mode(state->interface));
if (err)
netdev_err(mac->net_dev, "dpmac_set_protocol() = %d\n", err);
err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface);
if (err)
netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err);
}
static void dpaa2_mac_link_up(struct phylink_config *config,
struct phy_device *phy,
unsigned int mode, phy_interface_t interface,
int speed, int duplex,
bool tx_pause, bool rx_pause)
{
struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
struct dpmac_link_state *dpmac_state = &mac->state;
int err;
dpmac_state->up = 1;
dpmac_state->rate = speed;
if (duplex == DUPLEX_HALF)
dpmac_state->options |= DPMAC_LINK_OPT_HALF_DUPLEX;
else if (duplex == DUPLEX_FULL)
dpmac_state->options &= ~DPMAC_LINK_OPT_HALF_DUPLEX;
if (rx_pause)
dpmac_state->options |= DPMAC_LINK_OPT_PAUSE;
else
dpmac_state->options &= ~DPMAC_LINK_OPT_PAUSE;
if (rx_pause ^ tx_pause)
dpmac_state->options |= DPMAC_LINK_OPT_ASYM_PAUSE;
else
dpmac_state->options &= ~DPMAC_LINK_OPT_ASYM_PAUSE;
err = dpmac_set_link_state(mac->mc_io, 0,
mac->mc_dev->mc_handle, dpmac_state);
if (err)
netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n",
__func__, err);
}
static void dpaa2_mac_link_down(struct phylink_config *config,
unsigned int mode,
phy_interface_t interface)
{
struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
struct dpmac_link_state *dpmac_state = &mac->state;
int err;
dpmac_state->up = 0;
err = dpmac_set_link_state(mac->mc_io, 0,
mac->mc_dev->mc_handle, dpmac_state);
if (err)
netdev_err(mac->net_dev, "dpmac_set_link_state() = %d\n", err);
}
static const struct phylink_mac_ops dpaa2_mac_phylink_ops = {
.mac_select_pcs = dpaa2_mac_select_pcs,
.mac_config = dpaa2_mac_config,
.mac_link_up = dpaa2_mac_link_up,
.mac_link_down = dpaa2_mac_link_down,
};
static int dpaa2_pcs_create(struct dpaa2_mac *mac,
struct fwnode_handle *dpmac_node,
int id)
{
struct fwnode_handle *node;
struct phylink_pcs *pcs;
node = fwnode_find_reference(dpmac_node, "pcs-handle", 0);
if (IS_ERR(node)) {
/* do not error out on old DTS files */
netdev_warn(mac->net_dev, "pcs-handle node not found\n");
return 0;
}
pcs = lynx_pcs_create_fwnode(node);
fwnode_handle_put(node);
if (pcs == ERR_PTR(-EPROBE_DEFER)) {
netdev_dbg(mac->net_dev, "missing PCS device\n");
return -EPROBE_DEFER;
}
if (pcs == ERR_PTR(-ENODEV)) {
netdev_err(mac->net_dev, "pcs-handle node not available\n");
return PTR_ERR(pcs);
}
if (IS_ERR(pcs)) {
netdev_err(mac->net_dev,
"lynx_pcs_create_fwnode() failed: %pe\n", pcs);
return PTR_ERR(pcs);
}
mac->pcs = pcs;
return 0;
}
static void dpaa2_pcs_destroy(struct dpaa2_mac *mac)
{
struct phylink_pcs *phylink_pcs = mac->pcs;
if (phylink_pcs) {
lynx_pcs_destroy(phylink_pcs);
mac->pcs = NULL;
}
}
static void dpaa2_mac_set_supported_interfaces(struct dpaa2_mac *mac)
{
int intf, err;
/* We support the current interface mode, and if we have a PCS
* similar interface modes that do not require the SerDes lane to be
* reconfigured.
*/
__set_bit(mac->if_mode, mac->phylink_config.supported_interfaces);
if (mac->pcs) {
switch (mac->if_mode) {
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_SGMII:
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_SGMII,
mac->phylink_config.supported_interfaces);
break;
default:
break;
}
}
if (!mac->serdes_phy)
return;
/* In case we have access to the SerDes phy/lane, then ask the SerDes
* driver what interfaces are supported based on the current PLL
* configuration.
*/
for (intf = 0; intf < PHY_INTERFACE_MODE_MAX; intf++) {
if (intf == PHY_INTERFACE_MODE_NA)
continue;
err = phy_validate(mac->serdes_phy, PHY_MODE_ETHERNET, intf, NULL);
if (err)
continue;
__set_bit(intf, mac->phylink_config.supported_interfaces);
}
}
void dpaa2_mac_start(struct dpaa2_mac *mac)
{
ASSERT_RTNL();
if (mac->serdes_phy)
phy_power_on(mac->serdes_phy);
phylink_start(mac->phylink);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_start);
void dpaa2_mac_stop(struct dpaa2_mac *mac)
{
ASSERT_RTNL();
phylink_stop(mac->phylink);
if (mac->serdes_phy)
phy_power_off(mac->serdes_phy);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_stop);
int dpaa2_mac_connect(struct dpaa2_mac *mac)
{
struct net_device *net_dev = mac->net_dev;
struct fwnode_handle *dpmac_node;
struct phy *serdes_phy = NULL;
struct phylink *phylink;
int err;
mac->if_link_type = mac->attr.link_type;
dpmac_node = mac->fw_node;
if (!dpmac_node) {
netdev_err(net_dev, "No dpmac@%d node found.\n", mac->attr.id);
return -ENODEV;
}
err = dpaa2_mac_get_if_mode(dpmac_node, mac->attr);
if (err < 0)
return -EINVAL;
mac->if_mode = err;
if (mac->features & DPAA2_MAC_FEATURE_PROTOCOL_CHANGE &&
!phy_interface_mode_is_rgmii(mac->if_mode) &&
is_of_node(dpmac_node)) {
serdes_phy = of_phy_get(to_of_node(dpmac_node), NULL);
if (serdes_phy == ERR_PTR(-ENODEV))
serdes_phy = NULL;
else if (IS_ERR(serdes_phy))
return PTR_ERR(serdes_phy);
else
phy_init(serdes_phy);
}
mac->serdes_phy = serdes_phy;
/* The MAC does not have the capability to add RGMII delays so
* error out if the interface mode requests them and there is no PHY
* to act upon them
*/
if (of_phy_is_fixed_link(to_of_node(dpmac_node)) &&
(mac->if_mode == PHY_INTERFACE_MODE_RGMII_ID ||
mac->if_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
mac->if_mode == PHY_INTERFACE_MODE_RGMII_TXID)) {
netdev_err(net_dev, "RGMII delay not supported\n");
return -EINVAL;
}
if ((mac->attr.link_type == DPMAC_LINK_TYPE_PHY &&
mac->attr.eth_if != DPMAC_ETH_IF_RGMII) ||
mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE) {
err = dpaa2_pcs_create(mac, dpmac_node, mac->attr.id);
if (err)
return err;
}
memset(&mac->phylink_config, 0, sizeof(mac->phylink_config));
mac->phylink_config.dev = &net_dev->dev;
mac->phylink_config.type = PHYLINK_NETDEV;
mac->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
MAC_10FD | MAC_100FD | MAC_1000FD | MAC_2500FD | MAC_5000FD |
MAC_10000FD | MAC_25000FD;
dpaa2_mac_set_supported_interfaces(mac);
phylink = phylink_create(&mac->phylink_config,
dpmac_node, mac->if_mode,
&dpaa2_mac_phylink_ops);
if (IS_ERR(phylink)) {
err = PTR_ERR(phylink);
goto err_pcs_destroy;
}
mac->phylink = phylink;
rtnl_lock();
err = phylink_fwnode_phy_connect(mac->phylink, dpmac_node, 0);
rtnl_unlock();
if (err) {
netdev_err(net_dev, "phylink_fwnode_phy_connect() = %d\n", err);
goto err_phylink_destroy;
}
return 0;
err_phylink_destroy:
phylink_destroy(mac->phylink);
err_pcs_destroy:
dpaa2_pcs_destroy(mac);
return err;
}
EXPORT_SYMBOL_GPL(dpaa2_mac_connect);
void dpaa2_mac_disconnect(struct dpaa2_mac *mac)
{
rtnl_lock();
phylink_disconnect_phy(mac->phylink);
rtnl_unlock();
phylink_destroy(mac->phylink);
dpaa2_pcs_destroy(mac);
of_phy_put(mac->serdes_phy);
mac->serdes_phy = NULL;
}
EXPORT_SYMBOL_GPL(dpaa2_mac_disconnect);
int dpaa2_mac_open(struct dpaa2_mac *mac)
{
struct fsl_mc_device *dpmac_dev = mac->mc_dev;
struct net_device *net_dev = mac->net_dev;
struct fwnode_handle *fw_node;
int err;
err = dpmac_open(mac->mc_io, 0, dpmac_dev->obj_desc.id,
&dpmac_dev->mc_handle);
if (err || !dpmac_dev->mc_handle) {
netdev_err(net_dev, "dpmac_open() = %d\n", err);
return -ENODEV;
}
err = dpmac_get_attributes(mac->mc_io, 0, dpmac_dev->mc_handle,
&mac->attr);
if (err) {
netdev_err(net_dev, "dpmac_get_attributes() = %d\n", err);
goto err_close_dpmac;
}
err = dpmac_get_api_version(mac->mc_io, 0, &mac->ver_major, &mac->ver_minor);
if (err) {
netdev_err(net_dev, "dpmac_get_api_version() = %d\n", err);
goto err_close_dpmac;
}
dpaa2_mac_detect_features(mac);
/* Find the device node representing the MAC device and link the device
* behind the associated netdev to it.
*/
fw_node = dpaa2_mac_get_node(&mac->mc_dev->dev, mac->attr.id);
if (IS_ERR(fw_node)) {
err = PTR_ERR(fw_node);
goto err_close_dpmac;
}
mac->fw_node = fw_node;
net_dev->dev.of_node = to_of_node(mac->fw_node);
if (mac->features & DPAA2_MAC_FEATURE_STATS_BUNDLE)
dpaa2_mac_setup_stats(mac, &mac->ethtool_stats,
DPAA2_MAC_NUM_ETHTOOL_STATS,
dpaa2_mac_ethtool_stats);
if (mac->features & DPAA2_MAC_FEATURE_STANDARD_STATS) {
dpaa2_mac_setup_stats(mac, &mac->rmon_stats,
DPAA2_MAC_NUM_RMON_STATS,
dpaa2_mac_rmon_stats);
dpaa2_mac_setup_stats(mac, &mac->pause_stats,
DPAA2_MAC_NUM_PAUSE_STATS,
dpaa2_mac_pause_stats);
dpaa2_mac_setup_stats(mac, &mac->eth_ctrl_stats,
DPAA2_MAC_NUM_ETH_CTRL_STATS,
dpaa2_mac_eth_ctrl_stats);
dpaa2_mac_setup_stats(mac, &mac->eth_mac_stats,
DPAA2_MAC_NUM_ETH_MAC_STATS,
dpaa2_mac_eth_mac_stats);
}
return 0;
err_close_dpmac:
dpmac_close(mac->mc_io, 0, dpmac_dev->mc_handle);
return err;
}
EXPORT_SYMBOL_GPL(dpaa2_mac_open);
void dpaa2_mac_close(struct dpaa2_mac *mac)
{
struct fsl_mc_device *dpmac_dev = mac->mc_dev;
if (mac->features & DPAA2_MAC_FEATURE_STATS_BUNDLE)
dpaa2_mac_clear_stats(mac, &mac->ethtool_stats,
DPAA2_MAC_NUM_ETHTOOL_STATS);
if (mac->features & DPAA2_MAC_FEATURE_STANDARD_STATS) {
dpaa2_mac_clear_stats(mac, &mac->rmon_stats,
DPAA2_MAC_NUM_RMON_STATS);
dpaa2_mac_clear_stats(mac, &mac->pause_stats,
DPAA2_MAC_NUM_PAUSE_STATS);
dpaa2_mac_clear_stats(mac, &mac->eth_ctrl_stats,
DPAA2_MAC_NUM_ETH_CTRL_STATS);
dpaa2_mac_clear_stats(mac, &mac->eth_mac_stats,
DPAA2_MAC_NUM_ETH_MAC_STATS);
}
dpmac_close(mac->mc_io, 0, dpmac_dev->mc_handle);
if (mac->fw_node)
fwnode_handle_put(mac->fw_node);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_close);
static void dpaa2_mac_transfer_stats(const struct dpmac_counter *counters,
size_t num_counters, void *s,
__le64 *cnt_values)
{
for (size_t i = 0; i < num_counters; i++) {
u64 *p = s + counters[i].offset;
*p = le64_to_cpu(cnt_values[i]);
}
}
static const struct ethtool_rmon_hist_range dpaa2_mac_rmon_ranges[] = {
{ 64, 64 },
{ 65, 127 },
{ 128, 255 },
{ 256, 511 },
{ 512, 1023 },
{ 1024, 1518 },
{ 1519, DPAA2_ETH_MFL },
{},
};
static void dpaa2_mac_get_standard_stats(struct dpaa2_mac *mac,
struct dpaa2_mac_stats *stats,
size_t num_cnt,
const struct dpmac_counter *counters,
void *s)
{
struct device *dev = mac->net_dev->dev.parent;
struct fsl_mc_device *dpmac_dev = mac->mc_dev;
size_t values_size = num_cnt * sizeof(u64);
int err;
if (!(mac->features & DPAA2_MAC_FEATURE_STANDARD_STATS))
return;
if (!stats->idx_dma_mem || !stats->values_dma_mem)
return;
dma_sync_single_for_device(dev, stats->values_iova, values_size,
DMA_FROM_DEVICE);
err = dpmac_get_statistics(mac->mc_io, 0, dpmac_dev->mc_handle,
stats->idx_iova, stats->values_iova,
num_cnt);
if (err) {
netdev_err(mac->net_dev, "%s: dpmac_get_statistics() = %d\n",
__func__, err);
return;
}
dma_sync_single_for_cpu(dev, stats->values_iova, values_size,
DMA_FROM_DEVICE);
dpaa2_mac_transfer_stats(counters, num_cnt, s, stats->values_dma_mem);
}
void dpaa2_mac_get_rmon_stats(struct dpaa2_mac *mac,
struct ethtool_rmon_stats *s,
const struct ethtool_rmon_hist_range **ranges)
{
if (s->src != ETHTOOL_MAC_STATS_SRC_AGGREGATE)
return;
dpaa2_mac_get_standard_stats(mac, &mac->rmon_stats,
DPAA2_MAC_NUM_RMON_STATS,
dpaa2_mac_rmon_stats, s);
*ranges = dpaa2_mac_rmon_ranges;
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_rmon_stats);
void dpaa2_mac_get_pause_stats(struct dpaa2_mac *mac,
struct ethtool_pause_stats *s)
{
if (s->src != ETHTOOL_MAC_STATS_SRC_AGGREGATE)
return;
dpaa2_mac_get_standard_stats(mac, &mac->pause_stats,
DPAA2_MAC_NUM_PAUSE_STATS,
dpaa2_mac_pause_stats, s);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_pause_stats);
void dpaa2_mac_get_ctrl_stats(struct dpaa2_mac *mac,
struct ethtool_eth_ctrl_stats *s)
{
if (s->src != ETHTOOL_MAC_STATS_SRC_AGGREGATE)
return;
dpaa2_mac_get_standard_stats(mac, &mac->eth_ctrl_stats,
DPAA2_MAC_NUM_ETH_CTRL_STATS,
dpaa2_mac_eth_ctrl_stats, s);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_ctrl_stats);
void dpaa2_mac_get_eth_mac_stats(struct dpaa2_mac *mac,
struct ethtool_eth_mac_stats *s)
{
if (s->src != ETHTOOL_MAC_STATS_SRC_AGGREGATE)
return;
dpaa2_mac_get_standard_stats(mac, &mac->eth_mac_stats,
DPAA2_MAC_NUM_ETH_MAC_STATS,
dpaa2_mac_eth_mac_stats, s);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_eth_mac_stats);
int dpaa2_mac_get_sset_count(void)
{
return DPAA2_MAC_NUM_ETHTOOL_STATS;
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_sset_count);
void dpaa2_mac_get_strings(u8 **data)
{
int i;
for (i = 0; i < DPAA2_MAC_NUM_ETHTOOL_STATS; i++)
ethtool_puts(data, dpaa2_mac_ethtool_stats[i].name);
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_strings);
void dpaa2_mac_get_ethtool_stats(struct dpaa2_mac *mac, u64 *data)
{
size_t values_size = DPAA2_MAC_NUM_ETHTOOL_STATS * sizeof(u64);
struct device *dev = mac->net_dev->dev.parent;
struct fsl_mc_device *dpmac_dev = mac->mc_dev;
__le64 *cnt_values;
int i, err;
u64 value;
if (!(mac->features & DPAA2_MAC_FEATURE_STATS_BUNDLE))
goto fallback;
if (!mac->ethtool_stats.idx_dma_mem ||
!mac->ethtool_stats.values_dma_mem)
goto fallback;
dma_sync_single_for_device(dev, mac->ethtool_stats.values_iova,
values_size, DMA_FROM_DEVICE);
err = dpmac_get_statistics(mac->mc_io, 0, dpmac_dev->mc_handle,
mac->ethtool_stats.idx_iova,
mac->ethtool_stats.values_iova,
DPAA2_MAC_NUM_ETHTOOL_STATS);
if (err)
goto fallback;
dma_sync_single_for_cpu(dev, mac->ethtool_stats.values_iova,
values_size, DMA_FROM_DEVICE);
cnt_values = mac->ethtool_stats.values_dma_mem;
for (i = 0; i < DPAA2_MAC_NUM_ETHTOOL_STATS; i++)
*(data + i) = le64_to_cpu(*cnt_values++);
return;
fallback:
/* Fallback and retrieve each counter one by one */
for (i = 0; i < DPAA2_MAC_NUM_ETHTOOL_STATS; i++) {
err = dpmac_get_counter(mac->mc_io, 0, dpmac_dev->mc_handle,
dpaa2_mac_ethtool_stats[i].id, &value);
if (err) {
netdev_err_once(mac->net_dev,
"dpmac_get_counter error %d\n", err);
*(data + i) = U64_MAX;
continue;
}
*(data + i) = value;
}
}
EXPORT_SYMBOL_GPL(dpaa2_mac_get_ethtool_stats);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DPAA2 Ethernet MAC library");
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
+85
View File
@@ -0,0 +1,85 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2019, 2024-2026 NXP */
#ifndef DPAA2_MAC_H
#define DPAA2_MAC_H
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/phylink.h>
#include "dpmac.h"
#include "dpmac-cmd.h"
struct dpaa2_mac_stats {
__le32 *idx_dma_mem;
__le64 *values_dma_mem;
dma_addr_t idx_iova, values_iova;
};
struct dpaa2_mac {
struct fsl_mc_device *mc_dev;
struct dpmac_link_state state;
struct net_device *net_dev;
struct fsl_mc_io *mc_io;
struct dpmac_attr attr;
u16 ver_major, ver_minor;
unsigned long features;
struct phylink_config phylink_config;
struct phylink *phylink;
phy_interface_t if_mode;
enum dpmac_link_type if_link_type;
struct phylink_pcs *pcs;
struct fwnode_handle *fw_node;
struct phy *serdes_phy;
struct dpaa2_mac_stats ethtool_stats;
struct dpaa2_mac_stats rmon_stats;
struct dpaa2_mac_stats pause_stats;
struct dpaa2_mac_stats eth_ctrl_stats;
struct dpaa2_mac_stats eth_mac_stats;
};
static inline bool dpaa2_mac_is_type_phy(struct dpaa2_mac *mac)
{
if (!mac)
return false;
return mac->attr.link_type == DPMAC_LINK_TYPE_PHY ||
mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE;
}
int dpaa2_mac_open(struct dpaa2_mac *mac);
void dpaa2_mac_close(struct dpaa2_mac *mac);
int dpaa2_mac_connect(struct dpaa2_mac *mac);
void dpaa2_mac_disconnect(struct dpaa2_mac *mac);
int dpaa2_mac_get_sset_count(void);
void dpaa2_mac_get_strings(u8 **data);
void dpaa2_mac_get_ethtool_stats(struct dpaa2_mac *mac, u64 *data);
void dpaa2_mac_get_rmon_stats(struct dpaa2_mac *mac,
struct ethtool_rmon_stats *s,
const struct ethtool_rmon_hist_range **ranges);
void dpaa2_mac_get_pause_stats(struct dpaa2_mac *mac,
struct ethtool_pause_stats *s);
void dpaa2_mac_get_ctrl_stats(struct dpaa2_mac *mac,
struct ethtool_eth_ctrl_stats *s);
void dpaa2_mac_get_eth_mac_stats(struct dpaa2_mac *mac,
struct ethtool_eth_mac_stats *s);
void dpaa2_mac_start(struct dpaa2_mac *mac);
void dpaa2_mac_stop(struct dpaa2_mac *mac);
#endif /* DPAA2_MAC_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c
+259
View File
@@ -0,0 +1,259 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016-2018 NXP
* Copyright 2020 NXP
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/fsl/mc.h>
#include "dpaa2-ptp.h"
static int dpaa2_ptp_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
struct fsl_mc_device *mc_dev;
struct device *dev;
u32 mask = 0;
u32 bit;
int err;
dev = ptp_qoriq->dev;
mc_dev = to_fsl_mc_device(dev);
switch (rq->type) {
case PTP_CLK_REQ_EXTTS:
switch (rq->extts.index) {
case 0:
bit = DPRTC_EVENT_ETS1;
break;
case 1:
bit = DPRTC_EVENT_ETS2;
break;
default:
return -EINVAL;
}
if (on)
extts_clean_up(ptp_qoriq, rq->extts.index, false);
break;
case PTP_CLK_REQ_PPS:
bit = DPRTC_EVENT_PPS;
break;
default:
return -EOPNOTSUPP;
}
err = dprtc_get_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle,
DPRTC_IRQ_INDEX, &mask);
if (err < 0) {
dev_err(dev, "dprtc_get_irq_mask(): %d\n", err);
return err;
}
if (on)
mask |= bit;
else
mask &= ~bit;
err = dprtc_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle,
DPRTC_IRQ_INDEX, mask);
if (err < 0) {
dev_err(dev, "dprtc_set_irq_mask(): %d\n", err);
return err;
}
return 0;
}
static const struct ptp_clock_info dpaa2_ptp_caps = {
.owner = THIS_MODULE,
.name = "DPAA2 PTP Clock",
.max_adj = 512000,
.n_alarm = 2,
.n_ext_ts = 2,
.n_per_out = 3,
.n_pins = 0,
.pps = 1,
.adjfine = ptp_qoriq_adjfine,
.adjtime = ptp_qoriq_adjtime,
.gettime64 = ptp_qoriq_gettime,
.settime64 = ptp_qoriq_settime,
.enable = dpaa2_ptp_enable,
};
static irqreturn_t dpaa2_ptp_irq_handler_thread(int irq, void *priv)
{
struct ptp_qoriq *ptp_qoriq = priv;
struct ptp_clock_event event;
struct fsl_mc_device *mc_dev;
struct device *dev;
u32 status = 0;
int err;
dev = ptp_qoriq->dev;
mc_dev = to_fsl_mc_device(dev);
err = dprtc_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
DPRTC_IRQ_INDEX, &status);
if (unlikely(err)) {
dev_err(dev, "dprtc_get_irq_status err %d\n", err);
return IRQ_NONE;
}
if (status & DPRTC_EVENT_PPS) {
event.type = PTP_CLOCK_PPS;
ptp_clock_event(ptp_qoriq->clock, &event);
}
if (status & DPRTC_EVENT_ETS1)
extts_clean_up(ptp_qoriq, 0, true);
if (status & DPRTC_EVENT_ETS2)
extts_clean_up(ptp_qoriq, 1, true);
err = dprtc_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
DPRTC_IRQ_INDEX, status);
if (unlikely(err)) {
dev_err(dev, "dprtc_clear_irq_status err %d\n", err);
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev)
{
struct device *dev = &mc_dev->dev;
struct ptp_qoriq *ptp_qoriq;
struct device_node *node;
void __iomem *base;
int err;
ptp_qoriq = devm_kzalloc(dev, sizeof(*ptp_qoriq), GFP_KERNEL);
if (!ptp_qoriq)
return -ENOMEM;
err = fsl_mc_portal_allocate(mc_dev, 0, &mc_dev->mc_io);
if (err) {
if (err == -ENXIO)
err = -EPROBE_DEFER;
else
dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
goto err_exit;
}
err = dprtc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id,
&mc_dev->mc_handle);
if (err) {
dev_err(dev, "dprtc_open err %d\n", err);
goto err_free_mcp;
}
ptp_qoriq->dev = dev;
node = of_find_compatible_node(NULL, NULL, "fsl,dpaa2-ptp");
if (!node) {
err = -ENODEV;
goto err_close;
}
dev->of_node = node;
base = of_iomap(node, 0);
if (!base) {
err = -ENOMEM;
goto err_put;
}
err = fsl_mc_allocate_irqs(mc_dev);
if (err) {
dev_err(dev, "MC irqs allocation failed\n");
goto err_unmap;
}
ptp_qoriq->irq = mc_dev->irqs[0]->virq;
err = request_threaded_irq(ptp_qoriq->irq, NULL,
dpaa2_ptp_irq_handler_thread,
IRQF_NO_SUSPEND | IRQF_ONESHOT,
dev_name(dev), ptp_qoriq);
if (err < 0) {
dev_err(dev, "devm_request_threaded_irq(): %d\n", err);
goto err_free_mc_irq;
}
err = dprtc_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle,
DPRTC_IRQ_INDEX, 1);
if (err < 0) {
dev_err(dev, "dprtc_set_irq_enable(): %d\n", err);
goto err_free_threaded_irq;
}
err = ptp_qoriq_init(ptp_qoriq, base, &dpaa2_ptp_caps);
if (err)
goto err_free_threaded_irq;
dpaa2_phc_index = ptp_qoriq->phc_index;
dpaa2_ptp = ptp_qoriq;
dev_set_drvdata(dev, ptp_qoriq);
return 0;
err_free_threaded_irq:
free_irq(ptp_qoriq->irq, ptp_qoriq);
err_free_mc_irq:
fsl_mc_free_irqs(mc_dev);
err_unmap:
iounmap(base);
err_put:
of_node_put(node);
err_close:
dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
err_free_mcp:
fsl_mc_portal_free(mc_dev->mc_io);
err_exit:
return err;
}
static void dpaa2_ptp_remove(struct fsl_mc_device *mc_dev)
{
struct device *dev = &mc_dev->dev;
struct ptp_qoriq *ptp_qoriq;
ptp_qoriq = dev_get_drvdata(dev);
dpaa2_phc_index = -1;
ptp_qoriq_free(ptp_qoriq);
fsl_mc_free_irqs(mc_dev);
dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
fsl_mc_portal_free(mc_dev->mc_io);
}
static const struct fsl_mc_device_id dpaa2_ptp_match_id_table[] = {
{
.vendor = FSL_MC_VENDOR_FREESCALE,
.obj_type = "dprtc",
},
{}
};
MODULE_DEVICE_TABLE(fslmc, dpaa2_ptp_match_id_table);
static struct fsl_mc_driver dpaa2_ptp_drv = {
.driver = {
.name = KBUILD_MODNAME,
.owner = THIS_MODULE,
},
.probe = dpaa2_ptp_probe,
.remove = dpaa2_ptp_remove,
.match_id_table = dpaa2_ptp_match_id_table,
};
module_fsl_mc_driver(dpaa2_ptp_drv);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DPAA2 PTP Clock Driver");
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.h
+18
View File
@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2018 NXP
* Copyright 2020 NXP
*/
#ifndef __RTC_H
#define __RTC_H
#include <linux/fsl/ptp_qoriq.h>
#include "dprtc.h"
#include "dprtc-cmd.h"
extern int dpaa2_phc_index;
extern struct ptp_qoriq *dpaa2_ptp;
#endif
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-ethtool.c
+267
View File
@@ -0,0 +1,267 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DPAA2 Ethernet Switch ethtool support
*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2017-2018, 2024-2026 NXP
*
*/
#include <linux/ethtool.h>
#include "dpaa2-switch.h"
static struct {
enum dpsw_counter id;
char name[ETH_GSTRING_LEN];
} dpaa2_switch_ethtool_counters[] = {
{DPSW_CNT_ING_FRAME, "[hw] rx frames"},
{DPSW_CNT_ING_BYTE, "[hw] rx bytes"},
{DPSW_CNT_ING_FLTR_FRAME, "[hw] rx filtered frames"},
{DPSW_CNT_ING_FRAME_DISCARD, "[hw] rx discarded frames"},
{DPSW_CNT_ING_BCAST_FRAME, "[hw] rx bcast frames"},
{DPSW_CNT_ING_BCAST_BYTES, "[hw] rx bcast bytes"},
{DPSW_CNT_ING_MCAST_FRAME, "[hw] rx mcast frames"},
{DPSW_CNT_ING_MCAST_BYTE, "[hw] rx mcast bytes"},
{DPSW_CNT_EGR_FRAME, "[hw] tx frames"},
{DPSW_CNT_EGR_BYTE, "[hw] tx bytes"},
{DPSW_CNT_EGR_FRAME_DISCARD, "[hw] tx discarded frames"},
{DPSW_CNT_ING_NO_BUFF_DISCARD, "[hw] rx nobuffer discards"},
};
#define DPAA2_SWITCH_NUM_COUNTERS ARRAY_SIZE(dpaa2_switch_ethtool_counters)
static void dpaa2_switch_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
{
struct ethsw_port_priv *port_priv = netdev_priv(netdev);
u16 version_major, version_minor;
int err;
strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
err = dpsw_get_api_version(port_priv->ethsw_data->mc_io, 0,
&version_major,
&version_minor);
if (err)
strscpy(drvinfo->fw_version, "N/A",
sizeof(drvinfo->fw_version));
else
snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
"%u.%u", version_major, version_minor);
strscpy(drvinfo->bus_info, dev_name(netdev->dev.parent->parent),
sizeof(drvinfo->bus_info));
}
static int
dpaa2_switch_get_link_ksettings(struct net_device *netdev,
struct ethtool_link_ksettings *link_ksettings)
{
struct ethsw_port_priv *port_priv = netdev_priv(netdev);
struct dpsw_link_state state = {0};
int err;
mutex_lock(&port_priv->mac_lock);
if (dpaa2_switch_port_is_type_phy(port_priv)) {
err = phylink_ethtool_ksettings_get(port_priv->mac->phylink,
link_ksettings);
mutex_unlock(&port_priv->mac_lock);
return err;
}
mutex_unlock(&port_priv->mac_lock);
err = dpsw_if_get_link_state(port_priv->ethsw_data->mc_io, 0,
port_priv->ethsw_data->dpsw_handle,
port_priv->idx,
&state);
if (err) {
netdev_err(netdev, "ERROR %d getting link state\n", err);
goto out;
}
/* At the moment, we have no way of interrogating the DPMAC
* from the DPSW side or there may not exist a DPMAC at all.
* Report only autoneg state, duplexity and speed.
*/
if (state.options & DPSW_LINK_OPT_AUTONEG)
link_ksettings->base.autoneg = AUTONEG_ENABLE;
if (!(state.options & DPSW_LINK_OPT_HALF_DUPLEX))
link_ksettings->base.duplex = DUPLEX_FULL;
link_ksettings->base.speed = state.rate;
out:
return err;
}
static int
dpaa2_switch_set_link_ksettings(struct net_device *netdev,
const struct ethtool_link_ksettings *link_ksettings)
{
struct ethsw_port_priv *port_priv = netdev_priv(netdev);
struct ethsw_core *ethsw = port_priv->ethsw_data;
struct dpsw_link_cfg cfg = {0};
bool if_running;
int err = 0, ret;
mutex_lock(&port_priv->mac_lock);
if (dpaa2_switch_port_is_type_phy(port_priv)) {
err = phylink_ethtool_ksettings_set(port_priv->mac->phylink,
link_ksettings);
mutex_unlock(&port_priv->mac_lock);
return err;
}
mutex_unlock(&port_priv->mac_lock);
/* Interface needs to be down to change link settings */
if_running = netif_running(netdev);
if (if_running) {
err = dpsw_if_disable(ethsw->mc_io, 0,
ethsw->dpsw_handle,
port_priv->idx);
if (err) {
netdev_err(netdev, "dpsw_if_disable err %d\n", err);
return err;
}
}
cfg.rate = link_ksettings->base.speed;
if (link_ksettings->base.autoneg == AUTONEG_ENABLE)
cfg.options |= DPSW_LINK_OPT_AUTONEG;
else
cfg.options &= ~DPSW_LINK_OPT_AUTONEG;
if (link_ksettings->base.duplex == DUPLEX_HALF)
cfg.options |= DPSW_LINK_OPT_HALF_DUPLEX;
else
cfg.options &= ~DPSW_LINK_OPT_HALF_DUPLEX;
err = dpsw_if_set_link_cfg(port_priv->ethsw_data->mc_io, 0,
port_priv->ethsw_data->dpsw_handle,
port_priv->idx,
&cfg);
if (if_running) {
ret = dpsw_if_enable(ethsw->mc_io, 0,
ethsw->dpsw_handle,
port_priv->idx);
if (ret) {
netdev_err(netdev, "dpsw_if_enable err %d\n", ret);
return ret;
}
}
return err;
}
static int
dpaa2_switch_ethtool_get_sset_count(struct net_device *netdev, int sset)
{
switch (sset) {
case ETH_SS_STATS:
return DPAA2_SWITCH_NUM_COUNTERS + dpaa2_mac_get_sset_count();
default:
return -EOPNOTSUPP;
}
}
static void dpaa2_switch_ethtool_get_strings(struct net_device *netdev,
u32 stringset, u8 *data)
{
const char *str;
int i;
switch (stringset) {
case ETH_SS_STATS:
for (i = 0; i < DPAA2_SWITCH_NUM_COUNTERS; i++) {
str = dpaa2_switch_ethtool_counters[i].name;
ethtool_puts(&data, str);
}
dpaa2_mac_get_strings(&data);
break;
}
}
static void dpaa2_switch_ethtool_get_stats(struct net_device *netdev,
struct ethtool_stats *stats,
u64 *data)
{
struct ethsw_port_priv *port_priv = netdev_priv(netdev);
int i, err;
for (i = 0; i < DPAA2_SWITCH_NUM_COUNTERS; i++) {
err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
port_priv->ethsw_data->dpsw_handle,
port_priv->idx,
dpaa2_switch_ethtool_counters[i].id,
&data[i]);
if (err)
netdev_err(netdev, "dpsw_if_get_counter[%s] err %d\n",
dpaa2_switch_ethtool_counters[i].name, err);
}
mutex_lock(&port_priv->mac_lock);
if (dpaa2_switch_port_has_mac(port_priv))
dpaa2_mac_get_ethtool_stats(port_priv->mac, data + i);
mutex_unlock(&port_priv->mac_lock);
}
static void
dpaa2_switch_get_rmon_stats(struct net_device *netdev,
struct ethtool_rmon_stats *rmon_stats,
const struct ethtool_rmon_hist_range **ranges)
{
struct ethsw_port_priv *port_priv = netdev_priv(netdev);
mutex_lock(&port_priv->mac_lock);
if (dpaa2_switch_port_has_mac(port_priv))
dpaa2_mac_get_rmon_stats(port_priv->mac, rmon_stats, ranges);
mutex_unlock(&port_priv->mac_lock);
}
static void
dpaa2_switch_get_ctrl_stats(struct net_device *net_dev,
struct ethtool_eth_ctrl_stats *ctrl_stats)
{
struct ethsw_port_priv *port_priv = netdev_priv(net_dev);
mutex_lock(&port_priv->mac_lock);
if (dpaa2_switch_port_has_mac(port_priv))
dpaa2_mac_get_ctrl_stats(port_priv->mac, ctrl_stats);
mutex_unlock(&port_priv->mac_lock);
}
static void
dpaa2_switch_get_eth_mac_stats(struct net_device *net_dev,
struct ethtool_eth_mac_stats *eth_mac_stats)
{
struct ethsw_port_priv *port_priv = netdev_priv(net_dev);
mutex_lock(&port_priv->mac_lock);
if (dpaa2_switch_port_has_mac(port_priv))
dpaa2_mac_get_eth_mac_stats(port_priv->mac, eth_mac_stats);
mutex_unlock(&port_priv->mac_lock);
}
const struct ethtool_ops dpaa2_switch_port_ethtool_ops = {
.get_drvinfo = dpaa2_switch_get_drvinfo,
.get_link = ethtool_op_get_link,
.get_link_ksettings = dpaa2_switch_get_link_ksettings,
.set_link_ksettings = dpaa2_switch_set_link_ksettings,
.get_strings = dpaa2_switch_ethtool_get_strings,
.get_ethtool_stats = dpaa2_switch_ethtool_get_stats,
.get_sset_count = dpaa2_switch_ethtool_get_sset_count,
.get_rmon_stats = dpaa2_switch_get_rmon_stats,
.get_eth_ctrl_stats = dpaa2_switch_get_ctrl_stats,
.get_eth_mac_stats = dpaa2_switch_get_eth_mac_stats,
};
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
+891
View File
@@ -0,0 +1,891 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DPAA2 Ethernet Switch flower support
*
* Copyright 2021 NXP
*
*/
#include "dpaa2-switch.h"
static int dpaa2_switch_flower_parse_key(struct flow_cls_offload *cls,
struct dpsw_acl_key *acl_key)
{
struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
struct flow_dissector *dissector = rule->match.dissector;
struct netlink_ext_ack *extack = cls->common.extack;
struct dpsw_acl_fields *acl_h, *acl_m;
if (dissector->used_keys &
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS))) {
NL_SET_ERR_MSG_MOD(extack,
"Unsupported keys used");
return -EOPNOTSUPP;
}
acl_h = &acl_key->match;
acl_m = &acl_key->mask;
if (flow_rule_match_has_control_flags(rule, extack))
return -EOPNOTSUPP;
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
struct flow_match_basic match;
flow_rule_match_basic(rule, &match);
acl_h->l3_protocol = match.key->ip_proto;
acl_h->l2_ether_type = be16_to_cpu(match.key->n_proto);
acl_m->l3_protocol = match.mask->ip_proto;
acl_m->l2_ether_type = be16_to_cpu(match.mask->n_proto);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
struct flow_match_eth_addrs match;
flow_rule_match_eth_addrs(rule, &match);
ether_addr_copy(acl_h->l2_dest_mac, &match.key->dst[0]);
ether_addr_copy(acl_h->l2_source_mac, &match.key->src[0]);
ether_addr_copy(acl_m->l2_dest_mac, &match.mask->dst[0]);
ether_addr_copy(acl_m->l2_source_mac, &match.mask->src[0]);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
struct flow_match_vlan match;
flow_rule_match_vlan(rule, &match);
acl_h->l2_vlan_id = match.key->vlan_id;
acl_h->l2_tpid = be16_to_cpu(match.key->vlan_tpid);
acl_h->l2_pcp_dei = match.key->vlan_priority << 1 |
match.key->vlan_dei;
acl_m->l2_vlan_id = match.mask->vlan_id;
acl_m->l2_tpid = be16_to_cpu(match.mask->vlan_tpid);
acl_m->l2_pcp_dei = match.mask->vlan_priority << 1 |
match.mask->vlan_dei;
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) {
struct flow_match_ipv4_addrs match;
flow_rule_match_ipv4_addrs(rule, &match);
acl_h->l3_source_ip = be32_to_cpu(match.key->src);
acl_h->l3_dest_ip = be32_to_cpu(match.key->dst);
acl_m->l3_source_ip = be32_to_cpu(match.mask->src);
acl_m->l3_dest_ip = be32_to_cpu(match.mask->dst);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
struct flow_match_ports match;
flow_rule_match_ports(rule, &match);
acl_h->l4_source_port = be16_to_cpu(match.key->src);
acl_h->l4_dest_port = be16_to_cpu(match.key->dst);
acl_m->l4_source_port = be16_to_cpu(match.mask->src);
acl_m->l4_dest_port = be16_to_cpu(match.mask->dst);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
struct flow_match_ip match;
flow_rule_match_ip(rule, &match);
if (match.mask->ttl != 0) {
NL_SET_ERR_MSG_MOD(extack,
"Matching on TTL not supported");
return -EOPNOTSUPP;
}
if ((match.mask->tos & 0x3) != 0) {
NL_SET_ERR_MSG_MOD(extack,
"Matching on ECN not supported, only DSCP");
return -EOPNOTSUPP;
}
acl_h->l3_dscp = match.key->tos >> 2;
acl_m->l3_dscp = match.mask->tos >> 2;
}
return 0;
}
int dpaa2_switch_acl_entry_add(struct dpaa2_switch_filter_block *filter_block,
struct dpaa2_switch_acl_entry *entry)
{
struct dpsw_acl_entry_cfg *acl_entry_cfg = &entry->cfg;
struct ethsw_core *ethsw = filter_block->ethsw;
struct dpsw_acl_key *acl_key = &entry->key;
struct device *dev = ethsw->dev;
u8 *cmd_buff;
int err;
cmd_buff = kzalloc(DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE, GFP_KERNEL);
if (!cmd_buff)
return -ENOMEM;
dpsw_acl_prepare_entry_cfg(acl_key, cmd_buff);
acl_entry_cfg->key_iova = dma_map_single(dev, cmd_buff,
DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE,
DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, acl_entry_cfg->key_iova))) {
dev_err(dev, "DMA mapping failed\n");
kfree(cmd_buff);
return -EFAULT;
}
err = dpsw_acl_add_entry(ethsw->mc_io, 0, ethsw->dpsw_handle,
filter_block->acl_id, acl_entry_cfg);
dma_unmap_single(dev, acl_entry_cfg->key_iova,
DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE,
DMA_TO_DEVICE);
if (err) {
dev_err(dev, "dpsw_acl_add_entry() failed %d\n", err);
kfree(cmd_buff);
return err;
}
kfree(cmd_buff);
return 0;
}
static int
dpaa2_switch_acl_entry_remove(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry)
{
struct dpsw_acl_entry_cfg *acl_entry_cfg = &entry->cfg;
struct dpsw_acl_key *acl_key = &entry->key;
struct ethsw_core *ethsw = block->ethsw;
struct device *dev = ethsw->dev;
u8 *cmd_buff;
int err;
cmd_buff = kzalloc(DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE, GFP_KERNEL);
if (!cmd_buff)
return -ENOMEM;
dpsw_acl_prepare_entry_cfg(acl_key, cmd_buff);
acl_entry_cfg->key_iova = dma_map_single(dev, cmd_buff,
DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE,
DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, acl_entry_cfg->key_iova))) {
dev_err(dev, "DMA mapping failed\n");
kfree(cmd_buff);
return -EFAULT;
}
err = dpsw_acl_remove_entry(ethsw->mc_io, 0, ethsw->dpsw_handle,
block->acl_id, acl_entry_cfg);
dma_unmap_single(dev, acl_entry_cfg->key_iova,
DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE, DMA_TO_DEVICE);
if (err) {
dev_err(dev, "dpsw_acl_remove_entry() failed %d\n", err);
kfree(cmd_buff);
return err;
}
kfree(cmd_buff);
return 0;
}
static int
dpaa2_switch_acl_entry_add_to_list(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry)
{
struct dpaa2_switch_acl_entry *tmp;
struct list_head *pos, *n;
int index = 0;
if (list_empty(&block->acl_entries)) {
list_add(&entry->list, &block->acl_entries);
return index;
}
list_for_each_safe(pos, n, &block->acl_entries) {
tmp = list_entry(pos, struct dpaa2_switch_acl_entry, list);
if (entry->prio < tmp->prio)
break;
index++;
}
list_add(&entry->list, pos->prev);
return index;
}
static struct dpaa2_switch_acl_entry*
dpaa2_switch_acl_entry_get_by_index(struct dpaa2_switch_filter_block *block,
int index)
{
struct dpaa2_switch_acl_entry *tmp;
int i = 0;
list_for_each_entry(tmp, &block->acl_entries, list) {
if (i == index)
return tmp;
++i;
}
return NULL;
}
static int
dpaa2_switch_acl_entry_set_precedence(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry,
int precedence)
{
int err;
err = dpaa2_switch_acl_entry_remove(block, entry);
if (err)
return err;
entry->cfg.precedence = precedence;
return dpaa2_switch_acl_entry_add(block, entry);
}
static int
dpaa2_switch_acl_tbl_add_entry(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry)
{
struct dpaa2_switch_acl_entry *tmp;
int index, i, precedence, err;
/* Add the new ACL entry to the linked list and get its index */
index = dpaa2_switch_acl_entry_add_to_list(block, entry);
/* Move up in priority the ACL entries to make space
* for the new filter.
*/
precedence = DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES - block->num_acl_rules - 1;
for (i = 0; i < index; i++) {
tmp = dpaa2_switch_acl_entry_get_by_index(block, i);
err = dpaa2_switch_acl_entry_set_precedence(block, tmp,
precedence);
if (err)
return err;
precedence++;
}
/* Add the new entry to hardware */
entry->cfg.precedence = precedence;
err = dpaa2_switch_acl_entry_add(block, entry);
block->num_acl_rules++;
return err;
}
static struct dpaa2_switch_acl_entry *
dpaa2_switch_acl_tbl_find_entry_by_cookie(struct dpaa2_switch_filter_block *block,
unsigned long cookie)
{
struct dpaa2_switch_acl_entry *tmp, *n;
list_for_each_entry_safe(tmp, n, &block->acl_entries, list) {
if (tmp->cookie == cookie)
return tmp;
}
return NULL;
}
static int
dpaa2_switch_acl_entry_get_index(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry)
{
struct dpaa2_switch_acl_entry *tmp, *n;
int index = 0;
list_for_each_entry_safe(tmp, n, &block->acl_entries, list) {
if (tmp->cookie == entry->cookie)
return index;
index++;
}
return -ENOENT;
}
static struct dpaa2_switch_mirror_entry *
dpaa2_switch_mirror_find_entry_by_cookie(struct dpaa2_switch_filter_block *block,
unsigned long cookie)
{
struct dpaa2_switch_mirror_entry *tmp, *n;
list_for_each_entry_safe(tmp, n, &block->mirror_entries, list) {
if (tmp->cookie == cookie)
return tmp;
}
return NULL;
}
static int
dpaa2_switch_acl_tbl_remove_entry(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry)
{
struct dpaa2_switch_acl_entry *tmp;
int index, i, precedence, err;
index = dpaa2_switch_acl_entry_get_index(block, entry);
/* Remove from hardware the ACL entry */
err = dpaa2_switch_acl_entry_remove(block, entry);
if (err)
return err;
block->num_acl_rules--;
/* Remove it from the list also */
list_del(&entry->list);
/* Move down in priority the entries over the deleted one */
precedence = entry->cfg.precedence;
for (i = index - 1; i >= 0; i--) {
tmp = dpaa2_switch_acl_entry_get_by_index(block, i);
err = dpaa2_switch_acl_entry_set_precedence(block, tmp,
precedence);
if (err)
return err;
precedence--;
}
kfree(entry);
return 0;
}
static int dpaa2_switch_tc_parse_action_acl(struct ethsw_core *ethsw,
struct flow_action_entry *cls_act,
struct dpsw_acl_result *dpsw_act,
struct netlink_ext_ack *extack)
{
int err = 0;
switch (cls_act->id) {
case FLOW_ACTION_TRAP:
dpsw_act->action = DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF;
break;
case FLOW_ACTION_REDIRECT:
if (!dpaa2_switch_port_dev_check(cls_act->dev)) {
NL_SET_ERR_MSG_MOD(extack,
"Destination not a DPAA2 switch port");
return -EOPNOTSUPP;
}
dpsw_act->if_id = dpaa2_switch_get_index(ethsw, cls_act->dev);
dpsw_act->action = DPSW_ACL_ACTION_REDIRECT;
break;
case FLOW_ACTION_DROP:
dpsw_act->action = DPSW_ACL_ACTION_DROP;
break;
default:
NL_SET_ERR_MSG_MOD(extack,
"Action not supported");
err = -EOPNOTSUPP;
goto out;
}
out:
return err;
}
static int
dpaa2_switch_block_add_mirror(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_mirror_entry *entry,
u16 to, struct netlink_ext_ack *extack)
{
unsigned long block_ports = block->ports;
struct ethsw_core *ethsw = block->ethsw;
struct ethsw_port_priv *port_priv;
unsigned long ports_added = 0;
u16 vlan = entry->cfg.vlan_id;
bool mirror_port_enabled;
int err, port;
/* Setup the mirroring port */
mirror_port_enabled = (ethsw->mirror_port != ethsw->sw_attr.num_ifs);
if (!mirror_port_enabled) {
err = dpsw_set_reflection_if(ethsw->mc_io, 0,
ethsw->dpsw_handle, to);
if (err)
return err;
ethsw->mirror_port = to;
}
/* Setup the same egress mirroring configuration on all the switch
* ports that share the same filter block.
*/
for_each_set_bit(port, &block_ports, ethsw->sw_attr.num_ifs) {
port_priv = ethsw->ports[port];
/* We cannot add a per VLAN mirroring rule if the VLAN in
* question is not installed on the switch port.
*/
if (entry->cfg.filter == DPSW_REFLECTION_FILTER_INGRESS_VLAN &&
!(port_priv->vlans[vlan] & ETHSW_VLAN_MEMBER)) {
NL_SET_ERR_MSG(extack,
"VLAN must be installed on the switch port");
err = -EINVAL;
goto err_remove_filters;
}
err = dpsw_if_add_reflection(ethsw->mc_io, 0,
ethsw->dpsw_handle,
port, &entry->cfg);
if (err)
goto err_remove_filters;
ports_added |= BIT(port);
}
list_add(&entry->list, &block->mirror_entries);
return 0;
err_remove_filters:
for_each_set_bit(port, &ports_added, ethsw->sw_attr.num_ifs) {
dpsw_if_remove_reflection(ethsw->mc_io, 0, ethsw->dpsw_handle,
port, &entry->cfg);
}
if (!mirror_port_enabled)
ethsw->mirror_port = ethsw->sw_attr.num_ifs;
return err;
}
static int
dpaa2_switch_block_remove_mirror(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_mirror_entry *entry)
{
struct dpsw_reflection_cfg *cfg = &entry->cfg;
unsigned long block_ports = block->ports;
struct ethsw_core *ethsw = block->ethsw;
int port;
/* Remove this mirroring configuration from all the ports belonging to
* the filter block.
*/
for_each_set_bit(port, &block_ports, ethsw->sw_attr.num_ifs)
dpsw_if_remove_reflection(ethsw->mc_io, 0, ethsw->dpsw_handle,
port, cfg);
/* Also remove it from the list of mirror filters */
list_del(&entry->list);
kfree(entry);
/* If this was the last mirror filter, then unset the mirror port */
if (list_empty(&block->mirror_entries))
ethsw->mirror_port = ethsw->sw_attr.num_ifs;
return 0;
}
static int
dpaa2_switch_cls_flower_replace_acl(struct dpaa2_switch_filter_block *block,
struct flow_cls_offload *cls)
{
struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
struct netlink_ext_ack *extack = cls->common.extack;
struct dpaa2_switch_acl_entry *acl_entry;
struct ethsw_core *ethsw = block->ethsw;
struct flow_action_entry *act;
int err;
if (dpaa2_switch_acl_tbl_is_full(block)) {
NL_SET_ERR_MSG(extack, "Maximum filter capacity reached");
return -ENOMEM;
}
acl_entry = kzalloc_obj(*acl_entry);
if (!acl_entry)
return -ENOMEM;
err = dpaa2_switch_flower_parse_key(cls, &acl_entry->key);
if (err)
goto free_acl_entry;
act = &rule->action.entries[0];
err = dpaa2_switch_tc_parse_action_acl(ethsw, act,
&acl_entry->cfg.result, extack);
if (err)
goto free_acl_entry;
acl_entry->prio = cls->common.prio;
acl_entry->cookie = cls->cookie;
err = dpaa2_switch_acl_tbl_add_entry(block, acl_entry);
if (err)
goto free_acl_entry;
return 0;
free_acl_entry:
kfree(acl_entry);
return err;
}
static int dpaa2_switch_flower_parse_mirror_key(struct flow_cls_offload *cls,
u16 *vlan)
{
struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
struct flow_dissector *dissector = rule->match.dissector;
struct netlink_ext_ack *extack = cls->common.extack;
int ret = -EOPNOTSUPP;
if (dissector->used_keys &
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
NL_SET_ERR_MSG_MOD(extack,
"Mirroring is supported only per VLAN");
return -EOPNOTSUPP;
}
if (flow_rule_match_has_control_flags(rule, extack))
return -EOPNOTSUPP;
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
struct flow_match_vlan match;
flow_rule_match_vlan(rule, &match);
if (match.mask->vlan_priority != 0 ||
match.mask->vlan_dei != 0) {
NL_SET_ERR_MSG_MOD(extack,
"Only matching on VLAN ID supported");
return -EOPNOTSUPP;
}
if (match.mask->vlan_id != 0xFFF) {
NL_SET_ERR_MSG_MOD(extack,
"Masked matching not supported");
return -EOPNOTSUPP;
}
*vlan = (u16)match.key->vlan_id;
ret = 0;
}
return ret;
}
static int
dpaa2_switch_cls_flower_replace_mirror(struct dpaa2_switch_filter_block *block,
struct flow_cls_offload *cls)
{
struct netlink_ext_ack *extack = cls->common.extack;
struct dpaa2_switch_mirror_entry *mirror_entry;
struct ethsw_core *ethsw = block->ethsw;
struct dpaa2_switch_mirror_entry *tmp;
struct flow_action_entry *cls_act;
struct list_head *pos, *n;
bool mirror_port_enabled;
u16 if_id, vlan;
int err;
mirror_port_enabled = (ethsw->mirror_port != ethsw->sw_attr.num_ifs);
cls_act = &cls->rule->action.entries[0];
/* Offload rules only when the destination is a DPAA2 switch port */
if (!dpaa2_switch_port_dev_check(cls_act->dev)) {
NL_SET_ERR_MSG_MOD(extack,
"Destination not a DPAA2 switch port");
return -EOPNOTSUPP;
}
if_id = dpaa2_switch_get_index(ethsw, cls_act->dev);
/* We have a single mirror port but can configure egress mirroring on
* all the other switch ports. We need to allow mirroring rules only
* when the destination port is the same.
*/
if (mirror_port_enabled && ethsw->mirror_port != if_id) {
NL_SET_ERR_MSG_MOD(extack,
"Multiple mirror ports not supported");
return -EBUSY;
}
/* Parse the key */
err = dpaa2_switch_flower_parse_mirror_key(cls, &vlan);
if (err)
return err;
/* Make sure that we don't already have a mirror rule with the same
* configuration.
*/
list_for_each_safe(pos, n, &block->mirror_entries) {
tmp = list_entry(pos, struct dpaa2_switch_mirror_entry, list);
if (tmp->cfg.filter == DPSW_REFLECTION_FILTER_INGRESS_VLAN &&
tmp->cfg.vlan_id == vlan) {
NL_SET_ERR_MSG_MOD(extack,
"VLAN mirror filter already installed");
return -EBUSY;
}
}
mirror_entry = kzalloc_obj(*mirror_entry);
if (!mirror_entry)
return -ENOMEM;
mirror_entry->cfg.filter = DPSW_REFLECTION_FILTER_INGRESS_VLAN;
mirror_entry->cfg.vlan_id = vlan;
mirror_entry->cookie = cls->cookie;
return dpaa2_switch_block_add_mirror(block, mirror_entry, if_id,
extack);
}
int dpaa2_switch_cls_flower_replace(struct dpaa2_switch_filter_block *block,
struct flow_cls_offload *cls)
{
struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
struct netlink_ext_ack *extack = cls->common.extack;
struct flow_action_entry *act;
if (!flow_offload_has_one_action(&rule->action)) {
NL_SET_ERR_MSG(extack, "Only singular actions are supported");
return -EOPNOTSUPP;
}
act = &rule->action.entries[0];
switch (act->id) {
case FLOW_ACTION_REDIRECT:
case FLOW_ACTION_TRAP:
case FLOW_ACTION_DROP:
return dpaa2_switch_cls_flower_replace_acl(block, cls);
case FLOW_ACTION_MIRRED:
return dpaa2_switch_cls_flower_replace_mirror(block, cls);
default:
NL_SET_ERR_MSG_MOD(extack, "Action not supported");
return -EOPNOTSUPP;
}
}
int dpaa2_switch_cls_flower_destroy(struct dpaa2_switch_filter_block *block,
struct flow_cls_offload *cls)
{
struct dpaa2_switch_mirror_entry *mirror_entry;
struct dpaa2_switch_acl_entry *acl_entry;
/* If this filter is a an ACL one, remove it */
acl_entry = dpaa2_switch_acl_tbl_find_entry_by_cookie(block,
cls->cookie);
if (acl_entry)
return dpaa2_switch_acl_tbl_remove_entry(block, acl_entry);
/* If not, then it has to be a mirror */
mirror_entry = dpaa2_switch_mirror_find_entry_by_cookie(block,
cls->cookie);
if (mirror_entry)
return dpaa2_switch_block_remove_mirror(block,
mirror_entry);
return 0;
}
static int
dpaa2_switch_cls_matchall_replace_acl(struct dpaa2_switch_filter_block *block,
struct tc_cls_matchall_offload *cls)
{
struct netlink_ext_ack *extack = cls->common.extack;
struct ethsw_core *ethsw = block->ethsw;
struct dpaa2_switch_acl_entry *acl_entry;
struct flow_action_entry *act;
int err;
if (dpaa2_switch_acl_tbl_is_full(block)) {
NL_SET_ERR_MSG(extack, "Maximum filter capacity reached");
return -ENOMEM;
}
acl_entry = kzalloc_obj(*acl_entry);
if (!acl_entry)
return -ENOMEM;
act = &cls->rule->action.entries[0];
err = dpaa2_switch_tc_parse_action_acl(ethsw, act,
&acl_entry->cfg.result, extack);
if (err)
goto free_acl_entry;
acl_entry->prio = cls->common.prio;
acl_entry->cookie = cls->cookie;
err = dpaa2_switch_acl_tbl_add_entry(block, acl_entry);
if (err)
goto free_acl_entry;
return 0;
free_acl_entry:
kfree(acl_entry);
return err;
}
static int
dpaa2_switch_cls_matchall_replace_mirror(struct dpaa2_switch_filter_block *block,
struct tc_cls_matchall_offload *cls)
{
struct netlink_ext_ack *extack = cls->common.extack;
struct dpaa2_switch_mirror_entry *mirror_entry;
struct ethsw_core *ethsw = block->ethsw;
struct dpaa2_switch_mirror_entry *tmp;
struct flow_action_entry *cls_act;
struct list_head *pos, *n;
bool mirror_port_enabled;
u16 if_id;
mirror_port_enabled = (ethsw->mirror_port != ethsw->sw_attr.num_ifs);
cls_act = &cls->rule->action.entries[0];
/* Offload rules only when the destination is a DPAA2 switch port */
if (!dpaa2_switch_port_dev_check(cls_act->dev)) {
NL_SET_ERR_MSG_MOD(extack,
"Destination not a DPAA2 switch port");
return -EOPNOTSUPP;
}
if_id = dpaa2_switch_get_index(ethsw, cls_act->dev);
/* We have a single mirror port but can configure egress mirroring on
* all the other switch ports. We need to allow mirroring rules only
* when the destination port is the same.
*/
if (mirror_port_enabled && ethsw->mirror_port != if_id) {
NL_SET_ERR_MSG_MOD(extack,
"Multiple mirror ports not supported");
return -EBUSY;
}
/* Make sure that we don't already have a mirror rule with the same
* configuration. One matchall rule per block is the maximum.
*/
list_for_each_safe(pos, n, &block->mirror_entries) {
tmp = list_entry(pos, struct dpaa2_switch_mirror_entry, list);
if (tmp->cfg.filter == DPSW_REFLECTION_FILTER_INGRESS_ALL) {
NL_SET_ERR_MSG_MOD(extack,
"Matchall mirror filter already installed");
return -EBUSY;
}
}
mirror_entry = kzalloc_obj(*mirror_entry);
if (!mirror_entry)
return -ENOMEM;
mirror_entry->cfg.filter = DPSW_REFLECTION_FILTER_INGRESS_ALL;
mirror_entry->cookie = cls->cookie;
return dpaa2_switch_block_add_mirror(block, mirror_entry, if_id,
extack);
}
int dpaa2_switch_cls_matchall_replace(struct dpaa2_switch_filter_block *block,
struct tc_cls_matchall_offload *cls)
{
struct netlink_ext_ack *extack = cls->common.extack;
struct flow_action_entry *act;
if (!flow_offload_has_one_action(&cls->rule->action)) {
NL_SET_ERR_MSG(extack, "Only singular actions are supported");
return -EOPNOTSUPP;
}
act = &cls->rule->action.entries[0];
switch (act->id) {
case FLOW_ACTION_REDIRECT:
case FLOW_ACTION_TRAP:
case FLOW_ACTION_DROP:
return dpaa2_switch_cls_matchall_replace_acl(block, cls);
case FLOW_ACTION_MIRRED:
return dpaa2_switch_cls_matchall_replace_mirror(block, cls);
default:
NL_SET_ERR_MSG_MOD(extack, "Action not supported");
return -EOPNOTSUPP;
}
}
int dpaa2_switch_block_offload_mirror(struct dpaa2_switch_filter_block *block,
struct ethsw_port_priv *port_priv)
{
struct ethsw_core *ethsw = port_priv->ethsw_data;
struct dpaa2_switch_mirror_entry *tmp;
int err;
list_for_each_entry(tmp, &block->mirror_entries, list) {
err = dpsw_if_add_reflection(ethsw->mc_io, 0,
ethsw->dpsw_handle,
port_priv->idx, &tmp->cfg);
if (err)
goto unwind_add;
}
return 0;
unwind_add:
list_for_each_entry(tmp, &block->mirror_entries, list)
dpsw_if_remove_reflection(ethsw->mc_io, 0,
ethsw->dpsw_handle,
port_priv->idx, &tmp->cfg);
return err;
}
int dpaa2_switch_block_unoffload_mirror(struct dpaa2_switch_filter_block *block,
struct ethsw_port_priv *port_priv)
{
struct ethsw_core *ethsw = port_priv->ethsw_data;
struct dpaa2_switch_mirror_entry *tmp;
int err;
list_for_each_entry(tmp, &block->mirror_entries, list) {
err = dpsw_if_remove_reflection(ethsw->mc_io, 0,
ethsw->dpsw_handle,
port_priv->idx, &tmp->cfg);
if (err)
goto unwind_remove;
}
return 0;
unwind_remove:
list_for_each_entry(tmp, &block->mirror_entries, list)
dpsw_if_add_reflection(ethsw->mc_io, 0, ethsw->dpsw_handle,
port_priv->idx, &tmp->cfg);
return err;
}
int dpaa2_switch_cls_matchall_destroy(struct dpaa2_switch_filter_block *block,
struct tc_cls_matchall_offload *cls)
{
struct dpaa2_switch_mirror_entry *mirror_entry;
struct dpaa2_switch_acl_entry *acl_entry;
/* If this filter is a an ACL one, remove it */
acl_entry = dpaa2_switch_acl_tbl_find_entry_by_cookie(block,
cls->cookie);
if (acl_entry)
return dpaa2_switch_acl_tbl_remove_entry(block,
acl_entry);
/* If not, then it has to be a mirror */
mirror_entry = dpaa2_switch_mirror_find_entry_by_cookie(block,
cls->cookie);
if (mirror_entry)
return dpaa2_switch_block_remove_mirror(block,
mirror_entry);
return 0;
}
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c
+3660
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.h
+277
View File
@@ -0,0 +1,277 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* DPAA2 Ethernet Switch declarations
*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2017-2021 NXP
*
*/
#ifndef __ETHSW_H
#define __ETHSW_H
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/rtnetlink.h>
#include <linux/if_vlan.h>
#include <uapi/linux/if_bridge.h>
#include <net/switchdev.h>
#include <linux/if_bridge.h>
#include <linux/fsl/mc.h>
#include <net/pkt_cls.h>
#include <soc/fsl/dpaa2-io.h>
#include "dpaa2-mac.h"
#include "dpsw.h"
/* Number of IRQs supported */
#define DPSW_IRQ_NUM 2
/* Port is member of VLAN */
#define ETHSW_VLAN_MEMBER 1
/* VLAN to be treated as untagged on egress */
#define ETHSW_VLAN_UNTAGGED 2
/* Untagged frames will be assigned to this VLAN */
#define ETHSW_VLAN_PVID 4
/* VLAN configured on the switch */
#define ETHSW_VLAN_GLOBAL 8
/* Maximum Frame Length supported by HW (currently 10k) */
#define DPAA2_MFL (10 * 1024)
#define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
#define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
#define ETHSW_FEATURE_MAC_ADDR BIT(0)
/* Number of receive queues (one RX and one TX_CONF) */
#define DPAA2_SWITCH_RX_NUM_FQS 2
/* Hardware requires alignment for ingress/egress buffer addresses */
#define DPAA2_SWITCH_RX_BUF_RAW_SIZE PAGE_SIZE
#define DPAA2_SWITCH_RX_BUF_TAILROOM \
SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
#define DPAA2_SWITCH_RX_BUF_SIZE \
(DPAA2_SWITCH_RX_BUF_RAW_SIZE - DPAA2_SWITCH_RX_BUF_TAILROOM)
#define DPAA2_SWITCH_STORE_SIZE 16
/* Buffer management */
#define BUFS_PER_CMD 7
#define DPAA2_ETHSW_NUM_BUFS (1024 * BUFS_PER_CMD)
#define DPAA2_ETHSW_REFILL_THRESH (DPAA2_ETHSW_NUM_BUFS * 5 / 6)
/* Number of times to retry DPIO portal operations while waiting
* for portal to finish executing current command and become
* available. We want to avoid being stuck in a while loop in case
* hardware becomes unresponsive, but not give up too easily if
* the portal really is busy for valid reasons
*/
#define DPAA2_SWITCH_SWP_BUSY_RETRIES 1000
/* Hardware annotation buffer size */
#define DPAA2_SWITCH_HWA_SIZE 64
/* Software annotation buffer size */
#define DPAA2_SWITCH_SWA_SIZE 64
#define DPAA2_SWITCH_TX_BUF_ALIGN 64
#define DPAA2_SWITCH_TX_DATA_OFFSET \
(DPAA2_SWITCH_HWA_SIZE + DPAA2_SWITCH_SWA_SIZE)
#define DPAA2_SWITCH_NEEDED_HEADROOM \
(DPAA2_SWITCH_TX_DATA_OFFSET + DPAA2_SWITCH_TX_BUF_ALIGN)
#define DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES 16
#define DPAA2_ETHSW_PORT_DEFAULT_TRAPS 1
#define DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE 256
extern const struct ethtool_ops dpaa2_switch_port_ethtool_ops;
struct ethsw_core;
struct dpaa2_switch_fq {
struct ethsw_core *ethsw;
enum dpsw_queue_type type;
struct dpaa2_io_store *store;
struct dpaa2_io_notification_ctx nctx;
struct napi_struct napi;
u32 fqid;
};
struct dpaa2_switch_fdb {
struct net_device *bridge_dev;
u16 fdb_id;
bool in_use;
};
struct dpaa2_switch_acl_entry {
struct list_head list;
u16 prio;
unsigned long cookie;
struct dpsw_acl_entry_cfg cfg;
struct dpsw_acl_key key;
};
struct dpaa2_switch_mirror_entry {
struct list_head list;
struct dpsw_reflection_cfg cfg;
unsigned long cookie;
u16 if_id;
};
struct dpaa2_switch_filter_block {
struct ethsw_core *ethsw;
u64 ports;
bool in_use;
struct list_head acl_entries;
u16 acl_id;
u8 num_acl_rules;
struct list_head mirror_entries;
};
static inline bool
dpaa2_switch_acl_tbl_is_full(struct dpaa2_switch_filter_block *filter_block)
{
if ((filter_block->num_acl_rules + DPAA2_ETHSW_PORT_DEFAULT_TRAPS) >=
DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES)
return true;
return false;
}
/* Per port private data */
struct ethsw_port_priv {
struct net_device *netdev;
u16 idx;
struct ethsw_core *ethsw_data;
u8 link_state;
u8 stp_state;
u8 vlans[VLAN_VID_MASK + 1];
u16 pvid;
u16 tx_qdid;
struct dpaa2_switch_fdb *fdb;
bool bcast_flood;
bool ucast_flood;
bool learn_ena;
struct dpaa2_switch_filter_block *filter_block;
struct dpaa2_mac *mac;
/* Protects against changes to port_priv->mac */
struct mutex mac_lock;
};
/* Switch data */
struct ethsw_core {
struct device *dev;
struct fsl_mc_io *mc_io;
u16 dpsw_handle;
struct dpsw_attr sw_attr;
u16 major, minor;
unsigned long features;
int dev_id;
struct ethsw_port_priv **ports;
struct iommu_domain *iommu_domain;
u8 vlans[VLAN_VID_MASK + 1];
struct workqueue_struct *workqueue;
struct dpaa2_switch_fq fq[DPAA2_SWITCH_RX_NUM_FQS];
struct fsl_mc_device *dpbp_dev;
int buf_count;
u16 bpid;
int napi_users;
struct dpaa2_switch_fdb *fdbs;
struct dpaa2_switch_filter_block *filter_blocks;
u16 mirror_port;
};
static inline int dpaa2_switch_get_index(struct ethsw_core *ethsw,
struct net_device *netdev)
{
int i;
for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
if (ethsw->ports[i]->netdev == netdev)
return ethsw->ports[i]->idx;
return -EINVAL;
}
static inline bool dpaa2_switch_supports_cpu_traffic(struct ethsw_core *ethsw)
{
if (ethsw->sw_attr.options & DPSW_OPT_CTRL_IF_DIS) {
dev_err(ethsw->dev, "Control Interface is disabled, cannot probe\n");
return false;
}
if (ethsw->sw_attr.flooding_cfg != DPSW_FLOODING_PER_FDB) {
dev_err(ethsw->dev, "Flooding domain is not per FDB, cannot probe\n");
return false;
}
if (ethsw->sw_attr.broadcast_cfg != DPSW_BROADCAST_PER_FDB) {
dev_err(ethsw->dev, "Broadcast domain is not per FDB, cannot probe\n");
return false;
}
if (ethsw->sw_attr.max_fdbs < ethsw->sw_attr.num_ifs) {
dev_err(ethsw->dev, "The number of FDBs is lower than the number of ports, cannot probe\n");
return false;
}
return true;
}
static inline bool
dpaa2_switch_port_is_type_phy(struct ethsw_port_priv *port_priv)
{
return dpaa2_mac_is_type_phy(port_priv->mac);
}
static inline bool dpaa2_switch_port_has_mac(struct ethsw_port_priv *port_priv)
{
return port_priv->mac ? true : false;
}
bool dpaa2_switch_port_dev_check(const struct net_device *netdev);
int dpaa2_switch_port_vlans_add(struct net_device *netdev,
const struct switchdev_obj_port_vlan *vlan);
int dpaa2_switch_port_vlans_del(struct net_device *netdev,
const struct switchdev_obj_port_vlan *vlan);
typedef int dpaa2_switch_fdb_cb_t(struct ethsw_port_priv *port_priv,
struct fdb_dump_entry *fdb_entry,
void *data);
/* TC offload */
int dpaa2_switch_cls_flower_replace(struct dpaa2_switch_filter_block *block,
struct flow_cls_offload *cls);
int dpaa2_switch_cls_flower_destroy(struct dpaa2_switch_filter_block *block,
struct flow_cls_offload *cls);
int dpaa2_switch_cls_matchall_replace(struct dpaa2_switch_filter_block *block,
struct tc_cls_matchall_offload *cls);
int dpaa2_switch_cls_matchall_destroy(struct dpaa2_switch_filter_block *block,
struct tc_cls_matchall_offload *cls);
int dpaa2_switch_acl_entry_add(struct dpaa2_switch_filter_block *block,
struct dpaa2_switch_acl_entry *entry);
int dpaa2_switch_block_offload_mirror(struct dpaa2_switch_filter_block *block,
struct ethsw_port_priv *port_priv);
int dpaa2_switch_block_unoffload_mirror(struct dpaa2_switch_filter_block *block,
struct ethsw_port_priv *port_priv);
#endif /* __ETHSW_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpaa2-xsk.c
+452
View File
@@ -0,0 +1,452 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2022 NXP
*/
#include <linux/filter.h>
#include <linux/compiler.h>
#include <linux/bpf_trace.h>
#include <net/xdp.h>
#include <net/xdp_sock_drv.h>
#include "dpaa2-eth.h"
static void dpaa2_eth_setup_consume_func(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
enum dpaa2_eth_fq_type type,
dpaa2_eth_consume_cb_t *consume)
{
struct dpaa2_eth_fq *fq;
int i;
for (i = 0; i < priv->num_fqs; i++) {
fq = &priv->fq[i];
if (fq->type != type)
continue;
if (fq->channel != ch)
continue;
fq->consume = consume;
}
}
static u32 dpaa2_xsk_run_xdp(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_eth_fq *rx_fq,
struct dpaa2_fd *fd, void *vaddr)
{
dma_addr_t addr = dpaa2_fd_get_addr(fd);
struct bpf_prog *xdp_prog;
struct xdp_buff *xdp_buff;
struct dpaa2_eth_swa *swa;
u32 xdp_act = XDP_PASS;
int err;
xdp_prog = READ_ONCE(ch->xdp.prog);
if (!xdp_prog)
goto out;
swa = (struct dpaa2_eth_swa *)(vaddr + DPAA2_ETH_RX_HWA_SIZE +
ch->xsk_pool->umem->headroom);
xdp_buff = swa->xsk.xdp_buff;
xdp_buff->data_hard_start = vaddr;
xdp_buff->data = vaddr + dpaa2_fd_get_offset(fd);
xdp_buff->data_end = xdp_buff->data + dpaa2_fd_get_len(fd);
xdp_set_data_meta_invalid(xdp_buff);
xdp_buff->rxq = &ch->xdp_rxq;
xsk_buff_dma_sync_for_cpu(xdp_buff);
xdp_act = bpf_prog_run_xdp(xdp_prog, xdp_buff);
/* xdp.data pointer may have changed */
dpaa2_fd_set_offset(fd, xdp_buff->data - vaddr);
dpaa2_fd_set_len(fd, xdp_buff->data_end - xdp_buff->data);
if (likely(xdp_act == XDP_REDIRECT)) {
err = xdp_do_redirect(priv->net_dev, xdp_buff, xdp_prog);
if (unlikely(err)) {
ch->stats.xdp_drop++;
dpaa2_eth_recycle_buf(priv, ch, addr);
} else {
ch->buf_count--;
ch->stats.xdp_redirect++;
}
goto xdp_redir;
}
switch (xdp_act) {
case XDP_PASS:
break;
case XDP_TX:
dpaa2_eth_xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
break;
default:
bpf_warn_invalid_xdp_action(priv->net_dev, xdp_prog, xdp_act);
fallthrough;
case XDP_ABORTED:
trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
fallthrough;
case XDP_DROP:
dpaa2_eth_recycle_buf(priv, ch, addr);
ch->stats.xdp_drop++;
break;
}
xdp_redir:
ch->xdp.res |= xdp_act;
out:
return xdp_act;
}
/* Rx frame processing routine for the AF_XDP fast path */
static void dpaa2_xsk_rx(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
struct dpaa2_eth_fq *fq)
{
dma_addr_t addr = dpaa2_fd_get_addr(fd);
u8 fd_format = dpaa2_fd_get_format(fd);
struct rtnl_link_stats64 *percpu_stats;
u32 fd_length = dpaa2_fd_get_len(fd);
struct sk_buff *skb;
void *vaddr;
u32 xdp_act;
trace_dpaa2_rx_xsk_fd(priv->net_dev, fd);
vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
percpu_stats = this_cpu_ptr(priv->percpu_stats);
if (fd_format != dpaa2_fd_single) {
WARN_ON(priv->xdp_prog);
/* AF_XDP doesn't support any other formats */
goto err_frame_format;
}
xdp_act = dpaa2_xsk_run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
if (xdp_act != XDP_PASS) {
percpu_stats->rx_packets++;
percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
return;
}
/* Build skb */
skb = dpaa2_eth_alloc_skb(priv, ch, fd, fd_length, vaddr);
if (!skb)
/* Nothing else we can do, recycle the buffer and
* drop the frame.
*/
goto err_alloc_skb;
/* Send the skb to the Linux networking stack */
dpaa2_eth_receive_skb(priv, ch, fd, vaddr, fq, percpu_stats, skb);
return;
err_alloc_skb:
dpaa2_eth_recycle_buf(priv, ch, addr);
err_frame_format:
percpu_stats->rx_dropped++;
}
static void dpaa2_xsk_set_bp_per_qdbin(struct dpaa2_eth_priv *priv,
struct dpni_pools_cfg *pools_params)
{
int curr_bp = 0, i, j;
pools_params->pool_options = DPNI_POOL_ASSOC_QDBIN;
for (i = 0; i < priv->num_bps; i++) {
for (j = 0; j < priv->num_channels; j++)
if (priv->bp[i] == priv->channel[j]->bp)
pools_params->pools[curr_bp].priority_mask |= (1 << j);
if (!pools_params->pools[curr_bp].priority_mask)
continue;
pools_params->pools[curr_bp].dpbp_id = priv->bp[i]->bpid;
pools_params->pools[curr_bp].buffer_size = priv->rx_buf_size;
pools_params->pools[curr_bp++].backup_pool = 0;
}
pools_params->num_dpbp = curr_bp;
}
static int dpaa2_xsk_disable_pool(struct net_device *dev, u16 qid)
{
struct xsk_buff_pool *pool = xsk_get_pool_from_qid(dev, qid);
struct dpaa2_eth_priv *priv = netdev_priv(dev);
struct dpni_pools_cfg pools_params = { 0 };
struct dpaa2_eth_channel *ch;
int err;
bool up;
ch = priv->channel[qid];
if (!ch->xsk_pool)
return -EINVAL;
up = netif_running(dev);
if (up)
dev_close(dev);
xsk_pool_dma_unmap(pool, 0);
err = xdp_rxq_info_reg_mem_model(&ch->xdp_rxq,
MEM_TYPE_PAGE_ORDER0, NULL);
if (err)
netdev_err(dev, "xsk_rxq_info_reg_mem_model() failed (err = %d)\n",
err);
dpaa2_eth_free_dpbp(priv, ch->bp);
ch->xsk_zc = false;
ch->xsk_pool = NULL;
ch->xsk_tx_pkts_sent = 0;
ch->bp = priv->bp[DPAA2_ETH_DEFAULT_BP_IDX];
dpaa2_eth_setup_consume_func(priv, ch, DPAA2_RX_FQ, dpaa2_eth_rx);
dpaa2_xsk_set_bp_per_qdbin(priv, &pools_params);
err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
if (err)
netdev_err(dev, "dpni_set_pools() failed\n");
if (up) {
err = dev_open(dev, NULL);
if (err)
return err;
}
return 0;
}
static int dpaa2_xsk_enable_pool(struct net_device *dev,
struct xsk_buff_pool *pool,
u16 qid)
{
struct dpaa2_eth_priv *priv = netdev_priv(dev);
struct dpni_pools_cfg pools_params = { 0 };
struct dpaa2_eth_channel *ch;
int err, err2;
bool up;
if (priv->dpni_attrs.wriop_version < DPAA2_WRIOP_VERSION(3, 0, 0)) {
netdev_err(dev, "AF_XDP zero-copy not supported on devices <= WRIOP(3, 0, 0)\n");
return -EOPNOTSUPP;
}
if (priv->dpni_attrs.num_queues > 8) {
netdev_err(dev, "AF_XDP zero-copy not supported on DPNI with more then 8 queues\n");
return -EOPNOTSUPP;
}
up = netif_running(dev);
if (up)
dev_close(dev);
err = xsk_pool_dma_map(pool, priv->net_dev->dev.parent, 0);
if (err) {
netdev_err(dev, "xsk_pool_dma_map() failed (err = %d)\n",
err);
goto err_dma_unmap;
}
ch = priv->channel[qid];
err = xdp_rxq_info_reg_mem_model(&ch->xdp_rxq, MEM_TYPE_XSK_BUFF_POOL, NULL);
if (err) {
netdev_err(dev, "xdp_rxq_info_reg_mem_model() failed (err = %d)\n", err);
goto err_mem_model;
}
xsk_pool_set_rxq_info(pool, &ch->xdp_rxq);
priv->bp[priv->num_bps] = dpaa2_eth_allocate_dpbp(priv);
if (IS_ERR(priv->bp[priv->num_bps])) {
err = PTR_ERR(priv->bp[priv->num_bps]);
goto err_bp_alloc;
}
ch->xsk_zc = true;
ch->xsk_pool = pool;
ch->bp = priv->bp[priv->num_bps++];
dpaa2_eth_setup_consume_func(priv, ch, DPAA2_RX_FQ, dpaa2_xsk_rx);
dpaa2_xsk_set_bp_per_qdbin(priv, &pools_params);
err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
if (err) {
netdev_err(dev, "dpni_set_pools() failed\n");
goto err_set_pools;
}
if (up) {
err = dev_open(dev, NULL);
if (err)
return err;
}
return 0;
err_set_pools:
err2 = dpaa2_xsk_disable_pool(dev, qid);
if (err2)
netdev_err(dev, "dpaa2_xsk_disable_pool() failed %d\n", err2);
err_bp_alloc:
err2 = xdp_rxq_info_reg_mem_model(&priv->channel[qid]->xdp_rxq,
MEM_TYPE_PAGE_ORDER0, NULL);
if (err2)
netdev_err(dev, "xsk_rxq_info_reg_mem_model() failed with %d)\n", err2);
err_mem_model:
xsk_pool_dma_unmap(pool, 0);
err_dma_unmap:
if (up)
dev_open(dev, NULL);
return err;
}
int dpaa2_xsk_setup_pool(struct net_device *dev, struct xsk_buff_pool *pool, u16 qid)
{
return pool ? dpaa2_xsk_enable_pool(dev, pool, qid) :
dpaa2_xsk_disable_pool(dev, qid);
}
int dpaa2_xsk_wakeup(struct net_device *dev, u32 qid, u32 flags)
{
struct dpaa2_eth_priv *priv = netdev_priv(dev);
struct dpaa2_eth_channel *ch = priv->channel[qid];
if (!priv->link_state.up)
return -ENETDOWN;
if (!priv->xdp_prog)
return -EINVAL;
if (!ch->xsk_zc)
return -EINVAL;
/* We do not have access to a per channel SW interrupt, so instead we
* schedule a NAPI instance.
*/
if (!napi_if_scheduled_mark_missed(&ch->napi))
napi_schedule(&ch->napi);
return 0;
}
static int dpaa2_xsk_tx_build_fd(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_fd *fd,
struct xdp_desc *xdp_desc)
{
struct device *dev = priv->net_dev->dev.parent;
struct dpaa2_sg_entry *sgt;
struct dpaa2_eth_swa *swa;
void *sgt_buf = NULL;
dma_addr_t sgt_addr;
int sgt_buf_size;
dma_addr_t addr;
int err = 0;
/* Prepare the HW SGT structure */
sgt_buf_size = priv->tx_data_offset + sizeof(struct dpaa2_sg_entry);
sgt_buf = dpaa2_eth_sgt_get(priv);
if (unlikely(!sgt_buf))
return -ENOMEM;
sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
/* Get the address of the XSK Tx buffer */
addr = xsk_buff_raw_get_dma(ch->xsk_pool, xdp_desc->addr);
xsk_buff_raw_dma_sync_for_device(ch->xsk_pool, addr, xdp_desc->len);
/* Fill in the HW SGT structure */
dpaa2_sg_set_addr(sgt, addr);
dpaa2_sg_set_len(sgt, xdp_desc->len);
dpaa2_sg_set_final(sgt, true);
/* Store the necessary info in the SGT buffer */
swa = (struct dpaa2_eth_swa *)sgt_buf;
swa->type = DPAA2_ETH_SWA_XSK;
swa->xsk.sgt_size = sgt_buf_size;
/* Separately map the SGT buffer */
sgt_addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
if (unlikely(dma_mapping_error(dev, sgt_addr))) {
err = -ENOMEM;
goto sgt_map_failed;
}
/* Initialize FD fields */
memset(fd, 0, sizeof(struct dpaa2_fd));
dpaa2_fd_set_offset(fd, priv->tx_data_offset);
dpaa2_fd_set_format(fd, dpaa2_fd_sg);
dpaa2_fd_set_addr(fd, sgt_addr);
dpaa2_fd_set_len(fd, xdp_desc->len);
dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
return 0;
sgt_map_failed:
dpaa2_eth_sgt_recycle(priv, sgt_buf);
return err;
}
bool dpaa2_xsk_tx(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch)
{
struct xdp_desc *xdp_descs = ch->xsk_pool->tx_descs;
struct dpaa2_eth_drv_stats *percpu_extras;
struct rtnl_link_stats64 *percpu_stats;
int budget = DPAA2_ETH_TX_ZC_PER_NAPI;
int total_enqueued, enqueued;
int retries, max_retries;
struct dpaa2_eth_fq *fq;
struct dpaa2_fd *fds;
int batch, i, err;
percpu_stats = this_cpu_ptr(priv->percpu_stats);
percpu_extras = this_cpu_ptr(priv->percpu_extras);
fds = (this_cpu_ptr(priv->fd))->array;
/* Use the FQ with the same idx as the affine CPU */
fq = &priv->fq[ch->nctx.desired_cpu];
batch = xsk_tx_peek_release_desc_batch(ch->xsk_pool, budget);
if (!batch)
return false;
/* Create a FD for each XSK frame to be sent */
for (i = 0; i < batch; i++) {
err = dpaa2_xsk_tx_build_fd(priv, ch, &fds[i], &xdp_descs[i]);
if (err) {
batch = i;
break;
}
trace_dpaa2_tx_xsk_fd(priv->net_dev, &fds[i]);
}
/* Enqueue all the created FDs */
max_retries = batch * DPAA2_ETH_ENQUEUE_RETRIES;
total_enqueued = 0;
enqueued = 0;
retries = 0;
while (total_enqueued < batch && retries < max_retries) {
err = priv->enqueue(priv, fq, &fds[total_enqueued], 0,
batch - total_enqueued, &enqueued);
if (err == -EBUSY) {
retries++;
continue;
}
total_enqueued += enqueued;
}
percpu_extras->tx_portal_busy += retries;
/* Update statistics */
percpu_stats->tx_packets += total_enqueued;
for (i = 0; i < total_enqueued; i++)
percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
for (i = total_enqueued; i < batch; i++) {
dpaa2_eth_free_tx_fd(priv, ch, fq, &fds[i], false);
percpu_stats->tx_errors++;
}
return total_enqueued == budget;
}
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpkg.h
+481
View File
@@ -0,0 +1,481 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2013-2015 Freescale Semiconductor Inc.
*/
#ifndef __FSL_DPKG_H_
#define __FSL_DPKG_H_
#include <linux/types.h>
/* Data Path Key Generator API
* Contains initialization APIs and runtime APIs for the Key Generator
*/
/** Key Generator properties */
/**
* DPKG_NUM_OF_MASKS - Number of masks per key extraction
*/
#define DPKG_NUM_OF_MASKS 4
/**
* DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
*/
#define DPKG_MAX_NUM_OF_EXTRACTS 10
/**
* enum dpkg_extract_from_hdr_type - Selecting extraction by header types
* @DPKG_FROM_HDR: Extract selected bytes from header, by offset
* @DPKG_FROM_FIELD: Extract selected bytes from header, by offset from field
* @DPKG_FULL_FIELD: Extract a full field
*/
enum dpkg_extract_from_hdr_type {
DPKG_FROM_HDR = 0,
DPKG_FROM_FIELD = 1,
DPKG_FULL_FIELD = 2
};
/**
* enum dpkg_extract_type - Enumeration for selecting extraction type
* @DPKG_EXTRACT_FROM_HDR: Extract from the header
* @DPKG_EXTRACT_FROM_DATA: Extract from data not in specific header
* @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
* e.g. can be used to extract header existence;
* please refer to 'Parse Result definition' section in the parser BG
*/
enum dpkg_extract_type {
DPKG_EXTRACT_FROM_HDR = 0,
DPKG_EXTRACT_FROM_DATA = 1,
DPKG_EXTRACT_FROM_PARSE = 3
};
/**
* struct dpkg_mask - A structure for defining a single extraction mask
* @mask: Byte mask for the extracted content
* @offset: Offset within the extracted content
*/
struct dpkg_mask {
u8 mask;
u8 offset;
};
/* Protocol fields */
/* Ethernet fields */
#define NH_FLD_ETH_DA BIT(0)
#define NH_FLD_ETH_SA BIT(1)
#define NH_FLD_ETH_LENGTH BIT(2)
#define NH_FLD_ETH_TYPE BIT(3)
#define NH_FLD_ETH_FINAL_CKSUM BIT(4)
#define NH_FLD_ETH_PADDING BIT(5)
#define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1)
/* VLAN fields */
#define NH_FLD_VLAN_VPRI BIT(0)
#define NH_FLD_VLAN_CFI BIT(1)
#define NH_FLD_VLAN_VID BIT(2)
#define NH_FLD_VLAN_LENGTH BIT(3)
#define NH_FLD_VLAN_TYPE BIT(4)
#define NH_FLD_VLAN_ALL_FIELDS (BIT(5) - 1)
#define NH_FLD_VLAN_TCI (NH_FLD_VLAN_VPRI | \
NH_FLD_VLAN_CFI | \
NH_FLD_VLAN_VID)
/* IP (generic) fields */
#define NH_FLD_IP_VER BIT(0)
#define NH_FLD_IP_DSCP BIT(2)
#define NH_FLD_IP_ECN BIT(3)
#define NH_FLD_IP_PROTO BIT(4)
#define NH_FLD_IP_SRC BIT(5)
#define NH_FLD_IP_DST BIT(6)
#define NH_FLD_IP_TOS_TC BIT(7)
#define NH_FLD_IP_ID BIT(8)
#define NH_FLD_IP_ALL_FIELDS (BIT(9) - 1)
/* IPV4 fields */
#define NH_FLD_IPV4_VER BIT(0)
#define NH_FLD_IPV4_HDR_LEN BIT(1)
#define NH_FLD_IPV4_TOS BIT(2)
#define NH_FLD_IPV4_TOTAL_LEN BIT(3)
#define NH_FLD_IPV4_ID BIT(4)
#define NH_FLD_IPV4_FLAG_D BIT(5)
#define NH_FLD_IPV4_FLAG_M BIT(6)
#define NH_FLD_IPV4_OFFSET BIT(7)
#define NH_FLD_IPV4_TTL BIT(8)
#define NH_FLD_IPV4_PROTO BIT(9)
#define NH_FLD_IPV4_CKSUM BIT(10)
#define NH_FLD_IPV4_SRC_IP BIT(11)
#define NH_FLD_IPV4_DST_IP BIT(12)
#define NH_FLD_IPV4_OPTS BIT(13)
#define NH_FLD_IPV4_OPTS_COUNT BIT(14)
#define NH_FLD_IPV4_ALL_FIELDS (BIT(15) - 1)
/* IPV6 fields */
#define NH_FLD_IPV6_VER BIT(0)
#define NH_FLD_IPV6_TC BIT(1)
#define NH_FLD_IPV6_SRC_IP BIT(2)
#define NH_FLD_IPV6_DST_IP BIT(3)
#define NH_FLD_IPV6_NEXT_HDR BIT(4)
#define NH_FLD_IPV6_FL BIT(5)
#define NH_FLD_IPV6_HOP_LIMIT BIT(6)
#define NH_FLD_IPV6_ID BIT(7)
#define NH_FLD_IPV6_ALL_FIELDS (BIT(8) - 1)
/* ICMP fields */
#define NH_FLD_ICMP_TYPE BIT(0)
#define NH_FLD_ICMP_CODE BIT(1)
#define NH_FLD_ICMP_CKSUM BIT(2)
#define NH_FLD_ICMP_ID BIT(3)
#define NH_FLD_ICMP_SQ_NUM BIT(4)
#define NH_FLD_ICMP_ALL_FIELDS (BIT(5) - 1)
/* IGMP fields */
#define NH_FLD_IGMP_VERSION BIT(0)
#define NH_FLD_IGMP_TYPE BIT(1)
#define NH_FLD_IGMP_CKSUM BIT(2)
#define NH_FLD_IGMP_DATA BIT(3)
#define NH_FLD_IGMP_ALL_FIELDS (BIT(4) - 1)
/* TCP fields */
#define NH_FLD_TCP_PORT_SRC BIT(0)
#define NH_FLD_TCP_PORT_DST BIT(1)
#define NH_FLD_TCP_SEQ BIT(2)
#define NH_FLD_TCP_ACK BIT(3)
#define NH_FLD_TCP_OFFSET BIT(4)
#define NH_FLD_TCP_FLAGS BIT(5)
#define NH_FLD_TCP_WINDOW BIT(6)
#define NH_FLD_TCP_CKSUM BIT(7)
#define NH_FLD_TCP_URGPTR BIT(8)
#define NH_FLD_TCP_OPTS BIT(9)
#define NH_FLD_TCP_OPTS_COUNT BIT(10)
#define NH_FLD_TCP_ALL_FIELDS (BIT(11) - 1)
/* UDP fields */
#define NH_FLD_UDP_PORT_SRC BIT(0)
#define NH_FLD_UDP_PORT_DST BIT(1)
#define NH_FLD_UDP_LEN BIT(2)
#define NH_FLD_UDP_CKSUM BIT(3)
#define NH_FLD_UDP_ALL_FIELDS (BIT(4) - 1)
/* UDP-lite fields */
#define NH_FLD_UDP_LITE_PORT_SRC BIT(0)
#define NH_FLD_UDP_LITE_PORT_DST BIT(1)
#define NH_FLD_UDP_LITE_ALL_FIELDS (BIT(2) - 1)
/* UDP-encap-ESP fields */
#define NH_FLD_UDP_ENC_ESP_PORT_SRC BIT(0)
#define NH_FLD_UDP_ENC_ESP_PORT_DST BIT(1)
#define NH_FLD_UDP_ENC_ESP_LEN BIT(2)
#define NH_FLD_UDP_ENC_ESP_CKSUM BIT(3)
#define NH_FLD_UDP_ENC_ESP_SPI BIT(4)
#define NH_FLD_UDP_ENC_ESP_SEQUENCE_NUM BIT(5)
#define NH_FLD_UDP_ENC_ESP_ALL_FIELDS (BIT(6) - 1)
/* SCTP fields */
#define NH_FLD_SCTP_PORT_SRC BIT(0)
#define NH_FLD_SCTP_PORT_DST BIT(1)
#define NH_FLD_SCTP_VER_TAG BIT(2)
#define NH_FLD_SCTP_CKSUM BIT(3)
#define NH_FLD_SCTP_ALL_FIELDS (BIT(4) - 1)
/* DCCP fields */
#define NH_FLD_DCCP_PORT_SRC BIT(0)
#define NH_FLD_DCCP_PORT_DST BIT(1)
#define NH_FLD_DCCP_ALL_FIELDS (BIT(2) - 1)
/* IPHC fields */
#define NH_FLD_IPHC_CID BIT(0)
#define NH_FLD_IPHC_CID_TYPE BIT(1)
#define NH_FLD_IPHC_HCINDEX BIT(2)
#define NH_FLD_IPHC_GEN BIT(3)
#define NH_FLD_IPHC_D_BIT BIT(4)
#define NH_FLD_IPHC_ALL_FIELDS (BIT(5) - 1)
/* SCTP fields */
#define NH_FLD_SCTP_CHUNK_DATA_TYPE BIT(0)
#define NH_FLD_SCTP_CHUNK_DATA_FLAGS BIT(1)
#define NH_FLD_SCTP_CHUNK_DATA_LENGTH BIT(2)
#define NH_FLD_SCTP_CHUNK_DATA_TSN BIT(3)
#define NH_FLD_SCTP_CHUNK_DATA_STREAM_ID BIT(4)
#define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN BIT(5)
#define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID BIT(6)
#define NH_FLD_SCTP_CHUNK_DATA_UNORDERED BIT(7)
#define NH_FLD_SCTP_CHUNK_DATA_BEGGINING BIT(8)
#define NH_FLD_SCTP_CHUNK_DATA_END BIT(9)
#define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS (BIT(10) - 1)
/* L2TPV2 fields */
#define NH_FLD_L2TPV2_TYPE_BIT BIT(0)
#define NH_FLD_L2TPV2_LENGTH_BIT BIT(1)
#define NH_FLD_L2TPV2_SEQUENCE_BIT BIT(2)
#define NH_FLD_L2TPV2_OFFSET_BIT BIT(3)
#define NH_FLD_L2TPV2_PRIORITY_BIT BIT(4)
#define NH_FLD_L2TPV2_VERSION BIT(5)
#define NH_FLD_L2TPV2_LEN BIT(6)
#define NH_FLD_L2TPV2_TUNNEL_ID BIT(7)
#define NH_FLD_L2TPV2_SESSION_ID BIT(8)
#define NH_FLD_L2TPV2_NS BIT(9)
#define NH_FLD_L2TPV2_NR BIT(10)
#define NH_FLD_L2TPV2_OFFSET_SIZE BIT(11)
#define NH_FLD_L2TPV2_FIRST_BYTE BIT(12)
#define NH_FLD_L2TPV2_ALL_FIELDS (BIT(13) - 1)
/* L2TPV3 fields */
#define NH_FLD_L2TPV3_CTRL_TYPE_BIT BIT(0)
#define NH_FLD_L2TPV3_CTRL_LENGTH_BIT BIT(1)
#define NH_FLD_L2TPV3_CTRL_SEQUENCE_BIT BIT(2)
#define NH_FLD_L2TPV3_CTRL_VERSION BIT(3)
#define NH_FLD_L2TPV3_CTRL_LENGTH BIT(4)
#define NH_FLD_L2TPV3_CTRL_CONTROL BIT(5)
#define NH_FLD_L2TPV3_CTRL_SENT BIT(6)
#define NH_FLD_L2TPV3_CTRL_RECV BIT(7)
#define NH_FLD_L2TPV3_CTRL_FIRST_BYTE BIT(8)
#define NH_FLD_L2TPV3_CTRL_ALL_FIELDS (BIT(9) - 1)
#define NH_FLD_L2TPV3_SESS_TYPE_BIT BIT(0)
#define NH_FLD_L2TPV3_SESS_VERSION BIT(1)
#define NH_FLD_L2TPV3_SESS_ID BIT(2)
#define NH_FLD_L2TPV3_SESS_COOKIE BIT(3)
#define NH_FLD_L2TPV3_SESS_ALL_FIELDS (BIT(4) - 1)
/* PPP fields */
#define NH_FLD_PPP_PID BIT(0)
#define NH_FLD_PPP_COMPRESSED BIT(1)
#define NH_FLD_PPP_ALL_FIELDS (BIT(2) - 1)
/* PPPoE fields */
#define NH_FLD_PPPOE_VER BIT(0)
#define NH_FLD_PPPOE_TYPE BIT(1)
#define NH_FLD_PPPOE_CODE BIT(2)
#define NH_FLD_PPPOE_SID BIT(3)
#define NH_FLD_PPPOE_LEN BIT(4)
#define NH_FLD_PPPOE_SESSION BIT(5)
#define NH_FLD_PPPOE_PID BIT(6)
#define NH_FLD_PPPOE_ALL_FIELDS (BIT(7) - 1)
/* PPP-Mux fields */
#define NH_FLD_PPPMUX_PID BIT(0)
#define NH_FLD_PPPMUX_CKSUM BIT(1)
#define NH_FLD_PPPMUX_COMPRESSED BIT(2)
#define NH_FLD_PPPMUX_ALL_FIELDS (BIT(3) - 1)
/* PPP-Mux sub-frame fields */
#define NH_FLD_PPPMUX_SUBFRM_PFF BIT(0)
#define NH_FLD_PPPMUX_SUBFRM_LXT BIT(1)
#define NH_FLD_PPPMUX_SUBFRM_LEN BIT(2)
#define NH_FLD_PPPMUX_SUBFRM_PID BIT(3)
#define NH_FLD_PPPMUX_SUBFRM_USE_PID BIT(4)
#define NH_FLD_PPPMUX_SUBFRM_ALL_FIELDS (BIT(5) - 1)
/* LLC fields */
#define NH_FLD_LLC_DSAP BIT(0)
#define NH_FLD_LLC_SSAP BIT(1)
#define NH_FLD_LLC_CTRL BIT(2)
#define NH_FLD_LLC_ALL_FIELDS (BIT(3) - 1)
/* NLPID fields */
#define NH_FLD_NLPID_NLPID BIT(0)
#define NH_FLD_NLPID_ALL_FIELDS (BIT(1) - 1)
/* SNAP fields */
#define NH_FLD_SNAP_OUI BIT(0)
#define NH_FLD_SNAP_PID BIT(1)
#define NH_FLD_SNAP_ALL_FIELDS (BIT(2) - 1)
/* LLC SNAP fields */
#define NH_FLD_LLC_SNAP_TYPE BIT(0)
#define NH_FLD_LLC_SNAP_ALL_FIELDS (BIT(1) - 1)
/* ARP fields */
#define NH_FLD_ARP_HTYPE BIT(0)
#define NH_FLD_ARP_PTYPE BIT(1)
#define NH_FLD_ARP_HLEN BIT(2)
#define NH_FLD_ARP_PLEN BIT(3)
#define NH_FLD_ARP_OPER BIT(4)
#define NH_FLD_ARP_SHA BIT(5)
#define NH_FLD_ARP_SPA BIT(6)
#define NH_FLD_ARP_THA BIT(7)
#define NH_FLD_ARP_TPA BIT(8)
#define NH_FLD_ARP_ALL_FIELDS (BIT(9) - 1)
/* RFC2684 fields */
#define NH_FLD_RFC2684_LLC BIT(0)
#define NH_FLD_RFC2684_NLPID BIT(1)
#define NH_FLD_RFC2684_OUI BIT(2)
#define NH_FLD_RFC2684_PID BIT(3)
#define NH_FLD_RFC2684_VPN_OUI BIT(4)
#define NH_FLD_RFC2684_VPN_IDX BIT(5)
#define NH_FLD_RFC2684_ALL_FIELDS (BIT(6) - 1)
/* User defined fields */
#define NH_FLD_USER_DEFINED_SRCPORT BIT(0)
#define NH_FLD_USER_DEFINED_PCDID BIT(1)
#define NH_FLD_USER_DEFINED_ALL_FIELDS (BIT(2) - 1)
/* Payload fields */
#define NH_FLD_PAYLOAD_BUFFER BIT(0)
#define NH_FLD_PAYLOAD_SIZE BIT(1)
#define NH_FLD_MAX_FRM_SIZE BIT(2)
#define NH_FLD_MIN_FRM_SIZE BIT(3)
#define NH_FLD_PAYLOAD_TYPE BIT(4)
#define NH_FLD_FRAME_SIZE BIT(5)
#define NH_FLD_PAYLOAD_ALL_FIELDS (BIT(6) - 1)
/* GRE fields */
#define NH_FLD_GRE_TYPE BIT(0)
#define NH_FLD_GRE_ALL_FIELDS (BIT(1) - 1)
/* MINENCAP fields */
#define NH_FLD_MINENCAP_SRC_IP BIT(0)
#define NH_FLD_MINENCAP_DST_IP BIT(1)
#define NH_FLD_MINENCAP_TYPE BIT(2)
#define NH_FLD_MINENCAP_ALL_FIELDS (BIT(3) - 1)
/* IPSEC AH fields */
#define NH_FLD_IPSEC_AH_SPI BIT(0)
#define NH_FLD_IPSEC_AH_NH BIT(1)
#define NH_FLD_IPSEC_AH_ALL_FIELDS (BIT(2) - 1)
/* IPSEC ESP fields */
#define NH_FLD_IPSEC_ESP_SPI BIT(0)
#define NH_FLD_IPSEC_ESP_SEQUENCE_NUM BIT(1)
#define NH_FLD_IPSEC_ESP_ALL_FIELDS (BIT(2) - 1)
/* MPLS fields */
#define NH_FLD_MPLS_LABEL_STACK BIT(0)
#define NH_FLD_MPLS_LABEL_STACK_ALL_FIELDS (BIT(1) - 1)
/* MACSEC fields */
#define NH_FLD_MACSEC_SECTAG BIT(0)
#define NH_FLD_MACSEC_ALL_FIELDS (BIT(1) - 1)
/* GTP fields */
#define NH_FLD_GTP_TEID BIT(0)
/* Supported protocols */
enum net_prot {
NET_PROT_NONE = 0,
NET_PROT_PAYLOAD,
NET_PROT_ETH,
NET_PROT_VLAN,
NET_PROT_IPV4,
NET_PROT_IPV6,
NET_PROT_IP,
NET_PROT_TCP,
NET_PROT_UDP,
NET_PROT_UDP_LITE,
NET_PROT_IPHC,
NET_PROT_SCTP,
NET_PROT_SCTP_CHUNK_DATA,
NET_PROT_PPPOE,
NET_PROT_PPP,
NET_PROT_PPPMUX,
NET_PROT_PPPMUX_SUBFRM,
NET_PROT_L2TPV2,
NET_PROT_L2TPV3_CTRL,
NET_PROT_L2TPV3_SESS,
NET_PROT_LLC,
NET_PROT_LLC_SNAP,
NET_PROT_NLPID,
NET_PROT_SNAP,
NET_PROT_MPLS,
NET_PROT_IPSEC_AH,
NET_PROT_IPSEC_ESP,
NET_PROT_UDP_ENC_ESP, /* RFC 3948 */
NET_PROT_MACSEC,
NET_PROT_GRE,
NET_PROT_MINENCAP,
NET_PROT_DCCP,
NET_PROT_ICMP,
NET_PROT_IGMP,
NET_PROT_ARP,
NET_PROT_CAPWAP_DATA,
NET_PROT_CAPWAP_CTRL,
NET_PROT_RFC2684,
NET_PROT_ICMPV6,
NET_PROT_FCOE,
NET_PROT_FIP,
NET_PROT_ISCSI,
NET_PROT_GTP,
NET_PROT_USER_DEFINED_L2,
NET_PROT_USER_DEFINED_L3,
NET_PROT_USER_DEFINED_L4,
NET_PROT_USER_DEFINED_L5,
NET_PROT_USER_DEFINED_SHIM1,
NET_PROT_USER_DEFINED_SHIM2,
NET_PROT_DUMMY_LAST
};
/**
* struct dpkg_extract - A structure for defining a single extraction
* @type: Determines how the union below is interpreted:
* DPKG_EXTRACT_FROM_HDR: selects 'from_hdr';
* DPKG_EXTRACT_FROM_DATA: selects 'from_data';
* DPKG_EXTRACT_FROM_PARSE: selects 'from_parse'
* @extract: Selects extraction method
* @extract.from_hdr: Used when 'type = DPKG_EXTRACT_FROM_HDR'
* @extract.from_data: Used when 'type = DPKG_EXTRACT_FROM_DATA'
* @extract.from_parse: Used when 'type = DPKG_EXTRACT_FROM_PARSE'
* @extract.from_hdr.prot: Any of the supported headers
* @extract.from_hdr.type: Defines the type of header extraction:
* DPKG_FROM_HDR: use size & offset below;
* DPKG_FROM_FIELD: use field, size and offset below;
* DPKG_FULL_FIELD: use field below
* @extract.from_hdr.field: One of the supported fields (NH_FLD_)
* @extract.from_hdr.size: Size in bytes
* @extract.from_hdr.offset: Byte offset
* @extract.from_hdr.hdr_index: Clear for cases not listed below;
* Used for protocols that may have more than a single
* header, 0 indicates an outer header;
* Supported protocols (possible values):
* NET_PROT_VLAN (0, HDR_INDEX_LAST);
* NET_PROT_MPLS (0, 1, HDR_INDEX_LAST);
* NET_PROT_IP(0, HDR_INDEX_LAST);
* NET_PROT_IPv4(0, HDR_INDEX_LAST);
* NET_PROT_IPv6(0, HDR_INDEX_LAST);
* @extract.from_data.size: Size in bytes
* @extract.from_data.offset: Byte offset
* @extract.from_parse.size: Size in bytes
* @extract.from_parse.offset: Byte offset
* @num_of_byte_masks: Defines the number of valid entries in the array below;
* This is also the number of bytes to be used as masks
* @masks: Masks parameters
*/
struct dpkg_extract {
enum dpkg_extract_type type;
union {
struct {
enum net_prot prot;
enum dpkg_extract_from_hdr_type type;
u32 field;
u8 size;
u8 offset;
u8 hdr_index;
} from_hdr;
struct {
u8 size;
u8 offset;
} from_data;
struct {
u8 size;
u8 offset;
} from_parse;
} extract;
u8 num_of_byte_masks;
struct dpkg_mask masks[DPKG_NUM_OF_MASKS];
};
/**
* struct dpkg_profile_cfg - A structure for defining a full Key Generation
* profile (rule)
* @num_extracts: Defines the number of valid entries in the array below
* @extracts: Array of required extractions
*/
struct dpkg_profile_cfg {
u8 num_extracts;
struct dpkg_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
};
#endif /* __FSL_DPKG_H_ */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
+94
View File
@@ -0,0 +1,94 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2019, 2024-2026 NXP
*/
#ifndef _FSL_DPMAC_CMD_H
#define _FSL_DPMAC_CMD_H
/* DPMAC Version */
#define DPMAC_VER_MAJOR 4
#define DPMAC_VER_MINOR 4
#define DPMAC_CMD_BASE_VERSION 1
#define DPMAC_CMD_2ND_VERSION 2
#define DPMAC_CMD_ID_OFFSET 4
#define DPMAC_CMD(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_BASE_VERSION)
#define DPMAC_CMD_V2(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_2ND_VERSION)
/* Command IDs */
#define DPMAC_CMDID_CLOSE DPMAC_CMD(0x800)
#define DPMAC_CMDID_OPEN DPMAC_CMD(0x80c)
#define DPMAC_CMDID_GET_API_VERSION DPMAC_CMD(0xa0c)
#define DPMAC_CMDID_GET_ATTR DPMAC_CMD(0x004)
#define DPMAC_CMDID_SET_LINK_STATE DPMAC_CMD_V2(0x0c3)
#define DPMAC_CMDID_GET_COUNTER DPMAC_CMD(0x0c4)
#define DPMAC_CMDID_SET_PROTOCOL DPMAC_CMD(0x0c7)
#define DPMAC_CMDID_GET_STATISTICS DPMAC_CMD(0x0c8)
/* Macros for accessing command fields smaller than 1byte */
#define DPMAC_MASK(field) \
GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
DPMAC_##field##_SHIFT)
#define dpmac_set_field(var, field, val) \
((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
#define dpmac_get_field(var, field) \
(((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
struct dpmac_cmd_open {
__le32 dpmac_id;
};
struct dpmac_rsp_get_attributes {
u8 eth_if;
u8 link_type;
__le16 id;
__le32 max_rate;
};
#define DPMAC_STATE_SIZE 1
#define DPMAC_STATE_SHIFT 0
#define DPMAC_STATE_VALID_SIZE 1
#define DPMAC_STATE_VALID_SHIFT 1
struct dpmac_cmd_set_link_state {
__le64 options;
__le32 rate;
__le32 pad0;
/* from lsb: up:1, state_valid:1 */
u8 state;
u8 pad1[7];
__le64 supported;
__le64 advertising;
};
struct dpmac_cmd_get_counter {
u8 id;
};
struct dpmac_rsp_get_counter {
__le64 pad;
__le64 counter;
};
struct dpmac_rsp_get_api_version {
__le16 major;
__le16 minor;
};
struct dpmac_cmd_set_protocol {
u8 eth_if;
};
struct dpmac_cmd_get_statistics {
__le64 iova_cnt;
__le64 iova_values;
__le32 num_cnt;
};
#endif /* _FSL_DPMAC_CMD_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpmac.c
+266
View File
@@ -0,0 +1,266 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2019, 2024-2026 NXP
*/
#include <linux/fsl/mc.h>
#include "dpmac.h"
#include "dpmac-cmd.h"
/**
* dpmac_open() - Open a control session for the specified object.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @dpmac_id: DPMAC unique ID
* @token: Returned token; use in subsequent API calls
*
* This function can be used to open a control session for an
* already created object; an object may have been declared in
* the DPL or by calling the dpmac_create function.
* This function returns a unique authentication token,
* associated with the specific object ID and the specific MC
* portal; this token must be used in all subsequent commands for
* this specific object
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dpmac_id,
u16 *token)
{
struct dpmac_cmd_open *cmd_params;
struct fsl_mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
cmd_flags,
0);
cmd_params = (struct dpmac_cmd_open *)cmd.params;
cmd_params->dpmac_id = cpu_to_le32(dpmac_id);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
/* retrieve response parameters */
*token = mc_cmd_hdr_read_token(&cmd);
return err;
}
/**
* dpmac_close() - Close the control session of the object
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPMAC object
*
* After this function is called, no further operations are
* allowed on the object without opening a new control session.
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token)
{
struct fsl_mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
/**
* dpmac_get_attributes - Retrieve DPMAC attributes.
*
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPMAC object
* @attr: Returned object's attributes
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_get_attributes(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpmac_attr *attr)
{
struct dpmac_rsp_get_attributes *rsp_params;
struct fsl_mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
cmd_flags,
token);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
/* retrieve response parameters */
rsp_params = (struct dpmac_rsp_get_attributes *)cmd.params;
attr->eth_if = rsp_params->eth_if;
attr->link_type = rsp_params->link_type;
attr->id = le16_to_cpu(rsp_params->id);
attr->max_rate = le32_to_cpu(rsp_params->max_rate);
return 0;
}
/**
* dpmac_set_link_state() - Set the Ethernet link status
* @mc_io: Pointer to opaque I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPMAC object
* @link_state: Link state configuration
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_set_link_state(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpmac_link_state *link_state)
{
struct dpmac_cmd_set_link_state *cmd_params;
struct fsl_mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
cmd_flags,
token);
cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params;
cmd_params->options = cpu_to_le64(link_state->options);
cmd_params->rate = cpu_to_le32(link_state->rate);
dpmac_set_field(cmd_params->state, STATE, link_state->up);
dpmac_set_field(cmd_params->state, STATE_VALID,
link_state->state_valid);
cmd_params->supported = cpu_to_le64(link_state->supported);
cmd_params->advertising = cpu_to_le64(link_state->advertising);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
/**
* dpmac_get_counter() - Read a specific DPMAC counter
* @mc_io: Pointer to opaque I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPMAC object
* @id: The requested counter ID
* @value: Returned counter value
*
* Return: The requested counter; '0' otherwise.
*/
int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
enum dpmac_counter_id id, u64 *value)
{
struct dpmac_cmd_get_counter *dpmac_cmd;
struct dpmac_rsp_get_counter *dpmac_rsp;
struct fsl_mc_command cmd = { 0 };
int err = 0;
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
cmd_flags,
token);
dpmac_cmd = (struct dpmac_cmd_get_counter *)cmd.params;
dpmac_cmd->id = id;
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
dpmac_rsp = (struct dpmac_rsp_get_counter *)cmd.params;
*value = le64_to_cpu(dpmac_rsp->counter);
return 0;
}
/**
* dpmac_get_api_version() - Get Data Path MAC version
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @major_ver: Major version of data path mac API
* @minor_ver: Minor version of data path mac API
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 *major_ver, u16 *minor_ver)
{
struct dpmac_rsp_get_api_version *rsp_params;
struct fsl_mc_command cmd = { 0 };
int err;
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
cmd_flags,
0);
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
rsp_params = (struct dpmac_rsp_get_api_version *)cmd.params;
*major_ver = le16_to_cpu(rsp_params->major);
*minor_ver = le16_to_cpu(rsp_params->minor);
return 0;
}
/**
* dpmac_set_protocol() - Reconfigure the DPMAC protocol
* @mc_io: Pointer to opaque I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPMAC object
* @protocol: New protocol for the DPMAC to be reconfigured in.
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_set_protocol(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
enum dpmac_eth_if protocol)
{
struct dpmac_cmd_set_protocol *cmd_params;
struct fsl_mc_command cmd = { 0 };
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_PROTOCOL,
cmd_flags, token);
cmd_params = (struct dpmac_cmd_set_protocol *)cmd.params;
cmd_params->eth_if = protocol;
return mc_send_command(mc_io, &cmd);
}
/**
* dpmac_get_statistics() - Get MAC statistics
* @mc_io: Pointer to opaque I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPMAC object
* @iova_cnt: IOVA containing the requested MAC counters formatted as an
* array of __le32 representing the dpmac_counter_id.
* @iova_values: IOVA containing the values for all the requested counters
* formatted as an array of __le64.
* @num_cnt: Number of counters requested
*
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u64 iova_cnt, u64 iova_values, u32 num_cnt)
{
struct dpmac_cmd_get_statistics *cmd_params;
struct fsl_mc_command cmd = { 0 };
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_STATISTICS,
cmd_flags, token);
cmd_params = (struct dpmac_cmd_get_statistics *)cmd.params;
cmd_params->iova_cnt = cpu_to_le64(iova_cnt);
cmd_params->iova_values = cpu_to_le64(iova_values);
cmd_params->num_cnt = cpu_to_le32(num_cnt);
return mc_send_command(mc_io, &cmd);
}
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpmac.h
+303
View File
@@ -0,0 +1,303 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2019, 2024-2026 NXP
*/
#ifndef __FSL_DPMAC_H
#define __FSL_DPMAC_H
/* Data Path MAC API
* Contains initialization APIs and runtime control APIs for DPMAC
*/
struct fsl_mc_io;
int dpmac_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dpmac_id,
u16 *token);
int dpmac_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
/**
* enum dpmac_link_type - DPMAC link type
* @DPMAC_LINK_TYPE_NONE: No link
* @DPMAC_LINK_TYPE_FIXED: Link is fixed type
* @DPMAC_LINK_TYPE_PHY: Link by PHY ID
* @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
*/
enum dpmac_link_type {
DPMAC_LINK_TYPE_NONE,
DPMAC_LINK_TYPE_FIXED,
DPMAC_LINK_TYPE_PHY,
DPMAC_LINK_TYPE_BACKPLANE
};
/**
* enum dpmac_eth_if - DPMAC Ethrnet interface
* @DPMAC_ETH_IF_MII: MII interface
* @DPMAC_ETH_IF_RMII: RMII interface
* @DPMAC_ETH_IF_SMII: SMII interface
* @DPMAC_ETH_IF_GMII: GMII interface
* @DPMAC_ETH_IF_RGMII: RGMII interface
* @DPMAC_ETH_IF_SGMII: SGMII interface
* @DPMAC_ETH_IF_QSGMII: QSGMII interface
* @DPMAC_ETH_IF_XAUI: XAUI interface
* @DPMAC_ETH_IF_XFI: XFI interface
* @DPMAC_ETH_IF_CAUI: CAUI interface
* @DPMAC_ETH_IF_1000BASEX: 1000BASEX interface
* @DPMAC_ETH_IF_USXGMII: USXGMII interface
*/
enum dpmac_eth_if {
DPMAC_ETH_IF_MII,
DPMAC_ETH_IF_RMII,
DPMAC_ETH_IF_SMII,
DPMAC_ETH_IF_GMII,
DPMAC_ETH_IF_RGMII,
DPMAC_ETH_IF_SGMII,
DPMAC_ETH_IF_QSGMII,
DPMAC_ETH_IF_XAUI,
DPMAC_ETH_IF_XFI,
DPMAC_ETH_IF_CAUI,
DPMAC_ETH_IF_1000BASEX,
DPMAC_ETH_IF_USXGMII,
};
/**
* struct dpmac_attr - Structure representing DPMAC attributes
* @id: DPMAC object ID
* @max_rate: Maximum supported rate - in Mbps
* @eth_if: Ethernet interface
* @link_type: link type
*/
struct dpmac_attr {
u16 id;
u32 max_rate;
enum dpmac_eth_if eth_if;
enum dpmac_link_type link_type;
};
int dpmac_get_attributes(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpmac_attr *attr);
/* DPMAC link configuration/state options */
#define DPMAC_LINK_OPT_AUTONEG BIT_ULL(0)
#define DPMAC_LINK_OPT_HALF_DUPLEX BIT_ULL(1)
#define DPMAC_LINK_OPT_PAUSE BIT_ULL(2)
#define DPMAC_LINK_OPT_ASYM_PAUSE BIT_ULL(3)
/* Advertised link speeds */
#define DPMAC_ADVERTISED_10BASET_FULL BIT_ULL(0)
#define DPMAC_ADVERTISED_100BASET_FULL BIT_ULL(1)
#define DPMAC_ADVERTISED_1000BASET_FULL BIT_ULL(2)
#define DPMAC_ADVERTISED_10000BASET_FULL BIT_ULL(4)
#define DPMAC_ADVERTISED_2500BASEX_FULL BIT_ULL(5)
/* Advertise auto-negotiation enable */
#define DPMAC_ADVERTISED_AUTONEG BIT_ULL(3)
/**
* struct dpmac_link_state - DPMAC link configuration request
* @rate: Rate in Mbps
* @options: Enable/Disable DPMAC link cfg features (bitmap)
* @up: Link state
* @state_valid: Ignore/Update the state of the link
* @supported: Speeds capability of the phy (bitmap)
* @advertising: Speeds that are advertised for autoneg (bitmap)
*/
struct dpmac_link_state {
u32 rate;
u64 options;
int up;
int state_valid;
u64 supported;
u64 advertising;
};
int dpmac_set_link_state(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpmac_link_state *link_state);
/**
* enum dpmac_counter_id - DPMAC counter types
*
* @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
* @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad.
* @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad.
* @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad.
* @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad.
* @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad.
* @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger
* (up to max frame length specified),
* good or bad.
* @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received
* with a wrong CRC
* @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length
* specified, with a bad frame check sequence.
* @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors.
* Occurs when a receive FIFO overflows.
* Includes also frames truncated as a result of
* the receive FIFO overflow.
* @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error
* (optional used for wrong SFD).
* @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64
* bytes long with a good CRC.
* @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length
* specified, with a good frame check sequence.
* @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC)
* @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted
* (regular and PFC).
* @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid
* frames and valid pause frames.
* @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames.
* @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames.
* @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received.
* @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames.
* @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error
* (except for undersized/fragment frame).
* @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid
* frames and valid pause frames transmitted.
* @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames.
* @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames.
* @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames.
* @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error.
* @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including
* pause frames.
* @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
* pause frames.
* @DPMAC_CNT_EGR_FRAME_64: counts transmitted 64-bytes frames, good or bad.
* @DPMAC_CNT_EGR_FRAME_127: counts transmitted 65 to 127-bytes frames, good or
* bad.
* @DPMAC_CNT_EGR_FRAME_255: counts transmitted 128 to 255-bytes frames, good
* or bad.
* @DPMAC_CNT_EGR_FRAME_511: counts transmitted 256 to 511-bytes frames, good
* or bad.
* @DPMAC_CNT_EGR_FRAME_1023: counts transmitted 512 to 1023-bytes frames, good
* or bad.
* @DPMAC_CNT_EGR_FRAME_1518: counts transmitted 1024 to 1518-bytes frames,
* good or bad.
* @DPMAC_CNT_EGR_FRAME_1519_MAX: counts transmitted 1519-bytes frames and
* larger (up to max frame length specified),
* good or bad.
* @DPMAC_CNT_ING_ALL_BYTE: counts bytes received in both good and bad packets
* @DPMAC_CNT_ING_FCS_ERR: counts frames received with a CRC-32 error but the
* frame is otherwise of correct length
* @DPMAC_CNT_ING_VLAN_FRAME: counts the received VLAN tagged frames which are
* valid.
* @DPMAC_CNT_ING_UNDERSIZED: counts received frames which were less than 64
* bytes long and with a good CRC.
* @DPMAC_CNT_ING_CONTROL_FRAME: counts received control frames (type 0x8808)
* but not pause frames.
* @DPMAC_CNT_ING_FRAME_DISCARD_NOT_TRUNC: counts the fully dropped frames (not
* truncated) due to internal errors of
* the MAC client. Occurs when a
* receive FIFO overflows.
* @DPMAC_CNT_EGR_ALL_BYTE: counts transmitted bytes in both good and bad
* packets.
* @DPMAC_CNT_EGR_FCS_ERR: counts trasmitted frames with a CRC-32 error except
* for underflows.
* @DPMAC_CNT_EGR_VLAN_FRAME: counts the transmitted VLAN tagged frames which
* are valid.
* @DPMAC_CNT_EGR_ALL_FRAME: counts all trasmitted frames, good or bad.
* @DPMAC_CNT_EGR_CONTROL_FRAME: counts transmitted control frames (type
* 0x8808) but not pause frames.
* @DPMAC_CNT_ING_PFC0: number of PFC frames received for class 0.
* @DPMAC_CNT_ING_PFC1: number of PFC frames received for class 1.
* @DPMAC_CNT_ING_PFC2: number of PFC frames received for class 2.
* @DPMAC_CNT_ING_PFC3: number of PFC frames received for class 3.
* @DPMAC_CNT_ING_PFC4: number of PFC frames received for class 4.
* @DPMAC_CNT_ING_PFC5: number of PFC frames received for class 5.
* @DPMAC_CNT_ING_PFC6: number of PFC frames received for class 6.
* @DPMAC_CNT_ING_PFC7: number of PFC frames received for class 7.
* @DPMAC_CNT_EGR_PFC0: number of PFC frames transmitted for class 0.
* @DPMAC_CNT_EGR_PFC1: number of PFC frames transmitted for class 1.
* @DPMAC_CNT_EGR_PFC2: number of PFC frames transmitted for class 2.
* @DPMAC_CNT_EGR_PFC3: number of PFC frames transmitted for class 3.
* @DPMAC_CNT_EGR_PFC4: number of PFC frames transmitted for class 4.
* @DPMAC_CNT_EGR_PFC5: number of PFC frames transmitted for class 5.
* @DPMAC_CNT_EGR_PFC6: number of PFC frames transmitted for class 6.
* @DPMAC_CNT_EGR_PFC7: number of PFC frames transmitted for class 7.
*/
enum dpmac_counter_id {
DPMAC_CNT_ING_FRAME_64,
DPMAC_CNT_ING_FRAME_127,
DPMAC_CNT_ING_FRAME_255,
DPMAC_CNT_ING_FRAME_511,
DPMAC_CNT_ING_FRAME_1023,
DPMAC_CNT_ING_FRAME_1518,
DPMAC_CNT_ING_FRAME_1519_MAX,
DPMAC_CNT_ING_FRAG,
DPMAC_CNT_ING_JABBER,
DPMAC_CNT_ING_FRAME_DISCARD,
DPMAC_CNT_ING_ALIGN_ERR,
DPMAC_CNT_EGR_UNDERSIZED,
DPMAC_CNT_ING_OVERSIZED,
DPMAC_CNT_ING_VALID_PAUSE_FRAME,
DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
DPMAC_CNT_ING_BYTE,
DPMAC_CNT_ING_MCAST_FRAME,
DPMAC_CNT_ING_BCAST_FRAME,
DPMAC_CNT_ING_ALL_FRAME,
DPMAC_CNT_ING_UCAST_FRAME,
DPMAC_CNT_ING_ERR_FRAME,
DPMAC_CNT_EGR_BYTE,
DPMAC_CNT_EGR_MCAST_FRAME,
DPMAC_CNT_EGR_BCAST_FRAME,
DPMAC_CNT_EGR_UCAST_FRAME,
DPMAC_CNT_EGR_ERR_FRAME,
DPMAC_CNT_ING_GOOD_FRAME,
DPMAC_CNT_EGR_GOOD_FRAME,
DPMAC_CNT_EGR_FRAME_64,
DPMAC_CNT_EGR_FRAME_127,
DPMAC_CNT_EGR_FRAME_255,
DPMAC_CNT_EGR_FRAME_511,
DPMAC_CNT_EGR_FRAME_1023,
DPMAC_CNT_EGR_FRAME_1518,
DPMAC_CNT_EGR_FRAME_1519_MAX,
DPMAC_CNT_ING_ALL_BYTE,
DPMAC_CNT_ING_FCS_ERR,
DPMAC_CNT_ING_VLAN_FRAME,
DPMAC_CNT_ING_UNDERSIZED,
DPMAC_CNT_ING_CONTROL_FRAME,
DPMAC_CNT_ING_FRAME_DISCARD_NOT_TRUNC,
DPMAC_CNT_EGR_ALL_BYTE,
DPMAC_CNT_EGR_FCS_ERR,
DPMAC_CNT_EGR_VLAN_FRAME,
DPMAC_CNT_EGR_ALL_FRAME,
DPMAC_CNT_EGR_CONTROL_FRAME,
DPMAC_CNT_ING_PFC0,
DPMAC_CNT_ING_PFC1,
DPMAC_CNT_ING_PFC2,
DPMAC_CNT_ING_PFC3,
DPMAC_CNT_ING_PFC4,
DPMAC_CNT_ING_PFC5,
DPMAC_CNT_ING_PFC6,
DPMAC_CNT_ING_PFC7,
DPMAC_CNT_EGR_PFC0,
DPMAC_CNT_EGR_PFC1,
DPMAC_CNT_EGR_PFC2,
DPMAC_CNT_EGR_PFC3,
DPMAC_CNT_EGR_PFC4,
DPMAC_CNT_EGR_PFC5,
DPMAC_CNT_EGR_PFC6,
DPMAC_CNT_EGR_PFC7,
};
int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
enum dpmac_counter_id id, u64 *value);
int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 *major_ver, u16 *minor_ver);
int dpmac_set_protocol(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
enum dpmac_eth_if protocol);
int dpmac_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u64 iova_cnt, u64 iova_values, u32 num_cnt);
#endif /* __FSL_DPMAC_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h
+693
View File
@@ -0,0 +1,693 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
* Copyright 2020 NXP
*/
#ifndef _FSL_DPNI_CMD_H
#define _FSL_DPNI_CMD_H
#include "dpni.h"
/* DPNI Version */
#define DPNI_VER_MAJOR 7
#define DPNI_VER_MINOR 0
#define DPNI_CMD_BASE_VERSION 1
#define DPNI_CMD_2ND_VERSION 2
#define DPNI_CMD_3RD_VERSION 3
#define DPNI_CMD_ID_OFFSET 4
#define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION)
#define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_2ND_VERSION)
#define DPNI_CMD_V3(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_3RD_VERSION)
#define DPNI_CMDID_OPEN DPNI_CMD(0x801)
#define DPNI_CMDID_CLOSE DPNI_CMD(0x800)
#define DPNI_CMDID_CREATE DPNI_CMD(0x901)
#define DPNI_CMDID_DESTROY DPNI_CMD(0x900)
#define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01)
#define DPNI_CMDID_ENABLE DPNI_CMD(0x002)
#define DPNI_CMDID_DISABLE DPNI_CMD(0x003)
#define DPNI_CMDID_GET_ATTR DPNI_CMD(0x004)
#define DPNI_CMDID_RESET DPNI_CMD(0x005)
#define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006)
#define DPNI_CMDID_SET_IRQ DPNI_CMD(0x010)
#define DPNI_CMDID_GET_IRQ DPNI_CMD(0x011)
#define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012)
#define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013)
#define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014)
#define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015)
#define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016)
#define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017)
#define DPNI_CMDID_SET_POOLS DPNI_CMD_V3(0x200)
#define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B)
#define DPNI_CMDID_GET_QDID DPNI_CMD(0x210)
#define DPNI_CMDID_GET_TX_DATA_OFFSET DPNI_CMD(0x212)
#define DPNI_CMDID_GET_LINK_STATE DPNI_CMD(0x215)
#define DPNI_CMDID_SET_MAX_FRAME_LENGTH DPNI_CMD(0x216)
#define DPNI_CMDID_GET_MAX_FRAME_LENGTH DPNI_CMD(0x217)
#define DPNI_CMDID_SET_LINK_CFG DPNI_CMD(0x21A)
#define DPNI_CMDID_SET_TX_SHAPING DPNI_CMD_V2(0x21B)
#define DPNI_CMDID_SET_MCAST_PROMISC DPNI_CMD(0x220)
#define DPNI_CMDID_GET_MCAST_PROMISC DPNI_CMD(0x221)
#define DPNI_CMDID_SET_UNICAST_PROMISC DPNI_CMD(0x222)
#define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223)
#define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224)
#define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225)
#define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD(0x226)
#define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227)
#define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228)
#define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD(0x235)
#define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230)
#define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231)
#define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232)
#define DPNI_CMDID_SET_QOS_TBL DPNI_CMD(0x240)
#define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD(0x241)
#define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242)
#define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243)
#define DPNI_CMDID_ADD_FS_ENT DPNI_CMD(0x244)
#define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245)
#define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246)
#define DPNI_CMDID_GET_STATISTICS DPNI_CMD(0x25D)
#define DPNI_CMDID_GET_QUEUE DPNI_CMD(0x25F)
#define DPNI_CMDID_SET_QUEUE DPNI_CMD(0x260)
#define DPNI_CMDID_GET_TAILDROP DPNI_CMD(0x261)
#define DPNI_CMDID_SET_TAILDROP DPNI_CMD(0x262)
#define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263)
#define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD(0x264)
#define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD(0x265)
#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266)
#define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD(0x267)
#define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD(0x268)
#define DPNI_CMDID_SET_EARLY_DROP DPNI_CMD(0x269)
#define DPNI_CMDID_GET_EARLY_DROP DPNI_CMD(0x26A)
#define DPNI_CMDID_GET_OFFLOAD DPNI_CMD(0x26B)
#define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C)
#define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273)
#define DPNI_CMDID_SET_RX_HASH_DIST DPNI_CMD(0x274)
#define DPNI_CMDID_GET_LINK_CFG DPNI_CMD(0x278)
#define DPNI_CMDID_SET_SINGLE_STEP_CFG DPNI_CMD(0x279)
#define DPNI_CMDID_GET_SINGLE_STEP_CFG DPNI_CMD_V2(0x27a)
/* Macros for accessing command fields smaller than 1byte */
#define DPNI_MASK(field) \
GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
DPNI_##field##_SHIFT)
#define dpni_set_field(var, field, val) \
((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field)))
#define dpni_get_field(var, field) \
(((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT)
struct dpni_cmd_open {
__le32 dpni_id;
};
#define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order))
struct dpni_cmd_pool {
__le16 dpbp_id;
u8 priority_mask;
u8 pad;
};
struct dpni_cmd_set_pools {
u8 num_dpbp;
u8 backup_pool_mask;
u8 pad;
u8 pool_options;
struct dpni_cmd_pool pool[DPNI_MAX_DPBP];
__le16 buffer_size[DPNI_MAX_DPBP];
};
/* The enable indication is always the least significant bit */
#define DPNI_ENABLE_SHIFT 0
#define DPNI_ENABLE_SIZE 1
struct dpni_rsp_is_enabled {
u8 enabled;
};
struct dpni_rsp_get_irq {
/* response word 0 */
__le32 irq_val;
__le32 pad;
/* response word 1 */
__le64 irq_addr;
/* response word 2 */
__le32 irq_num;
__le32 type;
};
struct dpni_cmd_set_irq_enable {
u8 enable;
u8 pad[3];
u8 irq_index;
};
struct dpni_cmd_get_irq_enable {
__le32 pad;
u8 irq_index;
};
struct dpni_rsp_get_irq_enable {
u8 enabled;
};
struct dpni_cmd_set_irq_mask {
__le32 mask;
u8 irq_index;
};
struct dpni_cmd_get_irq_mask {
__le32 pad;
u8 irq_index;
};
struct dpni_rsp_get_irq_mask {
__le32 mask;
};
struct dpni_cmd_get_irq_status {
__le32 status;
u8 irq_index;
};
struct dpni_rsp_get_irq_status {
__le32 status;
};
struct dpni_cmd_clear_irq_status {
__le32 status;
u8 irq_index;
};
struct dpni_rsp_get_attr {
/* response word 0 */
__le32 options;
u8 num_queues;
u8 num_tcs;
u8 mac_filter_entries;
u8 pad0;
/* response word 1 */
u8 vlan_filter_entries;
u8 pad1;
u8 qos_entries;
u8 pad2;
__le16 fs_entries;
__le16 pad3;
/* response word 2 */
u8 qos_key_size;
u8 fs_key_size;
__le16 wriop_version;
};
#define DPNI_ERROR_ACTION_SHIFT 0
#define DPNI_ERROR_ACTION_SIZE 4
#define DPNI_FRAME_ANN_SHIFT 4
#define DPNI_FRAME_ANN_SIZE 1
struct dpni_cmd_set_errors_behavior {
__le32 errors;
/* from least significant bit: error_action:4, set_frame_annotation:1 */
u8 flags;
};
/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation
* buffer layouts, but they all share the same parameters.
* If one of the functions changes, below structure needs to be split.
*/
#define DPNI_PASS_TS_SHIFT 0
#define DPNI_PASS_TS_SIZE 1
#define DPNI_PASS_PR_SHIFT 1
#define DPNI_PASS_PR_SIZE 1
#define DPNI_PASS_FS_SHIFT 2
#define DPNI_PASS_FS_SIZE 1
struct dpni_cmd_get_buffer_layout {
u8 qtype;
};
struct dpni_rsp_get_buffer_layout {
/* response word 0 */
u8 pad0[6];
/* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
u8 flags;
u8 pad1;
/* response word 1 */
__le16 private_data_size;
__le16 data_align;
__le16 head_room;
__le16 tail_room;
};
struct dpni_cmd_set_buffer_layout {
/* cmd word 0 */
u8 qtype;
u8 pad0[3];
__le16 options;
/* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
u8 flags;
u8 pad1;
/* cmd word 1 */
__le16 private_data_size;
__le16 data_align;
__le16 head_room;
__le16 tail_room;
};
struct dpni_cmd_set_offload {
u8 pad[3];
u8 dpni_offload;
__le32 config;
};
struct dpni_cmd_get_offload {
u8 pad[3];
u8 dpni_offload;
};
struct dpni_rsp_get_offload {
__le32 pad;
__le32 config;
};
struct dpni_cmd_get_qdid {
u8 qtype;
};
struct dpni_rsp_get_qdid {
__le16 qdid;
};
struct dpni_rsp_get_tx_data_offset {
__le16 data_offset;
};
struct dpni_cmd_get_statistics {
u8 page_number;
};
struct dpni_rsp_get_statistics {
__le64 counter[DPNI_STATISTICS_CNT];
};
struct dpni_cmd_link_cfg {
/* cmd word 0 */
__le64 pad0;
/* cmd word 1 */
__le32 rate;
__le32 pad1;
/* cmd word 2 */
__le64 options;
};
#define DPNI_LINK_STATE_SHIFT 0
#define DPNI_LINK_STATE_SIZE 1
struct dpni_rsp_get_link_state {
/* response word 0 */
__le32 pad0;
/* from LSB: up:1 */
u8 flags;
u8 pad1[3];
/* response word 1 */
__le32 rate;
__le32 pad2;
/* response word 2 */
__le64 options;
};
struct dpni_cmd_set_max_frame_length {
__le16 max_frame_length;
};
struct dpni_rsp_get_max_frame_length {
__le16 max_frame_length;
};
struct dpni_cmd_set_multicast_promisc {
u8 enable;
};
struct dpni_rsp_get_multicast_promisc {
u8 enabled;
};
struct dpni_cmd_set_unicast_promisc {
u8 enable;
};
struct dpni_rsp_get_unicast_promisc {
u8 enabled;
};
struct dpni_cmd_set_primary_mac_addr {
__le16 pad;
u8 mac_addr[6];
};
struct dpni_rsp_get_primary_mac_addr {
__le16 pad;
u8 mac_addr[6];
};
struct dpni_rsp_get_port_mac_addr {
__le16 pad;
u8 mac_addr[6];
};
struct dpni_cmd_add_mac_addr {
__le16 pad;
u8 mac_addr[6];
};
struct dpni_cmd_remove_mac_addr {
__le16 pad;
u8 mac_addr[6];
};
#define DPNI_UNICAST_FILTERS_SHIFT 0
#define DPNI_UNICAST_FILTERS_SIZE 1
#define DPNI_MULTICAST_FILTERS_SHIFT 1
#define DPNI_MULTICAST_FILTERS_SIZE 1
struct dpni_cmd_clear_mac_filters {
/* from LSB: unicast:1, multicast:1 */
u8 flags;
};
#define DPNI_DIST_MODE_SHIFT 0
#define DPNI_DIST_MODE_SIZE 4
#define DPNI_MISS_ACTION_SHIFT 4
#define DPNI_MISS_ACTION_SIZE 4
struct dpni_cmd_set_rx_tc_dist {
/* cmd word 0 */
__le16 dist_size;
u8 tc_id;
/* from LSB: dist_mode:4, miss_action:4 */
u8 flags;
__le16 pad0;
__le16 default_flow_id;
/* cmd word 1..5 */
__le64 pad1[5];
/* cmd word 6 */
__le64 key_cfg_iova;
};
/* dpni_set_rx_tc_dist extension (structure of the DMA-able memory at
* key_cfg_iova)
*/
struct dpni_mask_cfg {
u8 mask;
u8 offset;
};
#define DPNI_EFH_TYPE_SHIFT 0
#define DPNI_EFH_TYPE_SIZE 4
#define DPNI_EXTRACT_TYPE_SHIFT 0
#define DPNI_EXTRACT_TYPE_SIZE 4
struct dpni_dist_extract {
/* word 0 */
u8 prot;
/* EFH type stored in the 4 least significant bits */
u8 efh_type;
u8 size;
u8 offset;
__le32 field;
/* word 1 */
u8 hdr_index;
u8 constant;
u8 num_of_repeats;
u8 num_of_byte_masks;
/* Extraction type is stored in the 4 LSBs */
u8 extract_type;
u8 pad[3];
/* word 2 */
struct dpni_mask_cfg masks[4];
};
struct dpni_ext_set_rx_tc_dist {
/* extension word 0 */
u8 num_extracts;
u8 pad[7];
/* words 1..25 */
struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
};
struct dpni_cmd_get_queue {
u8 qtype;
u8 tc;
u8 index;
};
#define DPNI_DEST_TYPE_SHIFT 0
#define DPNI_DEST_TYPE_SIZE 4
#define DPNI_STASH_CTRL_SHIFT 6
#define DPNI_STASH_CTRL_SIZE 1
#define DPNI_HOLD_ACTIVE_SHIFT 7
#define DPNI_HOLD_ACTIVE_SIZE 1
struct dpni_rsp_get_queue {
/* response word 0 */
__le64 pad0;
/* response word 1 */
__le32 dest_id;
__le16 pad1;
u8 dest_prio;
/* From LSB: dest_type:4, pad:2, flc_stash_ctrl:1, hold_active:1 */
u8 flags;
/* response word 2 */
__le64 flc;
/* response word 3 */
__le64 user_context;
/* response word 4 */
__le32 fqid;
__le16 qdbin;
};
struct dpni_cmd_set_queue {
/* cmd word 0 */
u8 qtype;
u8 tc;
u8 index;
u8 options;
__le32 pad0;
/* cmd word 1 */
__le32 dest_id;
__le16 pad1;
u8 dest_prio;
u8 flags;
/* cmd word 2 */
__le64 flc;
/* cmd word 3 */
__le64 user_context;
};
struct dpni_cmd_set_taildrop {
/* cmd word 0 */
u8 congestion_point;
u8 qtype;
u8 tc;
u8 index;
__le32 pad0;
/* cmd word 1 */
/* Only least significant bit is relevant */
u8 enable;
u8 pad1;
u8 units;
u8 pad2;
__le32 threshold;
};
struct dpni_cmd_get_taildrop {
u8 congestion_point;
u8 qtype;
u8 tc;
u8 index;
};
struct dpni_rsp_get_taildrop {
/* cmd word 0 */
__le64 pad0;
/* cmd word 1 */
/* only least significant bit is relevant */
u8 enable;
u8 pad1;
u8 units;
u8 pad2;
__le32 threshold;
};
struct dpni_rsp_get_api_version {
__le16 major;
__le16 minor;
};
#define DPNI_RX_FS_DIST_ENABLE_SHIFT 0
#define DPNI_RX_FS_DIST_ENABLE_SIZE 1
struct dpni_cmd_set_rx_fs_dist {
__le16 dist_size;
u8 enable;
u8 tc;
__le16 miss_flow_id;
__le16 pad;
__le64 key_cfg_iova;
};
#define DPNI_RX_HASH_DIST_ENABLE_SHIFT 0
#define DPNI_RX_HASH_DIST_ENABLE_SIZE 1
struct dpni_cmd_set_rx_hash_dist {
__le16 dist_size;
u8 enable;
u8 tc;
__le32 pad;
__le64 key_cfg_iova;
};
struct dpni_cmd_add_fs_entry {
/* cmd word 0 */
__le16 options;
u8 tc_id;
u8 key_size;
__le16 index;
__le16 flow_id;
/* cmd word 1 */
__le64 key_iova;
/* cmd word 2 */
__le64 mask_iova;
/* cmd word 3 */
__le64 flc;
};
struct dpni_cmd_remove_fs_entry {
/* cmd word 0 */
__le16 pad0;
u8 tc_id;
u8 key_size;
__le32 pad1;
/* cmd word 1 */
__le64 key_iova;
/* cmd word 2 */
__le64 mask_iova;
};
#define DPNI_DISCARD_ON_MISS_SHIFT 0
#define DPNI_DISCARD_ON_MISS_SIZE 1
struct dpni_cmd_set_qos_table {
__le32 pad;
u8 default_tc;
/* only the LSB */
u8 discard_on_miss;
__le16 pad1[21];
__le64 key_cfg_iova;
};
struct dpni_cmd_add_qos_entry {
__le16 pad;
u8 tc_id;
u8 key_size;
__le16 index;
__le16 pad1;
__le64 key_iova;
__le64 mask_iova;
};
struct dpni_cmd_remove_qos_entry {
u8 pad[3];
u8 key_size;
__le32 pad1;
__le64 key_iova;
__le64 mask_iova;
};
#define DPNI_DEST_TYPE_SHIFT 0
#define DPNI_DEST_TYPE_SIZE 4
#define DPNI_CONG_UNITS_SHIFT 4
#define DPNI_CONG_UNITS_SIZE 2
struct dpni_cmd_set_congestion_notification {
/* cmd word 0 */
u8 qtype;
u8 tc;
u8 pad[6];
/* cmd word 1 */
__le32 dest_id;
__le16 notification_mode;
u8 dest_priority;
/* from LSB: dest_type: 4 units:2 */
u8 type_units;
/* cmd word 2 */
__le64 message_iova;
/* cmd word 3 */
__le64 message_ctx;
/* cmd word 4 */
__le32 threshold_entry;
__le32 threshold_exit;
};
#define DPNI_COUPLED_SHIFT 0
#define DPNI_COUPLED_SIZE 1
struct dpni_cmd_set_tx_shaping {
__le16 tx_cr_max_burst_size;
__le16 tx_er_max_burst_size;
__le32 pad;
__le32 tx_cr_rate_limit;
__le32 tx_er_rate_limit;
/* from LSB: coupled:1 */
u8 coupled;
};
#define DPNI_PTP_ENABLE_SHIFT 0
#define DPNI_PTP_ENABLE_SIZE 1
#define DPNI_PTP_CH_UPDATE_SHIFT 1
#define DPNI_PTP_CH_UPDATE_SIZE 1
struct dpni_cmd_single_step_cfg {
__le16 flags;
__le16 offset;
__le32 peer_delay;
__le32 ptp_onestep_reg_base;
__le32 pad0;
};
struct dpni_rsp_single_step_cfg {
__le16 flags;
__le16 offset;
__le32 peer_delay;
__le32 ptp_onestep_reg_base;
__le32 pad0;
};
struct dpni_cmd_enable_vlan_filter {
/* only the LSB */
u8 en;
};
struct dpni_cmd_vlan_id {
u8 flags;
u8 tc_id;
u8 flow_id;
u8 pad;
__le16 vlan_id;
};
#endif /* _FSL_DPNI_CMD_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpni.c
+2185
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpni.h
+1119
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h
+74
View File
@@ -0,0 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016-2018 NXP
*/
#ifndef _FSL_DPRTC_CMD_H
#define _FSL_DPRTC_CMD_H
/* Command versioning */
#define DPRTC_CMD_BASE_VERSION 1
#define DPRTC_CMD_VERSION_2 2
#define DPRTC_CMD_ID_OFFSET 4
#define DPRTC_CMD(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION)
#define DPRTC_CMD_V2(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_VERSION_2)
/* Command IDs */
#define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800)
#define DPRTC_CMDID_OPEN DPRTC_CMD(0x810)
#define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012)
#define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013)
#define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD_V2(0x014)
#define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015)
#define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016)
#define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017)
#pragma pack(push, 1)
struct dprtc_cmd_open {
__le32 dprtc_id;
};
struct dprtc_cmd_get_irq {
__le32 pad;
u8 irq_index;
};
struct dprtc_cmd_set_irq_enable {
u8 en;
u8 pad[3];
u8 irq_index;
};
struct dprtc_rsp_get_irq_enable {
u8 en;
};
struct dprtc_cmd_set_irq_mask {
__le32 mask;
u8 irq_index;
};
struct dprtc_rsp_get_irq_mask {
__le32 mask;
};
struct dprtc_cmd_get_irq_status {
__le32 status;
u8 irq_index;
};
struct dprtc_rsp_get_irq_status {
__le32 status;
};
struct dprtc_cmd_clear_irq_status {
__le32 status;
u8 irq_index;
};
#pragma pack(pop)
#endif /* _FSL_DPRTC_CMD_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dprtc.c
+293
View File
@@ -0,0 +1,293 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016-2018 NXP
*/
#include <linux/fsl/mc.h>
#include "dprtc.h"
#include "dprtc-cmd.h"
/**
* dprtc_open() - Open a control session for the specified object.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @dprtc_id: DPRTC unique ID
* @token: Returned token; use in subsequent API calls
*
* This function can be used to open a control session for an
* already created object; an object may have been declared in
* the DPL or by calling the dprtc_create function.
* This function returns a unique authentication token,
* associated with the specific object ID and the specific MC
* portal; this token must be used in all subsequent commands for
* this specific object
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dprtc_id,
u16 *token)
{
struct dprtc_cmd_open *cmd_params;
struct fsl_mc_command cmd = { 0 };
int err;
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_OPEN,
cmd_flags,
0);
cmd_params = (struct dprtc_cmd_open *)cmd.params;
cmd_params->dprtc_id = cpu_to_le32(dprtc_id);
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
*token = mc_cmd_hdr_read_token(&cmd);
return 0;
}
/**
* dprtc_close() - Close the control session of the object
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
*
* After this function is called, no further operations are
* allowed on the object without opening a new control session.
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token)
{
struct fsl_mc_command cmd = { 0 };
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLOSE, cmd_flags,
token);
return mc_send_command(mc_io, &cmd);
}
/**
* dprtc_set_irq_enable() - Set overall interrupt state.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
* @irq_index: The interrupt index to configure
* @en: Interrupt state - enable = 1, disable = 0
*
* Allows GPP software to control when interrupts are generated.
* Each interrupt can have up to 32 causes. The enable/disable control's the
* overall interrupt state. if the interrupt is disabled no causes will cause
* an interrupt.
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u8 en)
{
struct dprtc_cmd_set_irq_enable *cmd_params;
struct fsl_mc_command cmd = { 0 };
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_ENABLE,
cmd_flags,
token);
cmd_params = (struct dprtc_cmd_set_irq_enable *)cmd.params;
cmd_params->irq_index = irq_index;
cmd_params->en = en;
return mc_send_command(mc_io, &cmd);
}
/**
* dprtc_get_irq_enable() - Get overall interrupt state
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
* @irq_index: The interrupt index to configure
* @en: Returned interrupt state - enable = 1, disable = 0
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u8 *en)
{
struct dprtc_rsp_get_irq_enable *rsp_params;
struct dprtc_cmd_get_irq *cmd_params;
struct fsl_mc_command cmd = { 0 };
int err;
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_ENABLE,
cmd_flags,
token);
cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
cmd_params->irq_index = irq_index;
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
rsp_params = (struct dprtc_rsp_get_irq_enable *)cmd.params;
*en = rsp_params->en;
return 0;
}
/**
* dprtc_set_irq_mask() - Set interrupt mask.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
* @irq_index: The interrupt index to configure
* @mask: Event mask to trigger interrupt;
* each bit:
* 0 = ignore event
* 1 = consider event for asserting IRQ
*
* Every interrupt can have up to 32 causes and the interrupt model supports
* masking/unmasking each cause independently
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 mask)
{
struct dprtc_cmd_set_irq_mask *cmd_params;
struct fsl_mc_command cmd = { 0 };
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_MASK,
cmd_flags,
token);
cmd_params = (struct dprtc_cmd_set_irq_mask *)cmd.params;
cmd_params->mask = cpu_to_le32(mask);
cmd_params->irq_index = irq_index;
return mc_send_command(mc_io, &cmd);
}
/**
* dprtc_get_irq_mask() - Get interrupt mask.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
* @irq_index: The interrupt index to configure
* @mask: Returned event mask to trigger interrupt
*
* Every interrupt can have up to 32 causes and the interrupt model supports
* masking/unmasking each cause independently
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 *mask)
{
struct dprtc_rsp_get_irq_mask *rsp_params;
struct dprtc_cmd_get_irq *cmd_params;
struct fsl_mc_command cmd = { 0 };
int err;
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_MASK,
cmd_flags,
token);
cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
cmd_params->irq_index = irq_index;
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
rsp_params = (struct dprtc_rsp_get_irq_mask *)cmd.params;
*mask = le32_to_cpu(rsp_params->mask);
return 0;
}
/**
* dprtc_get_irq_status() - Get the current status of any pending interrupts.
*
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
* @irq_index: The interrupt index to configure
* @status: Returned interrupts status - one bit per cause:
* 0 = no interrupt pending
* 1 = interrupt pending
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 *status)
{
struct dprtc_cmd_get_irq_status *cmd_params;
struct dprtc_rsp_get_irq_status *rsp_params;
struct fsl_mc_command cmd = { 0 };
int err;
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_STATUS,
cmd_flags,
token);
cmd_params = (struct dprtc_cmd_get_irq_status *)cmd.params;
cmd_params->status = cpu_to_le32(*status);
cmd_params->irq_index = irq_index;
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
rsp_params = (struct dprtc_rsp_get_irq_status *)cmd.params;
*status = le32_to_cpu(rsp_params->status);
return 0;
}
/**
* dprtc_clear_irq_status() - Clear a pending interrupt's status
*
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPRTC object
* @irq_index: The interrupt index to configure
* @status: Bits to clear (W1C) - one bit per cause:
* 0 = don't change
* 1 = clear status bit
*
* Return: '0' on Success; Error code otherwise.
*/
int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 status)
{
struct dprtc_cmd_clear_irq_status *cmd_params;
struct fsl_mc_command cmd = { 0 };
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLEAR_IRQ_STATUS,
cmd_flags,
token);
cmd_params = (struct dprtc_cmd_clear_irq_status *)cmd.params;
cmd_params->irq_index = irq_index;
cmd_params->status = cpu_to_le32(status);
return mc_send_command(mc_io, &cmd);
}
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dprtc.h
+68
View File
@@ -0,0 +1,68 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016-2018 NXP
*/
#ifndef __FSL_DPRTC_H
#define __FSL_DPRTC_H
/* Data Path Real Time Counter API
* Contains initialization APIs and runtime control APIs for RTC
*/
struct fsl_mc_io;
#define DPRTC_MAX_IRQ_NUM 1
#define DPRTC_IRQ_INDEX 0
#define DPRTC_EVENT_PPS 0x08000000
#define DPRTC_EVENT_ETS1 0x00800000
#define DPRTC_EVENT_ETS2 0x00400000
int dprtc_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dprtc_id,
u16 *token);
int dprtc_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u8 en);
int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u8 *en);
int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 mask);
int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 *mask);
int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 *status);
int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 irq_index,
u32 status);
#endif /* __FSL_DPRTC_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpsw-cmd.h
+556
View File
@@ -0,0 +1,556 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2017-2021 NXP
*
*/
#ifndef __FSL_DPSW_CMD_H
#define __FSL_DPSW_CMD_H
#include "dpsw.h"
/* DPSW Version */
#define DPSW_VER_MAJOR 8
#define DPSW_VER_MINOR 9
#define DPSW_CMD_BASE_VERSION 1
#define DPSW_CMD_VERSION_2 2
#define DPSW_CMD_ID_OFFSET 4
#define DPSW_CMD_ID(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION)
#define DPSW_CMD_V2(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_VERSION_2)
/* Command IDs */
#define DPSW_CMDID_CLOSE DPSW_CMD_ID(0x800)
#define DPSW_CMDID_OPEN DPSW_CMD_ID(0x802)
#define DPSW_CMDID_GET_API_VERSION DPSW_CMD_ID(0xa02)
#define DPSW_CMDID_ENABLE DPSW_CMD_ID(0x002)
#define DPSW_CMDID_DISABLE DPSW_CMD_ID(0x003)
#define DPSW_CMDID_GET_ATTR DPSW_CMD_V2(0x004)
#define DPSW_CMDID_RESET DPSW_CMD_ID(0x005)
#define DPSW_CMDID_SET_IRQ_ENABLE DPSW_CMD_ID(0x012)
#define DPSW_CMDID_SET_IRQ_MASK DPSW_CMD_ID(0x014)
#define DPSW_CMDID_GET_IRQ_STATUS DPSW_CMD_ID(0x016)
#define DPSW_CMDID_CLEAR_IRQ_STATUS DPSW_CMD_ID(0x017)
#define DPSW_CMDID_SET_REFLECTION_IF DPSW_CMD_ID(0x022)
#define DPSW_CMDID_IF_SET_TCI DPSW_CMD_ID(0x030)
#define DPSW_CMDID_IF_SET_STP DPSW_CMD_ID(0x031)
#define DPSW_CMDID_IF_GET_COUNTER DPSW_CMD_V2(0x034)
#define DPSW_CMDID_IF_ADD_REFLECTION DPSW_CMD_ID(0x037)
#define DPSW_CMDID_IF_REMOVE_REFLECTION DPSW_CMD_ID(0x038)
#define DPSW_CMDID_IF_ENABLE DPSW_CMD_ID(0x03D)
#define DPSW_CMDID_IF_DISABLE DPSW_CMD_ID(0x03E)
#define DPSW_CMDID_IF_GET_ATTR DPSW_CMD_ID(0x042)
#define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH DPSW_CMD_ID(0x044)
#define DPSW_CMDID_IF_GET_LINK_STATE DPSW_CMD_ID(0x046)
#define DPSW_CMDID_IF_GET_TCI DPSW_CMD_ID(0x04A)
#define DPSW_CMDID_IF_SET_LINK_CFG DPSW_CMD_ID(0x04C)
#define DPSW_CMDID_VLAN_ADD DPSW_CMD_ID(0x060)
#define DPSW_CMDID_VLAN_ADD_IF DPSW_CMD_V2(0x061)
#define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED DPSW_CMD_ID(0x062)
#define DPSW_CMDID_VLAN_REMOVE_IF DPSW_CMD_ID(0x064)
#define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED DPSW_CMD_ID(0x065)
#define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING DPSW_CMD_ID(0x066)
#define DPSW_CMDID_VLAN_REMOVE DPSW_CMD_ID(0x067)
#define DPSW_CMDID_FDB_ADD DPSW_CMD_ID(0x082)
#define DPSW_CMDID_FDB_REMOVE DPSW_CMD_ID(0x083)
#define DPSW_CMDID_FDB_ADD_UNICAST DPSW_CMD_ID(0x084)
#define DPSW_CMDID_FDB_REMOVE_UNICAST DPSW_CMD_ID(0x085)
#define DPSW_CMDID_FDB_ADD_MULTICAST DPSW_CMD_ID(0x086)
#define DPSW_CMDID_FDB_REMOVE_MULTICAST DPSW_CMD_ID(0x087)
#define DPSW_CMDID_FDB_DUMP DPSW_CMD_ID(0x08A)
#define DPSW_CMDID_ACL_ADD DPSW_CMD_ID(0x090)
#define DPSW_CMDID_ACL_REMOVE DPSW_CMD_ID(0x091)
#define DPSW_CMDID_ACL_ADD_ENTRY DPSW_CMD_ID(0x092)
#define DPSW_CMDID_ACL_REMOVE_ENTRY DPSW_CMD_ID(0x093)
#define DPSW_CMDID_ACL_ADD_IF DPSW_CMD_ID(0x094)
#define DPSW_CMDID_ACL_REMOVE_IF DPSW_CMD_ID(0x095)
#define DPSW_CMDID_IF_GET_PORT_MAC_ADDR DPSW_CMD_ID(0x0A7)
#define DPSW_CMDID_CTRL_IF_GET_ATTR DPSW_CMD_ID(0x0A0)
#define DPSW_CMDID_CTRL_IF_SET_POOLS DPSW_CMD_ID(0x0A1)
#define DPSW_CMDID_CTRL_IF_ENABLE DPSW_CMD_ID(0x0A2)
#define DPSW_CMDID_CTRL_IF_DISABLE DPSW_CMD_ID(0x0A3)
#define DPSW_CMDID_CTRL_IF_SET_QUEUE DPSW_CMD_ID(0x0A6)
#define DPSW_CMDID_SET_EGRESS_FLOOD DPSW_CMD_ID(0x0AC)
#define DPSW_CMDID_IF_SET_LEARNING_MODE DPSW_CMD_ID(0x0AD)
/* Macros for accessing command fields smaller than 1byte */
#define DPSW_MASK(field) \
GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
DPSW_##field##_SHIFT)
#define dpsw_set_field(var, field, val) \
((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field)))
#define dpsw_get_field(var, field) \
(((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT)
#define dpsw_get_bit(var, bit) \
(((var) >> (bit)) & GENMASK(0, 0))
#pragma pack(push, 1)
struct dpsw_cmd_open {
__le32 dpsw_id;
};
#define DPSW_COMPONENT_TYPE_SHIFT 0
#define DPSW_COMPONENT_TYPE_SIZE 4
struct dpsw_cmd_create {
/* cmd word 0 */
__le16 num_ifs;
u8 max_fdbs;
u8 max_meters_per_if;
/* from LSB: only the first 4 bits */
u8 component_type;
u8 pad[3];
/* cmd word 1 */
__le16 max_vlans;
__le16 max_fdb_entries;
__le16 fdb_aging_time;
__le16 max_fdb_mc_groups;
/* cmd word 2 */
__le64 options;
};
struct dpsw_cmd_destroy {
__le32 dpsw_id;
};
#define DPSW_ENABLE_SHIFT 0
#define DPSW_ENABLE_SIZE 1
struct dpsw_rsp_is_enabled {
/* from LSB: enable:1 */
u8 enabled;
};
struct dpsw_cmd_set_irq_enable {
u8 enable_state;
u8 pad[3];
u8 irq_index;
};
struct dpsw_cmd_get_irq_enable {
__le32 pad;
u8 irq_index;
};
struct dpsw_rsp_get_irq_enable {
u8 enable_state;
};
struct dpsw_cmd_set_irq_mask {
__le32 mask;
u8 irq_index;
};
struct dpsw_cmd_get_irq_mask {
__le32 pad;
u8 irq_index;
};
struct dpsw_rsp_get_irq_mask {
__le32 mask;
};
struct dpsw_cmd_get_irq_status {
__le32 status;
u8 irq_index;
};
struct dpsw_rsp_get_irq_status {
__le32 status;
};
struct dpsw_cmd_clear_irq_status {
__le32 status;
u8 irq_index;
};
#define DPSW_COMPONENT_TYPE_SHIFT 0
#define DPSW_COMPONENT_TYPE_SIZE 4
#define DPSW_FLOODING_CFG_SHIFT 0
#define DPSW_FLOODING_CFG_SIZE 4
#define DPSW_BROADCAST_CFG_SHIFT 4
#define DPSW_BROADCAST_CFG_SIZE 4
struct dpsw_rsp_get_attr {
/* cmd word 0 */
__le16 num_ifs;
u8 max_fdbs;
u8 num_fdbs;
__le16 max_vlans;
__le16 num_vlans;
/* cmd word 1 */
__le16 max_fdb_entries;
__le16 fdb_aging_time;
__le32 dpsw_id;
/* cmd word 2 */
__le16 mem_size;
__le16 max_fdb_mc_groups;
u8 max_meters_per_if;
/* from LSB only the first 4 bits */
u8 component_type;
/* [0:3] - flooding configuration
* [4:7] - broadcast configuration
*/
u8 repl_cfg;
u8 pad;
/* cmd word 3 */
__le64 options;
};
#define DPSW_VLAN_ID_SHIFT 0
#define DPSW_VLAN_ID_SIZE 12
#define DPSW_DEI_SHIFT 12
#define DPSW_DEI_SIZE 1
#define DPSW_PCP_SHIFT 13
#define DPSW_PCP_SIZE 3
struct dpsw_cmd_if_set_tci {
__le16 if_id;
/* from LSB: VLAN_ID:12 DEI:1 PCP:3 */
__le16 conf;
};
struct dpsw_cmd_if_get_tci {
__le16 if_id;
};
struct dpsw_rsp_if_get_tci {
__le16 pad;
__le16 vlan_id;
u8 dei;
u8 pcp;
};
#define DPSW_STATE_SHIFT 0
#define DPSW_STATE_SIZE 4
struct dpsw_cmd_if_set_stp {
__le16 if_id;
__le16 vlan_id;
/* only the first LSB 4 bits */
u8 state;
};
#define DPSW_COUNTER_TYPE_SHIFT 0
#define DPSW_COUNTER_TYPE_SIZE 5
struct dpsw_cmd_if_get_counter {
__le16 if_id;
/* from LSB: type:5 */
u8 type;
};
struct dpsw_rsp_if_get_counter {
__le64 pad;
__le64 counter;
};
struct dpsw_cmd_if {
__le16 if_id;
};
#define DPSW_ADMIT_UNTAGGED_SHIFT 0
#define DPSW_ADMIT_UNTAGGED_SIZE 4
#define DPSW_ENABLED_SHIFT 5
#define DPSW_ENABLED_SIZE 1
#define DPSW_ACCEPT_ALL_VLAN_SHIFT 6
#define DPSW_ACCEPT_ALL_VLAN_SIZE 1
struct dpsw_rsp_if_get_attr {
/* cmd word 0 */
/* from LSB: admit_untagged:4 enabled:1 accept_all_vlan:1 */
u8 conf;
u8 pad1;
u8 num_tcs;
u8 pad2;
__le16 qdid;
/* cmd word 1 */
__le32 options;
__le32 pad3;
/* cmd word 2 */
__le32 rate;
};
struct dpsw_cmd_if_set_max_frame_length {
__le16 if_id;
__le16 frame_length;
};
struct dpsw_cmd_if_set_link_cfg {
/* cmd word 0 */
__le16 if_id;
u8 pad[6];
/* cmd word 1 */
__le32 rate;
__le32 pad1;
/* cmd word 2 */
__le64 options;
};
struct dpsw_cmd_if_get_link_state {
__le16 if_id;
};
#define DPSW_UP_SHIFT 0
#define DPSW_UP_SIZE 1
struct dpsw_rsp_if_get_link_state {
/* cmd word 0 */
__le32 pad0;
u8 up;
u8 pad1[3];
/* cmd word 1 */
__le32 rate;
__le32 pad2;
/* cmd word 2 */
__le64 options;
};
struct dpsw_vlan_add {
__le16 fdb_id;
__le16 vlan_id;
};
struct dpsw_cmd_vlan_add_if {
/* cmd word 0 */
__le16 options;
__le16 vlan_id;
__le16 fdb_id;
__le16 pad0;
/* cmd word 1-4 */
__le64 if_id;
};
struct dpsw_cmd_vlan_manage_if {
/* cmd word 0 */
__le16 pad0;
__le16 vlan_id;
__le32 pad1;
/* cmd word 1-4 */
__le64 if_id;
};
struct dpsw_cmd_vlan_remove {
__le16 pad;
__le16 vlan_id;
};
struct dpsw_cmd_fdb_add {
__le32 pad;
__le16 fdb_ageing_time;
__le16 num_fdb_entries;
};
struct dpsw_rsp_fdb_add {
__le16 fdb_id;
};
struct dpsw_cmd_fdb_remove {
__le16 fdb_id;
};
#define DPSW_ENTRY_TYPE_SHIFT 0
#define DPSW_ENTRY_TYPE_SIZE 4
struct dpsw_cmd_fdb_unicast_op {
/* cmd word 0 */
__le16 fdb_id;
u8 mac_addr[6];
/* cmd word 1 */
__le16 if_egress;
/* only the first 4 bits from LSB */
u8 type;
};
struct dpsw_cmd_fdb_multicast_op {
/* cmd word 0 */
__le16 fdb_id;
__le16 num_ifs;
/* only the first 4 bits from LSB */
u8 type;
u8 pad[3];
/* cmd word 1 */
u8 mac_addr[6];
__le16 pad2;
/* cmd word 2-5 */
__le64 if_id;
};
struct dpsw_cmd_fdb_dump {
__le16 fdb_id;
__le16 pad0;
__le32 pad1;
__le64 iova_addr;
__le32 iova_size;
};
struct dpsw_rsp_fdb_dump {
__le16 num_entries;
};
struct dpsw_rsp_ctrl_if_get_attr {
__le64 pad;
__le32 rx_fqid;
__le32 rx_err_fqid;
__le32 tx_err_conf_fqid;
};
#define DPSW_BACKUP_POOL(val, order) (((val) & 0x1) << (order))
struct dpsw_cmd_ctrl_if_set_pools {
u8 num_dpbp;
u8 backup_pool_mask;
__le16 pad;
__le32 dpbp_id[DPSW_MAX_DPBP];
__le16 buffer_size[DPSW_MAX_DPBP];
};
#define DPSW_DEST_TYPE_SHIFT 0
#define DPSW_DEST_TYPE_SIZE 4
struct dpsw_cmd_ctrl_if_set_queue {
__le32 dest_id;
u8 dest_priority;
u8 pad;
/* from LSB: dest_type:4 */
u8 dest_type;
u8 qtype;
__le64 user_ctx;
__le32 options;
};
struct dpsw_rsp_get_api_version {
__le16 version_major;
__le16 version_minor;
};
struct dpsw_rsp_if_get_mac_addr {
__le16 pad;
u8 mac_addr[6];
};
struct dpsw_cmd_set_egress_flood {
__le16 fdb_id;
u8 flood_type;
u8 pad[5];
__le64 if_id;
};
#define DPSW_LEARNING_MODE_SHIFT 0
#define DPSW_LEARNING_MODE_SIZE 4
struct dpsw_cmd_if_set_learning_mode {
__le16 if_id;
/* only the first 4 bits from LSB */
u8 mode;
};
struct dpsw_cmd_acl_add {
__le16 pad;
__le16 max_entries;
};
struct dpsw_rsp_acl_add {
__le16 acl_id;
};
struct dpsw_cmd_acl_remove {
__le16 acl_id;
};
struct dpsw_cmd_acl_if {
__le16 acl_id;
__le16 num_ifs;
__le32 pad;
__le64 if_id;
};
struct dpsw_prep_acl_entry {
u8 match_l2_dest_mac[6];
__le16 match_l2_tpid;
u8 match_l2_source_mac[6];
__le16 match_l2_vlan_id;
__le32 match_l3_dest_ip;
__le32 match_l3_source_ip;
__le16 match_l4_dest_port;
__le16 match_l4_source_port;
__le16 match_l2_ether_type;
u8 match_l2_pcp_dei;
u8 match_l3_dscp;
u8 mask_l2_dest_mac[6];
__le16 mask_l2_tpid;
u8 mask_l2_source_mac[6];
__le16 mask_l2_vlan_id;
__le32 mask_l3_dest_ip;
__le32 mask_l3_source_ip;
__le16 mask_l4_dest_port;
__le16 mask_l4_source_port;
__le16 mask_l2_ether_type;
u8 mask_l2_pcp_dei;
u8 mask_l3_dscp;
u8 match_l3_protocol;
u8 mask_l3_protocol;
};
#define DPSW_RESULT_ACTION_SHIFT 0
#define DPSW_RESULT_ACTION_SIZE 4
struct dpsw_cmd_acl_entry {
__le16 acl_id;
__le16 result_if_id;
__le32 precedence;
/* from LSB only the first 4 bits */
u8 result_action;
u8 pad[7];
__le64 pad2[4];
__le64 key_iova;
};
struct dpsw_cmd_set_reflection_if {
__le16 if_id;
};
#define DPSW_FILTER_SHIFT 0
#define DPSW_FILTER_SIZE 2
struct dpsw_cmd_if_reflection {
__le16 if_id;
__le16 vlan_id;
/* only 2 bits from the LSB */
u8 filter;
};
#pragma pack(pop)
#endif /* __FSL_DPSW_CMD_H */
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpsw.c
+1661
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/freescale/dpaa2/dpsw.h
+791
View File
@@ -0,0 +1,791 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2017-2021 NXP
*
*/
#ifndef __FSL_DPSW_H
#define __FSL_DPSW_H
/* Data Path L2-Switch API
* Contains API for handling DPSW topology and functionality
*/
struct fsl_mc_io;
/* DPSW general definitions */
#define DPSW_MAX_PRIORITIES 8
#define DPSW_MAX_IF 64
int dpsw_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpsw_id, u16 *token);
int dpsw_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
/* DPSW options */
/**
* DPSW_OPT_FLOODING_DIS - Flooding was disabled at device create
*/
#define DPSW_OPT_FLOODING_DIS 0x0000000000000001ULL
/**
* DPSW_OPT_MULTICAST_DIS - Multicast was disabled at device create
*/
#define DPSW_OPT_MULTICAST_DIS 0x0000000000000004ULL
/**
* DPSW_OPT_CTRL_IF_DIS - Control interface support is disabled
*/
#define DPSW_OPT_CTRL_IF_DIS 0x0000000000000010ULL
/**
* enum dpsw_component_type - component type of a bridge
* @DPSW_COMPONENT_TYPE_C_VLAN: A C-VLAN component of an
* enterprise VLAN bridge or of a Provider Bridge used
* to process C-tagged frames
* @DPSW_COMPONENT_TYPE_S_VLAN: An S-VLAN component of a
* Provider Bridge
*
*/
enum dpsw_component_type {
DPSW_COMPONENT_TYPE_C_VLAN = 0,
DPSW_COMPONENT_TYPE_S_VLAN
};
/**
* enum dpsw_flooding_cfg - flooding configuration requested
* @DPSW_FLOODING_PER_VLAN: Flooding replicators are allocated per VLAN and
* interfaces present in each of them can be configured using
* dpsw_vlan_add_if_flooding()/dpsw_vlan_remove_if_flooding().
* This is the default configuration.
*
* @DPSW_FLOODING_PER_FDB: Flooding replicators are allocated per FDB and
* interfaces present in each of them can be configured using
* dpsw_set_egress_flood().
*/
enum dpsw_flooding_cfg {
DPSW_FLOODING_PER_VLAN = 0,
DPSW_FLOODING_PER_FDB,
};
/**
* enum dpsw_broadcast_cfg - broadcast configuration requested
* @DPSW_BROADCAST_PER_OBJECT: There is only one broadcast replicator per DPSW
* object. This is the default configuration.
* @DPSW_BROADCAST_PER_FDB: Broadcast replicators are allocated per FDB and
* interfaces present in each of them can be configured using
* dpsw_set_egress_flood().
*/
enum dpsw_broadcast_cfg {
DPSW_BROADCAST_PER_OBJECT = 0,
DPSW_BROADCAST_PER_FDB,
};
int dpsw_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
int dpsw_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
int dpsw_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
/* DPSW IRQ Index and Events */
#define DPSW_IRQ_INDEX_IF 0x0000
#define DPSW_IRQ_INDEX_L2SW 0x0001
/**
* DPSW_IRQ_EVENT_LINK_CHANGED - Indicates that the link state changed
*/
#define DPSW_IRQ_EVENT_LINK_CHANGED 0x0001
/**
* DPSW_IRQ_EVENT_ENDPOINT_CHANGED - Indicates a change in endpoint
*/
#define DPSW_IRQ_EVENT_ENDPOINT_CHANGED 0x0002
/**
* struct dpsw_irq_cfg - IRQ configuration
* @addr: Address that must be written to signal a message-based interrupt
* @val: Value to write into irq_addr address
* @irq_num: A user defined number associated with this IRQ
*/
struct dpsw_irq_cfg {
u64 addr;
u32 val;
int irq_num;
};
int dpsw_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u8 en);
int dpsw_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u32 mask);
int dpsw_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u32 *status);
int dpsw_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u32 status);
/**
* struct dpsw_attr - Structure representing DPSW attributes
* @id: DPSW object ID
* @options: Enable/Disable DPSW features
* @max_vlans: Maximum Number of VLANs
* @max_meters_per_if: Number of meters per interface
* @max_fdbs: Maximum Number of FDBs
* @max_fdb_entries: Number of FDB entries for default FDB table;
* 0 - indicates default 1024 entries.
* @fdb_aging_time: Default FDB aging time for default FDB table;
* 0 - indicates default 300 seconds
* @max_fdb_mc_groups: Number of multicast groups in each FDB table;
* 0 - indicates default 32
* @mem_size: DPSW frame storage memory size
* @num_ifs: Number of interfaces
* @num_vlans: Current number of VLANs
* @num_fdbs: Current number of FDBs
* @component_type: Component type of this bridge
* @flooding_cfg: Flooding configuration (PER_VLAN - default, PER_FDB)
* @broadcast_cfg: Broadcast configuration (PER_OBJECT - default, PER_FDB)
*/
struct dpsw_attr {
int id;
u64 options;
u16 max_vlans;
u8 max_meters_per_if;
u8 max_fdbs;
u16 max_fdb_entries;
u16 fdb_aging_time;
u16 max_fdb_mc_groups;
u16 num_ifs;
u16 mem_size;
u16 num_vlans;
u8 num_fdbs;
enum dpsw_component_type component_type;
enum dpsw_flooding_cfg flooding_cfg;
enum dpsw_broadcast_cfg broadcast_cfg;
};
int dpsw_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
struct dpsw_attr *attr);
/**
* struct dpsw_ctrl_if_attr - Control interface attributes
* @rx_fqid: Receive FQID
* @rx_err_fqid: Receive error FQID
* @tx_err_conf_fqid: Transmit error and confirmation FQID
*/
struct dpsw_ctrl_if_attr {
u32 rx_fqid;
u32 rx_err_fqid;
u32 tx_err_conf_fqid;
};
int dpsw_ctrl_if_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token, struct dpsw_ctrl_if_attr *attr);
enum dpsw_queue_type {
DPSW_QUEUE_RX,
DPSW_QUEUE_TX_ERR_CONF,
DPSW_QUEUE_RX_ERR,
};
#define DPSW_MAX_DPBP 8
/**
* struct dpsw_ctrl_if_pools_cfg - Control interface buffer pools configuration
* @num_dpbp: Number of DPBPs
* @pools: Array of buffer pools parameters; The number of valid entries
* must match 'num_dpbp' value
* @pools.dpbp_id: DPBP object ID
* @pools.buffer_size: Buffer size
* @pools.backup_pool: Backup pool
*/
struct dpsw_ctrl_if_pools_cfg {
u8 num_dpbp;
struct {
int dpbp_id;
u16 buffer_size;
int backup_pool;
} pools[DPSW_MAX_DPBP];
};
int dpsw_ctrl_if_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
const struct dpsw_ctrl_if_pools_cfg *cfg);
#define DPSW_CTRL_IF_QUEUE_OPT_USER_CTX 0x00000001
#define DPSW_CTRL_IF_QUEUE_OPT_DEST 0x00000002
enum dpsw_ctrl_if_dest {
DPSW_CTRL_IF_DEST_NONE = 0,
DPSW_CTRL_IF_DEST_DPIO = 1,
};
struct dpsw_ctrl_if_dest_cfg {
enum dpsw_ctrl_if_dest dest_type;
int dest_id;
u8 priority;
};
struct dpsw_ctrl_if_queue_cfg {
u32 options;
u64 user_ctx;
struct dpsw_ctrl_if_dest_cfg dest_cfg;
};
int dpsw_ctrl_if_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
enum dpsw_queue_type qtype,
const struct dpsw_ctrl_if_queue_cfg *cfg);
int dpsw_ctrl_if_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
int dpsw_ctrl_if_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
/**
* enum dpsw_action - Action selection for special/control frames
* @DPSW_ACTION_DROP: Drop frame
* @DPSW_ACTION_REDIRECT: Redirect frame to control port
*/
enum dpsw_action {
DPSW_ACTION_DROP = 0,
DPSW_ACTION_REDIRECT = 1
};
#define DPSW_LINK_OPT_AUTONEG 0x0000000000000001ULL
#define DPSW_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
#define DPSW_LINK_OPT_PAUSE 0x0000000000000004ULL
#define DPSW_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
/**
* struct dpsw_link_cfg - Structure representing DPSW link configuration
* @rate: Rate
* @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
*/
struct dpsw_link_cfg {
u32 rate;
u64 options;
};
int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 if_id,
struct dpsw_link_cfg *cfg);
/**
* struct dpsw_link_state - Structure representing DPSW link state
* @rate: Rate
* @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
* @up: 0 - covers two cases: down and disconnected, 1 - up
*/
struct dpsw_link_state {
u32 rate;
u64 options;
u8 up;
};
int dpsw_if_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, struct dpsw_link_state *state);
/**
* struct dpsw_tci_cfg - Tag Control Information (TCI) configuration
* @pcp: Priority Code Point (PCP): a 3-bit field which refers
* to the IEEE 802.1p priority
* @dei: Drop Eligible Indicator (DEI): a 1-bit field. May be used
* separately or in conjunction with PCP to indicate frames
* eligible to be dropped in the presence of congestion
* @vlan_id: VLAN Identifier (VID): a 12-bit field specifying the VLAN
* to which the frame belongs. The hexadecimal values
* of 0x000 and 0xFFF are reserved;
* all other values may be used as VLAN identifiers,
* allowing up to 4,094 VLANs
*/
struct dpsw_tci_cfg {
u8 pcp;
u8 dei;
u16 vlan_id;
};
int dpsw_if_set_tci(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 if_id,
const struct dpsw_tci_cfg *cfg);
int dpsw_if_get_tci(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 if_id,
struct dpsw_tci_cfg *cfg);
/**
* enum dpsw_stp_state - Spanning Tree Protocol (STP) states
* @DPSW_STP_STATE_DISABLED: Disabled state
* @DPSW_STP_STATE_LISTENING: Listening state
* @DPSW_STP_STATE_LEARNING: Learning state
* @DPSW_STP_STATE_FORWARDING: Forwarding state
* @DPSW_STP_STATE_BLOCKING: Blocking state
*
*/
enum dpsw_stp_state {
DPSW_STP_STATE_DISABLED = 0,
DPSW_STP_STATE_LISTENING = 1,
DPSW_STP_STATE_LEARNING = 2,
DPSW_STP_STATE_FORWARDING = 3,
DPSW_STP_STATE_BLOCKING = 0
};
/**
* struct dpsw_stp_cfg - Spanning Tree Protocol (STP) Configuration
* @vlan_id: VLAN ID STP state
* @state: STP state
*/
struct dpsw_stp_cfg {
u16 vlan_id;
enum dpsw_stp_state state;
};
int dpsw_if_set_stp(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 if_id,
const struct dpsw_stp_cfg *cfg);
/**
* enum dpsw_accepted_frames - Types of frames to accept
* @DPSW_ADMIT_ALL: The device accepts VLAN tagged, untagged and
* priority tagged frames
* @DPSW_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
* Priority-Tagged frames received on this interface.
*
*/
enum dpsw_accepted_frames {
DPSW_ADMIT_ALL = 1,
DPSW_ADMIT_ONLY_VLAN_TAGGED = 3
};
/**
* enum dpsw_counter - Counters types
* @DPSW_CNT_ING_FRAME: Counts ingress frames
* @DPSW_CNT_ING_BYTE: Counts ingress bytes
* @DPSW_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
* @DPSW_CNT_ING_FRAME_DISCARD: Counts discarded ingress frame
* @DPSW_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
* @DPSW_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
* @DPSW_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
* @DPSW_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
* @DPSW_CNT_EGR_FRAME: Counts egress frames
* @DPSW_CNT_EGR_BYTE: Counts egress bytes
* @DPSW_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
* @DPSW_CNT_EGR_STP_FRAME_DISCARD: Counts egress STP discarded frames
* @DPSW_CNT_ING_NO_BUFF_DISCARD: Counts ingress no buffer discarded frames
*/
enum dpsw_counter {
DPSW_CNT_ING_FRAME = 0x0,
DPSW_CNT_ING_BYTE = 0x1,
DPSW_CNT_ING_FLTR_FRAME = 0x2,
DPSW_CNT_ING_FRAME_DISCARD = 0x3,
DPSW_CNT_ING_MCAST_FRAME = 0x4,
DPSW_CNT_ING_MCAST_BYTE = 0x5,
DPSW_CNT_ING_BCAST_FRAME = 0x6,
DPSW_CNT_ING_BCAST_BYTES = 0x7,
DPSW_CNT_EGR_FRAME = 0x8,
DPSW_CNT_EGR_BYTE = 0x9,
DPSW_CNT_EGR_FRAME_DISCARD = 0xa,
DPSW_CNT_EGR_STP_FRAME_DISCARD = 0xb,
DPSW_CNT_ING_NO_BUFF_DISCARD = 0xc,
};
int dpsw_if_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, enum dpsw_counter type, u64 *counter);
int dpsw_if_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 if_id);
int dpsw_if_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 if_id);
/**
* struct dpsw_if_attr - Structure representing DPSW interface attributes
* @num_tcs: Number of traffic classes
* @rate: Transmit rate in bits per second
* @options: Interface configuration options (bitmap)
* @enabled: Indicates if interface is enabled
* @accept_all_vlan: The device discards/accepts incoming frames
* for VLANs that do not include this interface
* @admit_untagged: When set to 'DPSW_ADMIT_ONLY_VLAN_TAGGED', the device
* discards untagged frames or priority-tagged frames received on
* this interface;
* When set to 'DPSW_ADMIT_ALL', untagged frames or priority-
* tagged frames received on this interface are accepted
* @qdid: control frames transmit qdid
*/
struct dpsw_if_attr {
u8 num_tcs;
u32 rate;
u32 options;
int enabled;
int accept_all_vlan;
enum dpsw_accepted_frames admit_untagged;
u16 qdid;
};
int dpsw_if_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, struct dpsw_if_attr *attr);
int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, u16 frame_length);
/**
* struct dpsw_vlan_cfg - VLAN Configuration
* @fdb_id: Forwarding Data Base
*/
struct dpsw_vlan_cfg {
u16 fdb_id;
};
int dpsw_vlan_add(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 vlan_id, const struct dpsw_vlan_cfg *cfg);
#define DPSW_VLAN_ADD_IF_OPT_FDB_ID 0x0001
/**
* struct dpsw_vlan_if_cfg - Set of VLAN Interfaces
* @num_ifs: The number of interfaces that are assigned to the egress
* list for this VLAN
* @if_id: The set of interfaces that are
* assigned to the egress list for this VLAN
* @options: Options map for this command (DPSW_VLAN_ADD_IF_OPT_FDB_ID)
* @fdb_id: FDB id to be used by this VLAN on these specific interfaces
* (taken into account only if the DPSW_VLAN_ADD_IF_OPT_FDB_ID is
* specified in the options field)
*/
struct dpsw_vlan_if_cfg {
u16 num_ifs;
u16 options;
u16 if_id[DPSW_MAX_IF];
u16 fdb_id;
};
int dpsw_vlan_add_if(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg);
int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg);
int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg);
int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg);
int dpsw_vlan_remove(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 vlan_id);
/**
* enum dpsw_fdb_entry_type - FDB Entry type - Static/Dynamic
* @DPSW_FDB_ENTRY_STATIC: Static entry
* @DPSW_FDB_ENTRY_DINAMIC: Dynamic entry
*/
enum dpsw_fdb_entry_type {
DPSW_FDB_ENTRY_STATIC = 0,
DPSW_FDB_ENTRY_DINAMIC = 1
};
/**
* struct dpsw_fdb_unicast_cfg - Unicast entry configuration
* @type: Select static or dynamic entry
* @mac_addr: MAC address
* @if_egress: Egress interface ID
*/
struct dpsw_fdb_unicast_cfg {
enum dpsw_fdb_entry_type type;
u8 mac_addr[6];
u16 if_egress;
};
int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 fdb_id, const struct dpsw_fdb_unicast_cfg *cfg);
int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 fdb_id, const struct dpsw_fdb_unicast_cfg *cfg);
#define DPSW_FDB_ENTRY_TYPE_DYNAMIC BIT(0)
#define DPSW_FDB_ENTRY_TYPE_UNICAST BIT(1)
/**
* struct fdb_dump_entry - fdb snapshot entry
* @mac_addr: MAC address
* @type: bit0 - DINAMIC(1)/STATIC(0), bit1 - UNICAST(1)/MULTICAST(0)
* @if_info: unicast - egress interface, multicast - number of egress interfaces
* @if_mask: multicast - egress interface mask
*/
struct fdb_dump_entry {
u8 mac_addr[6];
u8 type;
u8 if_info;
u8 if_mask[8];
};
int dpsw_fdb_dump(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 fdb_id,
u64 iova_addr, u32 iova_size, u16 *num_entries);
/**
* struct dpsw_fdb_multicast_cfg - Multi-cast entry configuration
* @type: Select static or dynamic entry
* @mac_addr: MAC address
* @num_ifs: Number of external and internal interfaces
* @if_id: Egress interface IDs
*/
struct dpsw_fdb_multicast_cfg {
enum dpsw_fdb_entry_type type;
u8 mac_addr[6];
u16 num_ifs;
u16 if_id[DPSW_MAX_IF];
};
int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 fdb_id, const struct dpsw_fdb_multicast_cfg *cfg);
int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 fdb_id, const struct dpsw_fdb_multicast_cfg *cfg);
/**
* enum dpsw_learning_mode - Auto-learning modes
* @DPSW_LEARNING_MODE_DIS: Disable Auto-learning
* @DPSW_LEARNING_MODE_HW: Enable HW auto-Learning
* @DPSW_LEARNING_MODE_NON_SECURE: Enable None secure learning by CPU
* @DPSW_LEARNING_MODE_SECURE: Enable secure learning by CPU
*
* NONE - SECURE LEARNING
* SMAC found DMAC found CTLU Action
* v v Forward frame to
* 1. DMAC destination
* - v Forward frame to
* 1. DMAC destination
* 2. Control interface
* v - Forward frame to
* 1. Flooding list of interfaces
* - - Forward frame to
* 1. Flooding list of interfaces
* 2. Control interface
* SECURE LEARING
* SMAC found DMAC found CTLU Action
* v v Forward frame to
* 1. DMAC destination
* - v Forward frame to
* 1. Control interface
* v - Forward frame to
* 1. Flooding list of interfaces
* - - Forward frame to
* 1. Control interface
*/
enum dpsw_learning_mode {
DPSW_LEARNING_MODE_DIS = 0,
DPSW_LEARNING_MODE_HW = 1,
DPSW_LEARNING_MODE_NON_SECURE = 2,
DPSW_LEARNING_MODE_SECURE = 3
};
/**
* struct dpsw_fdb_attr - FDB Attributes
* @max_fdb_entries: Number of FDB entries
* @fdb_ageing_time: Ageing time in seconds
* @learning_mode: Learning mode
* @num_fdb_mc_groups: Current number of multicast groups
* @max_fdb_mc_groups: Maximum number of multicast groups
*/
struct dpsw_fdb_attr {
u16 max_fdb_entries;
u16 fdb_ageing_time;
enum dpsw_learning_mode learning_mode;
u16 num_fdb_mc_groups;
u16 max_fdb_mc_groups;
};
int dpsw_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 *major_ver, u16 *minor_ver);
int dpsw_if_get_port_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, u8 mac_addr[6]);
/**
* struct dpsw_fdb_cfg - FDB Configuration
* @num_fdb_entries: Number of FDB entries
* @fdb_ageing_time: Ageing time in seconds
*/
struct dpsw_fdb_cfg {
u16 num_fdb_entries;
u16 fdb_ageing_time;
};
int dpsw_fdb_add(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 *fdb_id,
const struct dpsw_fdb_cfg *cfg);
int dpsw_fdb_remove(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 fdb_id);
/**
* enum dpsw_flood_type - Define the flood type of a DPSW object
* @DPSW_BROADCAST: Broadcast flooding
* @DPSW_FLOODING: Unknown flooding
*/
enum dpsw_flood_type {
DPSW_BROADCAST = 0,
DPSW_FLOODING,
};
struct dpsw_egress_flood_cfg {
u16 fdb_id;
enum dpsw_flood_type flood_type;
u16 num_ifs;
u16 if_id[DPSW_MAX_IF];
};
int dpsw_set_egress_flood(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
const struct dpsw_egress_flood_cfg *cfg);
int dpsw_if_set_learning_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, enum dpsw_learning_mode mode);
/**
* struct dpsw_acl_cfg - ACL Configuration
* @max_entries: Number of ACL rules
*/
struct dpsw_acl_cfg {
u16 max_entries;
};
int dpsw_acl_add(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u16 *acl_id,
const struct dpsw_acl_cfg *cfg);
int dpsw_acl_remove(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 acl_id);
/**
* struct dpsw_acl_if_cfg - List of interfaces to associate with an ACL table
* @num_ifs: Number of interfaces
* @if_id: List of interfaces
*/
struct dpsw_acl_if_cfg {
u16 num_ifs;
u16 if_id[DPSW_MAX_IF];
};
int dpsw_acl_add_if(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 acl_id, const struct dpsw_acl_if_cfg *cfg);
int dpsw_acl_remove_if(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 acl_id, const struct dpsw_acl_if_cfg *cfg);
/**
* struct dpsw_acl_fields - ACL fields.
* @l2_dest_mac: Destination MAC address: BPDU, Multicast, Broadcast, Unicast,
* slow protocols, MVRP, STP
* @l2_source_mac: Source MAC address
* @l2_tpid: Layer 2 (Ethernet) protocol type, used to identify the following
* protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae,
* Q-in-Q, IPv4, IPv6, PPPoE
* @l2_pcp_dei: indicate which protocol is encapsulated in the payload
* @l2_vlan_id: layer 2 VLAN ID
* @l2_ether_type: layer 2 Ethernet type
* @l3_dscp: Layer 3 differentiated services code point
* @l3_protocol: Tells the Network layer at the destination host, to which
* Protocol this packet belongs to. The following protocol are
* supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6
* (encapsulation), GRE, PTP
* @l3_source_ip: Source IPv4 IP
* @l3_dest_ip: Destination IPv4 IP
* @l4_source_port: Source TCP/UDP Port
* @l4_dest_port: Destination TCP/UDP Port
*/
struct dpsw_acl_fields {
u8 l2_dest_mac[6];
u8 l2_source_mac[6];
u16 l2_tpid;
u8 l2_pcp_dei;
u16 l2_vlan_id;
u16 l2_ether_type;
u8 l3_dscp;
u8 l3_protocol;
u32 l3_source_ip;
u32 l3_dest_ip;
u16 l4_source_port;
u16 l4_dest_port;
};
/**
* struct dpsw_acl_key - ACL key
* @match: Match fields
* @mask: Mask: b'1 - valid, b'0 don't care
*/
struct dpsw_acl_key {
struct dpsw_acl_fields match;
struct dpsw_acl_fields mask;
};
/**
* enum dpsw_acl_action - action to be run on the ACL rule match
* @DPSW_ACL_ACTION_DROP: Drop frame
* @DPSW_ACL_ACTION_REDIRECT: Redirect to certain port
* @DPSW_ACL_ACTION_ACCEPT: Accept frame
* @DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF: Redirect to control interface
*/
enum dpsw_acl_action {
DPSW_ACL_ACTION_DROP,
DPSW_ACL_ACTION_REDIRECT,
DPSW_ACL_ACTION_ACCEPT,
DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF
};
/**
* struct dpsw_acl_result - ACL action
* @action: Action should be taken when ACL entry hit
* @if_id: Interface IDs to redirect frame. Valid only if redirect selected for
* action
*/
struct dpsw_acl_result {
enum dpsw_acl_action action;
u16 if_id;
};
/**
* struct dpsw_acl_entry_cfg - ACL entry
* @key_iova: I/O virtual address of DMA-able memory filled with key after call
* to dpsw_acl_prepare_entry_cfg()
* @result: Required action when entry hit occurs
* @precedence: Precedence inside ACL 0 is lowest; This priority can not change
* during the lifetime of a Policy. It is user responsibility to
* space the priorities according to consequent rule additions.
*/
struct dpsw_acl_entry_cfg {
u64 key_iova;
struct dpsw_acl_result result;
int precedence;
};
void dpsw_acl_prepare_entry_cfg(const struct dpsw_acl_key *key,
u8 *entry_cfg_buf);
int dpsw_acl_add_entry(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 acl_id, const struct dpsw_acl_entry_cfg *cfg);
int dpsw_acl_remove_entry(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 acl_id, const struct dpsw_acl_entry_cfg *cfg);
/**
* enum dpsw_reflection_filter - Filter type for frames to be reflected
* @DPSW_REFLECTION_FILTER_INGRESS_ALL: Reflect all frames
* @DPSW_REFLECTION_FILTER_INGRESS_VLAN: Reflect only frames that belong to
* the particular VLAN defined by vid parameter
*
*/
enum dpsw_reflection_filter {
DPSW_REFLECTION_FILTER_INGRESS_ALL = 0,
DPSW_REFLECTION_FILTER_INGRESS_VLAN = 1
};
/**
* struct dpsw_reflection_cfg - Structure representing the mirroring config
* @filter: Filter type for frames to be mirrored
* @vlan_id: VLAN ID to mirror; valid only when the type is DPSW_INGRESS_VLAN
*/
struct dpsw_reflection_cfg {
enum dpsw_reflection_filter filter;
u16 vlan_id;
};
int dpsw_set_reflection_if(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id);
int dpsw_if_add_reflection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, const struct dpsw_reflection_cfg *cfg);
int dpsw_if_remove_reflection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u16 if_id, const struct dpsw_reflection_cfg *cfg);
#endif /* __FSL_DPSW_H */