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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/net/ethernet/freescale/fman/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
config FSL_FMAN
tristate "FMan support"
depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
select GENERIC_ALLOCATOR
select PHYLINK
select PCS_LYNX
select CRC32
default n
help
Freescale Data-Path Acceleration Architecture Frame Manager
(FMan) support
config DPAA_ERRATUM_A050385
bool
depends on ARM64 && FSL_DPAA
default y
help
DPAA FMan erratum A050385 software workaround implementation:
align buffers, data start, SG fragment length to avoid FMan DMA
splits.
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any
one of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
linux-7.2.3/drivers/net/ethernet/freescale/fman/Makefile
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# SPDX-License-Identifier: GPL-2.0
subdir-ccflags-y += -I$(srctree)/drivers/net/ethernet/freescale/fman
obj-$(CONFIG_FSL_FMAN) += fsl_dpaa_fman.o
obj-$(CONFIG_FSL_FMAN) += fsl_dpaa_fman_port.o
obj-$(CONFIG_FSL_FMAN) += fsl_dpaa_mac.o
fsl_dpaa_fman-objs := fman_muram.o fman.o fman_sp.o fman_keygen.o
fsl_dpaa_fman_port-objs := fman_port.o
fsl_dpaa_mac-objs:= mac.o fman_dtsec.o fman_memac.o fman_tgec.o
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman.c
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linux-7.2.3/drivers/net/ethernet/freescale/fman/fman.h
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/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
#ifndef __FM_H
#define __FM_H
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
/* FM Frame descriptor macros */
/* Frame queue Context Override */
#define FM_FD_CMD_FCO 0x80000000
#define FM_FD_CMD_RPD 0x40000000 /* Read Prepended Data */
#define FM_FD_CMD_UPD 0x20000000 /* Update Prepended Data */
#define FM_FD_CMD_DTC 0x10000000 /* Do L4 Checksum */
/* TX-Port: Unsupported Format */
#define FM_FD_ERR_UNSUPPORTED_FORMAT 0x04000000
/* TX Port: Length Error */
#define FM_FD_ERR_LENGTH 0x02000000
#define FM_FD_ERR_DMA 0x01000000 /* DMA Data error */
/* IPR frame (not error) */
#define FM_FD_IPR 0x00000001
/* IPR non-consistent-sp */
#define FM_FD_ERR_IPR_NCSP (0x00100000 | FM_FD_IPR)
/* IPR error */
#define FM_FD_ERR_IPR (0x00200000 | FM_FD_IPR)
/* IPR timeout */
#define FM_FD_ERR_IPR_TO (0x00300000 | FM_FD_IPR)
/* TX Port: Length Error */
#define FM_FD_ERR_IPRE (FM_FD_ERR_IPR & ~FM_FD_IPR)
/* Rx FIFO overflow, FCS error, code error, running disparity error
* (SGMII and TBI modes), FIFO parity error. PHY Sequence error,
* PHY error control character detected.
*/
#define FM_FD_ERR_PHYSICAL 0x00080000
/* Frame too long OR Frame size exceeds max_length_frame */
#define FM_FD_ERR_SIZE 0x00040000
/* classification discard */
#define FM_FD_ERR_CLS_DISCARD 0x00020000
/* Extract Out of Frame */
#define FM_FD_ERR_EXTRACTION 0x00008000
/* No Scheme Selected */
#define FM_FD_ERR_NO_SCHEME 0x00004000
/* Keysize Overflow */
#define FM_FD_ERR_KEYSIZE_OVERFLOW 0x00002000
/* Frame color is red */
#define FM_FD_ERR_COLOR_RED 0x00000800
/* Frame color is yellow */
#define FM_FD_ERR_COLOR_YELLOW 0x00000400
/* Parser Time out Exceed */
#define FM_FD_ERR_PRS_TIMEOUT 0x00000080
/* Invalid Soft Parser instruction */
#define FM_FD_ERR_PRS_ILL_INSTRUCT 0x00000040
/* Header error was identified during parsing */
#define FM_FD_ERR_PRS_HDR_ERR 0x00000020
/* Frame parsed beyind 256 first bytes */
#define FM_FD_ERR_BLOCK_LIMIT_EXCEEDED 0x00000008
/* non Frame-Manager error */
#define FM_FD_RX_STATUS_ERR_NON_FM 0x00400000
/* FMan driver defines */
#define FMAN_BMI_FIFO_UNITS 0x100
#define OFFSET_UNITS 16
/* BMan defines */
#define BM_MAX_NUM_OF_POOLS 64 /* Buffers pools */
#define FMAN_PORT_MAX_EXT_POOLS_NUM 8 /* External BM pools per Rx port */
/* General defines */
#define MAX_NUM_OF_MACS 10
struct fman; /* FMan data */
/* Enum for defining port types */
enum fman_port_type {
FMAN_PORT_TYPE_TX = 0, /* TX Port */
FMAN_PORT_TYPE_RX, /* RX Port */
};
struct fman_rev_info {
u8 major; /* Major revision */
u8 minor; /* Minor revision */
};
enum fman_exceptions {
FMAN_EX_DMA_BUS_ERROR = 0, /* DMA bus error. */
FMAN_EX_DMA_READ_ECC, /* Read Buffer ECC error */
FMAN_EX_DMA_SYSTEM_WRITE_ECC, /* Write Buffer ECC err on sys side */
FMAN_EX_DMA_FM_WRITE_ECC, /* Write Buffer ECC error on FM side */
FMAN_EX_DMA_SINGLE_PORT_ECC, /* Single Port ECC error on FM side */
FMAN_EX_FPM_STALL_ON_TASKS, /* Stall of tasks on FPM */
FMAN_EX_FPM_SINGLE_ECC, /* Single ECC on FPM. */
FMAN_EX_FPM_DOUBLE_ECC, /* Double ECC error on FPM ram access */
FMAN_EX_QMI_SINGLE_ECC, /* Single ECC on QMI. */
FMAN_EX_QMI_DOUBLE_ECC, /* Double bit ECC occurred on QMI */
FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/* DeQ from unknown port id */
FMAN_EX_BMI_LIST_RAM_ECC, /* Linked List RAM ECC error */
FMAN_EX_BMI_STORAGE_PROFILE_ECC,/* storage profile */
FMAN_EX_BMI_STATISTICS_RAM_ECC,/* Statistics RAM ECC Err Enable */
FMAN_EX_BMI_DISPATCH_RAM_ECC, /* Dispatch RAM ECC Error Enable */
FMAN_EX_IRAM_ECC, /* Double bit ECC occurred on IRAM */
FMAN_EX_MURAM_ECC /* Double bit ECC occurred on MURAM */
};
/* Parse results memory layout */
struct fman_prs_result {
u8 lpid; /* Logical port id */
u8 shimr; /* Shim header result */
__be16 l2r; /* Layer 2 result */
__be16 l3r; /* Layer 3 result */
u8 l4r; /* Layer 4 result */
u8 cplan; /* Classification plan id */
__be16 nxthdr; /* Next Header */
__be16 cksum; /* Running-sum */
/* Flags&fragment-offset field of the last IP-header */
__be16 flags_frag_off;
/* Routing type field of a IPV6 routing extension header */
u8 route_type;
/* Routing Extension Header Present; last bit is IP valid */
u8 rhp_ip_valid;
u8 shim_off[2]; /* Shim offset */
u8 ip_pid_off; /* IP PID (last IP-proto) offset */
u8 eth_off; /* ETH offset */
u8 llc_snap_off; /* LLC_SNAP offset */
u8 vlan_off[2]; /* VLAN offset */
u8 etype_off; /* ETYPE offset */
u8 pppoe_off; /* PPP offset */
u8 mpls_off[2]; /* MPLS offset */
u8 ip_off[2]; /* IP offset */
u8 gre_off; /* GRE offset */
u8 l4_off; /* Layer 4 offset */
u8 nxthdr_off; /* Parser end point */
};
/* A structure for defining buffer prefix area content. */
struct fman_buffer_prefix_content {
/* Number of bytes to be left at the beginning of the external
* buffer; Note that the private-area will start from the base
* of the buffer address.
*/
u16 priv_data_size;
/* true to pass the parse result to/from the FM;
* User may use FM_PORT_GetBufferPrsResult() in
* order to get the parser-result from a buffer.
*/
bool pass_prs_result;
/* true to pass the timeStamp to/from the FM User */
bool pass_time_stamp;
/* true to pass the KG hash result to/from the FM User may
* use FM_PORT_GetBufferHashResult() in order to get the
* parser-result from a buffer.
*/
bool pass_hash_result;
/* Add all other Internal-Context information: AD,
* hash-result, key, etc.
*/
u16 data_align;
};
/* A structure of information about each of the external
* buffer pools used by a port or storage-profile.
*/
struct fman_ext_pool_params {
u8 id; /* External buffer pool id */
u16 size; /* External buffer pool buffer size */
};
/* A structure for informing the driver about the external
* buffer pools allocated in the BM and used by a port or a
* storage-profile.
*/
struct fman_ext_pools {
u8 num_of_pools_used; /* Number of pools use by this port */
struct fman_ext_pool_params ext_buf_pool[FMAN_PORT_MAX_EXT_POOLS_NUM];
/* Parameters for each port */
};
/* A structure for defining BM pool depletion criteria */
struct fman_buf_pool_depletion {
/* select mode in which pause frames will be sent after a
* number of pools (all together!) are depleted
*/
bool pools_grp_mode_enable;
/* the number of depleted pools that will invoke pause
* frames transmission.
*/
u8 num_of_pools;
/* For each pool, true if it should be considered for
* depletion (Note - this pool must be used by this port!).
*/
bool pools_to_consider[BM_MAX_NUM_OF_POOLS];
/* select mode in which pause frames will be sent
* after a single-pool is depleted;
*/
bool single_pool_mode_enable;
/* For each pool, true if it should be considered
* for depletion (Note - this pool must be used by this port!)
*/
bool pools_to_consider_for_single_mode[BM_MAX_NUM_OF_POOLS];
};
/* Enum for inter-module interrupts registration */
enum fman_event_modules {
FMAN_MOD_MAC = 0, /* MAC event */
FMAN_MOD_FMAN_CTRL, /* FMAN Controller */
FMAN_MOD_DUMMY_LAST
};
/* Enum for interrupts types */
enum fman_intr_type {
FMAN_INTR_TYPE_ERR,
FMAN_INTR_TYPE_NORMAL
};
/* Enum for inter-module interrupts registration */
enum fman_inter_module_event {
FMAN_EV_ERR_MAC0 = 0, /* MAC 0 error event */
FMAN_EV_ERR_MAC1, /* MAC 1 error event */
FMAN_EV_ERR_MAC2, /* MAC 2 error event */
FMAN_EV_ERR_MAC3, /* MAC 3 error event */
FMAN_EV_ERR_MAC4, /* MAC 4 error event */
FMAN_EV_ERR_MAC5, /* MAC 5 error event */
FMAN_EV_ERR_MAC6, /* MAC 6 error event */
FMAN_EV_ERR_MAC7, /* MAC 7 error event */
FMAN_EV_ERR_MAC8, /* MAC 8 error event */
FMAN_EV_ERR_MAC9, /* MAC 9 error event */
FMAN_EV_MAC0, /* MAC 0 event (Magic packet detection) */
FMAN_EV_MAC1, /* MAC 1 event (Magic packet detection) */
FMAN_EV_MAC2, /* MAC 2 (Magic packet detection) */
FMAN_EV_MAC3, /* MAC 3 (Magic packet detection) */
FMAN_EV_MAC4, /* MAC 4 (Magic packet detection) */
FMAN_EV_MAC5, /* MAC 5 (Magic packet detection) */
FMAN_EV_MAC6, /* MAC 6 (Magic packet detection) */
FMAN_EV_MAC7, /* MAC 7 (Magic packet detection) */
FMAN_EV_MAC8, /* MAC 8 event (Magic packet detection) */
FMAN_EV_MAC9, /* MAC 9 event (Magic packet detection) */
FMAN_EV_FMAN_CTRL_0, /* Fman controller event 0 */
FMAN_EV_FMAN_CTRL_1, /* Fman controller event 1 */
FMAN_EV_FMAN_CTRL_2, /* Fman controller event 2 */
FMAN_EV_FMAN_CTRL_3, /* Fman controller event 3 */
FMAN_EV_CNT
};
struct fman_intr_src {
void (*isr_cb)(void *src_arg);
void *src_handle;
};
/** fman_exceptions_cb
* fman - Pointer to FMan
* exception - The exception.
*
* Exceptions user callback routine, will be called upon an exception
* passing the exception identification.
*
* Return: irq status
*/
typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman,
enum fman_exceptions exception);
/** fman_bus_error_cb
* fman - Pointer to FMan
* port_id - Port id
* addr - Address that caused the error
* tnum - Owner of error
* liodn - Logical IO device number
*
* Bus error user callback routine, will be called upon bus error,
* passing parameters describing the errors and the owner.
*
* Return: IRQ status
*/
typedef irqreturn_t (fman_bus_error_cb)(struct fman *fman, u8 port_id,
u64 addr, u8 tnum, u16 liodn);
/* Structure that holds information received from device tree */
struct fman_dts_params {
void __iomem *base_addr; /* FMan virtual address */
struct resource *res; /* FMan memory resource */
u8 id; /* FMan ID */
int err_irq; /* FMan Error IRQ */
u16 clk_freq; /* FMan clock freq (In Mhz) */
u32 qman_channel_base; /* QMan channels base */
u32 num_of_qman_channels; /* Number of QMan channels */
struct resource muram_res; /* MURAM resource */
};
struct fman {
struct device *dev;
void __iomem *base_addr;
struct fman_intr_src intr_mng[FMAN_EV_CNT];
struct fman_fpm_regs __iomem *fpm_regs;
struct fman_bmi_regs __iomem *bmi_regs;
struct fman_qmi_regs __iomem *qmi_regs;
struct fman_dma_regs __iomem *dma_regs;
struct fman_hwp_regs __iomem *hwp_regs;
struct fman_kg_regs __iomem *kg_regs;
fman_exceptions_cb *exception_cb;
fman_bus_error_cb *bus_error_cb;
/* Spinlock for FMan use */
spinlock_t spinlock;
struct fman_state_struct *state;
struct fman_cfg *cfg;
struct muram_info *muram;
struct fman_keygen *keygen;
/* cam section in muram */
unsigned long cam_offset;
size_t cam_size;
/* Fifo in MURAM */
unsigned long fifo_offset;
size_t fifo_size;
u32 liodn_base[64];
u32 liodn_offset[64];
struct fman_dts_params dts_params;
};
/* Structure for port-FM communication during fman_port_init. */
struct fman_port_init_params {
u8 port_id; /* port Id */
enum fman_port_type port_type; /* Port type */
u16 port_speed; /* Port speed */
u16 liodn_offset; /* Port's requested resource */
u8 num_of_tasks; /* Port's requested resource */
u8 num_of_extra_tasks; /* Port's requested resource */
u8 num_of_open_dmas; /* Port's requested resource */
u8 num_of_extra_open_dmas; /* Port's requested resource */
u32 size_of_fifo; /* Port's requested resource */
u32 extra_size_of_fifo; /* Port's requested resource */
u8 deq_pipeline_depth; /* Port's requested resource */
u16 max_frame_length; /* Port's max frame length. */
u16 liodn_base;
/* LIODN base for this port, to be used together with LIODN offset. */
};
void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info);
void fman_register_intr(struct fman *fman, enum fman_event_modules mod,
u8 mod_id, enum fman_intr_type intr_type,
void (*f_isr)(void *h_src_arg), void *h_src_arg);
void fman_unregister_intr(struct fman *fman, enum fman_event_modules mod,
u8 mod_id, enum fman_intr_type intr_type);
int fman_set_port_params(struct fman *fman,
struct fman_port_init_params *port_params);
int fman_reset_mac(struct fman *fman, u8 mac_id);
u16 fman_get_clock_freq(struct fman *fman);
u32 fman_get_bmi_max_fifo_size(struct fman *fman);
int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl);
u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id);
struct resource *fman_get_mem_region(struct fman *fman);
u16 fman_get_max_frm(void);
int fman_get_rx_extra_headroom(void);
#ifdef CONFIG_DPAA_ERRATUM_A050385
bool fman_has_errata_a050385(void);
#endif
struct fman *fman_bind(struct device *dev);
#endif /* __FM_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_dtsec.c
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linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_dtsec.h
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/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __DTSEC_H
#define __DTSEC_H
#include "fman_mac.h"
struct mac_device;
int dtsec_initialization(struct mac_device *mac_dev,
struct device_node *mac_node,
struct fman_mac_params *params);
#endif /* __DTSEC_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_keygen.c
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
/*
* Copyright 2017 NXP
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/slab.h>
#include "fman_keygen.h"
/* Maximum number of HW Ports */
#define FMAN_MAX_NUM_OF_HW_PORTS 64
/* Maximum number of KeyGen Schemes */
#define FM_KG_MAX_NUM_OF_SCHEMES 32
/* Number of generic KeyGen Generic Extract Command Registers */
#define FM_KG_NUM_OF_GENERIC_REGS 8
/* Dummy port ID */
#define DUMMY_PORT_ID 0
/* Select Scheme Value Register */
#define KG_SCH_DEF_USE_KGSE_DV_0 2
#define KG_SCH_DEF_USE_KGSE_DV_1 3
/* Registers Shifting values */
#define FM_KG_KGAR_NUM_SHIFT 16
#define KG_SCH_DEF_L4_PORT_SHIFT 8
#define KG_SCH_DEF_IP_ADDR_SHIFT 18
#define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24
/* KeyGen Registers bit field masks: */
/* Enable bit field mask for KeyGen General Configuration Register */
#define FM_KG_KGGCR_EN 0x80000000
/* KeyGen Global Registers bit field masks */
#define FM_KG_KGAR_GO 0x80000000
#define FM_KG_KGAR_READ 0x40000000
#define FM_KG_KGAR_WRITE 0x00000000
#define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
#define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
#define FM_KG_KGAR_ERR 0x20000000
#define FM_KG_KGAR_SEL_CLS_PLAN_ENTRY 0x01000000
#define FM_KG_KGAR_SEL_PORT_ENTRY 0x02000000
#define FM_KG_KGAR_SEL_PORT_WSEL_SP 0x00008000
#define FM_KG_KGAR_SEL_PORT_WSEL_CPP 0x00004000
/* Error events exceptions */
#define FM_EX_KG_DOUBLE_ECC 0x80000000
#define FM_EX_KG_KEYSIZE_OVERFLOW 0x40000000
/* Scheme Registers bit field masks */
#define KG_SCH_MODE_EN 0x80000000
#define KG_SCH_VSP_NO_KSP_EN 0x80000000
#define KG_SCH_HASH_CONFIG_SYM 0x40000000
/* Known Protocol field codes */
#define KG_SCH_KN_PORT_ID 0x80000000
#define KG_SCH_KN_MACDST 0x40000000
#define KG_SCH_KN_MACSRC 0x20000000
#define KG_SCH_KN_TCI1 0x10000000
#define KG_SCH_KN_TCI2 0x08000000
#define KG_SCH_KN_ETYPE 0x04000000
#define KG_SCH_KN_PPPSID 0x02000000
#define KG_SCH_KN_PPPID 0x01000000
#define KG_SCH_KN_MPLS1 0x00800000
#define KG_SCH_KN_MPLS2 0x00400000
#define KG_SCH_KN_MPLS_LAST 0x00200000
#define KG_SCH_KN_IPSRC1 0x00100000
#define KG_SCH_KN_IPDST1 0x00080000
#define KG_SCH_KN_PTYPE1 0x00040000
#define KG_SCH_KN_IPTOS_TC1 0x00020000
#define KG_SCH_KN_IPV6FL1 0x00010000
#define KG_SCH_KN_IPSRC2 0x00008000
#define KG_SCH_KN_IPDST2 0x00004000
#define KG_SCH_KN_PTYPE2 0x00002000
#define KG_SCH_KN_IPTOS_TC2 0x00001000
#define KG_SCH_KN_IPV6FL2 0x00000800
#define KG_SCH_KN_GREPTYPE 0x00000400
#define KG_SCH_KN_IPSEC_SPI 0x00000200
#define KG_SCH_KN_IPSEC_NH 0x00000100
#define KG_SCH_KN_IPPID 0x00000080
#define KG_SCH_KN_L4PSRC 0x00000004
#define KG_SCH_KN_L4PDST 0x00000002
#define KG_SCH_KN_TFLG 0x00000001
/* NIA values */
#define NIA_ENG_BMI 0x00500000
#define NIA_BMI_AC_ENQ_FRAME 0x00000002
#define ENQUEUE_KG_DFLT_NIA (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)
/* Hard-coded configuration:
* These values are used as hard-coded values for KeyGen configuration
* and they replace user selections for this hard-coded version
*/
/* Hash distribution shift */
#define DEFAULT_HASH_DIST_FQID_SHIFT 0
/* Hash shift */
#define DEFAULT_HASH_SHIFT 0
/* Symmetric hash usage:
* Warning:
* - the value for symmetric hash usage must be in accordance with hash
* key defined below
* - according to tests performed, spreading is not working if symmetric
* hash is set on true
* So ultimately symmetric hash functionality should be always disabled:
*/
#define DEFAULT_SYMMETRIC_HASH false
/* Hash Key extraction fields: */
#define DEFAULT_HASH_KEY_EXTRACT_FIELDS \
(KG_SCH_KN_IPSRC1 | KG_SCH_KN_IPDST1 | \
KG_SCH_KN_L4PSRC | KG_SCH_KN_L4PDST | \
KG_SCH_KN_IPSEC_SPI)
/* Default values to be used as hash key in case IPv4 or L4 (TCP, UDP)
* don't exist in the frame
*/
/* Default IPv4 address */
#define DEFAULT_HASH_KEY_IPv4_ADDR 0x0A0A0A0A
/* Default L4 port */
#define DEFAULT_HASH_KEY_L4_PORT 0x0B0B0B0B
/* KeyGen Memory Mapped Registers: */
/* Scheme Configuration RAM Registers */
struct fman_kg_scheme_regs {
u32 kgse_mode; /* 0x100: MODE */
u32 kgse_ekfc; /* 0x104: Extract Known Fields Command */
u32 kgse_ekdv; /* 0x108: Extract Known Default Value */
u32 kgse_bmch; /* 0x10C: Bit Mask Command High */
u32 kgse_bmcl; /* 0x110: Bit Mask Command Low */
u32 kgse_fqb; /* 0x114: Frame Queue Base */
u32 kgse_hc; /* 0x118: Hash Command */
u32 kgse_ppc; /* 0x11C: Policer Profile Command */
u32 kgse_gec[FM_KG_NUM_OF_GENERIC_REGS];
/* 0x120: Generic Extract Command */
u32 kgse_spc;
/* 0x140: KeyGen Scheme Entry Statistic Packet Counter */
u32 kgse_dv0; /* 0x144: KeyGen Scheme Entry Default Value 0 */
u32 kgse_dv1; /* 0x148: KeyGen Scheme Entry Default Value 1 */
u32 kgse_ccbs;
/* 0x14C: KeyGen Scheme Entry Coarse Classification Bit*/
u32 kgse_mv; /* 0x150: KeyGen Scheme Entry Match vector */
u32 kgse_om; /* 0x154: KeyGen Scheme Entry Operation Mode bits */
u32 kgse_vsp;
/* 0x158: KeyGen Scheme Entry Virtual Storage Profile */
};
/* Port Partition Configuration Registers */
struct fman_kg_pe_regs {
u32 fmkg_pe_sp; /* 0x100: KeyGen Port entry Scheme Partition */
u32 fmkg_pe_cpp;
/* 0x104: KeyGen Port Entry Classification Plan Partition */
};
/* General Configuration and Status Registers
* Global Statistic Counters
* KeyGen Global Registers
*/
struct fman_kg_regs {
u32 fmkg_gcr; /* 0x000: KeyGen General Configuration Register */
u32 res004; /* 0x004: Reserved */
u32 res008; /* 0x008: Reserved */
u32 fmkg_eer; /* 0x00C: KeyGen Error Event Register */
u32 fmkg_eeer; /* 0x010: KeyGen Error Event Enable Register */
u32 res014; /* 0x014: Reserved */
u32 res018; /* 0x018: Reserved */
u32 fmkg_seer; /* 0x01C: KeyGen Scheme Error Event Register */
u32 fmkg_seeer; /* 0x020: KeyGen Scheme Error Event Enable Register */
u32 fmkg_gsr; /* 0x024: KeyGen Global Status Register */
u32 fmkg_tpc; /* 0x028: Total Packet Counter Register */
u32 fmkg_serc; /* 0x02C: Soft Error Capture Register */
u32 res030[4]; /* 0x030: Reserved */
u32 fmkg_fdor; /* 0x034: Frame Data Offset Register */
u32 fmkg_gdv0r; /* 0x038: Global Default Value Register 0 */
u32 fmkg_gdv1r; /* 0x03C: Global Default Value Register 1 */
u32 res04c[6]; /* 0x040: Reserved */
u32 fmkg_feer; /* 0x044: Force Error Event Register */
u32 res068[38]; /* 0x048: Reserved */
union {
u32 fmkg_indirect[63]; /* 0x100: Indirect Access Registers */
struct fman_kg_scheme_regs fmkg_sch; /* Scheme Registers */
struct fman_kg_pe_regs fmkg_pe; /* Port Partition Registers */
};
u32 fmkg_ar; /* 0x1FC: KeyGen Action Register */
};
/* KeyGen Scheme data */
struct keygen_scheme {
bool used; /* Specifies if this scheme is used */
u8 hw_port_id;
/* Hardware port ID
* schemes sharing between multiple ports is not
* currently supported
* so we have only one port id bound to a scheme
*/
u32 base_fqid;
/* Base FQID:
* Must be between 1 and 2^24-1
* If hash is used and an even distribution is
* expected according to hash_fqid_count,
* base_fqid must be aligned to hash_fqid_count
*/
u32 hash_fqid_count;
/* FQ range for hash distribution:
* Must be a power of 2
* Represents the range of queues for spreading
*/
bool use_hashing; /* Usage of Hashing and spreading over FQ */
bool symmetric_hash; /* Symmetric Hash option usage */
u8 hashShift;
/* Hash result right shift.
* Select the 24 bits out of the 64 hash result.
* 0 means using the 24 LSB's, otherwise
* use the 24 LSB's after shifting right
*/
u32 match_vector; /* Match Vector */
};
/* KeyGen driver data */
struct fman_keygen {
struct keygen_scheme schemes[FM_KG_MAX_NUM_OF_SCHEMES];
/* Array of schemes */
struct fman_kg_regs __iomem *keygen_regs; /* KeyGen registers */
};
/* keygen_write_ar_wait
*
* Write Action Register with specified value, wait for GO bit field to be
* idle and then read the error
*
* regs: KeyGen registers
* fmkg_ar: Action Register value
*
* Return: Zero for success or error code in case of failure
*/
static int keygen_write_ar_wait(struct fman_kg_regs __iomem *regs, u32 fmkg_ar)
{
iowrite32be(fmkg_ar, &regs->fmkg_ar);
/* Wait for GO bit field to be idle */
while (fmkg_ar & FM_KG_KGAR_GO)
fmkg_ar = ioread32be(&regs->fmkg_ar);
if (fmkg_ar & FM_KG_KGAR_ERR)
return -EINVAL;
return 0;
}
/* build_ar_scheme
*
* Build Action Register value for scheme settings
*
* scheme_id: Scheme ID
* update_counter: update scheme counter
* write: true for action to write the scheme or false for read action
*
* Return: AR value
*/
static u32 build_ar_scheme(u8 scheme_id, bool update_counter, bool write)
{
u32 rw = (u32)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
return (u32)(FM_KG_KGAR_GO |
rw |
FM_KG_KGAR_SEL_SCHEME_ENTRY |
DUMMY_PORT_ID |
((u32)scheme_id << FM_KG_KGAR_NUM_SHIFT) |
(update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT : 0));
}
/* build_ar_bind_scheme
*
* Build Action Register value for port binding to schemes
*
* hwport_id: HW Port ID
* write: true for action to write the bind or false for read action
*
* Return: AR value
*/
static u32 build_ar_bind_scheme(u8 hwport_id, bool write)
{
u32 rw = write ? (u32)FM_KG_KGAR_WRITE : (u32)FM_KG_KGAR_READ;
return (u32)(FM_KG_KGAR_GO |
rw |
FM_KG_KGAR_SEL_PORT_ENTRY |
hwport_id |
FM_KG_KGAR_SEL_PORT_WSEL_SP);
}
/* keygen_write_sp
*
* Write Scheme Partition Register with specified value
*
* regs: KeyGen Registers
* sp: Scheme Partition register value
* add: true to add a scheme partition or false to clear
*
* Return: none
*/
static void keygen_write_sp(struct fman_kg_regs __iomem *regs, u32 sp, bool add)
{
u32 tmp;
tmp = ioread32be(&regs->fmkg_pe.fmkg_pe_sp);
if (add)
tmp |= sp;
else
tmp &= ~sp;
iowrite32be(tmp, &regs->fmkg_pe.fmkg_pe_sp);
}
/* build_ar_bind_cls_plan
*
* Build Action Register value for Classification Plan
*
* hwport_id: HW Port ID
* write: true for action to write the CP or false for read action
*
* Return: AR value
*/
static u32 build_ar_bind_cls_plan(u8 hwport_id, bool write)
{
u32 rw = write ? (u32)FM_KG_KGAR_WRITE : (u32)FM_KG_KGAR_READ;
return (u32)(FM_KG_KGAR_GO |
rw |
FM_KG_KGAR_SEL_PORT_ENTRY |
hwport_id |
FM_KG_KGAR_SEL_PORT_WSEL_CPP);
}
/* keygen_write_cpp
*
* Write Classification Plan Partition Register with specified value
*
* regs: KeyGen Registers
* cpp: CPP register value
*
* Return: none
*/
static void keygen_write_cpp(struct fman_kg_regs __iomem *regs, u32 cpp)
{
iowrite32be(cpp, &regs->fmkg_pe.fmkg_pe_cpp);
}
/* keygen_write_scheme
*
* Write all Schemes Registers with specified values
*
* regs: KeyGen Registers
* scheme_id: Scheme ID
* scheme_regs: Scheme registers values desired to be written
* update_counter: update scheme counter
*
* Return: Zero for success or error code in case of failure
*/
static int keygen_write_scheme(struct fman_kg_regs __iomem *regs, u8 scheme_id,
struct fman_kg_scheme_regs *scheme_regs,
bool update_counter)
{
u32 ar_reg;
int err, i;
/* Write indirect scheme registers */
iowrite32be(scheme_regs->kgse_mode, &regs->fmkg_sch.kgse_mode);
iowrite32be(scheme_regs->kgse_ekfc, &regs->fmkg_sch.kgse_ekfc);
iowrite32be(scheme_regs->kgse_ekdv, &regs->fmkg_sch.kgse_ekdv);
iowrite32be(scheme_regs->kgse_bmch, &regs->fmkg_sch.kgse_bmch);
iowrite32be(scheme_regs->kgse_bmcl, &regs->fmkg_sch.kgse_bmcl);
iowrite32be(scheme_regs->kgse_fqb, &regs->fmkg_sch.kgse_fqb);
iowrite32be(scheme_regs->kgse_hc, &regs->fmkg_sch.kgse_hc);
iowrite32be(scheme_regs->kgse_ppc, &regs->fmkg_sch.kgse_ppc);
iowrite32be(scheme_regs->kgse_spc, &regs->fmkg_sch.kgse_spc);
iowrite32be(scheme_regs->kgse_dv0, &regs->fmkg_sch.kgse_dv0);
iowrite32be(scheme_regs->kgse_dv1, &regs->fmkg_sch.kgse_dv1);
iowrite32be(scheme_regs->kgse_ccbs, &regs->fmkg_sch.kgse_ccbs);
iowrite32be(scheme_regs->kgse_mv, &regs->fmkg_sch.kgse_mv);
iowrite32be(scheme_regs->kgse_om, &regs->fmkg_sch.kgse_om);
iowrite32be(scheme_regs->kgse_vsp, &regs->fmkg_sch.kgse_vsp);
for (i = 0 ; i < FM_KG_NUM_OF_GENERIC_REGS ; i++)
iowrite32be(scheme_regs->kgse_gec[i],
&regs->fmkg_sch.kgse_gec[i]);
/* Write AR (Action register) */
ar_reg = build_ar_scheme(scheme_id, update_counter, true);
err = keygen_write_ar_wait(regs, ar_reg);
if (err != 0) {
pr_err("Writing Action Register failed\n");
return err;
}
return err;
}
/* get_free_scheme_id
*
* Find the first free scheme available to be used
*
* keygen: KeyGen handle
* scheme_id: pointer to scheme id
*
* Return: 0 on success, -EINVAL when the are no available free schemes
*/
static int get_free_scheme_id(struct fman_keygen *keygen, u8 *scheme_id)
{
u8 i;
for (i = 0; i < FM_KG_MAX_NUM_OF_SCHEMES; i++)
if (!keygen->schemes[i].used) {
*scheme_id = i;
return 0;
}
return -EINVAL;
}
/* get_scheme
*
* Provides the scheme for specified ID
*
* keygen: KeyGen handle
* scheme_id: Scheme ID
*
* Return: handle to required scheme
*/
static struct keygen_scheme *get_scheme(struct fman_keygen *keygen,
u8 scheme_id)
{
if (scheme_id >= FM_KG_MAX_NUM_OF_SCHEMES)
return NULL;
return &keygen->schemes[scheme_id];
}
/* keygen_bind_port_to_schemes
*
* Bind the port to schemes
*
* keygen: KeyGen handle
* scheme_id: id of the scheme to bind to
* bind: true to bind the port or false to unbind it
*
* Return: Zero for success or error code in case of failure
*/
static int keygen_bind_port_to_schemes(struct fman_keygen *keygen,
u8 scheme_id,
bool bind)
{
struct fman_kg_regs __iomem *keygen_regs = keygen->keygen_regs;
struct keygen_scheme *scheme;
u32 ar_reg;
u32 schemes_vector = 0;
int err;
scheme = get_scheme(keygen, scheme_id);
if (!scheme) {
pr_err("Requested Scheme does not exist\n");
return -EINVAL;
}
if (!scheme->used) {
pr_err("Cannot bind port to an invalid scheme\n");
return -EINVAL;
}
schemes_vector |= 1 << (31 - scheme_id);
ar_reg = build_ar_bind_scheme(scheme->hw_port_id, false);
err = keygen_write_ar_wait(keygen_regs, ar_reg);
if (err != 0) {
pr_err("Reading Action Register failed\n");
return err;
}
keygen_write_sp(keygen_regs, schemes_vector, bind);
ar_reg = build_ar_bind_scheme(scheme->hw_port_id, true);
err = keygen_write_ar_wait(keygen_regs, ar_reg);
if (err != 0) {
pr_err("Writing Action Register failed\n");
return err;
}
return 0;
}
/* keygen_scheme_setup
*
* Setup the scheme according to required configuration
*
* keygen: KeyGen handle
* scheme_id: scheme ID
* enable: true to enable scheme or false to disable it
*
* Return: Zero for success or error code in case of failure
*/
static int keygen_scheme_setup(struct fman_keygen *keygen, u8 scheme_id,
bool enable)
{
struct fman_kg_regs __iomem *keygen_regs = keygen->keygen_regs;
struct fman_kg_scheme_regs scheme_regs;
struct keygen_scheme *scheme;
u32 tmp_reg;
int err;
scheme = get_scheme(keygen, scheme_id);
if (!scheme) {
pr_err("Requested Scheme does not exist\n");
return -EINVAL;
}
if (enable && scheme->used) {
pr_err("The requested Scheme is already used\n");
return -EINVAL;
}
/* Clear scheme registers */
memset(&scheme_regs, 0, sizeof(struct fman_kg_scheme_regs));
/* Setup all scheme registers: */
tmp_reg = 0;
if (enable) {
/* Enable Scheme */
tmp_reg |= KG_SCH_MODE_EN;
/* Enqueue frame NIA */
tmp_reg |= ENQUEUE_KG_DFLT_NIA;
}
scheme_regs.kgse_mode = tmp_reg;
scheme_regs.kgse_mv = scheme->match_vector;
/* Scheme don't override StorageProfile:
* valid only for DPAA_VERSION >= 11
*/
scheme_regs.kgse_vsp = KG_SCH_VSP_NO_KSP_EN;
/* Configure Hard-Coded Rx Hashing: */
if (scheme->use_hashing) {
/* configure kgse_ekfc */
scheme_regs.kgse_ekfc = DEFAULT_HASH_KEY_EXTRACT_FIELDS;
/* configure kgse_ekdv */
tmp_reg = 0;
tmp_reg |= (KG_SCH_DEF_USE_KGSE_DV_0 <<
KG_SCH_DEF_IP_ADDR_SHIFT);
tmp_reg |= (KG_SCH_DEF_USE_KGSE_DV_1 <<
KG_SCH_DEF_L4_PORT_SHIFT);
scheme_regs.kgse_ekdv = tmp_reg;
/* configure kgse_dv0 */
scheme_regs.kgse_dv0 = DEFAULT_HASH_KEY_IPv4_ADDR;
/* configure kgse_dv1 */
scheme_regs.kgse_dv1 = DEFAULT_HASH_KEY_L4_PORT;
/* configure kgse_hc */
tmp_reg = 0;
tmp_reg |= ((scheme->hash_fqid_count - 1) <<
DEFAULT_HASH_DIST_FQID_SHIFT);
tmp_reg |= scheme->hashShift << KG_SCH_HASH_CONFIG_SHIFT_SHIFT;
if (scheme->symmetric_hash) {
/* Normally extraction key should be verified if
* complies with symmetric hash
* But because extraction is hard-coded, we are sure
* the key is symmetric
*/
tmp_reg |= KG_SCH_HASH_CONFIG_SYM;
}
scheme_regs.kgse_hc = tmp_reg;
} else {
scheme_regs.kgse_ekfc = 0;
scheme_regs.kgse_hc = 0;
scheme_regs.kgse_ekdv = 0;
scheme_regs.kgse_dv0 = 0;
scheme_regs.kgse_dv1 = 0;
}
/* configure kgse_fqb: Scheme FQID base */
tmp_reg = 0;
tmp_reg |= scheme->base_fqid;
scheme_regs.kgse_fqb = tmp_reg;
/* features not used by hard-coded configuration */
scheme_regs.kgse_bmch = 0;
scheme_regs.kgse_bmcl = 0;
scheme_regs.kgse_spc = 0;
/* Write scheme registers */
err = keygen_write_scheme(keygen_regs, scheme_id, &scheme_regs, true);
if (err != 0) {
pr_err("Writing scheme registers failed\n");
return err;
}
/* Update used field for Scheme */
scheme->used = enable;
return 0;
}
/* keygen_init
*
* KeyGen initialization:
* Initializes and enables KeyGen, allocate driver memory, setup registers,
* clear port bindings, invalidate all schemes
*
* keygen_regs: KeyGen registers base address
*
* Return: Handle to KeyGen driver
*/
struct fman_keygen *keygen_init(struct fman_kg_regs __iomem *keygen_regs)
{
struct fman_keygen *keygen;
u32 ar;
int i;
/* Allocate memory for KeyGen driver */
keygen = kzalloc_obj(*keygen);
if (!keygen)
return NULL;
keygen->keygen_regs = keygen_regs;
/* KeyGen initialization (for Master partition):
* Setup KeyGen registers
*/
iowrite32be(ENQUEUE_KG_DFLT_NIA, &keygen_regs->fmkg_gcr);
iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW,
&keygen_regs->fmkg_eer);
iowrite32be(0, &keygen_regs->fmkg_fdor);
iowrite32be(0, &keygen_regs->fmkg_gdv0r);
iowrite32be(0, &keygen_regs->fmkg_gdv1r);
/* Clear binding between ports to schemes and classification plans
* so that all ports are not bound to any scheme/classification plan
*/
for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) {
/* Clear all pe sp schemes registers */
keygen_write_sp(keygen_regs, 0xffffffff, false);
ar = build_ar_bind_scheme(i, true);
keygen_write_ar_wait(keygen_regs, ar);
/* Clear all pe cpp classification plans registers */
keygen_write_cpp(keygen_regs, 0);
ar = build_ar_bind_cls_plan(i, true);
keygen_write_ar_wait(keygen_regs, ar);
}
/* Enable all scheme interrupts */
iowrite32be(0xFFFFFFFF, &keygen_regs->fmkg_seer);
iowrite32be(0xFFFFFFFF, &keygen_regs->fmkg_seeer);
/* Enable KyeGen */
iowrite32be(ioread32be(&keygen_regs->fmkg_gcr) | FM_KG_KGGCR_EN,
&keygen_regs->fmkg_gcr);
return keygen;
}
EXPORT_SYMBOL(keygen_init);
/* keygen_port_hashing_init
*
* Initializes a port for Rx Hashing with specified configuration parameters
*
* keygen: KeyGen handle
* hw_port_id: HW Port ID
* hash_base_fqid: Hashing Base FQID used for spreading
* hash_size: Hashing size
*
* Return: Zero for success or error code in case of failure
*/
int keygen_port_hashing_init(struct fman_keygen *keygen, u8 hw_port_id,
u32 hash_base_fqid, u32 hash_size)
{
struct keygen_scheme *scheme;
u8 scheme_id;
int err;
/* Validate Scheme configuration parameters */
if (hash_base_fqid == 0 || (hash_base_fqid & ~0x00FFFFFF)) {
pr_err("Base FQID must be between 1 and 2^24-1\n");
return -EINVAL;
}
if (hash_size == 0 || (hash_size & (hash_size - 1)) != 0) {
pr_err("Hash size must be power of two\n");
return -EINVAL;
}
/* Find a free scheme */
err = get_free_scheme_id(keygen, &scheme_id);
if (err) {
pr_err("The maximum number of available Schemes has been exceeded\n");
return -EINVAL;
}
/* Create and configure Hard-Coded Scheme: */
scheme = get_scheme(keygen, scheme_id);
if (!scheme) {
pr_err("Requested Scheme does not exist\n");
return -EINVAL;
}
if (scheme->used) {
pr_err("The requested Scheme is already used\n");
return -EINVAL;
}
/* Clear all scheme fields because the scheme may have been
* previously used
*/
memset(scheme, 0, sizeof(struct keygen_scheme));
/* Setup scheme: */
scheme->hw_port_id = hw_port_id;
scheme->use_hashing = true;
scheme->base_fqid = hash_base_fqid;
scheme->hash_fqid_count = hash_size;
scheme->symmetric_hash = DEFAULT_SYMMETRIC_HASH;
scheme->hashShift = DEFAULT_HASH_SHIFT;
/* All Schemes in hard-coded configuration
* are Indirect Schemes
*/
scheme->match_vector = 0;
err = keygen_scheme_setup(keygen, scheme_id, true);
if (err != 0) {
pr_err("Scheme setup failed\n");
return err;
}
/* Bind Rx port to Scheme */
err = keygen_bind_port_to_schemes(keygen, scheme_id, true);
if (err != 0) {
pr_err("Binding port to schemes failed\n");
return err;
}
return 0;
}
EXPORT_SYMBOL(keygen_port_hashing_init);
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_keygen.h
+19
View File
@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2017 NXP
*/
#ifndef __KEYGEN_H
#define __KEYGEN_H
#include <linux/io.h>
struct fman_keygen;
struct fman_kg_regs;
struct fman_keygen *keygen_init(struct fman_kg_regs __iomem *keygen_regs);
int keygen_port_hashing_init(struct fman_keygen *keygen, u8 hw_port_id,
u32 hash_base_fqid, u32 hash_size);
#endif /* __KEYGEN_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_mac.h
+245
View File
@@ -0,0 +1,245 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* FM MAC ... */
#ifndef __FM_MAC_H
#define __FM_MAC_H
#include "fman.h"
#include <linux/slab.h>
#include <linux/phy.h>
#include <linux/if_ether.h>
struct fman_mac;
struct mac_device;
/* Ethernet Address */
typedef u8 enet_addr_t[ETH_ALEN];
#define ENET_ADDR_TO_UINT64(_enet_addr) \
(u64)(((u64)(_enet_addr)[0] << 40) | \
((u64)(_enet_addr)[1] << 32) | \
((u64)(_enet_addr)[2] << 24) | \
((u64)(_enet_addr)[3] << 16) | \
((u64)(_enet_addr)[4] << 8) | \
((u64)(_enet_addr)[5]))
#define MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enet_addr) \
do { \
int i; \
for (i = 0; i < ETH_ALEN; i++) \
(_enet_addr)[i] = \
(u8)((_addr64) >> ((5 - i) * 8)); \
} while (0)
/* defaults */
#define DEFAULT_RESET_ON_INIT false
/* PFC defines */
#define FSL_FM_PAUSE_TIME_ENABLE 0xf000
#define FSL_FM_PAUSE_TIME_DISABLE 0
#define FSL_FM_PAUSE_THRESH_DEFAULT 0
#define FM_MAC_NO_PFC 0xff
/* HASH defines */
#define ETH_HASH_ENTRY_OBJ(ptr) \
hlist_entry_safe(ptr, struct eth_hash_entry, node)
/* FM MAC Exceptions */
enum fman_mac_exceptions {
FM_MAC_EX_10G_MDIO_SCAN_EVENT = 0
/* 10GEC MDIO scan event interrupt */
, FM_MAC_EX_10G_MDIO_CMD_CMPL
/* 10GEC MDIO command completion interrupt */
, FM_MAC_EX_10G_REM_FAULT
/* 10GEC, mEMAC Remote fault interrupt */
, FM_MAC_EX_10G_LOC_FAULT
/* 10GEC, mEMAC Local fault interrupt */
, FM_MAC_EX_10G_TX_ECC_ER
/* 10GEC, mEMAC Transmit frame ECC error interrupt */
, FM_MAC_EX_10G_TX_FIFO_UNFL
/* 10GEC, mEMAC Transmit FIFO underflow interrupt */
, FM_MAC_EX_10G_TX_FIFO_OVFL
/* 10GEC, mEMAC Transmit FIFO overflow interrupt */
, FM_MAC_EX_10G_TX_ER
/* 10GEC Transmit frame error interrupt */
, FM_MAC_EX_10G_RX_FIFO_OVFL
/* 10GEC, mEMAC Receive FIFO overflow interrupt */
, FM_MAC_EX_10G_RX_ECC_ER
/* 10GEC, mEMAC Receive frame ECC error interrupt */
, FM_MAC_EX_10G_RX_JAB_FRM
/* 10GEC Receive jabber frame interrupt */
, FM_MAC_EX_10G_RX_OVRSZ_FRM
/* 10GEC Receive oversized frame interrupt */
, FM_MAC_EX_10G_RX_RUNT_FRM
/* 10GEC Receive runt frame interrupt */
, FM_MAC_EX_10G_RX_FRAG_FRM
/* 10GEC Receive fragment frame interrupt */
, FM_MAC_EX_10G_RX_LEN_ER
/* 10GEC Receive payload length error interrupt */
, FM_MAC_EX_10G_RX_CRC_ER
/* 10GEC Receive CRC error interrupt */
, FM_MAC_EX_10G_RX_ALIGN_ER
/* 10GEC Receive alignment error interrupt */
, FM_MAC_EX_1G_BAB_RX
/* dTSEC Babbling receive error */
, FM_MAC_EX_1G_RX_CTL
/* dTSEC Receive control (pause frame) interrupt */
, FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET
/* dTSEC Graceful transmit stop complete */
, FM_MAC_EX_1G_BAB_TX
/* dTSEC Babbling transmit error */
, FM_MAC_EX_1G_TX_CTL
/* dTSEC Transmit control (pause frame) interrupt */
, FM_MAC_EX_1G_TX_ERR
/* dTSEC Transmit error */
, FM_MAC_EX_1G_LATE_COL
/* dTSEC Late collision */
, FM_MAC_EX_1G_COL_RET_LMT
/* dTSEC Collision retry limit */
, FM_MAC_EX_1G_TX_FIFO_UNDRN
/* dTSEC Transmit FIFO underrun */
, FM_MAC_EX_1G_MAG_PCKT
/* dTSEC Magic Packet detection */
, FM_MAC_EX_1G_MII_MNG_RD_COMPLET
/* dTSEC MII management read completion */
, FM_MAC_EX_1G_MII_MNG_WR_COMPLET
/* dTSEC MII management write completion */
, FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET
/* dTSEC Graceful receive stop complete */
, FM_MAC_EX_1G_DATA_ERR
/* dTSEC Internal data error on transmit */
, FM_MAC_1G_RX_DATA_ERR
/* dTSEC Internal data error on receive */
, FM_MAC_EX_1G_1588_TS_RX_ERR
/* dTSEC Time-Stamp Receive Error */
, FM_MAC_EX_1G_RX_MIB_CNT_OVFL
/* dTSEC MIB counter overflow */
, FM_MAC_EX_TS_FIFO_ECC_ERR
/* mEMAC Time-stamp FIFO ECC error interrupt;
* not supported on T4240/B4860 rev1 chips
*/
, FM_MAC_EX_MAGIC_PACKET_INDICATION = FM_MAC_EX_1G_MAG_PCKT
/* mEMAC Magic Packet Indication Interrupt */
};
struct eth_hash_entry {
u64 addr; /* Ethernet Address */
struct list_head node;
};
typedef void (fman_mac_exception_cb)(struct mac_device *dev_id,
enum fman_mac_exceptions exceptions);
/* FMan MAC config input */
struct fman_mac_params {
/* MAC ID; numbering of dTSEC and 1G-mEMAC:
* 0 - FM_MAX_NUM_OF_1G_MACS;
* numbering of 10G-MAC (TGEC) and 10G-mEMAC:
* 0 - FM_MAX_NUM_OF_10G_MACS
*/
u8 mac_id;
/* A handle to the FM object this port related to */
void *fm;
fman_mac_exception_cb *event_cb; /* MDIO Events Callback Routine */
fman_mac_exception_cb *exception_cb;/* Exception Callback Routine */
};
struct eth_hash_t {
u16 size;
struct list_head *lsts;
};
static inline struct eth_hash_entry
*dequeue_addr_from_hash_entry(struct list_head *addr_lst)
{
struct eth_hash_entry *hash_entry = NULL;
if (!list_empty(addr_lst)) {
hash_entry = ETH_HASH_ENTRY_OBJ(addr_lst->next);
list_del_init(&hash_entry->node);
}
return hash_entry;
}
static inline void free_hash_table(struct eth_hash_t *hash)
{
struct eth_hash_entry *hash_entry;
int i = 0;
if (hash) {
if (hash->lsts) {
for (i = 0; i < hash->size; i++) {
hash_entry =
dequeue_addr_from_hash_entry(&hash->lsts[i]);
while (hash_entry) {
kfree(hash_entry);
hash_entry =
dequeue_addr_from_hash_entry(&hash->
lsts[i]);
}
}
kfree(hash->lsts);
}
kfree(hash);
}
}
static inline struct eth_hash_t *alloc_hash_table(u16 size)
{
u32 i;
struct eth_hash_t *hash;
/* Allocate address hash table */
hash = kmalloc_obj(*hash);
if (!hash)
return NULL;
hash->size = size;
hash->lsts = kmalloc_objs(struct list_head, hash->size);
if (!hash->lsts) {
kfree(hash);
return NULL;
}
for (i = 0; i < hash->size; i++)
INIT_LIST_HEAD(&hash->lsts[i]);
return hash;
}
#endif /* __FM_MAC_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_memac.c
+1335
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linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_memac.h
+20
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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __MEMAC_H
#define __MEMAC_H
#include "fman_mac.h"
#include <linux/netdevice.h>
#include <linux/phy_fixed.h>
struct mac_device;
int memac_initialization(struct mac_device *mac_dev,
struct device_node *mac_node,
struct fman_mac_params *params);
#endif /* __MEMAC_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_muram.c
+131
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#include "fman_muram.h"
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/genalloc.h>
struct muram_info {
struct gen_pool *pool;
void __iomem *vbase;
phys_addr_t pbase;
};
static unsigned long fman_muram_vbase_to_offset(struct muram_info *muram,
unsigned long vaddr)
{
return vaddr - (unsigned long)muram->vbase;
}
/**
* fman_muram_init
* @base: Pointer to base of memory mapped FM-MURAM.
* @size: Size of the FM-MURAM partition.
*
* Creates partition in the MURAM.
* The routine returns a pointer to the MURAM partition.
* This pointer must be passed as to all other FM-MURAM function calls.
* No actual initialization or configuration of FM_MURAM hardware is done by
* this routine.
*
* Return: pointer to FM-MURAM object, or NULL for Failure.
*/
struct muram_info *fman_muram_init(phys_addr_t base, size_t size)
{
struct muram_info *muram;
void __iomem *vaddr;
int ret;
muram = kzalloc_obj(*muram);
if (!muram)
return NULL;
muram->pool = gen_pool_create(ilog2(64), -1);
if (!muram->pool) {
pr_err("%s(): MURAM pool create failed\n", __func__);
goto muram_free;
}
vaddr = ioremap(base, size);
if (!vaddr) {
pr_err("%s(): MURAM ioremap failed\n", __func__);
goto pool_destroy;
}
ret = gen_pool_add_virt(muram->pool, (unsigned long)vaddr,
base, size, -1);
if (ret < 0) {
pr_err("%s(): MURAM pool add failed\n", __func__);
iounmap(vaddr);
goto pool_destroy;
}
memset_io(vaddr, 0, (int)size);
muram->vbase = vaddr;
muram->pbase = base;
return muram;
pool_destroy:
gen_pool_destroy(muram->pool);
muram_free:
kfree(muram);
return NULL;
}
/**
* fman_muram_offset_to_vbase
* @muram: FM-MURAM module pointer.
* @offset: the offset of the memory block
*
* Gives the address of the memory region from specific offset
*
* Return: The address of the memory block
*/
unsigned long fman_muram_offset_to_vbase(struct muram_info *muram,
unsigned long offset)
{
return offset + (unsigned long)muram->vbase;
}
/**
* fman_muram_alloc
* @muram: FM-MURAM module pointer.
* @size: Size of the memory to be allocated.
*
* Allocate some memory from FM-MURAM partition.
*
* Return: address of the allocated memory; NULL otherwise.
*/
unsigned long fman_muram_alloc(struct muram_info *muram, size_t size)
{
unsigned long vaddr;
vaddr = gen_pool_alloc(muram->pool, size);
if (!vaddr)
return -ENOMEM;
memset_io((void __iomem *)vaddr, 0, size);
return fman_muram_vbase_to_offset(muram, vaddr);
}
/**
* fman_muram_free_mem
* @muram: FM-MURAM module pointer.
* @offset: offset of the memory region to be freed.
* @size: size of the memory to be freed.
*
* Free an allocated memory from FM-MURAM partition.
*/
void fman_muram_free_mem(struct muram_info *muram, unsigned long offset,
size_t size)
{
unsigned long addr = fman_muram_offset_to_vbase(muram, offset);
gen_pool_free(muram->pool, addr, size);
}
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_muram.h
+26
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@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __FM_MURAM_EXT
#define __FM_MURAM_EXT
#include <linux/types.h>
#define FM_MURAM_INVALID_ALLOCATION -1
/* Structure for FM MURAM information */
struct muram_info;
struct muram_info *fman_muram_init(phys_addr_t base, size_t size);
unsigned long fman_muram_offset_to_vbase(struct muram_info *muram,
unsigned long offset);
unsigned long fman_muram_alloc(struct muram_info *muram, size_t size);
void fman_muram_free_mem(struct muram_info *muram, unsigned long offset,
size_t size);
#endif /* __FM_MURAM_EXT */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_port.c
+1921
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linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_port.h
+135
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@@ -0,0 +1,135 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __FMAN_PORT_H
#define __FMAN_PORT_H
#include "fman.h"
/* FM Port API
* The FM uses a general module called "port" to represent a Tx port (MAC),
* an Rx port (MAC).
* The number of ports in an FM varies between SOCs.
* The SW driver manages these ports as sub-modules of the FM,i.e. after an
* FM is initialized, its ports may be initialized and operated upon.
* The port is initialized aware of its type, but other functions on a port
* may be indifferent to its type. When necessary, the driver verifies
* coherence and returns error if applicable.
* On initialization, user specifies the port type and it's index (relative
* to the port's type) - always starting at 0.
*/
/* FM Frame error */
/* Frame Descriptor errors */
/* Not for Rx-Port! Unsupported Format */
#define FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT FM_FD_ERR_UNSUPPORTED_FORMAT
/* Not for Rx-Port! Length Error */
#define FM_PORT_FRM_ERR_LENGTH FM_FD_ERR_LENGTH
/* DMA Data error */
#define FM_PORT_FRM_ERR_DMA FM_FD_ERR_DMA
/* non Frame-Manager error; probably come from SEC that was chained to FM */
#define FM_PORT_FRM_ERR_NON_FM FM_FD_RX_STATUS_ERR_NON_FM
/* IPR error */
#define FM_PORT_FRM_ERR_IPRE (FM_FD_ERR_IPR & ~FM_FD_IPR)
/* IPR non-consistent-sp */
#define FM_PORT_FRM_ERR_IPR_NCSP (FM_FD_ERR_IPR_NCSP & \
~FM_FD_IPR)
/* Rx FIFO overflow, FCS error, code error, running disparity
* error (SGMII and TBI modes), FIFO parity error.
* PHY Sequence error, PHY error control character detected.
*/
#define FM_PORT_FRM_ERR_PHYSICAL FM_FD_ERR_PHYSICAL
/* Frame too long OR Frame size exceeds max_length_frame */
#define FM_PORT_FRM_ERR_SIZE FM_FD_ERR_SIZE
/* indicates a classifier "drop" operation */
#define FM_PORT_FRM_ERR_CLS_DISCARD FM_FD_ERR_CLS_DISCARD
/* Extract Out of Frame */
#define FM_PORT_FRM_ERR_EXTRACTION FM_FD_ERR_EXTRACTION
/* No Scheme Selected */
#define FM_PORT_FRM_ERR_NO_SCHEME FM_FD_ERR_NO_SCHEME
/* Keysize Overflow */
#define FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW FM_FD_ERR_KEYSIZE_OVERFLOW
/* Frame color is red */
#define FM_PORT_FRM_ERR_COLOR_RED FM_FD_ERR_COLOR_RED
/* Frame color is yellow */
#define FM_PORT_FRM_ERR_COLOR_YELLOW FM_FD_ERR_COLOR_YELLOW
/* Parser Time out Exceed */
#define FM_PORT_FRM_ERR_PRS_TIMEOUT FM_FD_ERR_PRS_TIMEOUT
/* Invalid Soft Parser instruction */
#define FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT FM_FD_ERR_PRS_ILL_INSTRUCT
/* Header error was identified during parsing */
#define FM_PORT_FRM_ERR_PRS_HDR_ERR FM_FD_ERR_PRS_HDR_ERR
/* Frame parsed beyind 256 first bytes */
#define FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED FM_FD_ERR_BLOCK_LIMIT_EXCEEDED
/* FPM Frame Processing Timeout Exceeded */
#define FM_PORT_FRM_ERR_PROCESS_TIMEOUT 0x00000001
struct fman_port;
/* A structure for additional Rx port parameters */
struct fman_port_rx_params {
u32 err_fqid; /* Error Queue Id. */
u32 dflt_fqid; /* Default Queue Id. */
u32 pcd_base_fqid; /* PCD base Queue Id. */
u32 pcd_fqs_count; /* Number of PCD FQs. */
/* Which external buffer pools are used
* (up to FMAN_PORT_MAX_EXT_POOLS_NUM), and their sizes.
*/
struct fman_ext_pools ext_buf_pools;
};
/* A structure for additional non-Rx port parameters */
struct fman_port_non_rx_params {
/* Error Queue Id. */
u32 err_fqid;
/* For Tx - Default Confirmation queue, 0 means no Tx confirmation
* for processed frames. For OP port - default Rx queue.
*/
u32 dflt_fqid;
};
/* A union for additional parameters depending on port type */
union fman_port_specific_params {
/* Rx port parameters structure */
struct fman_port_rx_params rx_params;
/* Non-Rx port parameters structure */
struct fman_port_non_rx_params non_rx_params;
};
/* A structure representing FM initialization parameters */
struct fman_port_params {
/* Virtual Address of memory mapped FM Port registers. */
void *fm;
union fman_port_specific_params specific_params;
/* Additional parameters depending on port type. */
};
int fman_port_config(struct fman_port *port, struct fman_port_params *params);
void fman_port_use_kg_hash(struct fman_port *port, bool enable);
int fman_port_init(struct fman_port *port);
int fman_port_cfg_buf_prefix_content(struct fman_port *port,
struct fman_buffer_prefix_content
*buffer_prefix_content);
int fman_port_disable(struct fman_port *port);
int fman_port_enable(struct fman_port *port);
u32 fman_port_get_qman_channel_id(struct fman_port *port);
int fman_port_get_hash_result_offset(struct fman_port *port, u32 *offset);
int fman_port_get_tstamp(struct fman_port *port, const void *data, u64 *tstamp);
struct fman_port *fman_port_bind(struct device *dev);
struct device *fman_port_get_device(struct fman_port *port);
#endif /* __FMAN_PORT_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_sp.c
+142
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@@ -0,0 +1,142 @@
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#include "fman_sp.h"
#include "fman.h"
void fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(struct fman_ext_pools
*fm_ext_pools,
u8 *ordered_array,
u16 *sizes_array)
{
u16 buf_size = 0;
int i = 0, j = 0, k = 0;
/* First we copy the external buffers pools information
* to an ordered local array
*/
for (i = 0; i < fm_ext_pools->num_of_pools_used; i++) {
/* get pool size */
buf_size = fm_ext_pools->ext_buf_pool[i].size;
/* keep sizes in an array according to poolId
* for direct access
*/
sizes_array[fm_ext_pools->ext_buf_pool[i].id] = buf_size;
/* save poolId in an ordered array according to size */
for (j = 0; j <= i; j++) {
/* this is the next free place in the array */
if (j == i)
ordered_array[i] =
fm_ext_pools->ext_buf_pool[i].id;
else {
/* find the right place for this poolId */
if (buf_size < sizes_array[ordered_array[j]]) {
/* move the pool_ids one place ahead
* to make room for this poolId
*/
for (k = i; k > j; k--)
ordered_array[k] =
ordered_array[k - 1];
/* now k==j, this is the place for
* the new size
*/
ordered_array[k] =
fm_ext_pools->ext_buf_pool[i].id;
break;
}
}
}
}
}
EXPORT_SYMBOL(fman_sp_set_buf_pools_in_asc_order_of_buf_sizes);
int fman_sp_build_buffer_struct(struct fman_sp_int_context_data_copy *
int_context_data_copy,
struct fman_buffer_prefix_content *
buffer_prefix_content,
struct fman_sp_buf_margins *buf_margins,
struct fman_sp_buffer_offsets *buffer_offsets,
u8 *internal_buf_offset)
{
u32 tmp;
/* Align start of internal context data to 16 byte */
int_context_data_copy->ext_buf_offset = (u16)
((buffer_prefix_content->priv_data_size & (OFFSET_UNITS - 1)) ?
((buffer_prefix_content->priv_data_size + OFFSET_UNITS) &
~(u16)(OFFSET_UNITS - 1)) :
buffer_prefix_content->priv_data_size);
/* Translate margin and int_context params to FM parameters */
/* Initialize with illegal value. Later we'll set legal values. */
buffer_offsets->prs_result_offset = (u32)ILLEGAL_BASE;
buffer_offsets->time_stamp_offset = (u32)ILLEGAL_BASE;
buffer_offsets->hash_result_offset = (u32)ILLEGAL_BASE;
/* Internally the driver supports 4 options
* 1. prsResult/timestamp/hashResult selection (in fact 8 options,
* but for simplicity we'll
* relate to it as 1).
* 2. All IC context (from AD) not including debug.
*/
/* This case covers the options under 1 */
/* Copy size must be in 16-byte granularity. */
int_context_data_copy->size =
(u16)((buffer_prefix_content->pass_prs_result ? 32 : 0) +
((buffer_prefix_content->pass_time_stamp ||
buffer_prefix_content->pass_hash_result) ? 16 : 0));
/* Align start of internal context data to 16 byte */
int_context_data_copy->int_context_offset =
(u8)(buffer_prefix_content->pass_prs_result ? 32 :
((buffer_prefix_content->pass_time_stamp ||
buffer_prefix_content->pass_hash_result) ? 64 : 0));
if (buffer_prefix_content->pass_prs_result)
buffer_offsets->prs_result_offset =
int_context_data_copy->ext_buf_offset;
if (buffer_prefix_content->pass_time_stamp)
buffer_offsets->time_stamp_offset =
buffer_prefix_content->pass_prs_result ?
(int_context_data_copy->ext_buf_offset +
sizeof(struct fman_prs_result)) :
int_context_data_copy->ext_buf_offset;
if (buffer_prefix_content->pass_hash_result)
/* If PR is not requested, whether TS is
* requested or not, IC will be copied from TS
*/
buffer_offsets->hash_result_offset =
buffer_prefix_content->pass_prs_result ?
(int_context_data_copy->ext_buf_offset +
sizeof(struct fman_prs_result) + 8) :
int_context_data_copy->ext_buf_offset + 8;
if (int_context_data_copy->size)
buf_margins->start_margins =
(u16)(int_context_data_copy->ext_buf_offset +
int_context_data_copy->size);
else
/* No Internal Context passing, STartMargin is
* immediately after private_info
*/
buf_margins->start_margins =
buffer_prefix_content->priv_data_size;
/* align data start */
tmp = (u32)(buf_margins->start_margins %
buffer_prefix_content->data_align);
if (tmp)
buf_margins->start_margins +=
(buffer_prefix_content->data_align - tmp);
buffer_offsets->data_offset = buf_margins->start_margins;
return 0;
}
EXPORT_SYMBOL(fman_sp_build_buffer_struct);
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_sp.h
+77
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@@ -0,0 +1,77 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __FM_SP_H
#define __FM_SP_H
#include "fman.h"
#include <linux/types.h>
#define ILLEGAL_BASE (~0)
/* defaults */
#define DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN 64
/* Registers bit fields */
#define FMAN_SP_EXT_BUF_POOL_EN_COUNTER 0x40000000
#define FMAN_SP_EXT_BUF_POOL_VALID 0x80000000
#define FMAN_SP_EXT_BUF_POOL_BACKUP 0x20000000
#define FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE 0x00100000
#define FMAN_SP_SG_DISABLE 0x80000000
/* shifts */
#define FMAN_SP_EXT_BUF_MARG_START_SHIFT 16
#define FMAN_SP_DMA_ATTR_SWP_SHIFT 30
#define FMAN_SP_IC_TO_EXT_SHIFT 16
#define FMAN_SP_IC_FROM_INT_SHIFT 8
/* structure for defining internal context copying */
struct fman_sp_int_context_data_copy {
/* < Offset in External buffer to which internal
* context is copied to (Rx) or taken from (Tx, Op).
*/
u16 ext_buf_offset;
/* Offset within internal context to copy from
* (Rx) or to copy to (Tx, Op).
*/
u8 int_context_offset;
/* Internal offset size to be copied */
u16 size;
};
/* struct for defining external buffer margins */
struct fman_sp_buf_margins {
/* Number of bytes to be left at the beginning
* of the external buffer (must be divisible by 16)
*/
u16 start_margins;
/* number of bytes to be left at the end
* of the external buffer(must be divisible by 16)
*/
u16 end_margins;
};
struct fman_sp_buffer_offsets {
u32 data_offset;
u32 prs_result_offset;
u32 time_stamp_offset;
u32 hash_result_offset;
};
int fman_sp_build_buffer_struct(struct fman_sp_int_context_data_copy
*int_context_data_copy,
struct fman_buffer_prefix_content
*buffer_prefix_content,
struct fman_sp_buf_margins *buf_margins,
struct fman_sp_buffer_offsets
*buffer_offsets,
u8 *internal_buf_offset);
void fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(struct fman_ext_pools
*fm_ext_pools,
u8 *ordered_array,
u16 *sizes_array);
#endif /* __FM_SP_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_tgec.c
+816
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@@ -0,0 +1,816 @@
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include "fman_tgec.h"
#include "fman.h"
#include "mac.h"
#include <linux/slab.h>
#include <linux/bitrev.h>
#include <linux/io.h>
#include <linux/crc32.h>
#include <linux/netdevice.h>
/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
#define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
/* Command and Configuration Register (COMMAND_CONFIG) */
#define CMD_CFG_EN_TIMESTAMP 0x00100000
#define CMD_CFG_NO_LEN_CHK 0x00020000
#define CMD_CFG_PAUSE_IGNORE 0x00000100
#define CMF_CFG_CRC_FWD 0x00000040
#define CMD_CFG_PROMIS_EN 0x00000010
#define CMD_CFG_RX_EN 0x00000002
#define CMD_CFG_TX_EN 0x00000001
/* Interrupt Mask Register (IMASK) */
#define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000
#define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000
#define TGEC_IMASK_REM_FAULT 0x00004000
#define TGEC_IMASK_LOC_FAULT 0x00002000
#define TGEC_IMASK_TX_ECC_ER 0x00001000
#define TGEC_IMASK_TX_FIFO_UNFL 0x00000800
#define TGEC_IMASK_TX_FIFO_OVFL 0x00000400
#define TGEC_IMASK_TX_ER 0x00000200
#define TGEC_IMASK_RX_FIFO_OVFL 0x00000100
#define TGEC_IMASK_RX_ECC_ER 0x00000080
#define TGEC_IMASK_RX_JAB_FRM 0x00000040
#define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020
#define TGEC_IMASK_RX_RUNT_FRM 0x00000010
#define TGEC_IMASK_RX_FRAG_FRM 0x00000008
#define TGEC_IMASK_RX_LEN_ER 0x00000004
#define TGEC_IMASK_RX_CRC_ER 0x00000002
#define TGEC_IMASK_RX_ALIGN_ER 0x00000001
/* Hashtable Control Register (HASHTABLE_CTRL) */
#define TGEC_HASH_MCAST_SHIFT 23
#define TGEC_HASH_MCAST_EN 0x00000200
#define TGEC_HASH_ADR_MSK 0x000001ff
#define DEFAULT_TX_IPG_LENGTH 12
#define DEFAULT_MAX_FRAME_LENGTH 0x600
#define DEFAULT_PAUSE_QUANT 0xf000
/* number of pattern match registers (entries) */
#define TGEC_NUM_OF_PADDRS 1
/* Group address bit indication */
#define GROUP_ADDRESS 0x0000010000000000LL
/* Hash table size (= 32 bits*8 regs) */
#define TGEC_HASH_TABLE_SIZE 512
/* tGEC memory map */
struct tgec_regs {
u32 tgec_id; /* 0x000 Controller ID */
u32 reserved001[1]; /* 0x004 */
u32 command_config; /* 0x008 Control and configuration */
u32 mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */
u32 mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */
u32 maxfrm; /* 0x014 Maximum frame length */
u32 pause_quant; /* 0x018 Pause quanta */
u32 rx_fifo_sections; /* 0x01c */
u32 tx_fifo_sections; /* 0x020 */
u32 rx_fifo_almost_f_e; /* 0x024 */
u32 tx_fifo_almost_f_e; /* 0x028 */
u32 hashtable_ctrl; /* 0x02c Hash table control */
u32 mdio_cfg_status; /* 0x030 */
u32 mdio_command; /* 0x034 */
u32 mdio_data; /* 0x038 */
u32 mdio_regaddr; /* 0x03c */
u32 status; /* 0x040 */
u32 tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */
u32 mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */
u32 mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */
u32 rx_fifo_ptr_rd; /* 0x050 */
u32 rx_fifo_ptr_wr; /* 0x054 */
u32 tx_fifo_ptr_rd; /* 0x058 */
u32 tx_fifo_ptr_wr; /* 0x05c */
u32 imask; /* 0x060 Interrupt mask */
u32 ievent; /* 0x064 Interrupt event */
u32 udp_port; /* 0x068 Defines a UDP Port number */
u32 type_1588v2; /* 0x06c Type field for 1588v2 */
u32 reserved070[4]; /* 0x070 */
/* 10Ge Statistics Counter */
u32 tfrm_u; /* 80 aFramesTransmittedOK */
u32 tfrm_l; /* 84 aFramesTransmittedOK */
u32 rfrm_u; /* 88 aFramesReceivedOK */
u32 rfrm_l; /* 8c aFramesReceivedOK */
u32 rfcs_u; /* 90 aFrameCheckSequenceErrors */
u32 rfcs_l; /* 94 aFrameCheckSequenceErrors */
u32 raln_u; /* 98 aAlignmentErrors */
u32 raln_l; /* 9c aAlignmentErrors */
u32 txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */
u32 txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */
u32 rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */
u32 rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */
u32 rlong_u; /* B0 aFrameTooLongErrors */
u32 rlong_l; /* B4 aFrameTooLongErrors */
u32 rflr_u; /* B8 aInRangeLengthErrors */
u32 rflr_l; /* Bc aInRangeLengthErrors */
u32 tvlan_u; /* C0 VLANTransmittedOK */
u32 tvlan_l; /* C4 VLANTransmittedOK */
u32 rvlan_u; /* C8 VLANReceivedOK */
u32 rvlan_l; /* Cc VLANReceivedOK */
u32 toct_u; /* D0 if_out_octets */
u32 toct_l; /* D4 if_out_octets */
u32 roct_u; /* D8 if_in_octets */
u32 roct_l; /* Dc if_in_octets */
u32 ruca_u; /* E0 if_in_ucast_pkts */
u32 ruca_l; /* E4 if_in_ucast_pkts */
u32 rmca_u; /* E8 ifInMulticastPkts */
u32 rmca_l; /* Ec ifInMulticastPkts */
u32 rbca_u; /* F0 ifInBroadcastPkts */
u32 rbca_l; /* F4 ifInBroadcastPkts */
u32 terr_u; /* F8 if_out_errors */
u32 terr_l; /* Fc if_out_errors */
u32 reserved100[2]; /* 100-108 */
u32 tuca_u; /* 108 if_out_ucast_pkts */
u32 tuca_l; /* 10c if_out_ucast_pkts */
u32 tmca_u; /* 110 ifOutMulticastPkts */
u32 tmca_l; /* 114 ifOutMulticastPkts */
u32 tbca_u; /* 118 ifOutBroadcastPkts */
u32 tbca_l; /* 11c ifOutBroadcastPkts */
u32 rdrp_u; /* 120 etherStatsDropEvents */
u32 rdrp_l; /* 124 etherStatsDropEvents */
u32 reoct_u; /* 128 etherStatsOctets */
u32 reoct_l; /* 12c etherStatsOctets */
u32 rpkt_u; /* 130 etherStatsPkts */
u32 rpkt_l; /* 134 etherStatsPkts */
u32 trund_u; /* 138 etherStatsUndersizePkts */
u32 trund_l; /* 13c etherStatsUndersizePkts */
u32 r64_u; /* 140 etherStatsPkts64Octets */
u32 r64_l; /* 144 etherStatsPkts64Octets */
u32 r127_u; /* 148 etherStatsPkts65to127Octets */
u32 r127_l; /* 14c etherStatsPkts65to127Octets */
u32 r255_u; /* 150 etherStatsPkts128to255Octets */
u32 r255_l; /* 154 etherStatsPkts128to255Octets */
u32 r511_u; /* 158 etherStatsPkts256to511Octets */
u32 r511_l; /* 15c etherStatsPkts256to511Octets */
u32 r1023_u; /* 160 etherStatsPkts512to1023Octets */
u32 r1023_l; /* 164 etherStatsPkts512to1023Octets */
u32 r1518_u; /* 168 etherStatsPkts1024to1518Octets */
u32 r1518_l; /* 16c etherStatsPkts1024to1518Octets */
u32 r1519x_u; /* 170 etherStatsPkts1519toX */
u32 r1519x_l; /* 174 etherStatsPkts1519toX */
u32 trovr_u; /* 178 etherStatsOversizePkts */
u32 trovr_l; /* 17c etherStatsOversizePkts */
u32 trjbr_u; /* 180 etherStatsJabbers */
u32 trjbr_l; /* 184 etherStatsJabbers */
u32 trfrg_u; /* 188 etherStatsFragments */
u32 trfrg_l; /* 18C etherStatsFragments */
u32 rerr_u; /* 190 if_in_errors */
u32 rerr_l; /* 194 if_in_errors */
};
struct tgec_cfg {
bool pause_ignore;
bool promiscuous_mode_enable;
u16 max_frame_length;
u16 pause_quant;
u32 tx_ipg_length;
};
struct fman_mac {
/* Pointer to the memory mapped registers. */
struct tgec_regs __iomem *regs;
/* MAC address of device; */
u64 addr;
u16 max_speed;
struct mac_device *dev_id; /* device cookie used by the exception cbs */
fman_mac_exception_cb *exception_cb;
fman_mac_exception_cb *event_cb;
/* pointer to driver's global address hash table */
struct eth_hash_t *multicast_addr_hash;
/* pointer to driver's individual address hash table */
struct eth_hash_t *unicast_addr_hash;
u8 mac_id;
u32 exceptions;
struct tgec_cfg *cfg;
void *fm;
struct fman_rev_info fm_rev_info;
bool allmulti_enabled;
};
static void set_mac_address(struct tgec_regs __iomem *regs, const u8 *adr)
{
u32 tmp0, tmp1;
tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
tmp1 = (u32)(adr[4] | adr[5] << 8);
iowrite32be(tmp0, &regs->mac_addr_0);
iowrite32be(tmp1, &regs->mac_addr_1);
}
static void set_dflts(struct tgec_cfg *cfg)
{
cfg->promiscuous_mode_enable = false;
cfg->pause_ignore = false;
cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
cfg->pause_quant = DEFAULT_PAUSE_QUANT;
}
static int init(struct tgec_regs __iomem *regs, struct tgec_cfg *cfg,
u32 exception_mask)
{
u32 tmp;
/* Config */
tmp = CMF_CFG_CRC_FWD;
if (cfg->promiscuous_mode_enable)
tmp |= CMD_CFG_PROMIS_EN;
if (cfg->pause_ignore)
tmp |= CMD_CFG_PAUSE_IGNORE;
/* Payload length check disable */
tmp |= CMD_CFG_NO_LEN_CHK;
iowrite32be(tmp, &regs->command_config);
/* Max Frame Length */
iowrite32be((u32)cfg->max_frame_length, &regs->maxfrm);
/* Pause Time */
iowrite32be(cfg->pause_quant, &regs->pause_quant);
/* clear all pending events and set-up interrupts */
iowrite32be(0xffffffff, &regs->ievent);
iowrite32be(ioread32be(&regs->imask) | exception_mask, &regs->imask);
return 0;
}
static int check_init_parameters(struct fman_mac *tgec)
{
if (!tgec->exception_cb) {
pr_err("uninitialized exception_cb\n");
return -EINVAL;
}
if (!tgec->event_cb) {
pr_err("uninitialized event_cb\n");
return -EINVAL;
}
return 0;
}
static int get_exception_flag(enum fman_mac_exceptions exception)
{
u32 bit_mask;
switch (exception) {
case FM_MAC_EX_10G_MDIO_SCAN_EVENT:
bit_mask = TGEC_IMASK_MDIO_SCAN_EVENT;
break;
case FM_MAC_EX_10G_MDIO_CMD_CMPL:
bit_mask = TGEC_IMASK_MDIO_CMD_CMPL;
break;
case FM_MAC_EX_10G_REM_FAULT:
bit_mask = TGEC_IMASK_REM_FAULT;
break;
case FM_MAC_EX_10G_LOC_FAULT:
bit_mask = TGEC_IMASK_LOC_FAULT;
break;
case FM_MAC_EX_10G_TX_ECC_ER:
bit_mask = TGEC_IMASK_TX_ECC_ER;
break;
case FM_MAC_EX_10G_TX_FIFO_UNFL:
bit_mask = TGEC_IMASK_TX_FIFO_UNFL;
break;
case FM_MAC_EX_10G_TX_FIFO_OVFL:
bit_mask = TGEC_IMASK_TX_FIFO_OVFL;
break;
case FM_MAC_EX_10G_TX_ER:
bit_mask = TGEC_IMASK_TX_ER;
break;
case FM_MAC_EX_10G_RX_FIFO_OVFL:
bit_mask = TGEC_IMASK_RX_FIFO_OVFL;
break;
case FM_MAC_EX_10G_RX_ECC_ER:
bit_mask = TGEC_IMASK_RX_ECC_ER;
break;
case FM_MAC_EX_10G_RX_JAB_FRM:
bit_mask = TGEC_IMASK_RX_JAB_FRM;
break;
case FM_MAC_EX_10G_RX_OVRSZ_FRM:
bit_mask = TGEC_IMASK_RX_OVRSZ_FRM;
break;
case FM_MAC_EX_10G_RX_RUNT_FRM:
bit_mask = TGEC_IMASK_RX_RUNT_FRM;
break;
case FM_MAC_EX_10G_RX_FRAG_FRM:
bit_mask = TGEC_IMASK_RX_FRAG_FRM;
break;
case FM_MAC_EX_10G_RX_LEN_ER:
bit_mask = TGEC_IMASK_RX_LEN_ER;
break;
case FM_MAC_EX_10G_RX_CRC_ER:
bit_mask = TGEC_IMASK_RX_CRC_ER;
break;
case FM_MAC_EX_10G_RX_ALIGN_ER:
bit_mask = TGEC_IMASK_RX_ALIGN_ER;
break;
default:
bit_mask = 0;
break;
}
return bit_mask;
}
static void tgec_err_exception(void *handle)
{
struct fman_mac *tgec = (struct fman_mac *)handle;
struct tgec_regs __iomem *regs = tgec->regs;
u32 event;
/* do not handle MDIO events */
event = ioread32be(&regs->ievent) &
~(TGEC_IMASK_MDIO_SCAN_EVENT |
TGEC_IMASK_MDIO_CMD_CMPL);
event &= ioread32be(&regs->imask);
iowrite32be(event, &regs->ievent);
if (event & TGEC_IMASK_REM_FAULT)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_REM_FAULT);
if (event & TGEC_IMASK_LOC_FAULT)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_LOC_FAULT);
if (event & TGEC_IMASK_TX_ECC_ER)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
if (event & TGEC_IMASK_TX_FIFO_UNFL)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_UNFL);
if (event & TGEC_IMASK_TX_FIFO_OVFL)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_OVFL);
if (event & TGEC_IMASK_TX_ER)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ER);
if (event & TGEC_IMASK_RX_FIFO_OVFL)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FIFO_OVFL);
if (event & TGEC_IMASK_RX_ECC_ER)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
if (event & TGEC_IMASK_RX_JAB_FRM)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_JAB_FRM);
if (event & TGEC_IMASK_RX_OVRSZ_FRM)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_OVRSZ_FRM);
if (event & TGEC_IMASK_RX_RUNT_FRM)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_RUNT_FRM);
if (event & TGEC_IMASK_RX_FRAG_FRM)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FRAG_FRM);
if (event & TGEC_IMASK_RX_LEN_ER)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_LEN_ER);
if (event & TGEC_IMASK_RX_CRC_ER)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_CRC_ER);
if (event & TGEC_IMASK_RX_ALIGN_ER)
tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ALIGN_ER);
}
static void free_init_resources(struct fman_mac *tgec)
{
fman_unregister_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id,
FMAN_INTR_TYPE_ERR);
/* release the driver's group hash table */
free_hash_table(tgec->multicast_addr_hash);
tgec->multicast_addr_hash = NULL;
/* release the driver's individual hash table */
free_hash_table(tgec->unicast_addr_hash);
tgec->unicast_addr_hash = NULL;
}
static int tgec_enable(struct fman_mac *tgec)
{
return 0;
}
static void tgec_disable(struct fman_mac *tgec)
{
}
static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
{
struct tgec_regs __iomem *regs = tgec->regs;
u32 tmp;
tmp = ioread32be(&regs->command_config);
if (new_val)
tmp |= CMD_CFG_PROMIS_EN;
else
tmp &= ~CMD_CFG_PROMIS_EN;
iowrite32be(tmp, &regs->command_config);
return 0;
}
static int tgec_set_tx_pause_frames(struct fman_mac *tgec,
u8 __maybe_unused priority, u16 pause_time,
u16 __maybe_unused thresh_time)
{
struct tgec_regs __iomem *regs = tgec->regs;
iowrite32be((u32)pause_time, &regs->pause_quant);
return 0;
}
static int tgec_accept_rx_pause_frames(struct fman_mac *tgec, bool en)
{
struct tgec_regs __iomem *regs = tgec->regs;
u32 tmp;
tmp = ioread32be(&regs->command_config);
if (!en)
tmp |= CMD_CFG_PAUSE_IGNORE;
else
tmp &= ~CMD_CFG_PAUSE_IGNORE;
iowrite32be(tmp, &regs->command_config);
return 0;
}
static void tgec_mac_config(struct phylink_config *config, unsigned int mode,
const struct phylink_link_state *state)
{
}
static void tgec_link_up(struct phylink_config *config, struct phy_device *phy,
unsigned int mode, phy_interface_t interface,
int speed, int duplex, bool tx_pause, bool rx_pause)
{
struct mac_device *mac_dev = fman_config_to_mac(config);
struct fman_mac *tgec = mac_dev->fman_mac;
struct tgec_regs __iomem *regs = tgec->regs;
u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
FSL_FM_PAUSE_TIME_DISABLE;
u32 tmp;
tgec_set_tx_pause_frames(tgec, 0, pause_time, 0);
tgec_accept_rx_pause_frames(tgec, rx_pause);
mac_dev->update_speed(mac_dev, speed);
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
static void tgec_link_down(struct phylink_config *config, unsigned int mode,
phy_interface_t interface)
{
struct fman_mac *tgec = fman_config_to_mac(config)->fman_mac;
struct tgec_regs __iomem *regs = tgec->regs;
u32 tmp;
tmp = ioread32be(&regs->command_config);
tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
iowrite32be(tmp, &regs->command_config);
}
static const struct phylink_mac_ops tgec_mac_ops = {
.mac_config = tgec_mac_config,
.mac_link_up = tgec_link_up,
.mac_link_down = tgec_link_down,
};
static int tgec_modify_mac_address(struct fman_mac *tgec,
const enet_addr_t *p_enet_addr)
{
tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr));
return 0;
}
static int tgec_add_hash_mac_address(struct fman_mac *tgec,
enet_addr_t *eth_addr)
{
struct tgec_regs __iomem *regs = tgec->regs;
struct eth_hash_entry *hash_entry;
u32 crc = 0xFFFFFFFF, hash;
u64 addr;
addr = ENET_ADDR_TO_UINT64(*eth_addr);
if (!(addr & GROUP_ADDRESS)) {
/* Unicast addresses not supported in hash */
pr_err("Unicast Address\n");
return -EINVAL;
}
/* CRC calculation */
crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN);
crc = bitrev32(crc);
/* Take 9 MSB bits */
hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;
/* Create element to be added to the driver hash table */
hash_entry = kmalloc_obj(*hash_entry, GFP_ATOMIC);
if (!hash_entry)
return -ENOMEM;
hash_entry->addr = addr;
INIT_LIST_HEAD(&hash_entry->node);
list_add_tail(&hash_entry->node,
&tgec->multicast_addr_hash->lsts[hash]);
iowrite32be((hash | TGEC_HASH_MCAST_EN), &regs->hashtable_ctrl);
return 0;
}
static int tgec_set_allmulti(struct fman_mac *tgec, bool enable)
{
u32 entry;
struct tgec_regs __iomem *regs = tgec->regs;
if (enable) {
for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
iowrite32be(entry | TGEC_HASH_MCAST_EN,
&regs->hashtable_ctrl);
} else {
for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
iowrite32be(entry & ~TGEC_HASH_MCAST_EN,
&regs->hashtable_ctrl);
}
tgec->allmulti_enabled = enable;
return 0;
}
static int tgec_set_tstamp(struct fman_mac *tgec, bool enable)
{
struct tgec_regs __iomem *regs = tgec->regs;
u32 tmp;
tmp = ioread32be(&regs->command_config);
if (enable)
tmp |= CMD_CFG_EN_TIMESTAMP;
else
tmp &= ~CMD_CFG_EN_TIMESTAMP;
iowrite32be(tmp, &regs->command_config);
return 0;
}
static int tgec_del_hash_mac_address(struct fman_mac *tgec,
enet_addr_t *eth_addr)
{
struct tgec_regs __iomem *regs = tgec->regs;
struct eth_hash_entry *hash_entry = NULL;
struct list_head *pos;
u32 crc = 0xFFFFFFFF, hash;
u64 addr;
addr = ((*(u64 *)eth_addr) >> 16);
/* CRC calculation */
crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN);
crc = bitrev32(crc);
/* Take 9 MSB bits */
hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;
list_for_each(pos, &tgec->multicast_addr_hash->lsts[hash]) {
hash_entry = ETH_HASH_ENTRY_OBJ(pos);
if (hash_entry && hash_entry->addr == addr) {
list_del_init(&hash_entry->node);
kfree(hash_entry);
break;
}
}
if (!tgec->allmulti_enabled) {
if (list_empty(&tgec->multicast_addr_hash->lsts[hash]))
iowrite32be((hash & ~TGEC_HASH_MCAST_EN),
&regs->hashtable_ctrl);
}
return 0;
}
static int tgec_set_exception(struct fman_mac *tgec,
enum fman_mac_exceptions exception, bool enable)
{
struct tgec_regs __iomem *regs = tgec->regs;
u32 bit_mask = 0;
bit_mask = get_exception_flag(exception);
if (bit_mask) {
if (enable)
tgec->exceptions |= bit_mask;
else
tgec->exceptions &= ~bit_mask;
} else {
pr_err("Undefined exception\n");
return -EINVAL;
}
if (enable)
iowrite32be(ioread32be(&regs->imask) | bit_mask, &regs->imask);
else
iowrite32be(ioread32be(&regs->imask) & ~bit_mask, &regs->imask);
return 0;
}
static int tgec_init(struct fman_mac *tgec)
{
struct tgec_cfg *cfg;
enet_addr_t eth_addr;
int err;
if (DEFAULT_RESET_ON_INIT &&
(fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
pr_err("Can't reset MAC!\n");
return -EINVAL;
}
err = check_init_parameters(tgec);
if (err)
return err;
cfg = tgec->cfg;
if (tgec->addr) {
MAKE_ENET_ADDR_FROM_UINT64(tgec->addr, eth_addr);
set_mac_address(tgec->regs, (const u8 *)eth_addr);
}
/* interrupts */
/* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 Errata workaround */
if (tgec->fm_rev_info.major <= 2)
tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT |
TGEC_IMASK_LOC_FAULT);
err = init(tgec->regs, cfg, tgec->exceptions);
if (err) {
free_init_resources(tgec);
pr_err("TGEC version doesn't support this i/f mode\n");
return err;
}
/* Max Frame Length */
err = fman_set_mac_max_frame(tgec->fm, tgec->mac_id,
cfg->max_frame_length);
if (err) {
pr_err("Setting max frame length FAILED\n");
free_init_resources(tgec);
return -EINVAL;
}
/* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 Errata workaround */
if (tgec->fm_rev_info.major == 2) {
struct tgec_regs __iomem *regs = tgec->regs;
u32 tmp;
/* restore the default tx ipg Length */
tmp = (ioread32be(&regs->tx_ipg_len) &
~TGEC_TX_IPG_LENGTH_MASK) | 12;
iowrite32be(tmp, &regs->tx_ipg_len);
}
tgec->multicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE);
if (!tgec->multicast_addr_hash) {
free_init_resources(tgec);
pr_err("allocation hash table is FAILED\n");
return -ENOMEM;
}
tgec->unicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE);
if (!tgec->unicast_addr_hash) {
free_init_resources(tgec);
pr_err("allocation hash table is FAILED\n");
return -ENOMEM;
}
fman_register_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id,
FMAN_INTR_TYPE_ERR, tgec_err_exception, tgec);
kfree(cfg);
tgec->cfg = NULL;
return 0;
}
static int tgec_free(struct fman_mac *tgec)
{
free_init_resources(tgec);
kfree(tgec->cfg);
kfree(tgec);
return 0;
}
static struct fman_mac *tgec_config(struct mac_device *mac_dev,
struct fman_mac_params *params)
{
struct fman_mac *tgec;
struct tgec_cfg *cfg;
/* allocate memory for the UCC GETH data structure. */
tgec = kzalloc_obj(*tgec);
if (!tgec)
return NULL;
/* allocate memory for the 10G MAC driver parameters data structure. */
cfg = kzalloc_obj(*cfg);
if (!cfg) {
tgec_free(tgec);
return NULL;
}
/* Plant parameter structure pointer */
tgec->cfg = cfg;
set_dflts(cfg);
tgec->regs = mac_dev->vaddr;
tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
tgec->mac_id = params->mac_id;
tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT |
TGEC_IMASK_REM_FAULT |
TGEC_IMASK_LOC_FAULT |
TGEC_IMASK_TX_ECC_ER |
TGEC_IMASK_TX_FIFO_UNFL |
TGEC_IMASK_TX_FIFO_OVFL |
TGEC_IMASK_TX_ER |
TGEC_IMASK_RX_FIFO_OVFL |
TGEC_IMASK_RX_ECC_ER |
TGEC_IMASK_RX_JAB_FRM |
TGEC_IMASK_RX_OVRSZ_FRM |
TGEC_IMASK_RX_RUNT_FRM |
TGEC_IMASK_RX_FRAG_FRM |
TGEC_IMASK_RX_CRC_ER |
TGEC_IMASK_RX_ALIGN_ER);
tgec->exception_cb = params->exception_cb;
tgec->event_cb = params->event_cb;
tgec->dev_id = mac_dev;
tgec->fm = params->fm;
/* Save FMan revision */
fman_get_revision(tgec->fm, &tgec->fm_rev_info);
return tgec;
}
int tgec_initialization(struct mac_device *mac_dev,
struct device_node *mac_node,
struct fman_mac_params *params)
{
int err;
struct fman_mac *tgec;
mac_dev->phylink_ops = &tgec_mac_ops;
mac_dev->set_promisc = tgec_set_promiscuous;
mac_dev->change_addr = tgec_modify_mac_address;
mac_dev->add_hash_mac_addr = tgec_add_hash_mac_address;
mac_dev->remove_hash_mac_addr = tgec_del_hash_mac_address;
mac_dev->set_exception = tgec_set_exception;
mac_dev->set_allmulti = tgec_set_allmulti;
mac_dev->set_tstamp = tgec_set_tstamp;
mac_dev->enable = tgec_enable;
mac_dev->disable = tgec_disable;
mac_dev->fman_mac = tgec_config(mac_dev, params);
if (!mac_dev->fman_mac) {
err = -EINVAL;
goto _return;
}
/* The internal connection to the serdes is XGMII, but this isn't
* really correct for the phy mode (which is the external connection).
* However, this is how all older device trees say that they want
* XAUI, so just convert it for them.
*/
if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
mac_dev->phy_if = PHY_INTERFACE_MODE_XAUI;
__set_bit(PHY_INTERFACE_MODE_XAUI,
mac_dev->phylink_config.supported_interfaces);
mac_dev->phylink_config.mac_capabilities =
MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10000FD;
tgec = mac_dev->fman_mac;
tgec->cfg->max_frame_length = fman_get_max_frm();
err = tgec_init(tgec);
if (err < 0)
goto _return_fm_mac_free;
/* For 10G MAC, disable Tx ECC exception */
err = tgec_set_exception(tgec, FM_MAC_EX_10G_TX_ECC_ER, false);
if (err < 0)
goto _return_fm_mac_free;
pr_info("FMan XGEC version: 0x%08x\n",
ioread32be(&tgec->regs->tgec_id));
goto _return;
_return_fm_mac_free:
tgec_free(mac_dev->fman_mac);
_return:
return err;
}
linux-7.2.3/drivers/net/ethernet/freescale/fman/fman_tgec.h
+17
View File
@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __TGEC_H
#define __TGEC_H
#include "fman_mac.h"
struct mac_device;
int tgec_initialization(struct mac_device *mac_dev,
struct device_node *mac_node,
struct fman_mac_params *params);
#endif /* __TGEC_H */
linux-7.2.3/drivers/net/ethernet/freescale/fman/mac.c
+346
View File
@@ -0,0 +1,346 @@
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/device.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/libfdt_env.h>
#include <linux/platform_device.h>
#include "mac.h"
#include "fman_mac.h"
#include "fman_dtsec.h"
#include "fman_tgec.h"
#include "fman_memac.h"
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("FSL FMan MAC API based driver");
struct mac_priv_s {
u8 cell_index;
struct fman *fman;
struct platform_device *eth_dev;
u16 speed;
};
struct mac_address {
u8 addr[ETH_ALEN];
struct list_head list;
};
static void mac_exception(struct mac_device *mac_dev,
enum fman_mac_exceptions ex)
{
if (ex == FM_MAC_EX_10G_RX_FIFO_OVFL) {
/* don't flag RX FIFO after the first */
mac_dev->set_exception(mac_dev->fman_mac,
FM_MAC_EX_10G_RX_FIFO_OVFL, false);
dev_err(mac_dev->dev, "10G MAC got RX FIFO Error = %x\n", ex);
}
dev_dbg(mac_dev->dev, "%s:%s() -> %d\n", KBUILD_BASENAME ".c",
__func__, ex);
}
static DEFINE_MUTEX(eth_lock);
static struct platform_device *dpaa_eth_add_device(int fman_id,
struct mac_device *mac_dev)
{
struct platform_device *pdev;
struct dpaa_eth_data data;
struct mac_priv_s *priv;
static int dpaa_eth_dev_cnt;
int ret;
priv = mac_dev->priv;
data.mac_dev = mac_dev;
data.mac_hw_id = priv->cell_index;
data.fman_hw_id = fman_id;
mutex_lock(&eth_lock);
pdev = platform_device_alloc("dpaa-ethernet", dpaa_eth_dev_cnt);
if (!pdev) {
ret = -ENOMEM;
goto no_mem;
}
pdev->dev.parent = mac_dev->dev;
ret = platform_device_add_data(pdev, &data, sizeof(data));
if (ret)
goto err;
ret = platform_device_add(pdev);
if (ret)
goto err;
dpaa_eth_dev_cnt++;
mutex_unlock(&eth_lock);
return pdev;
err:
platform_device_put(pdev);
no_mem:
mutex_unlock(&eth_lock);
return ERR_PTR(ret);
}
static const struct of_device_id mac_match[] = {
{ .compatible = "fsl,fman-dtsec", .data = dtsec_initialization },
{ .compatible = "fsl,fman-xgec", .data = tgec_initialization },
{ .compatible = "fsl,fman-memac", .data = memac_initialization },
{}
};
MODULE_DEVICE_TABLE(of, mac_match);
static int mac_probe(struct platform_device *_of_dev)
{
int err, i, nph;
int (*init)(struct mac_device *mac_dev, struct device_node *mac_node,
struct fman_mac_params *params);
struct device *dev;
struct device_node *mac_node, *dev_node;
struct mac_device *mac_dev;
struct platform_device *of_dev;
struct mac_priv_s *priv;
struct fman_mac_params params;
u32 val;
u8 fman_id;
phy_interface_t phy_if;
dev = &_of_dev->dev;
mac_node = dev->of_node;
init = of_device_get_match_data(dev);
mac_dev = devm_kzalloc(dev, sizeof(*mac_dev), GFP_KERNEL);
if (!mac_dev)
return -ENOMEM;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(_of_dev, mac_dev);
/* Save private information */
mac_dev->priv = priv;
mac_dev->dev = dev;
/* Get the FM node */
dev_node = of_get_parent(mac_node);
if (!dev_node) {
dev_err(dev, "of_get_parent(%pOF) failed\n",
mac_node);
return -EINVAL;
}
of_dev = of_find_device_by_node(dev_node);
if (!of_dev) {
dev_err(dev, "of_find_device_by_node(%pOF) failed\n", dev_node);
err = -EINVAL;
goto _return_of_node_put;
}
mac_dev->fman_dev = &of_dev->dev;
/* Get the FMan cell-index */
err = of_property_read_u32(dev_node, "cell-index", &val);
if (err) {
dev_err(dev, "failed to read cell-index for %pOF\n", dev_node);
err = -EINVAL;
goto _return_dev_put;
}
/* cell-index 0 => FMan id 1 */
fman_id = (u8)(val + 1);
priv->fman = fman_bind(mac_dev->fman_dev);
if (!priv->fman) {
dev_err(dev, "fman_bind(%pOF) failed\n", dev_node);
err = -ENODEV;
goto _return_dev_put;
}
/* Two references have been taken in of_find_device_by_node()
* and fman_bind(). Release one of them here. The second one
* will be released in mac_remove().
*/
put_device(mac_dev->fman_dev);
of_node_put(dev_node);
dev_node = NULL;
/* Get the address of the memory mapped registers */
mac_dev->res = platform_get_mem_or_io(_of_dev, 0);
if (!mac_dev->res) {
dev_err(dev, "could not get registers\n");
err = -EINVAL;
goto _return_dev_put;
}
err = devm_request_resource(dev, fman_get_mem_region(priv->fman),
mac_dev->res);
if (err) {
dev_err_probe(dev, err, "could not request resource\n");
goto _return_dev_put;
}
mac_dev->vaddr = devm_ioremap(dev, mac_dev->res->start,
resource_size(mac_dev->res));
if (!mac_dev->vaddr) {
dev_err(dev, "devm_ioremap() failed\n");
err = -EIO;
goto _return_dev_put;
}
if (!of_device_is_available(mac_node)) {
err = -ENODEV;
goto _return_dev_put;
}
/* Get the cell-index */
err = of_property_read_u32(mac_node, "cell-index", &val);
if (err) {
dev_err(dev, "failed to read cell-index for %pOF\n", mac_node);
err = -EINVAL;
goto _return_dev_put;
}
if (val >= MAX_NUM_OF_MACS) {
dev_err(dev, "cell-index value is too big for %pOF\n", mac_node);
err = -EINVAL;
goto _return_dev_put;
}
priv->cell_index = (u8)val;
/* Get the MAC address */
err = of_get_mac_address(mac_node, mac_dev->addr);
if (err)
dev_warn(dev, "of_get_mac_address(%pOF) failed\n", mac_node);
/* Get the port handles */
nph = of_count_phandle_with_args(mac_node, "fsl,fman-ports", NULL);
if (unlikely(nph < 0)) {
dev_err(dev, "of_count_phandle_with_args(%pOF, fsl,fman-ports) failed\n",
mac_node);
err = nph;
goto _return_dev_put;
}
if (nph != ARRAY_SIZE(mac_dev->port)) {
dev_err(dev, "Not supported number of fman-ports handles of mac node %pOF from device tree\n",
mac_node);
err = -EINVAL;
goto _return_dev_put;
}
/* PORT_NUM determines the size of the port array */
for (i = 0; i < PORT_NUM; i++) {
/* Find the port node */
dev_node = of_parse_phandle(mac_node, "fsl,fman-ports", i);
if (!dev_node) {
dev_err(dev, "of_parse_phandle(%pOF, fsl,fman-ports) failed\n",
mac_node);
err = -EINVAL;
goto _return_dev_arr_put;
}
of_dev = of_find_device_by_node(dev_node);
if (!of_dev) {
dev_err(dev, "of_find_device_by_node(%pOF) failed\n",
dev_node);
err = -EINVAL;
goto _return_dev_arr_put;
}
mac_dev->fman_port_devs[i] = &of_dev->dev;
mac_dev->port[i] = fman_port_bind(mac_dev->fman_port_devs[i]);
if (!mac_dev->port[i]) {
dev_err(dev, "dev_get_drvdata(%pOF) failed\n",
dev_node);
err = -EINVAL;
goto _return_dev_arr_put;
}
/* Two references have been taken in of_find_device_by_node()
* and fman_port_bind(). Release one of them here. The second
* one will be released in mac_remove().
*/
put_device(mac_dev->fman_port_devs[i]);
of_node_put(dev_node);
dev_node = NULL;
}
/* Get the PHY connection type */
err = of_get_phy_mode(mac_node, &phy_if);
if (err) {
dev_warn(dev,
"of_get_phy_mode() for %pOF failed. Defaulting to SGMII\n",
mac_node);
phy_if = PHY_INTERFACE_MODE_SGMII;
}
mac_dev->phy_if = phy_if;
params.mac_id = priv->cell_index;
params.fm = (void *)priv->fman;
params.exception_cb = mac_exception;
params.event_cb = mac_exception;
err = init(mac_dev, mac_node, &params);
if (err < 0)
goto _return_dev_arr_put;
if (!is_zero_ether_addr(mac_dev->addr))
dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr);
priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
if (IS_ERR(priv->eth_dev)) {
err = PTR_ERR(priv->eth_dev);
dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
priv->cell_index);
priv->eth_dev = NULL;
}
return err;
_return_dev_arr_put:
/* mac_dev is kzalloc'ed */
for (i = 0; i < PORT_NUM; i++)
put_device(mac_dev->fman_port_devs[i]);
_return_dev_put:
put_device(mac_dev->fman_dev);
_return_of_node_put:
of_node_put(dev_node);
return err;
}
static void mac_remove(struct platform_device *pdev)
{
struct mac_device *mac_dev = platform_get_drvdata(pdev);
int i;
for (i = 0; i < PORT_NUM; i++)
put_device(mac_dev->fman_port_devs[i]);
put_device(mac_dev->fman_dev);
platform_device_unregister(mac_dev->priv->eth_dev);
}
static struct platform_driver mac_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = mac_match,
},
.probe = mac_probe,
.remove = mac_remove,
};
builtin_platform_driver(mac_driver);
linux-7.2.3/drivers/net/ethernet/freescale/fman/mac.h
+89
View File
@@ -0,0 +1,89 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
/*
* Copyright 2008 - 2015 Freescale Semiconductor Inc.
*/
#ifndef __MAC_H
#define __MAC_H
#include <linux/device.h>
#include <linux/if_ether.h>
#include <linux/phy.h>
#include <linux/phylink.h>
#include <linux/list.h>
#include "fman_port.h"
#include "fman.h"
#include "fman_mac.h"
struct ethtool_eth_ctrl_stats;
struct ethtool_eth_mac_stats;
struct ethtool_pause_stats;
struct ethtool_rmon_stats;
struct ethtool_rmon_hist_range;
struct fman_mac;
struct mac_priv_s;
#define PORT_NUM 2
struct mac_device {
void __iomem *vaddr;
struct device *dev;
struct resource *res;
u8 addr[ETH_ALEN];
struct fman_port *port[PORT_NUM];
struct phylink *phylink;
struct phylink_config phylink_config;
phy_interface_t phy_if;
bool promisc;
bool allmulti;
const struct phylink_mac_ops *phylink_ops;
int (*enable)(struct fman_mac *mac_dev);
void (*disable)(struct fman_mac *mac_dev);
int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
int (*change_addr)(struct fman_mac *mac_dev, const enet_addr_t *enet_addr);
int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
int (*set_tstamp)(struct fman_mac *mac_dev, bool enable);
int (*set_exception)(struct fman_mac *mac_dev,
enum fman_mac_exceptions exception, bool enable);
int (*add_hash_mac_addr)(struct fman_mac *mac_dev,
enet_addr_t *eth_addr);
int (*remove_hash_mac_addr)(struct fman_mac *mac_dev,
enet_addr_t *eth_addr);
void (*get_pause_stats)(struct fman_mac *memac,
struct ethtool_pause_stats *s);
void (*get_rmon_stats)(struct fman_mac *memac,
struct ethtool_rmon_stats *s,
const struct ethtool_rmon_hist_range **ranges);
void (*get_eth_ctrl_stats)(struct fman_mac *memac,
struct ethtool_eth_ctrl_stats *s);
void (*get_eth_mac_stats)(struct fman_mac *memac,
struct ethtool_eth_mac_stats *s);
void (*update_speed)(struct mac_device *mac_dev, int speed);
struct fman_mac *fman_mac;
struct mac_priv_s *priv;
struct device *fman_dev;
struct device *fman_port_devs[PORT_NUM];
};
static inline struct mac_device
*fman_config_to_mac(struct phylink_config *config)
{
return container_of(config, struct mac_device, phylink_config);
}
struct dpaa_eth_data {
struct mac_device *mac_dev;
int mac_hw_id;
int fman_hw_id;
};
extern const char *mac_driver_description;
int fman_set_multi(struct net_device *net_dev, struct mac_device *mac_dev);
#endif /* __MAC_H */