lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/Makefile
+16
View File
@@ -0,0 +1,16 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for Marvell's RVU Admin Function driver
#
ccflags-y += -I$(src)
obj-$(CONFIG_OCTEONTX2_MBOX) += rvu_mbox.o
obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o
rvu_mbox-y := mbox.o rvu_trace.o
rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \
rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \
rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \
rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \
cn20k/npa.o cn20k/npc.o
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
+2079
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
+191
View File
@@ -0,0 +1,191 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell OcteonTx2 CGX driver
*
* Copyright (C) 2018 Marvell.
*
*/
#ifndef CGX_H
#define CGX_H
#include "mbox.h"
#include "cgx_fw_if.h"
#include "rpm.h"
/* PCI device IDs */
#define PCI_DEVID_OCTEONTX2_CGX 0xA059
/* PCI BAR nos */
#define PCI_CFG_REG_BAR_NUM 0
#define CGX_ID_MASK 0xF
/* Registers */
#define CGXX_CMRX_CFG 0x00
#define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)
#define CMR_P2X_SEL_SHIFT 59ULL
#define CMR_P2X_SEL_NIX0 1ULL
#define CMR_P2X_SEL_NIX1 2ULL
#define DATA_PKT_TX_EN BIT_ULL(53)
#define DATA_PKT_RX_EN BIT_ULL(54)
#define CGX_LMAC_TYPE_SHIFT 40
#define CGX_LMAC_TYPE_MASK 0xF
#define CGXX_CMRX_INT 0x040
#define FW_CGX_INT BIT_ULL(1)
#define CGXX_CMR_GLOBAL_CONFIG 0x08
#define CGX_NIX0_RESET BIT_ULL(2)
#define CGX_NIX1_RESET BIT_ULL(3)
#define CGX_NSCI_DROP BIT_ULL(9)
#define CGXX_CMRX_INT_ENA_W1S 0x058
#define CGXX_CMRX_RX_ID_MAP 0x060
#define CGXX_CMRX_RX_STAT0 0x070
#define CGXX_CMRX_RX_LOGL_XON 0x100
#define CGXX_CMRX_RX_LMACS 0x128
#define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)
#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
#define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
#define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)
#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
#define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)
#define CGXX_CMRX_RX_DMAC_CAM1 0x400
#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
#define CGXX_CMRX_TX_STAT0 0x700
#define CGXX_SCRATCH0_REG 0x1050
#define CGXX_SCRATCH1_REG 0x1058
#define CGX_CONST 0x2000
#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(55, 32)
#define CGX_CONST_MAX_LMACS GENMASK_ULL(31, 24)
#define CGXX_SPUX_CONTROL1 0x10000
#define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x10700
#define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x10800
#define CGXX_SPUX_RSFEC_CORR 0x10088
#define CGXX_SPUX_RSFEC_UNCORR 0x10090
#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
#define CGXX_GMP_PCS_MRX_CTL 0x30000
#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
#define CGXX_SMUX_RX_FRM_CTL 0x20020
#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
#define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12)
#define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028
#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
#define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
#define CGXX_SMUX_TX_CTL 0x20178
#define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110
#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
#define CGXX_SMUX_SMAC 0x20108
#define CGXX_SMUX_CBFC_CTL 0x20218
#define CGXX_SMUX_CBFC_CTL_RX_EN BIT_ULL(0)
#define CGXX_SMUX_CBFC_CTL_TX_EN BIT_ULL(1)
#define CGXX_SMUX_CBFC_CTL_DRP_EN BIT_ULL(2)
#define CGXX_SMUX_CBFC_CTL_BCK_EN BIT_ULL(3)
#define CGX_PFC_CLASS_MASK GENMASK_ULL(47, 32)
#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230
#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248
#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
#define CGXX_CMR_RX_OVR_BP 0x130
#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))
#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))
#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
#define CGX_EVENT_REG CGXX_SCRATCH0_REG
#define CGX_CMD_TIMEOUT 5000 /* msecs */
#define DEFAULT_PAUSE_TIME 0x7FF
#define CGX_LMAC_FWI 0
enum cgx_nix_stat_type {
NIX_STATS_RX,
NIX_STATS_TX,
};
enum LMAC_TYPE {
LMAC_MODE_SGMII = 0,
LMAC_MODE_XAUI = 1,
LMAC_MODE_RXAUI = 2,
LMAC_MODE_10G_R = 3,
LMAC_MODE_40G_R = 4,
LMAC_MODE_QSGMII = 6,
LMAC_MODE_25G_R = 7,
LMAC_MODE_50G_R = 8,
LMAC_MODE_100G_R = 9,
LMAC_MODE_USXGMII = 10,
LMAC_MODE_USGMII = 11,
LMAC_MODE_MAX,
};
struct cgx_link_event {
struct cgx_link_user_info link_uinfo;
u8 cgx_id;
u8 lmac_id;
};
/**
* struct cgx_event_cb
* @notify_link_chg: callback for link change notification
* @data: data passed to callback function
*/
struct cgx_event_cb {
int (*notify_link_chg)(struct cgx_link_event *event, void *data);
void *data;
};
extern struct pci_driver cgx_driver;
int cgx_get_cgxcnt_max(void);
int cgx_get_cgxid(void *cgxd);
int cgx_get_lmac_cnt(void *cgxd);
void *cgx_get_pdata(int cgx_id);
int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
int cgx_get_pkind(void *cgxd, u8 lmac_id, int *pkind);
int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
int cgx_stats_reset(void *cgxd, int lmac_id);
int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
int cgx_get_link_info(void *cgxd, int lmac_id,
struct cgx_link_user_info *linfo);
int cgx_lmac_linkup_start(void *cgxd);
int cgx_get_fwdata_base(u64 *base);
void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
struct cgx_lmac_fwdata_s *linkmodes,
int cgx_id, int lmac_id);
u64 cgx_features_get(void *cgxd);
struct mac_ops *get_mac_ops(void *cgxd);
int cgx_get_nr_lmacs(void *cgxd);
u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
unsigned long cgx_get_lmac_bmap(void *cgxd);
void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
u64 cgx_read_dmac_entry(void *cgxd, int index);
int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
u16 pfc_en);
int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
u8 *rx_pause);
int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
int pfvf_idx);
int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr);
u32 cgx_get_fifo_len(void *cgxd);
#endif /* CGX_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
+295
View File
@@ -0,0 +1,295 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell OcteonTx2 CGX driver
*
* Copyright (C) 2018 Marvell.
*
*/
#ifndef __CGX_FW_INTF_H__
#define __CGX_FW_INTF_H__
#include <linux/bitops.h>
#include <linux/bitfield.h>
#define CGX_FIRMWARE_MAJOR_VER 1
#define CGX_FIRMWARE_MINOR_VER 0
#define CGX_EVENT_ACK 1UL
/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
enum cgx_error_type {
CGX_ERR_NONE,
CGX_ERR_LMAC_NOT_ENABLED,
CGX_ERR_LMAC_MODE_INVALID,
CGX_ERR_REQUEST_ID_INVALID,
CGX_ERR_PREV_ACK_NOT_CLEAR,
CGX_ERR_PHY_LINK_DOWN,
CGX_ERR_PCS_RESET_FAIL,
CGX_ERR_AN_CPT_FAIL,
CGX_ERR_TX_NOT_IDLE,
CGX_ERR_RX_NOT_IDLE,
CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
CGX_ERR_SPUX_RX_ALIGN_FAIL,
CGX_ERR_SPUX_TX_FAULT,
CGX_ERR_SPUX_RX_FAULT,
CGX_ERR_SPUX_RESET_FAIL,
CGX_ERR_SPUX_AN_RESET_FAIL,
CGX_ERR_SPUX_USX_AN_RESET_FAIL,
CGX_ERR_SMUX_RX_LINK_NOT_OK,
CGX_ERR_PCS_RECV_LINK_FAIL,
CGX_ERR_TRAINING_FAIL,
CGX_ERR_RX_EQU_FAIL,
CGX_ERR_SPUX_BER_FAIL,
CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
CGX_ERR_SPUX_MARKER_LOCK_FAIL,
CGX_ERR_SET_FEC_INVALID,
CGX_ERR_SET_FEC_FAIL,
CGX_ERR_MODULE_INVALID,
CGX_ERR_MODULE_NOT_PRESENT,
CGX_ERR_SPEED_CHANGE_INVALID,
};
/* LINK speed types */
enum cgx_link_speed {
CGX_LINK_NONE,
CGX_LINK_10M,
CGX_LINK_100M,
CGX_LINK_1G,
CGX_LINK_2HG,
CGX_LINK_5G,
CGX_LINK_10G,
CGX_LINK_20G,
CGX_LINK_25G,
CGX_LINK_40G,
CGX_LINK_50G,
CGX_LINK_80G,
CGX_LINK_100G,
CGX_LINK_SPEED_MAX,
};
enum CGX_MODE_ {
CGX_MODE_SGMII,
CGX_MODE_1000_BASEX,
CGX_MODE_QSGMII,
CGX_MODE_10G_C2C,
CGX_MODE_10G_C2M,
CGX_MODE_10G_KR,
CGX_MODE_20G_C2C,
CGX_MODE_25G_C2C,
CGX_MODE_25G_C2M,
CGX_MODE_25G_2_C2C,
CGX_MODE_25G_CR,
CGX_MODE_25G_KR,
CGX_MODE_40G_C2C,
CGX_MODE_40G_C2M,
CGX_MODE_40G_CR4,
CGX_MODE_40G_KR4,
CGX_MODE_40GAUI_C2C,
CGX_MODE_50G_C2C,
CGX_MODE_50G_C2M,
CGX_MODE_50G_4_C2C,
CGX_MODE_50G_CR,
CGX_MODE_50G_KR,
CGX_MODE_80GAUI_C2C,
CGX_MODE_100G_C2C,
CGX_MODE_100G_C2M,
CGX_MODE_100G_CR4,
CGX_MODE_100G_KR4,
CGX_MODE_LAUI_2_C2C_BIT,
CGX_MODE_LAUI_2_C2M_BIT,
CGX_MODE_50GBASE_CR2_C_BIT,
CGX_MODE_50GBASE_KR2_C_BIT, /* = 30 */
CGX_MODE_100GAUI_2_C2C_BIT,
CGX_MODE_100GAUI_2_C2M_BIT,
CGX_MODE_100GBASE_CR2_BIT,
CGX_MODE_100GBASE_KR2_BIT,
CGX_MODE_SFI_1G_BIT,
CGX_MODE_25GBASE_CR_C_BIT,
CGX_MODE_25GBASE_KR_C_BIT,
CGX_MODE_SGMII_10M_BIT,
CGX_MODE_SGMII_100M_BIT, /* = 39 */
CGX_MODE_2500_BASEX_BIT = 42, /* Mode group 1 */
CGX_MODE_5000_BASEX_BIT,
CGX_MODE_O_USGMII_BIT,
CGX_MODE_Q_USGMII_BIT,
CGX_MODE_2_5G_USXGMII_BIT,
CGX_MODE_5G_USXGMII_BIT,
CGX_MODE_10G_SXGMII_BIT,
CGX_MODE_10G_DXGMII_BIT,
CGX_MODE_10G_QXGMII_BIT,
CGX_MODE_TP_BIT,
CGX_MODE_FIBER_BIT,
CGX_MODE_MAX /* = 53 */
};
/* REQUEST ID types. Input to firmware */
enum cgx_cmd_id {
CGX_CMD_NONE,
CGX_CMD_GET_FW_VER,
CGX_CMD_GET_MAC_ADDR,
CGX_CMD_SET_MTU,
CGX_CMD_GET_LINK_STS, /* optional to user */
CGX_CMD_LINK_BRING_UP,
CGX_CMD_LINK_BRING_DOWN,
CGX_CMD_INTERNAL_LBK,
CGX_CMD_EXTERNAL_LBK,
CGX_CMD_HIGIG,
CGX_CMD_LINK_STAT_CHANGE,
CGX_CMD_MODE_CHANGE, /* hot plug support */
CGX_CMD_INTF_SHUTDOWN,
CGX_CMD_GET_MKEX_PRFL_SIZE,
CGX_CMD_GET_MKEX_PRFL_ADDR,
CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */
CGX_CMD_GET_LINK_MODES, /* Supported Link Modes */
CGX_CMD_SET_LINK_MODE,
CGX_CMD_GET_SUPPORTED_FEC,
CGX_CMD_SET_FEC,
CGX_CMD_GET_AN,
CGX_CMD_SET_AN,
CGX_CMD_GET_ADV_LINK_MODES,
CGX_CMD_GET_ADV_FEC,
CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
CGX_CMD_SET_PHY_MOD_TYPE,
CGX_CMD_PRBS,
CGX_CMD_DISPLAY_EYE,
CGX_CMD_GET_PHY_FEC_STATS,
};
/* async event ids */
enum cgx_evt_id {
CGX_EVT_NONE,
CGX_EVT_LINK_CHANGE,
};
/* event types - cause of interrupt */
enum cgx_evt_type {
CGX_EVT_ASYNC,
CGX_EVT_CMD_RESP
};
enum cgx_stat {
CGX_STAT_SUCCESS,
CGX_STAT_FAIL
};
enum cgx_cmd_own {
CGX_CMD_OWN_NS,
CGX_CMD_OWN_FIRMWARE,
};
/* m - bit mask
* y - value to be written in the bitrange
* x - input value whose bitrange to be modified
*/
#define FIELD_SET(m, y, x) \
(((x) & ~(m)) | \
FIELD_PREP((m), (y)))
/* scratchx(0) CSR used for ATF->non-secure SW communication.
* This acts as the status register
* Provides details on command ack/status, command response, error details
*/
#define EVTREG_ACK BIT_ULL(0)
#define EVTREG_EVT_TYPE BIT_ULL(1)
#define EVTREG_STAT BIT_ULL(2)
#define EVTREG_ID GENMASK_ULL(8, 3)
/* Response to command IDs with command status as CGX_STAT_FAIL
*
* Not applicable for commands :
* CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
*/
#define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
/* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
* CGX_STAT_SUCCESS
*/
#define RESP_MAJOR_VER GENMASK_ULL(12, 9)
#define RESP_MINOR_VER GENMASK_ULL(16, 13)
/* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
* CGX_STAT_SUCCESS
*/
#define RESP_MAC_ADDR GENMASK_ULL(56, 9)
/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as
* CGX_STAT_SUCCESS
*/
#define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as
* CGX_STAT_SUCCESS
*/
#define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
/* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as
* CGX_STAT_SUCCESS
*/
#define RESP_FWD_BASE GENMASK_ULL(56, 9)
#define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
* status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
*
* In case of CGX_STAT_FAIL, it indicates CGX configuration failed
* when processing link up/down/change command.
* Both err_type and current link status will be updated
*
* In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
* link status will be updated
*/
struct cgx_lnk_sts {
uint64_t reserved1:9;
uint64_t link_up:1;
uint64_t full_duplex:1;
uint64_t speed:4; /* cgx_link_speed */
uint64_t err_type:10;
uint64_t an:1; /* AN supported or not */
uint64_t fec:2; /* FEC type if enabled, if not 0 */
uint64_t port:8;
uint64_t reserved2:28;
};
#define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
#define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10)
#define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11)
#define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15)
#define RESP_LINKSTAT_AN GENMASK_ULL(25, 25)
#define RESP_LINKSTAT_FEC GENMASK_ULL(27, 26)
#define RESP_LINKSTAT_PORT GENMASK_ULL(35, 28)
/* scratchx(1) CSR used for non-secure SW->ATF communication
* This CSR acts as a command register
*/
#define CMDREG_OWN BIT_ULL(0)
#define CMDREG_ID GENMASK_ULL(7, 2)
/* Any command using enable/disable as an argument need
* to set this bitfield.
* Ex: Loopback, HiGig...
*/
#define CMDREG_ENABLE BIT_ULL(8)
/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
#define CMDMTU_SIZE GENMASK_ULL(23, 8)
/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
#define CMDLINKCHANGE_LINKUP BIT_ULL(8)
#define CMDLINKCHANGE_FULLDPLX BIT_ULL(9)
#define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)
#define CMDSETFEC GENMASK_ULL(9, 8)
/* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
#define CMDMODECHANGE_SPEED GENMASK_ULL(11, 8)
#define CMDMODECHANGE_DUPLEX GENMASK_ULL(12, 12)
#define CMDMODECHANGE_AN GENMASK_ULL(13, 13)
/* this field categorize the mode ID(FLAGS) range to accommodate
* more modes.
* To specify mode ID range of 0 - 41, this field will be 0.
* To specify mode ID range of 42 - 83, this field will be 1.
*/
#define CMDMODECHANGE_MODE_BASEIDX GENMASK_ULL(21, 20)
#define CMDMODECHANGE_FLAGS GENMASK_ULL(63, 22)
/* LINK_BRING_UP command timeout */
#define LINKCFG_TIMEOUT GENMASK_ULL(21, 8)
#endif /* __CGX_FW_INTF_H__ */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h
+32
View File
@@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#ifndef CN20K_API_H
#define CN20K_API_H
#include "../rvu.h"
struct ng_rvu {
struct mbox_ops *rvu_mbox_ops;
struct qmem *pf_mbox_addr;
struct qmem *vf_mbox_addr;
};
/* Mbox related APIs */
int cn20k_rvu_mbox_init(struct rvu *rvu, int type, int num);
int cn20k_rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
int num, int type, unsigned long *pf_bmap);
void cn20k_free_mbox_memory(struct rvu *rvu);
int cn20k_register_afpf_mbox_intr(struct rvu *rvu);
int cn20k_register_afvf_mbox_intr(struct rvu *rvu, int pf_vec_start);
void cn20k_rvu_enable_mbox_intr(struct rvu *rvu);
void cn20k_rvu_unregister_interrupts(struct rvu *rvu);
int cn20k_mbox_setup(struct otx2_mbox *mbox, struct pci_dev *pdev,
void *reg_base, int direction, int ndevs);
void cn20k_rvu_enable_afvf_intr(struct rvu *rvu, int vfs);
void cn20k_rvu_disable_afvf_intr(struct rvu *rvu, int vfs);
#endif /* CN20K_API_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c
+627
View File
@@ -0,0 +1,627 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "struct.h"
#include "rvu.h"
#include "debugfs.h"
#include "cn20k/reg.h"
#include "cn20k/npc.h"
static int npc_mcam_layout_show(struct seq_file *s, void *unused)
{
int i, j, sbd, idx0, idx1, vidx0, vidx1;
struct npc_priv_t *npc_priv;
char buf0[32], buf1[32];
struct npc_subbank *sb;
unsigned int bw0, bw1;
bool v0, v1;
int pf1, pf2;
bool e0, e1;
void *map;
npc_priv = s->private;
sbd = npc_priv->subbank_depth;
for (i = npc_priv->num_subbanks - 1; i >= 0; i--) {
sb = &npc_priv->sb[i];
mutex_lock(&sb->lock);
if (sb->flags & NPC_SUBBANK_FLAG_FREE)
goto next;
bw0 = bitmap_weight(sb->b0map, npc_priv->subbank_depth);
if (sb->key_type == NPC_MCAM_KEY_X4) {
seq_printf(s, "\n\nsubbank:%u, x4, free=%u, used=%u\n",
sb->idx, sb->free_cnt, bw0);
for (j = sbd - 1; j >= 0; j--) {
if (!test_bit(j, sb->b0map))
continue;
idx0 = sb->b0b + j;
map = xa_load(&npc_priv->xa_idx2pf_map, idx0);
pf1 = xa_to_value(map);
map = xa_load(&npc_priv->xa_idx2vidx_map, idx0);
if (map) {
vidx0 = xa_to_value(map);
snprintf(buf0, sizeof(buf0),
"v:%u", vidx0);
}
seq_printf(s, "\t%u(%#x)%c %s\n", idx0, pf1,
test_bit(idx0, npc_priv->en_map) ? '+' : ' ',
map ? buf0 : " ");
}
goto next;
}
bw1 = bitmap_weight(sb->b1map, npc_priv->subbank_depth);
seq_printf(s, "\n\nsubbank:%u, x2, free=%u, used=%u\n",
sb->idx, sb->free_cnt, bw0 + bw1);
seq_printf(s, "bank1(%u)\t\tbank0(%u)\n", bw1, bw0);
for (j = sbd - 1; j >= 0; j--) {
e0 = test_bit(j, sb->b0map);
e1 = test_bit(j, sb->b1map);
if (!e1 && !e0)
continue;
if (e1 && e0) {
idx0 = sb->b0b + j;
map = xa_load(&npc_priv->xa_idx2pf_map, idx0);
pf1 = xa_to_value(map);
map = xa_load(&npc_priv->xa_idx2vidx_map, idx0);
v0 = !!map;
if (v0) {
vidx0 = xa_to_value(map);
snprintf(buf0, sizeof(buf0), "v:%05u",
vidx0);
}
idx1 = sb->b1b + j;
map = xa_load(&npc_priv->xa_idx2pf_map, idx1);
pf2 = xa_to_value(map);
map = xa_load(&npc_priv->xa_idx2vidx_map, idx1);
v1 = !!map;
if (v1) {
vidx1 = xa_to_value(map);
snprintf(buf1, sizeof(buf1), "v:%05u",
vidx1);
}
seq_printf(s, "%05u(%#x)%c %s\t\t%05u(%#x)%c %s\n",
idx1, pf2,
test_bit(idx1, npc_priv->en_map) ? '+' : ' ',
v1 ? buf1 : " ",
idx0, pf1,
test_bit(idx0, npc_priv->en_map) ? '+' : ' ',
v0 ? buf0 : " ");
continue;
}
if (e0) {
idx0 = sb->b0b + j;
map = xa_load(&npc_priv->xa_idx2pf_map, idx0);
pf1 = xa_to_value(map);
map = xa_load(&npc_priv->xa_idx2vidx_map, idx0);
if (map) {
vidx0 = xa_to_value(map);
snprintf(buf0, sizeof(buf0), "v:%05u",
vidx0);
}
seq_printf(s, "\t\t \t\t%05u(%#x)%c %s\n", idx0, pf1,
test_bit(idx0, npc_priv->en_map) ? '+' : ' ',
map ? buf0 : " ");
continue;
}
idx1 = sb->b1b + j;
map = xa_load(&npc_priv->xa_idx2pf_map, idx1);
pf1 = xa_to_value(map);
map = xa_load(&npc_priv->xa_idx2vidx_map, idx1);
if (map) {
vidx1 = xa_to_value(map);
snprintf(buf1, sizeof(buf1), "v:%05u", vidx1);
}
seq_printf(s, "%05u(%#x)%c %s\n", idx1, pf1,
test_bit(idx1, npc_priv->en_map) ? '+' : ' ',
map ? buf1 : " ");
}
next:
mutex_unlock(&sb->lock);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(npc_mcam_layout);
#define __OCTEONTX2_DEBUGFS_ATTRIBUTE_FOPS(__name) \
static const struct file_operations __name ## _fops = { \
.owner = THIS_MODULE, \
.open = __name ## _open, \
.read = seq_read, \
.llseek = seq_lseek, \
.release = single_release, \
}
#define DEFINE_OCTEONTX2_DEBUGFS_ATTRIBUTE_WITH_SIZE(__name, __size) \
static int __name ## _open(struct inode *inode, struct file *file) \
{ \
return single_open_size(file, __name ## _show, inode->i_private, \
__size); \
} \
__OCTEONTX2_DEBUGFS_ATTRIBUTE_FOPS(__name)
static DEFINE_MUTEX(stats_lock);
/* MAX_NUM_BANKS, MAX_SUBBANK_DEPTH and MAX_NUM_SUB_BANKS represent
* hard limit on all silicon variants, preventing any possibility of
* out-of-bounds access.
*/
static u64 (*dstats)[MAX_NUM_BANKS][MAX_SUBBANK_DEPTH * MAX_NUM_SUB_BANKS];
static int npc_mcam_dstats_show(struct seq_file *s, void *unused)
{
struct npc_priv_t *npc_priv;
int blkaddr, pf, mcam_idx;
u64 stats, delta;
struct rvu *rvu;
char buff[64];
u8 key_type;
void *map;
npc_priv = npc_priv_get();
rvu = s->private;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
if (blkaddr < 0)
return 0;
mutex_lock(&stats_lock);
seq_puts(s, "idx\tpfunc\tstats\n");
for (int bank = npc_priv->num_banks - 1; bank >= 0; bank--) {
for (int idx = npc_priv->bank_depth - 1; idx >= 0; idx--) {
mcam_idx = bank * npc_priv->bank_depth + idx;
if (npc_mcam_idx_2_key_type(rvu, mcam_idx, &key_type))
continue;
if (key_type == NPC_MCAM_KEY_X4 && bank != 0)
continue;
if (!test_bit(mcam_idx, npc_priv->en_map))
continue;
stats = rvu_read64(rvu, blkaddr,
NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(idx, bank));
if (!stats)
continue;
if (stats == dstats[0][bank][idx])
continue;
if (stats < dstats[0][bank][idx])
dstats[0][bank][idx] = 0;
pf = 0xFFFF;
map = xa_load(&npc_priv->xa_idx2pf_map, mcam_idx);
if (map)
pf = xa_to_value(map);
delta = stats - dstats[0][bank][idx];
snprintf(buff, sizeof(buff), "%u\t%#04x\t%llu\n",
mcam_idx, pf, delta);
seq_puts(s, buff);
dstats[0][bank][idx] = stats;
}
}
mutex_unlock(&stats_lock);
return 0;
}
/* "%u\t%#04x\t%llu\n" needs less than 64 characters to print */
#define TOTAL_SZ (MAX_NUM_BANKS * MAX_NUM_SUB_BANKS * MAX_SUBBANK_DEPTH * 64)
DEFINE_OCTEONTX2_DEBUGFS_ATTRIBUTE_WITH_SIZE(npc_mcam_dstats, TOTAL_SZ);
static int npc_mcam_mismatch_show(struct seq_file *s, void *unused)
{
struct npc_priv_t *npc_priv;
struct npc_subbank *sb;
int mcam_idx, sb_off;
struct rvu *rvu;
char buff[64];
void *map;
int rc;
npc_priv = npc_priv_get();
rvu = s->private;
seq_puts(s, "index\tsb idx\tkw type\n");
for (int bank = npc_priv->num_banks - 1; bank >= 0; bank--) {
for (int idx = npc_priv->bank_depth - 1; idx >= 0; idx--) {
mcam_idx = bank * npc_priv->bank_depth + idx;
if (!test_bit(mcam_idx, npc_priv->en_map))
continue;
map = xa_load(&npc_priv->xa_idx2pf_map, mcam_idx);
if (map)
continue;
rc = npc_mcam_idx_2_subbank_idx(rvu, mcam_idx,
&sb, &sb_off);
if (rc)
continue;
snprintf(buff, sizeof(buff), "%u\t%d\t%u\n",
mcam_idx, sb->idx, sb->key_type);
seq_puts(s, buff);
}
}
return 0;
}
/* "%u\t%d\t%u\n" needs less than 64 characters to print. */
DEFINE_OCTEONTX2_DEBUGFS_ATTRIBUTE_WITH_SIZE(npc_mcam_mismatch, TOTAL_SZ);
static int npc_mcam_default_show(struct seq_file *s, void *unused)
{
struct npc_priv_t *npc_priv;
unsigned long index;
u16 ptr[4], pcifunc;
struct rvu *rvu;
int rc, i;
void *map;
npc_priv = npc_priv_get();
rvu = s->private;
seq_puts(s, "\npcifunc\tBcast\tmcast\tpromisc\tucast\n");
xa_for_each(&npc_priv->xa_pf_map, index, map) {
pcifunc = index;
for (i = 0; i < ARRAY_SIZE(ptr); i++)
ptr[i] = USHRT_MAX;
rc = npc_cn20k_dft_rules_idx_get(rvu, pcifunc, &ptr[0],
&ptr[1], &ptr[2], &ptr[3]);
if (rc)
continue;
seq_printf(s, "%#x\t", pcifunc);
for (i = 0; i < ARRAY_SIZE(ptr); i++) {
if (ptr[i] != USHRT_MAX)
seq_printf(s, "%u\t", ptr[i]);
else
seq_puts(s, "\t");
}
seq_puts(s, "\n");
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(npc_mcam_default);
static int npc_vidx2idx_map_show(struct seq_file *s, void *unused)
{
struct npc_priv_t *npc_priv;
unsigned long index, start;
struct xarray *xa;
void *map;
npc_priv = s->private;
start = npc_priv->bank_depth * 2;
xa = &npc_priv->xa_vidx2idx_map;
seq_puts(s, "\nvidx\tmcam_idx\n");
xa_for_each_start(xa, index, map, start)
seq_printf(s, "%lu\t%lu\n", index, xa_to_value(map));
return 0;
}
DEFINE_SHOW_ATTRIBUTE(npc_vidx2idx_map);
static int npc_idx2vidx_map_show(struct seq_file *s, void *unused)
{
struct npc_priv_t *npc_priv;
unsigned long index;
struct xarray *xa;
void *map;
npc_priv = s->private;
xa = &npc_priv->xa_idx2vidx_map;
seq_puts(s, "\nmidx\tvidx\n");
xa_for_each(xa, index, map)
seq_printf(s, "%lu\t%lu\n", index, xa_to_value(map));
return 0;
}
DEFINE_SHOW_ATTRIBUTE(npc_idx2vidx_map);
static int npc_defrag_show(struct seq_file *s, void *unused)
{
struct npc_defrag_show_node *node;
struct npc_priv_t *npc_priv;
u16 sbd, bdm;
npc_priv = s->private;
bdm = npc_priv->bank_depth - 1;
sbd = npc_priv->subbank_depth;
seq_puts(s, "\nold(sb) -> new(sb)\t\tvidx\n");
mutex_lock(&npc_priv->lock);
list_for_each_entry(node, &npc_priv->defrag_lh, list)
seq_printf(s, "%u(%u)\t%u(%u)\t%u\n", node->old_midx,
(node->old_midx & bdm) / sbd,
node->new_midx,
(node->new_midx & bdm) / sbd,
node->vidx);
mutex_unlock(&npc_priv->lock);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(npc_defrag);
int npc_cn20k_debugfs_init(struct rvu *rvu)
{
struct npc_priv_t *npc_priv = npc_priv_get();
debugfs_create_file("mcam_layout", 0444, rvu->rvu_dbg.npc,
npc_priv, &npc_mcam_layout_fops);
debugfs_create_file("mcam_default", 0444, rvu->rvu_dbg.npc,
rvu, &npc_mcam_default_fops);
debugfs_create_file("vidx2idx", 0444, rvu->rvu_dbg.npc,
npc_priv, &npc_vidx2idx_map_fops);
dstats = devm_kzalloc(rvu->dev, sizeof(*dstats), GFP_KERNEL);
if (!dstats)
return -ENOMEM;
debugfs_create_file("dstats", 0444, rvu->rvu_dbg.npc, rvu,
&npc_mcam_dstats_fops);
debugfs_create_file("mismatch", 0444, rvu->rvu_dbg.npc, rvu,
&npc_mcam_mismatch_fops);
debugfs_create_file("idx2vidx", 0444, rvu->rvu_dbg.npc,
npc_priv, &npc_idx2vidx_map_fops);
debugfs_create_file("defrag", 0444, rvu->rvu_dbg.npc,
npc_priv, &npc_defrag_fops);
return 0;
}
void npc_cn20k_debugfs_deinit(struct rvu *rvu)
{
debugfs_remove_recursive(rvu->rvu_dbg.npc);
}
void print_nix_cn20k_sq_ctx(struct seq_file *m,
struct nix_cn20k_sq_ctx_s *sq_ctx)
{
seq_printf(m, "W0: ena \t\t\t%d\nW0: qint_idx \t\t\t%d\n",
sq_ctx->ena, sq_ctx->qint_idx);
seq_printf(m, "W0: substream \t\t\t0x%03x\nW0: sdp_mcast \t\t\t%d\n",
sq_ctx->substream, sq_ctx->sdp_mcast);
seq_printf(m, "W0: cq \t\t\t\t%d\nW0: sqe_way_mask \t\t%d\n\n",
sq_ctx->cq, sq_ctx->sqe_way_mask);
seq_printf(m, "W1: smq \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: xoff\t\t\t%d\n",
sq_ctx->smq, sq_ctx->cq_ena, sq_ctx->xoff);
seq_printf(m, "W1: sso_ena \t\t\t%d\nW1: smq_rr_weight\t\t%d\n",
sq_ctx->sso_ena, sq_ctx->smq_rr_weight);
seq_printf(m, "W1: default_chan\t\t%d\nW1: sqb_count\t\t\t%d\n\n",
sq_ctx->default_chan, sq_ctx->sqb_count);
seq_printf(m, "W1: smq_rr_count_lb \t\t%d\n", sq_ctx->smq_rr_count_lb);
seq_printf(m, "W2: smq_rr_count_ub \t\t%d\n", sq_ctx->smq_rr_count_ub);
seq_printf(m, "W2: sqb_aura \t\t\t%d\nW2: sq_int \t\t\t%d\n",
sq_ctx->sqb_aura, sq_ctx->sq_int);
seq_printf(m, "W2: sq_int_ena \t\t\t%d\nW2: sqe_stype \t\t\t%d\n",
sq_ctx->sq_int_ena, sq_ctx->sqe_stype);
seq_printf(m, "W3: max_sqe_size\t\t%d\nW3: cq_limit\t\t\t%d\n",
sq_ctx->max_sqe_size, sq_ctx->cq_limit);
seq_printf(m, "W3: lmt_dis \t\t\t%d\nW3: mnq_dis \t\t\t%d\n",
sq_ctx->lmt_dis, sq_ctx->mnq_dis);
seq_printf(m, "W3: smq_next_sq\t\t\t%d\nW3: smq_lso_segnum\t\t%d\n",
sq_ctx->smq_next_sq, sq_ctx->smq_lso_segnum);
seq_printf(m, "W3: tail_offset \t\t%d\nW3: smenq_offset\t\t%d\n",
sq_ctx->tail_offset, sq_ctx->smenq_offset);
seq_printf(m, "W3: head_offset\t\t\t%d\nW3: smenq_next_sqb_vld\t\t%d\n\n",
sq_ctx->head_offset, sq_ctx->smenq_next_sqb_vld);
seq_printf(m, "W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d\n",
sq_ctx->smq_next_sq_vld, sq_ctx->smq_pend);
seq_printf(m, "W4: next_sqb \t\t\t%llx\n\n", sq_ctx->next_sqb);
seq_printf(m, "W5: tail_sqb \t\t\t%llx\n\n", sq_ctx->tail_sqb);
seq_printf(m, "W6: smenq_sqb \t\t\t%llx\n\n", sq_ctx->smenq_sqb);
seq_printf(m, "W7: smenq_next_sqb \t\t%llx\n\n",
sq_ctx->smenq_next_sqb);
seq_printf(m, "W8: head_sqb\t\t\t%llx\n\n", sq_ctx->head_sqb);
seq_printf(m, "W9: vfi_lso_total\t\t%d\n", sq_ctx->vfi_lso_total);
seq_printf(m, "W9: vfi_lso_sizem1\t\t%d\nW9: vfi_lso_sb\t\t\t%d\n",
sq_ctx->vfi_lso_sizem1, sq_ctx->vfi_lso_sb);
seq_printf(m, "W9: vfi_lso_mps\t\t\t%d\nW9: vfi_lso_vlan0_ins_ena\t%d\n",
sq_ctx->vfi_lso_mps, sq_ctx->vfi_lso_vlan0_ins_ena);
seq_printf(m, "W9: vfi_lso_vlan1_ins_ena\t%d\nW9: vfi_lso_vld \t\t%d\n\n",
sq_ctx->vfi_lso_vld, sq_ctx->vfi_lso_vlan1_ins_ena);
seq_printf(m, "W10: scm_lso_rem \t\t%llu\n\n",
(u64)sq_ctx->scm_lso_rem);
seq_printf(m, "W11: octs \t\t\t%llu\n\n", (u64)sq_ctx->octs);
seq_printf(m, "W12: pkts \t\t\t%llu\n\n", (u64)sq_ctx->pkts);
seq_printf(m, "W13: aged_drop_octs \t\t\t%llu\n\n",
(u64)sq_ctx->aged_drop_octs);
seq_printf(m, "W13: aged_drop_pkts \t\t\t%llu\n\n",
(u64)sq_ctx->aged_drop_pkts);
seq_printf(m, "W14: dropped_octs \t\t%llu\n\n",
(u64)sq_ctx->dropped_octs);
seq_printf(m, "W15: dropped_pkts \t\t%llu\n\n",
(u64)sq_ctx->dropped_pkts);
}
void print_nix_cn20k_cq_ctx(struct seq_file *m,
struct nix_cn20k_aq_enq_rsp *rsp)
{
struct nix_cn20k_cq_ctx_s *cq_ctx = &rsp->cq;
seq_printf(m, "W0: base \t\t\t%llx\n\n", cq_ctx->base);
seq_printf(m, "W1: wrptr \t\t\t%llx\n", (u64)cq_ctx->wrptr);
seq_printf(m, "W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d\n",
cq_ctx->avg_con, cq_ctx->cint_idx);
seq_printf(m, "W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d\n",
cq_ctx->cq_err, cq_ctx->qint_idx);
seq_printf(m, "W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n\n",
cq_ctx->bpid, cq_ctx->bp_ena);
seq_printf(m, "W1: lbpid_high \t\t\t0x%03x\n", cq_ctx->lbpid_high);
seq_printf(m, "W1: lbpid_med \t\t\t0x%03x\n", cq_ctx->lbpid_med);
seq_printf(m, "W1: lbpid_low \t\t\t0x%03x\n", cq_ctx->lbpid_low);
seq_printf(m, "(W1: lbpid) \t\t\t0x%03x\n",
cq_ctx->lbpid_high << 6 | cq_ctx->lbpid_med << 3 |
cq_ctx->lbpid_low);
seq_printf(m, "W1: lbp_ena \t\t\t\t%d\n\n", cq_ctx->lbp_ena);
seq_printf(m, "W2: update_time \t\t%d\nW2:avg_level \t\t\t%d\n",
cq_ctx->update_time, cq_ctx->avg_level);
seq_printf(m, "W2: head \t\t\t%d\nW2:tail \t\t\t%d\n\n",
cq_ctx->head, cq_ctx->tail);
seq_printf(m, "W3: cq_err_int_ena \t\t%d\nW3:cq_err_int \t\t\t%d\n",
cq_ctx->cq_err_int_ena, cq_ctx->cq_err_int);
seq_printf(m, "W3: qsize \t\t\t%d\nW3:stashing \t\t\t%d\n",
cq_ctx->qsize, cq_ctx->stashing);
seq_printf(m, "W3: caching \t\t\t%d\n", cq_ctx->caching);
seq_printf(m, "W3: lbp_frac \t\t\t%d\n", cq_ctx->lbp_frac);
seq_printf(m, "W3: stash_thresh \t\t\t%d\n",
cq_ctx->stash_thresh);
seq_printf(m, "W3: msh_valid \t\t\t%d\nW3:msh_dst \t\t\t%d\n",
cq_ctx->msh_valid, cq_ctx->msh_dst);
seq_printf(m, "W3: cpt_drop_err_en \t\t\t%d\n",
cq_ctx->cpt_drop_err_en);
seq_printf(m, "W3: ena \t\t\t%d\n",
cq_ctx->ena);
seq_printf(m, "W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d\n",
cq_ctx->drop_ena, cq_ctx->drop);
seq_printf(m, "W3: bp \t\t\t\t%d\n\n", cq_ctx->bp);
seq_printf(m, "W4: lbpid_ext \t\t\t\t%d\n\n", cq_ctx->lbpid_ext);
seq_printf(m, "W4: bpid_ext \t\t\t\t%d\n\n", cq_ctx->bpid_ext);
}
void print_npa_cn20k_aura_ctx(struct seq_file *m,
struct npa_cn20k_aq_enq_rsp *rsp)
{
struct npa_cn20k_aura_s *aura = &rsp->aura;
seq_printf(m, "W0: Pool addr\t\t%llx\n", aura->pool_addr);
seq_printf(m, "W1: ena\t\t\t%d\nW1: pool caching\t%d\n",
aura->ena, aura->pool_caching);
seq_printf(m, "W1: avg con\t\t%d\n", aura->avg_con);
seq_printf(m, "W1: pool drop ena\t%d\nW1: aura drop ena\t%d\n",
aura->pool_drop_ena, aura->aura_drop_ena);
seq_printf(m, "W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\n",
aura->bp_ena, aura->aura_drop);
seq_printf(m, "W1: aura shift\t\t%d\nW1: avg_level\t\t%d\n",
aura->shift, aura->avg_level);
seq_printf(m, "W2: count\t\t%llu\nW2: nix_bpid\t\t%d\n",
(u64)aura->count, aura->bpid);
seq_printf(m, "W3: limit\t\t%llu\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n",
(u64)aura->limit, aura->bp, aura->fc_ena);
seq_printf(m, "W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d\n",
aura->fc_up_crossing, aura->fc_stype);
seq_printf(m, "W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits);
seq_printf(m, "W4: fc_addr\t\t%llx\n", aura->fc_addr);
seq_printf(m, "W5: pool_drop\t\t%d\nW5: update_time\t\t%d\n",
aura->pool_drop, aura->update_time);
seq_printf(m, "W5: err_int \t\t%d\nW5: err_int_ena\t\t%d\n",
aura->err_int, aura->err_int_ena);
seq_printf(m, "W5: thresh_int\t\t%d\nW5: thresh_int_ena \t%d\n",
aura->thresh_int, aura->thresh_int_ena);
seq_printf(m, "W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d\n",
aura->thresh_up, aura->thresh_qint_idx);
seq_printf(m, "W5: err_qint_idx \t%d\n", aura->err_qint_idx);
seq_printf(m, "W6: thresh\t\t%llu\n", (u64)aura->thresh);
seq_printf(m, "W6: fc_msh_dst\t\t%d\n", aura->fc_msh_dst);
}
void print_npa_cn20k_pool_ctx(struct seq_file *m,
struct npa_cn20k_aq_enq_rsp *rsp)
{
struct npa_cn20k_pool_s *pool = &rsp->pool;
seq_printf(m, "W0: Stack base\t\t%llx\n", pool->stack_base);
seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n",
pool->ena, pool->nat_align);
seq_printf(m, "W1: stack_caching\t%d\n",
pool->stack_caching);
seq_printf(m, "W1: buf_offset\t\t%d\nW1: buf_size\t\t%d\n",
pool->buf_offset, pool->buf_size);
seq_printf(m, "W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n",
pool->stack_max_pages, pool->stack_pages);
seq_printf(m, "W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d\n",
pool->stack_offset, pool->shift, pool->avg_level);
seq_printf(m, "W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d\n",
pool->avg_con, pool->fc_ena, pool->fc_stype);
seq_printf(m, "W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d\n",
pool->fc_hyst_bits, pool->fc_up_crossing);
seq_printf(m, "W4: update_time\t\t%d\n", pool->update_time);
seq_printf(m, "W5: fc_addr\t\t%llx\n", pool->fc_addr);
seq_printf(m, "W6: ptr_start\t\t%llx\n", pool->ptr_start);
seq_printf(m, "W7: ptr_end\t\t%llx\n", pool->ptr_end);
seq_printf(m, "W8: err_int\t\t%d\nW8: err_int_ena\t\t%d\n",
pool->err_int, pool->err_int_ena);
seq_printf(m, "W8: thresh_int\t\t%d\n", pool->thresh_int);
seq_printf(m, "W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d\n",
pool->thresh_int_ena, pool->thresh_up);
seq_printf(m, "W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n",
pool->thresh_qint_idx, pool->err_qint_idx);
seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst);
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h
+31
View File
@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell OcteonTx2 CGX driver
*
* Copyright (C) 2024 Marvell.
*
*/
#ifndef DEBUFS_H
#define DEBUFS_H
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "struct.h"
#include "../mbox.h"
int npc_cn20k_debugfs_init(struct rvu *rvu);
void npc_cn20k_debugfs_deinit(struct rvu *rvu);
void print_nix_cn20k_sq_ctx(struct seq_file *m,
struct nix_cn20k_sq_ctx_s *sq_ctx);
void print_nix_cn20k_cq_ctx(struct seq_file *m,
struct nix_cn20k_aq_enq_rsp *rsp);
void print_npa_cn20k_aura_ctx(struct seq_file *m,
struct npa_cn20k_aq_enq_rsp *rsp);
void print_npa_cn20k_pool_ctx(struct seq_file *m,
struct npa_cn20k_aq_enq_rsp *rsp);
#endif
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
+441
View File
@@ -0,0 +1,441 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include "rvu_trace.h"
#include "mbox.h"
#include "reg.h"
#include "api.h"
static irqreturn_t cn20k_afvf_mbox_intr_handler(int irq, void *rvu_irq)
{
struct rvu_irq_data *rvu_irq_data = rvu_irq;
struct rvu *rvu = rvu_irq_data->rvu;
u64 intr;
/* Sync with mbox memory region */
rmb();
/* Clear interrupts */
intr = rvupf_read64(rvu, rvu_irq_data->intr_status);
rvupf_write64(rvu, rvu_irq_data->intr_status, intr);
if (intr)
trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
rvu_irq_data->afvf_queue_work_hdlr(&rvu->afvf_wq_info, rvu_irq_data->start,
rvu_irq_data->mdevs, intr);
return IRQ_HANDLED;
}
int cn20k_register_afvf_mbox_intr(struct rvu *rvu, int pf_vec_start)
{
struct rvu_irq_data *irq_data;
int intr_vec, offset, vec = 0;
int err;
/* irq data for 4 VFPF intr vectors */
irq_data = devm_kcalloc(rvu->dev, 4,
sizeof(struct rvu_irq_data), GFP_KERNEL);
if (!irq_data)
return -ENOMEM;
for (intr_vec = RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=
RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1;
intr_vec++, vec++) {
switch (intr_vec) {
case RVU_MBOX_PF_INT_VEC_VFPF_MBOX0:
irq_data[vec].intr_status =
RVU_MBOX_PF_VFPF_INTX(0);
irq_data[vec].start = 0;
irq_data[vec].mdevs = 64;
break;
case RVU_MBOX_PF_INT_VEC_VFPF_MBOX1:
irq_data[vec].intr_status =
RVU_MBOX_PF_VFPF_INTX(1);
irq_data[vec].start = 64;
irq_data[vec].mdevs = 64;
break;
case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0:
irq_data[vec].intr_status =
RVU_MBOX_PF_VFPF1_INTX(0);
irq_data[vec].start = 0;
irq_data[vec].mdevs = 64;
break;
case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1:
irq_data[vec].intr_status = RVU_MBOX_PF_VFPF1_INTX(1);
irq_data[vec].start = 64;
irq_data[vec].mdevs = 64;
break;
}
irq_data[vec].afvf_queue_work_hdlr =
rvu_queue_work;
offset = pf_vec_start + intr_vec;
irq_data[vec].vec_num = offset;
irq_data[vec].rvu = rvu;
sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAF VFAF%d Mbox%d",
vec / 2, vec % 2);
err = request_irq(pci_irq_vector(rvu->pdev, offset),
rvu->ng_rvu->rvu_mbox_ops->afvf_intr_handler, 0,
&rvu->irq_name[offset * NAME_SIZE],
&irq_data[vec]);
if (err) {
dev_err(rvu->dev,
"RVUAF: IRQ registration failed for AFVF mbox irq\n");
return err;
}
rvu->irq_allocated[offset] = true;
}
return 0;
}
/* CN20K mbox PFx => AF irq handler */
static irqreturn_t cn20k_mbox_pf_common_intr_handler(int irq, void *rvu_irq)
{
struct rvu_irq_data *rvu_irq_data = rvu_irq;
struct rvu *rvu = rvu_irq_data->rvu;
u64 intr;
/* Clear interrupts */
intr = rvu_read64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status);
rvu_write64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status, intr);
if (intr)
trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
/* Sync with mbox memory region */
rmb();
rvu_irq_data->rvu_queue_work_hdlr(&rvu->afpf_wq_info,
rvu_irq_data->start,
rvu_irq_data->mdevs, intr);
return IRQ_HANDLED;
}
void cn20k_rvu_enable_mbox_intr(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
/* Clear spurious irqs, if any */
rvu_write64(rvu, BLKADDR_RVUM,
RVU_MBOX_AF_PFAF_INT(0), INTR_MASK(hw->total_pfs));
rvu_write64(rvu, BLKADDR_RVUM,
RVU_MBOX_AF_PFAF_INT(1), INTR_MASK(hw->total_pfs - 64));
rvu_write64(rvu, BLKADDR_RVUM,
RVU_MBOX_AF_PFAF1_INT(0), INTR_MASK(hw->total_pfs));
rvu_write64(rvu, BLKADDR_RVUM,
RVU_MBOX_AF_PFAF1_INT(1), INTR_MASK(hw->total_pfs - 64));
/* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1S(0),
INTR_MASK(hw->total_pfs) & ~1ULL);
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1S(1),
INTR_MASK(hw->total_pfs - 64));
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1S(0),
INTR_MASK(hw->total_pfs) & ~1ULL);
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1S(1),
INTR_MASK(hw->total_pfs - 64));
}
void cn20k_rvu_unregister_interrupts(struct rvu *rvu)
{
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1C(0),
INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1C(1),
INTR_MASK(rvu->hw->total_pfs - 64));
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1C(0),
INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1C(1),
INTR_MASK(rvu->hw->total_pfs - 64));
}
int cn20k_register_afpf_mbox_intr(struct rvu *rvu)
{
struct rvu_irq_data *irq_data;
int intr_vec, ret, vec = 0;
/* irq data for 4 PF intr vectors */
irq_data = devm_kcalloc(rvu->dev, 4,
sizeof(struct rvu_irq_data), GFP_KERNEL);
if (!irq_data)
return -ENOMEM;
for (intr_vec = RVU_AF_CN20K_INT_VEC_PFAF_MBOX0; intr_vec <=
RVU_AF_CN20K_INT_VEC_PFAF1_MBOX1; intr_vec++,
vec++) {
switch (intr_vec) {
case RVU_AF_CN20K_INT_VEC_PFAF_MBOX0:
irq_data[vec].intr_status =
RVU_MBOX_AF_PFAF_INT(0);
irq_data[vec].start = 0;
irq_data[vec].mdevs = 64;
break;
case RVU_AF_CN20K_INT_VEC_PFAF_MBOX1:
irq_data[vec].intr_status =
RVU_MBOX_AF_PFAF_INT(1);
irq_data[vec].start = 64;
irq_data[vec].mdevs = 96;
break;
case RVU_AF_CN20K_INT_VEC_PFAF1_MBOX0:
irq_data[vec].intr_status =
RVU_MBOX_AF_PFAF1_INT(0);
irq_data[vec].start = 0;
irq_data[vec].mdevs = 64;
break;
case RVU_AF_CN20K_INT_VEC_PFAF1_MBOX1:
irq_data[vec].intr_status =
RVU_MBOX_AF_PFAF1_INT(1);
irq_data[vec].start = 64;
irq_data[vec].mdevs = 96;
break;
}
irq_data[vec].rvu_queue_work_hdlr = rvu_queue_work;
irq_data[vec].vec_num = intr_vec;
irq_data[vec].rvu = rvu;
/* Register mailbox interrupt handler */
sprintf(&rvu->irq_name[intr_vec * NAME_SIZE],
"RVUAF PFAF%d Mbox%d",
vec / 2, vec % 2);
ret = request_irq(pci_irq_vector(rvu->pdev, intr_vec),
rvu->ng_rvu->rvu_mbox_ops->pf_intr_handler, 0,
&rvu->irq_name[intr_vec * NAME_SIZE],
&irq_data[vec]);
if (ret)
return ret;
rvu->irq_allocated[intr_vec] = true;
}
return 0;
}
int cn20k_rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
int num, int type, unsigned long *pf_bmap)
{
int region;
u64 bar;
if (type == TYPE_AFVF) {
for (region = 0; region < num; region++) {
if (!test_bit(region, pf_bmap))
continue;
bar = (u64)phys_to_virt((u64)rvu->ng_rvu->vf_mbox_addr->base);
bar += region * MBOX_SIZE;
mbox_addr[region] = (void *)bar;
if (!mbox_addr[region])
return -ENOMEM;
}
return 0;
}
for (region = 0; region < num; region++) {
if (!test_bit(region, pf_bmap))
continue;
bar = (u64)phys_to_virt((u64)rvu->ng_rvu->pf_mbox_addr->base);
bar += region * MBOX_SIZE;
mbox_addr[region] = (void *)bar;
if (!mbox_addr[region])
return -ENOMEM;
}
return 0;
}
static int rvu_alloc_mbox_memory(struct rvu *rvu, int type,
int ndevs, int mbox_size)
{
struct qmem *mbox_addr;
dma_addr_t iova;
int pf, err;
/* Allocate contiguous memory for mailbox communication.
* eg: AF <=> PFx mbox memory
* This allocated memory is split into chunks of MBOX_SIZE
* and setup into each of the RVU PFs. In HW this memory will
* get aliased to an offset within BAR2 of those PFs.
*
* AF will access mbox memory using direct physical addresses
* and PFs will access the same shared memory from BAR2.
*
* PF <=> VF mbox memory also works in the same fashion.
* AFPF, PFVF requires IOVA to be used to maintain the mailbox msgs
*/
err = qmem_alloc(rvu->dev, &mbox_addr, ndevs, mbox_size);
if (err)
return -ENOMEM;
switch (type) {
case TYPE_AFPF:
rvu->ng_rvu->pf_mbox_addr = mbox_addr;
iova = (u64)mbox_addr->iova;
for (pf = 0; pf < ndevs; pf++) {
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFX_ADDR(pf),
(u64)iova);
iova += mbox_size;
}
break;
case TYPE_AFVF:
rvu->ng_rvu->vf_mbox_addr = mbox_addr;
rvupf_write64(rvu, RVU_PF_VF_MBOX_ADDR, (u64)mbox_addr->iova);
break;
default:
return 0;
}
return 0;
}
static struct mbox_ops cn20k_mbox_ops = {
.pf_intr_handler = cn20k_mbox_pf_common_intr_handler,
.afvf_intr_handler = cn20k_afvf_mbox_intr_handler,
};
int cn20k_rvu_mbox_init(struct rvu *rvu, int type, int ndevs)
{
int dev;
if (!is_cn20k(rvu->pdev))
return 0;
rvu->ng_rvu->rvu_mbox_ops = &cn20k_mbox_ops;
if (type == TYPE_AFVF) {
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_PF_VF_CFG, ilog2(MBOX_SIZE));
} else {
for (dev = 0; dev < ndevs; dev++)
rvu_write64(rvu, BLKADDR_RVUM,
RVU_MBOX_AF_PFX_CFG(dev), ilog2(MBOX_SIZE));
}
return rvu_alloc_mbox_memory(rvu, type, ndevs, MBOX_SIZE);
}
void cn20k_free_mbox_memory(struct rvu *rvu)
{
if (!is_cn20k(rvu->pdev))
return;
qmem_free(rvu->dev, rvu->ng_rvu->pf_mbox_addr);
qmem_free(rvu->dev, rvu->ng_rvu->vf_mbox_addr);
}
void cn20k_rvu_disable_afvf_intr(struct rvu *rvu, int vfs)
{
rvupf_write64(rvu, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
if (vfs <= 64)
return;
rvupf_write64(rvu, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
}
void cn20k_rvu_enable_afvf_intr(struct rvu *rvu, int vfs)
{
/* Clear any pending interrupts and enable AF VF interrupts for
* the first 64 VFs.
*/
rvupf_write64(rvu, RVU_MBOX_PF_VFPF_INTX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF1_INTX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(0), INTR_MASK(vfs));
/* FLR */
rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
/* Same for remaining VFs, if any. */
if (vfs <= 64)
return;
rvupf_write64(rvu, RVU_MBOX_PF_VFPF_INTX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF1_INTX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
}
int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf,
int blkaddr, int nixlf)
{
int qints, hwctx_size, err;
u64 cfg, ctx_cfg;
if (is_rvu_otx2(rvu) || is_cn20k(rvu->pdev))
return 0;
/* sanity check */
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_NIXX_CFG(0) |
(RVU_AFPF << 16));
if (!cfg)
return 0;
ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3);
/* Alloc memory for CQINT's HW contexts */
cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
qints = (cfg >> 24) & 0xFFF;
hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF);
err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size);
if (err)
return -ENOMEM;
rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf),
(u64)pfvf->cq_ints_ctx->iova);
/* Alloc memory for QINT's HW contexts */
cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
qints = (cfg >> 12) & 0xFFF;
hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF);
err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size);
if (err)
return -ENOMEM;
rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf),
(u64)pfvf->nix_qints_ctx->iova);
rvu_write64(rvu, BLKADDR_NIX0, RVU_AF_BAR2_SEL, RVU_AF_BAR2_PFID);
rvu_write64(rvu, BLKADDR_NIX0,
AF_BAR2_ALIASX(0, NIX_GINT_INT_W1S), ALTAF_RDY);
/* wait for ack */
err = rvu_poll_reg(rvu, BLKADDR_NIX0,
AF_BAR2_ALIASX(0, NIX_GINT_INT), ALTAF_RDY, true);
if (err)
rvu->altaf_ready = false;
else
rvu->altaf_ready = true;
return 0;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/nix.c
+20
View File
@@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#include <linux/module.h>
#include <linux/pci.h>
#include "struct.h"
#include "../rvu.h"
int rvu_mbox_handler_nix_cn20k_aq_enq(struct rvu *rvu,
struct nix_cn20k_aq_enq_req *req,
struct nix_cn20k_aq_enq_rsp *rsp)
{
return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req,
(struct nix_aq_enq_rsp *)rsp);
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c
+21
View File
@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#include <linux/module.h>
#include <linux/pci.h>
#include "struct.h"
#include "../rvu.h"
int rvu_mbox_handler_npa_cn20k_aq_enq(struct rvu *rvu,
struct npa_cn20k_aq_enq_req *req,
struct npa_cn20k_aq_enq_rsp *rsp)
{
return rvu_npa_aq_enq_inst(rvu, (struct npa_aq_enq_req *)req,
(struct npa_aq_enq_rsp *)rsp);
}
EXPORT_SYMBOL(rvu_mbox_handler_npa_cn20k_aq_enq);
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c
+4867
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h
+352
View File
@@ -0,0 +1,352 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2026 Marvell.
*
*/
#ifndef NPC_CN20K_H
#define NPC_CN20K_H
#define MKEX_CN20K_SIGN 0x19bbfdbd160
/* MAX_NUM_BANKS, MAX_SUBBANK_DEPTH and MAX_NUM_SUB_BANKS represent
* hard limit on all silicon variants, preventing any possibility of
* out-of-bounds access on matrix defined using these values.
*/
#define MAX_NUM_BANKS 2
#define MAX_NUM_SUB_BANKS 32
#define MAX_SUBBANK_DEPTH 256
/* strtoull of "mkexprof" with base:36 */
#define MKEX_END_SIGN 0xdeadbeef
#define NPC_CN20K_BYTESM GENMASK_ULL(18, 16)
#define NPC_CN20K_PARSE_NIBBLE GENMASK_ULL(22, 0)
#define NPC_CN20K_TOTAL_NIBBLE 23
#define CN20K_SET_EXTR_LT(intf, extr, ltype, cfg) \
rvu_write64(rvu, BLKADDR_NPC, \
NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype), cfg)
#define CN20K_GET_KEX_CFG(intf) \
rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
#define CN20K_GET_EXTR_LID(intf, extr) \
rvu_read64(rvu, BLKADDR_NPC, \
NPC_AF_INTFX_EXTRACTORX_CFG(intf, extr))
#define CN20K_SET_EXTR_LT(intf, extr, ltype, cfg) \
rvu_write64(rvu, BLKADDR_NPC, \
NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype), cfg)
#define CN20K_GET_EXTR_LT(intf, extr, ltype) \
rvu_read64(rvu, BLKADDR_NPC, \
NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype))
/* NPC_PARSE_KEX_S nibble definitions for each field */
#define NPC_CN20K_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
#define NPC_CN20K_PARSE_NIBBLE_ERRLEV BIT_ULL(3)
#define NPC_CN20K_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
#define NPC_CN20K_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6)
#define NPC_CN20K_PARSE_NIBBLE_LA_FLAGS BIT_ULL(7)
#define NPC_CN20K_PARSE_NIBBLE_LA_LTYPE BIT_ULL(8)
#define NPC_CN20K_PARSE_NIBBLE_LB_FLAGS BIT_ULL(9)
#define NPC_CN20K_PARSE_NIBBLE_LB_LTYPE BIT_ULL(10)
#define NPC_CN20K_PARSE_NIBBLE_LC_FLAGS BIT_ULL(11)
#define NPC_CN20K_PARSE_NIBBLE_LC_LTYPE BIT_ULL(12)
#define NPC_CN20K_PARSE_NIBBLE_LD_FLAGS BIT_ULL(13)
#define NPC_CN20K_PARSE_NIBBLE_LD_LTYPE BIT_ULL(14)
#define NPC_CN20K_PARSE_NIBBLE_LE_FLAGS BIT_ULL(15)
#define NPC_CN20K_PARSE_NIBBLE_LE_LTYPE BIT_ULL(16)
#define NPC_CN20K_PARSE_NIBBLE_LF_FLAGS BIT_ULL(17)
#define NPC_CN20K_PARSE_NIBBLE_LF_LTYPE BIT_ULL(18)
#define NPC_CN20K_PARSE_NIBBLE_LG_FLAGS BIT_ULL(19)
#define NPC_CN20K_PARSE_NIBBLE_LG_LTYPE BIT_ULL(20)
#define NPC_CN20K_PARSE_NIBBLE_LH_FLAGS BIT_ULL(21)
#define NPC_CN20K_PARSE_NIBBLE_LH_LTYPE BIT_ULL(22)
/* Rx parse key extract nibble enable */
#define NPC_CN20K_PARSE_NIBBLE_INTF_RX (NPC_CN20K_PARSE_NIBBLE_CHAN | \
NPC_CN20K_PARSE_NIBBLE_L2L3_BCAST | \
NPC_CN20K_PARSE_NIBBLE_LA_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LB_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LC_FLAGS | \
NPC_CN20K_PARSE_NIBBLE_LC_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LD_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LE_LTYPE)
/* Tx parse key extract nibble enable */
#define NPC_CN20K_PARSE_NIBBLE_INTF_TX (NPC_CN20K_PARSE_NIBBLE_LA_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LB_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LC_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LD_LTYPE | \
NPC_CN20K_PARSE_NIBBLE_LE_LTYPE)
/**
* enum npc_subbank_flag - NPC subbank status
*
* subbank flag indicates whether the subbank is free
* or used.
*
* @NPC_SUBBANK_FLAG_UNINIT: Subbank is not initialized.
* @NPC_SUBBANK_FLAG_FREE: Subbank is free.
* @NPC_SUBBANK_FLAG_USED: Subbank is used.
*/
enum npc_subbank_flag {
NPC_SUBBANK_FLAG_UNINIT,
NPC_SUBBANK_FLAG_FREE = BIT(0),
NPC_SUBBANK_FLAG_USED = BIT(1),
};
/**
* enum npc_dft_rule_id - Default rule type
*
* Mcam default rule type.
*
* @NPC_DFT_RULE_START_ID: Not used
* @NPC_DFT_RULE_PROMISC_ID: promiscuous rule
* @NPC_DFT_RULE_MCAST_ID: multicast rule
* @NPC_DFT_RULE_BCAST_ID: broadcast rule
* @NPC_DFT_RULE_UCAST_ID: unicast rule
* @NPC_DFT_RULE_MAX_ID: Maximum index.
*/
enum npc_dft_rule_id {
NPC_DFT_RULE_START_ID = 1,
NPC_DFT_RULE_PROMISC_ID = NPC_DFT_RULE_START_ID,
NPC_DFT_RULE_MCAST_ID,
NPC_DFT_RULE_BCAST_ID,
NPC_DFT_RULE_UCAST_ID,
NPC_DFT_RULE_MAX_ID,
};
/**
* struct npc_subbank - Subbank fields.
* @b0b: Subbanks bottom index for bank0
* @b1b: Subbanks bottom index for bank1
* @b0t: Subbanks top index for bank0
* @b1t: Subbanks top index for bank1
* @flags: Subbank flags
* @lock: Mutex lock for flags and rsrc mofiication
* @b0map: Bitmap map for bank0 indexes
* @b1map: Bitmap map for bank1 indexes
* @idx: Subbank index
* @arr_idx: Index to the free array or used array
* @free_cnt: Number of free slots in the subbank.
* @key_type: X4 or X2 subbank.
*
* MCAM resource is divided horizontally into multiple subbanks and
* Resource allocation from each subbank is managed by this data
* structure.
*/
struct npc_subbank {
u16 b0t, b0b, b1t, b1b;
enum npc_subbank_flag flags;
struct mutex lock; /* Protect subbank resources */
DECLARE_BITMAP(b0map, MAX_SUBBANK_DEPTH);
DECLARE_BITMAP(b1map, MAX_SUBBANK_DEPTH);
u16 idx;
u16 arr_idx;
u16 free_cnt;
u8 key_type;
};
/**
* struct npc_defrag_show_node - Defragmentation show node
* @old_midx: Old mcam index.
* @new_midx: New mcam index.
* @vidx: Virtual index
* @list: Linked list of these nodes
*
* This structure holds information on last defragmentation
* executed on mcam resource.
*/
struct npc_defrag_show_node {
u16 old_midx;
u16 new_midx;
u16 vidx;
struct list_head list;
};
/**
* struct npc_priv_t - NPC private structure.
* @bank_depth: Total entries in each bank.
* @num_banks: Number of banks.
* @num_subbanks: Number of subbanks.
* @subbank_depth: Depth of subbank.
* @en_map: Enable/disable status.
* @kw: Kex configured key type.
* @sb: Subbank array.
* @xa_sb_used: Array of used subbanks.
* @xa_sb_free: Array of free subbanks.
* @xa_pf2idx_map: PF to mcam index map.
* @xa_idx2pf_map: Mcam index to PF map.
* @xa_pf_map: Pcifunc to index map.
* @pf_cnt: Number of PFs.
* @xa_pf2dfl_rmap: PF to default rule index map.
* @xa_idx2vidx_map: Mcam index to virtual index map.
* @xa_vidx2idx_map: virtual index to mcam index map.
* @defrag_lh: Defrag list head.
* @lock: Lock for defrag list
*
* This structure is populated during probing time by reading
* HW csr registers.
*/
struct npc_priv_t {
int bank_depth;
int num_banks;
int num_subbanks;
int subbank_depth;
DECLARE_BITMAP(en_map, MAX_NUM_BANKS *
MAX_NUM_SUB_BANKS *
MAX_SUBBANK_DEPTH);
u8 kw;
struct npc_subbank *sb;
struct xarray xa_sb_used;
struct xarray xa_sb_free;
struct xarray *xa_pf2idx_map;
struct xarray xa_idx2pf_map;
struct xarray xa_pf_map;
struct xarray xa_pf2dfl_rmap;
struct xarray xa_idx2vidx_map;
struct xarray xa_vidx2idx_map;
struct list_head defrag_lh;
struct mutex lock; /* protect defrag nodes */
int pf_cnt;
};
struct npc_kpm_action0 {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 rsvd_63_57 : 7;
u64 byp_count : 3;
u64 capture_ena : 1;
u64 parse_done : 1;
u64 next_state : 8;
u64 rsvd_43 : 1;
u64 capture_lid : 3;
u64 capture_ltype : 4;
u64 rsvd_32_35 : 4;
u64 capture_flags : 4;
u64 ptr_advance : 8;
u64 var_len_offset : 8;
u64 var_len_mask : 8;
u64 var_len_right : 1;
u64 var_len_shift : 3;
#else
u64 var_len_shift : 3;
u64 var_len_right : 1;
u64 var_len_mask : 8;
u64 var_len_offset : 8;
u64 ptr_advance : 8;
u64 capture_flags : 4;
u64 rsvd_32_35 : 4;
u64 capture_ltype : 4;
u64 capture_lid : 3;
u64 rsvd_43 : 1;
u64 next_state : 8;
u64 parse_done : 1;
u64 capture_ena : 1;
u64 byp_count : 3;
u64 rsvd_63_57 : 7;
#endif
};
struct npc_mcam_kex_extr {
/* MKEX Profle Header */
u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */
u64 cpu_model; /* Format as profiled by CPU hardware */
u64 kpu_version; /* KPU firmware/profile version */
u64 reserved; /* Reserved for extension */
/* MKEX Profle Data */
u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
#define NPC_MAX_EXTRACTOR 24
/* MKEX Extractor data */
u64 intf_extr_lid[NPC_MAX_INTF][NPC_MAX_EXTRACTOR];
/* KEX configuration per extractor */
u64 intf_extr_lt[NPC_MAX_INTF][NPC_MAX_EXTRACTOR][NPC_MAX_LT];
} __packed;
struct npc_cn20k_kpu_profile_fwdata {
#define KPU_SIGN 0x00666f727075706b
#define KPU_NAME_LEN 32
/* Maximum number of custom KPU entries supported by
* the built-in profile.
*/
#define KPU_CN20K_MAX_CST_ENT 6
/* KPU Profle Header */
__le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */
u8 name[KPU_NAME_LEN]; /* KPU Profile name */
__le64 version; /* KPU profile version */
u8 kpus;
u8 reserved[7];
/* Default MKEX profile to be used with this KPU profile. May be
* overridden with mkex_profile module parameter.
* Format is same as for the MKEX profile to streamline processing.
*/
struct npc_mcam_kex_extr mkex;
/* LTYPE values for specific HW offloaded protocols. */
struct npc_lt_def_cfg lt_def;
/* Dynamically sized data:
* Custom KPU CAM and ACTION configuration entries.
* struct npc_kpu_fwdata kpu[kpus];
*/
u8 data[];
} __packed;
struct rvu;
struct npc_priv_t *npc_priv_get(void);
int npc_cn20k_init(struct rvu *rvu);
void npc_cn20k_deinit(struct rvu *rvu);
void npc_cn20k_subbank_calc_free(struct rvu *rvu, int *x2_free,
int *x4_free, int *sb_free);
int npc_cn20k_ref_idx_alloc(struct rvu *rvu, int pcifunc, int key_type,
int prio, u16 *mcam_idx, int ref, int limit,
bool contig, int count, bool virt);
int npc_cn20k_idx_free(struct rvu *rvu, u16 *mcam_idx, int count);
void npc_cn20k_parser_profile_init(struct rvu *rvu, int blkaddr);
struct npc_mcam_kex_extr *npc_mkex_extr_default_get(void);
void npc_cn20k_load_mkex_profile(struct rvu *rvu, int blkaddr,
const char *mkex_profile);
int npc_cn20k_apply_custom_kpu(struct rvu *rvu,
struct npc_kpu_profile_adapter *profile);
void
npc_cn20k_update_action_entries_n_flags(struct rvu *rvu,
struct npc_kpu_profile_adapter *pfl);
int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc);
void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pcifunc);
int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 pcifunc, u16 *bcast,
u16 *mcast, u16 *promisc, u16 *ucast);
int npc_cn20k_config_mcam_entry(struct rvu *rvu, int blkaddr, int index,
u8 intf, struct cn20k_mcam_entry *entry,
bool enable, u8 hw_prio, u8 req_kw_type);
int npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkaddr,
int index, bool enable);
int npc_cn20k_copy_mcam_entry(struct rvu *rvu, int blkaddr,
u16 src, u16 dest);
int npc_cn20k_read_mcam_entry(struct rvu *rvu, int blkaddr, u16 index,
struct cn20k_mcam_entry *entry, u8 *intf,
u8 *ena, u8 *hw_prio);
int npc_cn20k_clear_mcam_entry(struct rvu *rvu, int blkaddr, int index);
int npc_mcam_idx_2_key_type(struct rvu *rvu, u16 mcam_idx, u8 *key_type);
u16 npc_cn20k_vidx2idx(u16 index);
u16 npc_cn20k_idx2vidx(u16 idx);
int npc_cn20k_defrag(struct rvu *rvu);
bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc);
int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx,
struct npc_subbank **sb,
int *sb_off);
const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz);
int npc_cn20k_search_order_set(struct rvu *rvu, u64 narr[MAX_NUM_SUB_BANKS],
int cnt);
#endif /* NPC_CN20K_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h
+146
View File
@@ -0,0 +1,146 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#ifndef RVU_MBOX_REG_H
#define RVU_MBOX_REG_H
#include "../rvu.h"
#include "../rvu_reg.h"
/* RVUM block registers */
#define RVU_PF_DISC (0x0)
#define RVU_PRIV_PFX_DISC(a) (0x8000208 | (a) << 16)
#define RVU_PRIV_HWVFX_DISC(a) (0xD000000 | (a) << 12)
/* Mbox Registers */
/* RVU AF BAR0 Mbox registers for AF => PFx */
#define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4)
#define RVU_MBOX_AF_PFX_CFG(a) (0x6000 | (a) << 4)
#define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3)
#define RVU_MBOX_AF_PFAF_INT(a) (0x2980 | (a) << 6)
#define RVU_MBOX_AF_PFAF_INT_W1S(a) (0x2988 | (a) << 6)
#define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a) (0x2990 | (a) << 6)
#define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a) (0x2998 | (a) << 6)
#define RVU_MBOX_AF_PFAF1_INT(a) (0x29A0 | (a) << 6)
#define RVU_MBOX_AF_PFAF1_INT_W1S(a) (0x29A8 | (a) << 6)
#define RVU_MBOX_AF_PFAF1_INT_ENA_W1S(a) (0x29B0 | (a) << 6)
#define RVU_MBOX_AF_PFAF1_INT_ENA_W1C(a) (0x29B8 | (a) << 6)
/* RVU PF => AF mbox registers */
#define RVU_MBOX_PF_PFAF_TRIGX(a) (0xC00 | (a) << 3)
#define RVU_MBOX_PF_INT (0xC20)
#define RVU_MBOX_PF_INT_W1S (0xC28)
#define RVU_MBOX_PF_INT_ENA_W1S (0xC30)
#define RVU_MBOX_PF_INT_ENA_W1C (0xC38)
#define RVU_AF_BAR2_SEL (0x9000000)
#define RVU_AF_BAR2_PFID (0x16400)
#define NIX_CINTX_INT_W1S(a) (0xd30 | (a) << 12)
#define NIX_QINTX_CNT(a) (0xc00 | (a) << 12)
#define RVU_MBOX_AF_VFAF_INT(a) (0x3000 | (a) << 6)
#define RVU_MBOX_AF_VFAF_INT_W1S(a) (0x3008 | (a) << 6)
#define RVU_MBOX_AF_VFAF_INT_ENA_W1S(a) (0x3010 | (a) << 6)
#define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a) (0x3018 | (a) << 6)
#define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a) (0x3018 | (a) << 6)
#define RVU_MBOX_AF_VFAF1_INT(a) (0x3020 | (a) << 6)
#define RVU_MBOX_AF_VFAF1_INT_W1S(a) (0x3028 | (a) << 6)
#define RVU_MBOX_AF_VFAF1_IN_ENA_W1S(a) (0x3030 | (a) << 6)
#define RVU_MBOX_AF_VFAF1_IN_ENA_W1C(a) (0x3038 | (a) << 6)
#define RVU_MBOX_AF_AFVFX_TRIG(a, b) (0x10000 | (a) << 4 | (b) << 3)
#define RVU_MBOX_AF_VFX_ADDR(a) (0x20000 | (a) << 4)
#define RVU_MBOX_AF_VFX_CFG(a) (0x28000 | (a) << 4)
#define RVU_MBOX_PF_VFX_PFVF_TRIGX(a) (0x2000 | (a) << 3)
#define RVU_MBOX_PF_VFPF_INTX(a) (0x1000 | (a) << 3)
#define RVU_MBOX_PF_VFPF_INT_W1SX(a) (0x1020 | (a) << 3)
#define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a) (0x1040 | (a) << 3)
#define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a) (0x1060 | (a) << 3)
#define RVU_MBOX_PF_VFPF1_INTX(a) (0x1080 | (a) << 3)
#define RVU_MBOX_PF_VFPF1_INT_W1SX(a) (0x10a0 | (a) << 3)
#define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a) (0x10c0 | (a) << 3)
#define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a) (0x10e0 | (a) << 3)
#define RVU_MBOX_PF_VF_ADDR (0xC40)
#define RVU_MBOX_PF_LMTLINE_ADDR (0xC48)
#define RVU_MBOX_PF_VF_CFG (0xC60)
#define RVU_MBOX_VF_VFPF_TRIGX(a) (0x3000 | (a) << 3)
#define RVU_MBOX_VF_INT (0x20)
#define RVU_MBOX_VF_INT_W1S (0x28)
#define RVU_MBOX_VF_INT_ENA_W1S (0x30)
#define RVU_MBOX_VF_INT_ENA_W1C (0x38)
#define RVU_MBOX_VF_VFAF_TRIGX(a) (0x2000 | (a) << 3)
#define NIX_GINT_INT (0x200)
#define NIX_GINT_INT_W1S (0x208)
#define ALTAF_FLR BIT_ULL(0)
#define ALTAF_RDY BIT_ULL(1)
/* NPC registers */
#define NPC_AF_INTFX_EXTRACTORX_CFG(a, b) \
(0x20c000ull | (a) << 16 | (b) << 8)
#define NPC_AF_INTFX_EXTRACTORX_LTX_CFG(a, b, c) \
(0x204000ull | (a) << 16 | (b) << 8 | (c) << 3)
#define NPC_AF_KPMX_ENTRYX_CAMX(a, b, c) \
(0x20000ull | (a) << 12 | (b) << 3 | (c) << 16)
#define NPC_AF_KPMX_ENTRYX_ACTION0(a, b) \
(0x40000ull | (a) << 12 | (b) << 3)
#define NPC_AF_KPMX_ENTRYX_ACTION1(a, b) \
(0x50000ull | (a) << 12 | (b) << 3)
#define NPC_AF_KPMX_ENTRY_DISX(a, b) (0x60000ull | (a) << 12 | (b) << 3)
#define NPC_AF_KPM_PASS2_CFG 0x10210
#define NPC_AF_KPMX_PASS2_OFFSET(a) (0x60040ull | (a) << 12)
#define NPC_AF_MCAM_SECTIONX_CFG_EXT(a) (0xf000000ull | (a) << 3)
#define NPC_AF_CN20K_MCAMEX_BANKX_CAMX_INTF_EXT(a, b, c) ({ \
u64 offset; \
offset = (0x8000000ull | (a) << 4 | (b) << 20 | (c) << 3); \
offset; })
#define NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W0_EXT(a, b, c) ({ \
u64 offset; \
offset = (0x9000000ull | (a) << 4 | (b) << 20 | (c) << 3); \
offset; })
#define NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W1_EXT(a, b, c) ({ \
u64 offset; \
offset = (0x9400000ull | (a) << 4 | (b) << 20 | (c) << 3); \
offset; })
#define NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W2_EXT(a, b, c) ({ \
u64 offset; \
offset = (0x9800000ull | (a) << 4 | (b) << 20 | (c) << 3); \
offset; })
#define NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W3_EXT(a, b, c) ({ \
u64 offset; \
offset = (0x9c00000ull | (a) << 4 | (b) << 20 | (c) << 3); \
offset; })
#define NPC_AF_CN20K_MCAMEX_BANKX_CFG_EXT(a, b) ({ \
u64 offset; \
offset = (0xa000000ull | (a) << 4 | (b) << 20); \
offset; })
#define NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(a, b, c) ({ \
u64 offset; \
offset = (0xc000000ull | (a) << 4 | (b) << 20 | (c) << 22); \
offset; })
#define NPC_AF_INTFX_MISS_ACTX(a, b) (0xf003000 | (a) << 6 | (b) << 4)
#define NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(a, b) ({ \
u64 offset; \
offset = (0xb000000ull | (a) << 4 | (b) << 20); \
offset; })
#endif /* RVU_MBOX_REG_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h
+380
View File
@@ -0,0 +1,380 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#ifndef STRUCT_H
#define STRUCT_H
#define NIX_MAX_CTX_SIZE 128
/*
* CN20k RVU PF MBOX Interrupt Vector Enumeration
*
* Vectors 0 - 3 are compatible with pre cn20k and hence
* existing macros are being reused.
*/
enum rvu_mbox_pf_int_vec_e {
RVU_MBOX_PF_INT_VEC_VFPF_MBOX0 = 0x4,
RVU_MBOX_PF_INT_VEC_VFPF_MBOX1 = 0x5,
RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0 = 0x6,
RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1 = 0x7,
RVU_MBOX_PF_INT_VEC_AFPF_MBOX = 0x8,
RVU_MBOX_PF_INT_VEC_CNT = 0x9,
};
/* RVU Admin function Interrupt Vector Enumeration */
enum rvu_af_cn20k_int_vec_e {
RVU_AF_CN20K_INT_VEC_POISON = 0x0,
RVU_AF_CN20K_INT_VEC_PFFLR0 = 0x1,
RVU_AF_CN20K_INT_VEC_PFFLR1 = 0x2,
RVU_AF_CN20K_INT_VEC_PFME0 = 0x3,
RVU_AF_CN20K_INT_VEC_PFME1 = 0x4,
RVU_AF_CN20K_INT_VEC_GEN = 0x5,
RVU_AF_CN20K_INT_VEC_PFAF_MBOX0 = 0x6,
RVU_AF_CN20K_INT_VEC_PFAF_MBOX1 = 0x7,
RVU_AF_CN20K_INT_VEC_PFAF1_MBOX0 = 0x8,
RVU_AF_CN20K_INT_VEC_PFAF1_MBOX1 = 0x9,
RVU_AF_CN20K_INT_VEC_CNT = 0xa,
};
struct nix_cn20k_sq_ctx_s {
u64 ena : 1; /* W0 */
u64 qint_idx : 6;
u64 substream : 20;
u64 sdp_mcast : 1;
u64 cq : 20;
u64 sqe_way_mask : 16;
u64 smq : 11; /* W1 */
u64 cq_ena : 1;
u64 xoff : 1;
u64 sso_ena : 1;
u64 smq_rr_weight : 14;
u64 default_chan : 12;
u64 sqb_count : 16;
u64 reserved_120_120 : 1;
u64 smq_rr_count_lb : 7;
u64 smq_rr_count_ub : 25; /* W2 */
u64 sqb_aura : 20;
u64 sq_int : 8;
u64 sq_int_ena : 8;
u64 sqe_stype : 2;
u64 reserved_191_191 : 1;
u64 max_sqe_size : 2; /* W3 */
u64 cq_limit : 8;
u64 lmt_dis : 1;
u64 mnq_dis : 1;
u64 smq_next_sq : 20;
u64 smq_lso_segnum : 8;
u64 tail_offset : 6;
u64 smenq_offset : 6;
u64 head_offset : 6;
u64 smenq_next_sqb_vld : 1;
u64 smq_pend : 1;
u64 smq_next_sq_vld : 1;
u64 reserved_253_255 : 3;
u64 next_sqb : 64; /* W4 */
u64 tail_sqb : 64; /* W5 */
u64 smenq_sqb : 64; /* W6 */
u64 smenq_next_sqb : 64; /* W7 */
u64 head_sqb : 64; /* W8 */
u64 reserved_576_583 : 8; /* W9 */
u64 vfi_lso_total : 18;
u64 vfi_lso_sizem1 : 3;
u64 vfi_lso_sb : 8;
u64 vfi_lso_mps : 14;
u64 vfi_lso_vlan0_ins_ena : 1;
u64 vfi_lso_vlan1_ins_ena : 1;
u64 vfi_lso_vld : 1;
u64 reserved_630_639 : 10;
u64 scm_lso_rem : 18; /* W10 */
u64 reserved_658_703 : 46;
u64 octs : 48; /* W11 */
u64 reserved_752_767 : 16;
u64 pkts : 48; /* W12 */
u64 reserved_816_831 : 16;
u64 aged_drop_octs : 32; /* W13 */
u64 aged_drop_pkts : 32;
u64 dropped_octs : 48; /* W14 */
u64 reserved_944_959 : 16;
u64 dropped_pkts : 48; /* W15 */
u64 reserved_1008_1023 : 16;
};
static_assert(sizeof(struct nix_cn20k_sq_ctx_s) == NIX_MAX_CTX_SIZE);
struct nix_cn20k_cq_ctx_s {
u64 base : 64; /* W0 */
u64 lbp_ena : 1; /* W1 */
u64 lbpid_low : 3;
u64 bp_ena : 1;
u64 lbpid_med : 3;
u64 bpid : 9;
u64 lbpid_high : 3;
u64 qint_idx : 7;
u64 cq_err : 1;
u64 cint_idx : 7;
u64 avg_con : 9;
u64 wrptr : 20;
u64 tail : 20; /* W2 */
u64 head : 20;
u64 avg_level : 8;
u64 update_time : 16;
u64 bp : 8; /* W3 */
u64 drop : 8;
u64 drop_ena : 1;
u64 ena : 1;
u64 cpt_drop_err_en : 1;
u64 reserved_211_211 : 1;
u64 msh_dst : 11;
u64 msh_valid : 1;
u64 stash_thresh : 4;
u64 lbp_frac : 4;
u64 caching : 1;
u64 stashing : 1;
u64 reserved_234_235 : 2;
u64 qsize : 4;
u64 cq_err_int : 8;
u64 cq_err_int_ena : 8;
u64 bpid_ext : 2; /* W4 */
u64 reserved_258_259 : 2;
u64 lbpid_ext : 2;
u64 reserved_262_319 : 58;
u64 reserved_320_383 : 64; /* W5 */
u64 reserved_384_447 : 64; /* W6 */
u64 reserved_448_511 : 64; /* W7 */
u64 padding[8];
};
static_assert(sizeof(struct nix_cn20k_sq_ctx_s) == NIX_MAX_CTX_SIZE);
struct nix_cn20k_rq_ctx_s {
u64 ena : 1;
u64 sso_ena : 1;
u64 ipsech_ena : 1;
u64 ena_wqwd : 1;
u64 cq : 20;
u64 reserved_24_34 : 11;
u64 port_il4_dis : 1;
u64 port_ol4_dis : 1;
u64 lenerr_dis : 1;
u64 csum_il4_dis : 1;
u64 csum_ol4_dis : 1;
u64 len_il4_dis : 1;
u64 len_il3_dis : 1;
u64 len_ol4_dis : 1;
u64 len_ol3_dis : 1;
u64 wqe_aura : 20;
u64 spb_aura : 20;
u64 lpb_aura : 20;
u64 sso_grp : 10;
u64 sso_tt : 2;
u64 pb_caching : 2;
u64 wqe_caching : 1;
u64 xqe_drop_ena : 1;
u64 spb_drop_ena : 1;
u64 lpb_drop_ena : 1;
u64 pb_stashing : 1;
u64 ipsecd_drop_en : 1;
u64 chi_ena : 1;
u64 reserved_125_127 : 3;
u64 band_prof_id_l : 10;
u64 sso_fc_ena : 1;
u64 policer_ena : 1;
u64 spb_sizem1 : 6;
u64 wqe_skip : 2;
u64 spb_high_sizem1 : 3;
u64 spb_ena : 1;
u64 lpb_sizem1 : 12;
u64 first_skip : 7;
u64 reserved_171_171 : 1;
u64 later_skip : 6;
u64 xqe_imm_size : 6;
u64 band_prof_id_h : 4;
u64 reserved_188_189 : 2;
u64 xqe_imm_copy : 1;
u64 xqe_hdr_split : 1;
u64 xqe_drop : 8;
u64 xqe_pass : 8;
u64 wqe_pool_drop : 8;
u64 wqe_pool_pass : 8;
u64 spb_aura_drop : 8;
u64 spb_aura_pass : 8;
u64 spb_pool_drop : 8;
u64 spb_pool_pass : 8;
u64 lpb_aura_drop : 8;
u64 lpb_aura_pass : 8;
u64 lpb_pool_drop : 8;
u64 lpb_pool_pass : 8;
u64 reserved_288_291 : 4;
u64 rq_int : 8;
u64 rq_int_ena : 8;
u64 qint_idx : 7;
u64 reserved_315_319 : 5;
u64 ltag : 24;
u64 good_utag : 8;
u64 bad_utag : 8;
u64 flow_tagw : 6;
u64 ipsec_vwqe : 1;
u64 vwqe_ena : 1;
u64 vtime_wait : 8;
u64 max_vsize_exp : 4;
u64 vwqe_skip : 2;
u64 reserved_382_383 : 2;
u64 octs : 48;
u64 reserved_432_447 : 16;
u64 pkts : 48;
u64 reserved_496_511 : 16;
u64 drop_octs : 48;
u64 reserved_560_575 : 16;
u64 drop_pkts : 48;
u64 reserved_624_639 : 16;
u64 re_pkts : 48;
u64 reserved_688_703 : 16;
u64 reserved_704_767 : 64;
u64 reserved_768_831 : 64;
u64 reserved_832_895 : 64;
u64 reserved_896_959 : 64;
u64 reserved_960_1023 : 64;
};
static_assert(sizeof(struct nix_cn20k_rq_ctx_s) == NIX_MAX_CTX_SIZE);
struct npa_cn20k_aura_s {
u64 pool_addr; /* W0 */
u64 ena : 1; /* W1 */
u64 reserved_65 : 2;
u64 pool_caching : 1;
u64 reserved_68 : 16;
u64 avg_con : 9;
u64 reserved_93 : 1;
u64 pool_drop_ena : 1;
u64 aura_drop_ena : 1;
u64 bp_ena : 1;
u64 reserved_97_103 : 7;
u64 aura_drop : 8;
u64 shift : 6;
u64 reserved_118_119 : 2;
u64 avg_level : 8;
u64 count : 36; /* W2 */
u64 reserved_164_167 : 4;
u64 bpid : 12;
u64 reserved_180_191 : 12;
u64 limit : 36; /* W3 */
u64 reserved_228_231 : 4;
u64 bp : 7;
u64 reserved_239_243 : 5;
u64 fc_ena : 1;
u64 fc_up_crossing : 1;
u64 fc_stype : 2;
u64 fc_hyst_bits : 4;
u64 reserved_252_255 : 4;
u64 fc_addr; /* W4 */
u64 pool_drop : 8; /* W5 */
u64 update_time : 16;
u64 err_int : 8;
u64 err_int_ena : 8;
u64 thresh_int : 1;
u64 thresh_int_ena : 1;
u64 thresh_up : 1;
u64 reserved_363 : 1;
u64 thresh_qint_idx : 7;
u64 reserved_371 : 1;
u64 err_qint_idx : 7;
u64 reserved_379_383 : 5;
u64 thresh : 36; /* W6*/
u64 rsvd_423_420 : 4;
u64 fc_msh_dst : 11;
u64 reserved_435_438 : 4;
u64 op_dpc_ena : 1;
u64 op_dpc_set : 5;
u64 reserved_445_445 : 1;
u64 stream_ctx : 1;
u64 unified_ctx : 1;
u64 reserved_448_511; /* W7 */
u64 padding[8];
};
static_assert(sizeof(struct npa_cn20k_aura_s) == NIX_MAX_CTX_SIZE);
struct npa_cn20k_pool_s {
u64 stack_base; /* W0 */
u64 ena : 1;
u64 nat_align : 1;
u64 reserved_66_67 : 2;
u64 stack_caching : 1;
u64 reserved_69_87 : 19;
u64 buf_offset : 12;
u64 reserved_100_103 : 4;
u64 buf_size : 12;
u64 reserved_116_119 : 4;
u64 ref_cnt_prof : 3;
u64 reserved_123_127 : 5;
u64 stack_max_pages : 32;
u64 stack_pages : 32;
uint64_t bp_0 : 7;
uint64_t bp_1 : 7;
uint64_t bp_2 : 7;
uint64_t bp_3 : 7;
uint64_t bp_4 : 7;
uint64_t bp_5 : 7;
uint64_t bp_6 : 7;
uint64_t bp_7 : 7;
uint64_t bp_ena_0 : 1;
uint64_t bp_ena_1 : 1;
uint64_t bp_ena_2 : 1;
uint64_t bp_ena_3 : 1;
uint64_t bp_ena_4 : 1;
uint64_t bp_ena_5 : 1;
uint64_t bp_ena_6 : 1;
uint64_t bp_ena_7 : 1;
u64 stack_offset : 4;
u64 reserved_260_263 : 4;
u64 shift : 6;
u64 reserved_270_271 : 2;
u64 avg_level : 8;
u64 avg_con : 9;
u64 fc_ena : 1;
u64 fc_stype : 2;
u64 fc_hyst_bits : 4;
u64 fc_up_crossing : 1;
u64 reserved_297_299 : 3;
u64 update_time : 16;
u64 reserved_316_319 : 4;
u64 fc_addr; /* W5 */
u64 ptr_start; /* W6 */
u64 ptr_end; /* W7 */
u64 bpid_0 : 12;
u64 reserved_524_535 : 12;
u64 err_int : 8;
u64 err_int_ena : 8;
u64 thresh_int : 1;
u64 thresh_int_ena : 1;
u64 thresh_up : 1;
u64 reserved_555 : 1;
u64 thresh_qint_idx : 7;
u64 reserved_563 : 1;
u64 err_qint_idx : 7;
u64 reserved_571_575 : 5;
u64 thresh : 36;
u64 rsvd_612_615 : 4;
u64 fc_msh_dst : 11;
u64 reserved_627_630 : 4;
u64 op_dpc_ena : 1;
u64 op_dpc_set : 5;
u64 reserved_637_637 : 1;
u64 stream_ctx : 1;
u64 reserved_639 : 1;
u64 reserved_640_703; /* W10 */
u64 reserved_704_767; /* W11 */
u64 reserved_768_831; /* W12 */
u64 reserved_832_895; /* W13 */
u64 reserved_896_959; /* W14 */
u64 reserved_960_1023; /* W15 */
};
static_assert(sizeof(struct npa_cn20k_pool_s) == NIX_MAX_CTX_SIZE);
#endif
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/common.h
+239
View File
@@ -0,0 +1,239 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*/
#ifndef COMMON_H
#define COMMON_H
#include "rvu_struct.h"
#define OTX2_ALIGN 128 /* Align to cacheline */
#define Q_SIZE_16 0ULL /* 16 entries */
#define Q_SIZE_64 1ULL /* 64 entries */
#define Q_SIZE_256 2ULL
#define Q_SIZE_1K 3ULL
#define Q_SIZE_4K 4ULL
#define Q_SIZE_16K 5ULL
#define Q_SIZE_64K 6ULL
#define Q_SIZE_256K 7ULL
#define Q_SIZE_1M 8ULL /* Million entries */
#define Q_SIZE_MIN Q_SIZE_16
#define Q_SIZE_MAX Q_SIZE_1M
#define Q_COUNT(x) (16ULL << (2 * x))
#define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2)
/* Admin queue info */
/* Since we intend to add only one instruction at a time,
* keep queue size to it's minimum.
*/
#define AQ_SIZE Q_SIZE_16
/* HW head & tail pointer mask */
#define AQ_PTR_MASK 0xFFFFF
struct qmem {
void *base;
dma_addr_t iova;
int alloc_sz;
u32 entry_sz;
u8 align;
u32 qsize;
};
static inline int qmem_alloc(struct device *dev, struct qmem **q,
int qsize, int entry_sz)
{
struct qmem *qmem;
int aligned_addr;
if (!qsize)
return -EINVAL;
*q = devm_kzalloc(dev, sizeof(*qmem), GFP_KERNEL);
if (!*q)
return -ENOMEM;
qmem = *q;
qmem->entry_sz = entry_sz;
qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN;
qmem->base = dma_alloc_attrs(dev, qmem->alloc_sz, &qmem->iova,
GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS);
if (!qmem->base)
return -ENOMEM;
qmem->qsize = qsize;
aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN);
qmem->align = (aligned_addr - qmem->iova);
qmem->base += qmem->align;
qmem->iova += qmem->align;
return 0;
}
static inline void qmem_free(struct device *dev, struct qmem *qmem)
{
if (!qmem)
return;
if (qmem->base)
dma_free_attrs(dev, qmem->alloc_sz,
qmem->base - qmem->align,
qmem->iova - qmem->align,
DMA_ATTR_FORCE_CONTIGUOUS);
devm_kfree(dev, qmem);
}
struct admin_queue {
struct qmem *inst;
struct qmem *res;
spinlock_t lock; /* Serialize inst enqueue from PFs */
};
/* NPA aura count */
enum npa_aura_sz {
NPA_AURA_SZ_0,
NPA_AURA_SZ_128,
NPA_AURA_SZ_256,
NPA_AURA_SZ_512,
NPA_AURA_SZ_1K,
NPA_AURA_SZ_2K,
NPA_AURA_SZ_4K,
NPA_AURA_SZ_8K,
NPA_AURA_SZ_16K,
NPA_AURA_SZ_32K,
NPA_AURA_SZ_64K,
NPA_AURA_SZ_128K,
NPA_AURA_SZ_256K,
NPA_AURA_SZ_512K,
NPA_AURA_SZ_1M,
NPA_AURA_SZ_MAX,
};
#define NPA_AURA_COUNT(x) (1ULL << ((x) + 6))
/* NPA AQ result structure for init/read/write of aura HW contexts */
struct npa_aq_aura_res {
struct npa_aq_res_s res;
struct npa_aura_s aura_ctx;
struct npa_aura_s ctx_mask;
};
/* NPA AQ result structure for init/read/write of pool HW contexts */
struct npa_aq_pool_res {
struct npa_aq_res_s res;
struct npa_pool_s pool_ctx;
struct npa_pool_s ctx_mask;
};
/* NIX Transmit schedulers */
enum nix_scheduler {
NIX_TXSCH_LVL_SMQ = 0x0,
NIX_TXSCH_LVL_MDQ = 0x0,
NIX_TXSCH_LVL_TL4 = 0x1,
NIX_TXSCH_LVL_TL3 = 0x2,
NIX_TXSCH_LVL_TL2 = 0x3,
NIX_TXSCH_LVL_TL1 = 0x4,
NIX_TXSCH_LVL_CNT = 0x5,
};
#define TXSCH_RR_QTM_MAX ((1 << 24) - 1)
#define TXSCH_TL1_DFLT_RR_QTM TXSCH_RR_QTM_MAX
#define TXSCH_TL1_DFLT_RR_PRIO (0x7ull)
#define CN10K_MAX_DWRR_WEIGHT 16384 /* Weight is 14bit on CN10K */
/* Don't change the order as on CN10K (except CN10KB)
* SMQX_CFG[SDP] value should be 1 for SDP flows.
*/
#define SMQ_LINK_TYPE_RPM 0
#define SMQ_LINK_TYPE_SDP 1
#define SMQ_LINK_TYPE_LBK 2
/* Min/Max packet sizes, excluding FCS */
#define NIC_HW_MIN_FRS 40
#define NIC_HW_MAX_FRS 9212
#define SDP_HW_MAX_FRS 65535
#define SDP_HW_MIN_FRS 16
#define CN10K_LMAC_LINK_MAX_FRS 16380 /* 16k - FCS */
#define CN10K_LBK_LINK_MAX_FRS 65535 /* 64k */
#define SDP_LINK_CREDIT 0x320202
/* NIX RX action operation*/
#define NIX_RX_ACTIONOP_DROP (0x0ull)
#define NIX_RX_ACTIONOP_UCAST (0x1ull)
#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
#define NIX_RX_ACTIONOP_MCAST (0x3ull)
#define NIX_RX_ACTIONOP_RSS (0x4ull)
/* Use the RX action set in the default unicast entry */
#define NIX_RX_ACTION_DEFAULT (0xfull)
/* NIX TX action operation*/
#define NIX_TX_ACTIONOP_DROP (0x0ull)
#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
#define NIX_TX_ACTIONOP_MCAST (0x3ull)
#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
#define NIX_INTFX_RX(a) (0x0ull | (a) << 1)
#define NIX_INTFX_TX(a) (0x1ull | (a) << 1)
/* Default interfaces are NIX0_RX and NIX0_TX */
#define NIX_INTF_RX NIX_INTFX_RX(0)
#define NIX_INTF_TX NIX_INTFX_TX(0)
#define NIX_INTF_TYPE_CGX 0
#define NIX_INTF_TYPE_LBK 1
#define NIX_INTF_TYPE_SDP 2
#define MAX_LMAC_PKIND 12
#define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b))
#define NIX_LINK_LBK(a) (12 + (a))
#define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
#define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b))
#define NIX_CHAN_SDP_CH_START (0x700ull)
#define NIX_CHAN_SDP_CHX(a) (NIX_CHAN_SDP_CH_START + (a))
#define NIX_CHAN_SDP_NUM_CHANS 256
#define NIX_CHAN_CPT_CH_START (0x800ull)
/* The mask is to extract lower 10-bits of channel number
* which CPT will pass to X2P.
*/
#define NIX_CHAN_CPT_X2P_MASK (0x3ffull)
/* NIX LSO format indices.
* As of now TSO is the only one using, so statically assigning indices.
*/
#define NIX_LSO_FORMAT_IDX_TSOV4 0
#define NIX_LSO_FORMAT_IDX_TSOV6 1
/* RSS info */
#define MAX_RSS_GROUPS 8
/* Group 0 has to be used in default pkt forwarding MCAM entries
* reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple
* filters.
*/
#define DEFAULT_RSS_CONTEXT_GROUP 0
#define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */
/* NDC info */
enum ndc_idx_e {
NIX0_RX = 0x0,
NIX0_TX = 0x1,
NPA0_U = 0x2,
NIX1_RX = 0x4,
NIX1_TX = 0x5,
};
enum ndc_ctype_e {
CACHING = 0x0,
BYPASS = 0x1,
};
#define NDC_MAX_PORT 6
#define NDC_READ_TRANS 0
#define NDC_WRITE_TRANS 1
#endif /* COMMON_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h
+175
View File
@@ -0,0 +1,175 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell CN10K RPM driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef LMAC_COMMON_H
#define LMAC_COMMON_H
#include "rvu.h"
#include "cgx.h"
/**
* struct lmac - per lmac locks and properties
* @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion
* @cmd_lock: Lock to serialize the command interface
* @resp: command response
* @link_info: link related information
* @mac_to_index_bmap: Mac address to CGX table index mapping
* @rx_fc_pfvf_bmap: Receive flow control enabled netdev mapping
* @tx_fc_pfvf_bmap: Transmit flow control enabled netdev mapping
* @event_cb: callback for linkchange events
* @event_cb_lock: lock for serializing callback with unregister
* @cgx: parent cgx port
* @mcast_filters_count: Number of multicast filters installed
* @lmac_id: lmac port id
* @lmac_type: lmac type like SGMII/XAUI
* @cmd_pend: flag set before new command is started
* flag cleared after command response is received
* @name: lmac port name
*/
struct lmac {
wait_queue_head_t wq_cmd_cmplt;
/* Lock to serialize the command interface */
struct mutex cmd_lock;
u64 resp;
struct cgx_link_user_info link_info;
struct rsrc_bmap mac_to_index_bmap;
struct rsrc_bmap rx_fc_pfvf_bmap;
struct rsrc_bmap tx_fc_pfvf_bmap;
struct cgx_event_cb event_cb;
/* lock for serializing callback with unregister */
spinlock_t event_cb_lock;
struct cgx *cgx;
u8 mcast_filters_count;
u8 lmac_id;
u8 lmac_type;
bool cmd_pend;
char *name;
};
/* CGX & RPM has different feature set
* update the structure fields with different one
*/
struct mac_ops {
char *name;
/* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
* bar offset for example
* CGX DMAC_CTL0 0x1f8
* RPM DMAC_CTL0 0x4ff8
*/
u64 csr_offset;
/* For ATF to send events to kernel, there is no dedicated interrupt
* defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports
* SW_INT so that ATF triggers this interrupt after processing of
* requested command
*/
u64 int_register;
u64 int_set_reg;
/* lmac offset is different is RPM */
u8 lmac_offset;
u8 irq_offset;
u8 int_ena_bit;
u8 lmac_fwi;
bool non_contiguous_serdes_lane;
/* RPM & CGX differs in number of Receive/transmit stats */
u8 rx_stats_cnt;
u8 tx_stats_cnt;
/* Unlike CN10K which shares same CSR offset with CGX
* CNF10KB has different csr offset
*/
u64 rxid_map_offset;
u8 dmac_filter_count;
/* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST]
* number of setbits in lmac_exist tells number of lmacs
*/
int (*get_nr_lmacs)(void *cgx);
u8 (*get_lmac_type)(void *cgx, int lmac_id);
u32 (*lmac_fifo_len)(void *cgx, int lmac_id);
int (*mac_lmac_intl_lbk)(void *cgx, int lmac_id,
bool enable);
/* Register Stats related functions */
int (*mac_get_rx_stats)(void *cgx, int lmac_id,
int idx, u64 *rx_stat);
int (*mac_get_tx_stats)(void *cgx, int lmac_id,
int idx, u64 *tx_stat);
/* Enable LMAC Pause Frame Configuration */
void (*mac_enadis_rx_pause_fwding)(void *cgxd,
int lmac_id,
bool enable);
int (*mac_get_pause_frm_status)(void *cgxd,
int lmac_id,
u8 *tx_pause,
u8 *rx_pause);
int (*mac_enadis_pause_frm)(void *cgxd,
int lmac_id,
u8 tx_pause,
u8 rx_pause);
void (*mac_pause_frm_config)(void *cgxd,
int lmac_id,
bool enable);
/* Enable/Disable Inbound PTP */
void (*mac_enadis_ptp_config)(void *cgxd,
int lmac_id,
bool enable);
int (*mac_rx_tx_enable)(void *cgxd, int lmac_id, bool enable);
int (*mac_tx_enable)(void *cgxd, int lmac_id, bool enable);
int (*pfc_config)(void *cgxd, int lmac_id,
u8 tx_pause, u8 rx_pause, u16 pfc_en);
int (*mac_get_pfc_frm_cfg)(void *cgxd, int lmac_id,
u8 *tx_pause, u8 *rx_pause);
int (*mac_reset)(void *cgxd, int lmac_id, u8 pf_req_flr);
/* FEC stats */
int (*get_fec_stats)(void *cgxd, int lmac_id,
struct cgx_fec_stats_rsp *rsp);
int (*mac_stats_reset)(void *cgxd, int lmac_id);
void (*mac_x2p_reset)(void *cgxd, bool enable);
int (*mac_enadis_rx)(void *cgxd, int lmac_id, bool enable);
};
struct cgx {
void __iomem *reg_base;
struct pci_dev *pdev;
u8 cgx_id;
u8 lmac_count;
/* number of LMACs per MAC could be 4 or 8 */
u8 max_lmac_per_mac;
/* length of fifo varies depending on the number
* of LMACS
*/
u32 fifo_len;
#define MAX_LMAC_COUNT 8
struct lmac *lmac_idmap[MAX_LMAC_COUNT];
struct work_struct cgx_cmd_work;
struct workqueue_struct *cgx_cmd_workq;
struct list_head cgx_list;
u64 hw_features;
struct mac_ops *mac_ops;
unsigned long lmac_bmap; /* bitmap of enabled lmacs */
/* Lock to serialize read/write of global csrs like
* RPMX_MTI_STAT_DATA_HI_CDC etc
*/
struct mutex lock;
};
typedef struct cgx rpm_t;
/* Function Declarations */
void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val);
u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset);
struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx);
int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac);
int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id);
bool is_lmac_valid(struct cgx *cgx, int lmac_id);
struct mac_ops *rpm_get_mac_ops(struct cgx *cgx);
#endif /* LMAC_COMMON_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mbox.c
+569
View File
@@ -0,0 +1,569 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include "rvu_reg.h"
#include "cn20k/reg.h"
#include "cn20k/api.h"
#include "mbox.h"
#include "rvu_trace.h"
#include "rvu.h"
static const u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid)
{
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
struct mbox_hdr *tx_hdr, *rx_hdr;
void *hw_mbase = mdev->hwbase;
tx_hdr = hw_mbase + mbox->tx_start;
rx_hdr = hw_mbase + mbox->rx_start;
mdev->msg_size = 0;
mdev->rsp_size = 0;
tx_hdr->num_msgs = 0;
tx_hdr->msg_size = 0;
tx_hdr->sig = 0;
rx_hdr->num_msgs = 0;
rx_hdr->msg_size = 0;
rx_hdr->sig = 0;
}
EXPORT_SYMBOL(__otx2_mbox_reset);
void otx2_mbox_reset(struct otx2_mbox *mbox, int devid)
{
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
spin_lock(&mdev->mbox_lock);
__otx2_mbox_reset(mbox, devid);
spin_unlock(&mdev->mbox_lock);
}
EXPORT_SYMBOL(otx2_mbox_reset);
void otx2_mbox_destroy(struct otx2_mbox *mbox)
{
mbox->reg_base = NULL;
mbox->hwbase = NULL;
kfree(mbox->dev);
mbox->dev = NULL;
}
EXPORT_SYMBOL(otx2_mbox_destroy);
int cn20k_mbox_setup(struct otx2_mbox *mbox, struct pci_dev *pdev,
void *reg_base, int direction, int ndevs)
{
switch (direction) {
case MBOX_DIR_AFPF:
case MBOX_DIR_PFVF:
mbox->tx_start = MBOX_DOWN_TX_START;
mbox->rx_start = MBOX_DOWN_RX_START;
mbox->tx_size = MBOX_DOWN_TX_SIZE;
mbox->rx_size = MBOX_DOWN_RX_SIZE;
break;
case MBOX_DIR_PFAF:
case MBOX_DIR_VFPF:
mbox->tx_start = MBOX_DOWN_RX_START;
mbox->rx_start = MBOX_DOWN_TX_START;
mbox->tx_size = MBOX_DOWN_RX_SIZE;
mbox->rx_size = MBOX_DOWN_TX_SIZE;
break;
case MBOX_DIR_AFPF_UP:
case MBOX_DIR_PFVF_UP:
mbox->tx_start = MBOX_UP_TX_START;
mbox->rx_start = MBOX_UP_RX_START;
mbox->tx_size = MBOX_UP_TX_SIZE;
mbox->rx_size = MBOX_UP_RX_SIZE;
break;
case MBOX_DIR_PFAF_UP:
case MBOX_DIR_VFPF_UP:
mbox->tx_start = MBOX_UP_RX_START;
mbox->rx_start = MBOX_UP_TX_START;
mbox->tx_size = MBOX_UP_RX_SIZE;
mbox->rx_size = MBOX_UP_TX_SIZE;
break;
default:
return -ENODEV;
}
switch (direction) {
case MBOX_DIR_AFPF:
mbox->trigger = RVU_MBOX_AF_AFPFX_TRIGX(1);
mbox->tr_shift = 4;
break;
case MBOX_DIR_AFPF_UP:
mbox->trigger = RVU_MBOX_AF_AFPFX_TRIGX(0);
mbox->tr_shift = 4;
break;
case MBOX_DIR_PFAF:
mbox->trigger = RVU_MBOX_PF_PFAF_TRIGX(0);
mbox->tr_shift = 0;
break;
case MBOX_DIR_PFAF_UP:
mbox->trigger = RVU_MBOX_PF_PFAF_TRIGX(1);
mbox->tr_shift = 0;
break;
case MBOX_DIR_PFVF:
mbox->trigger = RVU_MBOX_PF_VFX_PFVF_TRIGX(1);
mbox->tr_shift = 4;
break;
case MBOX_DIR_PFVF_UP:
mbox->trigger = RVU_MBOX_PF_VFX_PFVF_TRIGX(0);
mbox->tr_shift = 4;
break;
case MBOX_DIR_VFPF:
mbox->trigger = RVU_MBOX_VF_VFPF_TRIGX(0);
mbox->tr_shift = 0;
break;
case MBOX_DIR_VFPF_UP:
mbox->trigger = RVU_MBOX_VF_VFPF_TRIGX(1);
mbox->tr_shift = 0;
break;
default:
return -ENODEV;
}
mbox->reg_base = reg_base;
mbox->pdev = pdev;
mbox->dev = kzalloc_objs(struct otx2_mbox_dev, ndevs);
if (!mbox->dev) {
otx2_mbox_destroy(mbox);
return -ENOMEM;
}
mbox->ndevs = ndevs;
return 0;
}
static int otx2_mbox_setup(struct otx2_mbox *mbox, struct pci_dev *pdev,
void *reg_base, int direction, int ndevs)
{
if (is_cn20k(pdev))
return cn20k_mbox_setup(mbox, pdev, reg_base,
direction, ndevs);
switch (direction) {
case MBOX_DIR_AFPF:
case MBOX_DIR_PFVF:
mbox->tx_start = MBOX_DOWN_TX_START;
mbox->rx_start = MBOX_DOWN_RX_START;
mbox->tx_size = MBOX_DOWN_TX_SIZE;
mbox->rx_size = MBOX_DOWN_RX_SIZE;
break;
case MBOX_DIR_PFAF:
case MBOX_DIR_VFPF:
mbox->tx_start = MBOX_DOWN_RX_START;
mbox->rx_start = MBOX_DOWN_TX_START;
mbox->tx_size = MBOX_DOWN_RX_SIZE;
mbox->rx_size = MBOX_DOWN_TX_SIZE;
break;
case MBOX_DIR_AFPF_UP:
case MBOX_DIR_PFVF_UP:
mbox->tx_start = MBOX_UP_TX_START;
mbox->rx_start = MBOX_UP_RX_START;
mbox->tx_size = MBOX_UP_TX_SIZE;
mbox->rx_size = MBOX_UP_RX_SIZE;
break;
case MBOX_DIR_PFAF_UP:
case MBOX_DIR_VFPF_UP:
mbox->tx_start = MBOX_UP_RX_START;
mbox->rx_start = MBOX_UP_TX_START;
mbox->tx_size = MBOX_UP_RX_SIZE;
mbox->rx_size = MBOX_UP_TX_SIZE;
break;
default:
return -ENODEV;
}
switch (direction) {
case MBOX_DIR_AFPF:
case MBOX_DIR_AFPF_UP:
mbox->trigger = RVU_AF_AFPF_MBOX0;
mbox->tr_shift = 4;
break;
case MBOX_DIR_PFAF:
case MBOX_DIR_PFAF_UP:
mbox->trigger = RVU_PF_PFAF_MBOX1;
mbox->tr_shift = 0;
break;
case MBOX_DIR_PFVF:
case MBOX_DIR_PFVF_UP:
mbox->trigger = RVU_PF_VFX_PFVF_MBOX0;
mbox->tr_shift = 12;
break;
case MBOX_DIR_VFPF:
case MBOX_DIR_VFPF_UP:
mbox->trigger = RVU_VF_VFPF_MBOX1;
mbox->tr_shift = 0;
break;
default:
return -ENODEV;
}
mbox->reg_base = reg_base;
mbox->pdev = pdev;
mbox->dev = kzalloc_objs(struct otx2_mbox_dev, ndevs);
if (!mbox->dev) {
otx2_mbox_destroy(mbox);
return -ENOMEM;
}
mbox->ndevs = ndevs;
return 0;
}
int otx2_mbox_init(struct otx2_mbox *mbox, void *hwbase, struct pci_dev *pdev,
void *reg_base, int direction, int ndevs)
{
struct otx2_mbox_dev *mdev;
int devid, err;
err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs);
if (err)
return err;
mbox->hwbase = hwbase;
for (devid = 0; devid < ndevs; devid++) {
mdev = &mbox->dev[devid];
mdev->mbase = mbox->hwbase + (devid * MBOX_SIZE);
mdev->hwbase = mdev->mbase;
spin_lock_init(&mdev->mbox_lock);
/* Init header to reset value */
otx2_mbox_reset(mbox, devid);
}
return 0;
}
EXPORT_SYMBOL(otx2_mbox_init);
/* Initialize mailbox with the set of mailbox region addresses
* in the array hwbase.
*/
int otx2_mbox_regions_init(struct otx2_mbox *mbox, void **hwbase,
struct pci_dev *pdev, void *reg_base,
int direction, int ndevs, unsigned long *pf_bmap)
{
struct otx2_mbox_dev *mdev;
int devid, err;
err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs);
if (err)
return err;
mbox->hwbase = hwbase[0];
for (devid = 0; devid < ndevs; devid++) {
if (!test_bit(devid, pf_bmap))
continue;
mdev = &mbox->dev[devid];
mdev->mbase = hwbase[devid];
mdev->hwbase = hwbase[devid];
spin_lock_init(&mdev->mbox_lock);
/* Init header to reset value */
otx2_mbox_reset(mbox, devid);
}
return 0;
}
EXPORT_SYMBOL(otx2_mbox_regions_init);
int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid)
{
unsigned long timeout = jiffies + msecs_to_jiffies(MBOX_RSP_TIMEOUT);
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
while (!time_after(jiffies, timeout)) {
if (mdev->num_msgs == mdev->msgs_acked)
return 0;
usleep_range(800, 1000);
}
trace_otx2_msg_wait_rsp(mbox->pdev);
return -EIO;
}
EXPORT_SYMBOL(otx2_mbox_wait_for_rsp);
int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid)
{
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
unsigned long timeout = jiffies + 1 * HZ;
while (!time_after(jiffies, timeout)) {
if (mdev->num_msgs == mdev->msgs_acked)
return 0;
cpu_relax();
}
return -EIO;
}
EXPORT_SYMBOL(otx2_mbox_busy_poll_for_rsp);
static void otx2_mbox_msg_send_data(struct otx2_mbox *mbox, int devid, u64 data)
{
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
struct mbox_hdr *tx_hdr, *rx_hdr;
void *hw_mbase = mdev->hwbase;
struct mbox_msghdr *msg;
u64 intr_val;
tx_hdr = hw_mbase + mbox->tx_start;
rx_hdr = hw_mbase + mbox->rx_start;
/* If bounce buffer is implemented copy mbox messages from
* bounce buffer to hw mbox memory.
*/
if (mdev->mbase != hw_mbase)
memcpy(hw_mbase + mbox->tx_start + msgs_offset,
mdev->mbase + mbox->tx_start + msgs_offset,
mdev->msg_size);
spin_lock(&mdev->mbox_lock);
if (!tx_hdr->sig) {
tx_hdr->msg_size = mdev->msg_size;
tx_hdr->num_msgs = mdev->num_msgs;
}
/* Reset header for next messages */
mdev->msg_size = 0;
mdev->rsp_size = 0;
mdev->msgs_acked = 0;
/* Sync mbox data into memory */
smp_wmb();
/* num_msgs != 0 signals to the peer that the buffer has a number of
* messages. So this should be written after writing all the messages
* to the shared memory.
*/
rx_hdr->num_msgs = 0;
msg = (struct mbox_msghdr *)(hw_mbase + mbox->tx_start + msgs_offset);
trace_otx2_msg_send(mbox->pdev, tx_hdr->num_msgs, tx_hdr->msg_size,
msg->id, msg->pcifunc);
spin_unlock(&mdev->mbox_lock);
/* Check if interrupt pending */
intr_val = readq((void __iomem *)mbox->reg_base +
(mbox->trigger | (devid << mbox->tr_shift)));
intr_val |= data;
/* The interrupt should be fired after num_msgs is written
* to the shared memory
*/
writeq(intr_val, (void __iomem *)mbox->reg_base +
(mbox->trigger | (devid << mbox->tr_shift)));
}
void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid)
{
otx2_mbox_msg_send_data(mbox, devid, MBOX_DOWN_MSG);
}
EXPORT_SYMBOL(otx2_mbox_msg_send);
void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid)
{
otx2_mbox_msg_send_data(mbox, devid, MBOX_UP_MSG);
}
EXPORT_SYMBOL(otx2_mbox_msg_send_up);
bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid)
{
u64 data;
data = readq((void __iomem *)mbox->reg_base +
(mbox->trigger | (devid << mbox->tr_shift)));
/* If data is non-zero wait for ~1ms and return to caller
* whether data has changed to zero or not after the wait.
*/
if (!data)
return true;
usleep_range(950, 1000);
data = readq((void __iomem *)mbox->reg_base +
(mbox->trigger | (devid << mbox->tr_shift)));
return data == 0;
}
EXPORT_SYMBOL(otx2_mbox_wait_for_zero);
struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
int size, int size_rsp)
{
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
struct mbox_msghdr *msghdr = NULL;
struct mbox_hdr *mboxhdr = NULL;
spin_lock(&mdev->mbox_lock);
size = ALIGN(size, MBOX_MSG_ALIGN);
size_rsp = ALIGN(size_rsp, MBOX_MSG_ALIGN);
/* Check if there is space in mailbox */
if ((mdev->msg_size + size) > mbox->tx_size - msgs_offset)
goto exit;
if ((mdev->rsp_size + size_rsp) > mbox->rx_size - msgs_offset)
goto exit;
if (mdev->msg_size == 0)
mdev->num_msgs = 0;
mdev->num_msgs++;
msghdr = mdev->mbase + mbox->tx_start + msgs_offset + mdev->msg_size;
/* Clear the whole msg region */
memset(msghdr, 0, size);
/* Init message header with reset values */
msghdr->ver = OTX2_MBOX_VERSION;
mdev->msg_size += size;
mdev->rsp_size += size_rsp;
msghdr->next_msgoff = mdev->msg_size + msgs_offset;
mboxhdr = mdev->mbase + mbox->tx_start;
/* Clear the msg header region */
memset(mboxhdr, 0, msgs_offset);
exit:
spin_unlock(&mdev->mbox_lock);
return msghdr;
}
EXPORT_SYMBOL(otx2_mbox_alloc_msg_rsp);
struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
struct mbox_msghdr *msg)
{
unsigned long imsg = mbox->tx_start + msgs_offset;
unsigned long irsp = mbox->rx_start + msgs_offset;
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
u16 msgs;
spin_lock(&mdev->mbox_lock);
if (mdev->num_msgs != mdev->msgs_acked)
goto error;
for (msgs = 0; msgs < mdev->msgs_acked; msgs++) {
struct mbox_msghdr *pmsg = mdev->mbase + imsg;
struct mbox_msghdr *prsp = mdev->mbase + irsp;
if (msg == pmsg) {
if (pmsg->id != prsp->id)
goto error;
spin_unlock(&mdev->mbox_lock);
return prsp;
}
imsg = mbox->tx_start + pmsg->next_msgoff;
irsp = mbox->rx_start + prsp->next_msgoff;
}
error:
spin_unlock(&mdev->mbox_lock);
return ERR_PTR(-ENODEV);
}
EXPORT_SYMBOL(otx2_mbox_get_rsp);
int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid)
{
unsigned long ireq = mbox->tx_start + msgs_offset;
unsigned long irsp = mbox->rx_start + msgs_offset;
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
int rc = -ENODEV;
u16 msgs;
spin_lock(&mdev->mbox_lock);
if (mdev->num_msgs != mdev->msgs_acked)
goto exit;
for (msgs = 0; msgs < mdev->msgs_acked; msgs++) {
struct mbox_msghdr *preq = mdev->mbase + ireq;
struct mbox_msghdr *prsp = mdev->mbase + irsp;
if (preq->id != prsp->id) {
trace_otx2_msg_check(mbox->pdev, preq->id,
prsp->id, prsp->rc);
goto exit;
}
if (prsp->rc) {
rc = prsp->rc;
trace_otx2_msg_check(mbox->pdev, preq->id,
prsp->id, prsp->rc);
goto exit;
}
ireq = mbox->tx_start + preq->next_msgoff;
irsp = mbox->rx_start + prsp->next_msgoff;
}
rc = 0;
exit:
spin_unlock(&mdev->mbox_lock);
return rc;
}
EXPORT_SYMBOL(otx2_mbox_check_rsp_msgs);
int
otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, u16 pcifunc, u16 id)
{
struct msg_rsp *rsp;
rsp = (struct msg_rsp *)
otx2_mbox_alloc_msg(mbox, devid, sizeof(*rsp));
if (!rsp)
return -ENOMEM;
rsp->hdr.id = id;
rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
rsp->hdr.rc = MBOX_MSG_INVALID;
rsp->hdr.pcifunc = pcifunc;
return 0;
}
EXPORT_SYMBOL(otx2_reply_invalid_msg);
bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
{
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
bool ret;
spin_lock(&mdev->mbox_lock);
ret = mdev->num_msgs != 0;
spin_unlock(&mdev->mbox_lock);
return ret;
}
EXPORT_SYMBOL(otx2_mbox_nonempty);
const char *otx2_mbox_id2name(u16 id)
{
switch (id) {
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
MBOX_MESSAGES
#undef M
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
MBOX_UP_CGX_MESSAGES
#undef M
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
MBOX_UP_CPT_MESSAGES
#undef M
default:
return "INVALID ID";
}
}
EXPORT_SYMBOL(otx2_mbox_id2name);
MODULE_AUTHOR("Marvell.");
MODULE_DESCRIPTION("Marvell RVU NIC Mbox helpers");
MODULE_LICENSE("GPL v2");
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+2645
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
+1617
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mcs.h
+246
View File
@@ -0,0 +1,246 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell CN10K MCS driver
*
* Copyright (C) 2022 Marvell.
*/
#ifndef MCS_H
#define MCS_H
#include <linux/bits.h>
#include "rvu.h"
#define PCI_DEVID_CN10K_MCS 0xA096
#define MCSX_LINK_LMAC_RANGE_MASK GENMASK_ULL(19, 16)
#define MCSX_LINK_LMAC_BASE_MASK GENMASK_ULL(11, 0)
#define MCS_ID_MASK 0x7
#define MCS_MAX_PFS 128
#define MCS_PORT_MODE_MASK 0x3
#define MCS_PORT_FIFO_SKID_MASK 0x3F
#define MCS_MAX_CUSTOM_TAGS 0x8
#define MCS_CTRLPKT_ETYPE_RULE_MAX 8
#define MCS_CTRLPKT_DA_RULE_MAX 8
#define MCS_CTRLPKT_DA_RANGE_RULE_MAX 4
#define MCS_CTRLPKT_COMBO_RULE_MAX 4
#define MCS_CTRLPKT_MAC_RULE_MAX 1
#define MCS_MAX_CTRLPKT_RULES (MCS_CTRLPKT_ETYPE_RULE_MAX + \
MCS_CTRLPKT_DA_RULE_MAX + \
MCS_CTRLPKT_DA_RANGE_RULE_MAX + \
MCS_CTRLPKT_COMBO_RULE_MAX + \
MCS_CTRLPKT_MAC_RULE_MAX)
#define MCS_CTRLPKT_ETYPE_RULE_OFFSET 0
#define MCS_CTRLPKT_DA_RULE_OFFSET 8
#define MCS_CTRLPKT_DA_RANGE_RULE_OFFSET 16
#define MCS_CTRLPKT_COMBO_RULE_OFFSET 20
#define MCS_CTRLPKT_MAC_EN_RULE_OFFSET 24
/* Reserved resources for default bypass entry */
#define MCS_RSRC_RSVD_CNT 1
/* MCS Interrupt Vector */
#define MCS_CNF10KB_INT_VEC_IP 0x13
#define MCS_CN10KB_INT_VEC_IP 0x53
#define MCS_MAX_BBE_INT 8ULL
#define MCS_BBE_INT_MASK 0xFFULL
#define MCS_MAX_PAB_INT 8ULL
#define MCS_PAB_INT_MASK 0xFULL
#define MCS_BBE_RX_INT_ENA BIT_ULL(0)
#define MCS_BBE_TX_INT_ENA BIT_ULL(1)
#define MCS_CPM_RX_INT_ENA BIT_ULL(2)
#define MCS_CPM_TX_INT_ENA BIT_ULL(3)
#define MCS_PAB_RX_INT_ENA BIT_ULL(4)
#define MCS_PAB_TX_INT_ENA BIT_ULL(5)
#define MCS_CPM_TX_INT_PACKET_XPN_EQ0 BIT_ULL(0)
#define MCS_CPM_TX_INT_PN_THRESH_REACHED BIT_ULL(1)
#define MCS_CPM_TX_INT_SA_NOT_VALID BIT_ULL(2)
#define MCS_CPM_RX_INT_SECTAG_V_EQ1 BIT_ULL(0)
#define MCS_CPM_RX_INT_SECTAG_E_EQ0_C_EQ1 BIT_ULL(1)
#define MCS_CPM_RX_INT_SL_GTE48 BIT_ULL(2)
#define MCS_CPM_RX_INT_ES_EQ1_SC_EQ1 BIT_ULL(3)
#define MCS_CPM_RX_INT_SC_EQ1_SCB_EQ1 BIT_ULL(4)
#define MCS_CPM_RX_INT_PACKET_XPN_EQ0 BIT_ULL(5)
#define MCS_CPM_RX_INT_PN_THRESH_REACHED BIT_ULL(6)
#define MCS_CPM_RX_INT_ALL (MCS_CPM_RX_INT_SECTAG_V_EQ1 | \
MCS_CPM_RX_INT_SECTAG_E_EQ0_C_EQ1 | \
MCS_CPM_RX_INT_SL_GTE48 | \
MCS_CPM_RX_INT_ES_EQ1_SC_EQ1 | \
MCS_CPM_RX_INT_SC_EQ1_SCB_EQ1 | \
MCS_CPM_RX_INT_PACKET_XPN_EQ0 | \
MCS_CPM_RX_INT_PN_THRESH_REACHED)
struct mcs_pfvf {
u64 intr_mask; /* Enabled Interrupt mask */
};
struct mcs_intr_event {
u16 pcifunc;
u64 intr_mask;
u64 sa_id;
u8 mcs_id;
u8 lmac_id;
};
struct mcs_intrq_entry {
struct list_head node;
struct mcs_intr_event intr_event;
};
struct secy_mem_map {
u8 flow_id;
u8 secy;
u8 ctrl_pkt;
u8 sc;
u64 sci;
};
struct mcs_rsrc_map {
u16 *flowid2pf_map;
u16 *secy2pf_map;
u16 *sc2pf_map;
u16 *sa2pf_map;
u16 *flowid2secy_map; /* bitmap flowid mapped to secy*/
u16 *ctrlpktrule2pf_map;
struct rsrc_bmap flow_ids;
struct rsrc_bmap secy;
struct rsrc_bmap sc;
struct rsrc_bmap sa;
struct rsrc_bmap ctrlpktrule;
};
struct hwinfo {
u8 tcam_entries;
u8 secy_entries;
u8 sc_entries;
u16 sa_entries;
u8 mcs_x2p_intf;
u8 lmac_cnt;
u8 mcs_blks;
unsigned long lmac_bmap; /* bitmap of enabled mcs lmac */
u16 ip_vec;
};
struct mcs {
void __iomem *reg_base;
struct pci_dev *pdev;
struct device *dev;
struct hwinfo *hw;
struct mcs_rsrc_map tx;
struct mcs_rsrc_map rx;
u16 pf_map[MCS_MAX_PFS]; /* List of PCIFUNC mapped to MCS */
u8 mcs_id;
struct mcs_ops *mcs_ops;
struct list_head mcs_list;
/* Lock for mcs stats */
struct mutex stats_lock;
struct mcs_pfvf *pf;
struct mcs_pfvf *vf;
u16 num_vec;
void *rvu;
u16 *tx_sa_active;
bool bypass;
};
struct mcs_ops {
void (*mcs_set_hw_capabilities)(struct mcs *mcs);
void (*mcs_parser_cfg)(struct mcs *mcs);
void (*mcs_tx_sa_mem_map_write)(struct mcs *mcs, struct mcs_tx_sc_sa_map *map);
void (*mcs_rx_sa_mem_map_write)(struct mcs *mcs, struct mcs_rx_sc_sa_map *map);
void (*mcs_flowid_secy_map)(struct mcs *mcs, struct secy_mem_map *map, int dir);
void (*mcs_bbe_intr_handler)(struct mcs *mcs, u64 intr, enum mcs_direction dir);
void (*mcs_pab_intr_handler)(struct mcs *mcs, u64 intr, enum mcs_direction dir);
};
extern struct pci_driver mcs_driver;
static inline void mcs_reg_write(struct mcs *mcs, u64 offset, u64 val)
{
writeq(val, mcs->reg_base + offset);
}
static inline u64 mcs_reg_read(struct mcs *mcs, u64 offset)
{
return readq(mcs->reg_base + offset);
}
/* MCS APIs */
struct mcs *mcs_get_pdata(int mcs_id);
int mcs_get_blkcnt(void);
int mcs_set_lmac_channels(int mcs_id, u16 base);
int mcs_alloc_rsrc(struct rsrc_bmap *rsrc, u16 *pf_map, u16 pcifunc);
int mcs_free_rsrc(struct rsrc_bmap *rsrc, u16 *pf_map, int rsrc_id, u16 pcifunc);
int mcs_alloc_all_rsrc(struct mcs *mcs, u8 *flowid, u8 *secy_id,
u8 *sc_id, u8 *sa1_id, u8 *sa2_id, u16 pcifunc, int dir);
int mcs_free_all_rsrc(struct mcs *mcs, int dir, u16 pcifunc);
void mcs_clear_secy_plcy(struct mcs *mcs, int secy_id, int dir);
void mcs_ena_dis_flowid_entry(struct mcs *mcs, int id, int dir, int ena);
void mcs_ena_dis_sc_cam_entry(struct mcs *mcs, int id, int ena);
void mcs_flowid_entry_write(struct mcs *mcs, u64 *data, u64 *mask, int id, int dir);
void mcs_secy_plcy_write(struct mcs *mcs, u64 plcy, int id, int dir);
void mcs_rx_sc_cam_write(struct mcs *mcs, u64 sci, u64 secy, int sc_id);
void mcs_sa_plcy_write(struct mcs *mcs, u64 *plcy, int sa, int dir);
void mcs_map_sc_to_sa(struct mcs *mcs, u64 *sa_map, int sc, int dir);
void mcs_pn_table_write(struct mcs *mcs, u8 pn_id, u64 next_pn, u8 dir);
void mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map);
void mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir);
void mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map);
void mcs_pn_threshold_set(struct mcs *mcs, struct mcs_set_pn_threshold *pn);
int mcs_install_flowid_bypass_entry(struct mcs *mcs);
void mcs_set_lmac_mode(struct mcs *mcs, int lmac_id, u8 mode);
void mcs_reset_port(struct mcs *mcs, u8 port_id, u8 reset);
void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req);
void mcs_get_port_cfg(struct mcs *mcs, struct mcs_port_cfg_get_req *req,
struct mcs_port_cfg_get_rsp *rsp);
void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *req,
struct mcs_custom_tag_cfg_get_rsp *rsp);
int mcs_alloc_ctrlpktrule(struct rsrc_bmap *rsrc, u16 *pf_map, u16 offset, u16 pcifunc);
int mcs_free_ctrlpktrule(struct mcs *mcs, struct mcs_free_ctrl_pkt_rule_req *req);
int mcs_ctrlpktrule_write(struct mcs *mcs, struct mcs_ctrl_pkt_rule_write_req *req);
bool is_mcs_bypass(int mcs_id);
/* CN10K-B APIs */
void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs);
void cn10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map);
void cn10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir);
void cn10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map);
void cn10kb_mcs_parser_cfg(struct mcs *mcs);
void cn10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir);
void cn10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir);
/* CNF10K-B APIs */
struct mcs_ops *cnf10kb_get_mac_ops(void);
void cnf10kb_mcs_set_hw_capabilities(struct mcs *mcs);
void cnf10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map);
void cnf10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir);
void cnf10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map);
void cnf10kb_mcs_parser_cfg(struct mcs *mcs);
void cnf10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs);
void cnf10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs);
void cnf10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir);
void cnf10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir);
/* Stats APIs */
void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats, int id, int dir);
void mcs_get_sa_stats(struct mcs *mcs, struct mcs_sa_stats *stats, int id, int dir);
void mcs_get_port_stats(struct mcs *mcs, struct mcs_port_stats *stats, int id, int dir);
void mcs_get_flowid_stats(struct mcs *mcs, struct mcs_flowid_stats *stats, int id, int dir);
void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id);
void mcs_get_tx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id);
void mcs_clear_stats(struct mcs *mcs, u8 type, u8 id, int dir);
int mcs_clear_all_stats(struct mcs *mcs, u16 pcifunc, int dir);
int mcs_set_force_clk_en(struct mcs *mcs, bool set);
int mcs_add_intr_wq_entry(struct mcs *mcs, struct mcs_intr_event *event);
#endif /* MCS_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
+277
View File
@@ -0,0 +1,277 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell MCS driver
*
* Copyright (C) 2022 Marvell.
*/
#include "mcs.h"
#include "mcs_reg.h"
static struct mcs_ops cnf10kb_mcs_ops = {
.mcs_set_hw_capabilities = cnf10kb_mcs_set_hw_capabilities,
.mcs_parser_cfg = cnf10kb_mcs_parser_cfg,
.mcs_tx_sa_mem_map_write = cnf10kb_mcs_tx_sa_mem_map_write,
.mcs_rx_sa_mem_map_write = cnf10kb_mcs_rx_sa_mem_map_write,
.mcs_flowid_secy_map = cnf10kb_mcs_flowid_secy_map,
.mcs_bbe_intr_handler = cnf10kb_mcs_bbe_intr_handler,
.mcs_pab_intr_handler = cnf10kb_mcs_pab_intr_handler,
};
struct mcs_ops *cnf10kb_get_mac_ops(void)
{
return &cnf10kb_mcs_ops;
}
void cnf10kb_mcs_set_hw_capabilities(struct mcs *mcs)
{
struct hwinfo *hw = mcs->hw;
hw->tcam_entries = 64; /* TCAM entries */
hw->secy_entries = 64; /* SecY entries */
hw->sc_entries = 64; /* SC CAM entries */
hw->sa_entries = 128; /* SA entries */
hw->lmac_cnt = 4; /* lmacs/ports per mcs block */
hw->mcs_x2p_intf = 1; /* x2p clabration intf */
hw->mcs_blks = 7; /* MCS blocks */
hw->ip_vec = MCS_CNF10KB_INT_VEC_IP; /* IP vector */
}
void cnf10kb_mcs_parser_cfg(struct mcs *mcs)
{
u64 reg, val;
/* VLAN Ctag */
val = (0x8100ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(22);
reg = MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(0);
mcs_reg_write(mcs, reg, val);
reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(0);
mcs_reg_write(mcs, reg, val);
/* VLAN STag */
val = (0x88a8ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(23);
/* RX */
reg = MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(1);
mcs_reg_write(mcs, reg, val);
/* TX */
reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(1);
mcs_reg_write(mcs, reg, val);
/* Enable custom tage 0 and 1 and sectag */
val = BIT_ULL(0) | BIT_ULL(1) | BIT_ULL(12);
reg = MCSX_PEX_RX_SLAVE_ETYPE_ENABLE;
mcs_reg_write(mcs, reg, val);
reg = MCSX_PEX_TX_SLAVE_ETYPE_ENABLE;
mcs_reg_write(mcs, reg, val);
}
void cnf10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir)
{
u64 reg, val;
val = (map->secy & 0x3F) | (map->ctrl_pkt & 0x1) << 6;
if (dir == MCS_RX) {
reg = MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(map->flow_id);
} else {
reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(map->flow_id);
mcs_reg_write(mcs, reg, map->sci);
val |= (map->sc & 0x3F) << 7;
reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_1X(map->flow_id);
}
mcs_reg_write(mcs, reg, val);
}
void cnf10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map)
{
u64 reg, val;
val = (map->sa_index0 & 0x7F) | (map->sa_index1 & 0x7F) << 7;
reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(map->sc_id);
mcs_reg_write(mcs, reg, val);
reg = MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0;
val = mcs_reg_read(mcs, reg);
if (map->rekey_ena)
val |= BIT_ULL(map->sc_id);
else
val &= ~BIT_ULL(map->sc_id);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(map->sc_id), map->sa_index0_vld);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(map->sc_id), map->sa_index1_vld);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(map->sc_id), map->tx_sa_active);
}
void cnf10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map)
{
u64 val, reg;
val = (map->sa_index & 0x7F) | (map->sa_in_use << 7);
reg = MCSX_CPM_RX_SLAVE_SA_MAP_MEMX((4 * map->sc_id) + map->an);
mcs_reg_write(mcs, reg, val);
}
int mcs_set_force_clk_en(struct mcs *mcs, bool set)
{
unsigned long timeout = jiffies + usecs_to_jiffies(2000);
u64 val;
val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL);
if (set) {
val |= BIT_ULL(4);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
/* Poll till mcsx_mil_ip_gbl_status.mcs_ip_stats_ready value is 1 */
while (!(mcs_reg_read(mcs, MCSX_MIL_IP_GBL_STATUS) & BIT_ULL(0))) {
if (time_after(jiffies, timeout)) {
dev_err(mcs->dev, "MCS set force clk enable failed\n");
break;
}
}
} else {
val &= ~BIT_ULL(4);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
}
return 0;
}
/* TX SA interrupt is raised only if autorekey is enabled.
* MCS_CPM_TX_SLAVE_SA_MAP_MEM_0X[sc].tx_sa_active bit gets toggled if
* one of two SAs mapped to SC gets expired. If tx_sa_active=0 implies
* SA in SA_index1 got expired else SA in SA_index0 got expired.
*/
void cnf10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs)
{
struct mcs_intr_event event;
struct rsrc_bmap *sc_bmap;
unsigned long rekey_ena;
u64 val, sa_status;
int sc;
sc_bmap = &mcs->tx.sc;
event.mcs_id = mcs->mcs_id;
event.intr_mask = MCS_CPM_TX_PN_THRESH_REACHED_INT;
rekey_ena = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0);
for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) {
/* Auto rekey is enable */
if (!test_bit(sc, &rekey_ena))
continue;
sa_status = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(sc));
/* Check if tx_sa_active status had changed */
if (sa_status == mcs->tx_sa_active[sc])
continue;
/* SA_index0 is expired */
val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc));
if (sa_status)
event.sa_id = val & 0x7F;
else
event.sa_id = (val >> 7) & 0x7F;
event.pcifunc = mcs->tx.sa2pf_map[event.sa_id];
mcs_add_intr_wq_entry(mcs, &event);
}
}
void cnf10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs)
{
struct mcs_intr_event event = { 0 };
struct rsrc_bmap *sc_bmap;
u64 val;
int sc;
sc_bmap = &mcs->tx.sc;
event.mcs_id = mcs->mcs_id;
event.intr_mask = MCS_CPM_TX_PACKET_XPN_EQ0_INT;
for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) {
val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc));
if (mcs->tx_sa_active[sc])
/* SA_index1 was used and got expired */
event.sa_id = (val >> 7) & 0x7F;
else
/* SA_index0 was used and got expired */
event.sa_id = val & 0x7F;
event.pcifunc = mcs->tx.sa2pf_map[event.sa_id];
mcs_add_intr_wq_entry(mcs, &event);
}
}
void cnf10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr,
enum mcs_direction dir)
{
struct mcs_intr_event event = { 0 };
int i;
if (!(intr & MCS_BBE_INT_MASK))
return;
event.mcs_id = mcs->mcs_id;
event.pcifunc = mcs->pf_map[0];
for (i = 0; i < MCS_MAX_BBE_INT; i++) {
if (!(intr & BIT_ULL(i)))
continue;
/* Lower nibble denotes data fifo overflow interrupts and
* upper nibble indicates policy fifo overflow interrupts.
*/
if (intr & 0xFULL)
event.intr_mask = (dir == MCS_RX) ?
MCS_BBE_RX_DFIFO_OVERFLOW_INT :
MCS_BBE_TX_DFIFO_OVERFLOW_INT;
else
event.intr_mask = (dir == MCS_RX) ?
MCS_BBE_RX_PLFIFO_OVERFLOW_INT :
MCS_BBE_TX_PLFIFO_OVERFLOW_INT;
/* Notify the lmac_id info which ran into BBE fatal error */
event.lmac_id = i & 0x3ULL;
mcs_add_intr_wq_entry(mcs, &event);
}
}
void cnf10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr,
enum mcs_direction dir)
{
struct mcs_intr_event event = { 0 };
int i;
if (!(intr & MCS_PAB_INT_MASK))
return;
event.mcs_id = mcs->mcs_id;
event.pcifunc = mcs->pf_map[0];
for (i = 0; i < MCS_MAX_PAB_INT; i++) {
if (!(intr & BIT_ULL(i)))
continue;
event.intr_mask = (dir == MCS_RX) ?
MCS_PAB_RX_CHAN_OVERFLOW_INT :
MCS_PAB_TX_CHAN_OVERFLOW_INT;
/* Notify the lmac_id info which ran into PAB fatal error */
event.lmac_id = i;
mcs_add_intr_wq_entry(mcs, &event);
}
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
+1129
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
+932
View File
@@ -0,0 +1,932 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell CN10K MCS driver
*
* Copyright (C) 2022 Marvell.
*/
#include <linux/types.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "mcs.h"
#include "rvu.h"
#include "mcs_reg.h"
#include "lmac_common.h"
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
static struct _req_type __maybe_unused \
*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
{ \
struct _req_type *req; \
\
req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
sizeof(struct _rsp_type)); \
if (!req) \
return NULL; \
req->hdr.sig = OTX2_MBOX_REQ_SIG; \
req->hdr.id = _id; \
return req; \
}
MBOX_UP_MCS_MESSAGES
#undef M
void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena)
{
struct mcs *mcs;
u64 cfg;
u8 port;
if (!rvu->mcs_blk_cnt)
return;
/* When ptp is enabled, RPM appends 8B header for all
* RX packets. MCS PEX need to configure to skip 8B
* during packet parsing.
*/
/* CNF10K-B */
if (rvu->mcs_blk_cnt > 1) {
mcs = mcs_get_pdata(rpm_id);
cfg = mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION);
if (ena)
cfg |= BIT_ULL(lmac_id);
else
cfg &= ~BIT_ULL(lmac_id);
mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, cfg);
return;
}
/* CN10KB */
mcs = mcs_get_pdata(0);
port = (rpm_id * rvu->hw->lmac_per_cgx) + lmac_id;
cfg = mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PORT_CFGX(port));
if (ena)
cfg |= BIT_ULL(0);
else
cfg &= ~BIT_ULL(0);
mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PORT_CFGX(port), cfg);
}
int rvu_mbox_handler_mcs_set_lmac_mode(struct rvu *rvu,
struct mcs_set_lmac_mode *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (BIT_ULL(req->lmac_id) & mcs->hw->lmac_bmap)
mcs_set_lmac_mode(mcs, req->lmac_id, req->mode);
return 0;
}
int mcs_add_intr_wq_entry(struct mcs *mcs, struct mcs_intr_event *event)
{
struct mcs_intrq_entry *qentry;
u16 pcifunc = event->pcifunc;
struct rvu *rvu = mcs->rvu;
struct mcs_pfvf *pfvf;
/* Check if it is PF or VF */
if (pcifunc & RVU_PFVF_FUNC_MASK)
pfvf = &mcs->vf[rvu_get_hwvf(rvu, pcifunc)];
else
pfvf = &mcs->pf[rvu_get_pf(rvu->pdev, pcifunc)];
event->intr_mask &= pfvf->intr_mask;
/* Check PF/VF interrupt notification is enabled */
if (!(pfvf->intr_mask && event->intr_mask))
return 0;
qentry = kmalloc_obj(*qentry, GFP_ATOMIC);
if (!qentry)
return -ENOMEM;
qentry->intr_event = *event;
spin_lock(&rvu->mcs_intrq_lock);
list_add_tail(&qentry->node, &rvu->mcs_intrq_head);
spin_unlock(&rvu->mcs_intrq_lock);
queue_work(rvu->mcs_intr_wq, &rvu->mcs_intr_work);
return 0;
}
static int mcs_notify_pfvf(struct mcs_intr_event *event, struct rvu *rvu)
{
struct mcs_intr_info *req;
int pf;
pf = rvu_get_pf(rvu->pdev, event->pcifunc);
mutex_lock(&rvu->mbox_lock);
req = otx2_mbox_alloc_msg_mcs_intr_notify(rvu, pf);
if (!req) {
mutex_unlock(&rvu->mbox_lock);
return -ENOMEM;
}
req->mcs_id = event->mcs_id;
req->intr_mask = event->intr_mask;
req->sa_id = event->sa_id;
req->hdr.pcifunc = event->pcifunc;
req->lmac_id = event->lmac_id;
otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf);
otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf);
otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pf);
mutex_unlock(&rvu->mbox_lock);
return 0;
}
static void mcs_intr_handler_task(struct work_struct *work)
{
struct rvu *rvu = container_of(work, struct rvu, mcs_intr_work);
struct mcs_intrq_entry *qentry;
struct mcs_intr_event *event;
unsigned long flags;
do {
spin_lock_irqsave(&rvu->mcs_intrq_lock, flags);
qentry = list_first_entry_or_null(&rvu->mcs_intrq_head,
struct mcs_intrq_entry,
node);
if (qentry)
list_del(&qentry->node);
spin_unlock_irqrestore(&rvu->mcs_intrq_lock, flags);
if (!qentry)
break; /* nothing more to process */
event = &qentry->intr_event;
mcs_notify_pfvf(event, rvu);
kfree(qentry);
} while (1);
}
int rvu_mbox_handler_mcs_intr_cfg(struct rvu *rvu,
struct mcs_intr_cfg *req,
struct msg_rsp *rsp)
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs_pfvf *pfvf;
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
/* Check if it is PF or VF */
if (pcifunc & RVU_PFVF_FUNC_MASK)
pfvf = &mcs->vf[rvu_get_hwvf(rvu, pcifunc)];
else
pfvf = &mcs->pf[rvu_get_pf(rvu->pdev, pcifunc)];
mcs->pf_map[0] = pcifunc;
pfvf->intr_mask = req->intr_mask;
return 0;
}
int rvu_mbox_handler_mcs_get_hw_info(struct rvu *rvu,
struct msg_req *req,
struct mcs_hw_info *rsp)
{
struct mcs *mcs;
if (!rvu->mcs_blk_cnt)
return MCS_AF_ERR_NOT_MAPPED;
/* MCS resources are same across all blocks */
mcs = mcs_get_pdata(0);
rsp->num_mcs_blks = rvu->mcs_blk_cnt;
rsp->tcam_entries = mcs->hw->tcam_entries;
rsp->secy_entries = mcs->hw->secy_entries;
rsp->sc_entries = mcs->hw->sc_entries;
rsp->sa_entries = mcs->hw->sa_entries;
return 0;
}
int rvu_mbox_handler_mcs_port_reset(struct rvu *rvu, struct mcs_port_reset_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_reset_port(mcs, req->port_id, req->reset);
return 0;
}
int rvu_mbox_handler_mcs_clear_stats(struct rvu *rvu,
struct mcs_clear_stats *req,
struct msg_rsp *rsp)
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mutex_lock(&mcs->stats_lock);
if (req->all)
mcs_clear_all_stats(mcs, pcifunc, req->dir);
else
mcs_clear_stats(mcs, req->type, req->id, req->dir);
mutex_unlock(&mcs->stats_lock);
return 0;
}
int rvu_mbox_handler_mcs_get_flowid_stats(struct rvu *rvu,
struct mcs_stats_req *req,
struct mcs_flowid_stats *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
/* In CNF10K-B, before reading the statistics,
* MCSX_MIL_GLOBAL.FORCE_CLK_EN_IP needs to be set
* to get accurate statistics
*/
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, true);
mutex_lock(&mcs->stats_lock);
mcs_get_flowid_stats(mcs, rsp, req->id, req->dir);
mutex_unlock(&mcs->stats_lock);
/* Clear MCSX_MIL_GLOBAL.FORCE_CLK_EN_IP after reading
* the statistics
*/
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, false);
return 0;
}
int rvu_mbox_handler_mcs_get_secy_stats(struct rvu *rvu,
struct mcs_stats_req *req,
struct mcs_secy_stats *rsp)
{ struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, true);
mutex_lock(&mcs->stats_lock);
if (req->dir == MCS_RX)
mcs_get_rx_secy_stats(mcs, rsp, req->id);
else
mcs_get_tx_secy_stats(mcs, rsp, req->id);
mutex_unlock(&mcs->stats_lock);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, false);
return 0;
}
int rvu_mbox_handler_mcs_get_sc_stats(struct rvu *rvu,
struct mcs_stats_req *req,
struct mcs_sc_stats *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, true);
mutex_lock(&mcs->stats_lock);
mcs_get_sc_stats(mcs, rsp, req->id, req->dir);
mutex_unlock(&mcs->stats_lock);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, false);
return 0;
}
int rvu_mbox_handler_mcs_get_sa_stats(struct rvu *rvu,
struct mcs_stats_req *req,
struct mcs_sa_stats *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, true);
mutex_lock(&mcs->stats_lock);
mcs_get_sa_stats(mcs, rsp, req->id, req->dir);
mutex_unlock(&mcs->stats_lock);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, false);
return 0;
}
int rvu_mbox_handler_mcs_get_port_stats(struct rvu *rvu,
struct mcs_stats_req *req,
struct mcs_port_stats *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, true);
mutex_lock(&mcs->stats_lock);
mcs_get_port_stats(mcs, rsp, req->id, req->dir);
mutex_unlock(&mcs->stats_lock);
if (mcs->hw->mcs_blks > 1)
mcs_set_force_clk_en(mcs, false);
return 0;
}
int rvu_mbox_handler_mcs_set_active_lmac(struct rvu *rvu,
struct mcs_set_active_lmac *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (!mcs)
return MCS_AF_ERR_NOT_MAPPED;
mcs->hw->lmac_bmap = req->lmac_bmap;
mcs_set_lmac_channels(req->mcs_id, req->chan_base);
return 0;
}
int rvu_mbox_handler_mcs_port_cfg_set(struct rvu *rvu, struct mcs_port_cfg_set_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (mcs->hw->lmac_cnt <= req->port_id || !(mcs->hw->lmac_bmap & BIT_ULL(req->port_id)))
return -EINVAL;
mcs_set_port_cfg(mcs, req);
return 0;
}
int rvu_mbox_handler_mcs_port_cfg_get(struct rvu *rvu, struct mcs_port_cfg_get_req *req,
struct mcs_port_cfg_get_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (mcs->hw->lmac_cnt <= req->port_id || !(mcs->hw->lmac_bmap & BIT_ULL(req->port_id)))
return -EINVAL;
mcs_get_port_cfg(mcs, req, rsp);
return 0;
}
int rvu_mbox_handler_mcs_custom_tag_cfg_get(struct rvu *rvu, struct mcs_custom_tag_cfg_get_req *req,
struct mcs_custom_tag_cfg_get_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_get_custom_tag_cfg(mcs, req, rsp);
return 0;
}
int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc)
{
struct mcs *mcs;
int mcs_id;
/* CNF10K-B mcs0-6 are mapped to RPM2-8*/
if (rvu->mcs_blk_cnt > 1) {
for (mcs_id = 0; mcs_id < rvu->mcs_blk_cnt; mcs_id++) {
mcs = mcs_get_pdata(mcs_id);
mcs_free_all_rsrc(mcs, MCS_RX, pcifunc);
mcs_free_all_rsrc(mcs, MCS_TX, pcifunc);
}
} else {
/* CN10K-B has only one mcs block */
mcs = mcs_get_pdata(0);
mcs_free_all_rsrc(mcs, MCS_RX, pcifunc);
mcs_free_all_rsrc(mcs, MCS_TX, pcifunc);
}
return 0;
}
int rvu_mbox_handler_mcs_flowid_ena_entry(struct rvu *rvu,
struct mcs_flowid_ena_dis_entry *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_ena_dis_flowid_entry(mcs, req->flow_id, req->dir, req->ena);
return 0;
}
int rvu_mbox_handler_mcs_pn_table_write(struct rvu *rvu,
struct mcs_pn_table_write_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_pn_table_write(mcs, req->pn_id, req->next_pn, req->dir);
return 0;
}
int rvu_mbox_handler_mcs_set_pn_threshold(struct rvu *rvu,
struct mcs_set_pn_threshold *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_pn_threshold_set(mcs, req);
return 0;
}
int rvu_mbox_handler_mcs_rx_sc_sa_map_write(struct rvu *rvu,
struct mcs_rx_sc_sa_map *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs->mcs_ops->mcs_rx_sa_mem_map_write(mcs, req);
return 0;
}
int rvu_mbox_handler_mcs_tx_sc_sa_map_write(struct rvu *rvu,
struct mcs_tx_sc_sa_map *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs->mcs_ops->mcs_tx_sa_mem_map_write(mcs, req);
mcs->tx_sa_active[req->sc_id] = req->tx_sa_active;
return 0;
}
int rvu_mbox_handler_mcs_sa_plcy_write(struct rvu *rvu,
struct mcs_sa_plcy_write_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
int i;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
for (i = 0; i < req->sa_cnt; i++)
mcs_sa_plcy_write(mcs, &req->plcy[i][0],
req->sa_index[i], req->dir);
return 0;
}
int rvu_mbox_handler_mcs_rx_sc_cam_write(struct rvu *rvu,
struct mcs_rx_sc_cam_write_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_rx_sc_cam_write(mcs, req->sci, req->secy_id, req->sc_id);
return 0;
}
int rvu_mbox_handler_mcs_secy_plcy_write(struct rvu *rvu,
struct mcs_secy_plcy_write_req *req,
struct msg_rsp *rsp)
{ struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mcs_secy_plcy_write(mcs, req->plcy,
req->secy_id, req->dir);
return 0;
}
int rvu_mbox_handler_mcs_flowid_entry_write(struct rvu *rvu,
struct mcs_flowid_entry_write_req *req,
struct msg_rsp *rsp)
{
struct secy_mem_map map;
struct mcs *mcs;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
/* TODO validate the flowid */
mcs_flowid_entry_write(mcs, req->data, req->mask,
req->flow_id, req->dir);
map.secy = req->secy_id;
map.sc = req->sc_id;
map.ctrl_pkt = req->ctrl_pkt;
map.flow_id = req->flow_id;
map.sci = req->sci;
mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, req->dir);
if (req->ena)
mcs_ena_dis_flowid_entry(mcs, req->flow_id,
req->dir, true);
return 0;
}
int rvu_mbox_handler_mcs_free_resources(struct rvu *rvu,
struct mcs_free_rsrc_req *req,
struct msg_rsp *rsp)
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs_rsrc_map *map;
struct mcs *mcs;
int rc = 0;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (req->dir == MCS_RX)
map = &mcs->rx;
else
map = &mcs->tx;
mutex_lock(&rvu->rsrc_lock);
/* Free all the cam resources mapped to PF/VF */
if (req->all) {
rc = mcs_free_all_rsrc(mcs, req->dir, pcifunc);
goto exit;
}
switch (req->rsrc_type) {
case MCS_RSRC_TYPE_FLOWID:
rc = mcs_free_rsrc(&map->flow_ids, map->flowid2pf_map, req->rsrc_id, pcifunc);
mcs_ena_dis_flowid_entry(mcs, req->rsrc_id, req->dir, false);
break;
case MCS_RSRC_TYPE_SECY:
rc = mcs_free_rsrc(&map->secy, map->secy2pf_map, req->rsrc_id, pcifunc);
mcs_clear_secy_plcy(mcs, req->rsrc_id, req->dir);
break;
case MCS_RSRC_TYPE_SC:
rc = mcs_free_rsrc(&map->sc, map->sc2pf_map, req->rsrc_id, pcifunc);
/* Disable SC CAM only on RX side */
if (req->dir == MCS_RX)
mcs_ena_dis_sc_cam_entry(mcs, req->rsrc_id, false);
break;
case MCS_RSRC_TYPE_SA:
rc = mcs_free_rsrc(&map->sa, map->sa2pf_map, req->rsrc_id, pcifunc);
break;
}
exit:
mutex_unlock(&rvu->rsrc_lock);
return rc;
}
int rvu_mbox_handler_mcs_alloc_resources(struct rvu *rvu,
struct mcs_alloc_rsrc_req *req,
struct mcs_alloc_rsrc_rsp *rsp)
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs_rsrc_map *map;
struct mcs *mcs;
int rsrc_id, i;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
if (req->dir == MCS_RX)
map = &mcs->rx;
else
map = &mcs->tx;
mutex_lock(&rvu->rsrc_lock);
if (req->all) {
rsrc_id = mcs_alloc_all_rsrc(mcs, &rsp->flow_ids[0],
&rsp->secy_ids[0],
&rsp->sc_ids[0],
&rsp->sa_ids[0],
&rsp->sa_ids[1],
pcifunc, req->dir);
goto exit;
}
switch (req->rsrc_type) {
case MCS_RSRC_TYPE_FLOWID:
for (i = 0; i < req->rsrc_cnt; i++) {
rsrc_id = mcs_alloc_rsrc(&map->flow_ids, map->flowid2pf_map, pcifunc);
if (rsrc_id < 0)
goto exit;
rsp->flow_ids[i] = rsrc_id;
rsp->rsrc_cnt++;
}
break;
case MCS_RSRC_TYPE_SECY:
for (i = 0; i < req->rsrc_cnt; i++) {
rsrc_id = mcs_alloc_rsrc(&map->secy, map->secy2pf_map, pcifunc);
if (rsrc_id < 0)
goto exit;
rsp->secy_ids[i] = rsrc_id;
rsp->rsrc_cnt++;
}
break;
case MCS_RSRC_TYPE_SC:
for (i = 0; i < req->rsrc_cnt; i++) {
rsrc_id = mcs_alloc_rsrc(&map->sc, map->sc2pf_map, pcifunc);
if (rsrc_id < 0)
goto exit;
rsp->sc_ids[i] = rsrc_id;
rsp->rsrc_cnt++;
}
break;
case MCS_RSRC_TYPE_SA:
for (i = 0; i < req->rsrc_cnt; i++) {
rsrc_id = mcs_alloc_rsrc(&map->sa, map->sa2pf_map, pcifunc);
if (rsrc_id < 0)
goto exit;
rsp->sa_ids[i] = rsrc_id;
rsp->rsrc_cnt++;
}
break;
}
rsp->rsrc_type = req->rsrc_type;
rsp->dir = req->dir;
rsp->mcs_id = req->mcs_id;
rsp->all = req->all;
exit:
if (rsrc_id < 0)
dev_err(rvu->dev, "Failed to allocate the mcs resources for PCIFUNC:%d\n", pcifunc);
mutex_unlock(&rvu->rsrc_lock);
return 0;
}
int rvu_mbox_handler_mcs_alloc_ctrl_pkt_rule(struct rvu *rvu,
struct mcs_alloc_ctrl_pkt_rule_req *req,
struct mcs_alloc_ctrl_pkt_rule_rsp *rsp)
{
u16 pcifunc = req->hdr.pcifunc;
struct mcs_rsrc_map *map;
struct mcs *mcs;
int rsrc_id;
u16 offset;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
map = (req->dir == MCS_RX) ? &mcs->rx : &mcs->tx;
mutex_lock(&rvu->rsrc_lock);
switch (req->rule_type) {
case MCS_CTRL_PKT_RULE_TYPE_ETH:
offset = MCS_CTRLPKT_ETYPE_RULE_OFFSET;
break;
case MCS_CTRL_PKT_RULE_TYPE_DA:
offset = MCS_CTRLPKT_DA_RULE_OFFSET;
break;
case MCS_CTRL_PKT_RULE_TYPE_RANGE:
offset = MCS_CTRLPKT_DA_RANGE_RULE_OFFSET;
break;
case MCS_CTRL_PKT_RULE_TYPE_COMBO:
offset = MCS_CTRLPKT_COMBO_RULE_OFFSET;
break;
case MCS_CTRL_PKT_RULE_TYPE_MAC:
offset = MCS_CTRLPKT_MAC_EN_RULE_OFFSET;
break;
}
rsrc_id = mcs_alloc_ctrlpktrule(&map->ctrlpktrule, map->ctrlpktrule2pf_map, offset,
pcifunc);
if (rsrc_id < 0)
goto exit;
rsp->rule_idx = rsrc_id;
rsp->rule_type = req->rule_type;
rsp->dir = req->dir;
rsp->mcs_id = req->mcs_id;
mutex_unlock(&rvu->rsrc_lock);
return 0;
exit:
if (rsrc_id < 0)
dev_err(rvu->dev, "Failed to allocate the mcs ctrl pkt rule for PCIFUNC:%d\n",
pcifunc);
mutex_unlock(&rvu->rsrc_lock);
return rsrc_id;
}
int rvu_mbox_handler_mcs_free_ctrl_pkt_rule(struct rvu *rvu,
struct mcs_free_ctrl_pkt_rule_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
int rc;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
mutex_lock(&rvu->rsrc_lock);
rc = mcs_free_ctrlpktrule(mcs, req);
mutex_unlock(&rvu->rsrc_lock);
return rc;
}
int rvu_mbox_handler_mcs_ctrl_pkt_rule_write(struct rvu *rvu,
struct mcs_ctrl_pkt_rule_write_req *req,
struct msg_rsp *rsp)
{
struct mcs *mcs;
int rc;
if (req->mcs_id >= rvu->mcs_blk_cnt)
return MCS_AF_ERR_INVALID_MCSID;
mcs = mcs_get_pdata(req->mcs_id);
rc = mcs_ctrlpktrule_write(mcs, req);
return rc;
}
static void rvu_mcs_set_lmac_bmap(struct rvu *rvu)
{
struct mcs *mcs = mcs_get_pdata(0);
unsigned long lmac_bmap;
int cgx, lmac, port;
for (port = 0; port < mcs->hw->lmac_cnt; port++) {
cgx = port / rvu->hw->lmac_per_cgx;
lmac = port % rvu->hw->lmac_per_cgx;
if (!is_lmac_valid(rvu_cgx_pdata(cgx, rvu), lmac))
continue;
set_bit(port, &lmac_bmap);
}
mcs->hw->lmac_bmap = lmac_bmap;
}
int rvu_mcs_init(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
int lmac, err = 0, mcs_id;
struct mcs *mcs;
rvu->mcs_blk_cnt = mcs_get_blkcnt();
if (!rvu->mcs_blk_cnt)
return 0;
/* Needed only for CN10K-B */
if (rvu->mcs_blk_cnt == 1) {
err = mcs_set_lmac_channels(0, hw->cgx_chan_base);
if (err)
return err;
/* Set active lmacs */
rvu_mcs_set_lmac_bmap(rvu);
}
/* Install default tcam bypass entry and set port to operational mode */
for (mcs_id = 0; mcs_id < rvu->mcs_blk_cnt; mcs_id++) {
mcs = mcs_get_pdata(mcs_id);
mcs_install_flowid_bypass_entry(mcs);
for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++)
mcs_set_lmac_mode(mcs, lmac, 0);
mcs->rvu = rvu;
/* Allocated memory for PFVF data */
mcs->pf = devm_kcalloc(mcs->dev, hw->total_pfs,
sizeof(struct mcs_pfvf), GFP_KERNEL);
if (!mcs->pf)
return -ENOMEM;
mcs->vf = devm_kcalloc(mcs->dev, hw->total_vfs,
sizeof(struct mcs_pfvf), GFP_KERNEL);
if (!mcs->vf)
return -ENOMEM;
}
/* Initialize the wq for handling mcs interrupts */
INIT_LIST_HEAD(&rvu->mcs_intrq_head);
INIT_WORK(&rvu->mcs_intr_work, mcs_intr_handler_task);
rvu->mcs_intr_wq = alloc_workqueue("mcs_intr_wq", WQ_PERCPU, 0);
if (!rvu->mcs_intr_wq) {
dev_err(rvu->dev, "mcs alloc workqueue failed\n");
return -ENOMEM;
}
return err;
}
void rvu_mcs_exit(struct rvu *rvu)
{
if (!rvu->mcs_intr_wq)
return;
destroy_workqueue(rvu->mcs_intr_wq);
rvu->mcs_intr_wq = NULL;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/npc.h
+669
View File
@@ -0,0 +1,669 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*
*/
#ifndef NPC_H
#define NPC_H
#define NPC_KEX_CHAN_MASK 0xFFFULL
#define SET_KEX_LD(intf, lid, ltype, ld, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
#define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
enum NPC_LID_E {
NPC_LID_LA = 0,
NPC_LID_LB,
NPC_LID_LC,
NPC_LID_LD,
NPC_LID_LE,
NPC_LID_LF,
NPC_LID_LG,
NPC_LID_LH,
};
#define NPC_LT_NA 0
enum npc_kpu_la_ltype {
NPC_LT_LA_8023 = 1,
NPC_LT_LA_ETHER,
NPC_LT_LA_IH_NIX_ETHER,
NPC_LT_LA_HIGIG2_ETHER = 7,
NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
NPC_LT_LA_CUSTOM_L2_90B_ETHER,
NPC_LT_LA_CPT_HDR,
NPC_LT_LA_CUSTOM_L2_24B_ETHER,
NPC_LT_LA_CUSTOM_PRE_L2_ETHER,
NPC_LT_LA_FP_ETHER,
NPC_LT_LA_CUSTOM0 = 0xE,
NPC_LT_LA_CUSTOM1 = 0xF,
};
enum npc_kpu_lb_ltype {
NPC_LT_LB_ETAG = 1,
NPC_LT_LB_CTAG,
NPC_LT_LB_STAG_QINQ,
NPC_LT_LB_BTAG,
NPC_LT_LB_PPPOE,
NPC_LT_LB_DSA,
NPC_LT_LB_DSA_VLAN,
NPC_LT_LB_EDSA,
NPC_LT_LB_EDSA_VLAN,
NPC_LT_LB_EXDSA,
NPC_LT_LB_EXDSA_VLAN,
NPC_LT_LB_FDSA,
NPC_LT_LB_VLAN_EXDSA,
NPC_LT_LB_CUSTOM0 = 0xE,
NPC_LT_LB_CUSTOM1 = 0xF,
};
/* Don't modify ltypes up to IP6_EXT, otherwise length and checksum of IP
* headers may not be checked correctly. IPv4 ltypes and IPv6 ltypes must
* differ only at bit 0 so mask 0xE can be used to detect extended headers.
*/
enum npc_kpu_lc_ltype {
NPC_LT_LC_PTP = 1,
NPC_LT_LC_IP,
NPC_LT_LC_IP_OPT,
NPC_LT_LC_IP6,
NPC_LT_LC_IP6_EXT,
NPC_LT_LC_ARP,
NPC_LT_LC_RARP,
NPC_LT_LC_MPLS,
NPC_LT_LC_NSH,
NPC_LT_LC_FCOE,
NPC_LT_LC_NGIO,
NPC_LT_LC_CUSTOM0 = 0xE,
NPC_LT_LC_CUSTOM1 = 0xF,
};
/* Don't modify Ltypes upto SCTP, otherwise it will
* effect flow tag calculation and thus RSS.
*/
enum npc_kpu_ld_ltype {
NPC_LT_LD_TCP = 1,
NPC_LT_LD_UDP,
NPC_LT_LD_SCTP = 4,
NPC_LT_LD_ICMP6,
NPC_LT_LD_CUSTOM0,
NPC_LT_LD_CUSTOM1,
NPC_LT_LD_IGMP = 8,
NPC_LT_LD_AH,
NPC_LT_LD_GRE,
NPC_LT_LD_NVGRE,
NPC_LT_LD_NSH,
NPC_LT_LD_TU_MPLS_IN_NSH,
NPC_LT_LD_TU_MPLS_IN_IP,
NPC_LT_LD_ICMP,
};
enum npc_kpu_le_ltype {
NPC_LT_LE_VXLAN = 1,
NPC_LT_LE_GENEVE,
NPC_LT_LE_ESP,
NPC_LT_LE_GTPU = 4,
NPC_LT_LE_VXLANGPE,
NPC_LT_LE_GTPC,
NPC_LT_LE_NSH,
NPC_LT_LE_TU_MPLS_IN_GRE,
NPC_LT_LE_TU_NSH_IN_GRE,
NPC_LT_LE_TU_MPLS_IN_UDP,
NPC_LT_LE_ROCEV2,
NPC_LT_LE_CUSTOM0 = 0xE,
NPC_LT_LE_CUSTOM1 = 0xF,
};
enum npc_kpu_lf_ltype {
NPC_LT_LF_TU_ETHER = 1,
NPC_LT_LF_TU_PPP,
NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
NPC_LT_LF_TU_NSH_IN_VXLANGPE,
NPC_LT_LF_TU_MPLS_IN_NSH,
NPC_LT_LF_TU_3RD_NSH,
NPC_LT_LF_CUSTOM0 = 0xE,
NPC_LT_LF_CUSTOM1 = 0xF,
};
enum npc_kpu_lg_ltype {
NPC_LT_LG_TU_IP = 1,
NPC_LT_LG_TU_IP6,
NPC_LT_LG_TU_ARP,
NPC_LT_LG_TU_ETHER_IN_NSH,
NPC_LT_LG_CUSTOM0 = 0xE,
NPC_LT_LG_CUSTOM1 = 0xF,
};
/* Don't modify Ltypes upto SCTP, otherwise it will
* effect flow tag calculation and thus RSS.
*/
enum npc_kpu_lh_ltype {
NPC_LT_LH_TU_TCP = 1,
NPC_LT_LH_TU_UDP,
NPC_LT_LH_TU_SCTP = 4,
NPC_LT_LH_TU_ICMP6,
NPC_LT_LH_CUSTOM0,
NPC_LT_LH_CUSTOM1,
NPC_LT_LH_TU_IGMP = 8,
NPC_LT_LH_TU_ESP,
NPC_LT_LH_TU_AH,
NPC_LT_LH_TU_ICMP = 0xF,
};
/* NPC port kind defines how the incoming or outgoing packets
* are processed. NPC accepts packets from up to 64 pkinds.
* Software assigns pkind for each incoming port such as CGX
* Ethernet interfaces, LBK interfaces, etc.
*/
#define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CPT_HDR_PTP_PKIND
enum npc_pkind_type {
NPC_RX_LBK_PKIND = 0ULL,
NPC_RX_CPT_HDR_PTP_PKIND = 54ULL,
NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
NPC_RX_CHLEN24B_PKIND = 57ULL,
NPC_RX_CPT_HDR_PKIND,
NPC_RX_CHLEN90B_PKIND,
NPC_TX_HIGIG_PKIND,
NPC_RX_HIGIG_PKIND,
NPC_RX_EDSA_PKIND,
NPC_TX_DEF_PKIND, /* NIX-TX PKIND */
};
enum npc_interface_type {
NPC_INTF_MODE_DEF,
};
/* list of known and supported fields in packet header and
* fields present in key structure.
*/
enum key_fields {
NPC_DMAC,
NPC_SMAC,
NPC_ETYPE,
NPC_VLAN_ETYPE_CTAG, /* 0x8100 */
NPC_VLAN_ETYPE_STAG, /* 0x88A8 */
NPC_OUTER_VID,
NPC_INNER_VID,
NPC_TOS,
NPC_IPFRAG_IPV4,
NPC_SIP_IPV4,
NPC_DIP_IPV4,
NPC_IPFRAG_IPV6,
NPC_SIP_IPV6,
NPC_DIP_IPV6,
NPC_IPPROTO_TCP,
NPC_IPPROTO_UDP,
NPC_IPPROTO_SCTP,
NPC_IPPROTO_AH,
NPC_IPPROTO_ESP,
NPC_IPPROTO_ICMP,
NPC_IPPROTO_ICMP6,
NPC_SPORT_TCP,
NPC_DPORT_TCP,
NPC_SPORT_UDP,
NPC_DPORT_UDP,
NPC_SPORT_SCTP,
NPC_DPORT_SCTP,
NPC_IPSEC_SPI,
NPC_MPLS1_LBTCBOS,
NPC_MPLS1_TTL,
NPC_MPLS2_LBTCBOS,
NPC_MPLS2_TTL,
NPC_MPLS3_LBTCBOS,
NPC_MPLS3_TTL,
NPC_MPLS4_LBTCBOS,
NPC_MPLS4_TTL,
NPC_TYPE_ICMP,
NPC_CODE_ICMP,
NPC_TCP_FLAGS,
NPC_HEADER_FIELDS_MAX,
NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */
NPC_PF_FUNC, /* Valid when Tx */
NPC_ERRLEV,
NPC_ERRCODE,
NPC_LXMB,
NPC_EXACT_RESULT,
NPC_LA,
NPC_LB,
NPC_LC,
NPC_LD,
NPC_LE,
NPC_LF,
NPC_LG,
NPC_LH,
/* Ethertype for untagged frame */
NPC_ETYPE_ETHER,
/* Ethertype for single tagged frame */
NPC_ETYPE_TAG1,
/* Ethertype for double tagged frame */
NPC_ETYPE_TAG2,
/* outer vlan tci for single tagged frame */
NPC_VLAN_TAG1,
/* outer vlan tci for double tagged frame */
NPC_VLAN_TAG2,
/* inner vlan tci for double tagged frame */
NPC_VLAN_TAG3,
/* other header fields programmed to extract but not of our interest */
NPC_UNKNOWN,
NPC_KEY_FIELDS_MAX,
};
struct npc_kpu_profile_cam {
u8 state;
u8 state_mask;
u16 dp0;
u16 dp0_mask;
u16 dp1;
u16 dp1_mask;
u16 dp2;
u16 dp2_mask;
} __packed;
struct npc_kpu_profile_cam2 {
u8 state;
u8 state_mask;
u16 dp0;
u16 dp0_mask;
u16 dp1;
u16 dp1_mask;
u16 dp2;
u16 dp2_mask;
u8 ptype;
u8 ptype_mask;
} __packed;
struct npc_kpu_profile_action {
u8 errlev;
u8 errcode;
u8 dp0_offset;
u8 dp1_offset;
u8 dp2_offset;
u8 bypass_count;
u8 parse_done;
u8 next_state;
u8 ptr_advance;
u8 cap_ena;
u8 lid;
u8 ltype;
u8 flags;
u8 offset;
u8 mask;
u8 right;
u8 shift;
} __packed;
struct npc_kpu_profile {
int cam_entries;
int action_entries;
struct npc_kpu_profile_cam *cam;
struct npc_kpu_profile_action *action;
int cam_entries2;
int action_entries2;
struct npc_kpu_profile_action *action2;
struct npc_kpu_profile_cam2 *cam2;
};
/* NPC KPU register formats */
struct npc_kpu_cam {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 rsvd_63_56 : 8;
u64 state : 8;
u64 dp2_data : 16;
u64 dp1_data : 16;
u64 dp0_data : 16;
#else
u64 dp0_data : 16;
u64 dp1_data : 16;
u64 dp2_data : 16;
u64 state : 8;
u64 rsvd_63_56 : 8;
#endif
};
struct npc_kpu_action0 {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 rsvd_63_57 : 7;
u64 byp_count : 3;
u64 capture_ena : 1;
u64 parse_done : 1;
u64 next_state : 8;
u64 rsvd_43 : 1;
u64 capture_lid : 3;
u64 capture_ltype : 4;
u64 capture_flags : 8;
u64 ptr_advance : 8;
u64 var_len_offset : 8;
u64 var_len_mask : 8;
u64 var_len_right : 1;
u64 var_len_shift : 3;
#else
u64 var_len_shift : 3;
u64 var_len_right : 1;
u64 var_len_mask : 8;
u64 var_len_offset : 8;
u64 ptr_advance : 8;
u64 capture_flags : 8;
u64 capture_ltype : 4;
u64 capture_lid : 3;
u64 rsvd_43 : 1;
u64 next_state : 8;
u64 parse_done : 1;
u64 capture_ena : 1;
u64 byp_count : 3;
u64 rsvd_63_57 : 7;
#endif
};
struct npc_kpu_action1 {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 rsvd_63_36 : 28;
u64 errlev : 4;
u64 errcode : 8;
u64 dp2_offset : 8;
u64 dp1_offset : 8;
u64 dp0_offset : 8;
#else
u64 dp0_offset : 8;
u64 dp1_offset : 8;
u64 dp2_offset : 8;
u64 errcode : 8;
u64 errlev : 4;
u64 rsvd_63_36 : 28;
#endif
};
struct npc_kpu_pkind_cpi_def {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 ena : 1;
u64 rsvd_62_59 : 4;
u64 lid : 3;
u64 ltype_match : 4;
u64 ltype_mask : 4;
u64 flags_match : 8;
u64 flags_mask : 8;
u64 add_offset : 8;
u64 add_mask : 8;
u64 rsvd_15 : 1;
u64 add_shift : 3;
u64 rsvd_11_10 : 2;
u64 cpi_base : 10;
#else
u64 cpi_base : 10;
u64 rsvd_11_10 : 2;
u64 add_shift : 3;
u64 rsvd_15 : 1;
u64 add_mask : 8;
u64 add_offset : 8;
u64 flags_mask : 8;
u64 flags_match : 8;
u64 ltype_mask : 4;
u64 ltype_match : 4;
u64 lid : 3;
u64 rsvd_62_59 : 4;
u64 ena : 1;
#endif
};
struct nix_rx_action {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 rsvd_63_61 :3;
u64 flow_key_alg :5;
u64 match_id :16;
u64 index :20;
u64 pf_func :16;
u64 op :4;
#else
u64 op :4;
u64 pf_func :16;
u64 index :20;
u64 match_id :16;
u64 flow_key_alg :5;
u64 rsvd_63_61 :3;
#endif
};
/* NPC_AF_INTFX_KEX_CFG field masks */
#define NPC_EXACT_NIBBLE_START 40
#define NPC_EXACT_NIBBLE_END 43
#define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)
/* NPC_EXACT_KEX_S nibble definitions for each field */
#define NPC_EXACT_NIBBLE_HIT BIT_ULL(40)
#define NPC_EXACT_NIBBLE_OPC BIT_ULL(40)
#define NPC_EXACT_NIBBLE_WAY BIT_ULL(40)
#define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)
#define NPC_EXACT_RESULT_HIT BIT_ULL(0)
#define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
#define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)
#define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)
/* NPC_AF_INTFX_KEX_CFG field masks */
#define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
#define NPC_TOTAL_NIBBLE 31
/* NPC_PARSE_KEX_S nibble definitions for each field */
#define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
#define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3)
#define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
#define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6)
#define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
#define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9)
#define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)
#define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12)
#define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13)
#define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15)
#define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16)
#define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18)
#define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19)
#define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21)
#define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22)
#define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24)
#define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25)
#define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27)
#define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28)
#define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30)
struct nix_tx_action {
#if defined(__BIG_ENDIAN_BITFIELD)
u64 rsvd_63_48 :16;
u64 match_id :16;
u64 index :20;
u64 rsvd_11_8 :8;
u64 op :4;
#else
u64 op :4;
u64 rsvd_11_8 :8;
u64 index :20;
u64 match_id :16;
u64 rsvd_63_48 :16;
#endif
};
/* NIX Receive Vtag Action Structure */
#define RX_VTAG0_VALID_BIT BIT_ULL(15)
#define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12)
#define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8)
#define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0)
#define RX_VTAG1_VALID_BIT BIT_ULL(47)
#define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44)
#define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40)
#define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32)
/* NIX Transmit Vtag Action Structure */
#define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16)
#define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12)
#define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8)
#define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0)
#define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48)
#define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44)
#define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40)
#define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32)
/* NPC MCAM reserved entry index per nixlf */
#define NIXLF_UCAST_ENTRY 0
#define NIXLF_BCAST_ENTRY 1
#define NIXLF_ALLMULTI_ENTRY 2
#define NIXLF_PROMISC_ENTRY 3
struct npc_coalesced_kpu_prfl {
#define NPC_SIGN 0x00666f727063706e
#define NPC_PRFL_NAME "npc_prfls_array"
#define NPC_NAME_LEN 32
__le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */
u8 name[NPC_NAME_LEN]; /* KPU Profile name */
u64 version; /* KPU firmware/profile version */
u8 num_prfl; /* No of NPC profiles. */
u16 prfl_sz[];
};
struct npc_mcam_kex {
/* MKEX Profle Header */
u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */
u64 cpu_model; /* Format as profiled by CPU hardware */
u64 kpu_version; /* KPU firmware/profile version */
u64 reserved; /* Reserved for extension */
/* MKEX Profle Data */
u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
u64 kex_ld_flags[NPC_MAX_LD];
/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
} __packed;
struct npc_kpu_fwdata {
int entries;
/* What follows is:
* struct npc_kpu_profile_cam[entries];
* struct npc_kpu_profile_action[entries];
*/
u8 data[];
} __packed;
struct npc_lt_def {
u8 ltype_mask;
u8 ltype_match;
u8 lid;
} __packed;
struct npc_lt_def_ipsec {
u8 ltype_mask;
u8 ltype_match;
u8 lid;
u8 spi_offset;
u8 spi_nz;
} __packed;
struct npc_lt_def_apad {
u8 ltype_mask;
u8 ltype_match;
u8 lid;
u8 valid;
} __packed;
struct npc_lt_def_color {
u8 ltype_mask;
u8 ltype_match;
u8 lid;
u8 noffset;
u8 offset;
} __packed;
struct npc_lt_def_et {
u8 ltype_mask;
u8 ltype_match;
u8 lid;
u8 valid;
u8 offset;
} __packed;
struct npc_lt_def_cfg {
struct npc_lt_def rx_ol2;
struct npc_lt_def rx_oip4;
struct npc_lt_def rx_iip4;
struct npc_lt_def rx_oip6;
struct npc_lt_def rx_iip6;
struct npc_lt_def rx_otcp;
struct npc_lt_def rx_itcp;
struct npc_lt_def rx_oudp;
struct npc_lt_def rx_iudp;
struct npc_lt_def rx_osctp;
struct npc_lt_def rx_isctp;
struct npc_lt_def_ipsec rx_ipsec[2];
struct npc_lt_def pck_ol2;
struct npc_lt_def pck_oip4;
struct npc_lt_def pck_oip6;
struct npc_lt_def pck_iip4;
struct npc_lt_def_apad rx_apad0;
struct npc_lt_def_apad rx_apad1;
struct npc_lt_def_color ovlan;
struct npc_lt_def_color ivlan;
struct npc_lt_def_color rx_gen0_color;
struct npc_lt_def_color rx_gen1_color;
struct npc_lt_def_et rx_et[2];
} __packed;
/* Loadable KPU profile firmware data */
struct npc_kpu_profile_fwdata {
#define KPU_SIGN 0x00666f727075706b
#define KPU_NAME_LEN 32
/** Maximum number of custom KPU entries supported by the built-in profile. */
#define KPU_MAX_CST_ENT 6
/* KPU Profle Header */
__le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */
u8 name[KPU_NAME_LEN]; /* KPU Profile name */
__le64 version; /* KPU profile version */
u8 kpus;
u8 reserved[7];
/* Default MKEX profile to be used with this KPU profile. May be
* overridden with mkex_profile module parameter. Format is same as for
* the MKEX profile to streamline processing.
*/
struct npc_mcam_kex mkex;
/* LTYPE values for specific HW offloaded protocols. */
struct npc_lt_def_cfg lt_def;
/* Dynamically sized data:
* Custom KPU CAM and ACTION configuration entries.
* struct npc_kpu_fwdata kpu[kpus];
*/
u8 data[];
} __packed;
struct rvu_npc_mcam_rule {
struct flow_msg packet;
struct flow_msg mask;
u8 intf;
union {
struct nix_tx_action tx_action;
struct nix_rx_action rx_action;
};
u64 vtag_action;
struct list_head list;
u64 features;
u16 owner;
u16 entry;
u16 cntr;
bool has_cntr;
u8 default_rule;
bool enable;
bool vfvlan_cfg;
u16 chan;
u16 chan_mask;
u8 lxmb;
u8 hw_prio;
};
#endif /* NPC_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
+16773
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
+676
View File
@@ -0,0 +1,676 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell PTP driver
*
* Copyright (C) 2020 Marvell.
*
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/hrtimer.h>
#include <linux/ktime.h>
#include "mbox.h"
#include "ptp.h"
#include "rvu.h"
#define DRV_NAME "Marvell PTP Driver"
#define PCI_DEVID_OCTEONTX2_PTP 0xA00C
#define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100
#define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200
#define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300
#define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP 0xB400
#define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500
#define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP 0xB600
#define PCI_DEVID_OCTEONTX2_RST 0xA085
#define PCI_DEVID_CN10K_PTP 0xA09E
#define PCI_SUBSYS_DEVID_CN10K_A_PTP 0xB900
#define PCI_SUBSYS_DEVID_CNF10K_A_PTP 0xBA00
#define PCI_SUBSYS_DEVID_CNF10K_B_PTP 0xBC00
#define PCI_PTP_BAR_NO 0
#define PTP_CLOCK_CFG 0xF00ULL
#define PTP_CLOCK_CFG_PTP_EN BIT_ULL(0)
#define PTP_CLOCK_CFG_EXT_CLK_EN BIT_ULL(1)
#define PTP_CLOCK_CFG_EXT_CLK_IN_MASK GENMASK_ULL(7, 2)
#define PTP_CLOCK_CFG_TSTMP_EDGE BIT_ULL(9)
#define PTP_CLOCK_CFG_TSTMP_EN BIT_ULL(8)
#define PTP_CLOCK_CFG_TSTMP_IN_MASK GENMASK_ULL(15, 10)
#define PTP_CLOCK_CFG_ATOMIC_OP_MASK GENMASK_ULL(28, 26)
#define PTP_CLOCK_CFG_PPS_EN BIT_ULL(30)
#define PTP_CLOCK_CFG_PPS_INV BIT_ULL(31)
#define PTP_PPS_HI_INCR 0xF60ULL
#define PTP_PPS_LO_INCR 0xF68ULL
#define PTP_PPS_THRESH_LO 0xF50ULL
#define PTP_PPS_THRESH_HI 0xF58ULL
#define PTP_CLOCK_LO 0xF08ULL
#define PTP_CLOCK_HI 0xF10ULL
#define PTP_CLOCK_COMP 0xF18ULL
#define PTP_TIMESTAMP 0xF20ULL
#define PTP_CLOCK_SEC 0xFD0ULL
#define PTP_SEC_ROLLOVER 0xFD8ULL
/* Atomic update related CSRs */
#define PTP_FRNS_TIMESTAMP 0xFE0ULL
#define PTP_NXT_ROLLOVER_SET 0xFE8ULL
#define PTP_CURR_ROLLOVER_SET 0xFF0ULL
#define PTP_NANO_TIMESTAMP 0xFF8ULL
#define PTP_SEC_TIMESTAMP 0x1000ULL
#define CYCLE_MULT 1000
#define is_rev_A0(ptp) (((ptp)->pdev->revision & 0x0F) == 0x0)
#define is_rev_A1(ptp) (((ptp)->pdev->revision & 0x0F) == 0x1)
/* PTP atomic update operation type */
enum atomic_opcode {
ATOMIC_SET = 1,
ATOMIC_INC = 3,
ATOMIC_DEC = 4
};
static struct ptp *first_ptp_block;
static const struct pci_device_id ptp_id_table[];
static bool is_ptp_dev_cnf10ka(struct ptp *ptp)
{
return ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A_PTP;
}
static bool is_ptp_dev_cn10ka(struct ptp *ptp)
{
return ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_PTP;
}
static bool cn10k_ptp_errata(struct ptp *ptp)
{
if ((is_ptp_dev_cn10ka(ptp) || is_ptp_dev_cnf10ka(ptp)) &&
(is_rev_A0(ptp) || is_rev_A1(ptp)))
return true;
return false;
}
static bool is_tstmp_atomic_update_supported(struct rvu *rvu)
{
struct ptp *ptp = rvu->ptp;
if (is_rvu_otx2(rvu))
return false;
/* On older silicon variants of CN10K, atomic update feature
* is not available.
*/
if ((is_ptp_dev_cn10ka(ptp) || is_ptp_dev_cnf10ka(ptp)) &&
(is_rev_A0(ptp) || is_rev_A1(ptp)))
return false;
return true;
}
static enum hrtimer_restart ptp_reset_thresh(struct hrtimer *hrtimer)
{
struct ptp *ptp = container_of(hrtimer, struct ptp, hrtimer);
ktime_t curr_ts = ktime_get();
ktime_t delta_ns, period_ns;
u64 ptp_clock_hi;
/* calculate the elapsed time since last restart */
delta_ns = ktime_to_ns(ktime_sub(curr_ts, ptp->last_ts));
/* if the ptp clock value has crossed 0.5 seconds,
* its too late to update pps threshold value, so
* update threshold after 1 second.
*/
ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI);
if (ptp_clock_hi > 500000000) {
period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - ptp_clock_hi));
} else {
writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI);
period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - delta_ns));
}
hrtimer_forward_now(hrtimer, period_ns);
ptp->last_ts = curr_ts;
return HRTIMER_RESTART;
}
static void ptp_hrtimer_start(struct ptp *ptp, ktime_t start_ns)
{
ktime_t period_ns;
period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - start_ns));
hrtimer_start(&ptp->hrtimer, period_ns, HRTIMER_MODE_REL);
ptp->last_ts = ktime_get();
}
static u64 read_ptp_tstmp_sec_nsec(struct ptp *ptp)
{
u64 sec, sec1, nsec;
unsigned long flags;
spin_lock_irqsave(&ptp->ptp_lock, flags);
sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL;
nsec = readq(ptp->reg_base + PTP_CLOCK_HI);
sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL;
/* check nsec rollover */
if (sec1 > sec) {
nsec = readq(ptp->reg_base + PTP_CLOCK_HI);
sec = sec1;
}
spin_unlock_irqrestore(&ptp->ptp_lock, flags);
return sec * NSEC_PER_SEC + nsec;
}
static u64 read_ptp_tstmp_nsec(struct ptp *ptp)
{
return readq(ptp->reg_base + PTP_CLOCK_HI);
}
static u64 ptp_calc_adjusted_comp(u64 ptp_clock_freq)
{
u64 comp, adj = 0, cycles_per_sec, ns_drift = 0;
u32 ptp_clock_nsec, cycle_time;
int cycle;
/* Errata:
* Issue #1: At the time of 1 sec rollover of the nano-second counter,
* the nano-second counter is set to 0. However, it should be set to
* (existing counter_value - 10^9).
*
* Issue #2: The nano-second counter rolls over at 0x3B9A_C9FF.
* It should roll over at 0x3B9A_CA00.
*/
/* calculate ptp_clock_comp value */
comp = ((u64)1000000000ULL << 32) / ptp_clock_freq;
/* use CYCLE_MULT to avoid accuracy loss due to integer arithmetic */
cycle_time = NSEC_PER_SEC * CYCLE_MULT / ptp_clock_freq;
/* cycles per sec */
cycles_per_sec = ptp_clock_freq;
/* check whether ptp nanosecond counter rolls over early */
cycle = cycles_per_sec - 1;
ptp_clock_nsec = (cycle * comp) >> 32;
while (ptp_clock_nsec < NSEC_PER_SEC) {
if (ptp_clock_nsec == 0x3B9AC9FF)
goto calc_adj_comp;
cycle++;
ptp_clock_nsec = (cycle * comp) >> 32;
}
/* compute nanoseconds lost per second when nsec counter rolls over */
ns_drift = ptp_clock_nsec - NSEC_PER_SEC;
/* calculate ptp_clock_comp adjustment */
if (ns_drift > 0) {
adj = comp * ns_drift;
adj = adj / 1000000000ULL;
}
/* speed up the ptp clock to account for nanoseconds lost */
comp += adj;
return comp;
calc_adj_comp:
/* slow down the ptp clock to not rollover early */
adj = comp * cycle_time;
adj = adj / 1000000000ULL;
adj = adj / CYCLE_MULT;
comp -= adj;
return comp;
}
struct ptp *ptp_get(void)
{
struct ptp *ptp = first_ptp_block;
/* Check PTP block is present in hardware */
if (!pci_dev_present(ptp_id_table))
return ERR_PTR(-ENODEV);
/* Check driver is bound to PTP block */
if (!ptp)
ptp = ERR_PTR(-EPROBE_DEFER);
else if (!IS_ERR(ptp))
pci_dev_get(ptp->pdev);
return ptp;
}
void ptp_put(struct ptp *ptp)
{
if (!ptp)
return;
pci_dev_put(ptp->pdev);
}
static void ptp_atomic_update(struct ptp *ptp, u64 timestamp)
{
u64 regval, curr_rollover_set, nxt_rollover_set;
/* First setup NSECs and SECs */
writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP);
writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);
writeq(timestamp / NSEC_PER_SEC,
ptp->reg_base + PTP_SEC_TIMESTAMP);
nxt_rollover_set = roundup(timestamp, NSEC_PER_SEC);
curr_rollover_set = nxt_rollover_set - NSEC_PER_SEC;
writeq(nxt_rollover_set, ptp->reg_base + PTP_NXT_ROLLOVER_SET);
writeq(curr_rollover_set, ptp->reg_base + PTP_CURR_ROLLOVER_SET);
/* Now, initiate atomic update */
regval = readq(ptp->reg_base + PTP_CLOCK_CFG);
regval &= ~PTP_CLOCK_CFG_ATOMIC_OP_MASK;
regval |= (ATOMIC_SET << 26);
writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);
}
static void ptp_atomic_adjtime(struct ptp *ptp, s64 delta)
{
bool neg_adj = false, atomic_inc_dec = false;
u64 regval, ptp_clock_hi;
if (delta < 0) {
delta = -delta;
neg_adj = true;
}
/* use atomic inc/dec when delta < 1 second */
if (delta < NSEC_PER_SEC)
atomic_inc_dec = true;
if (!atomic_inc_dec) {
ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI);
if (neg_adj) {
if (ptp_clock_hi > delta)
ptp_clock_hi -= delta;
else
ptp_clock_hi = delta - ptp_clock_hi;
} else {
ptp_clock_hi += delta;
}
ptp_atomic_update(ptp, ptp_clock_hi);
} else {
writeq(delta, ptp->reg_base + PTP_NANO_TIMESTAMP);
writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);
/* initiate atomic inc/dec */
regval = readq(ptp->reg_base + PTP_CLOCK_CFG);
regval &= ~PTP_CLOCK_CFG_ATOMIC_OP_MASK;
regval |= neg_adj ? (ATOMIC_DEC << 26) : (ATOMIC_INC << 26);
writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);
}
}
static int ptp_adjfine(struct ptp *ptp, long scaled_ppm)
{
bool neg_adj = false;
u32 freq, freq_adj;
u64 comp, adj;
s64 ppb;
if (scaled_ppm < 0) {
neg_adj = true;
scaled_ppm = -scaled_ppm;
}
/* The hardware adds the clock compensation value to the PTP clock
* on every coprocessor clock cycle. Typical convention is that it
* represent number of nanosecond betwen each cycle. In this
* convention compensation value is in 64 bit fixed-point
* representation where upper 32 bits are number of nanoseconds
* and lower is fractions of nanosecond.
* The scaled_ppm represent the ratio in "parts per million" by which
* the compensation value should be corrected.
* To calculate new compenstation value we use 64bit fixed point
* arithmetic on following formula
* comp = tbase + tbase * scaled_ppm / (1M * 2^16)
* where tbase is the basic compensation value calculated
* initialy in the probe function.
*/
/* convert scaled_ppm to ppb */
ppb = 1 + scaled_ppm;
ppb *= 125;
ppb >>= 13;
if (cn10k_ptp_errata(ptp)) {
/* calculate the new frequency based on ppb */
freq_adj = (ptp->clock_rate * ppb) / 1000000000ULL;
freq = neg_adj ? ptp->clock_rate + freq_adj : ptp->clock_rate - freq_adj;
comp = ptp_calc_adjusted_comp(freq);
} else {
comp = ((u64)1000000000ull << 32) / ptp->clock_rate;
adj = comp * ppb;
adj = div_u64(adj, 1000000000ull);
comp = neg_adj ? comp - adj : comp + adj;
}
writeq(comp, ptp->reg_base + PTP_CLOCK_COMP);
return 0;
}
static int ptp_get_clock(struct ptp *ptp, u64 *clk)
{
/* Return the current PTP clock */
*clk = ptp->read_ptp_tstmp(ptp);
return 0;
}
void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts)
{
struct ptp *ptp = rvu->ptp;
struct pci_dev *pdev;
u64 clock_comp;
u64 clock_cfg;
if (!ptp)
return;
pdev = ptp->pdev;
if (!sclk) {
dev_err(&pdev->dev, "PTP input clock cannot be zero\n");
return;
}
/* sclk is in MHz */
ptp->clock_rate = sclk * 1000000;
/* Program the seconds rollover value to 1 second */
if (is_tstmp_atomic_update_supported(rvu)) {
writeq(0, ptp->reg_base + PTP_NANO_TIMESTAMP);
writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);
writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP);
writeq(0, ptp->reg_base + PTP_CURR_ROLLOVER_SET);
writeq(0x3b9aca00, ptp->reg_base + PTP_NXT_ROLLOVER_SET);
writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER);
}
/* Enable PTP clock */
clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
if (ext_clk_freq) {
ptp->clock_rate = ext_clk_freq;
/* Set GPIO as PTP clock source */
clock_cfg &= ~PTP_CLOCK_CFG_EXT_CLK_IN_MASK;
clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN;
}
if (extts) {
clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE;
/* Set GPIO as timestamping source */
clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK;
clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN;
}
clock_cfg |= PTP_CLOCK_CFG_PTP_EN;
writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
clock_cfg &= ~PTP_CLOCK_CFG_ATOMIC_OP_MASK;
clock_cfg |= (ATOMIC_SET << 26);
writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
if (cn10k_ptp_errata(ptp))
clock_comp = ptp_calc_adjusted_comp(ptp->clock_rate);
else
clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate;
/* Initial compensation value to start the nanosecs counter */
writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);
}
static int ptp_get_tstmp(struct ptp *ptp, u64 *clk)
{
u64 timestamp;
if (is_ptp_dev_cn10ka(ptp) || is_ptp_dev_cnf10ka(ptp)) {
timestamp = readq(ptp->reg_base + PTP_TIMESTAMP);
*clk = (timestamp >> 32) * NSEC_PER_SEC + (timestamp & 0xFFFFFFFF);
} else {
*clk = readq(ptp->reg_base + PTP_TIMESTAMP);
}
return 0;
}
static int ptp_set_thresh(struct ptp *ptp, u64 thresh)
{
if (!cn10k_ptp_errata(ptp))
writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI);
return 0;
}
static int ptp_config_hrtimer(struct ptp *ptp, int on)
{
u64 ptp_clock_hi;
if (on) {
ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI);
ptp_hrtimer_start(ptp, (ktime_t)ptp_clock_hi);
} else {
if (hrtimer_active(&ptp->hrtimer))
hrtimer_cancel(&ptp->hrtimer);
}
return 0;
}
static int ptp_pps_on(struct ptp *ptp, int on, u64 period)
{
u64 clock_cfg;
clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
if (on) {
if (cn10k_ptp_errata(ptp) && period != NSEC_PER_SEC) {
dev_err(&ptp->pdev->dev, "Supports max period value as 1 second\n");
return -EINVAL;
}
if (period > (8 * NSEC_PER_SEC)) {
dev_err(&ptp->pdev->dev, "Supports max period as 8 seconds\n");
return -EINVAL;
}
clock_cfg |= PTP_CLOCK_CFG_PPS_EN | PTP_CLOCK_CFG_PPS_INV;
writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
writeq(0, ptp->reg_base + PTP_PPS_THRESH_HI);
writeq(0, ptp->reg_base + PTP_PPS_THRESH_LO);
/* Configure high/low phase time */
period = period / 2;
writeq(((u64)period << 32), ptp->reg_base + PTP_PPS_HI_INCR);
writeq(((u64)period << 32), ptp->reg_base + PTP_PPS_LO_INCR);
} else {
clock_cfg &= ~(PTP_CLOCK_CFG_PPS_EN | PTP_CLOCK_CFG_PPS_INV);
writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
}
if (on && cn10k_ptp_errata(ptp)) {
/* The ptp_clock_hi rollsover to zero once clock cycle before it
* reaches one second boundary. so, program the pps_lo_incr in
* such a way that the pps threshold value comparison at one
* second boundary will succeed and pps edge changes. After each
* one second boundary, the hrtimer handler will be invoked and
* reprograms the pps threshold value.
*/
ptp->clock_period = NSEC_PER_SEC / ptp->clock_rate;
writeq((0x1dcd6500ULL - ptp->clock_period) << 32,
ptp->reg_base + PTP_PPS_LO_INCR);
}
if (cn10k_ptp_errata(ptp))
ptp_config_hrtimer(ptp, on);
return 0;
}
static int ptp_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct ptp *ptp;
int err;
ptp = kzalloc_obj(*ptp);
if (!ptp) {
err = -ENOMEM;
goto error;
}
ptp->pdev = pdev;
err = pcim_enable_device(pdev);
if (err)
goto error_free;
err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev));
if (err)
goto error_free;
ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
pci_set_drvdata(pdev, ptp);
if (!first_ptp_block)
first_ptp_block = ptp;
spin_lock_init(&ptp->ptp_lock);
if (cn10k_ptp_errata(ptp)) {
ptp->read_ptp_tstmp = &read_ptp_tstmp_sec_nsec;
hrtimer_setup(&ptp->hrtimer, ptp_reset_thresh, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
} else {
ptp->read_ptp_tstmp = &read_ptp_tstmp_nsec;
}
return 0;
error_free:
kfree(ptp);
error:
/* For `ptp_get()` we need to differentiate between the case
* when the core has not tried to probe this device and the case when
* the probe failed. In the later case we keep the error in
* `dev->driver_data`.
*/
pci_set_drvdata(pdev, ERR_PTR(err));
if (!first_ptp_block)
first_ptp_block = ERR_PTR(err);
return err;
}
static void ptp_remove(struct pci_dev *pdev)
{
struct ptp *ptp = pci_get_drvdata(pdev);
u64 clock_cfg;
if (IS_ERR_OR_NULL(ptp))
return;
if (cn10k_ptp_errata(ptp) && hrtimer_active(&ptp->hrtimer))
hrtimer_cancel(&ptp->hrtimer);
/* Disable PTP clock */
clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
kfree(ptp);
}
static const struct pci_device_id ptp_id_table[] = {
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_98xx_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_96XX_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP) },
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_PTP) },
{ 0, }
};
struct pci_driver ptp_driver = {
.name = DRV_NAME,
.id_table = ptp_id_table,
.probe = ptp_probe,
.remove = ptp_remove,
};
int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req,
struct ptp_rsp *rsp)
{
int err = 0;
/* This function is the PTP mailbox handler invoked when
* called by AF consumers/netdev drivers via mailbox mechanism.
* It is used by netdev driver to get the PTP clock and to set
* frequency adjustments. Since mailbox can be called without
* notion of whether the driver is bound to ptp device below
* validation is needed as first step.
*/
if (!rvu->ptp)
return -ENODEV;
switch (req->op) {
case PTP_OP_ADJFINE:
err = ptp_adjfine(rvu->ptp, req->scaled_ppm);
break;
case PTP_OP_GET_CLOCK:
err = ptp_get_clock(rvu->ptp, &rsp->clk);
break;
case PTP_OP_GET_TSTMP:
err = ptp_get_tstmp(rvu->ptp, &rsp->clk);
break;
case PTP_OP_SET_THRESH:
err = ptp_set_thresh(rvu->ptp, req->thresh);
break;
case PTP_OP_PPS_ON:
err = ptp_pps_on(rvu->ptp, req->pps_on, req->period);
break;
case PTP_OP_ADJTIME:
ptp_atomic_adjtime(rvu->ptp, req->delta);
break;
case PTP_OP_SET_CLOCK:
ptp_atomic_update(rvu->ptp, (u64)req->clk);
break;
default:
err = -EINVAL;
break;
}
return err;
}
int rvu_mbox_handler_ptp_get_cap(struct rvu *rvu, struct msg_req *req,
struct ptp_get_cap_rsp *rsp)
{
if (!rvu->ptp)
return -ENODEV;
if (is_tstmp_atomic_update_supported(rvu))
rsp->cap |= PTP_CAP_HW_ATOMIC_UPDATE;
else
rsp->cap &= ~BIT_ULL_MASK(0);
return 0;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/ptp.h
+33
View File
@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell PTP driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef PTP_H
#define PTP_H
#include <linux/timecounter.h>
#include <linux/time64.h>
#include <linux/spinlock.h>
struct ptp {
struct pci_dev *pdev;
void __iomem *reg_base;
u64 (*read_ptp_tstmp)(struct ptp *ptp);
spinlock_t ptp_lock; /* lock */
struct hrtimer hrtimer;
ktime_t last_ts;
u32 clock_rate;
u32 clock_period;
};
struct rvu;
struct ptp *ptp_get(void);
void ptp_put(struct ptp *ptp);
void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts);
extern struct pci_driver ptp_driver;
#endif
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rpm.c
+812
View File
@@ -0,0 +1,812 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell CN10K RPM driver
*
* Copyright (C) 2020 Marvell.
*
*/
#include "cgx.h"
#include "lmac_common.h"
static struct mac_ops rpm_mac_ops = {
.name = "rpm",
.csr_offset = 0x4e00,
.lmac_offset = 20,
.int_register = RPMX_CMRX_SW_INT,
.int_set_reg = RPMX_CMRX_SW_INT_ENA_W1S,
.irq_offset = 1,
.int_ena_bit = BIT_ULL(0),
.lmac_fwi = RPM_LMAC_FWI,
.non_contiguous_serdes_lane = true,
.rx_stats_cnt = 43,
.tx_stats_cnt = 34,
.dmac_filter_count = 32,
.get_nr_lmacs = rpm_get_nr_lmacs,
.get_lmac_type = rpm_get_lmac_type,
.lmac_fifo_len = rpm_get_lmac_fifo_len,
.mac_lmac_intl_lbk = rpm_lmac_internal_loopback,
.mac_get_rx_stats = rpm_get_rx_stats,
.mac_get_tx_stats = rpm_get_tx_stats,
.get_fec_stats = rpm_get_fec_stats,
.mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding,
.mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status,
.mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm,
.mac_pause_frm_config = rpm_lmac_pause_frm_config,
.mac_enadis_ptp_config = rpm_lmac_ptp_config,
.mac_rx_tx_enable = rpm_lmac_rx_tx_enable,
.mac_tx_enable = rpm_lmac_tx_enable,
.pfc_config = rpm_lmac_pfc_config,
.mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg,
.mac_reset = rpm_lmac_reset,
.mac_stats_reset = rpm_stats_reset,
.mac_x2p_reset = rpm_x2p_reset,
.mac_enadis_rx = rpm_enadis_rx,
};
static struct mac_ops rpm2_mac_ops = {
.name = "rpm",
.csr_offset = RPM2_CSR_OFFSET,
.lmac_offset = 20,
.int_register = RPM2_CMRX_SW_INT,
.int_set_reg = RPM2_CMRX_SW_INT_ENA_W1S,
.irq_offset = 1,
.int_ena_bit = BIT_ULL(0),
.lmac_fwi = RPM2_LMAC_FWI,
.non_contiguous_serdes_lane = true,
.rx_stats_cnt = 43,
.tx_stats_cnt = 34,
.dmac_filter_count = 64,
.get_nr_lmacs = rpm2_get_nr_lmacs,
.get_lmac_type = rpm_get_lmac_type,
.lmac_fifo_len = rpm2_get_lmac_fifo_len,
.mac_lmac_intl_lbk = rpm_lmac_internal_loopback,
.mac_get_rx_stats = rpm_get_rx_stats,
.mac_get_tx_stats = rpm_get_tx_stats,
.get_fec_stats = rpm_get_fec_stats,
.mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding,
.mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status,
.mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm,
.mac_pause_frm_config = rpm_lmac_pause_frm_config,
.mac_enadis_ptp_config = rpm_lmac_ptp_config,
.mac_rx_tx_enable = rpm_lmac_rx_tx_enable,
.mac_tx_enable = rpm_lmac_tx_enable,
.pfc_config = rpm_lmac_pfc_config,
.mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg,
.mac_reset = rpm_lmac_reset,
.mac_stats_reset = rpm_stats_reset,
.mac_x2p_reset = rpm_x2p_reset,
.mac_enadis_rx = rpm_enadis_rx,
};
bool is_dev_rpm2(void *rpmd)
{
rpm_t *rpm = rpmd;
return (rpm->pdev->device == PCI_DEVID_CN10KB_RPM);
}
struct mac_ops *rpm_get_mac_ops(rpm_t *rpm)
{
if (is_dev_rpm2(rpm))
return &rpm2_mac_ops;
else
return &rpm_mac_ops;
}
static void rpm_write(rpm_t *rpm, u64 lmac, u64 offset, u64 val)
{
cgx_write(rpm, lmac, offset, val);
}
static u64 rpm_read(rpm_t *rpm, u64 lmac, u64 offset)
{
return cgx_read(rpm, lmac, offset);
}
/* Read HW major version to determine RPM
* MAC type 100/USX
*/
static bool is_mac_rpmusx(void *rpmd)
{
rpm_t *rpm = rpmd;
return rpm_read(rpm, 0, RPMX_CONST1) & 0x700ULL;
}
int rpm_get_nr_lmacs(void *rpmd)
{
rpm_t *rpm = rpmd;
return hweight8(rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS) & 0xFULL);
}
int rpm2_get_nr_lmacs(void *rpmd)
{
rpm_t *rpm = rpmd;
return hweight8(rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL);
}
int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable)
{
rpm_t *rpm = rpmd;
u64 cfg, last;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
last = cfg;
if (enable)
cfg |= RPM_TX_EN;
else
cfg &= ~(RPM_TX_EN);
if (cfg != last)
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
return !!(last & RPM_TX_EN);
}
int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
if (enable)
cfg |= RPM_RX_EN | RPM_TX_EN;
else
cfg &= ~(RPM_RX_EN | RPM_TX_EN);
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
return 0;
}
void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable)
{
rpm_t *rpm = rpmd;
struct lmac *lmac;
u64 cfg;
if (!rpm)
return;
lmac = lmac_pdata(lmac_id, rpm);
if (!lmac)
return;
/* Pause frames are not enabled just return */
if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
return;
if (enable) {
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
} else {
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
}
}
int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id,
u8 *tx_pause, u8 *rx_pause)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
if (!(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE)) {
*rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE);
*tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE);
}
return 0;
}
static void rpm_cfg_pfc_quanta_thresh(rpm_t *rpm, int lmac_id,
unsigned long pfc_en,
bool enable)
{
u64 quanta_offset = 0, quanta_thresh = 0, cfg;
int i, shift;
/* Set pause time and interval */
for_each_set_bit(i, &pfc_en, 16) {
switch (i) {
case 0:
case 1:
quanta_offset = RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL01_QUANTA_THRESH;
break;
case 2:
case 3:
quanta_offset = RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL23_QUANTA_THRESH;
break;
case 4:
case 5:
quanta_offset = RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL45_QUANTA_THRESH;
break;
case 6:
case 7:
quanta_offset = RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL67_QUANTA_THRESH;
break;
case 8:
case 9:
quanta_offset = RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL89_QUANTA_THRESH;
break;
case 10:
case 11:
quanta_offset = RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH;
break;
case 12:
case 13:
quanta_offset = RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH;
break;
case 14:
case 15:
quanta_offset = RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA;
quanta_thresh = RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH;
break;
}
if (!quanta_offset || !quanta_thresh)
continue;
shift = (i % 2) ? 1 : 0;
cfg = rpm_read(rpm, lmac_id, quanta_offset);
if (enable) {
cfg |= ((u64)RPM_DEFAULT_PAUSE_TIME << shift * 16);
} else {
if (!shift)
cfg &= ~GENMASK_ULL(15, 0);
else
cfg &= ~GENMASK_ULL(31, 16);
}
rpm_write(rpm, lmac_id, quanta_offset, cfg);
cfg = rpm_read(rpm, lmac_id, quanta_thresh);
if (enable) {
cfg |= ((u64)(RPM_DEFAULT_PAUSE_TIME / 2) << shift * 16);
} else {
if (!shift)
cfg &= ~GENMASK_ULL(15, 0);
else
cfg &= ~GENMASK_ULL(31, 16);
}
rpm_write(rpm, lmac_id, quanta_thresh, cfg);
}
}
static void rpm2_lmac_cfg_bp(rpm_t *rpm, int lmac_id, u8 tx_pause, u8 rx_pause)
{
u64 cfg;
cfg = rpm_read(rpm, lmac_id, RPM2_CMR_RX_OVR_BP);
if (tx_pause) {
/* Configure CL0 Pause Quanta & threshold
* for 802.3X frames
*/
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true);
cfg &= ~RPM2_CMR_RX_OVR_BP_EN;
} else {
/* Disable all Pause Quanta & threshold values */
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false);
cfg |= RPM2_CMR_RX_OVR_BP_EN;
cfg &= ~RPM2_CMR_RX_OVR_BP_BP;
}
rpm_write(rpm, lmac_id, RPM2_CMR_RX_OVR_BP, cfg);
}
static void rpm_lmac_cfg_bp(rpm_t *rpm, int lmac_id, u8 tx_pause, u8 rx_pause)
{
u64 cfg;
cfg = rpm_read(rpm, 0, RPMX_CMR_RX_OVR_BP);
if (tx_pause) {
/* Configure CL0 Pause Quanta & threshold for
* 802.3X frames
*/
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true);
cfg &= ~RPMX_CMR_RX_OVR_BP_EN(lmac_id);
} else {
/* Disable all Pause Quanta & threshold values */
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false);
cfg |= RPMX_CMR_RX_OVR_BP_EN(lmac_id);
cfg &= ~RPMX_CMR_RX_OVR_BP_BP(lmac_id);
}
rpm_write(rpm, 0, RPMX_CMR_RX_OVR_BP, cfg);
}
int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,
u8 rx_pause)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
cfg |= tx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
if (is_dev_rpm2(rpm))
rpm2_lmac_cfg_bp(rpm, lmac_id, tx_pause, rx_pause);
else
rpm_lmac_cfg_bp(rpm, lmac_id, tx_pause, rx_pause);
return 0;
}
void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
{
u64 cfg, pfc_class_mask_cfg;
rpm_t *rpm = rpmd;
/* ALL pause frames received are completely ignored */
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
/* Disable forward pause to TX block */
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
/* Disable pause frames transmission */
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
/* Disable forward pause to driver */
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
/* Enable channel mask for all LMACS */
if (is_dev_rpm2(rpm))
rpm_write(rpm, lmac_id, RPM2_CMR_CHAN_MSK_OR, 0xffff);
else
rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL);
/* Disable all PFC classes */
pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
RPMX_CMRX_PRT_CBFC_CTL;
cfg = rpm_read(rpm, lmac_id, pfc_class_mask_cfg);
cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg);
rpm_write(rpm, lmac_id, pfc_class_mask_cfg, cfg);
}
int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat)
{
rpm_t *rpm = rpmd;
u64 val_lo, val_hi;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
mutex_lock(&rpm->lock);
/* Update idx to point per lmac Rx statistics page */
idx += lmac_id * rpm->mac_ops->rx_stats_cnt;
/* Read lower 32 bits of counter */
val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX +
(idx * 8));
/* upon read of lower 32 bits, higher 32 bits are written
* to RPMX_MTI_STAT_DATA_HI_CDC
*/
val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
*rx_stat = (val_hi << 32 | val_lo);
mutex_unlock(&rpm->lock);
return 0;
}
int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat)
{
rpm_t *rpm = rpmd;
u64 val_lo, val_hi;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
mutex_lock(&rpm->lock);
/* Update idx to point per lmac Tx statistics page */
idx += lmac_id * rpm->mac_ops->tx_stats_cnt;
val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX +
(idx * 8));
val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
*tx_stat = (val_hi << 32 | val_lo);
mutex_unlock(&rpm->lock);
return 0;
}
int rpm_stats_reset(void *rpmd, int lmac_id)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, 0, RPMX_MTI_STAT_STATN_CONTROL);
cfg |= RPMX_CMD_CLEAR_TX | RPMX_CMD_CLEAR_RX | BIT_ULL(lmac_id);
rpm_write(rpm, 0, RPMX_MTI_STAT_STATN_CONTROL, cfg);
return 0;
}
u8 rpm_get_lmac_type(void *rpmd, int lmac_id)
{
rpm_t *rpm = rpmd;
u64 req = 0, resp;
int err;
req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req);
err = cgx_fwi_cmd_generic(req, &resp, rpm, lmac_id);
if (!err)
return FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, resp);
return err;
}
u32 rpm_get_lmac_fifo_len(void *rpmd, int lmac_id)
{
rpm_t *rpm = rpmd;
u64 hi_perf_lmac;
u8 num_lmacs;
u32 fifo_len;
fifo_len = rpm->fifo_len;
num_lmacs = rpm->mac_ops->get_nr_lmacs(rpm);
switch (num_lmacs) {
case 1:
return fifo_len;
case 2:
return fifo_len / 2;
case 3:
/* LMAC marked as hi_perf gets half of the FIFO and rest 1/4th */
hi_perf_lmac = rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS);
hi_perf_lmac = (hi_perf_lmac >> 4) & 0x3ULL;
if (lmac_id == hi_perf_lmac)
return fifo_len / 2;
return fifo_len / 4;
case 4:
default:
return fifo_len / 4;
}
return 0;
}
static int rpmusx_lmac_internal_loopback(rpm_t *rpm, int lmac_id, bool enable)
{
u64 cfg;
cfg = rpm_read(rpm, lmac_id, RPM2_USX_PCSX_CONTROL1);
if (enable)
cfg |= RPM2_USX_PCS_LBK;
else
cfg &= ~RPM2_USX_PCS_LBK;
rpm_write(rpm, lmac_id, RPM2_USX_PCSX_CONTROL1, cfg);
return 0;
}
u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id)
{
u64 hi_perf_lmac, lmac_info;
rpm_t *rpm = rpmd;
u8 num_lmacs;
u32 fifo_len;
u16 max_lmac;
lmac_info = rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS);
/* LMACs are divided into two groups and each group
* gets half of the FIFO
* Group0 lmac_id range {0..3}
* Group1 lmac_id range {4..7}
*/
max_lmac = (rpm_read(rpm, 0, CGX_CONST) >> 24) & 0xFF;
if (max_lmac > 4)
fifo_len = rpm->fifo_len / 2;
else
fifo_len = rpm->fifo_len;
if (lmac_id < 4) {
num_lmacs = hweight8(lmac_info & 0xF);
hi_perf_lmac = (lmac_info >> 8) & 0x3ULL;
} else {
num_lmacs = hweight8(lmac_info & 0xF0);
hi_perf_lmac = (lmac_info >> 10) & 0x3ULL;
hi_perf_lmac += 4;
}
switch (num_lmacs) {
case 1:
return fifo_len;
case 2:
return fifo_len / 2;
case 3:
/* LMAC marked as hi_perf gets half of the FIFO
* and rest 1/4th
*/
if (lmac_id == hi_perf_lmac)
return fifo_len / 2;
return fifo_len / 4;
case 4:
default:
return fifo_len / 4;
}
return 0;
}
int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable)
{
rpm_t *rpm = rpmd;
struct lmac *lmac;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
lmac = lmac_pdata(lmac_id, rpm);
if (lmac->lmac_type == LMAC_MODE_QSGMII ||
lmac->lmac_type == LMAC_MODE_SGMII) {
dev_err(&rpm->pdev->dev, "loopback not supported for LPC mode\n");
return 0;
}
if (is_dev_rpm2(rpm) && is_mac_rpmusx(rpm))
return rpmusx_lmac_internal_loopback(rpm, lmac_id, enable);
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1);
if (enable)
cfg |= RPMX_MTI_PCS_LBK;
else
cfg &= ~RPMX_MTI_PCS_LBK;
rpm_write(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1, cfg);
return 0;
}
void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return;
cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_CFG);
if (enable) {
cfg |= RPMX_RX_TS_PREPEND;
cfg |= RPMX_TX_PTP_1S_SUPPORT;
} else {
cfg &= ~RPMX_RX_TS_PREPEND;
cfg &= ~RPMX_TX_PTP_1S_SUPPORT;
}
rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg);
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE);
if (enable) {
cfg |= RPMX_ONESTEP_ENABLE;
cfg &= ~RPMX_TS_BINARY_MODE;
} else {
cfg &= ~RPMX_ONESTEP_ENABLE;
}
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE, cfg);
}
int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en)
{
u64 cfg, class_en, pfc_class_mask_cfg;
rpm_t *rpm = rpmd;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
RPMX_CMRX_PRT_CBFC_CTL;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
class_en = rpm_read(rpm, lmac_id, pfc_class_mask_cfg);
pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en);
if (rx_pause) {
cfg &= ~(RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |
RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE);
} else {
cfg |= (RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |
RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE);
}
if (tx_pause) {
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, pfc_en, true);
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
class_en = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, class_en);
} else {
rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xfff, false);
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
class_en = FIELD_SET(RPM_PFC_CLASS_MASK, 0, class_en);
}
if (!rx_pause && !tx_pause)
cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
else
cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en);
return 0;
}
int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, u8 *rx_pause)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
if (cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE) {
*rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE);
*tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE);
}
return 0;
}
int rpm_get_fec_stats(void *rpmd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
{
u64 val_lo, val_hi;
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE)
return 0;
/* latched registers FCFECX_CW_HI/RSFEC_STAT_FAST_DATA_HI_CDC are common
* for all counters. Acquire lock to ensure serialized reads
*/
mutex_lock(&rpm->lock);
if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
val_lo = rpm_read(rpm, 0, RPMX_MTI_FCFECX_VL0_CCW_LO(lmac_id));
val_hi = rpm_read(rpm, 0, RPMX_MTI_FCFECX_CW_HI(lmac_id));
rsp->fec_corr_blks = (val_hi << 16 | val_lo);
val_lo = rpm_read(rpm, 0, RPMX_MTI_FCFECX_VL0_NCCW_LO(lmac_id));
val_hi = rpm_read(rpm, 0, RPMX_MTI_FCFECX_CW_HI(lmac_id));
rsp->fec_uncorr_blks = (val_hi << 16 | val_lo);
/* 50G uses 2 Physical serdes lines */
if (rpm->lmac_idmap[lmac_id]->link_info.lmac_type_id ==
LMAC_MODE_50G_R) {
val_lo = rpm_read(rpm, 0,
RPMX_MTI_FCFECX_VL1_CCW_LO(lmac_id));
val_hi = rpm_read(rpm, 0,
RPMX_MTI_FCFECX_CW_HI(lmac_id));
rsp->fec_corr_blks += (val_hi << 16 | val_lo);
val_lo = rpm_read(rpm, 0,
RPMX_MTI_FCFECX_VL1_NCCW_LO(lmac_id));
val_hi = rpm_read(rpm, 0,
RPMX_MTI_FCFECX_CW_HI(lmac_id));
rsp->fec_uncorr_blks += (val_hi << 16 | val_lo);
}
} else {
/* enable RS-FEC capture */
cfg = rpm_read(rpm, 0, RPMX_MTI_RSFEC_STAT_STATN_CONTROL);
cfg |= RPMX_RSFEC_RX_CAPTURE | BIT(lmac_id);
rpm_write(rpm, 0, RPMX_MTI_RSFEC_STAT_STATN_CONTROL, cfg);
val_lo = rpm_read(rpm, 0,
RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2);
val_hi = rpm_read(rpm, 0, RPMX_MTI_RSFEC_STAT_FAST_DATA_HI_CDC);
rsp->fec_corr_blks = (val_hi << 32 | val_lo);
val_lo = rpm_read(rpm, 0,
RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3);
val_hi = rpm_read(rpm, 0, RPMX_MTI_RSFEC_STAT_FAST_DATA_HI_CDC);
rsp->fec_uncorr_blks = (val_hi << 32 | val_lo);
}
mutex_unlock(&rpm->lock);
return 0;
}
int rpm_lmac_reset(void *rpmd, int lmac_id, u8 pf_req_flr)
{
u64 rx_logl_xon, cfg;
rpm_t *rpm = rpmd;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
/* Resetting PFC related CSRs */
rx_logl_xon = is_dev_rpm2(rpm) ? RPM2_CMRX_RX_LOGL_XON :
RPMX_CMRX_RX_LOGL_XON;
cfg = 0xff;
rpm_write(rpm, lmac_id, rx_logl_xon, cfg);
if (pf_req_flr)
rpm_lmac_internal_loopback(rpm, lmac_id, false);
return 0;
}
void rpm_x2p_reset(void *rpmd, bool enable)
{
rpm_t *rpm = rpmd;
int lmac_id;
u64 cfg;
if (enable) {
for_each_set_bit(lmac_id, &rpm->lmac_bmap, rpm->max_lmac_per_mac)
rpm->mac_ops->mac_enadis_rx(rpm, lmac_id, false);
usleep_range(1000, 2000);
cfg = rpm_read(rpm, 0, RPMX_CMR_GLOBAL_CFG);
rpm_write(rpm, 0, RPMX_CMR_GLOBAL_CFG, cfg | RPM_NIX0_RESET);
} else {
cfg = rpm_read(rpm, 0, RPMX_CMR_GLOBAL_CFG);
cfg &= ~RPM_NIX0_RESET;
rpm_write(rpm, 0, RPMX_CMR_GLOBAL_CFG, cfg);
}
}
int rpm_enadis_rx(void *rpmd, int lmac_id, bool enable)
{
rpm_t *rpm = rpmd;
u64 cfg;
if (!is_lmac_valid(rpm, lmac_id))
return -ENODEV;
cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
if (enable)
cfg |= RPM_RX_EN;
else
cfg &= ~RPM_RX_EN;
rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
return 0;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rpm.h
+146
View File
@@ -0,0 +1,146 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell CN10K RPM driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef RPM_H
#define RPM_H
#include <linux/bits.h>
/* PCI device IDs */
#define PCI_DEVID_CN10K_RPM 0xA060
#define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
#define PCI_DEVID_CN10KB_RPM 0xA09F
/* Registers */
#define RPMX_CMRX_CFG 0x00
#define RPMX_CMR_GLOBAL_CFG 0x08
#define RPM_NIX0_RESET BIT_ULL(3)
#define RPMX_RX_TS_PREPEND BIT_ULL(22)
#define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
#define RPMX_CMRX_RX_ID_MAP 0x80
#define RPMX_CMRX_SW_INT 0x180
#define RPMX_CMRX_SW_INT_W1S 0x188
#define RPMX_CMRX_SW_INT_ENA_W1S 0x198
#define RPMX_CMRX_LINK_CFG 0x1070
#define RPMX_MTI_PCS100X_CONTROL1 0x20000
#define RPMX_MTI_PCS_LBK BIT_ULL(14)
#define RPMX_MTI_LPCSX_CONTROL(id) (0x30000 | ((id) * 0x100))
#define RPMX_CMRX_LINK_RANGE_MASK GENMASK_ULL(19, 16)
#define RPMX_CMRX_LINK_BASE_MASK GENMASK_ULL(11, 0)
#define RPMX_MTI_MAC100X_COMMAND_CONFIG 0x8010
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)
#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8
#define RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA 0x80B0
#define RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA 0x80B8
#define RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA 0x80C0
#define RPMX_MTI_MAC100X_CL01_QUANTA_THRESH 0x80C8
#define RPMX_MTI_MAC100X_CL23_QUANTA_THRESH 0x80D0
#define RPMX_MTI_MAC100X_CL45_QUANTA_THRESH 0x80D8
#define RPMX_MTI_MAC100X_CL67_QUANTA_THRESH 0x80E0
#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108
#define RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA 0x8110
#define RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA 0x8118
#define RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA 0x8120
#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128
#define RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH 0x8130
#define RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH 0x8138
#define RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH 0x8140
#define RPMX_CMR_RX_OVR_BP 0x4120
#define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)
#define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)
#define RPMX_CMR_CHAN_MSK_OR 0x4118
#define RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX 0x12000
#define RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX 0x13000
#define RPMX_MTI_STAT_DATA_HI_CDC 0x10038
#define RPM_LMAC_FWI 0xa
#define RPM_TX_EN BIT_ULL(0)
#define RPM_RX_EN BIT_ULL(1)
#define RPMX_CMRX_PRT_CBFC_CTL 0x5B08
#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_RX_SHIFT 33
#define RPMX_CMRX_PRT_CBFC_CTL_PHYS_BP_SHIFT 16
#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_TX_SHIFT 0
#define RPM_PFC_CLASS_MASK GENMASK_ULL(48, 33)
#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_PAD_EN BIT_ULL(11)
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD BIT_ULL(7)
#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8
#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108
#define RPM_DEFAULT_PAUSE_TIME 0x7FF
#define RPMX_CMRX_RX_LOGL_XON 0x4100
#define RPMX_MTI_MAC100X_XIF_MODE 0x8100
#define RPMX_ONESTEP_ENABLE BIT_ULL(5)
#define RPMX_TS_BINARY_MODE BIT_ULL(11)
#define RPMX_CONST1 0x2008
/* FEC stats */
#define RPMX_MTI_STAT_STATN_CONTROL 0x10018
#define RPMX_MTI_STAT_DATA_HI_CDC 0x10038
#define RPMX_RSFEC_RX_CAPTURE BIT_ULL(28)
#define RPMX_CMD_CLEAR_RX BIT_ULL(30)
#define RPMX_CMD_CLEAR_TX BIT_ULL(31)
#define RPMX_MTI_RSFEC_STAT_STATN_CONTROL 0x40018
#define RPMX_MTI_RSFEC_STAT_FAST_DATA_HI_CDC 0x40000
#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2 0x40050
#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3 0x40058
#define RPMX_MTI_FCFECX_VL0_CCW_LO(a) (0x38618 + ((a) * 0x40))
#define RPMX_MTI_FCFECX_VL0_NCCW_LO(a) (0x38620 + ((a) * 0x40))
#define RPMX_MTI_FCFECX_VL1_CCW_LO(a) (0x38628 + ((a) * 0x40))
#define RPMX_MTI_FCFECX_VL1_NCCW_LO(a) (0x38630 + ((a) * 0x40))
#define RPMX_MTI_FCFECX_CW_HI(a) (0x38638 + ((a) * 0x40))
/* CN10KB CSR Declaration */
#define RPM2_CMRX_SW_INT 0x1b0
#define RPM2_CMRX_SW_INT_ENA_W1S 0x1c8
#define RPM2_LMAC_FWI 0x12
#define RPM2_CMR_CHAN_MSK_OR 0x3120
#define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2)
#define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1)
#define RPM2_CMR_RX_OVR_BP 0x3130
#define RPM2_CSR_OFFSET 0x3e00
#define RPM2_CMRX_PRT_CBFC_CTL 0x6510
#define RPM2_CMRX_RX_LMACS 0x100
#define RPM2_CMRX_RX_LOGL_XON 0x3100
#define RPM2_CMRX_RX_STAT2 0x3010
#define RPM2_USX_PCSX_CONTROL1 0x80000
#define RPM2_USX_PCS_LBK BIT_ULL(14)
/* Function Declarations */
int rpm_get_nr_lmacs(void *rpmd);
u8 rpm_get_lmac_type(void *rpmd, int lmac_id);
u32 rpm_get_lmac_fifo_len(void *rpmd, int lmac_id);
u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id);
int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable);
void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable);
int rpm_lmac_get_pause_frm_status(void *cgxd, int lmac_id, u8 *tx_pause,
u8 *rx_pause);
void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable);
int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,
u8 rx_pause);
int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat);
int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat);
void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable);
int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable);
int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable);
int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause,
u16 pfc_en);
int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause,
u8 *rx_pause);
int rpm2_get_nr_lmacs(void *rpmd);
bool is_dev_rpm2(void *rpmd);
int rpm_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
int rpm_lmac_reset(void *rpmd, int lmac_id, u8 pf_req_flr);
int rpm_stats_reset(void *rpmd, int lmac_id);
void rpm_x2p_reset(void *rpmd, bool enable);
int rpm_enadis_rx(void *rpmd, int lmac_id, bool enable);
#endif /* RPM_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+3793
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+1201
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
+1436
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+593
View File
@@ -0,0 +1,593 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RPM CN10K driver
*
* Copyright (C) 2020 Marvell.
*/
#include <linux/bitfield.h>
#include <linux/pci.h>
#include "rvu.h"
#include "cgx.h"
#include "rvu_reg.h"
/* RVU LMTST */
#define LMT_TBL_OP_READ 0
#define LMT_TBL_OP_WRITE 1
#define LMT_MAPTBL_ENTRY_SIZE 16
#define LMT_MAX_VFS 256
#define LMT_MAP_ENTRY_ENA BIT_ULL(20)
#define LMT_MAP_ENTRY_LINES GENMASK_ULL(18, 16)
/* Function to perform operations (read/write) on lmtst map table */
static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
int lmt_tbl_op)
{
void __iomem *lmt_map_base;
u64 tbl_base, cfg;
int pfs, vfs;
tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
cfg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
vfs = 1 << (cfg & 0xF);
pfs = 1 << ((cfg >> 4) & 0x7);
lmt_map_base = ioremap_wc(tbl_base, pfs * vfs * LMT_MAPTBL_ENTRY_SIZE);
if (!lmt_map_base) {
dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
return -ENOMEM;
}
if (lmt_tbl_op == LMT_TBL_OP_READ) {
*val = readq(lmt_map_base + index);
} else {
writeq((*val), (lmt_map_base + index));
cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
/* 2048 LMTLINES */
cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
writeq(cfg, (lmt_map_base + (index + 8)));
/* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
* changes effective. Write 1 for flush and read is being used as a
* barrier and sets up a data dependency. Write to 0 after a write
* to 1 to complete the flush.
*/
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0));
rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL);
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, 0x00);
}
iounmap(lmt_map_base);
return 0;
}
#define LMT_MAP_TBL_W1_OFF 8
static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
{
return ((rvu_get_pf(rvu->pdev, pcifunc) * LMT_MAX_VFS) +
(pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;
}
static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc,
u64 iova, u64 *lmt_addr)
{
u64 pa, val, pf;
int err = 0;
if (!iova) {
dev_err(rvu->dev, "%s Requested Null address for transulation\n", __func__);
return -EINVAL;
}
mutex_lock(&rvu->rsrc_lock);
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova);
pf = rvu_get_pf(rvu->pdev, pcifunc) & RVU_OTX2_PFVF_PF_MASK;
val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 |
((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF);
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val);
err = rvu_poll_reg(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS, BIT_ULL(0), false);
if (err) {
dev_err(rvu->dev, "%s LMTLINE iova transulation failed\n", __func__);
goto exit;
}
val = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS);
if (val & ~0x1ULL) {
dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val);
err = -EIO;
goto exit;
}
/* PA[51:12] = RVU_AF_SMMU_TLN_FLIT0[57:18]
* PA[11:0] = IOVA[11:0]
*/
pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18;
pa &= GENMASK_ULL(39, 0);
*lmt_addr = (pa << 12) | (iova & 0xFFF);
exit:
mutex_unlock(&rvu->rsrc_lock);
return err;
}
static int rvu_update_lmtaddr(struct rvu *rvu, u16 pcifunc, u64 lmt_addr)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
u32 tbl_idx;
int err = 0;
u64 val;
/* Read the current lmt addr of pcifunc */
tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc);
err = lmtst_map_table_ops(rvu, tbl_idx, &val, LMT_TBL_OP_READ);
if (err) {
dev_err(rvu->dev,
"Failed to read LMT map table: index 0x%x err %d\n",
tbl_idx, err);
return err;
}
/* Storing the seondary's lmt base address as this needs to be
* reverted in FLR. Also making sure this default value doesn't
* get overwritten on multiple calls to this mailbox.
*/
if (!pfvf->lmt_base_addr)
pfvf->lmt_base_addr = val;
/* Update the LMT table with new addr */
err = lmtst_map_table_ops(rvu, tbl_idx, &lmt_addr, LMT_TBL_OP_WRITE);
if (err) {
dev_err(rvu->dev,
"Failed to update LMT map table: index 0x%x err %d\n",
tbl_idx, err);
return err;
}
return 0;
}
int rvu_mbox_handler_lmtst_tbl_setup(struct rvu *rvu,
struct lmtst_tbl_setup_req *req,
struct msg_rsp *rsp)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
u32 pri_tbl_idx, tbl_idx;
u64 lmt_addr;
int err = 0;
u64 val;
/* Check if PF_FUNC wants to use its own local memory as LMTLINE
* region, if so, convert that IOVA to physical address and
* populate LMT table with that address
*/
if (req->use_local_lmt_region) {
err = rvu_get_lmtaddr(rvu, req->hdr.pcifunc,
req->lmt_iova, &lmt_addr);
if (err < 0)
return err;
/* Update the lmt addr for this PFFUNC in the LMT table */
err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, lmt_addr);
if (err)
return err;
}
/* Reconfiguring lmtst map table in lmt region shared mode i.e. make
* multiple PF_FUNCs to share an LMTLINE region, so primary/base
* pcifunc (which is passed as an argument to mailbox) is the one
* whose lmt base address will be shared among other secondary
* pcifunc (will be the one who is calling this mailbox).
*/
if (req->base_pcifunc) {
/* A VF is untrusted and must not redirect its LMTLINE to
* another PF's region, so confine VF callers to their own PF.
*/
if (is_vf(req->hdr.pcifunc) &&
(!is_pf_func_valid(rvu, req->base_pcifunc) ||
rvu_get_pf(rvu->pdev, req->hdr.pcifunc) !=
rvu_get_pf(rvu->pdev, req->base_pcifunc)))
return -EPERM;
/* Calculating the LMT table index equivalent to primary
* pcifunc.
*/
pri_tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->base_pcifunc);
/* Read the base lmt addr of the primary pcifunc */
err = lmtst_map_table_ops(rvu, pri_tbl_idx, &val,
LMT_TBL_OP_READ);
if (err) {
dev_err(rvu->dev,
"Failed to read LMT map table: index 0x%x err %d\n",
pri_tbl_idx, err);
goto error;
}
/* Update the base lmt addr of secondary with primary's base
* lmt addr.
*/
err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, val);
if (err)
return err;
}
/* This mailbox can also be used to update word1 of APR_LMT_MAP_ENTRY_S
* like enabling scheduled LMTST, disable LMTLINE prefetch, disable
* early completion for ordered LMTST.
*/
if (req->sch_ena || req->dis_sched_early_comp || req->dis_line_pref) {
tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->hdr.pcifunc);
err = lmtst_map_table_ops(rvu, tbl_idx + LMT_MAP_TBL_W1_OFF,
&val, LMT_TBL_OP_READ);
if (err) {
dev_err(rvu->dev,
"Failed to read LMT map table: index 0x%x err %d\n",
tbl_idx + LMT_MAP_TBL_W1_OFF, err);
goto error;
}
/* Storing lmt map table entry word1 default value as this needs
* to be reverted in FLR. Also making sure this default value
* doesn't get overwritten on multiple calls to this mailbox.
*/
if (!pfvf->lmt_map_ent_w1)
pfvf->lmt_map_ent_w1 = val;
/* Disable early completion for Ordered LMTSTs. */
if (req->dis_sched_early_comp)
val |= (req->dis_sched_early_comp <<
APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT);
/* Enable scheduled LMTST */
if (req->sch_ena)
val |= (req->sch_ena << APR_LMT_MAP_ENT_SCH_ENA_SHIFT) |
req->ssow_pf_func;
/* Disables LMTLINE prefetch before receiving store data. */
if (req->dis_line_pref)
val |= (req->dis_line_pref <<
APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT);
err = lmtst_map_table_ops(rvu, tbl_idx + LMT_MAP_TBL_W1_OFF,
&val, LMT_TBL_OP_WRITE);
if (err) {
dev_err(rvu->dev,
"Failed to update LMT map table: index 0x%x err %d\n",
tbl_idx + LMT_MAP_TBL_W1_OFF, err);
goto error;
}
}
error:
return err;
}
/* Resetting the lmtst map table to original base addresses */
void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
u32 tbl_idx;
int err;
if (is_rvu_otx2(rvu))
return;
if (pfvf->lmt_base_addr || pfvf->lmt_map_ent_w1) {
/* This corresponds to lmt map table index */
tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc);
/* Reverting back original lmt base addr for respective
* pcifunc.
*/
if (pfvf->lmt_base_addr) {
err = lmtst_map_table_ops(rvu, tbl_idx,
&pfvf->lmt_base_addr,
LMT_TBL_OP_WRITE);
if (err)
dev_err(rvu->dev,
"Failed to update LMT map table: index 0x%x err %d\n",
tbl_idx, err);
pfvf->lmt_base_addr = 0;
}
/* Reverting back to orginal word1 val of lmtst map table entry
* which underwent changes.
*/
if (pfvf->lmt_map_ent_w1) {
err = lmtst_map_table_ops(rvu,
tbl_idx + LMT_MAP_TBL_W1_OFF,
&pfvf->lmt_map_ent_w1,
LMT_TBL_OP_WRITE);
if (err)
dev_err(rvu->dev,
"Failed to update LMT map table: index 0x%x err %d\n",
tbl_idx + LMT_MAP_TBL_W1_OFF, err);
pfvf->lmt_map_ent_w1 = 0;
}
}
}
int rvu_set_channels_base(struct rvu *rvu)
{
u16 nr_lbk_chans, nr_sdp_chans, nr_cgx_chans, nr_cpt_chans;
u16 sdp_chan_base, cgx_chan_base, cpt_chan_base;
struct rvu_hwinfo *hw = rvu->hw;
u64 nix_const, nix_const1;
int blkaddr;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
if (blkaddr < 0)
return blkaddr;
nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
hw->cgx = (nix_const >> 12) & 0xFULL;
hw->lmac_per_cgx = (nix_const >> 8) & 0xFULL;
hw->cgx_links = hw->cgx * hw->lmac_per_cgx;
hw->lbk_links = (nix_const >> 24) & 0xFULL;
hw->cpt_links = (nix_const >> 44) & 0xFULL;
hw->sdp_links = 1;
hw->cgx_chan_base = NIX_CHAN_CGX_LMAC_CHX(0, 0, 0);
hw->lbk_chan_base = NIX_CHAN_LBK_CHX(0, 0);
hw->sdp_chan_base = NIX_CHAN_SDP_CH_START;
/* No Programmable channels */
if (!(nix_const & BIT_ULL(60)))
return 0;
hw->cap.programmable_chans = true;
/* If programmable channels are present then configure
* channels such that all channel numbers are contiguous
* leaving no holes. This way the new CPT channels can be
* accomodated. The order of channel numbers assigned is
* LBK, SDP, CGX and CPT. Also the base channel number
* of a block must be multiple of number of channels
* of the block.
*/
nr_lbk_chans = (nix_const >> 16) & 0xFFULL;
nr_sdp_chans = nix_const1 & 0xFFFULL;
nr_cgx_chans = nix_const & 0xFFULL;
nr_cpt_chans = (nix_const >> 32) & 0xFFFULL;
sdp_chan_base = hw->lbk_chan_base + hw->lbk_links * nr_lbk_chans;
/* Round up base channel to multiple of number of channels */
hw->sdp_chan_base = ALIGN(sdp_chan_base, nr_sdp_chans);
cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * nr_sdp_chans;
hw->cgx_chan_base = ALIGN(cgx_chan_base, nr_cgx_chans);
cpt_chan_base = hw->cgx_chan_base + hw->cgx_links * nr_cgx_chans;
hw->cpt_chan_base = ALIGN(cpt_chan_base, nr_cpt_chans);
/* Out of 4096 channels start CPT from 2048 so
* that MSB for CPT channels is always set
*/
if (cpt_chan_base <= NIX_CHAN_CPT_CH_START) {
hw->cpt_chan_base = NIX_CHAN_CPT_CH_START;
} else {
dev_err(rvu->dev,
"CPT channels could not fit in the range 2048-4095\n");
return -EINVAL;
}
return 0;
}
#define LBK_CONNECT_NIXX(a) (0x0 + (a))
static void __rvu_lbk_set_chans(struct rvu *rvu, void __iomem *base,
u64 offset, int lbkid, u16 chans)
{
struct rvu_hwinfo *hw = rvu->hw;
u64 cfg;
cfg = readq(base + offset);
cfg &= ~(LBK_LINK_CFG_RANGE_MASK |
LBK_LINK_CFG_ID_MASK | LBK_LINK_CFG_BASE_MASK);
cfg |= FIELD_PREP(LBK_LINK_CFG_RANGE_MASK, ilog2(chans));
cfg |= FIELD_PREP(LBK_LINK_CFG_ID_MASK, lbkid);
cfg |= FIELD_PREP(LBK_LINK_CFG_BASE_MASK, hw->lbk_chan_base);
writeq(cfg, base + offset);
}
static void rvu_lbk_set_channels(struct rvu *rvu)
{
struct pci_dev *pdev = NULL;
void __iomem *base;
u64 lbk_const;
u8 src, dst;
u16 chans;
/* To loopback packets between multiple NIX blocks
* mutliple LBK blocks are needed. With two NIX blocks,
* four LBK blocks are needed and each LBK block
* source and destination are as follows:
* LBK0 - source NIX0 and destination NIX1
* LBK1 - source NIX0 and destination NIX1
* LBK2 - source NIX1 and destination NIX0
* LBK3 - source NIX1 and destination NIX1
* As per the HRM channel numbers should be programmed as:
* P2X and X2P of LBK0 as same
* P2X and X2P of LBK3 as same
* P2X of LBK1 and X2P of LBK2 as same
* P2X of LBK2 and X2P of LBK1 as same
*/
while (true) {
pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVID_OCTEONTX2_LBK, pdev);
if (!pdev)
return;
base = pci_ioremap_bar(pdev, 0);
if (!base)
goto err_put;
lbk_const = readq(base + LBK_CONST);
chans = FIELD_GET(LBK_CONST_CHANS, lbk_const);
dst = FIELD_GET(LBK_CONST_DST, lbk_const);
src = FIELD_GET(LBK_CONST_SRC, lbk_const);
if (src == dst) {
if (src == LBK_CONNECT_NIXX(0)) { /* LBK0 */
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
0, chans);
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
0, chans);
} else if (src == LBK_CONNECT_NIXX(1)) { /* LBK3 */
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
1, chans);
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
1, chans);
}
} else {
if (src == LBK_CONNECT_NIXX(0)) { /* LBK1 */
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
0, chans);
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
1, chans);
} else if (src == LBK_CONNECT_NIXX(1)) { /* LBK2 */
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
1, chans);
__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
0, chans);
}
}
iounmap(base);
}
err_put:
pci_dev_put(pdev);
}
static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr)
{
u64 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
u64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
u16 cgx_chans, lbk_chans, sdp_chans, cpt_chans;
struct rvu_hwinfo *hw = rvu->hw;
int link, nix_link = 0;
u16 start;
u64 cfg;
cgx_chans = nix_const & 0xFFULL;
lbk_chans = (nix_const >> 16) & 0xFFULL;
sdp_chans = nix_const1 & 0xFFFULL;
cpt_chans = (nix_const >> 32) & 0xFFFULL;
start = hw->cgx_chan_base;
for (link = 0; link < hw->cgx_links; link++, nix_link++) {
cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cgx_chans));
cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
start += cgx_chans;
}
start = hw->lbk_chan_base;
for (link = 0; link < hw->lbk_links; link++, nix_link++) {
cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(lbk_chans));
cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
start += lbk_chans;
}
start = hw->sdp_chan_base;
for (link = 0; link < hw->sdp_links; link++, nix_link++) {
cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(sdp_chans));
cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
start += sdp_chans;
}
start = hw->cpt_chan_base;
for (link = 0; link < hw->cpt_links; link++, nix_link++) {
cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cpt_chans));
cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
start += cpt_chans;
}
}
static void rvu_nix_set_channels(struct rvu *rvu)
{
int blkaddr = 0;
blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
while (blkaddr) {
__rvu_nix_set_channels(rvu, blkaddr);
blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
}
}
static void __rvu_rpm_set_channels(int cgxid, int lmacid, u16 base)
{
u64 cfg;
cfg = cgx_lmac_read(cgxid, lmacid, RPMX_CMRX_LINK_CFG);
cfg &= ~(RPMX_CMRX_LINK_BASE_MASK | RPMX_CMRX_LINK_RANGE_MASK);
/* There is no read-only constant register to read
* the number of channels for LMAC and it is always 16.
*/
cfg |= FIELD_PREP(RPMX_CMRX_LINK_RANGE_MASK, ilog2(16));
cfg |= FIELD_PREP(RPMX_CMRX_LINK_BASE_MASK, base);
cgx_lmac_write(cgxid, lmacid, RPMX_CMRX_LINK_CFG, cfg);
}
static void rvu_rpm_set_channels(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
u16 base = hw->cgx_chan_base;
int cgx, lmac;
for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) {
for (lmac = 0; lmac < hw->lmac_per_cgx; lmac++) {
__rvu_rpm_set_channels(cgx, lmac, base);
base += 16;
}
}
}
void rvu_program_channels(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
if (!hw->cap.programmable_chans)
return;
rvu_nix_set_channels(rvu);
rvu_lbk_set_channels(rvu);
rvu_rpm_set_channels(rvu);
}
void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw)
{
int blkaddr = nix_hw->blkaddr;
u64 cfg;
/* Set AF vWQE timer interval to a LF configurable range of
* 6.4us to 1.632ms.
*/
rvu_write64(rvu, blkaddr, NIX_AF_VWQE_TIMER, 0x3FULL);
/* Enable NIX RX stream and global conditional clock to
* avoild multiple free of NPA buffers.
*/
cfg = rvu_read64(rvu, blkaddr, NIX_AF_CFG);
cfg |= BIT_ULL(1) | BIT_ULL(2);
rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg);
}
void rvu_apr_block_cn10k_init(struct rvu *rvu)
{
u64 reg;
reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
reg |= FIELD_PREP(LMTST_THROTTLE_MASK, LMTST_WR_PEND_MAX);
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg);
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+1319
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
+4065
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
+1813
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.h
+82
View File
@@ -0,0 +1,82 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function Devlink
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef RVU_DEVLINK_H
#define RVU_DEVLINK_H
#define RVU_REPORTERS(_name) \
static const struct devlink_health_reporter_ops rvu_ ## _name ## _reporter_ops = { \
.name = #_name, \
.recover = rvu_ ## _name ## _recover, \
.dump = rvu_ ## _name ## _dump, \
}
enum npa_af_rvu_health {
NPA_AF_RVU_INTR,
NPA_AF_RVU_GEN,
NPA_AF_RVU_ERR,
NPA_AF_RVU_RAS,
};
struct rvu_npa_event_ctx {
u64 npa_af_rvu_int;
u64 npa_af_rvu_gen;
u64 npa_af_rvu_err;
u64 npa_af_rvu_ras;
};
struct rvu_npa_health_reporters {
struct rvu_npa_event_ctx *npa_event_ctx;
struct devlink_health_reporter *rvu_hw_npa_intr_reporter;
struct work_struct intr_work;
struct devlink_health_reporter *rvu_hw_npa_gen_reporter;
struct work_struct gen_work;
struct devlink_health_reporter *rvu_hw_npa_err_reporter;
struct work_struct err_work;
struct devlink_health_reporter *rvu_hw_npa_ras_reporter;
struct work_struct ras_work;
};
enum nix_af_rvu_health {
NIX_AF_RVU_INTR,
NIX_AF_RVU_GEN,
NIX_AF_RVU_ERR,
NIX_AF_RVU_RAS,
};
struct rvu_nix_event_ctx {
u64 nix_af_rvu_int;
u64 nix_af_rvu_gen;
u64 nix_af_rvu_err;
u64 nix_af_rvu_ras;
};
struct rvu_nix_health_reporters {
struct rvu_nix_event_ctx *nix_event_ctx;
struct devlink_health_reporter *rvu_hw_nix_intr_reporter;
struct work_struct intr_work;
struct devlink_health_reporter *rvu_hw_nix_gen_reporter;
struct work_struct gen_work;
struct devlink_health_reporter *rvu_hw_nix_err_reporter;
struct work_struct err_work;
struct devlink_health_reporter *rvu_hw_nix_ras_reporter;
struct work_struct ras_work;
};
struct rvu_devlink {
struct devlink *dl;
struct rvu *rvu;
struct workqueue_struct *devlink_wq;
struct rvu_npa_health_reporters *rvu_npa_health_reporter;
struct rvu_nix_health_reporters *rvu_nix_health_reporter;
};
/* Devlink APIs */
int rvu_register_dl(struct rvu *rvu);
void rvu_unregister_dl(struct rvu *rvu);
#endif /* RVU_DEVLINK_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+6706
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
+614
View File
@@ -0,0 +1,614 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*
*/
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "rvu_struct.h"
#include "rvu_reg.h"
#include "rvu.h"
static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
struct npa_aq_inst_s *inst)
{
struct admin_queue *aq = block->aq;
struct npa_aq_res_s *result;
int timeout = 1000;
u64 reg, head;
result = (struct npa_aq_res_s *)aq->res->base;
/* Get current head pointer where to append this instruction */
reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS);
head = (reg >> 4) & AQ_PTR_MASK;
memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)),
(void *)inst, aq->inst->entry_sz);
memset(result, 0, sizeof(*result));
/* sync into memory */
wmb();
/* Ring the doorbell and wait for result */
rvu_write64(rvu, block->addr, NPA_AF_AQ_DOOR, 1);
while (result->compcode == NPA_AQ_COMP_NOTDONE) {
cpu_relax();
udelay(1);
timeout--;
if (!timeout)
return -EBUSY;
}
if (result->compcode != NPA_AQ_COMP_GOOD) {
/* TODO: Replace this with some error code */
if (result->compcode == NPA_AQ_COMP_CTX_FAULT ||
result->compcode == NPA_AQ_COMP_LOCKERR ||
result->compcode == NPA_AQ_COMP_CTX_POISON) {
if (rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NPA0))
dev_err(rvu->dev,
"%s: Not able to unlock cachelines\n", __func__);
}
return -EBUSY;
}
return 0;
}
int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
struct npa_aq_enq_rsp *rsp)
{
struct rvu_hwinfo *hw = rvu->hw;
u16 pcifunc = req->hdr.pcifunc;
int blkaddr, npalf, rc = 0;
struct npa_aq_inst_s inst;
struct rvu_block *block;
struct admin_queue *aq;
struct rvu_pfvf *pfvf;
void *ctx, *mask;
bool ena;
pfvf = rvu_get_pfvf(rvu, pcifunc);
if (!pfvf->aura_ctx || req->aura_id >= pfvf->aura_ctx->qsize)
return NPA_AF_ERR_AQ_ENQUEUE;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
if (!pfvf->npalf || blkaddr < 0)
return NPA_AF_ERR_AF_LF_INVALID;
block = &hw->block[blkaddr];
aq = block->aq;
if (!aq) {
dev_warn(rvu->dev, "%s: NPA AQ not initialized\n", __func__);
return NPA_AF_ERR_AQ_ENQUEUE;
}
npalf = rvu_get_lf(rvu, block, pcifunc, 0);
if (npalf < 0)
return NPA_AF_ERR_AF_LF_INVALID;
memset(&inst, 0, sizeof(struct npa_aq_inst_s));
inst.cindex = req->aura_id;
inst.lf = npalf;
inst.ctype = req->ctype;
inst.op = req->op;
/* Currently we are not supporting enqueuing multiple instructions,
* so always choose first entry in result memory.
*/
inst.res_addr = (u64)aq->res->iova;
/* Hardware uses same aq->res->base for updating result of
* previous instruction hence wait here till it is done.
*/
spin_lock(&aq->lock);
/* Clean result + context memory */
memset(aq->res->base, 0, aq->res->entry_sz);
/* Context needs to be written at RES_ADDR + 128 */
ctx = aq->res->base + 128;
/* Mask needs to be written at RES_ADDR + 256 */
mask = aq->res->base + 256;
switch (req->op) {
case NPA_AQ_INSTOP_WRITE:
/* Copy context and write mask */
if (req->ctype == NPA_AQ_CTYPE_AURA) {
memcpy(mask, &req->aura_mask,
sizeof(struct npa_aura_s));
memcpy(ctx, &req->aura, sizeof(struct npa_aura_s));
} else {
memcpy(mask, &req->pool_mask,
sizeof(struct npa_pool_s));
memcpy(ctx, &req->pool, sizeof(struct npa_pool_s));
}
break;
case NPA_AQ_INSTOP_INIT:
if (req->ctype == NPA_AQ_CTYPE_AURA) {
if (req->aura.pool_addr >= pfvf->pool_ctx->qsize) {
rc = NPA_AF_ERR_AQ_FULL;
break;
}
/* Set pool's context address */
req->aura.pool_addr = pfvf->pool_ctx->iova +
(req->aura.pool_addr * pfvf->pool_ctx->entry_sz);
memcpy(ctx, &req->aura, sizeof(struct npa_aura_s));
} else { /* POOL's context */
memcpy(ctx, &req->pool, sizeof(struct npa_pool_s));
}
break;
case NPA_AQ_INSTOP_NOP:
case NPA_AQ_INSTOP_READ:
case NPA_AQ_INSTOP_LOCK:
case NPA_AQ_INSTOP_UNLOCK:
break;
default:
rc = NPA_AF_ERR_AQ_FULL;
break;
}
if (rc) {
spin_unlock(&aq->lock);
return rc;
}
/* Submit the instruction to AQ */
rc = npa_aq_enqueue_wait(rvu, block, &inst);
if (rc) {
spin_unlock(&aq->lock);
return rc;
}
/* Set aura bitmap if aura hw context is enabled */
if (req->ctype == NPA_AQ_CTYPE_AURA) {
if (req->op == NPA_AQ_INSTOP_INIT && req->aura.ena)
__set_bit(req->aura_id, pfvf->aura_bmap);
if (req->op == NPA_AQ_INSTOP_WRITE) {
ena = (req->aura.ena & req->aura_mask.ena) |
(test_bit(req->aura_id, pfvf->aura_bmap) &
~req->aura_mask.ena);
if (ena)
__set_bit(req->aura_id, pfvf->aura_bmap);
else
__clear_bit(req->aura_id, pfvf->aura_bmap);
}
}
/* Set pool bitmap if pool hw context is enabled */
if (req->ctype == NPA_AQ_CTYPE_POOL) {
if (req->op == NPA_AQ_INSTOP_INIT && req->pool.ena)
__set_bit(req->aura_id, pfvf->pool_bmap);
if (req->op == NPA_AQ_INSTOP_WRITE) {
ena = (req->pool.ena & req->pool_mask.ena) |
(test_bit(req->aura_id, pfvf->pool_bmap) &
~req->pool_mask.ena);
if (ena)
__set_bit(req->aura_id, pfvf->pool_bmap);
else
__clear_bit(req->aura_id, pfvf->pool_bmap);
}
}
spin_unlock(&aq->lock);
if (rsp) {
/* Copy read context into mailbox */
if (req->op == NPA_AQ_INSTOP_READ) {
if (req->ctype == NPA_AQ_CTYPE_AURA)
memcpy(&rsp->aura, ctx,
sizeof(struct npa_aura_s));
else
memcpy(&rsp->pool, ctx,
sizeof(struct npa_pool_s));
}
}
return 0;
}
static int npa_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
struct npa_aq_enq_req aq_req;
unsigned long *bmap;
int id, cnt = 0;
int err = 0, rc;
if (!pfvf->pool_ctx || !pfvf->aura_ctx)
return NPA_AF_ERR_AQ_ENQUEUE;
memset(&aq_req, 0, sizeof(struct npa_aq_enq_req));
aq_req.hdr.pcifunc = req->hdr.pcifunc;
if (req->ctype == NPA_AQ_CTYPE_POOL) {
aq_req.pool.ena = 0;
aq_req.pool_mask.ena = 1;
cnt = pfvf->pool_ctx->qsize;
bmap = pfvf->pool_bmap;
} else if (req->ctype == NPA_AQ_CTYPE_AURA) {
aq_req.aura.ena = 0;
aq_req.aura_mask.ena = 1;
aq_req.aura.bp_ena = 0;
aq_req.aura_mask.bp_ena = 1;
cnt = pfvf->aura_ctx->qsize;
bmap = pfvf->aura_bmap;
}
aq_req.ctype = req->ctype;
aq_req.op = NPA_AQ_INSTOP_WRITE;
for (id = 0; id < cnt; id++) {
if (!test_bit(id, bmap))
continue;
aq_req.aura_id = id;
rc = rvu_npa_aq_enq_inst(rvu, &aq_req, NULL);
if (rc) {
err = rc;
dev_err(rvu->dev, "Failed to disable %s:%d context\n",
(req->ctype == NPA_AQ_CTYPE_AURA) ?
"Aura" : "Pool", id);
}
}
return err;
}
#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING
static int npa_lf_hwctx_lockdown(struct rvu *rvu, struct npa_aq_enq_req *req)
{
struct npa_aq_enq_req lock_ctx_req;
int err;
if (req->op != NPA_AQ_INSTOP_INIT)
return 0;
memset(&lock_ctx_req, 0, sizeof(struct npa_aq_enq_req));
lock_ctx_req.hdr.pcifunc = req->hdr.pcifunc;
lock_ctx_req.ctype = req->ctype;
lock_ctx_req.op = NPA_AQ_INSTOP_LOCK;
lock_ctx_req.aura_id = req->aura_id;
err = rvu_npa_aq_enq_inst(rvu, &lock_ctx_req, NULL);
if (err)
dev_err(rvu->dev,
"PFUNC 0x%x: Failed to lock NPA context %s:%d\n",
req->hdr.pcifunc,
(req->ctype == NPA_AQ_CTYPE_AURA) ?
"Aura" : "Pool", req->aura_id);
return err;
}
int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu,
struct npa_aq_enq_req *req,
struct npa_aq_enq_rsp *rsp)
{
int err;
err = rvu_npa_aq_enq_inst(rvu, req, rsp);
if (!err)
err = npa_lf_hwctx_lockdown(rvu, req);
return err;
}
#else
int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu,
struct npa_aq_enq_req *req,
struct npa_aq_enq_rsp *rsp)
{
return rvu_npa_aq_enq_inst(rvu, req, rsp);
}
#endif
int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu,
struct hwctx_disable_req *req,
struct msg_rsp *rsp)
{
return npa_lf_hwctx_disable(rvu, req);
}
static void npa_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf)
{
kfree(pfvf->aura_bmap);
pfvf->aura_bmap = NULL;
qmem_free(rvu->dev, pfvf->aura_ctx);
pfvf->aura_ctx = NULL;
kfree(pfvf->pool_bmap);
pfvf->pool_bmap = NULL;
qmem_free(rvu->dev, pfvf->pool_ctx);
pfvf->pool_ctx = NULL;
qmem_free(rvu->dev, pfvf->npa_qints_ctx);
pfvf->npa_qints_ctx = NULL;
}
int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu,
struct npa_lf_alloc_req *req,
struct npa_lf_alloc_rsp *rsp)
{
int npalf, qints, hwctx_size, err, rc = 0;
struct rvu_hwinfo *hw = rvu->hw;
u16 pcifunc = req->hdr.pcifunc;
struct rvu_block *block;
struct rvu_pfvf *pfvf;
u64 cfg, ctx_cfg;
int blkaddr;
if (req->aura_sz > NPA_AURA_SZ_MAX ||
req->aura_sz == NPA_AURA_SZ_0 || !req->nr_pools)
return NPA_AF_ERR_PARAM;
if (req->way_mask)
req->way_mask &= 0xFFFF;
pfvf = rvu_get_pfvf(rvu, pcifunc);
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
if (!pfvf->npalf || blkaddr < 0)
return NPA_AF_ERR_AF_LF_INVALID;
block = &hw->block[blkaddr];
npalf = rvu_get_lf(rvu, block, pcifunc, 0);
if (npalf < 0)
return NPA_AF_ERR_AF_LF_INVALID;
/* Reset this NPA LF */
err = rvu_lf_reset(rvu, block, npalf);
if (err) {
dev_err(rvu->dev, "Failed to reset NPALF%d\n", npalf);
return NPA_AF_ERR_LF_RESET;
}
ctx_cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST1);
/* Alloc memory for aura HW contexts */
hwctx_size = 1UL << (ctx_cfg & 0xF);
err = qmem_alloc(rvu->dev, &pfvf->aura_ctx,
NPA_AURA_COUNT(req->aura_sz), hwctx_size);
if (err)
goto free_mem;
pfvf->aura_bmap = kcalloc(NPA_AURA_COUNT(req->aura_sz), sizeof(long),
GFP_KERNEL);
if (!pfvf->aura_bmap)
goto free_mem;
/* Alloc memory for pool HW contexts */
hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF);
err = qmem_alloc(rvu->dev, &pfvf->pool_ctx, req->nr_pools, hwctx_size);
if (err)
goto free_mem;
pfvf->pool_bmap = kcalloc(NPA_AURA_COUNT(req->aura_sz), sizeof(long),
GFP_KERNEL);
if (!pfvf->pool_bmap)
goto free_mem;
/* Get no of queue interrupts supported */
cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST);
qints = (cfg >> 28) & 0xFFF;
/* Alloc memory for Qints HW contexts */
hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF);
err = qmem_alloc(rvu->dev, &pfvf->npa_qints_ctx, qints, hwctx_size);
if (err)
goto free_mem;
cfg = rvu_read64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf));
/* Clear way partition mask and set aura offset to '0' */
cfg &= ~(BIT_ULL(34) - 1);
/* Set aura size & enable caching of contexts */
cfg |= (req->aura_sz << 16) | BIT_ULL(34) | req->way_mask;
rvu_write64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf), cfg);
/* Configure aura HW context's base */
rvu_write64(rvu, blkaddr, NPA_AF_LFX_LOC_AURAS_BASE(npalf),
(u64)pfvf->aura_ctx->iova);
/* Enable caching of qints hw context */
rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_CFG(npalf),
BIT_ULL(36) | req->way_mask << 20);
rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_BASE(npalf),
(u64)pfvf->npa_qints_ctx->iova);
goto exit;
free_mem:
npa_ctx_free(rvu, pfvf);
rc = -ENOMEM;
exit:
/* set stack page info */
cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST);
rsp->stack_pg_ptrs = (cfg >> 8) & 0xFF;
rsp->stack_pg_bytes = cfg & 0xFF;
rsp->qints = (cfg >> 28) & 0xFFF;
if (!is_rvu_otx2(rvu)) {
cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);
rsp->cache_lines = (cfg >> 1) & 0x3F;
}
return rc;
}
int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req,
struct msg_rsp *rsp)
{
struct rvu_hwinfo *hw = rvu->hw;
u16 pcifunc = req->hdr.pcifunc;
struct rvu_block *block;
struct rvu_pfvf *pfvf;
int npalf, err;
int blkaddr;
pfvf = rvu_get_pfvf(rvu, pcifunc);
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
if (!pfvf->npalf || blkaddr < 0)
return NPA_AF_ERR_AF_LF_INVALID;
block = &hw->block[blkaddr];
npalf = rvu_get_lf(rvu, block, pcifunc, 0);
if (npalf < 0)
return NPA_AF_ERR_AF_LF_INVALID;
/* Reset this NPA LF */
err = rvu_lf_reset(rvu, block, npalf);
if (err) {
dev_err(rvu->dev, "Failed to reset NPALF%d\n", npalf);
return NPA_AF_ERR_LF_RESET;
}
npa_ctx_free(rvu, pfvf);
return 0;
}
static void npa_aq_ndc_config(struct rvu *rvu, struct rvu_block *block)
{
u64 cfg;
if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */
return;
/* Do not bypass NDC cache */
cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG);
cfg &= ~0x03DULL;
#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING
/* Disable caching of stack pages */
cfg |= 0x10ULL;
#endif
rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg);
}
static int npa_aq_init(struct rvu *rvu, struct rvu_block *block)
{
u64 cfg;
int err;
/* Set admin queue endianness */
cfg = rvu_read64(rvu, block->addr, NPA_AF_GEN_CFG);
#ifdef __BIG_ENDIAN
cfg |= BIT_ULL(1);
rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg);
#else
cfg &= ~BIT_ULL(1);
rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg);
#endif
npa_aq_ndc_config(rvu, block);
/* For CN10K NPA BATCH DMA set 35 cache lines */
if (!is_rvu_otx2(rvu)) {
cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);
cfg &= ~0x7EULL;
cfg |= BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1);
rvu_write64(rvu, block->addr, NPA_AF_BATCH_CTL, cfg);
}
/* Result structure can be followed by Aura/Pool context at
* RES + 128bytes and a write mask at RES + 256 bytes, depending on
* operation type. Alloc sufficient result memory for all operations.
*/
err = rvu_aq_alloc(rvu, &block->aq,
Q_COUNT(AQ_SIZE), sizeof(struct npa_aq_inst_s),
ALIGN(sizeof(struct npa_aq_res_s), 128) + 256);
if (err)
return err;
rvu_write64(rvu, block->addr, NPA_AF_AQ_CFG, AQ_SIZE);
rvu_write64(rvu, block->addr,
NPA_AF_AQ_BASE, (u64)block->aq->inst->iova);
return 0;
}
int rvu_npa_init(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
int blkaddr;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0);
if (blkaddr < 0)
return 0;
/* Initialize admin queue */
return npa_aq_init(rvu, &hw->block[blkaddr]);
}
void rvu_npa_freemem(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
struct rvu_block *block;
int blkaddr;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0);
if (blkaddr < 0)
return;
block = &hw->block[blkaddr];
rvu_aq_free(rvu, block->aq);
}
void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
struct hwctx_disable_req ctx_req;
/* Disable all pools */
ctx_req.hdr.pcifunc = pcifunc;
ctx_req.ctype = NPA_AQ_CTYPE_POOL;
npa_lf_hwctx_disable(rvu, &ctx_req);
/* Disable all auras */
ctx_req.ctype = NPA_AQ_CTYPE_AURA;
npa_lf_hwctx_disable(rvu, &ctx_req);
npa_ctx_free(rvu, pfvf);
}
/* Due to an Hardware errata, in some corner cases, AQ context lock
* operations can result in a NDC way getting into an illegal state
* of not valid but locked.
*
* This API solves the problem by clearing the lock bit of the NDC block.
* The operation needs to be done for each line of all the NDC banks.
*/
int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr)
{
int bank, max_bank, line, max_line, err;
u64 reg, ndc_af_const;
if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */
return 0;
/* Set the ENABLE bit(63) to '0' */
reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL);
rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0));
/* Poll until the BUSY bits(47:32) are set to '0' */
err = rvu_poll_reg(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, GENMASK_ULL(47, 32), true);
if (err) {
dev_err(rvu->dev, "Timed out while polling for NDC CAM busy bits.\n");
return err;
}
ndc_af_const = rvu_read64(rvu, blkaddr, NDC_AF_CONST);
max_bank = FIELD_GET(NDC_AF_BANK_MASK, ndc_af_const);
max_line = FIELD_GET(NDC_AF_BANK_LINE_MASK, ndc_af_const);
for (bank = 0; bank < max_bank; bank++) {
for (line = 0; line < max_line; line++) {
/* Check if 'cache line valid bit(63)' is not set
* but 'cache line lock bit(60)' is set and on
* success, reset the lock bit(60).
*/
reg = rvu_read64(rvu, blkaddr,
NDC_AF_BANKX_LINEX_METADATA(bank, line));
if (!(reg & BIT_ULL(63)) && (reg & BIT_ULL(60))) {
rvu_write64(rvu, blkaddr,
NDC_AF_BANKX_LINEX_METADATA(bank, line),
reg & ~BIT_ULL(60));
}
}
}
return 0;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+4405
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.h
+38
View File
@@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2026 Marvell.
*
*/
#ifndef RVU_NPC_H
#define RVU_NPC_H
u64 npc_enable_mask(int count);
void npc_load_kpu_profile(struct rvu *rvu);
void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
const struct npc_kpu_profile_action *kpuaction,
int kpu, int entry, bool pkind);
int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr,
u64 *size);
void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index);
void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index);
struct npc_kpu_profile_action *
npc_get_ikpu_nth_entry(struct rvu *rvu, int n);
int
npc_get_num_kpu_cam_entries(struct rvu *rvu,
const struct npc_kpu_profile *kpu_pfl);
struct npc_kpu_profile_cam *
npc_get_kpu_cam_nth_entry(struct rvu *rvu,
const struct npc_kpu_profile *kpu_pfl, int n);
int
npc_get_num_kpu_action_entries(struct rvu *rvu,
const struct npc_kpu_profile *kpu_pfl);
struct npc_kpu_profile_action *
npc_get_kpu_action_nth_entry(struct rvu *rvu,
const struct npc_kpu_profile *kpu_pfl, int n);
#endif /* RVU_NPC_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
+2256
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.h
+33
View File
@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2022 Marvell.
*
*/
#ifndef __RVU_NPC_FS_H
#define __RVU_NPC_FS_H
#define IPV6_WORDS 4
#define NPC_BYTESM GENMASK_ULL(19, 16)
#define NPC_HDR_OFFSET GENMASK_ULL(15, 8)
#define NPC_KEY_OFFSET GENMASK_ULL(5, 0)
#define NPC_LDATA_EN BIT_ULL(7)
void npc_update_entry(struct rvu *rvu, enum key_fields type,
struct mcam_entry_mdata *mdata, u64 val_lo,
u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf);
void npc_update_flow(struct rvu *rvu, struct mcam_entry_mdata *mdata,
u64 features, struct flow_msg *pkt,
struct flow_msg *mask,
struct rvu_npc_mcam_rule *output, u8 intf,
int blkaddr);
void
npc_populate_mcam_mdata(struct rvu *rvu,
struct mcam_entry_mdata *mdata,
struct cn20k_mcam_entry *cn20k_entry,
struct mcam_entry *entry);
#endif /* RVU_NPC_FS_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c
+2052
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h
+237
View File
@@ -0,0 +1,237 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2022 Marvell.
*
*/
#ifndef __RVU_NPC_HASH_H
#define __RVU_NPC_HASH_H
#define RVU_NPC_HASH_SECRET_KEY0 0xa9d5af4c9fbc76b1
#define RVU_NPC_HASH_SECRET_KEY1 0xa9d5af4c9fbc87b4
#define RVU_NPC_HASH_SECRET_KEY2 0x5954c9e7
#define NPC_MAX_HASH 2
#define NPC_MAX_HASH_MASK 2
#define KEX_LD_CFG_USE_HASH(use_hash, bytesm1, hdr_ofs, ena, flags_ena, key_ofs) \
((use_hash) << 20 | ((bytesm1) << 16) | ((hdr_ofs) << 8) | \
((ena) << 7) | ((flags_ena) << 6) | ((key_ofs) & 0x3F))
#define KEX_LD_CFG_HASH(hdr_ofs, bytesm1, lt_en, lid_en, lid, ltype_match, ltype_mask) \
(((hdr_ofs) << 32) | ((bytesm1) << 16) | \
((lt_en) << 12) | ((lid_en) << 11) | ((lid) << 8) | \
((ltype_match) << 4) | ((ltype_mask) & 0xF))
#define SET_KEX_LD_HASH(intf, ld, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_HASHX_CFG(intf, ld), cfg)
#define SET_KEX_LD_HASH_MASK(intf, ld, mask_idx, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_HASHX_MASKX(intf, ld, mask_idx), cfg)
#define GET_KEX_LD_HASH_CTRL(intf, ld) \
rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_RESULT_CTRL(intf, ld))
#define GET_KEX_LD_HASH_MASK(intf, ld, mask_idx) \
rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_MASKX(intf, ld, mask_idx))
#define SET_KEX_LD_HASH_CTRL(intf, ld, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_HASHX_RESULT_CTRL(intf, ld), cfg)
struct npc_mcam_kex_hash {
/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
bool lid_lt_ld_hash_en[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
/* NPC_AF_INTF(0..1)_HASH(0..1)_CFG */
u64 hash[NPC_MAX_INTF][NPC_MAX_HASH];
/* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
/* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
} __packed;
void npc_update_field_hash(struct rvu *rvu, u8 intf,
struct mcam_entry_mdata *mdata,
int blkaddr,
u64 features,
struct flow_msg *pkt,
struct flow_msg *mask,
struct flow_msg *opkt,
struct flow_msg *omask);
void npc_config_secret_key(struct rvu *rvu, int blkaddr);
void npc_program_mkex_hash(struct rvu *rvu, int blkaddr);
u32 npc_field_hash_calc(u64 *ldata, struct npc_get_field_hash_info_rsp rsp,
u8 intf, u8 hash_idx);
static struct npc_mcam_kex_hash npc_mkex_hash_default __maybe_unused = {
.lid_lt_ld_hash_en = {
[NIX_INTF_RX] = {
[NPC_LID_LC] = {
[NPC_LT_LC_IP6] = {
false,
false,
},
},
},
[NIX_INTF_TX] = {
[NPC_LID_LC] = {
[NPC_LT_LC_IP6] = {
false,
false,
},
},
},
},
.hash = {
[NIX_INTF_RX] = {
KEX_LD_CFG_HASH(0x8ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf),
KEX_LD_CFG_HASH(0x18ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf),
},
[NIX_INTF_TX] = {
KEX_LD_CFG_HASH(0x8ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf),
KEX_LD_CFG_HASH(0x18ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf),
},
},
.hash_mask = {
[NIX_INTF_RX] = {
[0] = {
GENMASK_ULL(63, 0),
GENMASK_ULL(63, 0),
},
[1] = {
GENMASK_ULL(63, 0),
GENMASK_ULL(63, 0),
},
},
[NIX_INTF_TX] = {
[0] = {
GENMASK_ULL(63, 0),
GENMASK_ULL(63, 0),
},
[1] = {
GENMASK_ULL(63, 0),
GENMASK_ULL(63, 0),
},
},
},
.hash_ctrl = {
[NIX_INTF_RX] = {
[0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
[1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
},
[NIX_INTF_TX] = {
[0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
[1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
},
},
};
/* If exact match table support is enabled, enable drop rules */
#define NPC_MCAM_DROP_RULE_MAX 30
#define NPC_MCAM_SDP_DROP_RULE_IDX 0
#define RVU_PFFUNC(pdev, pf, func) rvu_make_pcifunc(pdev, pf, func)
enum npc_exact_opc_type {
NPC_EXACT_OPC_MEM,
NPC_EXACT_OPC_CAM,
};
struct npc_exact_table_entry {
struct list_head list;
struct list_head glist;
u32 seq_id; /* Sequence number of entry */
u32 index; /* Mem table or cam table index */
u32 mcam_idx;
/* Mcam index. This is valid only if "cmd" field is false */
enum npc_exact_opc_type opc_type;
u16 chan;
u16 pcifunc;
u8 ways;
u8 mac[ETH_ALEN];
u8 ctype;
u8 cgx_id;
u8 lmac_id;
bool cmd; /* Is added by ethtool command ? */
};
struct npc_exact_table {
struct mutex lock; /* entries update lock */
unsigned long *id_bmap;
int num_drop_rules;
u32 tot_ids;
u16 cnt_cmd_rules[NPC_MCAM_DROP_RULE_MAX];
u16 counter_idx[NPC_MCAM_DROP_RULE_MAX];
bool promisc_mode[NPC_MCAM_DROP_RULE_MAX];
struct {
int ways;
int depth;
unsigned long *bmap;
u64 mask; // Masks before hash calculation.
u16 hash_mask; // 11 bits for hash mask
u16 hash_offset; // 11 bits offset
} mem_table;
struct {
int depth;
unsigned long *bmap;
} cam_table;
struct {
bool valid;
u16 chan_val;
u16 chan_mask;
u16 pcifunc;
u8 drop_rule_idx;
} drop_rule_map[NPC_MCAM_DROP_RULE_MAX];
#define NPC_EXACT_TBL_MAX_WAYS 4
struct list_head lhead_mem_tbl_entry[NPC_EXACT_TBL_MAX_WAYS];
int mem_tbl_entry_cnt;
struct list_head lhead_cam_tbl_entry;
int cam_tbl_entry_cnt;
struct list_head lhead_gbl;
};
bool rvu_npc_exact_has_match_table(struct rvu *rvu);
u32 rvu_npc_exact_get_max_entries(struct rvu *rvu);
int rvu_npc_exact_init(struct rvu *rvu);
int rvu_npc_exact_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req,
struct msg_rsp *rsp);
int rvu_npc_exact_mac_addr_update(struct rvu *rvu,
struct cgx_mac_addr_update_req *req,
struct cgx_mac_addr_update_rsp *rsp);
int rvu_npc_exact_mac_addr_add(struct rvu *rvu,
struct cgx_mac_addr_add_req *req,
struct cgx_mac_addr_add_rsp *rsp);
int rvu_npc_exact_mac_addr_del(struct rvu *rvu,
struct cgx_mac_addr_del_req *req,
struct msg_rsp *rsp);
int rvu_npc_exact_mac_addr_set(struct rvu *rvu, struct cgx_mac_addr_set_or_get *req,
struct cgx_mac_addr_set_or_get *rsp);
void rvu_npc_exact_reset(struct rvu *rvu, u16 pcifunc);
bool rvu_npc_exact_can_disable_feature(struct rvu *rvu);
void rvu_npc_exact_disable_feature(struct rvu *rvu);
void rvu_npc_exact_reset(struct rvu *rvu, u16 pcifunc);
u16 rvu_npc_exact_drop_rule_to_pcifunc(struct rvu *rvu, u32 drop_rule_idx);
int rvu_npc_exact_promisc_disable(struct rvu *rvu, u16 pcifunc);
int rvu_npc_exact_promisc_enable(struct rvu *rvu, u16 pcifunc);
#endif /* RVU_NPC_HASH_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
+68
View File
@@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*
*/
#include <linux/module.h>
#include <linux/pci.h>
#include "rvu_struct.h"
#include "common.h"
#include "mbox.h"
#include "rvu.h"
struct reg_range {
u64 start;
u64 end;
};
struct hw_reg_map {
u8 regblk;
u8 num_ranges;
u64 mask;
#define MAX_REG_RANGES 8
struct reg_range range[MAX_REG_RANGES];
};
static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
{NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
{0x1200, 0x12E0} } },
{NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
{0x1610, 0x1618}, {0x1700, 0x17C8} } },
{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
};
bool rvu_check_valid_reg(int regmap, int regblk, u64 reg)
{
int idx;
struct hw_reg_map *map;
/* Only 64bit offsets */
if (reg & 0x07)
return false;
if (regmap == TXSCHQ_HWREGMAP) {
if (regblk >= NIX_TXSCH_LVL_CNT)
return false;
map = &txsch_reg_map[regblk];
} else {
return false;
}
/* Should never happen */
if (map->regblk != regblk)
return false;
reg &= map->mask;
for (idx = 0; idx < map->num_ranges; idx++) {
if (reg >= map->range[idx].start &&
reg < map->range[idx].end)
return true;
}
return false;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
+755
View File
@@ -0,0 +1,755 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*
*/
#ifndef RVU_REG_H
#define RVU_REG_H
/* Admin function registers */
#define RVU_AF_MSIXTR_BASE (0x10)
#define RVU_AF_ECO (0x20)
#define RVU_AF_BLK_RST (0x30)
#define RVU_AF_PF_BAR4_ADDR (0x40)
#define RVU_AF_RAS (0x100)
#define RVU_AF_RAS_W1S (0x108)
#define RVU_AF_RAS_ENA_W1S (0x110)
#define RVU_AF_RAS_ENA_W1C (0x118)
#define RVU_AF_GEN_INT (0x120)
#define RVU_AF_GEN_INT_W1S (0x128)
#define RVU_AF_GEN_INT_ENA_W1S (0x130)
#define RVU_AF_GEN_INT_ENA_W1C (0x138)
#define RVU_AF_AFPF_MBOX0 (0x02000)
#define RVU_AF_AFPF_MBOX1 (0x02008)
#define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3)
#define RVU_AF_PFME_STATUS (0x2800)
#define RVU_AF_PFTRPEND (0x2810)
#define RVU_AF_PFTRPEND_W1S (0x2820)
#define RVU_AF_PF_RST (0x2840)
#define RVU_AF_HWVF_RST (0x2850)
#define RVU_AF_PFAF_MBOX_INT (0x2880)
#define RVU_AF_PFAF_MBOX_INT_W1S (0x2888)
#define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890)
#define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898)
#define RVU_AF_PFFLR_INT (0x28a0)
#define RVU_AF_PFFLR_INT_W1S (0x28a8)
#define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0)
#define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8)
#define RVU_AF_PFME_INT (0x28c0)
#define RVU_AF_PFME_INT_W1S (0x28c8)
#define RVU_AF_PFME_INT_ENA_W1S (0x28d0)
#define RVU_AF_PFME_INT_ENA_W1C (0x28d8)
#define RVU_AF_PFX_BAR4_ADDR(a) (0x5000 | (a) << 4)
#define RVU_AF_PFX_BAR4_CFG (0x5200 | (a) << 4)
#define RVU_AF_PFX_VF_BAR4_ADDR (0x5400 | (a) << 4)
#define RVU_AF_PFX_VF_BAR4_CFG (0x5600 | (a) << 4)
#define RVU_AF_PFX_LMTLINE_ADDR (0x5800 | (a) << 4)
#define RVU_AF_SMMU_ADDR_REQ (0x6000)
#define RVU_AF_SMMU_TXN_REQ (0x6008)
#define RVU_AF_SMMU_ADDR_RSP_STS (0x6010)
#define RVU_AF_SMMU_ADDR_TLN (0x6018)
#define RVU_AF_SMMU_TLN_FLIT0 (0x6020)
/* Admin function's privileged PF/VF registers */
#define RVU_PRIV_CONST (0x8000000)
#define RVU_PRIV_GEN_CFG (0x8000010)
#define RVU_PRIV_CLK_CFG (0x8000020)
#define RVU_PRIV_ACTIVE_PC (0x8000030)
#define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16)
#define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16)
#define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16)
#define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16)
#define RVU_PRIV_PFX_NIXX_CFG(a) (0x8000300 | (a) << 3)
#define RVU_PRIV_PFX_NPA_CFG (0x8000310)
#define RVU_PRIV_PFX_SSO_CFG (0x8000320)
#define RVU_PRIV_PFX_SSOW_CFG (0x8000330)
#define RVU_PRIV_PFX_TIM_CFG (0x8000340)
#define RVU_PRIV_PFX_CPTX_CFG(a) (0x8000350 | (a) << 3)
#define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3)
#define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16)
#define RVU_PRIV_HWVFX_NIXX_CFG(a) (0x8001300 | (a) << 3)
#define RVU_PRIV_HWVFX_NPA_CFG (0x8001310)
#define RVU_PRIV_HWVFX_SSO_CFG (0x8001320)
#define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330)
#define RVU_PRIV_HWVFX_TIM_CFG (0x8001340)
#define RVU_PRIV_HWVFX_CPTX_CFG(a) (0x8001350 | (a) << 3)
/* RVU PF registers */
#define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
#define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
#define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
#define RVU_PF_VF_BAR4_ADDR (0x10)
#define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
#define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
#define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
#define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
#define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
#define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3)
#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3)
#define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3)
#define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3)
#define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3)
#define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3)
#define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3)
#define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3)
#define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3)
#define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3)
#define RVU_PF_PFAF_MBOX0 (0xC00)
#define RVU_PF_PFAF_MBOX1 (0xC08)
#define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3)
#define RVU_PF_INT (0xc20)
#define RVU_PF_INT_W1S (0xc28)
#define RVU_PF_INT_ENA_W1S (0xc30)
#define RVU_PF_INT_ENA_W1C (0xc38)
#define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4)
#define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4)
#define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3)
#define RVU_PF_VF_MBOX_ADDR (0xC40)
#define RVU_PF_LMTLINE_ADDR (0xC48)
/* RVU VF registers */
#define RVU_VF_VFPF_MBOX0 (0x00000)
#define RVU_VF_VFPF_MBOX1 (0x00008)
/* NPA block's admin function registers */
#define NPA_AF_BLK_RST (0x0000)
#define NPA_AF_CONST (0x0010)
#define NPA_AF_CONST1 (0x0018)
#define NPA_AF_LF_RST (0x0020)
#define NPA_AF_GEN_CFG (0x0030)
#define NPA_AF_NDC_CFG (0x0040)
#define NPA_AF_NDC_SYNC (0x0050)
#define NPA_AF_INP_CTL (0x00D0)
#define NPA_AF_ACTIVE_CYCLES_PC (0x00F0)
#define NPA_AF_AVG_DELAY (0x0100)
#define NPA_AF_GEN_INT (0x0140)
#define NPA_AF_GEN_INT_W1S (0x0148)
#define NPA_AF_GEN_INT_ENA_W1S (0x0150)
#define NPA_AF_GEN_INT_ENA_W1C (0x0158)
#define NPA_AF_RVU_INT (0x0160)
#define NPA_AF_RVU_INT_W1S (0x0168)
#define NPA_AF_RVU_INT_ENA_W1S (0x0170)
#define NPA_AF_RVU_INT_ENA_W1C (0x0178)
#define NPA_AF_ERR_INT (0x0180)
#define NPA_AF_ERR_INT_W1S (0x0188)
#define NPA_AF_ERR_INT_ENA_W1S (0x0190)
#define NPA_AF_ERR_INT_ENA_W1C (0x0198)
#define NPA_AF_RAS (0x01A0)
#define NPA_AF_RAS_W1S (0x01A8)
#define NPA_AF_RAS_ENA_W1S (0x01B0)
#define NPA_AF_RAS_ENA_W1C (0x01B8)
#define NPA_AF_BP_TEST (0x0200)
#define NPA_AF_ECO (0x0300)
#define NPA_AF_AQ_CFG (0x0600)
#define NPA_AF_AQ_BASE (0x0610)
#define NPA_AF_AQ_STATUS (0x0620)
#define NPA_AF_AQ_DOOR (0x0630)
#define NPA_AF_AQ_DONE_WAIT (0x0640)
#define NPA_AF_AQ_DONE (0x0650)
#define NPA_AF_AQ_DONE_ACK (0x0660)
#define NPA_AF_AQ_DONE_INT (0x0680)
#define NPA_AF_AQ_DONE_INT_W1S (0x0688)
#define NPA_AF_AQ_DONE_ENA_W1S (0x0690)
#define NPA_AF_AQ_DONE_ENA_W1C (0x0698)
#define NPA_AF_BATCH_CTL (0x06a0)
#define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18)
#define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18)
#define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18)
#define NPA_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 18)
#define NPA_PRIV_AF_INT_CFG (0x10000)
#define NPA_PRIV_LFX_CFG (0x10010)
#define NPA_PRIV_LFX_INT_CFG (0x10020)
#define NPA_AF_RVU_LF_CFG_DEBUG (0x10030)
/* NIX block's admin function registers */
#define NIX_AF_CFG (0x0000)
#define NIX_AF_STATUS (0x0010)
#define NIX_AF_NDC_CFG (0x0018)
#define NIX_AF_CONST (0x0020)
#define NIX_AF_CONST1 (0x0028)
#define NIX_AF_CONST2 (0x0030)
#define NIX_AF_CONST3 (0x0038)
#define NIX_AF_SQ_CONST (0x0040)
#define NIX_AF_CQ_CONST (0x0048)
#define NIX_AF_RQ_CONST (0x0050)
#define NIX_AF_PL_CONST (0x0058)
#define NIX_AF_PSE_CONST (0x0060)
#define NIX_AF_TL1_CONST (0x0070)
#define NIX_AF_TL2_CONST (0x0078)
#define NIX_AF_TL3_CONST (0x0080)
#define NIX_AF_TL4_CONST (0x0088)
#define NIX_AF_MDQ_CONST (0x0090)
#define NIX_AF_MC_MIRROR_CONST (0x0098)
#define NIX_AF_LSO_CFG (0x00A8)
#define NIX_AF_BLK_RST (0x00B0)
#define NIX_AF_TX_TSTMP_CFG (0x00C0)
#define NIX_AF_PL_TS (0x00C8)
#define NIX_AF_RX_CFG (0x00D0)
#define NIX_AF_AVG_DELAY (0x00E0)
#define NIX_AF_CINT_DELAY (0x00F0)
#define NIX_AF_VWQE_TIMER (0x00F8)
#define NIX_AF_RX_MCAST_BASE (0x0100)
#define NIX_AF_RX_MCAST_CFG (0x0110)
#define NIX_AF_RX_MCAST_BUF_BASE (0x0120)
#define NIX_AF_RX_MCAST_BUF_CFG (0x0130)
#define NIX_AF_RX_MIRROR_BUF_BASE (0x0140)
#define NIX_AF_RX_MIRROR_BUF_CFG (0x0148)
#define NIX_AF_LF_RST (0x0150)
#define NIX_AF_GEN_INT (0x0160)
#define NIX_AF_GEN_INT_W1S (0x0168)
#define NIX_AF_GEN_INT_ENA_W1S (0x0170)
#define NIX_AF_GEN_INT_ENA_W1C (0x0178)
#define NIX_AF_ERR_INT (0x0180)
#define NIX_AF_ERR_INT_W1S (0x0188)
#define NIX_AF_ERR_INT_ENA_W1S (0x0190)
#define NIX_AF_ERR_INT_ENA_W1C (0x0198)
#define NIX_AF_RAS (0x01A0)
#define NIX_AF_RAS_W1S (0x01A8)
#define NIX_AF_RAS_ENA_W1S (0x01B0)
#define NIX_AF_RAS_ENA_W1C (0x01B8)
#define NIX_AF_RVU_INT (0x01C0)
#define NIX_AF_RVU_INT_W1S (0x01C8)
#define NIX_AF_RVU_INT_ENA_W1S (0x01D0)
#define NIX_AF_RVU_INT_ENA_W1C (0x01D8)
#define NIX_AF_TCP_TIMER (0x01E0)
#define NIX_AF_RX_DEF_ET(a) (0x01F0ull | (uint64_t)(a) << 3)
#define NIX_AF_RX_DEF_OL2 (0x0200)
#define NIX_AF_RX_DEF_OIP4 (0x0210)
#define NIX_AF_RX_DEF_IIP4 (0x0220)
#define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x0228)
#define NIX_AF_RX_DEF_OIP6 (0x0230)
#define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x0238)
#define NIX_AF_RX_DEF_IIP6 (0x0240)
#define NIX_AF_RX_DEF_OTCP (0x0250)
#define NIX_AF_RX_DEF_ITCP (0x0260)
#define NIX_AF_RX_DEF_OUDP (0x0270)
#define NIX_AF_RX_DEF_IUDP (0x0280)
#define NIX_AF_RX_DEF_OSCTP (0x0290)
#define NIX_AF_RX_DEF_CST_APAD0 (0x0298)
#define NIX_AF_RX_DEF_ISCTP (0x02A0)
#define NIX_AF_RX_DEF_IPSECX (0x02B0)
#define NIX_AF_RX_DEF_CST_APAD1 (0x02A8)
#define NIX_AF_RX_DEF_IIP4_DSCP (0x02E0)
#define NIX_AF_RX_DEF_OIP4_DSCP (0x02E8)
#define NIX_AF_RX_DEF_IIP6_DSCP (0x02F0)
#define NIX_AF_RX_DEF_OIP6_DSCP (0x02F8)
#define NIX_AF_RX_IPSEC_GEN_CFG (0x0300)
#define NIX_AF_RX_CPTX_INST_ADDR (0x0310)
#define NIX_AF_RX_CPTX_INST_QSEL(a) (0x0320ull | (uint64_t)(a) << 3)
#define NIX_AF_RX_CPTX_CREDIT(a) (0x0360ull | (uint64_t)(a) << 3)
#define NIX_AF_NDC_RX_SYNC (0x03E0)
#define NIX_AF_NDC_TX_SYNC (0x03F0)
#define NIX_AF_AQ_CFG (0x0400)
#define NIX_AF_AQ_BASE (0x0410)
#define NIX_AF_AQ_STATUS (0x0420)
#define NIX_AF_AQ_DOOR (0x0430)
#define NIX_AF_AQ_DONE_WAIT (0x0440)
#define NIX_AF_AQ_DONE (0x0450)
#define NIX_AF_AQ_DONE_ACK (0x0460)
#define NIX_AF_AQ_DONE_TIMER (0x0470)
#define NIX_AF_AQ_DONE_INT (0x0480)
#define NIX_AF_AQ_DONE_INT_W1S (0x0488)
#define NIX_AF_AQ_DONE_ENA_W1S (0x0490)
#define NIX_AF_AQ_DONE_ENA_W1C (0x0498)
#define NIX_AF_RX_LINKX_SLX_SPKT_CNT (0x0500)
#define NIX_AF_RX_LINKX_SLX_SXQE_CNT (0x0510)
#define NIX_AF_RX_MCAST_JOBSX_SW_CNT (0x0520)
#define NIX_AF_RX_MIRROR_JOBSX_SW_CNT (0x0530)
#define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16)
#define NIX_AF_RX_SW_SYNC (0x0550)
#define NIX_AF_RX_SW_SYNC_DONE (0x0560)
#define NIX_AF_SEB_ECO (0x0600)
#define NIX_AF_SEB_TEST_BP (0x0610)
#define NIX_AF_NORM_TX_FIFO_STATUS (0x0620)
#define NIX_AF_EXPR_TX_FIFO_STATUS (0x0630)
#define NIX_AF_SDP_TX_FIFO_STATUS (0x0640)
#define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x0660)
#define NIX_AF_TX_NPC_CAPTURE_INFO (0x0670)
#define NIX_AF_SEB_CFG (0x05F0)
#define NIX_PTP_1STEP_EN BIT_ULL(2)
#define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3)
#define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16)
#define NIX_AF_SQM_DBG_CTL_STATUS (0x750)
#define NIX_AF_DWRR_SDP_MTU (0x790) /* All CN10K except CN10KB */
#define NIX_AF_DWRR_MTUX(a) (0x790 | (a) << 16) /* Only for CN10KB */
#define NIX_AF_DWRR_RPM_MTU (0x7A0)
#define NIX_AF_PSE_CHANNEL_LEVEL (0x800)
#define NIX_AF_PSE_SHAPER_CFG (0x810)
#define NIX_AF_TX_EXPR_CREDIT (0x830)
#define NIX_AF_MARK_FORMATX_CTL(a) (0x900 | (a) << 18)
#define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xA00 | (a) << 16)
#define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xA10 | (a) << 16)
#define NIX_AF_TX_LINKX_SW_XOFF(a) (0xA20 | (a) << 16)
#define NIX_AF_TX_LINKX_HW_XOFF(a) (0xA30 | (a) << 16)
#define NIX_AF_SDP_LINK_CREDIT (0xa40)
#define NIX_AF_SDP_SW_XOFFX(a) (0xA60 | (a) << 3)
#define NIX_AF_SDP_HW_XOFFX(a) (0xAC0 | (a) << 3)
#define NIX_AF_TL4X_BP_STATUS(a) (0xB00 | (a) << 16)
#define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (a) << 16)
#define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16)
#define NIX_AF_TL1X_SHAPE(a) (0xC10 | (a) << 16)
#define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16)
#define NIX_AF_TL1X_SHAPE_STATE(a) (0xC50 | (a) << 16)
#define NIX_AF_TL1X_SW_XOFF(a) (0xC70 | (a) << 16)
#define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16)
#define NIX_AF_TL1X_GREEN(a) (0xC90 | (a) << 16)
#define NIX_AF_TL1X_YELLOW(a) (0xCA0 | (a) << 16)
#define NIX_AF_TL1X_RED(a) (0xCB0 | (a) << 16)
#define NIX_AF_TL1X_MD_DEBUG0(a) (0xCC0 | (a) << 16)
#define NIX_AF_TL1X_MD_DEBUG1(a) (0xCC8 | (a) << 16)
#define NIX_AF_TL1X_MD_DEBUG2(a) (0xCD0 | (a) << 16)
#define NIX_AF_TL1X_MD_DEBUG3(a) (0xCD8 | (a) << 16)
#define NIX_AF_TL1A_DEBUG (0xce0)
#define NIX_AF_TL1B_DEBUG (0xcf0)
#define NIX_AF_TL1_DEBUG_GREEN (0xd00)
#define NIX_AF_TL1_DEBUG_NODE (0xd10)
#define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xD20 | (a) << 16)
#define NIX_AF_TL1X_DROPPED_BYTES(a) (0xD30 | (a) << 16)
#define NIX_AF_TL1X_RED_PACKETS(a) (0xD40 | (a) << 16)
#define NIX_AF_TL1X_RED_BYTES(a) (0xD50 | (a) << 16)
#define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xD60 | (a) << 16)
#define NIX_AF_TL1X_YELLOW_BYTES(a) (0xD70 | (a) << 16)
#define NIX_AF_TL1X_GREEN_PACKETS(a) (0xD80 | (a) << 16)
#define NIX_AF_TL1X_GREEN_BYTES(a) (0xD90 | (a) << 16)
#define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16)
#define NIX_AF_TL2X_SHAPE(a) (0xE10 | (a) << 16)
#define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16)
#define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16)
#define NIX_AF_TL2X_SCHED_STATE(a) (0xE40 | (a) << 16)
#define NIX_AF_TL2X_SHAPE_STATE(a) (0xE50 | (a) << 16)
#define NIX_AF_TL2X_POINTERS(a) (0xE60 | (a) << 16)
#define NIX_AF_TL2X_SW_XOFF(a) (0xE70 | (a) << 16)
#define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16)
#define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16)
#define NIX_AF_TL2X_GREEN(a) (0xE90 | (a) << 16)
#define NIX_AF_TL2X_YELLOW(a) (0xEA0 | (a) << 16)
#define NIX_AF_TL2X_RED(a) (0xEB0 | (a) << 16)
#define NIX_AF_TL2X_MD_DEBUG0(a) (0xEC0 | (a) << 16)
#define NIX_AF_TL2X_MD_DEBUG1(a) (0xEC8 | (a) << 16)
#define NIX_AF_TL2X_MD_DEBUG2(a) (0xED0 | (a) << 16)
#define NIX_AF_TL2X_MD_DEBUG3(a) (0xED8 | (a) << 16)
#define NIX_AF_TL2A_DEBUG (0xee0)
#define NIX_AF_TL2B_DEBUG (0xef0)
#define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16)
#define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16)
#define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16)
#define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16)
#define NIX_AF_TL3X_SCHED_STATE(a) (0x1040 | (a) << 16)
#define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050 | (a) << 16)
#define NIX_AF_TL3X_POINTERS(a) (0x1060 | (a) << 16)
#define NIX_AF_TL3X_SW_XOFF(a) (0x1070 | (a) << 16)
#define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16)
#define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16)
#define NIX_AF_TL3X_GREEN(a) (0x1090 | (a) << 16)
#define NIX_AF_TL3X_YELLOW(a) (0x10A0 | (a) << 16)
#define NIX_AF_TL3X_RED(a) (0x10B0 | (a) << 16)
#define NIX_AF_TL3X_MD_DEBUG0(a) (0x10C0 | (a) << 16)
#define NIX_AF_TL3X_MD_DEBUG1(a) (0x10C8 | (a) << 16)
#define NIX_AF_TL3X_MD_DEBUG2(a) (0x10D0 | (a) << 16)
#define NIX_AF_TL3X_MD_DEBUG3(a) (0x10D8 | (a) << 16)
#define NIX_AF_TL3A_DEBUG (0x10e0)
#define NIX_AF_TL3B_DEBUG (0x10f0)
#define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16)
#define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16)
#define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16)
#define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16)
#define NIX_AF_TL4X_SCHED_STATE(a) (0x1240 | (a) << 16)
#define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250 | (a) << 16)
#define NIX_AF_TL4X_POINTERS(a) (0x1260 | (a) << 16)
#define NIX_AF_TL4X_SW_XOFF(a) (0x1270 | (a) << 16)
#define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16)
#define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16)
#define NIX_AF_TL4X_GREEN(a) (0x1290 | (a) << 16)
#define NIX_AF_TL4X_YELLOW(a) (0x12A0 | (a) << 16)
#define NIX_AF_TL4X_RED(a) (0x12B0 | (a) << 16)
#define NIX_AF_TL4X_MD_DEBUG0(a) (0x12C0 | (a) << 16)
#define NIX_AF_TL4X_MD_DEBUG1(a) (0x12C8 | (a) << 16)
#define NIX_AF_TL4X_MD_DEBUG2(a) (0x12D0 | (a) << 16)
#define NIX_AF_TL4X_MD_DEBUG3(a) (0x12D8 | (a) << 16)
#define NIX_AF_TL4A_DEBUG (0x12e0)
#define NIX_AF_TL4B_DEBUG (0x12f0)
#define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16)
#define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16)
#define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16)
#define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16)
#define NIX_AF_MDQX_SCHED_STATE(a) (0x1440 | (a) << 16)
#define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450 | (a) << 16)
#define NIX_AF_MDQX_POINTERS(a) (0x1460 | (a) << 16)
#define NIX_AF_MDQX_SW_XOFF(a) (0x1470 | (a) << 16)
#define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16)
#define NIX_AF_MDQX_MD_DEBUG(a) (0x14C0 | (a) << 16)
#define NIX_AF_MDQX_PTR_FIFO(a) (0x14D0 | (a) << 16)
#define NIX_AF_MDQA_DEBUG (0x14e0)
#define NIX_AF_MDQB_DEBUG (0x14f0)
#define NIX_AF_TL3_TL2X_CFG(a) (0x1600 | (a) << 18)
#define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610 | (a) << 16)
#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3)
#define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) (0x1800 | (a) << 18 | (b) << 3)
#define NIX_AF_TX_MCASTX(a) (0x1900 | (a) << 15)
#define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1A00 | (a) << 16)
#define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1A10 | (a) << 16)
#define NIX_AF_RX_BPIDX_STATUS(a) (0x1A20 | (a) << 17)
#define NIX_AF_RX_CHANX_CFG(a) (0x1A30 | (a) << 15)
#define NIX_AF_CINT_TIMERX(a) (0x1A40 | (a) << 18)
#define NIX_AF_LSO_FORMATX_FIELDX(a, b) (0x1B00 | (a) << 16 | (b) << 3)
#define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17)
#define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17)
#define NIX_AF_LFX_TX_CFG2(a) (0x4028 | (a) << 17)
#define NIX_AF_LFX_SQS_BASE(a) (0x4030 | (a) << 17)
#define NIX_AF_LFX_RQS_CFG(a) (0x4040 | (a) << 17)
#define NIX_AF_LFX_RQS_BASE(a) (0x4050 | (a) << 17)
#define NIX_AF_LFX_CQS_CFG(a) (0x4060 | (a) << 17)
#define NIX_AF_LFX_CQS_BASE(a) (0x4070 | (a) << 17)
#define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17)
#define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090 | (a) << 17)
#define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17)
#define NIX_AF_LFX_RSS_CFG(a) (0x40C0 | (a) << 17)
#define NIX_AF_LFX_RSS_BASE(a) (0x40D0 | (a) << 17)
#define NIX_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 17)
#define NIX_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 17)
#define NIX_AF_LFX_CINTS_CFG(a) (0x4120 | (a) << 17)
#define NIX_AF_LFX_CINTS_BASE(a) (0x4130 | (a) << 17)
#define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140 | (a) << 17)
#define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148 | (a) << 17)
#define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150 | (a) << 17)
#define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158 | (a) << 17)
#define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170 | (a) << 17)
#define NIX_AF_LFX_TX_STATUS(a) (0x4180 | (a) << 17)
#define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) (0x4200 | (a) << 17 | (b) << 3)
#define NIX_AF_LFX_LOCKX(a, b) (0x4300 | (a) << 17 | (b) << 3)
#define NIX_AF_LFX_TX_STATX(a, b) (0x4400 | (a) << 17 | (b) << 3)
#define NIX_AF_LFX_RX_STATX(a, b) (0x4500 | (a) << 17 | (b) << 3)
#define NIX_AF_LFX_RSS_GRPX(a, b) (0x4600 | (a) << 17 | (b) << 3)
#define NIX_AF_RX_NPC_MC_RCV (0x4700)
#define NIX_AF_RX_NPC_MC_DROP (0x4710)
#define NIX_AF_RX_NPC_MIRROR_RCV (0x4720)
#define NIX_AF_RX_NPC_MIRROR_DROP (0x4730)
#define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16)
#define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17)
#define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16)
#define NIX_AF_SMQX_STATUS(a) (0x730 | (a) << 16)
#define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0 | (a) << 16)
#define NIX_PRIV_AF_INT_CFG (0x8000000)
#define NIX_PRIV_LFX_CFG (0x8000010)
#define NIX_PRIV_LFX_INT_CFG (0x8000020)
#define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030)
#define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0)
#define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16)
#define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32)
#define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12)
#define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0)
#define NIX_VLAN_ETYPE_MASK GENMASK_ULL(63, 48)
#define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16)
#define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16)
#define NIX_AF_TL3_PARENT_MASK GENMASK_ULL(23, 16)
#define NIX_AF_TL2_PARENT_MASK GENMASK_ULL(20, 16)
/* SSO */
#define SSO_AF_CONST (0x1000)
#define SSO_AF_CONST1 (0x1008)
#define SSO_AF_BLK_RST (0x10f8)
#define SSO_AF_LF_HWGRP_RST (0x10e0)
#define SSO_AF_RVU_LF_CFG_DEBUG (0x3800)
#define SSO_PRIV_LFX_HWGRP_CFG (0x10000)
#define SSO_PRIV_LFX_HWGRP_INT_CFG (0x20000)
/* SSOW */
#define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x0010)
#define SSOW_AF_LF_HWS_RST (0x0030)
#define SSOW_PRIV_LFX_HWS_CFG (0x1000)
#define SSOW_PRIV_LFX_HWS_INT_CFG (0x2000)
/* TIM */
#define TIM_AF_CONST (0x90)
#define TIM_PRIV_LFX_CFG (0x20000)
#define TIM_PRIV_LFX_INT_CFG (0x24000)
#define TIM_AF_RVU_LF_CFG_DEBUG (0x30000)
#define TIM_AF_BLK_RST (0x10)
#define TIM_AF_LF_RST (0x20)
/* CPT */
#define CPT_AF_CONSTANTS0 (0x0000)
#define CPT_AF_CONSTANTS1 (0x1000)
#define CPT_AF_DIAG (0x3000)
#define CPT_AF_ECO (0x4000)
#define CPT_AF_FLTX_INT(a) (0xa000ull | (u64)(a) << 3)
#define CPT_AF_FLTX_INT_W1S(a) (0xb000ull | (u64)(a) << 3)
#define CPT_AF_FLTX_INT_ENA_W1C(a) (0xc000ull | (u64)(a) << 3)
#define CPT_AF_FLTX_INT_ENA_W1S(a) (0xd000ull | (u64)(a) << 3)
#define CPT_AF_PSNX_EXE(a) (0xe000ull | (u64)(a) << 3)
#define CPT_AF_PSNX_EXE_W1S(a) (0xf000ull | (u64)(a) << 3)
#define CPT_AF_PSNX_LF(a) (0x10000ull | (u64)(a) << 3)
#define CPT_AF_PSNX_LF_W1S(a) (0x11000ull | (u64)(a) << 3)
#define CPT_AF_EXEX_CTL2(a) (0x12000ull | (u64)(a) << 3)
#define CPT_AF_EXEX_STS(a) (0x13000ull | (u64)(a) << 3)
#define CPT_AF_EXE_ERR_INFO (0x14000)
#define CPT_AF_EXEX_ACTIVE(a) (0x16000ull | (u64)(a) << 3)
#define CPT_AF_INST_REQ_PC (0x17000)
#define CPT_AF_INST_LATENCY_PC (0x18000)
#define CPT_AF_RD_REQ_PC (0x19000)
#define CPT_AF_RD_LATENCY_PC (0x1a000)
#define CPT_AF_RD_UC_PC (0x1b000)
#define CPT_AF_ACTIVE_CYCLES_PC (0x1c000)
#define CPT_AF_EXE_DBG_CTL (0x1d000)
#define CPT_AF_EXE_DBG_DATA (0x1e000)
#define CPT_AF_EXE_REQ_TIMER (0x1f000)
#define CPT_AF_EXEX_CTL(a) (0x20000ull | (u64)(a) << 3)
#define CPT_AF_EXE_PERF_CTL (0x21000)
#define CPT_AF_EXE_DBG_CNTX(a) (0x22000ull | (u64)(a) << 3)
#define CPT_AF_EXE_PERF_EVENT_CNT (0x23000)
#define CPT_AF_EXE_EPCI_INBX_CNT(a) (0x24000ull | (u64)(a) << 3)
#define CPT_AF_EXE_EPCI_OUTBX_CNT(a) (0x25000ull | (u64)(a) << 3)
#define CPT_AF_EXEX_UCODE_BASE(a) (0x26000ull | (u64)(a) << 3)
#define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3)
#define CPT_AF_LFX_CTL2(a) (0x29000ull | (u64)(a) << 3)
#define CPT_AF_CPTCLK_CNT (0x2a000)
#define CPT_AF_PF_FUNC (0x2b000)
#define CPT_AF_LFX_PTR_CTL(a) (0x2c000ull | (u64)(a) << 3)
#define CPT_AF_GRPX_THR(a) (0x2d000ull | (u64)(a) << 3)
#define CPT_AF_CTL (0x2e000ull)
#define CPT_AF_XEX_THR(a) (0x2f000ull | (u64)(a) << 3)
#define CPT_PRIV_LFX_CFG (0x41000)
#define CPT_PRIV_AF_INT_CFG (0x42000)
#define CPT_PRIV_LFX_INT_CFG (0x43000)
#define CPT_AF_LF_RST (0x44000)
#define CPT_AF_RVU_LF_CFG_DEBUG (0x45000)
#define CPT_AF_BLK_RST (0x46000)
#define CPT_AF_RVU_INT (0x47000)
#define CPT_AF_RVU_INT_W1S (0x47008)
#define CPT_AF_RVU_INT_ENA_W1S (0x47010)
#define CPT_AF_RVU_INT_ENA_W1C (0x47018)
#define CPT_AF_RAS_INT (0x47020)
#define CPT_AF_RAS_INT_W1S (0x47028)
#define CPT_AF_RAS_INT_ENA_W1S (0x47030)
#define CPT_AF_RAS_INT_ENA_W1C (0x47038)
#define CPT_AF_CTX_FLUSH_TIMER (0x48000ull)
#define CPT_AF_CTX_ERR (0x48008ull)
#define CPT_AF_CTX_ENC_ID (0x48010ull)
#define CPT_AF_CTX_MIS_PC (0x49400ull)
#define CPT_AF_CTX_HIT_PC (0x49408ull)
#define CPT_AF_CTX_AOP_PC (0x49410ull)
#define CPT_AF_CTX_AOP_LATENCY_PC (0x49418ull)
#define CPT_AF_CTX_IFETCH_PC (0x49420ull)
#define CPT_AF_CTX_IFETCH_LATENCY_PC (0x49428ull)
#define CPT_AF_CTX_FFETCH_PC (0x49430ull)
#define CPT_AF_CTX_FFETCH_LATENCY_PC (0x49438ull)
#define CPT_AF_CTX_WBACK_PC (0x49440ull)
#define CPT_AF_CTX_WBACK_LATENCY_PC (0x49448ull)
#define CPT_AF_CTX_PSH_PC (0x49450ull)
#define CPT_AF_CTX_PSH_LATENCY_PC (0x49458ull)
#define CPT_AF_CTX_CAM_DATA(a) (0x49800ull | (u64)(a) << 3)
#define CPT_AF_RXC_CFG1 (0x50000ull)
#define CPT_AF_RXC_TIME (0x50010ull)
#define CPT_AF_RXC_TIME_CFG (0x50018ull)
#define CPT_AF_RXC_DFRG (0x50020ull)
#define CPT_AF_RXC_ACTIVE_STS (0x50028ull)
#define CPT_AF_RXC_ZOMBIE_STS (0x50030ull)
#define CPT_AF_X2PX_LINK_CFG(a) (0x51000ull | (u64)(a) << 3)
#define AF_BAR2_ALIASX(a, b) (0x9100000ull | (a) << 12 | (b))
#define CPT_AF_BAR2_SEL 0x9000000
#define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b)
#define CPT_AF_LF_CTL2_SHIFT 3
#define CPT_AF_LF_SSO_PF_FUNC_SHIFT 32
#define CPT_LF_CTL 0x10
#define CPT_LF_INPROG 0x40
#define CPT_LF_Q_SIZE 0x100
#define CPT_LF_Q_INST_PTR 0x110
#define CPT_LF_Q_GRP_PTR 0x120
#define CPT_LF_CTX_FLUSH 0x510
#define NPC_AF_BLK_RST (0x00040)
/* NPC */
#define NPC_AF_CFG (0x00000)
#define NPC_AF_ACTIVE_PC (0x00010)
#define NPC_AF_CONST (0x00020)
#define NPC_AF_CONST1 (0x00030)
#define NPC_AF_BLK_RST (0x00040)
#define NPC_AF_MCAM_SCRUB_CTL (0x000a0)
#define NPC_AF_KCAM_SCRUB_CTL (0x000b0)
#define NPC_AF_CONST2 (0x00100)
#define NPC_AF_CONST3 (0x00110)
#define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3)
#define NPC_AF_PCK_CFG (0x00600)
#define NPC_AF_PCK_DEF_OL2 (0x00610)
#define NPC_AF_PCK_DEF_OIP4 (0x00620)
#define NPC_AF_PCK_DEF_OIP6 (0x00630)
#define NPC_AF_PCK_DEF_IIP4 (0x00640)
#define NPC_AF_INTFX_HASHX_RESULT_CTRL(a, b) (0x006c0 | (a) << 4 | (b) << 3)
#define NPC_AF_INTFX_HASHX_MASKX(a, b, c) (0x00700 | (a) << 5 | (b) << 4 | (c) << 3)
#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3)
#define NPC_AF_INTFX_HASHX_CFG(a, b) (0x00b00 | (a) << 6 | (b) << 4)
#define NPC_AF_INTFX_SECRET_KEY0(a) (0x00e00 | (a) << 3)
#define NPC_AF_INTFX_SECRET_KEY1(a) (0x00e20 | (a) << 3)
#define NPC_AF_INTFX_SECRET_KEY2(a) (0x00e40 | (a) << 3)
#define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8)
#define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6)
#define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6)
#define NPC_AF_PKINDX_TYPE(a) (0x80010ull | (a) << 6)
#define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3)
#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \
(0x100000 | (a) << 14 | (b) << 6 | (c) << 3)
#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \
(0x100020 | (a) << 14 | (b) << 6)
#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \
(0x100028 | (a) << 14 | (b) << 6)
#define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3)
#define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3)
#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \
(0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3)
#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \
(0x980000 | (a) << 16 | (b) << 12 | (c) << 3)
#define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8)
#define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4)
#define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4)
#define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4)
#define NPC_AF_LKUP_CTL (0x2000000)
#define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4)
#define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4)
#define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4)
#define NPC_AF_DBG_CTL (0x3000000)
#define NPC_AF_DBG_STATUS (0x3000010)
#define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8)
#define NPC_AF_IKPU_ERR_CTL (0x3000080)
#define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8)
#define NPC_AF_MCAM_DBG (0x3001000)
#define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4)
#define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4)
#define NPC_AF_EXACT_MEM_ENTRY(a, b) (0x300000 | (a) << 15 | (b) << 3)
#define NPC_AF_EXACT_CAM_ENTRY(a) (0xC00 | (a) << 3)
#define NPC_AF_INTFX_EXACT_MASK(a) (0x660 | (a) << 3)
#define NPC_AF_INTFX_EXACT_RESULT_CTL(a)(0x680 | (a) << 3)
#define NPC_AF_INTFX_EXACT_CFG(a) (0xA00 | (a) << 3)
#define NPC_AF_INTFX_EXACT_SECRET0(a) (0xE00 | (a) << 3)
#define NPC_AF_INTFX_EXACT_SECRET1(a) (0xE20 | (a) << 3)
#define NPC_AF_INTFX_EXACT_SECRET2(a) (0xE40 | (a) << 3)
#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) ({ \
u64 offset; \
\
offset = (0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000000ull | (a) << 8 | (b) << 22 | (c) << 3); \
offset; })
#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) ({ \
u64 offset; \
\
offset = (0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000010ull | (a) << 8 | (b) << 22 | (c) << 3); \
offset; })
#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) ({ \
u64 offset; \
\
offset = (0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000020ull | (a) << 8 | (b) << 22 | (c) << 3); \
offset; })
#define NPC_AF_MCAMEX_BANKX_CFG(a, b) ({ \
u64 offset; \
\
offset = (0x1800000ull | (a) << 8 | (b) << 4); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000038ull | (a) << 8 | (b) << 22); \
offset; })
#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) ({ \
u64 offset; \
\
offset = (0x1900000ull | (a) << 8 | (b) << 4); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000040ull | (a) << 8 | (b) << 22); \
offset; }) \
#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) ({ \
u64 offset; \
\
offset = (0x1900008ull | (a) << 8 | (b) << 4); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000048ull | (a) << 8 | (b) << 22); \
offset; }) \
#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) ({ \
u64 offset; \
\
offset = (0x1880000ull | (a) << 8 | (b) << 4); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000050ull | (a) << 8 | (b) << 22); \
offset; }) \
#define NPC_AF_MATCH_STATX(a) ({ \
u64 offset; \
\
offset = (0x1880008ull | (a) << 8); \
if (rvu->hw->npc_ext_set) \
offset = (0x8000078ull | (a) << 8); \
offset; }) \
/* NDC */
#define NDC_AF_CONST (0x00000)
#define NDC_AF_CLK_EN (0x00020)
#define NDC_AF_CTL (0x00030)
#define NDC_AF_BANK_CTL (0x00040)
#define NDC_AF_BANK_CTL_DONE (0x00048)
#define NDC_AF_INTR (0x00058)
#define NDC_AF_INTR_W1S (0x00060)
#define NDC_AF_INTR_ENA_W1S (0x00068)
#define NDC_AF_INTR_ENA_W1C (0x00070)
#define NDC_AF_ACTIVE_PC (0x00078)
#define NDC_AF_CAMS_RD_INTERVAL (0x00080)
#define NDC_AF_BP_TEST_ENABLE (0x001F8)
#define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3)
#define NDC_AF_BLK_RST (0x002F0)
#define NDC_PRIV_AF_INT_CFG (0x002F8)
#define NDC_AF_HASHX(a) (0x00300 | (a) << 3)
#define NDC_AF_PORTX_RTX_RWX_REQ_PC(a, b, c) \
(0x00C00 | (a) << 5 | (b) << 4 | (c) << 3)
#define NDC_AF_PORTX_RTX_RWX_OSTDN_PC(a, b, c) \
(0x00D00 | (a) << 5 | (b) << 4 | (c) << 3)
#define NDC_AF_PORTX_RTX_RWX_LAT_PC(a, b, c) \
(0x00E00 | (a) << 5 | (b) << 4 | (c) << 3)
#define NDC_AF_PORTX_RTX_CANT_ALLOC_PC(a, b) \
(0x00F00 | (a) << 5 | (b) << 4)
#define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3)
#define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3)
#define NDC_AF_BANKX_LINEX_METADATA(a, b) \
(0x10000 | (a) << 12 | (b) << 3)
/* LBK */
#define LBK_CONST (0x10ull)
#define LBK_LINK_CFG_P2X (0x400ull)
#define LBK_LINK_CFG_X2P (0x408ull)
#define LBK_CONST_CHANS GENMASK_ULL(47, 32)
#define LBK_CONST_DST GENMASK_ULL(31, 28)
#define LBK_CONST_SRC GENMASK_ULL(27, 24)
#define LBK_CONST_BUF_SIZE GENMASK_ULL(23, 0)
#define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16)
#define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6)
#define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0)
/* APR */
#define APR_AF_LMT_CFG (0x000ull)
#define APR_AF_LMT_MAP_BASE (0x008ull)
#define APR_AF_LMT_CTL (0x010ull)
#define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23
#define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22
#define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21
#define LMTST_THROTTLE_MASK GENMASK_ULL(38, 35)
#define LMTST_WR_PEND_MAX 15
#endif /* RVU_REG_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
+477
View File
@@ -0,0 +1,477 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2024 Marvell.
*
*/
#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "rvu.h"
#include "rvu_reg.h"
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
static struct _req_type __maybe_unused \
*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
{ \
struct _req_type *req; \
\
req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
sizeof(struct _rsp_type)); \
if (!req) \
return NULL; \
req->hdr.sig = OTX2_MBOX_REQ_SIG; \
req->hdr.id = _id; \
return req; \
}
MBOX_UP_REP_MESSAGES
#undef M
static int rvu_rep_up_notify(struct rvu *rvu, struct rep_event *event)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, event->pcifunc);
struct rep_event *msg;
int pf;
pf = rvu_get_pf(rvu->pdev, event->pcifunc);
if (event->event & RVU_EVENT_MAC_ADDR_CHANGE)
ether_addr_copy(pfvf->mac_addr, event->evt_data.mac);
mutex_lock(&rvu->mbox_lock);
msg = otx2_mbox_alloc_msg_rep_event_up_notify(rvu, pf);
if (!msg) {
mutex_unlock(&rvu->mbox_lock);
return -ENOMEM;
}
msg->hdr.pcifunc = event->pcifunc;
msg->event = event->event;
memcpy(&msg->evt_data, &event->evt_data, sizeof(struct rep_evt_data));
otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf);
otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf);
otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pf);
mutex_unlock(&rvu->mbox_lock);
return 0;
}
static void rvu_rep_wq_handler(struct work_struct *work)
{
struct rvu *rvu = container_of(work, struct rvu, rep_evt_work);
struct rep_evtq_ent *qentry;
struct rep_event *event;
unsigned long flags;
do {
spin_lock_irqsave(&rvu->rep_evtq_lock, flags);
qentry = list_first_entry_or_null(&rvu->rep_evtq_head,
struct rep_evtq_ent,
node);
if (qentry)
list_del(&qentry->node);
spin_unlock_irqrestore(&rvu->rep_evtq_lock, flags);
if (!qentry)
break; /* nothing more to process */
event = &qentry->event;
rvu_rep_up_notify(rvu, event);
kfree(qentry);
} while (1);
}
int rvu_mbox_handler_rep_event_notify(struct rvu *rvu, struct rep_event *req,
struct msg_rsp *rsp)
{
struct rep_evtq_ent *qentry;
/* The mailbox dispatcher normalises only the header pcifunc; the
* nested struct rep_event::pcifunc body field is sender-controlled
* and is later used by rvu_rep_up_notify() to index rvu->pf[] /
* rvu->hwvf[]. Reject out-of-range body selectors before queueing.
*/
if (!is_pf_func_valid(rvu, req->pcifunc))
return -EINVAL;
qentry = kmalloc_obj(*qentry, GFP_ATOMIC);
if (!qentry)
return -ENOMEM;
qentry->event = *req;
spin_lock(&rvu->rep_evtq_lock);
list_add_tail(&qentry->node, &rvu->rep_evtq_head);
spin_unlock(&rvu->rep_evtq_lock);
queue_work(rvu->rep_evt_wq, &rvu->rep_evt_work);
return 0;
}
int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable)
{
struct rep_event *req;
int pf;
if (!is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)))
return 0;
pf = rvu_get_pf(rvu->pdev, rvu->rep_pcifunc);
mutex_lock(&rvu->mbox_lock);
req = otx2_mbox_alloc_msg_rep_event_up_notify(rvu, pf);
if (!req) {
mutex_unlock(&rvu->mbox_lock);
return -ENOMEM;
}
req->hdr.pcifunc = rvu->rep_pcifunc;
req->event |= RVU_EVENT_PFVF_STATE;
req->pcifunc = pcifunc;
req->evt_data.vf_state = enable;
otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf);
otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf);
mutex_unlock(&rvu->mbox_lock);
return 0;
}
#define RVU_LF_RX_STATS(reg) \
rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, reg))
#define RVU_LF_TX_STATS(reg) \
rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, reg))
int rvu_mbox_handler_nix_lf_stats(struct rvu *rvu,
struct nix_stats_req *req,
struct nix_stats_rsp *rsp)
{
u16 pcifunc = req->pcifunc;
int nixlf, blkaddr, err;
struct msg_req rst_req;
struct msg_rsp rst_rsp;
err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
if (err)
return 0;
if (req->reset) {
rst_req.hdr.pcifunc = pcifunc;
return rvu_mbox_handler_nix_stats_rst(rvu, &rst_req, &rst_rsp);
}
rsp->rx.octs = RVU_LF_RX_STATS(RX_OCTS);
rsp->rx.ucast = RVU_LF_RX_STATS(RX_UCAST);
rsp->rx.bcast = RVU_LF_RX_STATS(RX_BCAST);
rsp->rx.mcast = RVU_LF_RX_STATS(RX_MCAST);
rsp->rx.drop = RVU_LF_RX_STATS(RX_DROP);
rsp->rx.err = RVU_LF_RX_STATS(RX_ERR);
rsp->rx.drop_octs = RVU_LF_RX_STATS(RX_DROP_OCTS);
rsp->rx.drop_mcast = RVU_LF_RX_STATS(RX_DRP_MCAST);
rsp->rx.drop_bcast = RVU_LF_RX_STATS(RX_DRP_BCAST);
rsp->tx.octs = RVU_LF_TX_STATS(TX_OCTS);
rsp->tx.ucast = RVU_LF_TX_STATS(TX_UCAST);
rsp->tx.bcast = RVU_LF_TX_STATS(TX_BCAST);
rsp->tx.mcast = RVU_LF_TX_STATS(TX_MCAST);
rsp->tx.drop = RVU_LF_TX_STATS(TX_DROP);
rsp->pcifunc = req->pcifunc;
return 0;
}
static u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc)
{
int id;
for (id = 0; id < rvu->rep_cnt; id++)
if (rvu->rep2pfvf_map[id] == pcifunc)
return id;
return 0;
}
static int rvu_rep_tx_vlan_cfg(struct rvu *rvu, u16 pcifunc,
u16 vlan_tci, int *vidx)
{
struct nix_vtag_config_rsp rsp = {};
struct nix_vtag_config req = {};
u64 etype = ETH_P_8021Q;
int err;
/* Insert vlan tag */
req.hdr.pcifunc = pcifunc;
req.vtag_size = VTAGSIZE_T4;
req.cfg_type = 0; /* tx vlan cfg */
req.tx.cfg_vtag0 = true;
req.tx.vtag0 = FIELD_PREP(NIX_VLAN_ETYPE_MASK, etype) | vlan_tci;
err = rvu_mbox_handler_nix_vtag_cfg(rvu, &req, &rsp);
if (err) {
dev_err(rvu->dev, "Tx vlan config failed\n");
return err;
}
*vidx = rsp.vtag0_idx;
return 0;
}
static int rvu_rep_rx_vlan_cfg(struct rvu *rvu, u16 pcifunc)
{
struct nix_vtag_config req = {};
struct nix_vtag_config_rsp rsp;
/* config strip, capture and size */
req.hdr.pcifunc = pcifunc;
req.vtag_size = VTAGSIZE_T4;
req.cfg_type = 1; /* rx vlan cfg */
req.rx.vtag_type = NIX_AF_LFX_RX_VTAG_TYPE0;
req.rx.strip_vtag = true;
req.rx.capture_vtag = false;
return rvu_mbox_handler_nix_vtag_cfg(rvu, &req, &rsp);
}
static int rvu_rep_install_rx_rule(struct rvu *rvu, u16 pcifunc,
u16 entry, bool rte)
{
struct npc_install_flow_req req = {};
struct npc_install_flow_rsp rsp = {};
struct rvu_pfvf *pfvf;
u16 vlan_tci, rep_id;
pfvf = rvu_get_pfvf(rvu, pcifunc);
/* To steer the traffic from Representee to Representor */
rep_id = rvu_rep_get_vlan_id(rvu, pcifunc);
if (rte) {
vlan_tci = rep_id | BIT_ULL(8);
req.vf = rvu->rep_pcifunc;
req.op = NIX_RX_ACTIONOP_UCAST;
req.index = rep_id;
} else {
vlan_tci = rep_id;
req.vf = pcifunc;
req.op = NIX_RX_ACTION_DEFAULT;
}
rvu_rep_rx_vlan_cfg(rvu, req.vf);
req.entry = entry;
req.hdr.pcifunc = 0; /* AF is requester */
req.features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_VLAN_ETYPE_CTAG);
req.vtag0_valid = true;
req.vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE0;
req.packet.vlan_etype = cpu_to_be16(ETH_P_8021Q);
req.mask.vlan_etype = cpu_to_be16(ETH_P_8021Q);
req.packet.vlan_tci = cpu_to_be16(vlan_tci);
req.mask.vlan_tci = cpu_to_be16(0xffff);
req.channel = RVU_SWITCH_LBK_CHAN;
req.chan_mask = 0xffff;
req.intf = pfvf->nix_rx_intf;
return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
}
static int rvu_rep_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry,
bool rte)
{
struct npc_install_flow_req req = {};
struct npc_install_flow_rsp rsp = {};
struct rvu_pfvf *pfvf;
int vidx, err;
u16 vlan_tci;
u8 lbkid;
pfvf = rvu_get_pfvf(rvu, pcifunc);
vlan_tci = rvu_rep_get_vlan_id(rvu, pcifunc);
if (rte)
vlan_tci |= BIT_ULL(8);
err = rvu_rep_tx_vlan_cfg(rvu, pcifunc, vlan_tci, &vidx);
if (err)
return err;
lbkid = pfvf->nix_blkaddr == BLKADDR_NIX0 ? 0 : 1;
req.hdr.pcifunc = 0; /* AF is requester */
if (rte) {
req.vf = pcifunc;
} else {
req.vf = rvu->rep_pcifunc;
req.packet.sq_id = vlan_tci;
req.mask.sq_id = 0xffff;
}
req.entry = entry;
req.intf = pfvf->nix_tx_intf;
req.op = NIX_TX_ACTIONOP_UCAST_CHAN;
req.index = (lbkid << 8) | RVU_SWITCH_LBK_CHAN;
req.set_cntr = 1;
req.vtag0_def = vidx;
req.vtag0_op = 1;
return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
}
int rvu_rep_install_mcam_rules(struct rvu *rvu)
{
struct rvu_switch *rswitch = &rvu->rswitch;
u16 start = rswitch->start_entry;
struct rvu_hwinfo *hw = rvu->hw;
u16 pcifunc, entry = 0;
int pf, vf, numvfs;
int err, nixlf, i;
u8 rep;
for (pf = 1; pf < hw->total_pfs; pf++) {
if (!is_pf_cgxmapped(rvu, pf))
continue;
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0);
rvu_get_nix_blkaddr(rvu, pcifunc);
rep = true;
for (i = 0; i < 2; i++) {
err = rvu_rep_install_rx_rule(rvu, pcifunc,
start + entry, rep);
if (err)
return err;
rswitch->entry2pcifunc[entry++] = pcifunc;
err = rvu_rep_install_tx_rule(rvu, pcifunc,
start + entry, rep);
if (err)
return err;
rswitch->entry2pcifunc[entry++] = pcifunc;
rep = false;
}
rvu_get_pf_numvfs(rvu, pf, &numvfs, NULL);
for (vf = 0; vf < numvfs; vf++) {
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, vf + 1);
rvu_get_nix_blkaddr(rvu, pcifunc);
/* Skip installimg rules if nixlf is not attached */
err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
if (err)
continue;
rep = true;
for (i = 0; i < 2; i++) {
err = rvu_rep_install_rx_rule(rvu, pcifunc,
start + entry,
rep);
if (err)
return err;
rswitch->entry2pcifunc[entry++] = pcifunc;
err = rvu_rep_install_tx_rule(rvu, pcifunc,
start + entry,
rep);
if (err)
return err;
rswitch->entry2pcifunc[entry++] = pcifunc;
rep = false;
}
}
}
/* Initialize the wq for handling REP events */
spin_lock_init(&rvu->rep_evtq_lock);
INIT_LIST_HEAD(&rvu->rep_evtq_head);
INIT_WORK(&rvu->rep_evt_work, rvu_rep_wq_handler);
rvu->rep_evt_wq = alloc_workqueue("rep_evt_wq", WQ_PERCPU, 0);
if (!rvu->rep_evt_wq) {
dev_err(rvu->dev, "REP workqueue allocation failed\n");
return -ENOMEM;
}
return 0;
}
void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena)
{
struct rvu_switch *rswitch = &rvu->rswitch;
struct npc_mcam *mcam = &rvu->hw->mcam;
u32 max = rswitch->used_entries;
int blkaddr;
u16 entry;
if (!rswitch->used_entries)
return;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
if (blkaddr < 0)
return;
rvu_switch_enable_lbk_link(rvu, pcifunc, ena);
mutex_lock(&mcam->lock);
for (entry = 0; entry < max; entry++) {
if (rswitch->entry2pcifunc[entry] == pcifunc)
npc_enable_mcam_entry(rvu, mcam, blkaddr, entry, ena);
}
mutex_unlock(&mcam->lock);
}
int rvu_rep_pf_init(struct rvu *rvu)
{
u16 pcifunc = rvu->rep_pcifunc;
struct rvu_pfvf *pfvf;
pfvf = rvu_get_pfvf(rvu, pcifunc);
set_bit(NIXLF_INITIALIZED, &pfvf->flags);
rvu_switch_enable_lbk_link(rvu, pcifunc, true);
rvu_rep_rx_vlan_cfg(rvu, pcifunc);
return 0;
}
int rvu_mbox_handler_esw_cfg(struct rvu *rvu, struct esw_cfg_req *req,
struct msg_rsp *rsp)
{
if (req->hdr.pcifunc != rvu->rep_pcifunc)
return 0;
rvu->rep_mode = req->ena;
if (!rvu->rep_mode)
rvu_npc_free_mcam_entries(rvu, req->hdr.pcifunc, -1);
return 0;
}
int rvu_mbox_handler_get_rep_cnt(struct rvu *rvu, struct msg_req *req,
struct get_rep_cnt_rsp *rsp)
{
int pf, vf, numvfs, hwvf, rep = 0;
u16 pcifunc;
rvu->rep_pcifunc = req->hdr.pcifunc;
rsp->rep_cnt = rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs;
rvu->rep_cnt = rsp->rep_cnt;
rvu->rep2pfvf_map = devm_kzalloc(rvu->dev, rvu->rep_cnt *
sizeof(u16), GFP_KERNEL);
if (!rvu->rep2pfvf_map)
return -ENOMEM;
for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
if (!is_pf_cgxmapped(rvu, pf))
continue;
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0);
rvu->rep2pfvf_map[rep] = pcifunc;
rsp->rep_pf_map[rep] = pcifunc;
rep++;
rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
for (vf = 0; vf < numvfs; vf++) {
rvu->rep2pfvf_map[rep] = pcifunc |
((vf + 1) & RVU_PFVF_FUNC_MASK);
rsp->rep_pf_map[rep] = rvu->rep2pfvf_map[rep];
rep++;
}
}
return 0;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_sdp.c
+123
View File
@@ -0,0 +1,123 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2021 Marvell.
*
*/
#include <linux/pci.h>
#include "rvu.h"
/* SDP PF device id */
#define PCI_DEVID_OTX2_SDP_PF 0xA0F6
/* Maximum SDP blocks in a chip */
#define MAX_SDP 2
/* SDP PF number */
static int sdp_pf_num[MAX_SDP] = {-1, -1};
bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc)
{
u16 pf = rvu_get_pf(rvu->pdev, pcifunc);
u32 found = 0, i = 0;
while (i < MAX_SDP) {
if (pf == sdp_pf_num[i])
found = 1;
i++;
}
if (!found)
return false;
return true;
}
bool is_sdp_pf(struct rvu *rvu, u16 pcifunc)
{
return (is_sdp_pfvf(rvu, pcifunc) &&
!(pcifunc & RVU_PFVF_FUNC_MASK));
}
#define RVU_SDP_VF_DEVID 0xA0F7
bool is_sdp_vf(struct rvu *rvu, u16 pcifunc)
{
if (!(pcifunc & ~RVU_PFVF_FUNC_MASK))
return (rvu->vf_devid == RVU_SDP_VF_DEVID);
return (is_sdp_pfvf(rvu, pcifunc) &&
!!(pcifunc & RVU_PFVF_FUNC_MASK));
}
int rvu_sdp_init(struct rvu *rvu)
{
struct pci_dev *pdev = NULL;
struct rvu_pfvf *pfvf;
u32 i = 0;
if (rvu->fwdata && rvu->fwdata->channel_data.valid) {
sdp_pf_num[0] = 0;
pfvf = &rvu->pf[sdp_pf_num[0]];
pfvf->sdp_info = &rvu->fwdata->channel_data.info;
return 0;
}
while ((i < MAX_SDP) && (pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVID_OTX2_SDP_PF,
pdev)) != NULL) {
/* The RVU PF number is one less than bus number */
sdp_pf_num[i] = pdev->bus->number - 1;
pfvf = &rvu->pf[sdp_pf_num[i]];
pfvf->sdp_info = devm_kzalloc(rvu->dev,
sizeof(struct sdp_node_info),
GFP_KERNEL);
if (!pfvf->sdp_info) {
pci_dev_put(pdev);
return -ENOMEM;
}
dev_info(rvu->dev, "SDP PF number:%d\n", sdp_pf_num[i]);
i++;
}
pci_dev_put(pdev);
return 0;
}
int
rvu_mbox_handler_set_sdp_chan_info(struct rvu *rvu,
struct sdp_chan_info_msg *req,
struct msg_rsp *rsp)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
memcpy(pfvf->sdp_info, &req->info, sizeof(struct sdp_node_info));
dev_info(rvu->dev, "AF: SDP%d max_vfs %d num_pf_rings %d pf_srn %d\n",
req->info.node_id, req->info.max_vfs, req->info.num_pf_rings,
req->info.pf_srn);
return 0;
}
int
rvu_mbox_handler_get_sdp_chan_info(struct rvu *rvu, struct msg_req *req,
struct sdp_get_chan_info_msg *rsp)
{
struct rvu_hwinfo *hw = rvu->hw;
int blkaddr;
if (!hw->cap.programmable_chans) {
rsp->chan_base = NIX_CHAN_SDP_CH_START;
rsp->num_chan = NIX_CHAN_SDP_NUM_CHANS;
} else {
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
rsp->chan_base = hw->sdp_chan_base;
rsp->num_chan = rvu_read64(rvu, blkaddr, NIX_AF_CONST1) & 0xFFFUL;
}
return 0;
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
+879
View File
@@ -0,0 +1,879 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2018 Marvell.
*
*/
#ifndef RVU_STRUCT_H
#define RVU_STRUCT_H
/* RVU Block revision IDs */
#define RVU_BLK_RVUM_REVID 0x01
#define RVU_MULTI_BLK_VER 0x7ULL
#define NIX_MAX_CTX_SIZE 128
/* RVU Block Address Enumeration */
enum rvu_block_addr_e {
BLKADDR_RVUM = 0x0ULL,
BLKADDR_LMT = 0x1ULL,
BLKADDR_MSIX = 0x2ULL,
BLKADDR_NPA = 0x3ULL,
BLKADDR_NIX0 = 0x4ULL,
BLKADDR_NIX1 = 0x5ULL,
BLKADDR_NPC = 0x6ULL,
BLKADDR_SSO = 0x7ULL,
BLKADDR_SSOW = 0x8ULL,
BLKADDR_TIM = 0x9ULL,
BLKADDR_CPT0 = 0xaULL,
BLKADDR_CPT1 = 0xbULL,
BLKADDR_NDC_NIX0_RX = 0xcULL,
BLKADDR_NDC_NIX0_TX = 0xdULL,
BLKADDR_NDC_NPA0 = 0xeULL,
BLKADDR_NDC_NIX1_RX = 0x10ULL,
BLKADDR_NDC_NIX1_TX = 0x11ULL,
BLKADDR_APR = 0x16ULL,
BLKADDR_MBOX = 0x1bULL,
BLK_COUNT = 0x1cULL,
};
/* RVU Block Type Enumeration */
enum rvu_block_type_e {
BLKTYPE_RVUM = 0x0,
BLKTYPE_MSIX = 0x1,
BLKTYPE_LMT = 0x2,
BLKTYPE_NIX = 0x3,
BLKTYPE_NPA = 0x4,
BLKTYPE_NPC = 0x5,
BLKTYPE_SSO = 0x6,
BLKTYPE_SSOW = 0x7,
BLKTYPE_TIM = 0x8,
BLKTYPE_CPT = 0x9,
BLKTYPE_NDC = 0xa,
BLKTYPE_MBOX = 0x13,
BLKTYPE_MAX = 0x13,
};
/* RVU Admin function Interrupt Vector Enumeration */
enum rvu_af_int_vec_e {
RVU_AF_INT_VEC_POISON = 0x0,
RVU_AF_INT_VEC_PFFLR = 0x1,
RVU_AF_INT_VEC_PFME = 0x2,
RVU_AF_INT_VEC_GEN = 0x3,
RVU_AF_INT_VEC_MBOX = 0x4,
RVU_AF_INT_VEC_CNT = 0x5,
};
/* CPT Admin function Interrupt Vector Enumeration */
enum cpt_af_int_vec_e {
CPT_AF_INT_VEC_FLT0 = 0x0,
CPT_AF_INT_VEC_FLT1 = 0x1,
CPT_AF_INT_VEC_RVU = 0x2,
CPT_AF_INT_VEC_RAS = 0x3,
CPT_AF_INT_VEC_CNT = 0x4,
};
enum cpt_cn10k_flt_int_vec_e {
CPT_10K_AF_INT_VEC_FLT0 = 0x0,
CPT_10K_AF_INT_VEC_FLT1 = 0x1,
CPT_10K_AF_INT_VEC_FLT2 = 0x2,
CPT_10K_AF_INT_VEC_FLT_MAX = 0x3,
};
/* NPA Admin function Interrupt Vector Enumeration */
enum npa_af_int_vec_e {
NPA_AF_INT_VEC_RVU = 0x0,
NPA_AF_INT_VEC_GEN = 0x1,
NPA_AF_INT_VEC_AQ_DONE = 0x2,
NPA_AF_INT_VEC_AF_ERR = 0x3,
NPA_AF_INT_VEC_POISON = 0x4,
NPA_AF_INT_VEC_CNT = 0x5,
};
/* NIX Admin function Interrupt Vector Enumeration */
enum nix_af_int_vec_e {
NIX_AF_INT_VEC_RVU = 0x0,
NIX_AF_INT_VEC_GEN = 0x1,
NIX_AF_INT_VEC_AQ_DONE = 0x2,
NIX_AF_INT_VEC_AF_ERR = 0x3,
NIX_AF_INT_VEC_POISON = 0x4,
NIX_AF_INT_VEC_CNT = 0x5,
};
/**
* RVU PF Interrupt Vector Enumeration
*/
enum rvu_pf_int_vec_e {
RVU_PF_INT_VEC_VFFLR0 = 0x0,
RVU_PF_INT_VEC_VFFLR1 = 0x1,
RVU_PF_INT_VEC_VFME0 = 0x2,
RVU_PF_INT_VEC_VFME1 = 0x3,
RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4,
RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5,
RVU_PF_INT_VEC_AFPF_MBOX = 0x6,
RVU_PF_INT_VEC_CNT = 0x7,
};
/* NPA admin queue completion enumeration */
enum npa_aq_comp {
NPA_AQ_COMP_NOTDONE = 0x0,
NPA_AQ_COMP_GOOD = 0x1,
NPA_AQ_COMP_SWERR = 0x2,
NPA_AQ_COMP_CTX_POISON = 0x3,
NPA_AQ_COMP_CTX_FAULT = 0x4,
NPA_AQ_COMP_LOCKERR = 0x5,
};
/* NPA admin queue context types */
enum npa_aq_ctype {
NPA_AQ_CTYPE_AURA = 0x0,
NPA_AQ_CTYPE_POOL = 0x1,
};
/* NPA admin queue instruction opcodes */
enum npa_aq_instop {
NPA_AQ_INSTOP_NOP = 0x0,
NPA_AQ_INSTOP_INIT = 0x1,
NPA_AQ_INSTOP_WRITE = 0x2,
NPA_AQ_INSTOP_READ = 0x3,
NPA_AQ_INSTOP_LOCK = 0x4,
NPA_AQ_INSTOP_UNLOCK = 0x5,
};
/* ALLOC/FREE input queues Enumeration from coprocessors */
enum npa_inpq {
NPA_INPQ_NIX0_RX = 0x0,
NPA_INPQ_NIX0_TX = 0x1,
NPA_INPQ_NIX1_RX = 0x2,
NPA_INPQ_NIX1_TX = 0x3,
NPA_INPQ_SSO = 0x4,
NPA_INPQ_TIM = 0x5,
NPA_INPQ_DPI = 0x6,
NPA_INPQ_AURA_OP = 0xe,
NPA_INPQ_INTERNAL_RSV = 0xf,
};
/* NPA admin queue instruction structure */
struct npa_aq_inst_s {
u64 op : 4; /* W0 */
u64 ctype : 4;
u64 lf : 9;
u64 reserved_17_23 : 7;
u64 cindex : 20;
u64 reserved_44_62 : 19;
u64 doneint : 1;
u64 res_addr; /* W1 */
};
/* NPA admin queue result structure */
struct npa_aq_res_s {
u64 op : 4; /* W0 */
u64 ctype : 4;
u64 compcode : 8;
u64 doneint : 1;
u64 reserved_17_63 : 47;
u64 reserved_64_127; /* W1 */
};
struct npa_aura_s {
u64 pool_addr; /* W0 */
u64 ena : 1; /* W1 */
u64 reserved_65 : 2;
u64 pool_caching : 1;
u64 pool_way_mask : 16;
u64 avg_con : 9;
u64 reserved_93 : 1;
u64 pool_drop_ena : 1;
u64 aura_drop_ena : 1;
u64 bp_ena : 2;
u64 reserved_98_103 : 6;
u64 aura_drop : 8;
u64 shift : 6;
u64 reserved_118_119 : 2;
u64 avg_level : 8;
u64 count : 36; /* W2 */
u64 reserved_164_167 : 4;
u64 nix0_bpid : 9;
u64 reserved_177_179 : 3;
u64 nix1_bpid : 9;
u64 reserved_189_191 : 3;
u64 limit : 36; /* W3 */
u64 reserved_228_231 : 4;
u64 bp : 8;
u64 reserved_241_243 : 3;
u64 fc_be : 1;
u64 fc_ena : 1;
u64 fc_up_crossing : 1;
u64 fc_stype : 2;
u64 fc_hyst_bits : 4;
u64 reserved_252_255 : 4;
u64 fc_addr; /* W4 */
u64 pool_drop : 8; /* W5 */
u64 update_time : 16;
u64 err_int : 8;
u64 err_int_ena : 8;
u64 thresh_int : 1;
u64 thresh_int_ena : 1;
u64 thresh_up : 1;
u64 reserved_363 : 1;
u64 thresh_qint_idx : 7;
u64 reserved_371 : 1;
u64 err_qint_idx : 7;
u64 reserved_379_383 : 5;
u64 thresh : 36; /* W6*/
u64 rsvd_423_420 : 4;
u64 fc_msh_dst : 11;
u64 reserved_435_447 : 13;
u64 reserved_448_511; /* W7 */
};
struct npa_pool_s {
u64 stack_base; /* W0 */
u64 ena : 1;
u64 nat_align : 1;
u64 reserved_66_67 : 2;
u64 stack_caching : 1;
u64 reserved_70_71 : 3;
u64 stack_way_mask : 16;
u64 buf_offset : 12;
u64 reserved_100_103 : 4;
u64 buf_size : 11;
u64 reserved_115_127 : 13;
u64 stack_max_pages : 32;
u64 stack_pages : 32;
u64 op_pc : 48;
u64 reserved_240_255 : 16;
u64 stack_offset : 4;
u64 reserved_260_263 : 4;
u64 shift : 6;
u64 reserved_270_271 : 2;
u64 avg_level : 8;
u64 avg_con : 9;
u64 fc_ena : 1;
u64 fc_stype : 2;
u64 fc_hyst_bits : 4;
u64 fc_up_crossing : 1;
u64 fc_be : 1;
u64 reserved_298_299 : 2;
u64 update_time : 16;
u64 reserved_316_319 : 4;
u64 fc_addr; /* W5 */
u64 ptr_start; /* W6 */
u64 ptr_end; /* W7 */
u64 reserved_512_535 : 24;
u64 err_int : 8;
u64 err_int_ena : 8;
u64 thresh_int : 1;
u64 thresh_int_ena : 1;
u64 thresh_up : 1;
u64 reserved_555 : 1;
u64 thresh_qint_idx : 7;
u64 reserved_563 : 1;
u64 err_qint_idx : 7;
u64 reserved_571_575 : 5;
u64 thresh : 36;
u64 rsvd_615_612 : 4;
u64 fc_msh_dst : 11;
u64 reserved_627_639 : 13;
u64 reserved_640_703; /* W10 */
u64 reserved_704_767; /* W11 */
u64 reserved_768_831; /* W12 */
u64 reserved_832_895; /* W13 */
u64 reserved_896_959; /* W14 */
u64 reserved_960_1023; /* W15 */
};
/* NIX admin queue completion status */
enum nix_aq_comp {
NIX_AQ_COMP_NOTDONE = 0x0,
NIX_AQ_COMP_GOOD = 0x1,
NIX_AQ_COMP_SWERR = 0x2,
NIX_AQ_COMP_CTX_POISON = 0x3,
NIX_AQ_COMP_CTX_FAULT = 0x4,
NIX_AQ_COMP_LOCKERR = 0x5,
NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6,
};
/* NIX admin queue context types */
enum nix_aq_ctype {
NIX_AQ_CTYPE_RQ = 0x0,
NIX_AQ_CTYPE_SQ = 0x1,
NIX_AQ_CTYPE_CQ = 0x2,
NIX_AQ_CTYPE_MCE = 0x3,
NIX_AQ_CTYPE_RSS = 0x4,
NIX_AQ_CTYPE_DYNO = 0x5,
NIX_AQ_CTYPE_BANDPROF = 0x6,
};
/* NIX admin queue instruction opcodes */
enum nix_aq_instop {
NIX_AQ_INSTOP_NOP = 0x0,
NIX_AQ_INSTOP_INIT = 0x1,
NIX_AQ_INSTOP_WRITE = 0x2,
NIX_AQ_INSTOP_READ = 0x3,
NIX_AQ_INSTOP_LOCK = 0x4,
NIX_AQ_INSTOP_UNLOCK = 0x5,
};
/* NIX admin queue instruction structure */
struct nix_aq_inst_s {
u64 op : 4;
u64 ctype : 4;
u64 lf : 9;
u64 reserved_17_23 : 7;
u64 cindex : 20;
u64 reserved_44_62 : 19;
u64 doneint : 1;
u64 res_addr; /* W1 */
};
/* NIX admin queue result structure */
struct nix_aq_res_s {
u64 op : 4;
u64 ctype : 4;
u64 compcode : 8;
u64 doneint : 1;
u64 reserved_17_63 : 47;
u64 reserved_64_127; /* W1 */
};
/* NIX Completion queue context structure */
struct nix_cq_ctx_s {
u64 base;
u64 lbp_ena : 1;
u64 lbpid_low : 3;
u64 bp_ena : 1;
u64 lbpid_med : 3;
u64 bpid : 9;
u64 lbpid_high : 3;
u64 qint_idx : 7;
u64 cq_err : 1;
u64 cint_idx : 7;
u64 avg_con : 9;
u64 wrptr : 20;
u64 tail : 20;
u64 head : 20;
u64 avg_level : 8;
u64 update_time : 16;
u64 bp : 8;
u64 drop : 8;
u64 drop_ena : 1;
u64 ena : 1;
u64 cpt_drop_err_en : 1;
u64 rsvd_211 : 1;
u64 substream : 12;
u64 stash_thresh : 4;
u64 lbp_frac : 4;
u64 caching : 1;
u64 stashing : 1;
u64 rsvd_234_235 : 2;
u64 qsize : 4;
u64 cq_err_int : 8;
u64 cq_err_int_ena : 8;
/* Ensure all context sizes are 128 bytes */
u64 padding[12];
};
static_assert(sizeof(struct nix_cq_ctx_s) == NIX_MAX_CTX_SIZE);
/* CN10K NIX Receive queue context structure */
struct nix_cn10k_rq_ctx_s {
u64 ena : 1;
u64 sso_ena : 1;
u64 ipsech_ena : 1;
u64 ena_wqwd : 1;
u64 cq : 20;
u64 rsvd_36_24 : 13;
u64 lenerr_dis : 1;
u64 csum_il4_dis : 1;
u64 csum_ol4_dis : 1;
u64 len_il4_dis : 1;
u64 len_il3_dis : 1;
u64 len_ol4_dis : 1;
u64 len_ol3_dis : 1;
u64 wqe_aura : 20;
u64 spb_aura : 20;
u64 lpb_aura : 20;
u64 sso_grp : 10;
u64 sso_tt : 2;
u64 pb_caching : 2;
u64 wqe_caching : 1;
u64 xqe_drop_ena : 1;
u64 spb_drop_ena : 1;
u64 lpb_drop_ena : 1;
u64 pb_stashing : 1;
u64 ipsecd_drop_ena : 1;
u64 chi_ena : 1;
u64 rsvd_127_125 : 3;
u64 band_prof_id : 10; /* W2 */
u64 rsvd_138 : 1;
u64 policer_ena : 1;
u64 spb_sizem1 : 6;
u64 wqe_skip : 2;
u64 rsvd_150_148 : 3;
u64 spb_ena : 1;
u64 lpb_sizem1 : 12;
u64 first_skip : 7;
u64 rsvd_171 : 1;
u64 later_skip : 6;
u64 xqe_imm_size : 6;
u64 band_prof_id_h : 4;
u64 rsvd_189_188 : 2;
u64 xqe_imm_copy : 1;
u64 xqe_hdr_split : 1;
u64 xqe_drop : 8; /* W3 */
u64 xqe_pass : 8;
u64 wqe_pool_drop : 8;
u64 wqe_pool_pass : 8;
u64 spb_aura_drop : 8;
u64 spb_aura_pass : 8;
u64 spb_pool_drop : 8;
u64 spb_pool_pass : 8;
u64 lpb_aura_drop : 8; /* W4 */
u64 lpb_aura_pass : 8;
u64 lpb_pool_drop : 8;
u64 lpb_pool_pass : 8;
u64 rsvd_291_288 : 4;
u64 rq_int : 8;
u64 rq_int_ena : 8;
u64 qint_idx : 7;
u64 rsvd_319_315 : 5;
u64 ltag : 24; /* W5 */
u64 good_utag : 8;
u64 bad_utag : 8;
u64 flow_tagw : 6;
u64 ipsec_vwqe : 1;
u64 vwqe_ena : 1;
u64 vwqe_wait : 8;
u64 max_vsize_exp : 4;
u64 vwqe_skip : 2;
u64 rsvd_383_382 : 2;
u64 octs : 48; /* W6 */
u64 rsvd_447_432 : 16;
u64 pkts : 48; /* W7 */
u64 rsvd_511_496 : 16;
u64 drop_octs : 48; /* W8 */
u64 rsvd_575_560 : 16;
u64 drop_pkts : 48; /* W9 */
u64 rsvd_639_624 : 16;
u64 re_pkts : 48; /* W10 */
u64 rsvd_703_688 : 16;
u64 rsvd_767_704; /* W11 */
u64 rsvd_831_768; /* W12 */
u64 rsvd_895_832; /* W13 */
u64 rsvd_959_896; /* W14 */
u64 rsvd_1023_960; /* W15 */
};
static_assert(sizeof(struct nix_cn10k_rq_ctx_s) == NIX_MAX_CTX_SIZE);
/* CN10K NIX Send queue context structure */
struct nix_cn10k_sq_ctx_s {
u64 ena : 1;
u64 qint_idx : 6;
u64 substream : 20;
u64 sdp_mcast : 1;
u64 cq : 20;
u64 sqe_way_mask : 16;
u64 smq : 10; /* W1 */
u64 cq_ena : 1;
u64 xoff : 1;
u64 sso_ena : 1;
u64 smq_rr_weight : 14;
u64 default_chan : 12;
u64 sqb_count : 16;
u64 rsvd_120_119 : 2;
u64 smq_rr_count_lb : 7;
u64 smq_rr_count_ub : 25; /* W2 */
u64 sqb_aura : 20;
u64 sq_int : 8;
u64 sq_int_ena : 8;
u64 sqe_stype : 2;
u64 rsvd_191 : 1;
u64 max_sqe_size : 2; /* W3 */
u64 cq_limit : 8;
u64 lmt_dis : 1;
u64 mnq_dis : 1;
u64 smq_next_sq : 20;
u64 smq_lso_segnum : 8;
u64 tail_offset : 6;
u64 smenq_offset : 6;
u64 head_offset : 6;
u64 smenq_next_sqb_vld : 1;
u64 smq_pend : 1;
u64 smq_next_sq_vld : 1;
u64 rsvd_255_253 : 3;
u64 next_sqb : 64; /* W4 */
u64 tail_sqb : 64; /* W5 */
u64 smenq_sqb : 64; /* W6 */
u64 smenq_next_sqb : 64; /* W7 */
u64 head_sqb : 64; /* W8 */
u64 rsvd_583_576 : 8; /* W9 */
u64 vfi_lso_total : 18;
u64 vfi_lso_sizem1 : 3;
u64 vfi_lso_sb : 8;
u64 vfi_lso_mps : 14;
u64 vfi_lso_vlan0_ins_ena : 1;
u64 vfi_lso_vlan1_ins_ena : 1;
u64 vfi_lso_vld : 1;
u64 rsvd_639_630 : 10;
u64 scm_lso_rem : 18; /* W10 */
u64 rsvd_703_658 : 46;
u64 octs : 48; /* W11 */
u64 rsvd_767_752 : 16;
u64 pkts : 48; /* W12 */
u64 rsvd_831_816 : 16;
u64 rsvd_895_832 : 64; /* W13 */
u64 dropped_octs : 48;
u64 rsvd_959_944 : 16;
u64 dropped_pkts : 48;
u64 rsvd_1023_1008 : 16;
};
static_assert(sizeof(struct nix_cn10k_sq_ctx_s) == NIX_MAX_CTX_SIZE);
/* NIX Receive queue context structure */
struct nix_rq_ctx_s {
u64 ena : 1;
u64 sso_ena : 1;
u64 ipsech_ena : 1;
u64 ena_wqwd : 1;
u64 cq : 20;
u64 substream : 20;
u64 wqe_aura : 20;
u64 spb_aura : 20;
u64 lpb_aura : 20;
u64 sso_grp : 10;
u64 sso_tt : 2;
u64 pb_caching : 2;
u64 wqe_caching : 1;
u64 xqe_drop_ena : 1;
u64 spb_drop_ena : 1;
u64 lpb_drop_ena : 1;
u64 rsvd_127_122 : 6;
u64 rsvd_139_128 : 12; /* W2 */
u64 spb_sizem1 : 6;
u64 wqe_skip : 2;
u64 rsvd_150_148 : 3;
u64 spb_ena : 1;
u64 lpb_sizem1 : 12;
u64 first_skip : 7;
u64 rsvd_171 : 1;
u64 later_skip : 6;
u64 xqe_imm_size : 6;
u64 rsvd_189_184 : 6;
u64 xqe_imm_copy : 1;
u64 xqe_hdr_split : 1;
u64 xqe_drop : 8; /* W3*/
u64 xqe_pass : 8;
u64 wqe_pool_drop : 8;
u64 wqe_pool_pass : 8;
u64 spb_aura_drop : 8;
u64 spb_aura_pass : 8;
u64 spb_pool_drop : 8;
u64 spb_pool_pass : 8;
u64 lpb_aura_drop : 8; /* W4 */
u64 lpb_aura_pass : 8;
u64 lpb_pool_drop : 8;
u64 lpb_pool_pass : 8;
u64 rsvd_291_288 : 4;
u64 rq_int : 8;
u64 rq_int_ena : 8;
u64 qint_idx : 7;
u64 rsvd_319_315 : 5;
u64 ltag : 24; /* W5 */
u64 good_utag : 8;
u64 bad_utag : 8;
u64 flow_tagw : 6;
u64 rsvd_383_366 : 18;
u64 octs : 48; /* W6 */
u64 rsvd_447_432 : 16;
u64 pkts : 48; /* W7 */
u64 rsvd_511_496 : 16;
u64 drop_octs : 48; /* W8 */
u64 rsvd_575_560 : 16;
u64 drop_pkts : 48; /* W9 */
u64 rsvd_639_624 : 16;
u64 re_pkts : 48; /* W10 */
u64 rsvd_703_688 : 16;
u64 rsvd_767_704; /* W11 */
u64 rsvd_831_768; /* W12 */
u64 rsvd_895_832; /* W13 */
u64 rsvd_959_896; /* W14 */
u64 rsvd_1023_960; /* W15 */
};
static_assert(sizeof(struct nix_rq_ctx_s) == NIX_MAX_CTX_SIZE);
/* NIX sqe sizes */
enum nix_maxsqesz {
NIX_MAXSQESZ_W16 = 0x0,
NIX_MAXSQESZ_W8 = 0x1,
};
/* NIX SQB caching type */
enum nix_stype {
NIX_STYPE_STF = 0x0,
NIX_STYPE_STT = 0x1,
NIX_STYPE_STP = 0x2,
};
/* NIX Send queue context structure */
struct nix_sq_ctx_s {
u64 ena : 1;
u64 qint_idx : 6;
u64 substream : 20;
u64 sdp_mcast : 1;
u64 cq : 20;
u64 sqe_way_mask : 16;
u64 smq : 9;
u64 cq_ena : 1;
u64 xoff : 1;
u64 sso_ena : 1;
u64 smq_rr_quantum : 24;
u64 default_chan : 12;
u64 sqb_count : 16;
u64 smq_rr_count : 25;
u64 sqb_aura : 20;
u64 sq_int : 8;
u64 sq_int_ena : 8;
u64 sqe_stype : 2;
u64 rsvd_191 : 1;
u64 max_sqe_size : 2;
u64 cq_limit : 8;
u64 lmt_dis : 1;
u64 mnq_dis : 1;
u64 smq_next_sq : 20;
u64 smq_lso_segnum : 8;
u64 tail_offset : 6;
u64 smenq_offset : 6;
u64 head_offset : 6;
u64 smenq_next_sqb_vld : 1;
u64 smq_pend : 1;
u64 smq_next_sq_vld : 1;
u64 rsvd_255_253 : 3;
u64 next_sqb : 64;/* W4 */
u64 tail_sqb : 64;/* W5 */
u64 smenq_sqb : 64;/* W6 */
u64 smenq_next_sqb : 64;/* W7 */
u64 head_sqb : 64;/* W8 */
u64 rsvd_583_576 : 8;
u64 vfi_lso_total : 18;
u64 vfi_lso_sizem1 : 3;
u64 vfi_lso_sb : 8;
u64 vfi_lso_mps : 14;
u64 vfi_lso_vlan0_ins_ena : 1;
u64 vfi_lso_vlan1_ins_ena : 1;
u64 vfi_lso_vld : 1;
u64 rsvd_639_630 : 10;
u64 scm_lso_rem : 18;
u64 rsvd_703_658 : 46;
u64 octs : 48;
u64 rsvd_767_752 : 16;
u64 pkts : 48;
u64 rsvd_831_816 : 16;
u64 rsvd_895_832 : 64;/* W13 */
u64 dropped_octs : 48;
u64 rsvd_959_944 : 16;
u64 dropped_pkts : 48;
u64 rsvd_1023_1008 : 16;
};
static_assert(sizeof(struct nix_sq_ctx_s) == NIX_MAX_CTX_SIZE);
/* NIX Receive side scaling entry structure*/
struct nix_rsse_s {
uint32_t rq : 20;
uint32_t reserved_20_31 : 12;
/* Ensure all context sizes are minimum 128 bytes */
u64 padding[15];
};
static_assert(sizeof(struct nix_rsse_s) == NIX_MAX_CTX_SIZE);
/* NIX receive multicast/mirror entry structure */
struct nix_rx_mce_s {
uint64_t op : 2;
uint64_t rsvd_2 : 1;
uint64_t eol : 1;
uint64_t index : 20;
uint64_t rsvd_31_24 : 8;
uint64_t pf_func : 16;
uint64_t next : 16;
/* Ensure all context sizes are minimum 128 bytes */
u64 padding[15];
};
static_assert(sizeof(struct nix_rx_mce_s) == NIX_MAX_CTX_SIZE);
enum nix_band_prof_layers {
BAND_PROF_LEAF_LAYER = 0,
BAND_PROF_INVAL_LAYER = 1,
BAND_PROF_MID_LAYER = 2,
BAND_PROF_TOP_LAYER = 3,
BAND_PROF_NUM_LAYERS = 4,
};
enum NIX_RX_BAND_PROF_ACTIONRESULT_E {
NIX_RX_BAND_PROF_ACTIONRESULT_PASS = 0x0,
NIX_RX_BAND_PROF_ACTIONRESULT_DROP = 0x1,
NIX_RX_BAND_PROF_ACTIONRESULT_RED = 0x2,
};
enum nix_band_prof_pc_mode {
NIX_RX_PC_MODE_VLAN = 0,
NIX_RX_PC_MODE_DSCP = 1,
NIX_RX_PC_MODE_GEN = 2,
NIX_RX_PC_MODE_RSVD = 3,
};
/* NIX ingress policer bandwidth profile structure */
struct nix_bandprof_s {
uint64_t pc_mode : 2; /* W0 */
uint64_t icolor : 2;
uint64_t tnl_ena : 1;
uint64_t reserved_5_7 : 3;
uint64_t peir_exponent : 5;
uint64_t reserved_13_15 : 3;
uint64_t pebs_exponent : 5;
uint64_t reserved_21_23 : 3;
uint64_t cir_exponent : 5;
uint64_t reserved_29_31 : 3;
uint64_t cbs_exponent : 5;
uint64_t reserved_37_39 : 3;
uint64_t peir_mantissa : 8;
uint64_t pebs_mantissa : 8;
uint64_t cir_mantissa : 8;
uint64_t cbs_mantissa : 8; /* W1 */
uint64_t lmode : 1;
uint64_t l_sellect : 3;
uint64_t rdiv : 4;
uint64_t adjust_exponent : 5;
uint64_t reserved_85_86 : 2;
uint64_t adjust_mantissa : 9;
uint64_t gc_action : 2;
uint64_t yc_action : 2;
uint64_t rc_action : 2;
uint64_t meter_algo : 2;
uint64_t band_prof_id : 7;
uint64_t band_prof_id_h : 4;
uint64_t reserved_115_118 : 4;
uint64_t hl_en : 1;
uint64_t reserved_120_127 : 8;
uint64_t ts : 48; /* W2 */
uint64_t reserved_176_191 : 16;
uint64_t pe_accum : 32; /* W3 */
uint64_t c_accum : 32;
uint64_t green_pkt_pass : 48; /* W4 */
uint64_t reserved_304_319 : 16;
uint64_t yellow_pkt_pass : 48; /* W5 */
uint64_t reserved_368_383 : 16;
uint64_t red_pkt_pass : 48; /* W6 */
uint64_t reserved_432_447 : 16;
uint64_t green_octs_pass : 48; /* W7 */
uint64_t reserved_496_511 : 16;
uint64_t yellow_octs_pass : 48; /* W8 */
uint64_t reserved_560_575 : 16;
uint64_t red_octs_pass : 48; /* W9 */
uint64_t reserved_624_639 : 16;
uint64_t green_pkt_drop : 48; /* W10 */
uint64_t reserved_688_703 : 16;
uint64_t yellow_pkt_drop : 48; /* W11 */
uint64_t reserved_752_767 : 16;
uint64_t red_pkt_drop : 48; /* W12 */
uint64_t reserved_816_831 : 16;
uint64_t green_octs_drop : 48; /* W13 */
uint64_t reserved_880_895 : 16;
uint64_t yellow_octs_drop : 48; /* W14 */
uint64_t reserved_944_959 : 16;
uint64_t red_octs_drop : 48; /* W15 */
uint64_t reserved_1008_1023 : 16;
};
static_assert(sizeof(struct nix_bandprof_s) == NIX_MAX_CTX_SIZE);
enum nix_lsoalg {
NIX_LSOALG_NOP,
NIX_LSOALG_ADD_SEGNUM,
NIX_LSOALG_ADD_PAYLEN,
NIX_LSOALG_ADD_OFFSET,
NIX_LSOALG_TCP_FLAGS,
};
enum nix_txlayer {
NIX_TXLAYER_OL3,
NIX_TXLAYER_OL4,
NIX_TXLAYER_IL3,
NIX_TXLAYER_IL4,
};
struct nix_lso_format {
u64 offset : 8;
u64 layer : 2;
u64 rsvd_10_11 : 2;
u64 sizem1 : 2;
u64 rsvd_14_15 : 2;
u64 alg : 3;
u64 rsvd_19_63 : 45;
};
struct nix_rx_flowkey_alg {
u64 key_offset :6;
u64 ln_mask :1;
u64 fn_mask :1;
u64 hdr_offset :8;
u64 bytesm1 :5;
u64 lid :3;
u64 reserved_24_24 :1;
u64 ena :1;
u64 sel_chan :1;
u64 ltype_mask :4;
u64 ltype_match :4;
u64 reserved_35_63 :29;
};
/* NIX VTAG size */
enum nix_vtag_size {
VTAGSIZE_T4 = 0x0,
VTAGSIZE_T8 = 0x1,
};
enum nix_tx_vtag_op {
NOP = 0x0,
VTAG_INSERT = 0x1,
VTAG_REPLACE = 0x2,
};
/* NIX RX VTAG actions */
#define VTAG_STRIP BIT_ULL(4)
#define VTAG_CAPTURE BIT_ULL(5)
/* NIX TX stats */
enum nix_stat_lf_tx {
TX_UCAST = 0x0,
TX_BCAST = 0x1,
TX_MCAST = 0x2,
TX_DROP = 0x3,
TX_OCTS = 0x4,
TX_STATS_ENUM_LAST,
};
/* NIX RX stats */
enum nix_stat_lf_rx {
RX_OCTS = 0x0,
RX_UCAST = 0x1,
RX_BCAST = 0x2,
RX_MCAST = 0x3,
RX_DROP = 0x4,
RX_DROP_OCTS = 0x5,
RX_FCS = 0x6,
RX_ERR = 0x7,
RX_DRP_BCAST = 0x8,
RX_DRP_MCAST = 0x9,
RX_DRP_L3BCAST = 0xa,
RX_DRP_L3MCAST = 0xb,
RX_STATS_ENUM_LAST,
};
#endif /* RVU_STRUCT_H */
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c
+294
View File
@@ -0,0 +1,294 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2021 Marvell.
*
*/
#include <linux/bitfield.h>
#include "rvu.h"
void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool enable)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
struct nix_hw *nix_hw;
nix_hw = get_nix_hw(rvu->hw, pfvf->nix_blkaddr);
/* Enable LBK links with channel 63 for TX MCAM rule */
rvu_nix_tx_tl2_cfg(rvu, pfvf->nix_blkaddr, pcifunc,
&nix_hw->txsch[NIX_TXSCH_LVL_TL2], enable);
}
static int rvu_switch_install_rx_rule(struct rvu *rvu, u16 pcifunc,
u16 chan_mask)
{
struct npc_install_flow_req req = { 0 };
struct npc_install_flow_rsp rsp = { 0 };
struct rvu_pfvf *pfvf;
pfvf = rvu_get_pfvf(rvu, pcifunc);
/* If the pcifunc is not initialized then nothing to do.
* This same function will be called again via rvu_switch_update_rules
* after pcifunc is initialized.
*/
if (!test_bit(NIXLF_INITIALIZED, &pfvf->flags))
return 0;
ether_addr_copy(req.packet.dmac, pfvf->mac_addr);
eth_broadcast_addr((u8 *)&req.mask.dmac);
req.hdr.pcifunc = 0; /* AF is requester */
req.vf = pcifunc;
req.features = BIT_ULL(NPC_DMAC);
req.channel = pfvf->rx_chan_base;
req.chan_mask = chan_mask;
req.intf = pfvf->nix_rx_intf;
req.op = NIX_RX_ACTION_DEFAULT;
req.default_rule = 1;
return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
}
static int rvu_switch_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry)
{
struct npc_install_flow_req req = { 0 };
struct npc_install_flow_rsp rsp = { 0 };
struct rvu_pfvf *pfvf;
u8 lbkid;
pfvf = rvu_get_pfvf(rvu, pcifunc);
/* If the pcifunc is not initialized then nothing to do.
* This same function will be called again via rvu_switch_update_rules
* after pcifunc is initialized.
*/
if (!test_bit(NIXLF_INITIALIZED, &pfvf->flags))
return 0;
rvu_switch_enable_lbk_link(rvu, pcifunc, true);
lbkid = pfvf->nix_blkaddr == BLKADDR_NIX0 ? 0 : 1;
ether_addr_copy(req.packet.dmac, pfvf->mac_addr);
eth_broadcast_addr((u8 *)&req.mask.dmac);
req.hdr.pcifunc = 0; /* AF is requester */
req.vf = pcifunc;
req.entry = entry;
req.features = BIT_ULL(NPC_DMAC);
req.intf = pfvf->nix_tx_intf;
req.op = NIX_TX_ACTIONOP_UCAST_CHAN;
req.index = (lbkid << 8) | RVU_SWITCH_LBK_CHAN;
req.set_cntr = 1;
return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
}
static int rvu_switch_install_rules(struct rvu *rvu)
{
struct rvu_switch *rswitch = &rvu->rswitch;
u16 start = rswitch->start_entry;
struct rvu_hwinfo *hw = rvu->hw;
u16 pcifunc, entry = 0;
int pf, vf, numvfs;
int err;
for (pf = 1; pf < hw->total_pfs; pf++) {
if (!is_pf_cgxmapped(rvu, pf))
continue;
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0);
/* rvu_get_nix_blkaddr sets up the corresponding NIX block
* address and NIX RX and TX interfaces for a pcifunc.
* Generally it is called during attach call of a pcifunc but it
* is called here since we are pre-installing rules before
* nixlfs are attached
*/
rvu_get_nix_blkaddr(rvu, pcifunc);
/* MCAM RX rule for a PF/VF already exists as default unicast
* rules installed by AF. Hence change the channel in those
* rules to ignore channel so that packets with the required
* DMAC received from LBK(by other PF/VFs in system) or from
* external world (from wire) are accepted.
*/
err = rvu_switch_install_rx_rule(rvu, pcifunc, 0x0);
if (err) {
dev_err(rvu->dev, "RX rule for PF%d failed(%d)\n",
pf, err);
return err;
}
err = rvu_switch_install_tx_rule(rvu, pcifunc, start + entry);
if (err) {
dev_err(rvu->dev, "TX rule for PF%d failed(%d)\n",
pf, err);
return err;
}
rswitch->entry2pcifunc[entry++] = pcifunc;
rvu_get_pf_numvfs(rvu, pf, &numvfs, NULL);
for (vf = 0; vf < numvfs; vf++) {
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, (vf + 1));
rvu_get_nix_blkaddr(rvu, pcifunc);
err = rvu_switch_install_rx_rule(rvu, pcifunc, 0x0);
if (err) {
dev_err(rvu->dev,
"RX rule for PF%dVF%d failed(%d)\n",
pf, vf, err);
return err;
}
err = rvu_switch_install_tx_rule(rvu, pcifunc,
start + entry);
if (err) {
dev_err(rvu->dev,
"TX rule for PF%dVF%d failed(%d)\n",
pf, vf, err);
return err;
}
rswitch->entry2pcifunc[entry++] = pcifunc;
}
}
return 0;
}
void rvu_switch_enable(struct rvu *rvu)
{
struct npc_mcam_alloc_entry_req alloc_req = { 0 };
struct npc_mcam_alloc_entry_rsp alloc_rsp = { 0 };
struct npc_delete_flow_req uninstall_req = { 0 };
struct npc_delete_flow_rsp uninstall_rsp = { 0 };
struct npc_mcam_free_entry_req free_req = { 0 };
struct rvu_switch *rswitch = &rvu->rswitch;
struct msg_rsp rsp;
int ret;
alloc_req.contig = true;
alloc_req.count = rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs;
if (rvu->rep_mode)
alloc_req.count = alloc_req.count * 4;
ret = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, &alloc_req,
&alloc_rsp);
if (ret) {
dev_err(rvu->dev,
"Unable to allocate MCAM entries\n");
goto exit;
}
if (alloc_rsp.count != alloc_req.count) {
dev_err(rvu->dev,
"Unable to allocate %d MCAM entries, got %d\n",
alloc_req.count, alloc_rsp.count);
goto free_entries;
}
rswitch->entry2pcifunc = kcalloc(alloc_req.count, sizeof(u16),
GFP_KERNEL);
if (!rswitch->entry2pcifunc)
goto free_entries;
rswitch->used_entries = alloc_rsp.count;
rswitch->start_entry = alloc_rsp.entry;
if (rvu->rep_mode) {
rvu_rep_pf_init(rvu);
ret = rvu_rep_install_mcam_rules(rvu);
} else {
ret = rvu_switch_install_rules(rvu);
}
if (ret)
goto uninstall_rules;
return;
uninstall_rules:
uninstall_req.start = rswitch->start_entry;
uninstall_req.end = rswitch->start_entry + rswitch->used_entries - 1;
rvu_mbox_handler_npc_delete_flow(rvu, &uninstall_req, &uninstall_rsp);
kfree(rswitch->entry2pcifunc);
free_entries:
free_req.all = 1;
rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp);
exit:
return;
}
void rvu_switch_disable(struct rvu *rvu)
{
struct npc_delete_flow_req uninstall_req = { 0 };
struct npc_delete_flow_rsp uninstall_rsp = { 0 };
struct npc_mcam_free_entry_req free_req = { 0 };
struct rvu_switch *rswitch = &rvu->rswitch;
struct rvu_hwinfo *hw = rvu->hw;
int pf, vf, numvfs;
struct msg_rsp rsp;
u16 pcifunc;
int err;
if (!rswitch->used_entries)
return;
if (rvu->rep_mode)
goto free_ents;
for (pf = 1; pf < hw->total_pfs; pf++) {
if (!is_pf_cgxmapped(rvu, pf))
continue;
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0);
err = rvu_switch_install_rx_rule(rvu, pcifunc, 0xFFF);
if (err)
dev_err(rvu->dev,
"Reverting RX rule for PF%d failed(%d)\n",
pf, err);
/* Disable LBK link */
rvu_switch_enable_lbk_link(rvu, pcifunc, false);
rvu_get_pf_numvfs(rvu, pf, &numvfs, NULL);
for (vf = 0; vf < numvfs; vf++) {
pcifunc = rvu_make_pcifunc(rvu->pdev, pf, (vf + 1));
err = rvu_switch_install_rx_rule(rvu, pcifunc, 0xFFF);
if (err)
dev_err(rvu->dev,
"Reverting RX rule for PF%dVF%d failed(%d)\n",
pf, vf, err);
rvu_switch_enable_lbk_link(rvu, pcifunc, false);
}
}
free_ents:
uninstall_req.start = rswitch->start_entry;
uninstall_req.end = rswitch->start_entry + rswitch->used_entries - 1;
free_req.all = 1;
rvu_mbox_handler_npc_delete_flow(rvu, &uninstall_req, &uninstall_rsp);
rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp);
rswitch->used_entries = 0;
kfree(rswitch->entry2pcifunc);
}
void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena)
{
struct rvu_switch *rswitch = &rvu->rswitch;
u32 max = rswitch->used_entries;
u16 entry;
if (rvu->rep_mode)
return rvu_rep_update_rules(rvu, pcifunc, ena);
if (!rswitch->used_entries)
return;
for (entry = 0; entry < max; entry++) {
if (rswitch->entry2pcifunc[entry] == pcifunc)
break;
}
if (entry >= max)
return;
rvu_switch_install_tx_rule(rvu, pcifunc, rswitch->start_entry + entry);
rvu_switch_install_rx_rule(rvu, pcifunc, 0x0);
}
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.c
+15
View File
@@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2020 Marvell.
*
*/
#define CREATE_TRACE_POINTS
#include "rvu_trace.h"
EXPORT_TRACEPOINT_SYMBOL(otx2_msg_alloc);
EXPORT_TRACEPOINT_SYMBOL(otx2_msg_interrupt);
EXPORT_TRACEPOINT_SYMBOL(otx2_msg_process);
EXPORT_TRACEPOINT_SYMBOL(otx2_msg_status);
EXPORT_TRACEPOINT_SYMBOL(otx2_parse_dump);
linux-7.2.3/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.h
+170
View File
@@ -0,0 +1,170 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell RVU Admin Function driver
*
* Copyright (C) 2020 Marvell.
*
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM rvu
#if !defined(__RVU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
#define __RVU_TRACE_H
#include <linux/types.h>
#include <linux/tracepoint.h>
#include <linux/pci.h>
#include "mbox.h"
TRACE_EVENT(otx2_msg_alloc,
TP_PROTO(const struct pci_dev *pdev, u16 id, u64 size, u16 pcifunc),
TP_ARGS(pdev, id, size, pcifunc),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__field(u16, id)
__field(u64, size)
__field(u16, pcifunc)
),
TP_fast_assign(__assign_str(dev);
__entry->id = id;
__entry->size = size;
__entry->pcifunc = pcifunc;
),
TP_printk("[%s] msg:(%s) size:%lld pcifunc:0x%x\n", __get_str(dev),
otx2_mbox_id2name(__entry->id), __entry->size,
__entry->pcifunc)
);
TRACE_EVENT(otx2_msg_send,
TP_PROTO(const struct pci_dev *pdev, u16 num_msgs, u64 msg_size,
u16 id, u16 pcifunc),
TP_ARGS(pdev, num_msgs, msg_size, id, pcifunc),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__field(u16, num_msgs)
__field(u64, msg_size)
__field(u16, id)
__field(u16, pcifunc)
),
TP_fast_assign(__assign_str(dev);
__entry->num_msgs = num_msgs;
__entry->msg_size = msg_size;
__entry->id = id;
__entry->pcifunc = pcifunc;
),
TP_printk("[%s] sent %d msg(s) of size:%lld msg:(%s) pcifunc:0x%x\n",
__get_str(dev), __entry->num_msgs, __entry->msg_size,
otx2_mbox_id2name(__entry->id), __entry->pcifunc)
);
TRACE_EVENT(otx2_msg_check,
TP_PROTO(const struct pci_dev *pdev, u16 reqid, u16 rspid, int rc),
TP_ARGS(pdev, reqid, rspid, rc),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__field(u16, reqid)
__field(u16, rspid)
__field(int, rc)
),
TP_fast_assign(__assign_str(dev);
__entry->reqid = reqid;
__entry->rspid = rspid;
__entry->rc = rc;
),
TP_printk("[%s] req->id:0x%x rsp->id:0x%x resp_code:%d\n",
__get_str(dev), __entry->reqid,
__entry->rspid, __entry->rc)
);
TRACE_EVENT(otx2_msg_interrupt,
TP_PROTO(const struct pci_dev *pdev, const char *msg, u64 intr),
TP_ARGS(pdev, msg, intr),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__string(str, msg)
__field(u64, intr)
),
TP_fast_assign(__assign_str(dev);
__assign_str(str);
__entry->intr = intr;
),
TP_printk("[%s] mbox interrupt %s (0x%llx)\n", __get_str(dev),
__get_str(str), __entry->intr)
);
TRACE_EVENT(otx2_msg_process,
TP_PROTO(const struct pci_dev *pdev, u16 id, int err, u16 pcifunc),
TP_ARGS(pdev, id, err, pcifunc),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__field(u16, id)
__field(int, err)
__field(u16, pcifunc)
),
TP_fast_assign(__assign_str(dev);
__entry->id = id;
__entry->err = err;
__entry->pcifunc = pcifunc;
),
TP_printk("[%s] msg:(%s) error:%d pcifunc:0x%x\n", __get_str(dev),
otx2_mbox_id2name(__entry->id),
__entry->err, __entry->pcifunc)
);
TRACE_EVENT(otx2_msg_wait_rsp,
TP_PROTO(const struct pci_dev *pdev),
TP_ARGS(pdev),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
),
TP_fast_assign(__assign_str(dev)
),
TP_printk("[%s] timed out while waiting for response\n",
__get_str(dev))
);
TRACE_EVENT(otx2_msg_status,
TP_PROTO(const struct pci_dev *pdev, const char *msg, u16 num_msgs),
TP_ARGS(pdev, msg, num_msgs),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__string(str, msg)
__field(u16, num_msgs)
),
TP_fast_assign(__assign_str(dev);
__assign_str(str);
__entry->num_msgs = num_msgs;
),
TP_printk("[%s] %s num_msgs:%d\n", __get_str(dev),
__get_str(str), __entry->num_msgs)
);
TRACE_EVENT(otx2_parse_dump,
TP_PROTO(const struct pci_dev *pdev, char *msg, u64 *word),
TP_ARGS(pdev, msg, word),
TP_STRUCT__entry(__string(dev, pci_name(pdev))
__string(str, msg)
__field(u64, w0)
__field(u64, w1)
__field(u64, w2)
__field(u64, w3)
__field(u64, w4)
__field(u64, w5)
),
TP_fast_assign(__assign_str(dev);
__assign_str(str);
__entry->w0 = *(word + 0);
__entry->w1 = *(word + 1);
__entry->w2 = *(word + 2);
__entry->w3 = *(word + 3);
__entry->w4 = *(word + 4);
__entry->w5 = *(word + 5);
),
TP_printk("[%s] nix parse %s W0:%#llx W1:%#llx W2:%#llx W3:%#llx W4:%#llx W5:%#llx\n",
__get_str(dev), __get_str(str), __entry->w0, __entry->w1, __entry->w2,
__entry->w3, __entry->w4, __entry->w5)
);
#endif /* __RVU_TRACE_H */
#undef TRACE_INCLUDE_PATH
#define TRACE_INCLUDE_PATH .
#undef TRACE_INCLUDE_FILE
#define TRACE_INCLUDE_FILE rvu_trace
#include <trace/define_trace.h>