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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/net/ieee802154/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
menuconfig IEEE802154_DRIVERS
tristate "IEEE 802.15.4 drivers"
depends on NETDEVICES && IEEE802154
default y
help
Say Y here to get to see options for IEEE 802.15.4 Low-Rate
Wireless Personal Area Network device drivers. This option alone
does not add any kernel code.
If you say N, all options in this submenu will be skipped and
disabled.
config IEEE802154_FAKELB
depends on IEEE802154_DRIVERS && MAC802154
tristate "IEEE 802.15.4 loopback driver"
help
Say Y here to enable the fake driver that can emulate a net
of several interconnected radio devices.
This driver can also be built as a module. To do so say M here.
The module will be called 'fakelb'.
config IEEE802154_AT86RF230
depends on IEEE802154_DRIVERS && MAC802154
tristate "AT86RF230/231/233/212 transceiver driver"
depends on SPI
select REGMAP_SPI
help
Say Y here to enable the at86rf230/231/233/212 SPI 802.15.4 wireless
controller.
This driver can also be built as a module. To do so, say M here.
the module will be called 'at86rf230'.
config IEEE802154_MRF24J40
tristate "Microchip MRF24J40 transceiver driver"
depends on IEEE802154_DRIVERS && MAC802154
depends on SPI
select REGMAP_SPI
help
Say Y here to enable the MRF24J20 SPI 802.15.4 wireless
controller.
This driver can also be built as a module. To do so, say M here.
the module will be called 'mrf24j40'.
config IEEE802154_CC2520
depends on IEEE802154_DRIVERS && MAC802154
tristate "CC2520 transceiver driver"
depends on SPI
help
Say Y here to enable the CC2520 SPI 802.15.4 wireless
controller.
This driver can also be built as a module. To do so, say M here.
the module will be called 'cc2520'.
config IEEE802154_ATUSB
tristate "ATUSB transceiver driver"
depends on IEEE802154_DRIVERS && MAC802154 && USB
help
Say Y here to enable the ATUSB IEEE 802.15.4 wireless
controller.
This driver can also be built as a module. To do so say M here.
The module will be called 'atusb'.
config IEEE802154_ADF7242
tristate "ADF7242 transceiver driver"
depends on IEEE802154_DRIVERS && MAC802154
depends on SPI
help
Say Y here to enable the ADF7242 SPI 802.15.4 wireless
controller.
This driver can also be built as a module. To do so, say M here.
the module will be called 'adf7242'.
config IEEE802154_CA8210
tristate "Cascoda CA8210 transceiver driver"
depends on IEEE802154_DRIVERS && MAC802154
depends on COMMON_CLK
depends on SPI
help
Say Y here to enable the CA8210 SPI 802.15.4 wireless
controller.
This driver can also be built as a module. To do so, say M here.
the module will be called 'ca8210'.
config IEEE802154_CA8210_DEBUGFS
bool "CA8210 debugfs interface"
depends on IEEE802154_CA8210
depends on DEBUG_FS
help
This option compiles debugfs code for the ca8210 driver. This
exposes a debugfs node for each CA8210 instance which allows
direct use of the Cascoda API, exposing the 802.15.4 MAC
management entities.
config IEEE802154_MCR20A
tristate "MCR20A transceiver driver"
select REGMAP_SPI
depends on IEEE802154_DRIVERS && MAC802154
depends on SPI
help
Say Y here to enable the MCR20A SPI 802.15.4 wireless
controller.
This driver can also be built as a module. To do so, say M here.
the module will be called 'mcr20a'.
config IEEE802154_HWSIM
depends on IEEE802154_DRIVERS && MAC802154
tristate "Simulated radio testing tool for mac802154"
help
This driver is a developer testing tool that can be used to test
IEEE 802.15.4 networking stack (mac802154) functionality. This is not
needed for normal wpan usage and is only for testing.
This driver can also be built as a module. To do so say M here.
The module will be called 'mac802154_hwsim'.
linux-7.2.3/drivers/net/ieee802154/Makefile
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# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_IEEE802154_FAKELB) += fakelb.o
obj-$(CONFIG_IEEE802154_AT86RF230) += at86rf230.o
obj-$(CONFIG_IEEE802154_MRF24J40) += mrf24j40.o
obj-$(CONFIG_IEEE802154_CC2520) += cc2520.o
obj-$(CONFIG_IEEE802154_ATUSB) += atusb.o
obj-$(CONFIG_IEEE802154_ADF7242) += adf7242.o
obj-$(CONFIG_IEEE802154_CA8210) += ca8210.o
obj-$(CONFIG_IEEE802154_MCR20A) += mcr20a.o
obj-$(CONFIG_IEEE802154_HWSIM) += mac802154_hwsim.o
linux-7.2.3/drivers/net/ieee802154/adf7242.c
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linux-7.2.3/drivers/net/ieee802154/at86rf230.c
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linux-7.2.3/drivers/net/ieee802154/at86rf230.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AT86RF230/RF231 driver
*
* Copyright (C) 2009-2012 Siemens AG
*
* Written by:
* Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
* Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
*/
#ifndef _AT86RF230_H
#define _AT86RF230_H
#define RG_TRX_STATUS (0x01)
#define SR_TRX_STATUS 0x01, 0x1f, 0
#define SR_RESERVED_01_3 0x01, 0x20, 5
#define SR_CCA_STATUS 0x01, 0x40, 6
#define SR_CCA_DONE 0x01, 0x80, 7
#define RG_TRX_STATE (0x02)
#define SR_TRX_CMD 0x02, 0x1f, 0
#define SR_TRAC_STATUS 0x02, 0xe0, 5
#define RG_TRX_CTRL_0 (0x03)
#define SR_CLKM_CTRL 0x03, 0x07, 0
#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
#define SR_PAD_IO_CLKM 0x03, 0x30, 4
#define SR_PAD_IO 0x03, 0xc0, 6
#define RG_TRX_CTRL_1 (0x04)
#define SR_IRQ_POLARITY 0x04, 0x01, 0
#define SR_IRQ_MASK_MODE 0x04, 0x02, 1
#define SR_SPI_CMD_MODE 0x04, 0x0c, 2
#define SR_RX_BL_CTRL 0x04, 0x10, 4
#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
#define SR_PA_EXT_EN 0x04, 0x80, 7
#define RG_PHY_TX_PWR (0x05)
#define SR_TX_PWR_23X 0x05, 0x0f, 0
#define SR_PA_LT_230 0x05, 0x30, 4
#define SR_PA_BUF_LT_230 0x05, 0xc0, 6
#define SR_TX_PWR_212 0x05, 0x1f, 0
#define SR_GC_PA_212 0x05, 0x60, 5
#define SR_PA_BOOST_LT_212 0x05, 0x80, 7
#define RG_PHY_RSSI (0x06)
#define SR_RSSI 0x06, 0x1f, 0
#define SR_RND_VALUE 0x06, 0x60, 5
#define SR_RX_CRC_VALID 0x06, 0x80, 7
#define RG_PHY_ED_LEVEL (0x07)
#define SR_ED_LEVEL 0x07, 0xff, 0
#define RG_PHY_CC_CCA (0x08)
#define SR_CHANNEL 0x08, 0x1f, 0
#define SR_CCA_MODE 0x08, 0x60, 5
#define SR_CCA_REQUEST 0x08, 0x80, 7
#define RG_CCA_THRES (0x09)
#define SR_CCA_ED_THRES 0x09, 0x0f, 0
#define SR_RESERVED_09_1 0x09, 0xf0, 4
#define RG_RX_CTRL (0x0a)
#define SR_PDT_THRES 0x0a, 0x0f, 0
#define SR_RESERVED_0a_1 0x0a, 0xf0, 4
#define RG_SFD_VALUE (0x0b)
#define SR_SFD_VALUE 0x0b, 0xff, 0
#define RG_TRX_CTRL_2 (0x0c)
#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
#define SR_SUB_MODE 0x0c, 0x04, 2
#define SR_BPSK_QPSK 0x0c, 0x08, 3
#define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
#define SR_RESERVED_0c_5 0x0c, 0x60, 5
#define SR_RX_SAFE_MODE 0x0c, 0x80, 7
#define RG_ANT_DIV (0x0d)
#define SR_ANT_CTRL 0x0d, 0x03, 0
#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
#define SR_ANT_DIV_EN 0x0d, 0x08, 3
#define SR_RESERVED_0d_2 0x0d, 0x70, 4
#define SR_ANT_SEL 0x0d, 0x80, 7
#define RG_IRQ_MASK (0x0e)
#define SR_IRQ_MASK 0x0e, 0xff, 0
#define RG_IRQ_STATUS (0x0f)
#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
#define SR_IRQ_5_AMI 0x0f, 0x20, 5
#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
#define RG_VREG_CTRL (0x10)
#define SR_RESERVED_10_6 0x10, 0x03, 0
#define SR_DVDD_OK 0x10, 0x04, 2
#define SR_DVREG_EXT 0x10, 0x08, 3
#define SR_RESERVED_10_3 0x10, 0x30, 4
#define SR_AVDD_OK 0x10, 0x40, 6
#define SR_AVREG_EXT 0x10, 0x80, 7
#define RG_BATMON (0x11)
#define SR_BATMON_VTH 0x11, 0x0f, 0
#define SR_BATMON_HR 0x11, 0x10, 4
#define SR_BATMON_OK 0x11, 0x20, 5
#define SR_RESERVED_11_1 0x11, 0xc0, 6
#define RG_XOSC_CTRL (0x12)
#define SR_XTAL_TRIM 0x12, 0x0f, 0
#define SR_XTAL_MODE 0x12, 0xf0, 4
#define RG_RX_SYN (0x15)
#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
#define SR_RESERVED_15_2 0x15, 0x70, 4
#define SR_RX_PDT_DIS 0x15, 0x80, 7
#define RG_XAH_CTRL_1 (0x17)
#define SR_RESERVED_17_8 0x17, 0x01, 0
#define SR_AACK_PROM_MODE 0x17, 0x02, 1
#define SR_AACK_ACK_TIME 0x17, 0x04, 2
#define SR_RESERVED_17_5 0x17, 0x08, 3
#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
#define SR_CSMA_LBT_MODE 0x17, 0x40, 6
#define SR_RESERVED_17_1 0x17, 0x80, 7
#define RG_FTN_CTRL (0x18)
#define SR_RESERVED_18_2 0x18, 0x7f, 0
#define SR_FTN_START 0x18, 0x80, 7
#define RG_PLL_CF (0x1a)
#define SR_RESERVED_1a_2 0x1a, 0x7f, 0
#define SR_PLL_CF_START 0x1a, 0x80, 7
#define RG_PLL_DCU (0x1b)
#define SR_RESERVED_1b_3 0x1b, 0x3f, 0
#define SR_RESERVED_1b_2 0x1b, 0x40, 6
#define SR_PLL_DCU_START 0x1b, 0x80, 7
#define RG_PART_NUM (0x1c)
#define SR_PART_NUM 0x1c, 0xff, 0
#define RG_VERSION_NUM (0x1d)
#define SR_VERSION_NUM 0x1d, 0xff, 0
#define RG_MAN_ID_0 (0x1e)
#define SR_MAN_ID_0 0x1e, 0xff, 0
#define RG_MAN_ID_1 (0x1f)
#define SR_MAN_ID_1 0x1f, 0xff, 0
#define RG_SHORT_ADDR_0 (0x20)
#define SR_SHORT_ADDR_0 0x20, 0xff, 0
#define RG_SHORT_ADDR_1 (0x21)
#define SR_SHORT_ADDR_1 0x21, 0xff, 0
#define RG_PAN_ID_0 (0x22)
#define SR_PAN_ID_0 0x22, 0xff, 0
#define RG_PAN_ID_1 (0x23)
#define SR_PAN_ID_1 0x23, 0xff, 0
#define RG_IEEE_ADDR_0 (0x24)
#define SR_IEEE_ADDR_0 0x24, 0xff, 0
#define RG_IEEE_ADDR_1 (0x25)
#define SR_IEEE_ADDR_1 0x25, 0xff, 0
#define RG_IEEE_ADDR_2 (0x26)
#define SR_IEEE_ADDR_2 0x26, 0xff, 0
#define RG_IEEE_ADDR_3 (0x27)
#define SR_IEEE_ADDR_3 0x27, 0xff, 0
#define RG_IEEE_ADDR_4 (0x28)
#define SR_IEEE_ADDR_4 0x28, 0xff, 0
#define RG_IEEE_ADDR_5 (0x29)
#define SR_IEEE_ADDR_5 0x29, 0xff, 0
#define RG_IEEE_ADDR_6 (0x2a)
#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
#define RG_IEEE_ADDR_7 (0x2b)
#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
#define RG_XAH_CTRL_0 (0x2c)
#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
#define RG_CSMA_SEED_0 (0x2d)
#define SR_CSMA_SEED_0 0x2d, 0xff, 0
#define RG_CSMA_SEED_1 (0x2e)
#define SR_CSMA_SEED_1 0x2e, 0x07, 0
#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
#define SR_AACK_SET_PD 0x2e, 0x20, 5
#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
#define RG_CSMA_BE (0x2f)
#define SR_MIN_BE 0x2f, 0x0f, 0
#define SR_MAX_BE 0x2f, 0xf0, 4
#define CMD_REG 0x80
#define CMD_REG_MASK 0x3f
#define CMD_WRITE 0x40
#define CMD_FB 0x20
#define IRQ_BAT_LOW BIT(7)
#define IRQ_TRX_UR BIT(6)
#define IRQ_AMI BIT(5)
#define IRQ_CCA_ED BIT(4)
#define IRQ_TRX_END BIT(3)
#define IRQ_RX_START BIT(2)
#define IRQ_PLL_UNL BIT(1)
#define IRQ_PLL_LOCK BIT(0)
#define IRQ_ACTIVE_HIGH 0
#define IRQ_ACTIVE_LOW 1
#define STATE_P_ON 0x00 /* BUSY */
#define STATE_BUSY_RX 0x01
#define STATE_BUSY_TX 0x02
#define STATE_FORCE_TRX_OFF 0x03
#define STATE_FORCE_TX_ON 0x04 /* IDLE */
/* 0x05 */ /* INVALID_PARAMETER */
#define STATE_RX_ON 0x06
/* 0x07 */ /* SUCCESS */
#define STATE_TRX_OFF 0x08
#define STATE_TX_ON 0x09
/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
#define STATE_SLEEP 0x0F
#define STATE_PREP_DEEP_SLEEP 0x10
#define STATE_BUSY_RX_AACK 0x11
#define STATE_BUSY_TX_ARET 0x12
#define STATE_RX_AACK_ON 0x16
#define STATE_TX_ARET_ON 0x19
#define STATE_RX_ON_NOCLK 0x1C
#define STATE_RX_AACK_ON_NOCLK 0x1D
#define STATE_BUSY_RX_AACK_NOCLK 0x1E
#define STATE_TRANSITION_IN_PROGRESS 0x1F
#define TRX_STATE_MASK (0x1F)
#define TRAC_MASK(x) ((x & 0xe0) >> 5)
#define TRAC_SUCCESS 0
#define TRAC_SUCCESS_DATA_PENDING 1
#define TRAC_SUCCESS_WAIT_FOR_ACK 2
#define TRAC_CHANNEL_ACCESS_FAILURE 3
#define TRAC_NO_ACK 5
#define TRAC_INVALID 7
#endif /* !_AT86RF230_H */
linux-7.2.3/drivers/net/ieee802154/atusb.c
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linux-7.2.3/drivers/net/ieee802154/atusb.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* atusb.h - Definitions shared between kernel and ATUSB firmware
*
* Written 2013 by Werner Almesberger <werner@almesberger.net>
*
* (at your option) any later version.
*
* This file should be identical for kernel and firmware.
* Kernel: drivers/net/ieee802154/atusb.h
* Firmware: ben-wpan/atusb/fw/include/atusb/atusb.h
*/
#ifndef _ATUSB_H
#define _ATUSB_H
#define ATUSB_VENDOR_ID 0x20b7 /* Qi Hardware*/
#define ATUSB_PRODUCT_ID 0x1540 /* 802.15.4, device 0 */
/* -- - - */
#define ATUSB_BUILD_SIZE 256 /* maximum build version/date message length */
/* Commands to our device. Make sure this is synced with the firmware */
enum atusb_requests {
ATUSB_ID = 0x00, /* system status/control grp */
ATUSB_BUILD,
ATUSB_RESET,
ATUSB_RF_RESET = 0x10, /* debug/test group */
ATUSB_POLL_INT,
ATUSB_TEST, /* atusb-sil only */
ATUSB_TIMER,
ATUSB_GPIO,
ATUSB_SLP_TR,
ATUSB_GPIO_CLEANUP,
ATUSB_REG_WRITE = 0x20, /* transceiver group */
ATUSB_REG_READ,
ATUSB_BUF_WRITE,
ATUSB_BUF_READ,
ATUSB_SRAM_WRITE,
ATUSB_SRAM_READ,
ATUSB_SPI_WRITE = 0x30, /* SPI group */
ATUSB_SPI_READ1,
ATUSB_SPI_READ2,
ATUSB_SPI_WRITE2_SYNC,
ATUSB_RX_MODE = 0x40, /* HardMAC group */
ATUSB_TX,
ATUSB_EUI64_WRITE = 0x50, /* Parameter in EEPROM grp */
ATUSB_EUI64_READ,
};
enum {
ATUSB_HW_TYPE_100813, /* 2010-08-13 */
ATUSB_HW_TYPE_101216, /* 2010-12-16 */
ATUSB_HW_TYPE_110131, /* 2011-01-31, ATmega32U2-based */
ATUSB_HW_TYPE_RZUSB, /* Atmel Raven USB dongle with at86rf230 */
ATUSB_HW_TYPE_HULUSB, /* Busware HUL USB dongle with at86rf212 */
};
/*
* Direction bRequest wValue wIndex wLength
*
* ->host ATUSB_ID - - 3
* ->host ATUSB_BUILD - - #bytes
* host-> ATUSB_RESET - - 0
*
* host-> ATUSB_RF_RESET - - 0
* ->host ATUSB_POLL_INT - - 1
* host-> ATUSB_TEST - - 0
* ->host ATUSB_TIMER - - #bytes (6)
* ->host ATUSB_GPIO dir+data mask+p# 3
* host-> ATUSB_SLP_TR - - 0
* host-> ATUSB_GPIO_CLEANUP - - 0
*
* host-> ATUSB_REG_WRITE value addr 0
* ->host ATUSB_REG_READ - addr 1
* host-> ATUSB_BUF_WRITE - - #bytes
* ->host ATUSB_BUF_READ - - #bytes
* host-> ATUSB_SRAM_WRITE - addr #bytes
* ->host ATUSB_SRAM_READ - addr #bytes
*
* host-> ATUSB_SPI_WRITE byte0 byte1 #bytes
* ->host ATUSB_SPI_READ1 byte0 - #bytes
* ->host ATUSB_SPI_READ2 byte0 byte1 #bytes
* ->host ATUSB_SPI_WRITE2_SYNC byte0 byte1 0/1
*
* host-> ATUSB_RX_MODE on - 0
* host-> ATUSB_TX flags ack_seq #bytes
* host-> ATUSB_EUI64_WRITE - - #bytes (8)
* ->host ATUSB_EUI64_READ - - #bytes (8)
*/
#define ATUSB_REQ_FROM_DEV (USB_TYPE_VENDOR | USB_DIR_IN)
#define ATUSB_REQ_TO_DEV (USB_TYPE_VENDOR | USB_DIR_OUT)
#endif /* !_ATUSB_H */
linux-7.2.3/drivers/net/ieee802154/ca8210.c
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linux-7.2.3/drivers/net/ieee802154/cc2520.c
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linux-7.2.3/drivers/net/ieee802154/fakelb.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Loopback IEEE 802.15.4 interface
*
* Copyright 2007-2012 Siemens AG
*
* Written by:
* Sergey Lapin <slapin@ossfans.org>
* Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
* Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
*/
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/platform_device.h>
#include <linux/netdevice.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <net/mac802154.h>
#include <net/cfg802154.h>
static int numlbs = 2;
static LIST_HEAD(fakelb_phys);
static DEFINE_MUTEX(fakelb_phys_lock);
static LIST_HEAD(fakelb_ifup_phys);
static DEFINE_RWLOCK(fakelb_ifup_phys_lock);
struct fakelb_phy {
struct ieee802154_hw *hw;
u8 page;
u8 channel;
bool suspended;
struct list_head list;
struct list_head list_ifup;
};
static int fakelb_hw_ed(struct ieee802154_hw *hw, u8 *level)
{
WARN_ON(!level);
*level = 0xbe;
return 0;
}
static int fakelb_hw_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->page = page;
phy->channel = channel;
write_unlock_bh(&fakelb_ifup_phys_lock);
return 0;
}
static int fakelb_hw_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
{
struct fakelb_phy *current_phy = hw->priv, *phy;
read_lock_bh(&fakelb_ifup_phys_lock);
WARN_ON(current_phy->suspended);
list_for_each_entry(phy, &fakelb_ifup_phys, list_ifup) {
if (current_phy == phy)
continue;
if (current_phy->page == phy->page &&
current_phy->channel == phy->channel) {
struct sk_buff *newskb = pskb_copy(skb, GFP_ATOMIC);
if (newskb)
ieee802154_rx_irqsafe(phy->hw, newskb, 0xcc);
}
}
read_unlock_bh(&fakelb_ifup_phys_lock);
ieee802154_xmit_complete(hw, skb, false);
return 0;
}
static int fakelb_hw_start(struct ieee802154_hw *hw)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->suspended = false;
list_add(&phy->list_ifup, &fakelb_ifup_phys);
write_unlock_bh(&fakelb_ifup_phys_lock);
return 0;
}
static void fakelb_hw_stop(struct ieee802154_hw *hw)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->suspended = true;
list_del(&phy->list_ifup);
write_unlock_bh(&fakelb_ifup_phys_lock);
}
static int
fakelb_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
{
return 0;
}
static const struct ieee802154_ops fakelb_ops = {
.owner = THIS_MODULE,
.xmit_async = fakelb_hw_xmit,
.ed = fakelb_hw_ed,
.set_channel = fakelb_hw_channel,
.start = fakelb_hw_start,
.stop = fakelb_hw_stop,
.set_promiscuous_mode = fakelb_set_promiscuous_mode,
};
/* Number of dummy devices to be set up by this module. */
module_param(numlbs, int, 0);
MODULE_PARM_DESC(numlbs, " number of pseudo devices");
static int fakelb_add_one(struct device *dev)
{
struct ieee802154_hw *hw;
struct fakelb_phy *phy;
int err;
hw = ieee802154_alloc_hw(sizeof(*phy), &fakelb_ops);
if (!hw)
return -ENOMEM;
phy = hw->priv;
phy->hw = hw;
/* 868 MHz BPSK 802.15.4-2003 */
hw->phy->supported.channels[0] |= 1;
/* 915 MHz BPSK 802.15.4-2003 */
hw->phy->supported.channels[0] |= 0x7fe;
/* 2.4 GHz O-QPSK 802.15.4-2003 */
hw->phy->supported.channels[0] |= 0x7FFF800;
/* 868 MHz ASK 802.15.4-2006 */
hw->phy->supported.channels[1] |= 1;
/* 915 MHz ASK 802.15.4-2006 */
hw->phy->supported.channels[1] |= 0x7fe;
/* 868 MHz O-QPSK 802.15.4-2006 */
hw->phy->supported.channels[2] |= 1;
/* 915 MHz O-QPSK 802.15.4-2006 */
hw->phy->supported.channels[2] |= 0x7fe;
/* 2.4 GHz CSS 802.15.4a-2007 */
hw->phy->supported.channels[3] |= 0x3fff;
/* UWB Sub-gigahertz 802.15.4a-2007 */
hw->phy->supported.channels[4] |= 1;
/* UWB Low band 802.15.4a-2007 */
hw->phy->supported.channels[4] |= 0x1e;
/* UWB High band 802.15.4a-2007 */
hw->phy->supported.channels[4] |= 0xffe0;
/* 750 MHz O-QPSK 802.15.4c-2009 */
hw->phy->supported.channels[5] |= 0xf;
/* 750 MHz MPSK 802.15.4c-2009 */
hw->phy->supported.channels[5] |= 0xf0;
/* 950 MHz BPSK 802.15.4d-2009 */
hw->phy->supported.channels[6] |= 0x3ff;
/* 950 MHz GFSK 802.15.4d-2009 */
hw->phy->supported.channels[6] |= 0x3ffc00;
ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
/* fake phy channel 13 as default */
hw->phy->current_channel = 13;
phy->channel = hw->phy->current_channel;
hw->flags = IEEE802154_HW_PROMISCUOUS;
hw->parent = dev;
err = ieee802154_register_hw(hw);
if (err)
goto err_reg;
mutex_lock(&fakelb_phys_lock);
list_add_tail(&phy->list, &fakelb_phys);
mutex_unlock(&fakelb_phys_lock);
return 0;
err_reg:
ieee802154_free_hw(phy->hw);
return err;
}
static void fakelb_del(struct fakelb_phy *phy)
{
list_del(&phy->list);
ieee802154_unregister_hw(phy->hw);
ieee802154_free_hw(phy->hw);
}
static int fakelb_probe(struct platform_device *pdev)
{
struct fakelb_phy *phy, *tmp;
int err, i;
for (i = 0; i < numlbs; i++) {
err = fakelb_add_one(&pdev->dev);
if (err < 0)
goto err_slave;
}
dev_info(&pdev->dev, "added %i fake ieee802154 hardware devices\n", numlbs);
return 0;
err_slave:
mutex_lock(&fakelb_phys_lock);
list_for_each_entry_safe(phy, tmp, &fakelb_phys, list)
fakelb_del(phy);
mutex_unlock(&fakelb_phys_lock);
return err;
}
static void fakelb_remove(struct platform_device *pdev)
{
struct fakelb_phy *phy, *tmp;
mutex_lock(&fakelb_phys_lock);
list_for_each_entry_safe(phy, tmp, &fakelb_phys, list)
fakelb_del(phy);
mutex_unlock(&fakelb_phys_lock);
}
static struct platform_device *ieee802154fake_dev;
static struct platform_driver ieee802154fake_driver = {
.probe = fakelb_probe,
.remove = fakelb_remove,
.driver = {
.name = "ieee802154fakelb",
},
};
static __init int fakelb_init_module(void)
{
ieee802154fake_dev = platform_device_register_simple(
"ieee802154fakelb", -1, NULL, 0);
pr_warn("fakelb driver is marked as deprecated, please use mac802154_hwsim!\n");
return platform_driver_register(&ieee802154fake_driver);
}
static __exit void fake_remove_module(void)
{
platform_driver_unregister(&ieee802154fake_driver);
platform_device_unregister(ieee802154fake_dev);
}
module_init(fakelb_init_module);
module_exit(fake_remove_module);
MODULE_DESCRIPTION("IEEE 802.15.4 loopback driver");
MODULE_LICENSE("GPL");
linux-7.2.3/drivers/net/ieee802154/mac802154_hwsim.c
+1092
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linux-7.2.3/drivers/net/ieee802154/mac802154_hwsim.h
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#ifndef __MAC802154_HWSIM_H
#define __MAC802154_HWSIM_H
/* mac802154 hwsim netlink commands
*
* @MAC802154_HWSIM_CMD_UNSPEC: unspecified command to catch error
* @MAC802154_HWSIM_CMD_GET_RADIO: fetch information about existing radios
* @MAC802154_HWSIM_CMD_SET_RADIO: change radio parameters during runtime
* @MAC802154_HWSIM_CMD_NEW_RADIO: create a new radio with the given parameters
* returns the radio ID (>= 0) or negative on errors, if successful
* then multicast the result
* @MAC802154_HWSIM_CMD_DEL_RADIO: destroy a radio, reply is multicasted
* @MAC802154_HWSIM_CMD_GET_EDGE: fetch information about existing edges
* @MAC802154_HWSIM_CMD_SET_EDGE: change edge parameters during runtime
* @MAC802154_HWSIM_CMD_DEL_EDGE: delete edges between radios
* @MAC802154_HWSIM_CMD_NEW_EDGE: create a new edge between two radios
* @__MAC802154_HWSIM_CMD_MAX: enum limit
*/
enum {
MAC802154_HWSIM_CMD_UNSPEC,
MAC802154_HWSIM_CMD_GET_RADIO,
MAC802154_HWSIM_CMD_SET_RADIO,
MAC802154_HWSIM_CMD_NEW_RADIO,
MAC802154_HWSIM_CMD_DEL_RADIO,
MAC802154_HWSIM_CMD_GET_EDGE,
MAC802154_HWSIM_CMD_SET_EDGE,
MAC802154_HWSIM_CMD_DEL_EDGE,
MAC802154_HWSIM_CMD_NEW_EDGE,
__MAC802154_HWSIM_CMD_MAX,
};
#define MAC802154_HWSIM_CMD_MAX (__MAC802154_HWSIM_MAX - 1)
/* mac802154 hwsim netlink attributes
*
* @MAC802154_HWSIM_ATTR_UNSPEC: unspecified attribute to catch error
* @MAC802154_HWSIM_ATTR_RADIO_ID: u32 attribute to identify the radio
* @MAC802154_HWSIM_ATTR_EDGE: nested attribute of edges
* @MAC802154_HWSIM_ATTR_EDGES: list if nested attributes which contains the
* edge information according the radio id
* @__MAC802154_HWSIM_ATTR_MAX: enum limit
*/
enum {
MAC802154_HWSIM_ATTR_UNSPEC,
MAC802154_HWSIM_ATTR_RADIO_ID,
MAC802154_HWSIM_ATTR_RADIO_EDGE,
MAC802154_HWSIM_ATTR_RADIO_EDGES,
__MAC802154_HWSIM_ATTR_MAX,
};
#define MAC802154_HWSIM_ATTR_MAX (__MAC802154_HWSIM_ATTR_MAX - 1)
/* mac802154 hwsim edge netlink attributes
*
* @MAC802154_HWSIM_EDGE_ATTR_UNSPEC: unspecified attribute to catch error
* @MAC802154_HWSIM_EDGE_ATTR_ENDPOINT_ID: radio id where the edge points to
* @MAC802154_HWSIM_EDGE_ATTR_LQI: LQI value which the endpoint radio will
* receive for this edge
* @__MAC802154_HWSIM_ATTR_MAX: enum limit
*/
enum {
MAC802154_HWSIM_EDGE_ATTR_UNSPEC,
MAC802154_HWSIM_EDGE_ATTR_ENDPOINT_ID,
MAC802154_HWSIM_EDGE_ATTR_LQI,
__MAC802154_HWSIM_EDGE_ATTR_MAX,
};
#define MAC802154_HWSIM_EDGE_ATTR_MAX (__MAC802154_HWSIM_EDGE_ATTR_MAX - 1)
#endif /* __MAC802154_HWSIM_H */
linux-7.2.3/drivers/net/ieee802154/mcr20a.c
+1362
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linux-7.2.3/drivers/net/ieee802154/mcr20a.h
+489
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
*
* Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com>
*/
#ifndef _MCR20A_H
#define _MCR20A_H
/* Direct Accress Register */
#define DAR_IRQ_STS1 0x00
#define DAR_IRQ_STS2 0x01
#define DAR_IRQ_STS3 0x02
#define DAR_PHY_CTRL1 0x03
#define DAR_PHY_CTRL2 0x04
#define DAR_PHY_CTRL3 0x05
#define DAR_RX_FRM_LEN 0x06
#define DAR_PHY_CTRL4 0x07
#define DAR_SRC_CTRL 0x08
#define DAR_SRC_ADDRS_SUM_LSB 0x09
#define DAR_SRC_ADDRS_SUM_MSB 0x0A
#define DAR_CCA1_ED_FNL 0x0B
#define DAR_EVENT_TMR_LSB 0x0C
#define DAR_EVENT_TMR_MSB 0x0D
#define DAR_EVENT_TMR_USB 0x0E
#define DAR_TIMESTAMP_LSB 0x0F
#define DAR_TIMESTAMP_MSB 0x10
#define DAR_TIMESTAMP_USB 0x11
#define DAR_T3CMP_LSB 0x12
#define DAR_T3CMP_MSB 0x13
#define DAR_T3CMP_USB 0x14
#define DAR_T2PRIMECMP_LSB 0x15
#define DAR_T2PRIMECMP_MSB 0x16
#define DAR_T1CMP_LSB 0x17
#define DAR_T1CMP_MSB 0x18
#define DAR_T1CMP_USB 0x19
#define DAR_T2CMP_LSB 0x1A
#define DAR_T2CMP_MSB 0x1B
#define DAR_T2CMP_USB 0x1C
#define DAR_T4CMP_LSB 0x1D
#define DAR_T4CMP_MSB 0x1E
#define DAR_T4CMP_USB 0x1F
#define DAR_PLL_INT0 0x20
#define DAR_PLL_FRAC0_LSB 0x21
#define DAR_PLL_FRAC0_MSB 0x22
#define DAR_PA_PWR 0x23
#define DAR_SEQ_STATE 0x24
#define DAR_LQI_VALUE 0x25
#define DAR_RSSI_CCA_CONT 0x26
/*------------------ 0x27 */
#define DAR_ASM_CTRL1 0x28
#define DAR_ASM_CTRL2 0x29
#define DAR_ASM_DATA_0 0x2A
#define DAR_ASM_DATA_1 0x2B
#define DAR_ASM_DATA_2 0x2C
#define DAR_ASM_DATA_3 0x2D
#define DAR_ASM_DATA_4 0x2E
#define DAR_ASM_DATA_5 0x2F
#define DAR_ASM_DATA_6 0x30
#define DAR_ASM_DATA_7 0x31
#define DAR_ASM_DATA_8 0x32
#define DAR_ASM_DATA_9 0x33
#define DAR_ASM_DATA_A 0x34
#define DAR_ASM_DATA_B 0x35
#define DAR_ASM_DATA_C 0x36
#define DAR_ASM_DATA_D 0x37
#define DAR_ASM_DATA_E 0x38
#define DAR_ASM_DATA_F 0x39
/*----------------------- 0x3A */
#define DAR_OVERWRITE_VER 0x3B
#define DAR_CLK_OUT_CTRL 0x3C
#define DAR_PWR_MODES 0x3D
#define IAR_INDEX 0x3E
#define IAR_DATA 0x3F
/* Indirect Resgister Memory */
#define IAR_PART_ID 0x00
#define IAR_XTAL_TRIM 0x01
#define IAR_PMC_LP_TRIM 0x02
#define IAR_MACPANID0_LSB 0x03
#define IAR_MACPANID0_MSB 0x04
#define IAR_MACSHORTADDRS0_LSB 0x05
#define IAR_MACSHORTADDRS0_MSB 0x06
#define IAR_MACLONGADDRS0_0 0x07
#define IAR_MACLONGADDRS0_8 0x08
#define IAR_MACLONGADDRS0_16 0x09
#define IAR_MACLONGADDRS0_24 0x0A
#define IAR_MACLONGADDRS0_32 0x0B
#define IAR_MACLONGADDRS0_40 0x0C
#define IAR_MACLONGADDRS0_48 0x0D
#define IAR_MACLONGADDRS0_56 0x0E
#define IAR_RX_FRAME_FILTER 0x0F
#define IAR_PLL_INT1 0x10
#define IAR_PLL_FRAC1_LSB 0x11
#define IAR_PLL_FRAC1_MSB 0x12
#define IAR_MACPANID1_LSB 0x13
#define IAR_MACPANID1_MSB 0x14
#define IAR_MACSHORTADDRS1_LSB 0x15
#define IAR_MACSHORTADDRS1_MSB 0x16
#define IAR_MACLONGADDRS1_0 0x17
#define IAR_MACLONGADDRS1_8 0x18
#define IAR_MACLONGADDRS1_16 0x19
#define IAR_MACLONGADDRS1_24 0x1A
#define IAR_MACLONGADDRS1_32 0x1B
#define IAR_MACLONGADDRS1_40 0x1C
#define IAR_MACLONGADDRS1_48 0x1D
#define IAR_MACLONGADDRS1_56 0x1E
#define IAR_DUAL_PAN_CTRL 0x1F
#define IAR_DUAL_PAN_DWELL 0x20
#define IAR_DUAL_PAN_STS 0x21
#define IAR_CCA1_THRESH 0x22
#define IAR_CCA1_ED_OFFSET_COMP 0x23
#define IAR_LQI_OFFSET_COMP 0x24
#define IAR_CCA_CTRL 0x25
#define IAR_CCA2_CORR_PEAKS 0x26
#define IAR_CCA2_CORR_THRESH 0x27
#define IAR_TMR_PRESCALE 0x28
/*-------------------- 0x29 */
#define IAR_GPIO_DATA 0x2A
#define IAR_GPIO_DIR 0x2B
#define IAR_GPIO_PUL_EN 0x2C
#define IAR_GPIO_PUL_SEL 0x2D
#define IAR_GPIO_DS 0x2E
/*------------------ 0x2F */
#define IAR_ANT_PAD_CTRL 0x30
#define IAR_MISC_PAD_CTRL 0x31
#define IAR_BSM_CTRL 0x32
/*------------------- 0x33 */
#define IAR_RNG 0x34
#define IAR_RX_BYTE_COUNT 0x35
#define IAR_RX_WTR_MARK 0x36
#define IAR_SOFT_RESET 0x37
#define IAR_TXDELAY 0x38
#define IAR_ACKDELAY 0x39
#define IAR_SEQ_MGR_CTRL 0x3A
#define IAR_SEQ_MGR_STS 0x3B
#define IAR_SEQ_T_STS 0x3C
#define IAR_ABORT_STS 0x3D
#define IAR_CCCA_BUSY_CNT 0x3E
#define IAR_SRC_ADDR_CHECKSUM1 0x3F
#define IAR_SRC_ADDR_CHECKSUM2 0x40
#define IAR_SRC_TBL_VALID1 0x41
#define IAR_SRC_TBL_VALID2 0x42
#define IAR_FILTERFAIL_CODE1 0x43
#define IAR_FILTERFAIL_CODE2 0x44
#define IAR_SLOT_PRELOAD 0x45
/*-------------------- 0x46 */
#define IAR_CORR_VT 0x47
#define IAR_SYNC_CTRL 0x48
#define IAR_PN_LSB_0 0x49
#define IAR_PN_LSB_1 0x4A
#define IAR_PN_MSB_0 0x4B
#define IAR_PN_MSB_1 0x4C
#define IAR_CORR_NVAL 0x4D
#define IAR_TX_MODE_CTRL 0x4E
#define IAR_SNF_THR 0x4F
#define IAR_FAD_THR 0x50
#define IAR_ANT_AGC_CTRL 0x51
#define IAR_AGC_THR1 0x52
#define IAR_AGC_THR2 0x53
#define IAR_AGC_HYS 0x54
#define IAR_AFC 0x55
/*------------------- 0x56 */
/*------------------- 0x57 */
#define IAR_PHY_STS 0x58
#define IAR_RX_MAX_CORR 0x59
#define IAR_RX_MAX_PREAMBLE 0x5A
#define IAR_RSSI 0x5B
/*------------------- 0x5C */
/*------------------- 0x5D */
#define IAR_PLL_DIG_CTRL 0x5E
#define IAR_VCO_CAL 0x5F
#define IAR_VCO_BEST_DIFF 0x60
#define IAR_VCO_BIAS 0x61
#define IAR_KMOD_CTRL 0x62
#define IAR_KMOD_CAL 0x63
#define IAR_PA_CAL 0x64
#define IAR_PA_PWRCAL 0x65
#define IAR_ATT_RSSI1 0x66
#define IAR_ATT_RSSI2 0x67
#define IAR_RSSI_OFFSET 0x68
#define IAR_RSSI_SLOPE 0x69
#define IAR_RSSI_CAL1 0x6A
#define IAR_RSSI_CAL2 0x6B
/*------------------- 0x6C */
/*------------------- 0x6D */
#define IAR_XTAL_CTRL 0x6E
#define IAR_XTAL_COMP_MIN 0x6F
#define IAR_XTAL_COMP_MAX 0x70
#define IAR_XTAL_GM 0x71
/*------------------- 0x72 */
/*------------------- 0x73 */
#define IAR_LNA_TUNE 0x74
#define IAR_LNA_AGCGAIN 0x75
/*------------------- 0x76 */
/*------------------- 0x77 */
#define IAR_CHF_PMA_GAIN 0x78
#define IAR_CHF_IBUF 0x79
#define IAR_CHF_QBUF 0x7A
#define IAR_CHF_IRIN 0x7B
#define IAR_CHF_QRIN 0x7C
#define IAR_CHF_IL 0x7D
#define IAR_CHF_QL 0x7E
#define IAR_CHF_CC1 0x7F
#define IAR_CHF_CCL 0x80
#define IAR_CHF_CC2 0x81
#define IAR_CHF_IROUT 0x82
#define IAR_CHF_QROUT 0x83
/*------------------- 0x84 */
/*------------------- 0x85 */
#define IAR_RSSI_CTRL 0x86
/*------------------- 0x87 */
/*------------------- 0x88 */
#define IAR_PA_BIAS 0x89
#define IAR_PA_TUNING 0x8A
/*------------------- 0x8B */
/*------------------- 0x8C */
#define IAR_PMC_HP_TRIM 0x8D
#define IAR_VREGA_TRIM 0x8E
/*------------------- 0x8F */
/*------------------- 0x90 */
#define IAR_VCO_CTRL1 0x91
#define IAR_VCO_CTRL2 0x92
/*------------------- 0x93 */
/*------------------- 0x94 */
#define IAR_ANA_SPARE_OUT1 0x95
#define IAR_ANA_SPARE_OUT2 0x96
#define IAR_ANA_SPARE_IN 0x97
#define IAR_MISCELLANEOUS 0x98
/*------------------- 0x99 */
#define IAR_SEQ_MGR_OVRD0 0x9A
#define IAR_SEQ_MGR_OVRD1 0x9B
#define IAR_SEQ_MGR_OVRD2 0x9C
#define IAR_SEQ_MGR_OVRD3 0x9D
#define IAR_SEQ_MGR_OVRD4 0x9E
#define IAR_SEQ_MGR_OVRD5 0x9F
#define IAR_SEQ_MGR_OVRD6 0xA0
#define IAR_SEQ_MGR_OVRD7 0xA1
/*------------------- 0xA2 */
#define IAR_TESTMODE_CTRL 0xA3
#define IAR_DTM_CTRL1 0xA4
#define IAR_DTM_CTRL2 0xA5
#define IAR_ATM_CTRL1 0xA6
#define IAR_ATM_CTRL2 0xA7
#define IAR_ATM_CTRL3 0xA8
/*------------------- 0xA9 */
#define IAR_LIM_FE_TEST_CTRL 0xAA
#define IAR_CHF_TEST_CTRL 0xAB
#define IAR_VCO_TEST_CTRL 0xAC
#define IAR_PLL_TEST_CTRL 0xAD
#define IAR_PA_TEST_CTRL 0xAE
#define IAR_PMC_TEST_CTRL 0xAF
#define IAR_SCAN_DTM_PROTECT_1 0xFE
#define IAR_SCAN_DTM_PROTECT_0 0xFF
/* IRQSTS1 bits */
#define DAR_IRQSTS1_RX_FRM_PEND BIT(7)
#define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
#define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5)
#define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4)
#define DAR_IRQSTS1_CCAIRQ BIT(3)
#define DAR_IRQSTS1_RXIRQ BIT(2)
#define DAR_IRQSTS1_TXIRQ BIT(1)
#define DAR_IRQSTS1_SEQIRQ BIT(0)
/* IRQSTS2 bits */
#define DAR_IRQSTS2_CRCVALID BIT(7)
#define DAR_IRQSTS2_CCA BIT(6)
#define DAR_IRQSTS2_SRCADDR BIT(5)
#define DAR_IRQSTS2_PI BIT(4)
#define DAR_IRQSTS2_TMRSTATUS BIT(3)
#define DAR_IRQSTS2_ASM_IRQ BIT(2)
#define DAR_IRQSTS2_PB_ERR_IRQ BIT(1)
#define DAR_IRQSTS2_WAKE_IRQ BIT(0)
/* IRQSTS3 bits */
#define DAR_IRQSTS3_TMR4MSK BIT(7)
#define DAR_IRQSTS3_TMR3MSK BIT(6)
#define DAR_IRQSTS3_TMR2MSK BIT(5)
#define DAR_IRQSTS3_TMR1MSK BIT(4)
#define DAR_IRQSTS3_TMR4IRQ BIT(3)
#define DAR_IRQSTS3_TMR3IRQ BIT(2)
#define DAR_IRQSTS3_TMR2IRQ BIT(1)
#define DAR_IRQSTS3_TMR1IRQ BIT(0)
/* PHY_CTRL1 bits */
#define DAR_PHY_CTRL1_TMRTRIGEN BIT(7)
#define DAR_PHY_CTRL1_SLOTTED BIT(6)
#define DAR_PHY_CTRL1_CCABFRTX BIT(5)
#define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5
#define DAR_PHY_CTRL1_RXACKRQD BIT(4)
#define DAR_PHY_CTRL1_AUTOACK BIT(3)
#define DAR_PHY_CTRL1_XCVSEQ_MASK 0x07
/* PHY_CTRL2 bits */
#define DAR_PHY_CTRL2_CRC_MSK BIT(7)
#define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6)
#define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
#define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4)
#define DAR_PHY_CTRL2_CCAMSK BIT(3)
#define DAR_PHY_CTRL2_RXMSK BIT(2)
#define DAR_PHY_CTRL2_TXMSK BIT(1)
#define DAR_PHY_CTRL2_SEQMSK BIT(0)
/* PHY_CTRL3 bits */
#define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7)
#define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6)
#define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5)
#define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4)
#define DAR_PHY_CTRL3_ASM_MSK BIT(2)
#define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1)
#define DAR_PHY_CTRL3_WAKE_MSK BIT(0)
/* RX_FRM_LEN bits */
#define DAR_RX_FRAME_LENGTH_MASK (0x7F)
/* PHY_CTRL4 bits */
#define DAR_PHY_CTRL4_TRCV_MSK BIT(7)
#define DAR_PHY_CTRL4_TC3TMOUT BIT(6)
#define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5)
#define DAR_PHY_CTRL4_CCATYPE (3)
#define DAR_PHY_CTRL4_CCATYPE_SHIFT (3)
#define DAR_PHY_CTRL4_CCATYPE_MASK (0x18)
#define DAR_PHY_CTRL4_TMRLOAD BIT(2)
#define DAR_PHY_CTRL4_PROMISCUOUS BIT(1)
#define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0)
/* SRC_CTRL bits */
#define DAR_SRC_CTRL_INDEX (0x0F)
#define DAR_SRC_CTRL_INDEX_SHIFT (4)
#define DAR_SRC_CTRL_ACK_FRM_PND BIT(3)
#define DAR_SRC_CTRL_SRCADDR_EN BIT(2)
#define DAR_SRC_CTRL_INDEX_EN BIT(1)
#define DAR_SRC_CTRL_INDEX_DISABLE BIT(0)
/* DAR_ASM_CTRL1 bits */
#define DAR_ASM_CTRL1_CLEAR BIT(7)
#define DAR_ASM_CTRL1_START BIT(6)
#define DAR_ASM_CTRL1_SELFTST BIT(5)
#define DAR_ASM_CTRL1_CTR BIT(4)
#define DAR_ASM_CTRL1_CBC BIT(3)
#define DAR_ASM_CTRL1_AES BIT(2)
#define DAR_ASM_CTRL1_LOAD_MAC BIT(1)
/* DAR_ASM_CTRL2 bits */
#define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL (7)
#define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5)
#define DAR_ASM_CTRL2_TSTPAS BIT(1)
/* DAR_CLK_OUT_CTRL bits */
#define DAR_CLK_OUT_CTRL_EXTEND BIT(7)
#define DAR_CLK_OUT_CTRL_HIZ BIT(6)
#define DAR_CLK_OUT_CTRL_SR BIT(5)
#define DAR_CLK_OUT_CTRL_DS BIT(4)
#define DAR_CLK_OUT_CTRL_EN BIT(3)
#define DAR_CLK_OUT_CTRL_DIV (7)
/* DAR_PWR_MODES bits */
#define DAR_PWR_MODES_XTAL_READY BIT(5)
#define DAR_PWR_MODES_XTALEN BIT(4)
#define DAR_PWR_MODES_ASM_CLK_EN BIT(3)
#define DAR_PWR_MODES_AUTODOZE BIT(1)
#define DAR_PWR_MODES_PMC_MODE BIT(0)
/* RX_FRAME_FILTER bits */
#define IAR_RX_FRAME_FLT_FRM_VER (0xC0)
#define IAR_RX_FRAME_FLT_FRM_VER_SHIFT (6)
#define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5)
#define IAR_RX_FRAME_FLT_NS_FT BIT(4)
#define IAR_RX_FRAME_FLT_CMD_FT BIT(3)
#define IAR_RX_FRAME_FLT_ACK_FT BIT(2)
#define IAR_RX_FRAME_FLT_DATA_FT BIT(1)
#define IAR_RX_FRAME_FLT_BEACON_FT BIT(0)
/* DUAL_PAN_CTRL bits */
#define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
#define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4)
#define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3)
#define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2)
#define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1)
#define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0)
/* DUAL_PAN_STS bits */
#define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7)
#define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6)
#define IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
/* CCA_CTRL bits */
#define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6)
#define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5)
#define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4)
#define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3)
#define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2)
#define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1)
#define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0)
/* ANT_PAD_CTRL bits */
#define IAR_ANT_PAD_CTRL_ANTX_POL (0x0F)
#define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4)
#define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3)
#define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2)
#define IAR_ANT_PAD_CTRL_ANTX_EN (3)
/* MISC_PAD_CTRL bits */
#define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3)
#define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2)
#define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1)
#define IAR_MISC_PAD_CTRL_ANTX_CURR (1)
/* ANT_AGC_CTRL bits */
#define IAR_ANT_AGC_CTRL_FAD_EN_SHIFT (0)
#define IAR_ANT_AGC_CTRL_FAD_EN_MASK (1)
#define IAR_ANT_AGC_CTRL_ANTX_SHIFT (1)
#define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT)
/* BSM_CTRL bits */
#define BSM_CTRL_BSM_EN (1)
/* SOFT_RESET bits */
#define IAR_SOFT_RESET_SOG_RST BIT(7)
#define IAR_SOFT_RESET_REGS_RST BIT(4)
#define IAR_SOFT_RESET_PLL_RST BIT(3)
#define IAR_SOFT_RESET_TX_RST BIT(2)
#define IAR_SOFT_RESET_RX_RST BIT(1)
#define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0)
/* SEQ_MGR_CTRL bits */
#define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
#define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6)
#define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
#define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
#define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3)
#define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2)
#define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1)
#define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0)
/* SEQ_MGR_STS bits */
#define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7)
#define IAR_SEQ_MGR_STS_RX_MODE BIT(6)
#define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
#define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
#define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3)
#define IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL (7)
/* ABORT_STS bits */
#define IAR_ABORT_STS_PLL_ABORTED BIT(2)
#define IAR_ABORT_STS_TC3_ABORTED BIT(1)
#define IAR_ABORT_STS_SW_ABORTED BIT(0)
/* IAR_FILTERFAIL_CODE2 bits */
#define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7)
#define IAR_FILTERFAIL_CODE2_9_8 (3)
/* PHY_STS bits */
#define IAR_PHY_STS_PLL_UNLOCK BIT(7)
#define IAR_PHY_STS_PLL_LOCK_ERR BIT(6)
#define IAR_PHY_STS_PLL_LOCK BIT(5)
#define IAR_PHY_STS_CRCVALID BIT(3)
#define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2)
#define IAR_PHY_STS_SFD_DET BIT(1)
#define IAR_PHY_STS_PREAMBLE_DET BIT(0)
/* TESTMODE_CTRL bits */
#define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4)
#define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3)
#define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2)
#define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1)
#define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0)
/* DTM_CTRL1 bits */
#define IAR_DTM_CTRL1_ATM_LOCKED BIT(7)
#define IAR_DTM_CTRL1_DTM_EN BIT(6)
#define IAR_DTM_CTRL1_PAGE5 BIT(5)
#define IAR_DTM_CTRL1_PAGE4 BIT(4)
#define IAR_DTM_CTRL1_PAGE3 BIT(3)
#define IAR_DTM_CTRL1_PAGE2 BIT(2)
#define IAR_DTM_CTRL1_PAGE1 BIT(1)
#define IAR_DTM_CTRL1_PAGE0 BIT(0)
/* TX_MODE_CTRL */
#define IAR_TX_MODE_CTRL_TX_INV BIT(4)
#define IAR_TX_MODE_CTRL_BT_EN BIT(3)
#define IAR_TX_MODE_CTRL_DTS2 BIT(2)
#define IAR_TX_MODE_CTRL_DTS1 BIT(1)
#define IAR_TX_MODE_CTRL_DTS0 BIT(0)
#define TX_MODE_CTRL_DTS_MASK (7)
#endif /* _MCR20A_H */
linux-7.2.3/drivers/net/ieee802154/mrf24j40.c
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