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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v3.1.c
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(2, 0),
[CHTYPE_DIR] = BIT(3),
[CH_EE] = GENMASK(7, 4),
[CHID] = GENMASK(12, 8),
/* Bit 13 reserved */
[ERINDEX] = GENMASK(18, 14),
/* Bit 19 reserved */
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(15, 0),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(3, 0),
[EV_EE] = GENMASK(7, 4),
[EV_EVCHID] = GENMASK(15, 8),
[EV_INTYPE] = BIT(16),
/* Bits 17-19 reserved */
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(15, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(9, 5),
[GENERIC_EE] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x0001f098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001f09c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x0001f0a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x0001f0a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x0001f0b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x0001f0c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v3_1 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v3.5.1.c
+305
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@@ -0,0 +1,305 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(2, 0),
[CHTYPE_DIR] = BIT(3),
[CH_EE] = GENMASK(7, 4),
[CHID] = GENMASK(12, 8),
/* Bit 13 reserved */
[ERINDEX] = GENMASK(18, 14),
/* Bit 19 reserved */
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(15, 0),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(3, 0),
[EV_EE] = GENMASK(7, 4),
[EV_EVCHID] = GENMASK(15, 8),
[EV_INTYPE] = BIT(16),
/* Bits 17-19 reserved */
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(15, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(9, 5),
[GENERIC_EE] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
static const u32 reg_hw_param_2_fmask[] = {
[IRAM_SIZE] = GENMASK(2, 0),
[NUM_CH_PER_EE] = GENMASK(7, 3),
[NUM_EV_PER_EE] = GENMASK(12, 8),
[GSI_CH_PEND_TRANSLATE] = BIT(13),
[GSI_CH_FULL_LOGIC] = BIT(14),
/* Bits 15-31 reserved */
};
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x0001f098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001f09c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x0001f0a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x0001f0a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x0001f0b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x0001f0c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[HW_PARAM_2] = &reg_hw_param_2,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v3_5_1 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v4.0.c
+310
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@@ -0,0 +1,310 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(2, 0),
[CHTYPE_DIR] = BIT(3),
[CH_EE] = GENMASK(7, 4),
[CHID] = GENMASK(12, 8),
/* Bit 13 reserved */
[ERINDEX] = GENMASK(18, 14),
/* Bit 19 reserved */
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(15, 0),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
[USE_ESCAPE_BUF_ONLY] = BIT(10),
/* Bits 11-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(3, 0),
[EV_EE] = GENMASK(7, 4),
[EV_EVCHID] = GENMASK(15, 8),
[EV_INTYPE] = BIT(16),
/* Bits 17-19 reserved */
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(15, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(9, 5),
[GENERIC_EE] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
static const u32 reg_hw_param_2_fmask[] = {
[IRAM_SIZE] = GENMASK(2, 0),
[NUM_CH_PER_EE] = GENMASK(7, 3),
[NUM_EV_PER_EE] = GENMASK(12, 8),
[GSI_CH_PEND_TRANSLATE] = BIT(13),
[GSI_CH_FULL_LOGIC] = BIT(14),
[GSI_USE_SDMA] = BIT(15),
[GSI_SDMA_N_INT] = GENMASK(18, 16),
[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
/* Bits 30-31 reserved */
};
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x0001f098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001f09c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x0001f0a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x0001f0a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x0001f0b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x0001f0c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[HW_PARAM_2] = &reg_hw_param_2,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v4_0 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v4.11.c
+315
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@@ -0,0 +1,315 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(2, 0),
[CHTYPE_DIR] = BIT(3),
[CH_EE] = GENMASK(7, 4),
[CHID] = GENMASK(12, 8),
[CHTYPE_PROTOCOL_MSB] = BIT(13),
[ERINDEX] = GENMASK(18, 14),
/* Bit 19 reserved */
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(19, 0),
/* Bits 20-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
[PREFETCH_MODE] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
[DB_IN_BYTES] = BIT(24),
/* Bits 25-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(3, 0),
[EV_EE] = GENMASK(7, 4),
[EV_EVCHID] = GENMASK(15, 8),
[EV_INTYPE] = BIT(16),
/* Bits 17-19 reserved */
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(19, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(9, 5),
[GENERIC_EE] = GENMASK(13, 10),
/* Bits 14-23 reserved */
[GENERIC_PARAMS] = GENMASK(31, 24),
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
static const u32 reg_hw_param_2_fmask[] = {
[IRAM_SIZE] = GENMASK(2, 0),
[NUM_CH_PER_EE] = GENMASK(7, 3),
[NUM_EV_PER_EE] = GENMASK(12, 8),
[GSI_CH_PEND_TRANSLATE] = BIT(13),
[GSI_CH_FULL_LOGIC] = BIT(14),
[GSI_USE_SDMA] = BIT(15),
[GSI_SDMA_N_INT] = GENMASK(18, 16),
[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
[GSI_USE_RD_WR_ENG] = BIT(30),
[GSI_USE_INTER_EE] = BIT(31),
};
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x00012098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001209c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x000120a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x000120a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x000120b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x000120c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[HW_PARAM_2] = &reg_hw_param_2,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v4_11 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v4.5.c
+313
View File
@@ -0,0 +1,313 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(2, 0),
[CHTYPE_DIR] = BIT(3),
[CH_EE] = GENMASK(7, 4),
[CHID] = GENMASK(12, 8),
[CHTYPE_PROTOCOL_MSB] = BIT(13),
[ERINDEX] = GENMASK(18, 14),
/* Bit 19 reserved */
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(15, 0),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
[PREFETCH_MODE] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
/* Bits 24-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(3, 0),
[EV_EE] = GENMASK(7, 4),
[EV_EVCHID] = GENMASK(15, 8),
[EV_INTYPE] = BIT(16),
/* Bits 17-19 reserved */
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(15, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(9, 5),
[GENERIC_EE] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
static const u32 reg_hw_param_2_fmask[] = {
[IRAM_SIZE] = GENMASK(2, 0),
[NUM_CH_PER_EE] = GENMASK(7, 3),
[NUM_EV_PER_EE] = GENMASK(12, 8),
[GSI_CH_PEND_TRANSLATE] = BIT(13),
[GSI_CH_FULL_LOGIC] = BIT(14),
[GSI_USE_SDMA] = BIT(15),
[GSI_SDMA_N_INT] = GENMASK(18, 16),
[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
[GSI_USE_RD_WR_ENG] = BIT(30),
[GSI_USE_INTER_EE] = BIT(31),
};
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x00012098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001209c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x000120a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x000120a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x000120b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x000120c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[HW_PARAM_2] = &reg_hw_param_2,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v4_5 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v4.9.c
+314
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@@ -0,0 +1,314 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(2, 0),
[CHTYPE_DIR] = BIT(3),
[CH_EE] = GENMASK(7, 4),
[CHID] = GENMASK(12, 8),
[CHTYPE_PROTOCOL_MSB] = BIT(13),
[ERINDEX] = GENMASK(18, 14),
/* Bit 19 reserved */
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(19, 0),
/* Bits 20-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
[PREFETCH_MODE] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
[DB_IN_BYTES] = BIT(24),
/* Bits 25-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(3, 0),
[EV_EE] = GENMASK(7, 4),
[EV_EVCHID] = GENMASK(15, 8),
[EV_INTYPE] = BIT(16),
/* Bits 17-19 reserved */
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(15, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(9, 5),
[GENERIC_EE] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
static const u32 reg_hw_param_2_fmask[] = {
[IRAM_SIZE] = GENMASK(2, 0),
[NUM_CH_PER_EE] = GENMASK(7, 3),
[NUM_EV_PER_EE] = GENMASK(12, 8),
[GSI_CH_PEND_TRANSLATE] = BIT(13),
[GSI_CH_FULL_LOGIC] = BIT(14),
[GSI_USE_SDMA] = BIT(15),
[GSI_SDMA_N_INT] = GENMASK(18, 16),
[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
[GSI_USE_RD_WR_ENG] = BIT(30),
[GSI_USE_INTER_EE] = BIT(31),
};
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x00012098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001209c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x000120a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x000120a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x000120b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x000120c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[HW_PARAM_2] = &reg_hw_param_2,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v4_9 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/gsi_reg-v5.0.c
+320
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@@ -0,0 +1,320 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../gsi_reg.h"
#include "../ipa_version.h"
#include "../reg.h"
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c01c + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c028 + 0x1000 * GSI_EE_AP);
static const u32 reg_ch_c_cntxt_0_fmask[] = {
[CHTYPE_PROTOCOL] = GENMASK(6, 0),
[CHTYPE_DIR] = BIT(7),
[CH_EE] = GENMASK(11, 8),
[CHID] = GENMASK(19, 12),
[CHSTATE] = GENMASK(23, 20),
[ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_cntxt_1_fmask[] = {
[CH_R_LENGTH] = GENMASK(23, 0),
[CH_ERINDEX] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
static const u32 reg_ch_c_qos_fmask[] = {
[WRR_WEIGHT] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_PREFETCH] = BIT(8),
[USE_DB_ENG] = BIT(9),
[PREFETCH_MODE] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
[DB_IN_BYTES] = BIT(24),
[LOW_LATENCY_EN] = BIT(25),
/* Bits 26-31 reserved */
};
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
0x0001404c + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
0x00014050 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
0x00014054 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
0x00014058 + 0x12000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
[EV_CHTYPE] = GENMASK(6, 0),
[EV_INTYPE] = BIT(7),
[EV_EVCHID] = GENMASK(15, 8),
[EV_EE] = GENMASK(19, 16),
[EV_CHSTATE] = GENMASK(23, 20),
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
0x0001c000 + 0x12000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
[R_LENGTH] = GENMASK(23, 0),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
0x0001c004 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
0x0001c008 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
0x0001c00c + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
0x0001c010 + 0x12000 * GSI_EE_AP, 0x80);
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
[EV_MODT] = GENMASK(15, 0),
[EV_MODC] = GENMASK(23, 16),
[EV_MOD_CNT] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
0x0001c020 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
0x0001c024 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
0x0001c028 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
0x0001c02c + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
0x0001c030 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
0x0001c034 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
0x0001c048 + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
0x0001c04c + 0x12000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
0x00024000 + 0x12000 * GSI_EE_AP, 0x08);
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x00024800 + 0x12000 * GSI_EE_AP, 0x08);
static const u32 reg_gsi_status_fmask[] = {
[ENABLED] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(GSI_STATUS, gsi_status, 0x00025000 + 0x12000 * GSI_EE_AP);
static const u32 reg_ch_cmd_fmask[] = {
[CH_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[CH_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(CH_CMD, ch_cmd, 0x00025008 + 0x12000 * GSI_EE_AP);
static const u32 reg_ev_ch_cmd_fmask[] = {
[EV_CHID] = GENMASK(7, 0),
/* Bits 8-23 reserved */
[EV_OPCODE] = GENMASK(31, 24),
};
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00025010 + 0x12000 * GSI_EE_AP);
static const u32 reg_generic_cmd_fmask[] = {
[GENERIC_OPCODE] = GENMASK(4, 0),
[GENERIC_CHID] = GENMASK(12, 5),
[GENERIC_EE] = GENMASK(16, 13),
/* Bits 17-23 reserved */
[GENERIC_PARAMS] = GENMASK(31, 24),
};
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00025018 + 0x12000 * GSI_EE_AP);
static const u32 reg_hw_param_2_fmask[] = {
[NUM_CH_PER_EE] = GENMASK(7, 0),
[IRAM_SIZE] = GENMASK(12, 8),
[GSI_CH_PEND_TRANSLATE] = BIT(13),
[GSI_CH_FULL_LOGIC] = BIT(14),
[GSI_USE_SDMA] = BIT(15),
[GSI_SDMA_N_INT] = GENMASK(18, 16),
[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
[GSI_USE_RD_WR_ENG] = BIT(30),
[GSI_USE_INTER_EE] = BIT(31),
};
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00025040 + 0x12000 * GSI_EE_AP);
static const u32 reg_hw_param_4_fmask[] = {
[EV_PER_EE] = GENMASK(7, 0),
[IRAM_PROTOCOL_COUNT] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
REG_FIELDS(HW_PARAM_4, hw_param_4, 0x00025050 + 0x12000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00025080 + 0x12000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00025088 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00025090 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x00025094 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x00025098 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0002509c + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x000250a0 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x000250a4 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000250a8 + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x000250ac + 0x12000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x000250b0 + 0x12000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00025200 + 0x12000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00025204 + 0x12000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00025208 + 0x12000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0002520c + 0x12000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00025210 + 0x12000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00025214 + 0x12000 * GSI_EE_AP);
static const u32 reg_cntxt_intset_fmask[] = {
[INTYPE] = BIT(0)
/* Bits 1-31 reserved */
};
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00025220 + 0x12000 * GSI_EE_AP);
static const u32 reg_error_log_fmask[] = {
[ERR_ARG3] = GENMASK(3, 0),
[ERR_ARG2] = GENMASK(7, 4),
[ERR_ARG1] = GENMASK(11, 8),
[ERR_CODE] = GENMASK(15, 12),
/* Bits 16-18 reserved */
[ERR_VIRT_IDX] = GENMASK(23, 19),
[ERR_TYPE] = GENMASK(27, 24),
[ERR_EE] = GENMASK(31, 28),
};
REG_FIELDS(ERROR_LOG, error_log, 0x00025240 + 0x12000 * GSI_EE_AP);
REG(ERROR_LOG_CLR, error_log_clr, 0x00025244 + 0x12000 * GSI_EE_AP);
static const u32 reg_cntxt_scratch_0_fmask[] = {
[INTER_EE_RESULT] = GENMASK(2, 0),
/* Bits 3-4 reserved */
[GENERIC_EE_RESULT] = GENMASK(7, 5),
/* Bits 8-31 reserved */
};
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00025400 + 0x12000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
[CH_C_QOS] = &reg_ch_c_qos,
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[GSI_STATUS] = &reg_gsi_status,
[CH_CMD] = &reg_ch_cmd,
[EV_CH_CMD] = &reg_ev_ch_cmd,
[GENERIC_CMD] = &reg_generic_cmd,
[HW_PARAM_2] = &reg_hw_param_2,
[HW_PARAM_4] = &reg_hw_param_4,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[ERROR_LOG] = &reg_error_log,
[ERROR_LOG_CLR] = &reg_error_log_clr,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v5_0 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v3.1.c
+436
View File
@@ -0,0 +1,436 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
[COMP_CFG_ENABLE] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[IPA_DCMP_FAST_CLK_EN] = BIT(4),
/* Bits 5-31 reserved */
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_counter_cfg_fmask[] = {
[EOT_COAL_GRANULARITY] = GENMASK(3, 0),
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 5-31 reserved */
};
REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020);
static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000040c, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
0x0000050c, 0x0020);
static const u32 reg_endp_init_ctrl_fmask[] = {
[ENDP_SUSPEND] = BIT(0),
[ENDP_DELAY] = BIT(1),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
[HDR_A5_MUX] = BIT(26),
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_METADATA_REG_VALID] = BIT(28),
/* Bits 29-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
/* Bit 3 reserved */
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
[HDR_FTCH_DISABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(9, 5),
[TIME_LIMIT] = GENMASK(14, 10),
[PKT_LIMIT] = GENMASK(20, 15),
[SW_EOF_ACTIVE] = BIT(21),
[FORCE_CLOSE] = BIT(22),
/* Bit 23 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(24),
/* Bits 25-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
/* Entire register is a tick count */
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_BASE_VALUE] = GENMASK(31, 0),
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
[SEQ_REP_TYPE] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-7 reserved */
[STATUS_LOCATION] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
[FILTER_HASH_MSK_SRC_PORT] = BIT(3),
[FILTER_HASH_MSK_DST_PORT] = BIT(4),
[FILTER_HASH_MSK_PROTOCOL] = BIT(5),
[FILTER_HASH_MSK_METADATA] = BIT(6),
[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
/* Bits 7-15 reserved */
[ROUTER_HASH_MSK_SRC_ID] = BIT(16),
[ROUTER_HASH_MSK_SRC_IP] = BIT(17),
[ROUTER_HASH_MSK_DST_IP] = BIT(18),
[ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
[ROUTER_HASH_MSK_DST_PORT] = BIT(20),
[ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
[ROUTER_HASH_MSK_METADATA] = BIT(22),
[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
/* Bits 23-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[IPA_BCR] = &reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[COUNTER_CFG] = &reg_counter_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[SRC_RSRC_GRP_67_RSRC_TYPE] = &reg_src_rsrc_grp_67_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_67_RSRC_TYPE] = &reg_dst_rsrc_grp_67_rsrc_type,
[ENDP_INIT_CTRL] = &reg_endp_init_ctrl,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v3_1 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v3.5.1.c
+446
View File
@@ -0,0 +1,446 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
[COMP_CFG_ENABLE] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[IPA_DCMP_FAST_CLK_EN] = BIT(4),
/* Bits 5-31 reserved */
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bit 17 reserved */
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
/* Bits 22-31 reserved */
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_counter_cfg_fmask[] = {
/* Bits 0-3 reserved */
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 5-31 reserved */
};
REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 reg_ipa_tx_cfg_fmask[] = {
[TX0_PREFETCH_DISABLE] = BIT(0),
[TX1_PREFETCH_DISABLE] = BIT(1),
[PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2),
/* Bits 5-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[MAX_PROD_PIPES] = GENMASK(20, 16),
/* Bits 21-23 reserved */
[PROD_LOWEST] = GENMASK(27, 24),
/* Bits 28-31 reserved */
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_endp_init_ctrl_fmask[] = {
[ENDP_SUSPEND] = BIT(0),
[ENDP_DELAY] = BIT(1),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
[HDR_A5_MUX] = BIT(26),
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_METADATA_REG_VALID] = BIT(28),
/* Bits 29-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
/* Bit 3 reserved */
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
[HDR_FTCH_DISABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(9, 5),
[TIME_LIMIT] = GENMASK(14, 10),
[PKT_LIMIT] = GENMASK(20, 15),
[SW_EOF_ACTIVE] = BIT(21),
[FORCE_CLOSE] = BIT(22),
/* Bit 23 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(24),
/* Bits 25-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
/* Entire register is a tick count */
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_BASE_VALUE] = GENMASK(31, 0),
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
[SEQ_REP_TYPE] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-7 reserved */
[STATUS_LOCATION] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
[FILTER_HASH_MSK_SRC_PORT] = BIT(3),
[FILTER_HASH_MSK_DST_PORT] = BIT(4),
[FILTER_HASH_MSK_PROTOCOL] = BIT(5),
[FILTER_HASH_MSK_METADATA] = BIT(6),
[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
/* Bits 7-15 reserved */
[ROUTER_HASH_MSK_SRC_ID] = BIT(16),
[ROUTER_HASH_MSK_SRC_IP] = BIT(17),
[ROUTER_HASH_MSK_DST_IP] = BIT(18),
[ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
[ROUTER_HASH_MSK_DST_PORT] = BIT(20),
[ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
[ROUTER_HASH_MSK_METADATA] = BIT(22),
[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
/* Bits 23-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[IPA_BCR] = &reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[COUNTER_CFG] = &reg_counter_cfg,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CTRL] = &reg_endp_init_ctrl,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v3_5_1 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v4.11.c
+502
View File
@@ -0,0 +1,502 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
/* Bit 18 reserved */
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22),
/* Bits 24-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bit 17 reserved */
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
[DRBIP] = BIT(31),
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bits 19-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[MAX_PROD_PIPES] = GENMASK(20, 16),
/* Bits 21-23 reserved */
[PROD_LOWEST] = GENMASK(27, 24),
/* Bits 28-31 reserved */
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
/* Bits 9-31 reserved */
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
/* Bit 26 reserved */
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
/* Bits 22-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
[DRBIP_ACL_ENABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
/* Bits 28-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
[FILTER_HASH_MSK_SRC_PORT] = BIT(3),
[FILTER_HASH_MSK_DST_PORT] = BIT(4),
[FILTER_HASH_MSK_PROTOCOL] = BIT(5),
[FILTER_HASH_MSK_METADATA] = BIT(6),
[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
/* Bits 7-15 reserved */
[ROUTER_HASH_MSK_SRC_ID] = BIT(16),
[ROUTER_HASH_MSK_SRC_IP] = BIT(17),
[ROUTER_HASH_MSK_DST_IP] = BIT(18),
[ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
[ROUTER_HASH_MSK_DST_PORT] = BIT(20),
[ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
[ROUTER_HASH_MSK_METADATA] = BIT(22),
[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
/* Bits 23-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_11 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v4.2.c
+460
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@@ -0,0 +1,460 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
/* Bit 0 reserved */
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[IPA_DCMP_FAST_CLK_EN] = BIT(4),
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
/* Bits 21-31 reserved */
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bit 17 reserved */
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
/* Bits 30-31 reserved */
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_counter_cfg_fmask[] = {
/* Bits 0-3 reserved */
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 9-31 reserved */
};
REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
/* Bit 17 reserved */
[SSPND_PA_NO_START_STATE] = BIT(18),
[SSPND_PA_NO_BQ_STATE] = BIT(19),
/* Bits 20-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[MAX_PROD_PIPES] = GENMASK(20, 16),
/* Bits 21-23 reserved */
[PROD_LOWEST] = GENMASK(27, 24),
/* Bits 28-31 reserved */
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
[HDR_A5_MUX] = BIT(26),
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_METADATA_REG_VALID] = BIT(28),
/* Bits 29-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
/* Bit 3 reserved */
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
[HDR_FTCH_DISABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(9, 5),
[TIME_LIMIT] = GENMASK(14, 10),
[PKT_LIMIT] = GENMASK(20, 15),
[SW_EOF_ACTIVE] = BIT(21),
[FORCE_CLOSE] = BIT(22),
/* Bit 23 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(24),
/* Bits 25-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_BASE_VALUE] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_SCALE] = GENMASK(12, 8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
[SEQ_REP_TYPE] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-7 reserved */
[STATUS_LOCATION] = BIT(8),
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[IPA_BCR] = &reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[COUNTER_CFG] = &reg_counter_cfg,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_2 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v4.5.c
+523
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@@ -0,0 +1,523 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
/* Bit 0 reserved */
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
/* Bits 22-31 reserved */
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
[CLKON_DCMP] = BIT(17),
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
/* Bit 31 reserved */
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
/* Bits 18-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[MAX_PROD_PIPES] = GENMASK(20, 16),
/* Bits 21-23 reserved */
[PROD_LOWEST] = GENMASK(27, 24),
/* Bits 28-31 reserved */
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
[HDR_A5_MUX] = BIT(26),
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
/* Bits 22-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
/* Bits 28-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
[FILTER_HASH_MSK_SRC_PORT] = BIT(3),
[FILTER_HASH_MSK_DST_PORT] = BIT(4),
[FILTER_HASH_MSK_PROTOCOL] = BIT(5),
[FILTER_HASH_MSK_METADATA] = BIT(6),
[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
/* Bits 7-15 reserved */
[ROUTER_HASH_MSK_SRC_ID] = BIT(16),
[ROUTER_HASH_MSK_SRC_IP] = BIT(17),
[ROUTER_HASH_MSK_DST_IP] = BIT(18),
[ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
[ROUTER_HASH_MSK_DST_PORT] = BIT(20),
[ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
[ROUTER_HASH_MSK_METADATA] = BIT(22),
[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
/* Bits 23-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_5 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v4.7.c
+494
View File
@@ -0,0 +1,494 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
/* Bits 22-31 reserved */
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
[CLKON_DCMP] = BIT(17),
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
[DRBIP] = BIT(31),
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bits 19-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[MAX_PROD_PIPES] = GENMASK(20, 16),
/* Bits 21-23 reserved */
[PROD_LOWEST] = GENMASK(27, 24),
/* Bits 28-31 reserved */
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
[HDR_A5_MUX] = BIT(26),
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
/* Bits 22-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
/* Bits 28-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
[FILTER_HASH_MSK_SRC_PORT] = BIT(3),
[FILTER_HASH_MSK_DST_PORT] = BIT(4),
[FILTER_HASH_MSK_PROTOCOL] = BIT(5),
[FILTER_HASH_MSK_METADATA] = BIT(6),
[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
/* Bits 7-15 reserved */
[ROUTER_HASH_MSK_SRC_ID] = BIT(16),
[ROUTER_HASH_MSK_SRC_IP] = BIT(17),
[ROUTER_HASH_MSK_DST_IP] = BIT(18),
[ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
[ROUTER_HASH_MSK_DST_PORT] = BIT(20),
[ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
[ROUTER_HASH_MSK_METADATA] = BIT(22),
[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
/* Bits 23-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_7 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v4.9.c
+499
View File
@@ -0,0 +1,499 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22),
/* Bits 25-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
[CLKON_DCMP] = BIT(17),
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
[DRBIP] = BIT(31),
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = BIT(8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = BIT(12),
/* Bits 13-31 reserved */
};
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bits 19-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[MAX_PROD_PIPES] = GENMASK(20, 16),
/* Bits 21-23 reserved */
[PROD_LOWEST] = GENMASK(27, 24),
/* Bits 28-31 reserved */
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
/* Bits 22-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
/* Bits 9-11 reserved */
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
[DRBIP_ACL_ENABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
/* Bits 28-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
[FILTER_HASH_MSK_SRC_PORT] = BIT(3),
[FILTER_HASH_MSK_DST_PORT] = BIT(4),
[FILTER_HASH_MSK_PROTOCOL] = BIT(5),
[FILTER_HASH_MSK_METADATA] = BIT(6),
[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
/* Bits 7-15 reserved */
[ROUTER_HASH_MSK_SRC_ID] = BIT(16),
[ROUTER_HASH_MSK_SRC_IP] = BIT(17),
[ROUTER_HASH_MSK_DST_IP] = BIT(18),
[ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
[ROUTER_HASH_MSK_DST_PORT] = BIT(20),
[ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
[ROUTER_HASH_MSK_METADATA] = BIT(22),
[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
/* Bits 23-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_9 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v5.0.c
+566
View File
@@ -0,0 +1,566 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(7, 0),
[MAX_CONS_PIPES] = GENMASK(15, 8),
[MAX_PROD_PIPES] = GENMASK(23, 16),
[PROD_LOWEST] = GENMASK(31, 24),
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
/* Bit 18 reserved */
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
/* Bits 28-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bit 17 reserved */
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
[DRBIP] = BIT(31),
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
static const u32 reg_route_fmask[] = {
[ROUTE_DEF_PIPE] = GENMASK(7, 0),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
[ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
[ROUTE_DEF_HDR_TABLE] = BIT(26),
[ROUTE_DEF_RETAIN_HDR] = BIT(27),
[ROUTE_DIS] = BIT(28),
/* Bits 29-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000038);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
static const u32 reg_filt_rout_cache_flush_fmask[] = {
[ROUTER_CACHE] = BIT(0),
/* Bits 1-3 reserved */
[FILTER_CACHE] = BIT(4),
/* Bits 5-31 reserved */
};
REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bit 19 reserved */
[HOLB_STICKY_DROP_EN] = BIT(20),
/* Bits 21-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
[PULSE_GRAN_3] = GENMASK(11, 9),
/* Bits 12-31 reserved */
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000050c, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000600, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000604, 0x0020);
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000608, 0x0020);
static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
0x0000060c, 0x0020);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
/* Bit 26 reserved */
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
[HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
/* Bit 23 reserved */
[HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00001018, 0x0080);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(11, 4),
[BYTE_THRESHOLD] = GENMASK(27, 12),
[PIPE_REPLICATION_EN] = BIT(28),
[PAD_EN] = BIT(29),
[DRBIP_ACL_ENABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
/* Bits 28-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000102c, 0x0080);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = GENMASK(9, 8),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00001030, 0x0080);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(8, 1),
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
static const u32 reg_endp_filter_cache_cfg_fmask[] = {
[CACHE_MSK_SRC_ID] = BIT(0),
[CACHE_MSK_SRC_IP] = BIT(1),
[CACHE_MSK_DST_IP] = BIT(2),
[CACHE_MSK_SRC_PORT] = BIT(3),
[CACHE_MSK_DST_PORT] = BIT(4),
[CACHE_MSK_PROTOCOL] = BIT(5),
[CACHE_MSK_METADATA] = BIT(6),
/* Bits 7-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
0x0000105c, 0x0080);
static const u32 reg_endp_router_cache_cfg_fmask[] = {
[CACHE_MSK_SRC_ID] = BIT(0),
[CACHE_MSK_SRC_IP] = BIT(1),
[CACHE_MSK_DST_IP] = BIT(2),
[CACHE_MSK_SRC_PORT] = BIT(3),
[CACHE_MSK_DST_PORT] = BIT(4),
[CACHE_MSK_PROTOCOL] = BIT(5),
[CACHE_MSK_METADATA] = BIT(6),
/* Bits 7-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
0x00001070, 0x0080);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_CACHE_FLUSH] = &reg_filt_rout_cache_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[SRC_RSRC_GRP_67_RSRC_TYPE] = &reg_src_rsrc_grp_67_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_67_RSRC_TYPE] = &reg_dst_rsrc_grp_67_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_CACHE_CFG] = &reg_endp_filter_cache_cfg,
[ENDP_ROUTER_CACHE_CFG] = &reg_endp_router_cache_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v5_0 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
linux-7.2.3/drivers/net/ipa/reg/ipa_reg-v5.5.c
+565
View File
@@ -0,0 +1,565 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023-2024 Linaro Ltd. */
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(7, 0),
[MAX_CONS_PIPES] = GENMASK(15, 8),
[MAX_PROD_PIPES] = GENMASK(23, 16),
[PROD_LOWEST] = GENMASK(31, 24),
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
/* Bits 17-18 reserved */
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
/* Bits 28-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bit 17 reserved */
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
[DRBIP] = BIT(31),
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050);
static const u32 reg_route_fmask[] = {
[ROUTE_DEF_PIPE] = GENMASK(7, 0),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
[ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
[ROUTE_DEF_HDR_TABLE] = BIT(26),
[ROUTE_DEF_RETAIN_HDR] = BIT(27),
[ROUTE_DIS] = BIT(28),
/* Bits 29-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000054);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000070);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000074);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000120, 0x0004);
static const u32 reg_filt_rout_cache_flush_fmask[] = {
[ROUTER_CACHE] = BIT(0),
/* Bits 1-3 reserved */
[FILTER_CACHE] = BIT(4),
/* Bits 5-31 reserved */
};
REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bit 19 reserved */
[HOLB_STICKY_DROP_EN] = BIT(20),
/* Bits 21-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
/* Bits 0-7 reserved */
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
[PULSE_GRAN_3] = GENMASK(11, 9),
/* Bits 12-31 reserved */
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000050c, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000600, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000604, 0x0020);
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000608, 0x0020);
static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
0x0000060c, 0x0020);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
[PIPE_REPLICATE_EN] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
/* Bit 26 reserved */
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
[HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
/* Bit 23 reserved */
[HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00001018, 0x0080);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(11, 4),
[BYTE_THRESHOLD] = GENMASK(27, 12),
/* Bit 28 reserved */
[PAD_EN] = BIT(29),
[DRBIP_ACL_ENABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
[AGGR_COAL_L2] = BIT(28),
/* Bits 27-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000102c, 0x0080);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = GENMASK(9, 8),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00001030, 0x0080);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(8, 1),
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
static const u32 reg_endp_filter_cache_cfg_fmask[] = {
[CACHE_MSK_SRC_ID] = BIT(0),
[CACHE_MSK_SRC_IP] = BIT(1),
[CACHE_MSK_DST_IP] = BIT(2),
[CACHE_MSK_SRC_PORT] = BIT(3),
[CACHE_MSK_DST_PORT] = BIT(4),
[CACHE_MSK_PROTOCOL] = BIT(5),
[CACHE_MSK_METADATA] = BIT(6),
/* Bits 7-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
0x0000105c, 0x0080);
static const u32 reg_endp_router_cache_cfg_fmask[] = {
[CACHE_MSK_SRC_ID] = BIT(0),
[CACHE_MSK_SRC_IP] = BIT(1),
[CACHE_MSK_DST_IP] = BIT(2),
[CACHE_MSK_SRC_PORT] = BIT(3),
[CACHE_MSK_DST_PORT] = BIT(4),
[CACHE_MSK_PROTOCOL] = BIT(5),
[CACHE_MSK_METADATA] = BIT(6),
/* Bits 7-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
0x00001060, 0x0080);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_CACHE_FLUSH] = &reg_filt_rout_cache_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[SRC_RSRC_GRP_67_RSRC_TYPE] = &reg_src_rsrc_grp_67_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_67_RSRC_TYPE] = &reg_dst_rsrc_grp_67_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_CACHE_CFG] = &reg_endp_filter_cache_cfg,
[ENDP_ROUTER_CACHE_CFG] = &reg_endp_router_cache_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v5_5 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};