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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
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// SPDX-License-Identifier: GPL-2.0+
/* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/seq_file.h>
#include <linux/workqueue.h>
#include <linux/completion.h>
#include "pcie_priv.h"
#include "bus.h"
#include "shm_ipc.h"
#include "core.h"
#include "debug.h"
#include "util.h"
#include "qtn_hw_ids.h"
#define QTN_SYSCTL_BAR 0
#define QTN_SHMEM_BAR 2
#define QTN_DMA_BAR 3
#define QTN_PCIE_MAX_FW_BUFSZ (1 * 1024 * 1024)
static bool use_msi = true;
module_param(use_msi, bool, 0644);
MODULE_PARM_DESC(use_msi, "set 0 to use legacy interrupt");
static unsigned int tx_bd_size_param;
module_param(tx_bd_size_param, uint, 0644);
MODULE_PARM_DESC(tx_bd_size_param, "Tx descriptors queue size");
static unsigned int rx_bd_size_param;
module_param(rx_bd_size_param, uint, 0644);
MODULE_PARM_DESC(rx_bd_size_param, "Rx descriptors queue size");
static u8 flashboot = 1;
module_param(flashboot, byte, 0644);
MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary file on FS");
static unsigned int fw_blksize_param = QTN_PCIE_MAX_FW_BUFSZ;
module_param(fw_blksize_param, uint, 0644);
MODULE_PARM_DESC(fw_blksize_param, "firmware loading block size in bytes");
#define DRV_NAME "qtnfmac_pcie"
int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb)
{
struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
int ret;
ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len);
if (ret == -ETIMEDOUT) {
pr_err("EP firmware is dead\n");
bus->fw_state = QTNF_FW_STATE_DEAD;
}
return ret;
}
int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv)
{
struct sk_buff **vaddr;
int len;
len = priv->tx_bd_num * sizeof(*priv->tx_skb) +
priv->rx_bd_num * sizeof(*priv->rx_skb);
vaddr = devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL);
if (!vaddr)
return -ENOMEM;
priv->tx_skb = vaddr;
vaddr += priv->tx_bd_num;
priv->rx_skb = vaddr;
return 0;
}
static void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus)
{
struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
struct pci_dev *pdev = priv->pdev;
get_device(&pdev->dev);
schedule_work(&bus->fw_work);
}
static int qtnf_dbg_mps_show(struct seq_file *s, void *data)
{
struct qtnf_bus *bus = dev_get_drvdata(s->private);
struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
seq_printf(s, "%d\n", pcie_get_mps(priv->pdev));
return 0;
}
static int qtnf_dbg_msi_show(struct seq_file *s, void *data)
{
struct qtnf_bus *bus = dev_get_drvdata(s->private);
struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
seq_printf(s, "%u\n", priv->msi_enabled);
return 0;
}
static int qtnf_dbg_shm_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus = dev_get_drvdata(s->private);
struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n",
priv->shm_ipc_ep_in.tx_packet_count);
seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n",
priv->shm_ipc_ep_in.rx_packet_count);
seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n",
priv->shm_ipc_ep_out.tx_timeout_count);
seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n",
priv->shm_ipc_ep_out.rx_packet_count);
return 0;
}
int qtnf_pcie_fw_boot_done(struct qtnf_bus *bus)
{
struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
char card_id[64];
int ret;
bus->fw_state = QTNF_FW_STATE_BOOT_DONE;
ret = qtnf_core_attach(bus);
if (ret) {
pr_err("failed to attach core\n");
} else {
snprintf(card_id, sizeof(card_id), "%s:%s",
DRV_NAME, pci_name(priv->pdev));
qtnf_debugfs_init(bus, card_id);
qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show);
qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show);
qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats);
}
return ret;
}
static void qtnf_tune_pcie_mps(struct pci_dev *pdev)
{
struct pci_dev *parent;
int mps_p, mps_o, mps_m, mps;
int ret;
/* current mps */
mps_o = pcie_get_mps(pdev);
/* maximum supported mps */
mps_m = 128 << pdev->pcie_mpss;
/* suggested new mps value */
mps = mps_m;
if (pdev->bus && pdev->bus->self) {
/* parent (bus) mps */
parent = pdev->bus->self;
if (pci_is_pcie(parent)) {
mps_p = pcie_get_mps(parent);
mps = min(mps_m, mps_p);
}
}
ret = pcie_set_mps(pdev, mps);
if (ret) {
pr_err("failed to set mps to %d, keep using current %d\n",
mps, mps_o);
return;
}
pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m);
}
static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv, bool use_msi)
{
struct pci_dev *pdev = priv->pdev;
/* fall back to legacy INTx interrupts by default */
priv->msi_enabled = 0;
/* check if MSI capability is available */
if (use_msi) {
if (!pci_enable_msi(pdev)) {
pr_debug("enabled MSI interrupt\n");
priv->msi_enabled = 1;
} else {
pr_warn("failed to enable MSI interrupts");
}
}
if (!priv->msi_enabled) {
pr_warn("legacy PCIE interrupts enabled\n");
pcim_intx(pdev, 1);
}
}
static void __iomem *qtnf_map_bar(struct pci_dev *pdev, u8 index)
{
void __iomem *vaddr;
dma_addr_t busaddr;
size_t len;
int ret;
ret = pcim_iomap_regions(pdev, 1 << index, "qtnfmac_pcie");
if (ret)
return IOMEM_ERR_PTR(ret);
busaddr = pci_resource_start(pdev, index);
len = pci_resource_len(pdev, index);
vaddr = pcim_iomap_table(pdev)[index];
if (!vaddr)
return IOMEM_ERR_PTR(-ENOMEM);
pr_debug("BAR%u vaddr=0x%p busaddr=%pad len=%u\n",
index, vaddr, &busaddr, (int)len);
return vaddr;
}
static void qtnf_pcie_control_rx_callback(void *arg, const u8 __iomem *buf,
size_t len)
{
struct qtnf_pcie_bus_priv *priv = arg;
struct qtnf_bus *bus = pci_get_drvdata(priv->pdev);
struct sk_buff *skb;
if (unlikely(len == 0)) {
pr_warn("zero length packet received\n");
return;
}
skb = __dev_alloc_skb(len, GFP_KERNEL);
if (unlikely(!skb)) {
pr_err("failed to allocate skb\n");
return;
}
memcpy_fromio(skb_put(skb, len), buf, len);
qtnf_trans_handle_rx_ctl_packet(bus, skb);
}
void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
const struct qtnf_shm_ipc_int *ipc_int)
{
const struct qtnf_shm_ipc_rx_callback rx_callback = {
qtnf_pcie_control_rx_callback, priv };
qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND,
ipc_tx_reg, priv->workqueue,
ipc_int, &rx_callback);
qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND,
ipc_rx_reg, priv->workqueue,
ipc_int, &rx_callback);
}
static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct qtnf_pcie_bus_priv *pcie_priv;
struct qtnf_bus *bus;
void __iomem *sysctl_bar;
void __iomem *epmem_bar;
void __iomem *dmareg_bar;
unsigned int chipid;
int ret;
if (!pci_is_pcie(pdev)) {
pr_err("device %s is not PCI Express\n", pci_name(pdev));
return -EIO;
}
qtnf_tune_pcie_mps(pdev);
ret = pcim_enable_device(pdev);
if (ret) {
pr_err("failed to init PCI device %x\n", pdev->device);
return ret;
}
pci_set_master(pdev);
sysctl_bar = qtnf_map_bar(pdev, QTN_SYSCTL_BAR);
if (IS_ERR(sysctl_bar)) {
pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR);
return PTR_ERR(sysctl_bar);
}
dmareg_bar = qtnf_map_bar(pdev, QTN_DMA_BAR);
if (IS_ERR(dmareg_bar)) {
pr_err("failed to map BAR%u\n", QTN_DMA_BAR);
return PTR_ERR(dmareg_bar);
}
epmem_bar = qtnf_map_bar(pdev, QTN_SHMEM_BAR);
if (IS_ERR(epmem_bar)) {
pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR);
return PTR_ERR(epmem_bar);
}
chipid = qtnf_chip_id_get(sysctl_bar);
pr_info("identified device: %s\n", qtnf_chipid_to_string(chipid));
switch (chipid) {
case QTN_CHIP_ID_PEARL:
case QTN_CHIP_ID_PEARL_B:
case QTN_CHIP_ID_PEARL_C:
bus = qtnf_pcie_pearl_alloc(pdev);
break;
case QTN_CHIP_ID_TOPAZ:
bus = qtnf_pcie_topaz_alloc(pdev);
break;
default:
pr_err("unsupported chip ID 0x%x\n", chipid);
return -ENOTSUPP;
}
if (!bus)
return -ENOMEM;
pcie_priv = get_bus_priv(bus);
pci_set_drvdata(pdev, bus);
bus->dev = &pdev->dev;
bus->fw_state = QTNF_FW_STATE_DETACHED;
pcie_priv->pdev = pdev;
pcie_priv->tx_stopped = 0;
pcie_priv->flashboot = flashboot;
if (fw_blksize_param > QTN_PCIE_MAX_FW_BUFSZ)
pcie_priv->fw_blksize = QTN_PCIE_MAX_FW_BUFSZ;
else
pcie_priv->fw_blksize = fw_blksize_param;
mutex_init(&bus->bus_lock);
spin_lock_init(&pcie_priv->tx_lock);
spin_lock_init(&pcie_priv->tx_reclaim_lock);
pcie_priv->tx_full_count = 0;
pcie_priv->tx_done_count = 0;
pcie_priv->pcie_irq_count = 0;
pcie_priv->tx_reclaim_done = 0;
pcie_priv->tx_reclaim_req = 0;
pcie_priv->workqueue = create_singlethread_workqueue("QTNF_PCIE");
if (!pcie_priv->workqueue) {
pr_err("failed to alloc bus workqueue\n");
return -ENODEV;
}
ret = dma_set_mask_and_coherent(&pdev->dev,
pcie_priv->dma_mask_get_cb());
if (ret) {
pr_err("PCIE DMA coherent mask init failed 0x%llx\n",
pcie_priv->dma_mask_get_cb());
goto error;
}
bus->mux_dev = alloc_netdev_dummy(0);
if (!bus->mux_dev) {
ret = -ENOMEM;
goto error;
}
qtnf_pcie_init_irq(pcie_priv, use_msi);
pcie_priv->sysctl_bar = sysctl_bar;
pcie_priv->dmareg_bar = dmareg_bar;
pcie_priv->epmem_bar = epmem_bar;
pci_save_state(pdev);
ret = pcie_priv->probe_cb(bus, tx_bd_size_param, rx_bd_size_param);
if (ret)
goto error_free;
qtnf_pcie_bringup_fw_async(bus);
return 0;
error_free:
free_netdev(bus->mux_dev);
error:
destroy_workqueue(pcie_priv->workqueue);
pci_set_drvdata(pdev, NULL);
return ret;
}
static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv)
{
qtnf_shm_ipc_free(&priv->shm_ipc_ep_in);
qtnf_shm_ipc_free(&priv->shm_ipc_ep_out);
}
static void qtnf_pcie_remove(struct pci_dev *dev)
{
struct qtnf_pcie_bus_priv *priv;
struct qtnf_bus *bus;
bus = pci_get_drvdata(dev);
if (!bus)
return;
priv = get_bus_priv(bus);
cancel_work_sync(&bus->fw_work);
if (qtnf_fw_is_attached(bus))
qtnf_core_detach(bus);
netif_napi_del(&bus->mux_napi);
destroy_workqueue(priv->workqueue);
tasklet_kill(&priv->reclaim_tq);
free_netdev(bus->mux_dev);
qtnf_pcie_free_shm_ipc(priv);
qtnf_debugfs_remove(bus);
priv->remove_cb(bus);
pci_set_drvdata(priv->pdev, NULL);
}
#ifdef CONFIG_PM_SLEEP
static int qtnf_pcie_suspend(struct device *dev)
{
struct qtnf_pcie_bus_priv *priv;
struct qtnf_bus *bus;
bus = dev_get_drvdata(dev);
if (!bus)
return -EFAULT;
priv = get_bus_priv(bus);
return priv->suspend_cb(bus);
}
static int qtnf_pcie_resume(struct device *dev)
{
struct qtnf_pcie_bus_priv *priv;
struct qtnf_bus *bus;
bus = dev_get_drvdata(dev);
if (!bus)
return -EFAULT;
priv = get_bus_priv(bus);
return priv->resume_cb(bus);
}
/* Power Management Hooks */
static SIMPLE_DEV_PM_OPS(qtnf_pcie_pm_ops, qtnf_pcie_suspend,
qtnf_pcie_resume);
#endif
static const struct pci_device_id qtnf_pcie_devid_table[] = {
{
PCIE_VENDOR_ID_QUANTENNA, PCIE_DEVICE_ID_QSR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
},
{ },
};
MODULE_DEVICE_TABLE(pci, qtnf_pcie_devid_table);
static struct pci_driver qtnf_pcie_drv_data = {
.name = DRV_NAME,
.id_table = qtnf_pcie_devid_table,
.probe = qtnf_pcie_probe,
.remove = qtnf_pcie_remove,
#ifdef CONFIG_PM_SLEEP
.driver = {
.pm = &qtnf_pcie_pm_ops,
},
#endif
};
module_pci_driver(qtnf_pcie_drv_data)
MODULE_AUTHOR("Quantenna Communications");
MODULE_DESCRIPTION("Quantenna PCIe bus driver for 802.11 wireless LAN.");
MODULE_LICENSE("GPL");
linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
+90
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/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */
#ifndef _QTN_FMAC_PCIE_H_
#define _QTN_FMAC_PCIE_H_
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/skbuff.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include "shm_ipc.h"
#include "bus.h"
#define SKB_BUF_SIZE 2048
#define QTN_FW_DL_TIMEOUT_MS 3000
#define QTN_FW_QLINK_TIMEOUT_MS 30000
#define QTN_EP_RESET_WAIT_MS 1000
struct qtnf_pcie_bus_priv {
struct pci_dev *pdev;
int (*probe_cb)(struct qtnf_bus *bus, unsigned int tx_bd_size,
unsigned int rx_bd_size);
void (*remove_cb)(struct qtnf_bus *bus);
int (*suspend_cb)(struct qtnf_bus *bus);
int (*resume_cb)(struct qtnf_bus *bus);
u64 (*dma_mask_get_cb)(void);
spinlock_t tx_reclaim_lock;
spinlock_t tx_lock;
struct workqueue_struct *workqueue;
struct tasklet_struct reclaim_tq;
void __iomem *sysctl_bar;
void __iomem *epmem_bar;
void __iomem *dmareg_bar;
struct qtnf_shm_ipc shm_ipc_ep_in;
struct qtnf_shm_ipc shm_ipc_ep_out;
u16 tx_bd_num;
u16 rx_bd_num;
struct sk_buff **tx_skb;
struct sk_buff **rx_skb;
unsigned int fw_blksize;
u32 rx_bd_w_index;
u32 rx_bd_r_index;
u32 tx_bd_w_index;
u32 tx_bd_r_index;
/* diagnostics stats */
u32 pcie_irq_count;
u32 tx_full_count;
u32 tx_done_count;
u32 tx_reclaim_done;
u32 tx_reclaim_req;
u8 msi_enabled;
u8 tx_stopped;
bool flashboot;
};
int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb);
int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv);
int qtnf_pcie_fw_boot_done(struct qtnf_bus *bus);
void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
const struct qtnf_shm_ipc_int *ipc_int);
struct qtnf_bus *qtnf_pcie_pearl_alloc(struct pci_dev *pdev);
struct qtnf_bus *qtnf_pcie_topaz_alloc(struct pci_dev *pdev);
static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
{
writel(val, basereg);
/* flush posted write */
readl(basereg);
}
#endif /* _QTN_FMAC_PCIE_H_ */
linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+1199
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
+82
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@@ -0,0 +1,82 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2015-2016 Quantenna Communications */
#ifndef _QTN_FMAC_PCIE_IPC_H_
#define _QTN_FMAC_PCIE_IPC_H_
#include <linux/types.h>
#include "shm_ipc_defs.h"
/* bitmap for EP status and flags: updated by EP, read by RC */
#define QTN_EP_HAS_UBOOT BIT(0)
#define QTN_EP_HAS_FIRMWARE BIT(1)
#define QTN_EP_REQ_UBOOT BIT(2)
#define QTN_EP_REQ_FIRMWARE BIT(3)
#define QTN_EP_ERROR_UBOOT BIT(4)
#define QTN_EP_ERROR_FIRMWARE BIT(5)
#define QTN_EP_FW_LOADRDY BIT(8)
#define QTN_EP_FW_SYNC BIT(9)
#define QTN_EP_FW_RETRY BIT(10)
#define QTN_EP_FW_QLINK_DONE BIT(15)
#define QTN_EP_FW_DONE BIT(16)
/* bitmap for RC status and flags: updated by RC, read by EP */
#define QTN_RC_PCIE_LINK BIT(0)
#define QTN_RC_NET_LINK BIT(1)
#define QTN_RC_FW_FLASHBOOT BIT(5)
#define QTN_RC_FW_QLINK BIT(7)
#define QTN_RC_FW_LOADRDY BIT(8)
#define QTN_RC_FW_SYNC BIT(9)
#define PCIE_HDP_INT_RX_BITS (0 \
| PCIE_HDP_INT_EP_TXDMA \
| PCIE_HDP_INT_EP_TXEMPTY \
| PCIE_HDP_INT_HHBM_UF \
)
#define PCIE_HDP_INT_TX_BITS (0 \
| PCIE_HDP_INT_EP_RXDMA \
)
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
#define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32))
#define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL))
#define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l))
#else
#define QTN_HOST_HI32(a) 0
#define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL))
#define QTN_HOST_ADDR(h, l) ((u32)l)
#endif
#define QTN_PCIE_BDA_VERSION 0x1002
#define PCIE_BDA_NAMELEN 32
#define PCIE_HHBM_MAX_SIZE 2048
#define QTN_PCIE_BOARDFLG "PCIEQTN"
#define QTN_PCIE_FW_DLMASK 0xF
#define QTN_PCIE_FW_BUFSZ 2048
#define QTN_ENET_ADDR_LENGTH 6
#define QTN_TXDONE_MASK ((u32)0x80000000)
#define QTN_GET_LEN(x) ((x) & 0xFFFF)
#define QTN_PCIE_TX_DESC_LEN_MASK 0xFFFF
#define QTN_PCIE_TX_DESC_LEN_SHIFT 0
#define QTN_PCIE_TX_DESC_PORT_MASK 0xF
#define QTN_PCIE_TX_DESC_PORT_SHIFT 16
#define QTN_PCIE_TX_DESC_TQE_BIT BIT(24)
#define QTN_EP_LHOST_TQE_PORT 4
enum qtnf_fw_loadtype {
QTN_FW_DBEGIN,
QTN_FW_DSUB,
QTN_FW_DEND,
QTN_FW_CTRL
};
#endif /* _QTN_FMAC_PCIE_IPC_H_ */
linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h
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@@ -0,0 +1,121 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2015 Quantenna Communications */
#ifndef __PEARL_PCIE_H
#define __PEARL_PCIE_H
/* Pearl PCIe HDP registers */
#define PCIE_HDP_CTRL(base) ((base) + 0x2c00)
#define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04)
#define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10)
#define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14)
#define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18)
#define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c)
#define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20)
#define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24)
#define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28)
#define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c)
#define PCIE_HDP_RX_INT_CTRL(base) ((base) + 0x2c30)
#define PCIE_HDP_TX_INT_CTRL(base) ((base) + 0x2c34)
#define PCIE_HDP_INT_STATUS(base) ((base) + 0x2c38)
#define PCIE_HDP_INT_EN(base) ((base) + 0x2c3c)
#define PCIE_HDP_RX_DESC0_PTR(base) ((base) + 0x2c40)
#define PCIE_HDP_RX_DESC0_NOE(base) ((base) + 0x2c44)
#define PCIE_HDP_RX_DESC1_PTR(base) ((base) + 0x2c48)
#define PCIE_HDP_RX_DESC1_NOE(base) ((base) + 0x2c4c)
#define PCIE_HDP_RX_DESC2_PTR(base) ((base) + 0x2c50)
#define PCIE_HDP_RX_DESC2_NOE(base) ((base) + 0x2c54)
#define PCIE_HDP_RX_DESC3_PTR(base) ((base) + 0x2c58)
#define PCIE_HDP_RX_DESC3_NOE(base) ((base) + 0x2c5c)
#define PCIE_HDP_TX0_BASE_ADDR(base) ((base) + 0x2c60)
#define PCIE_HDP_TX1_BASE_ADDR(base) ((base) + 0x2c64)
#define PCIE_HDP_TX0_Q_CTRL(base) ((base) + 0x2c70)
#define PCIE_HDP_TX1_Q_CTRL(base) ((base) + 0x2c74)
#define PCIE_HDP_CFG0(base) ((base) + 0x2c80)
#define PCIE_HDP_CFG1(base) ((base) + 0x2c84)
#define PCIE_HDP_CFG2(base) ((base) + 0x2c88)
#define PCIE_HDP_CFG3(base) ((base) + 0x2c8c)
#define PCIE_HDP_CFG4(base) ((base) + 0x2c90)
#define PCIE_HDP_CFG5(base) ((base) + 0x2c94)
#define PCIE_HDP_CFG6(base) ((base) + 0x2c98)
#define PCIE_HDP_CFG7(base) ((base) + 0x2c9c)
#define PCIE_HDP_CFG8(base) ((base) + 0x2ca0)
#define PCIE_HDP_CFG9(base) ((base) + 0x2ca4)
#define PCIE_HDP_CFG10(base) ((base) + 0x2ca8)
#define PCIE_HDP_CFG11(base) ((base) + 0x2cac)
#define PCIE_INT(base) ((base) + 0x2cb0)
#define PCIE_INT_MASK(base) ((base) + 0x2cb4)
#define PCIE_MSI_MASK(base) ((base) + 0x2cb8)
#define PCIE_MSI_PNDG(base) ((base) + 0x2cbc)
#define PCIE_PRI_CFG(base) ((base) + 0x2cc0)
#define PCIE_PHY_CR(base) ((base) + 0x2cc4)
#define PCIE_HDP_CTAG_CTRL(base) ((base) + 0x2cf4)
#define PCIE_HDP_HHBM_BUF_PTR(base) ((base) + 0x2d00)
#define PCIE_HDP_HHBM_BUF_PTR_H(base) ((base) + 0x2d04)
#define PCIE_HDP_HHBM_BUF_FIFO_NOE(base) ((base) + 0x2d04)
#define PCIE_HDP_RX0DMA_CNT(base) ((base) + 0x2d10)
#define PCIE_HDP_RX1DMA_CNT(base) ((base) + 0x2d14)
#define PCIE_HDP_RX2DMA_CNT(base) ((base) + 0x2d18)
#define PCIE_HDP_RX3DMA_CNT(base) ((base) + 0x2d1c)
#define PCIE_HDP_TX0DMA_CNT(base) ((base) + 0x2d20)
#define PCIE_HDP_TX1DMA_CNT(base) ((base) + 0x2d24)
#define PCIE_HDP_RXDMA_CTRL(base) ((base) + 0x2d28)
#define PCIE_HDP_TX_HOST_Q_SZ_CTRL(base) ((base) + 0x2d2c)
#define PCIE_HDP_TX_HOST_Q_BASE_L(base) ((base) + 0x2d30)
#define PCIE_HDP_TX_HOST_Q_BASE_H(base) ((base) + 0x2d34)
#define PCIE_HDP_TX_HOST_Q_WR_PTR(base) ((base) + 0x2d38)
#define PCIE_HDP_TX_HOST_Q_RD_PTR(base) ((base) + 0x2d3c)
#define PCIE_HDP_TX_HOST_Q_STS(base) ((base) + 0x2d40)
/* Pearl PCIe HBM pool registers */
#define PCIE_HHBM_CSR_REG(base) ((base) + 0x2e00)
#define PCIE_HHBM_Q_BASE_REG(base) ((base) + 0x2e04)
#define PCIE_HHBM_Q_LIMIT_REG(base) ((base) + 0x2e08)
#define PCIE_HHBM_Q_WR_REG(base) ((base) + 0x2e0c)
#define PCIE_HHBM_Q_RD_REG(base) ((base) + 0x2e10)
#define PCIE_HHBM_POOL_DATA_0_H(base) ((base) + 0x2e90)
#define PCIE_HHBM_CONFIG(base) ((base) + 0x2f9c)
#define PCIE_HHBM_POOL_REQ_0(base) ((base) + 0x2f10)
#define PCIE_HHBM_POOL_DATA_0(base) ((base) + 0x2f40)
#define PCIE_HHBM_WATERMARK_MASKED_INT(base) ((base) + 0x2f68)
#define PCIE_HHBM_WATERMARK_INT(base) ((base) + 0x2f6c)
#define PCIE_HHBM_POOL_WATERMARK(base) ((base) + 0x2f70)
#define PCIE_HHBM_POOL_OVERFLOW_CNT(base) ((base) + 0x2f90)
#define PCIE_HHBM_POOL_UNDERFLOW_CNT(base) ((base) + 0x2f94)
#define HBM_INT_STATUS(base) ((base) + 0x2f9c)
#define PCIE_HHBM_POOL_CNFIG(base) ((base) + 0x2f9c)
/* Pearl PCIe HBM bit field definitions */
#define HHBM_CONFIG_SOFT_RESET (BIT(8))
#define HHBM_WR_REQ (BIT(0))
#define HHBM_RD_REQ (BIT(1))
#define HHBM_DONE (BIT(31))
#define HHBM_64BIT (BIT(10))
/* PCIe HDP interrupt status definition */
#define PCIE_HDP_INT_EP_RXDMA (BIT(0))
#define PCIE_HDP_INT_HBM_UF (BIT(1))
#define PCIE_HDP_INT_RX_LEN_ERR (BIT(2))
#define PCIE_HDP_INT_RX_HDR_LEN_ERR (BIT(3))
#define PCIE_HDP_INT_EP_TXDMA (BIT(12))
#define PCIE_HDP_INT_HHBM_UF (BIT(13))
#define PCIE_HDP_INT_EP_TXEMPTY (BIT(15))
#define PCIE_HDP_INT_IPC (BIT(29))
/* PCIe interrupt status definition */
#define PCIE_INT_MSI (BIT(24))
#define PCIE_INT_INTX (BIT(23))
/* PCIe legacy INTx */
#define PEARL_PCIE_CFG0_OFFSET (0x6C)
#define PEARL_ASSERT_INTX (BIT(9))
/* SYS CTL regs */
#define QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET (0x001C)
#define QTN_PEARL_IPC_IRQ_WORD(irq) (BIT(irq) | BIT(irq + 16))
#define QTN_PEARL_LHOST_IPC_IRQ (6)
#define QTN_PEARL_LHOST_EP_RESET (7)
#endif /* __PEARL_PCIE_H */
linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
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linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2018 Quantenna Communications */
#ifndef _QTN_FMAC_PCIE_IPC_H_
#define _QTN_FMAC_PCIE_IPC_H_
#include <linux/types.h>
#include "shm_ipc_defs.h"
/* EP/RC status and flags */
#define QTN_BDA_PCIE_INIT 0x01
#define QTN_BDA_PCIE_RDY 0x02
#define QTN_BDA_FW_LOAD_RDY 0x03
#define QTN_BDA_FW_LOAD_DONE 0x04
#define QTN_BDA_FW_START 0x05
#define QTN_BDA_FW_RUN 0x06
#define QTN_BDA_FW_HOST_RDY 0x07
#define QTN_BDA_FW_TARGET_RDY 0x11
#define QTN_BDA_FW_TARGET_BOOT 0x12
#define QTN_BDA_FW_FLASH_BOOT 0x13
#define QTN_BDA_FW_QLINK_DONE 0x14
#define QTN_BDA_FW_HOST_LOAD 0x08
#define QTN_BDA_FW_BLOCK_DONE 0x09
#define QTN_BDA_FW_BLOCK_RDY 0x0A
#define QTN_BDA_FW_EP_RDY 0x0B
#define QTN_BDA_FW_BLOCK_END 0x0C
#define QTN_BDA_FW_CONFIG 0x0D
#define QTN_BDA_FW_RUNNING 0x0E
#define QTN_BDA_PCIE_FAIL 0x82
#define QTN_BDA_FW_LOAD_FAIL 0x85
#define QTN_BDA_RCMODE BIT(1)
#define QTN_BDA_MSI BIT(2)
#define QTN_BDA_HOST_CALCMD BIT(3)
#define QTN_BDA_FLASH_PRESENT BIT(4)
#define QTN_BDA_FLASH_BOOT BIT(5)
#define QTN_BDA_XMIT_UBOOT BIT(6)
#define QTN_BDA_HOST_QLINK_DRV BIT(7)
#define QTN_BDA_TARGET_FBOOT_ERR BIT(8)
#define QTN_BDA_TARGET_FWLOAD_ERR BIT(9)
#define QTN_BDA_HOST_NOFW_ERR BIT(12)
#define QTN_BDA_HOST_MEMALLOC_ERR BIT(13)
#define QTN_BDA_HOST_MEMMAP_ERR BIT(14)
#define QTN_BDA_VER(x) (((x) >> 4) & 0xFF)
#define QTN_BDA_ERROR_MASK 0xFF00
/* registers and shmem address macros */
#if BITS_PER_LONG == 64
#define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32))
#define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL))
#define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l))
#elif BITS_PER_LONG == 32
#define QTN_HOST_HI32(a) 0
#define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL))
#define QTN_HOST_ADDR(h, l) ((u32)l)
#else
#error Unexpected BITS_PER_LONG value
#endif
#define QTN_PCIE_BDA_VERSION 0x1001
#define PCIE_BDA_NAMELEN 32
#define QTN_PCIE_RC_TX_QUEUE_LEN 256
#define QTN_PCIE_TX_VALID_PKT 0x80000000
#define QTN_PCIE_PKT_LEN_MASK 0xffff
#define QTN_BD_EMPTY ((uint32_t)0x00000001)
#define QTN_BD_WRAP ((uint32_t)0x00000002)
#define QTN_BD_MASK_LEN ((uint32_t)0xFFFF0000)
#define QTN_BD_MASK_OFFSET ((uint32_t)0x0000FF00)
#define QTN_GET_LEN(x) (((x) >> 16) & 0xFFFF)
#define QTN_GET_OFFSET(x) (((x) >> 8) & 0xFF)
#define QTN_SET_LEN(len) (((len) & 0xFFFF) << 16)
#define QTN_SET_OFFSET(of) (((of) & 0xFF) << 8)
#define RX_DONE_INTR_MSK ((0x1 << 6) - 1)
#define PCIE_DMA_OFFSET_ERROR 0xFFFF
#define PCIE_DMA_OFFSET_ERROR_MASK 0xFFFF
#define QTN_PCI_ENDIAN_DETECT_DATA 0x12345678
#define QTN_PCI_ENDIAN_REVERSE_DATA 0x78563412
#define QTN_PCI_ENDIAN_VALID_STATUS 0x3c3c3c3c
#define QTN_PCI_ENDIAN_INVALID_STATUS 0
#define QTN_PCI_LITTLE_ENDIAN 0
#define QTN_PCI_BIG_ENDIAN 0xffffffff
#define NBLOCKS(size, blksize) \
((size) / (blksize) + (((size) % (blksize) > 0) ? 1 : 0))
#endif /* _QTN_FMAC_PCIE_IPC_H_ */
linux-7.2.3/drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2018 Quantenna Communications */
#ifndef __TOPAZ_PCIE_H
#define __TOPAZ_PCIE_H
/* Topaz PCIe DMA registers */
#define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
#define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
#define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
#define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
#define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
#define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
#define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
#define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
#define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
#define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
#define PCIE_DMA_RD_ERR_STATUS_HIGH(base) ((base) + 0x328)
#define PCIE_DMA_RD_DONE_IMWR_ADDR_LOW(base) ((base) + 0x33c)
#define PCIE_DMA_RD_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x340)
/* Topaz LHost IPC4 interrupt */
#define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C)
#define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140)
#define TOPAZ_RC_TX_DONE_IRQ (0)
#define TOPAZ_RC_RST_EP_IRQ (1)
#define TOPAZ_RC_TX_STOP_IRQ (2)
#define TOPAZ_RC_RX_DONE_IRQ (3)
#define TOPAZ_RC_PM_EP_IRQ (4)
/* Topaz LHost M2L interrupt */
#define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C)
#define TOPAZ_CTL_M2L_INT_MASK(base) ((base) + 0x30)
#define TOPAZ_RC_CTRL_IRQ (6)
#define TOPAZ_IPC_IRQ_WORD(irq) (BIT(irq) | BIT(irq + 16))
/* PCIe legacy INTx */
#define TOPAZ_PCIE_CFG0_OFFSET (0x6C)
#define TOPAZ_ASSERT_INTX BIT(9)
#endif /* __TOPAZ_PCIE_H */