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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/pinctrl/samsung/Kconfig
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# SPDX-License-Identifier: GPL-2.0
#
# Samsung Pin control drivers
#
config PINCTRL_SAMSUNG
bool
select GPIOLIB
select PINMUX
select PINCONF
config PINCTRL_EXYNOS
bool "Pinctrl common driver part for Samsung Exynos SoCs"
depends on ARCH_EXYNOS || ARCH_S5PV210 || (COMPILE_TEST && OF)
select PINCTRL_SAMSUNG
select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
config PINCTRL_EXYNOS_ARM
bool "ARMv7-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
depends on PINCTRL_EXYNOS
config PINCTRL_EXYNOS_ARM64
bool "ARMv8-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
depends on PINCTRL_EXYNOS
config PINCTRL_S3C64XX
bool "Samsung S3C64XX SoC pinctrl driver"
depends on ARCH_S3C64XX || (COMPILE_TEST && OF)
select PINCTRL_SAMSUNG
linux-7.2.3/drivers/pinctrl/samsung/Makefile
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# SPDX-License-Identifier: GPL-2.0
# Samsung pin control drivers
obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o
obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o
obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
linux-7.2.3/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
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// SPDX-License-Identifier: GPL-2.0+
//
// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
//
// Copyright (c) 2012 Samsung Electronics Co., Ltd.
// http://www.samsung.com
// Copyright (c) 2012 Linaro Ltd
// http://www.linaro.org
//
// Author: Thomas Abraham <thomas.ab@samsung.com>
//
// This file contains the Samsung Exynos specific information required by the
// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
// external gpio and wakeup interrupt support.
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include "pinctrl-samsung.h"
#include "pinctrl-exynos.h"
static const struct samsung_pin_bank_type bank_type_off = {
.fld_width = { 4, 1, 2, 2, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
};
static const struct samsung_pin_bank_type bank_type_alive = {
.fld_width = { 4, 1, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
/* Retention control for S5PV210 are located at the end of clock controller */
#define S5P_OTHERS 0xE000
#define S5P_OTHERS_RET_IO (1 << 31)
#define S5P_OTHERS_RET_CF (1 << 30)
#define S5P_OTHERS_RET_MMC (1 << 29)
#define S5P_OTHERS_RET_UART (1 << 28)
#define S5P_PIN_PULL_DISABLE 0
#define S5P_PIN_PULL_DOWN 1
#define S5P_PIN_PULL_UP 2
static void s5pv210_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
{
unsigned int *pud_val = drvdata->pud_val;
pud_val[PUD_PULL_DISABLE] = S5P_PIN_PULL_DISABLE;
pud_val[PUD_PULL_DOWN] = S5P_PIN_PULL_DOWN;
pud_val[PUD_PULL_UP] = S5P_PIN_PULL_UP;
}
static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
{
void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
u32 tmp;
tmp = __raw_readl(clk_base + S5P_OTHERS);
tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
S5P_OTHERS_RET_UART);
__raw_writel(tmp, clk_base + S5P_OTHERS);
}
static struct samsung_retention_ctrl *
s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
const struct samsung_retention_data *data)
{
struct samsung_retention_ctrl *ctrl;
struct device_node *np;
void __iomem *clk_base;
ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return ERR_PTR(-ENOMEM);
np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
if (!np) {
pr_err("%s: failed to find clock controller DT node\n",
__func__);
return ERR_PTR(-ENODEV);
}
clk_base = of_iomap(np, 0);
of_node_put(np);
if (!clk_base) {
pr_err("%s: failed to map clock registers\n", __func__);
return ERR_PTR(-EINVAL);
}
ctrl->priv = (void __force *)clk_base;
ctrl->disable = s5pv210_retention_disable;
return ctrl;
}
static const struct samsung_retention_data s5pv210_retention_data __initconst = {
.init = s5pv210_retention_init,
};
/* pin banks of s5pv210 pin-controller */
static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
};
static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = s5pv210_pin_bank,
.nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.pud_value_init = s5pv210_pud_value_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &s5pv210_retention_data,
},
};
const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
.ctrl = s5pv210_pin_ctrl,
.num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl),
};
/* Pad retention control code for accessing PMU regmap */
static atomic_t exynos_shared_retention_refcnt;
/* pin banks of exynos3250 pin-controller 0 */
static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
};
/* pin banks of exynos3250 pin-controller 1 */
static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
};
/*
* PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
* them all together
*/
static const u32 exynos3250_retention_regs[] = {
S5P_PAD_RET_MAUDIO_OPTION,
S5P_PAD_RET_GPIO_OPTION,
S5P_PAD_RET_UART_OPTION,
S5P_PAD_RET_MMCA_OPTION,
S5P_PAD_RET_MMCB_OPTION,
S5P_PAD_RET_EBIA_OPTION,
S5P_PAD_RET_EBIB_OPTION,
S5P_PAD_RET_MMC2_OPTION,
S5P_PAD_RET_SPI_OPTION,
};
static const struct samsung_retention_data exynos3250_retention_data __initconst = {
.regs = exynos3250_retention_regs,
.nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
.value = EXYNOS_WAKEUP_FROM_LOWPWR,
.refcnt = &exynos_shared_retention_refcnt,
.init = exynos_retention_init,
};
/*
* Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
* two gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos3250_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos3250_retention_data,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos3250_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos3250_retention_data,
},
};
const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
.ctrl = exynos3250_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl),
};
/* pin banks of exynos4210 pin-controller 0 */
static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
};
/* pin banks of exynos4210 pin-controller 1 */
static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos4210 pin-controller 2 */
static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
};
/* PMU pad retention groups registers for Exynos4 (without audio) */
static const u32 exynos4_retention_regs[] = {
S5P_PAD_RET_GPIO_OPTION,
S5P_PAD_RET_UART_OPTION,
S5P_PAD_RET_MMCA_OPTION,
S5P_PAD_RET_MMCB_OPTION,
S5P_PAD_RET_EBIA_OPTION,
S5P_PAD_RET_EBIB_OPTION,
};
static const struct samsung_retention_data exynos4_retention_data __initconst = {
.regs = exynos4_retention_regs,
.nr_regs = ARRAY_SIZE(exynos4_retention_regs),
.value = EXYNOS_WAKEUP_FROM_LOWPWR,
.refcnt = &exynos_shared_retention_refcnt,
.init = exynos_retention_init,
};
/* PMU retention control for audio pins can be tied to audio pin bank */
static const u32 exynos4_audio_retention_regs[] = {
S5P_PAD_RET_MAUDIO_OPTION,
};
static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
.regs = exynos4_audio_retention_regs,
.nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
.value = EXYNOS_WAKEUP_FROM_LOWPWR,
.init = exynos_retention_init,
};
/*
* Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
* three gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos4210_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_retention_data,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos4210_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_retention_data,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos4210_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
.retention_data = &exynos4_audio_retention_data,
},
};
const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
.ctrl = exynos4210_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl),
};
/* pin banks of exynos4x12 pin-controller 0 */
static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
};
/* pin banks of exynos4x12 pin-controller 1 */
static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos4x12 pin-controller 2 */
static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
};
/* pin banks of exynos4x12 pin-controller 3 */
static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
};
/*
* Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
* four gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos4x12_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_retention_data,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos4x12_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_retention_data,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos4x12_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_audio_retention_data,
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos4x12_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
},
};
const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
.ctrl = exynos4x12_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl),
};
/* pin banks of exynos5250 pin-controller 0 */
static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos5250 pin-controller 1 */
static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
};
/* pin banks of exynos5250 pin-controller 2 */
static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
};
/* pin banks of exynos5250 pin-controller 3 */
static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
};
/*
* Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
* four gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5250_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_retention_data,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5250_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_retention_data,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5250_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos5250_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_audio_retention_data,
},
};
const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
.ctrl = exynos5250_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl),
};
/* pin banks of exynos5260 pin-controller 0 */
static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
};
/* pin banks of exynos5260 pin-controller 1 */
static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
};
/* pin banks of exynos5260 pin-controller 2 */
static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
};
/*
* Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
* three gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5260_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5260_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5260_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
},
};
const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
.ctrl = exynos5260_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl),
};
/* pin banks of exynos5410 pin-controller 0 */
static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos5410 pin-controller 1 */
static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
};
/* pin banks of exynos5410 pin-controller 2 */
static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
};
/* pin banks of exynos5410 pin-controller 3 */
static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
};
/*
* Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
* four gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5410_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5410_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5410_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos5410_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
},
};
const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
.ctrl = exynos5410_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl),
};
/* pin banks of exynos5420 pin-controller 0 */
static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos5420 pin-controller 1 */
static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
};
/* pin banks of exynos5420 pin-controller 2 */
static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
};
/* pin banks of exynos5420 pin-controller 3 */
static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
};
/* pin banks of exynos5420 pin-controller 4 */
static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
};
/* PMU pad retention groups registers for Exynos5420 (without audio) */
static const u32 exynos5420_retention_regs[] = {
EXYNOS_PAD_RET_DRAM_OPTION,
EXYNOS_PAD_RET_JTAG_OPTION,
EXYNOS5420_PAD_RET_GPIO_OPTION,
EXYNOS5420_PAD_RET_UART_OPTION,
EXYNOS5420_PAD_RET_MMCA_OPTION,
EXYNOS5420_PAD_RET_MMCB_OPTION,
EXYNOS5420_PAD_RET_MMCC_OPTION,
EXYNOS5420_PAD_RET_HSI_OPTION,
EXYNOS_PAD_RET_EBIA_OPTION,
EXYNOS_PAD_RET_EBIB_OPTION,
EXYNOS5420_PAD_RET_SPI_OPTION,
EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
};
static const struct samsung_retention_data exynos5420_retention_data __initconst = {
.regs = exynos5420_retention_regs,
.nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
.value = EXYNOS_WAKEUP_FROM_LOWPWR,
.refcnt = &exynos_shared_retention_refcnt,
.init = exynos_retention_init,
};
/*
* Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
* four gpio/pin-mux/pinconfig controllers.
*/
static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5420_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5420_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5420_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos5420_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 4 data */
.pin_banks = exynos5420_pin_banks4,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_audio_retention_data,
},
};
const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
.ctrl = exynos5420_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl),
};
linux-7.2.3/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
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linux-7.2.3/drivers/pinctrl/samsung/pinctrl-exynos.c
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linux-7.2.3/drivers/pinctrl/samsung/pinctrl-exynos.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Exynos specific definitions for Samsung pinctrl and gpiolib driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* http://www.linaro.org
*
* This file contains the Exynos specific definitions for the Samsung
* pinctrl/gpiolib interface drivers.
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
*/
#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
#define __PINCTRL_SAMSUNG_EXYNOS_H
/* Values for the pin CON register */
#define EXYNOS_PIN_CON_FUNC_EINT 0xf
/* External GPIO and wakeup interrupt related definitions */
#define EXYNOS_GPIO_ECON_OFFSET 0x700
#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
#define EXYNOS_GPIO_EMASK_OFFSET 0x900
#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
#define EXYNOS_WKUP_ECON_OFFSET 0xE00
#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
#define EXYNOS7_WKUP_ECON_OFFSET 0x700
#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
#define EXYNOS_SVC_OFFSET 0xB08
#define EXYNOSAUTO_SVC_OFFSET 0xF008
/* helpers to access interrupt service register */
#define EXYNOS_SVC_GROUP_SHIFT 3
#define EXYNOS_SVC_GROUP_MASK 0x1f
#define EXYNOS_SVC_NUM_MASK 7
#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
EXYNOS_SVC_GROUP_MASK)
/* Exynos specific external interrupt trigger types */
#define EXYNOS_EINT_LEVEL_LOW 0
#define EXYNOS_EINT_LEVEL_HIGH 1
#define EXYNOS_EINT_EDGE_FALLING 2
#define EXYNOS_EINT_EDGE_RISING 3
#define EXYNOS_EINT_EDGE_BOTH 4
#define EXYNOS_EINT_CON_MASK 0xF
#define EXYNOS_EINT_CON_LEN 4
#define EXYNOS_EINT_MAX_PER_BANK 8
#define EXYNOS_EINT_NR_WKUP_EINT
/*
* EINT filter configuration register (on alive banks) has
* the following layout.
*
* BitfieldName[PinNum][Bit:Bit]
* FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
* FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
* FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
* FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0]
*
* FLT_EN 0x0 = Disable, 0x1=Enable
* FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count)
* FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1
*/
#define EXYNOS_FLTCON_EN BIT(7)
#define EXYNOS_FLTCON_DIGITAL BIT(6)
#define EXYNOS_FLTCON_ANALOG (0 << 6)
#define EXYNOS_FLTCON_LEN 8
#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
{ \
.type = &bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
{ \
.type = &bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &exynos5433_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
{ \
.type = &exynos5433_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
{ \
.type = &exynos5433_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id, \
.pctl_res_idx = pctl_idx, \
} \
#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \
{ \
.type = &exynos7870_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \
{ \
.type = &exynos7870_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
{ \
.type = &exynos850_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &exynos850_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \
{ \
.type = &exynos850_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &exynos8895_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
{ \
.type = &exynos850_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_con_offset = con_offs, \
.eint_mask_offset = mask_offs, \
.eint_pend_offset = pend_offs, \
.name = id \
}
#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \
{ \
.type = &exynos850_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_con_offset = con_offs, \
.eint_mask_offset = mask_offs, \
.eint_pend_offset = pend_offs, \
.name = id \
}
#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
{ \
.type = &exynos850_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.eint_fltcon_offset = fltcon_offs, \
.name = id \
}
#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
{ \
.type = &exynos850_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.eint_fltcon_offset = fltcon_offs, \
.name = id \
}
#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &artpec_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.
* @irq: interrupt number within the domain.
* @bank: bank responsible for this interrupt
*/
struct exynos_weint_data {
unsigned int irq;
struct samsung_pin_bank *bank;
};
/**
* struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
* generated by the external wakeup interrupt controller.
* @nr_banks: count of banks being part of the mux
* @banks: array of banks being part of the mux
*/
struct exynos_muxed_weint_data {
unsigned int nr_banks;
struct samsung_pin_bank *banks[] __counted_by(nr_banks);
};
int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
void gs101_pinctrl_suspend(struct samsung_pin_bank *bank);
void gs101_pinctrl_resume(struct samsung_pin_bank *bank);
struct samsung_retention_ctrl *
exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
const struct samsung_retention_data *data);
#endif /* __PINCTRL_SAMSUNG_EXYNOS_H */
linux-7.2.3/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
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// SPDX-License-Identifier: GPL-2.0+
//
// S3C64xx specific support for pinctrl-samsung driver.
//
// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
//
// Based on pinctrl-exynos.c, please see the file for original copyrights.
//
// This file contains the Samsung S3C64xx specific information required by the
// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
// external gpio and wakeup interrupt support.
#include <linux/init.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/slab.h>
#include <linux/err.h>
#include "pinctrl-samsung.h"
#define NUM_EINT0 28
#define NUM_EINT0_IRQ 4
#define EINT_MAX_PER_REG 16
#define EINT_MAX_PER_GROUP 16
/* External GPIO and wakeup interrupt related definitions */
#define SVC_GROUP_SHIFT 4
#define SVC_GROUP_MASK 0xf
#define SVC_NUM_MASK 0xf
#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
SVC_GROUP_MASK)
#define EINT12CON_REG 0x200
#define EINT12MASK_REG 0x240
#define EINT12PEND_REG 0x260
#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
#define EINT_REG(g) (4 * ((g) / 2))
#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
#define SERVICE_REG 0x284
#define SERVICEPEND_REG 0x288
#define EINT0CON0_REG 0x900
#define EINT0MASK_REG 0x920
#define EINT0PEND_REG 0x924
/* S3C64xx specific external interrupt trigger types */
#define EINT_LEVEL_LOW 0
#define EINT_LEVEL_HIGH 1
#define EINT_EDGE_FALLING 2
#define EINT_EDGE_RISING 4
#define EINT_EDGE_BOTH 6
#define EINT_CON_MASK 0xF
#define EINT_CON_LEN 4
#define S3C_PIN_PULL_DISABLE 0
#define S3C_PIN_PULL_DOWN 1
#define S3C_PIN_PULL_UP 2
static const struct samsung_pin_bank_type bank_type_4bit_off = {
.fld_width = { 4, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
};
static const struct samsung_pin_bank_type bank_type_4bit_alive = {
.fld_width = { 4, 1, 2, },
.reg_offset = { 0x00, 0x04, 0x08, },
};
static const struct samsung_pin_bank_type bank_type_4bit2_off = {
.fld_width = { 4, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
};
static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
.fld_width = { 4, 1, 2, },
.reg_offset = { 0x00, 0x08, 0x0c, },
};
static const struct samsung_pin_bank_type bank_type_2bit_off = {
.fld_width = { 2, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
};
static const struct samsung_pin_bank_type bank_type_2bit_alive = {
.fld_width = { 2, 1, 2, },
.reg_offset = { 0x00, 0x04, 0x08, },
};
#define PIN_BANK_4BIT(pins, reg, id) \
{ \
.type = &bank_type_4bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
{ \
.type = &bank_type_4bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_func = 7, \
.eint_mask = (1 << (pins)) - 1, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
{ \
.type = &bank_type_4bit_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 3, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
{ \
.type = &bank_type_4bit2_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_func = 7, \
.eint_mask = (1 << (pins)) - 1, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
{ \
.type = &bank_type_4bit2_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 3, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
{ \
.type = &bank_type_4bit2_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT(pins, reg, id) \
{ \
.type = &bank_type_2bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
{ \
.type = &bank_type_2bit_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_func = 3, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
{ \
.type = &bank_type_2bit_alive,\
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 2, \
.eint_mask = (1 << (pins)) - 1, \
.eint_offset = eoffs, \
.name = id \
}
/**
* struct s3c64xx_eint0_data - EINT0 common data
* @drvdata: pin controller driver data
* @domains: IRQ domains of particular EINT0 interrupts
* @pins: pin offsets inside of banks of particular EINT0 interrupts
*/
struct s3c64xx_eint0_data {
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *domains[NUM_EINT0];
u8 pins[NUM_EINT0];
};
/**
* struct s3c64xx_eint0_domain_data - EINT0 per-domain data
* @bank: pin bank related to the domain
* @eints: EINT0 interrupts related to the domain
*/
struct s3c64xx_eint0_domain_data {
struct samsung_pin_bank *bank;
u8 eints[];
};
/**
* struct s3c64xx_eint_gpio_data - GPIO EINT data
* @drvdata: pin controller driver data
* @domains: array of domains related to EINT interrupt groups
*/
struct s3c64xx_eint_gpio_data {
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *domains[];
};
/*
* Common functions for S3C64xx EINT configuration
*/
static int s3c64xx_irq_get_trigger(unsigned int type)
{
int trigger;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
trigger = EINT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
trigger = EINT_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
trigger = EINT_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
trigger = EINT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
trigger = EINT_LEVEL_LOW;
break;
default:
return -EINVAL;
}
return trigger;
}
static void s3c64xx_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
{
unsigned int *pud_val = drvdata->pud_val;
pud_val[PUD_PULL_DISABLE] = S3C_PIN_PULL_DISABLE;
pud_val[PUD_PULL_DOWN] = S3C_PIN_PULL_DOWN;
pud_val[PUD_PULL_UP] = S3C_PIN_PULL_UP;
}
static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
{
/* Edge- and level-triggered interrupts need different handlers */
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else
irq_set_handler_locked(d, handle_level_irq);
}
static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
struct samsung_pin_bank *bank, int pin)
{
const struct samsung_pin_bank_type *bank_type = bank->type;
unsigned long flags;
void __iomem *reg;
u8 shift;
u32 mask;
u32 val;
/* Make sure that pin is configured as interrupt */
reg = d->virt_base + bank->pctl_offset;
shift = pin;
if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
/* 4-bit bank type with 2 con regs */
reg += 4;
shift -= 8;
}
shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
raw_spin_lock_irqsave(&bank->slock, flags);
val = readl(reg);
val &= ~(mask << shift);
val |= bank->eint_func << shift;
writel(val, reg);
raw_spin_unlock_irqrestore(&bank->slock, flags);
}
/*
* Functions for EINT GPIO configuration (EINT groups 1-9)
*/
static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
u32 val;
val = readl(reg);
if (mask)
val |= 1 << index;
else
val &= ~(1 << index);
writel(val, reg);
}
static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
{
s3c64xx_gpio_irq_set_mask(irqd, false);
}
static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
{
s3c64xx_gpio_irq_set_mask(irqd, true);
}
static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
writel(1 << index, reg);
}
static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
void __iomem *reg;
int trigger;
u8 shift;
u32 val;
trigger = s3c64xx_irq_get_trigger(type);
if (trigger < 0) {
pr_err("unsupported external interrupt type\n");
return -EINVAL;
}
s3c64xx_irq_set_handler(irqd, type);
/* Set up interrupt trigger */
reg = d->virt_base + EINTCON_REG(bank->eint_offset);
shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
val = readl(reg);
val &= ~(EINT_CON_MASK << shift);
val |= trigger << shift;
writel(val, reg);
s3c64xx_irq_set_function(d, bank, irqd->hwirq);
return 0;
}
/*
* irq_chip for gpio interrupts.
*/
static struct irq_chip s3c64xx_gpio_irq_chip = {
.name = "GPIO",
.irq_unmask = s3c64xx_gpio_irq_unmask,
.irq_mask = s3c64xx_gpio_irq_mask,
.irq_ack = s3c64xx_gpio_irq_ack,
.irq_set_type = s3c64xx_gpio_irq_set_type,
};
static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct samsung_pin_bank *bank = h->host_data;
if (!(bank->eint_mask & (1 << hw)))
return -EINVAL;
irq_set_chip_and_handler(virq,
&s3c64xx_gpio_irq_chip, handle_level_irq);
irq_set_chip_data(virq, bank);
return 0;
}
/*
* irq domain callbacks for external gpio interrupt controller.
*/
static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
.map = s3c64xx_gpio_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
chained_irq_enter(chip, desc);
do {
unsigned int svc;
unsigned int group;
unsigned int pin;
int ret;
svc = readl(drvdata->virt_base + SERVICE_REG);
group = SVC_GROUP(svc);
pin = svc & SVC_NUM_MASK;
if (!group)
break;
/* Group 1 is used for two pin banks */
if (group == 1) {
if (pin < 8)
group = 0;
else
pin -= 8;
}
ret = generic_handle_domain_irq(data->domains[group], pin);
/*
* Something must be really wrong if an unmapped EINT
* was unmasked...
*/
BUG_ON(ret);
} while (1);
chained_irq_exit(chip, desc);
}
/**
* s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
* @d: driver data of samsung pinctrl driver.
*/
static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
{
struct s3c64xx_eint_gpio_data *data;
struct samsung_pin_bank *bank;
struct device *dev = d->dev;
unsigned int nr_domains;
unsigned int i;
if (!d->irq) {
dev_err(dev, "irq number not available\n");
return -EINVAL;
}
nr_domains = 0;
bank = d->pin_banks;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
unsigned int nr_eints;
unsigned int mask;
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
mask = bank->eint_mask;
nr_eints = fls(mask);
bank->irq_domain = irq_domain_create_linear(bank->fwnode,
nr_eints, &s3c64xx_gpio_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "gpio irq domain add failed\n");
return -ENXIO;
}
++nr_domains;
}
data = devm_kzalloc(dev, struct_size(data, domains, nr_domains),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->drvdata = d;
bank = d->pin_banks;
nr_domains = 0;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
data->domains[nr_domains++] = bank->irq_domain;
}
irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
return 0;
}
/*
* Functions for configuration of EINT0 wake-up interrupts
*/
static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
u32 val;
val = readl(d->virt_base + EINT0MASK_REG);
if (mask)
val |= 1 << ddata->eints[irqd->hwirq];
else
val &= ~(1 << ddata->eints[irqd->hwirq]);
writel(val, d->virt_base + EINT0MASK_REG);
}
static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
{
s3c64xx_eint0_irq_set_mask(irqd, false);
}
static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
{
s3c64xx_eint0_irq_set_mask(irqd, true);
}
static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
writel(1 << ddata->eints[irqd->hwirq],
d->virt_base + EINT0PEND_REG);
}
static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pin_bank *bank = ddata->bank;
struct samsung_pinctrl_drv_data *d = bank->drvdata;
void __iomem *reg;
int trigger;
u8 shift;
u32 val;
trigger = s3c64xx_irq_get_trigger(type);
if (trigger < 0) {
pr_err("unsupported external interrupt type\n");
return -EINVAL;
}
s3c64xx_irq_set_handler(irqd, type);
/* Set up interrupt trigger */
reg = d->virt_base + EINT0CON0_REG;
shift = ddata->eints[irqd->hwirq];
if (shift >= EINT_MAX_PER_REG) {
reg += 4;
shift -= EINT_MAX_PER_REG;
}
shift = EINT_CON_LEN * (shift / 2);
val = readl(reg);
val &= ~(EINT_CON_MASK << shift);
val |= trigger << shift;
writel(val, reg);
s3c64xx_irq_set_function(d, bank, irqd->hwirq);
return 0;
}
/*
* irq_chip for wakeup interrupts
*/
static struct irq_chip s3c64xx_eint0_irq_chip = {
.name = "EINT0",
.irq_unmask = s3c64xx_eint0_irq_unmask,
.irq_mask = s3c64xx_eint0_irq_mask,
.irq_ack = s3c64xx_eint0_irq_ack,
.irq_set_type = s3c64xx_eint0_irq_set_type,
};
static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
unsigned int pend, mask;
chained_irq_enter(chip, desc);
pend = readl(drvdata->virt_base + EINT0PEND_REG);
mask = readl(drvdata->virt_base + EINT0MASK_REG);
pend = pend & range & ~mask;
pend &= range;
while (pend) {
unsigned int irq;
int ret;
irq = fls(pend) - 1;
pend &= ~(1 << irq);
ret = generic_handle_domain_irq(data->domains[irq], data->pins[irq]);
/*
* Something must be really wrong if an unmapped EINT
* was unmasked...
*/
BUG_ON(ret);
}
chained_irq_exit(chip, desc);
}
static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(desc, 0xf);
}
static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(desc, 0xff0);
}
static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(desc, 0xff000);
}
static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
{
s3c64xx_irq_demux_eint(desc, 0xff00000);
}
static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
s3c64xx_demux_eint0_3,
s3c64xx_demux_eint4_11,
s3c64xx_demux_eint12_19,
s3c64xx_demux_eint20_27,
};
static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct s3c64xx_eint0_domain_data *ddata = h->host_data;
struct samsung_pin_bank *bank = ddata->bank;
if (!(bank->eint_mask & (1 << hw)))
return -EINVAL;
irq_set_chip_and_handler(virq,
&s3c64xx_eint0_irq_chip, handle_level_irq);
irq_set_chip_data(virq, ddata);
return 0;
}
/*
* irq domain callbacks for external wakeup interrupt controller.
*/
static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
.map = s3c64xx_eint0_irq_map,
.xlate = irq_domain_xlate_twocell,
};
/* list of external wakeup controllers supported */
static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
{ .compatible = "samsung,s3c64xx-wakeup-eint", },
{ }
};
/**
* s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
*/
static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
{
struct device *dev = d->dev;
struct device_node *eint0_np = NULL;
struct device_node *np;
struct samsung_pin_bank *bank;
struct s3c64xx_eint0_data *data;
unsigned int i;
for_each_child_of_node(dev->of_node, np) {
if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
eint0_np = np;
break;
}
}
if (!eint0_np)
return -ENODEV;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data) {
of_node_put(eint0_np);
return -ENOMEM;
}
data->drvdata = d;
for (i = 0; i < NUM_EINT0_IRQ; ++i) {
unsigned int irq;
irq = irq_of_parse_and_map(eint0_np, i);
if (!irq) {
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
of_node_put(eint0_np);
return -ENXIO;
}
irq_set_chained_handler_and_data(irq,
s3c64xx_eint0_handlers[i],
data);
}
of_node_put(eint0_np);
bank = d->pin_banks;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
struct s3c64xx_eint0_domain_data *ddata;
unsigned int nr_eints;
unsigned int mask;
unsigned int irq;
unsigned int pin;
if (bank->eint_type != EINT_TYPE_WKUP)
continue;
mask = bank->eint_mask;
nr_eints = fls(mask);
ddata = devm_kzalloc(dev,
sizeof(*ddata) + nr_eints, GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->bank = bank;
bank->irq_domain = irq_domain_create_linear(bank->fwnode,
nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
}
irq = bank->eint_offset;
mask = bank->eint_mask;
for (pin = 0; mask; ++pin, mask >>= 1) {
if (!(mask & 1))
continue;
data->domains[irq] = bank->irq_domain;
data->pins[irq] = pin;
ddata->eints[pin] = irq;
++irq;
}
}
return 0;
}
/* pin banks of s3c64xx pin-controller 0 */
static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
PIN_BANK_4BIT(5, 0x080, "gpe"),
PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
PIN_BANK_2BIT(16, 0x100, "gpi"),
PIN_BANK_2BIT(12, 0x120, "gpj"),
PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
};
/*
* Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
* one gpio/pin-mux/pinconfig controller.
*/
static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
{
/* pin-controller instance 1 data */
.pin_banks = s3c64xx_pin_banks0,
.nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
.eint_gpio_init = s3c64xx_eint_gpio_init,
.eint_wkup_init = s3c64xx_eint_eint0_init,
.pud_value_init = s3c64xx_pud_value_init,
},
};
const struct samsung_pinctrl_of_match_data s3c64xx_of_data __initconst = {
.ctrl = s3c64xx_pin_ctrl,
.num_ctrl = ARRAY_SIZE(s3c64xx_pin_ctrl),
};
linux-7.2.3/drivers/pinctrl/samsung/pinctrl-samsung.c
+1546
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/pinctrl/samsung/pinctrl-samsung.h
+411
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@@ -0,0 +1,411 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* http://www.linaro.org
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
*/
#ifndef __PINCTRL_SAMSUNG_H
#define __PINCTRL_SAMSUNG_H
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/gpio/driver.h>
/**
* enum pincfg_type - possible pin configuration types supported.
* @PINCFG_TYPE_FUNC: Function configuration.
* @PINCFG_TYPE_DAT: Pin value configuration.
* @PINCFG_TYPE_PUD: Pull up/down configuration.
* @PINCFG_TYPE_DRV: Drive strength configuration.
* @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
* @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
*/
enum pincfg_type {
PINCFG_TYPE_FUNC,
PINCFG_TYPE_DAT,
PINCFG_TYPE_PUD,
PINCFG_TYPE_DRV,
PINCFG_TYPE_CON_PDN,
PINCFG_TYPE_PUD_PDN,
PINCFG_TYPE_NUM
};
/*
* pin configuration (pull up/down and drive strength) type and its value are
* packed together into a 16-bits. The upper 8-bits represent the configuration
* type and the lower 8-bits hold the value of the configuration type.
*/
#define PINCFG_TYPE_MASK 0xFF
#define PINCFG_VALUE_SHIFT 8
#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
PINCFG_VALUE_SHIFT)
/*
* Values for the pin CON register, choosing pin function.
* The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210,
* Exynos ARMv7, Exynos ARMv8, Tesla FSD.
*/
#define PIN_CON_FUNC_INPUT 0x0
#define PIN_CON_FUNC_OUTPUT 0x1
/* Values for the pin PUD register */
#define EXYNOS_PIN_PUD_PULL_DISABLE 0x0
#define EXYNOS_PIN_PID_PULL_DOWN 0x1
#define EXYNOS_PIN_PID_PULL_UP 0x3
/*
* enum pud_index - Possible index values to access the pud_val array.
* @PUD_PULL_DISABLE: Index for the value of pud disable
* @PUD_PULL_DOWN: Index for the value of pull down enable
* @PUD_PULL_UP: Index for the value of pull up enable
* @PUD_MAX: Maximum value of the index
*/
enum pud_index {
PUD_PULL_DISABLE,
PUD_PULL_DOWN,
PUD_PULL_UP,
PUD_MAX,
};
/**
* enum eint_type - possible external interrupt types.
* @EINT_TYPE_NONE: bank does not support external interrupts
* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
*
* Samsung GPIO controller groups all the available pins into banks. The pins
* in a pin bank can support external gpio interrupts or external wakeup
* interrupts or no interrupts at all. From a software perspective, the only
* difference between external gpio and external wakeup interrupts is that
* the wakeup interrupts can additionally wakeup the system if it is in
* suspended state.
*/
enum eint_type {
EINT_TYPE_NONE,
EINT_TYPE_GPIO,
EINT_TYPE_WKUP,
EINT_TYPE_WKUP_MUX,
};
/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
#define PIN_NAME_LENGTH 10
#define PIN_GROUP(n, p, f) \
{ \
.name = n, \
.pins = p, \
.num_pins = ARRAY_SIZE(p), \
.func = f \
}
#define PMX_FUNC(n, g) \
{ \
.name = n, \
.groups = g, \
.num_groups = ARRAY_SIZE(g), \
}
struct samsung_pinctrl_drv_data;
/**
* struct samsung_pin_bank_type: pin bank type description
* @fld_width: widths of configuration bitfields (0 if unavailable)
* @reg_offset: offsets of configuration registers (don't care of width is 0)
*/
struct samsung_pin_bank_type {
u8 fld_width[PINCFG_TYPE_NUM];
u8 reg_offset[PINCFG_TYPE_NUM];
};
/**
* struct samsung_pin_bank_data: represent a controller pin-bank (init data).
* @type: type of the bank (register offsets and bitfield widths)
* @pctl_offset: starting offset of the pin-bank registers.
* @pctl_res_idx: index of base address for pin-bank registers.
* @nr_pins: number of pins included in this bank.
* @eint_func: function to set in CON register to configure pin as EINT.
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
* @eint_num: total number of eint pins.
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
* @name: name to be prefixed for each pin in this pin bank.
*/
struct samsung_pin_bank_data {
const struct samsung_pin_bank_type *type;
u32 pctl_offset;
u8 pctl_res_idx;
u8 nr_pins;
u8 eint_func;
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
u32 eint_num;
u32 eint_con_offset;
u32 eint_mask_offset;
u32 eint_pend_offset;
u32 eint_fltcon_offset;
const char *name;
};
/**
* struct samsung_pin_bank: represent a controller pin-bank.
* @type: type of the bank (register offsets and bitfield widths)
* @pctl_base: base address of the pin-bank registers
* @pctl_offset: starting offset of the pin-bank registers.
* @nr_pins: number of pins included in this bank.
* @eint_base: base address of the pin-bank EINT registers.
* @eint_func: function to set in CON register to configure pin as EINT.
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
* @eint_num: total number of eint pins.
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
* @name: name to be prefixed for each pin in this pin bank.
* @id: id of the bank, propagated to the pin range.
* @pin_base: starting pin number of the bank.
* @soc_priv: per-bank private data for SoC-specific code.
* @of_node: OF node of the bank.
* @drvdata: link to controller driver data
* @irq_domain: IRQ domain of the bank.
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
* @irq_chip: link to irq chip for external gpio and wakeup interrupts.
* @slock: spinlock protecting bank registers
* @pm_save: saved register values during suspend
*/
struct samsung_pin_bank {
const struct samsung_pin_bank_type *type;
void __iomem *pctl_base;
u32 pctl_offset;
u8 nr_pins;
void __iomem *eint_base;
u8 eint_func;
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
u32 eint_num;
u32 eint_con_offset;
u32 eint_mask_offset;
u32 eint_pend_offset;
u32 eint_fltcon_offset;
const char *name;
u32 id;
u32 pin_base;
void *soc_priv;
struct fwnode_handle *fwnode;
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *irq_domain;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
struct exynos_irq_chip *irq_chip;
raw_spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
};
/**
* struct samsung_retention_data: runtime pin-bank retention control data.
* @regs: array of PMU registers to control pad retention.
* @nr_regs: number of registers in @regs array.
* @value: value to store to registers to turn off retention.
* @refcnt: atomic counter if retention control affects more than one bank.
* @priv: retention control code private data
* @enable: platform specific callback to enter retention mode.
* @disable: platform specific callback to exit retention mode.
**/
struct samsung_retention_ctrl {
const u32 *regs;
int nr_regs;
u32 value;
atomic_t *refcnt;
void *priv;
void (*enable)(struct samsung_pinctrl_drv_data *);
void (*disable)(struct samsung_pinctrl_drv_data *);
};
/**
* struct samsung_retention_data: represent a pin-bank retention control data.
* @regs: array of PMU registers to control pad retention.
* @nr_regs: number of registers in @regs array.
* @value: value to store to registers to turn off retention.
* @refcnt: atomic counter if retention control affects more than one bank.
* @init: platform specific callback to initialize retention control.
**/
struct samsung_retention_data {
const u32 *regs;
int nr_regs;
u32 value;
atomic_t *refcnt;
struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,
const struct samsung_retention_data *);
};
/**
* struct samsung_pin_ctrl: represent a pin controller.
* @pin_banks: list of pin banks included in this controller.
* @nr_banks: number of pin banks.
* @nr_ext_resources: number of the extra base address for pin banks.
* @retention_data: configuration data for retention control.
* @eint_gpio_init: platform specific callback to setup the external gpio
* interrupts for the controller.
* @eint_wkup_init: platform specific callback to setup the external wakeup
* interrupts for the controller.
* @suspend: platform specific suspend callback, executed during pin controller
* device suspend, see samsung_pinctrl_suspend()
* @resume: platform specific resume callback, executed during pin controller
* device suspend, see samsung_pinctrl_resume()
*
* External wakeup interrupts must define at least eint_wkup_init,
* retention_data and suspend in order for proper suspend/resume to work.
*/
struct samsung_pin_ctrl {
const struct samsung_pin_bank_data *pin_banks;
unsigned int nr_banks;
unsigned int nr_ext_resources;
const struct samsung_retention_data *retention_data;
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata);
void (*suspend)(struct samsung_pin_bank *bank);
void (*resume)(struct samsung_pin_bank *bank);
};
/**
* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
* @node: global list node
* @virt_base: register base address of the controller; this will be equal
* to each bank samsung_pin_bank->pctl_base and used on legacy
* platforms (like S3C24XX or S3C64XX) which has to access the base
* through samsung_pinctrl_drv_data, not samsung_pin_bank).
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
* @pclk: optional bus clock if required for accessing registers
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
* @pin_groups: list of pin groups available to the driver.
* @nr_groups: number of such pin groups.
* @pmx_functions: list of pin functions available to the driver.
* @nr_function: number of such pin functions.
* @nr_pins: number of pins supported by the controller.
* @retention_ctrl: retention control runtime data.
* @suspend: platform specific suspend callback, executed during pin controller
* device suspend, see samsung_pinctrl_suspend()
* @resume: platform specific resume callback, executed during pin controller
* device suspend, see samsung_pinctrl_resume()
*/
struct samsung_pinctrl_drv_data {
struct list_head node;
void __iomem *virt_base;
struct device *dev;
int irq;
struct clk *pclk;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
const struct samsung_pin_group *pin_groups;
unsigned int nr_groups;
const struct samsung_pmx_func *pmx_functions;
unsigned int nr_functions;
struct samsung_pin_bank *pin_banks;
unsigned int nr_banks;
unsigned int nr_pins;
unsigned int pud_val[PUD_MAX];
struct samsung_retention_ctrl *retention_ctrl;
void (*suspend)(struct samsung_pin_bank *bank);
void (*resume)(struct samsung_pin_bank *bank);
};
/**
* struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
* @ctrl: array of pin controller data.
* @num_ctrl: size of array @ctrl.
*/
struct samsung_pinctrl_of_match_data {
const struct samsung_pin_ctrl *ctrl;
unsigned int num_ctrl;
};
/**
* struct samsung_pin_group: represent group of pins of a pinmux function.
* @name: name of the pin group, used to lookup the group.
* @pins: the pins included in this group.
* @num_pins: number of pins included in this group.
* @func: the function number to be programmed when selected.
*/
struct samsung_pin_group {
const char *name;
const unsigned int *pins;
u8 num_pins;
u8 func;
};
/**
* struct samsung_pmx_func: represent a pin function.
* @name: name of the pin function, used to lookup the function.
* @groups: one or more names of pin groups that provide this function.
* @num_groups: number of groups included in @groups.
*/
struct samsung_pmx_func {
const char *name;
const char **groups;
u8 num_groups;
u32 val;
};
/* list of all exported SoC specific data */
extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
extern const struct samsung_pinctrl_of_match_data artpec9_of_data;
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5250_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
extern const struct samsung_pinctrl_of_match_data exynos9810_of_data;
extern const struct samsung_pinctrl_of_match_data exynos990_of_data;
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
extern const struct samsung_pinctrl_of_match_data gs101_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
#endif /* __PINCTRL_SAMSUNG_H */