lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/drivers/platform/x86/intel/pmc/Kconfig
+55
View File
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0
#
# Intel x86 Platform-Specific Drivers
#
config INTEL_PMC_CORE
tristate "Intel PMC Core driver"
depends on PCI
depends on ACPI
depends on INTEL_PMT_TELEMETRY
select INTEL_PMC_SSRAM_TELEMETRY
select INTEL_PMC_PWRM_TELEMETRY
help
The Intel Platform Controller Hub for Intel Core SoCs provides access
to Power Management Controller registers via various interfaces. This
driver can utilize debugging capabilities and supported features as
exposed by the Power Management Controller. It also may perform some
tasks in the PMC in order to enable transition into the SLPS0 state.
It should be selected on all Intel platforms supported by the driver.
Supported features:
- SLP_S0_RESIDENCY counter
- PCH IP Power Gating status
- LTR Ignore / LTR Show
- MPHY/PLL gating status (Sunrisepoint PCH only)
- SLPS0 Debug registers (Cannonlake/Icelake PCH)
- Low Power Mode registers (Tigerlake and beyond)
- PMC quirks as needed to enable SLPS0/S0ix
config INTEL_PMC_SSRAM_TELEMETRY
tristate
help
This driver discovers PMC SSRAM telemetry regions through the PMC's
MMIO interface (PCI) or ACPI _DSD properties and registers them with
the Intel VSEC framework as Intel PMT telemetry devices.
It probes the PMC SSRAM device, extracts DVSEC information from MMIO,
reads device IDs and base addresses for multiple PMCs (main, IOE, PCH),
and exposes the discovered telemetry through Intel PMT interfaces
(including sysfs).
This option is selected by INTEL_PMC_CORE.
config INTEL_PMC_PWRM_TELEMETRY
tristate
help
This driver discovers PMC PWRM telemetry regions described in ACPI
_DSD and registers them with the Intel VSEC framework as Intel PMT
telemetry devices.
It validates the ACPI discovery data and publishes the discovered
regions so they can be accessed through the Intel PMT telemetry
interfaces (including sysfs).
This option is selected by INTEL_PMC_CORE.
linux-7.2.3/drivers/platform/x86/intel/pmc/Makefile
+17
View File
@@ -0,0 +1,17 @@
# SPDX-License-Identifier: GPL-2.0
#
# Intel x86 Platform-Specific Drivers
#
intel_pmc_core-y := core.o spt.o cnp.o icl.o \
tgl.o adl.o mtl.o arl.o \
lnl.o ptl.o wcl.o nvl.o
obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
intel_pmc_core_pltdrv-y := pltdrv.o
obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
# Intel PMC SSRAM driver
intel_pmc_ssram_telemetry-y += ssram_telemetry.o
obj-$(CONFIG_INTEL_PMC_SSRAM_TELEMETRY) += intel_pmc_ssram_telemetry.o
intel_pmc_pwrm_telemetry-y += pwrm_telemetry.o
obj-$(CONFIG_INTEL_PMC_PWRM_TELEMETRY) += intel_pmc_pwrm_telemetry.o
linux-7.2.3/drivers/platform/x86/intel/pmc/adl.c
+318
View File
@@ -0,0 +1,318 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Alder Lake PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include "core.h"
/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
static const struct pmc_bit_map adl_pfear_map[] = {
{"SPI/eSPI", BIT(2)},
{"XHCI", BIT(3)},
{"SPA", BIT(4)},
{"SPB", BIT(5)},
{"SPC", BIT(6)},
{"GBE", BIT(7)},
{"SATA", BIT(0)},
{"HDA_PGD0", BIT(1)},
{"HDA_PGD1", BIT(2)},
{"HDA_PGD2", BIT(3)},
{"HDA_PGD3", BIT(4)},
{"SPD", BIT(5)},
{"LPSS", BIT(6)},
{"SMB", BIT(0)},
{"ISH", BIT(1)},
{"ITH", BIT(3)},
{"XDCI", BIT(1)},
{"DCI", BIT(2)},
{"CSE", BIT(3)},
{"CSME_KVM", BIT(4)},
{"CSME_PMT", BIT(5)},
{"CSME_CLINK", BIT(6)},
{"CSME_PTIO", BIT(7)},
{"CSME_USBR", BIT(0)},
{"CSME_SUSRAM", BIT(1)},
{"CSME_SMT1", BIT(2)},
{"CSME_SMS2", BIT(4)},
{"CSME_SMS1", BIT(5)},
{"CSME_RTC", BIT(6)},
{"CSME_PSF", BIT(7)},
{"CNVI", BIT(3)},
{"HDA_PGD4", BIT(2)},
{"HDA_PGD5", BIT(3)},
{"HDA_PGD6", BIT(4)},
{}
};
static const struct pmc_bit_map *ext_adl_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
adl_pfear_map,
NULL
};
static const struct pmc_bit_map adl_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
{"ME", CNP_PMC_LTR_ME},
/* EVA is Enterprise Value Add, doesn't really exist on PCH */
{"SATA1", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"SATA2", CNP_PMC_LTR_CAM},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
{"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
{}
};
static const struct pmc_bit_map adl_clocksource_status_map[] = {
{"CLKPART1_OFF_STS", BIT(0)},
{"CLKPART2_OFF_STS", BIT(1)},
{"CLKPART3_OFF_STS", BIT(2)},
{"CLKPART4_OFF_STS", BIT(3)},
{"CLKPART5_OFF_STS", BIT(4)},
{"CLKPART6_OFF_STS", BIT(5)},
{"CLKPART7_OFF_STS", BIT(6)},
{"CLKPART8_OFF_STS", BIT(7)},
{"PCIE0PLL_OFF_STS", BIT(10)},
{"PCIE1PLL_OFF_STS", BIT(11)},
{"PCIE2PLL_OFF_STS", BIT(12)},
{"PCIE3PLL_OFF_STS", BIT(13)},
{"PCIE4PLL_OFF_STS", BIT(14)},
{"PCIE5PLL_OFF_STS", BIT(15)},
{"PCIE6PLL_OFF_STS", BIT(16)},
{"USB2PLL_OFF_STS", BIT(18)},
{"OCPLL_OFF_STS", BIT(22)},
{"AUDIOPLL_OFF_STS", BIT(23)},
{"GBEPLL_OFF_STS", BIT(24)},
{"Fast_XTAL_Osc_OFF_STS", BIT(25)},
{"AC_Ring_Osc_OFF_STS", BIT(26)},
{"MC_Ring_Osc_OFF_STS", BIT(27)},
{"SATAPLL_OFF_STS", BIT(29)},
{"USB3PLL_OFF_STS", BIT(31)},
{}
};
static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
{"PMC_PGD0_PG_STS", BIT(0)},
{"DMI_PGD0_PG_STS", BIT(1)},
{"ESPISPI_PGD0_PG_STS", BIT(2)},
{"XHCI_PGD0_PG_STS", BIT(3)},
{"SPA_PGD0_PG_STS", BIT(4)},
{"SPB_PGD0_PG_STS", BIT(5)},
{"SPC_PGD0_PG_STS", BIT(6)},
{"GBE_PGD0_PG_STS", BIT(7)},
{"SATA_PGD0_PG_STS", BIT(8)},
{"DSP_PGD0_PG_STS", BIT(9)},
{"DSP_PGD1_PG_STS", BIT(10)},
{"DSP_PGD2_PG_STS", BIT(11)},
{"DSP_PGD3_PG_STS", BIT(12)},
{"SPD_PGD0_PG_STS", BIT(13)},
{"LPSS_PGD0_PG_STS", BIT(14)},
{"SMB_PGD0_PG_STS", BIT(16)},
{"ISH_PGD0_PG_STS", BIT(17)},
{"NPK_PGD0_PG_STS", BIT(19)},
{"PECI_PGD0_PG_STS", BIT(21)},
{"XDCI_PGD0_PG_STS", BIT(25)},
{"EXI_PGD0_PG_STS", BIT(26)},
{"CSE_PGD0_PG_STS", BIT(27)},
{"KVMCC_PGD0_PG_STS", BIT(28)},
{"PMT_PGD0_PG_STS", BIT(29)},
{"CLINK_PGD0_PG_STS", BIT(30)},
{"PTIO_PGD0_PG_STS", BIT(31)},
{}
};
static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
{"USBR0_PGD0_PG_STS", BIT(0)},
{"SMT1_PGD0_PG_STS", BIT(2)},
{"CSMERTC_PGD0_PG_STS", BIT(6)},
{"CSMEPSF_PGD0_PG_STS", BIT(7)},
{"CNVI_PGD0_PG_STS", BIT(19)},
{"DSP_PGD4_PG_STS", BIT(26)},
{"SPG_PGD0_PG_STS", BIT(27)},
{"SPE_PGD0_PG_STS", BIT(28)},
{}
};
static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
{"THC0_PGD0_PG_STS", BIT(7)},
{"THC1_PGD0_PG_STS", BIT(8)},
{"SPF_PGD0_PG_STS", BIT(14)},
{}
};
static const struct pmc_bit_map adl_d3_status_0_map[] = {
{"ISH_D3_STS", BIT(2)},
{"LPSS_D3_STS", BIT(3)},
{"XDCI_D3_STS", BIT(4)},
{"XHCI_D3_STS", BIT(5)},
{"SPA_D3_STS", BIT(12)},
{"SPB_D3_STS", BIT(13)},
{"SPC_D3_STS", BIT(14)},
{"SPD_D3_STS", BIT(15)},
{"SPE_D3_STS", BIT(16)},
{"DSP_D3_STS", BIT(19)},
{"SATA_D3_STS", BIT(20)},
{"DMI_D3_STS", BIT(22)},
{}
};
static const struct pmc_bit_map adl_d3_status_1_map[] = {
{"GBE_D3_STS", BIT(19)},
{"CNVI_D3_STS", BIT(27)},
{}
};
static const struct pmc_bit_map adl_d3_status_2_map[] = {
{"CSMERTC_D3_STS", BIT(1)},
{"CSE_D3_STS", BIT(4)},
{"KVMCC_D3_STS", BIT(5)},
{"USBR0_D3_STS", BIT(6)},
{"SMT1_D3_STS", BIT(8)},
{"PTIO_D3_STS", BIT(16)},
{"PMT_D3_STS", BIT(17)},
{}
};
static const struct pmc_bit_map adl_d3_status_3_map[] = {
{"THC0_D3_STS", BIT(14)},
{"THC1_D3_STS", BIT(15)},
{}
};
static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
{"ISH_VNN_REQ_STS", BIT(2)},
{"ESPISPI_VNN_REQ_STS", BIT(18)},
{"DSP_VNN_REQ_STS", BIT(19)},
{}
};
static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
{"NPK_VNN_REQ_STS", BIT(4)},
{"EXI_VNN_REQ_STS", BIT(9)},
{"GBE_VNN_REQ_STS", BIT(19)},
{"SMB_VNN_REQ_STS", BIT(25)},
{"CNVI_VNN_REQ_STS", BIT(27)},
{}
};
static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
{"CSMERTC_VNN_REQ_STS", BIT(1)},
{"CSE_VNN_REQ_STS", BIT(4)},
{"SMT1_VNN_REQ_STS", BIT(8)},
{"CLINK_VNN_REQ_STS", BIT(14)},
{"GPIOCOM4_VNN_REQ_STS", BIT(20)},
{"GPIOCOM3_VNN_REQ_STS", BIT(21)},
{"GPIOCOM2_VNN_REQ_STS", BIT(22)},
{"GPIOCOM1_VNN_REQ_STS", BIT(23)},
{"GPIOCOM0_VNN_REQ_STS", BIT(24)},
{}
};
static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
{}
};
static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS", BIT(0)},
{"PCIe_LPM_En_REQ_STS", BIT(3)},
{"ITH_REQ_STS", BIT(5)},
{"CNVI_REQ_STS", BIT(6)},
{"ISH_REQ_STS", BIT(7)},
{"USB2_SUS_PG_Sys_REQ_STS", BIT(10)},
{"PCIe_Clk_REQ_STS", BIT(12)},
{"MPHY_Core_DL_REQ_STS", BIT(16)},
{"Break-even_En_REQ_STS", BIT(17)},
{"MPHY_SUS_REQ_STS", BIT(22)},
{"xDCI_attached_REQ_STS", BIT(24)},
{}
};
static const struct pmc_bit_map *adl_lpm_maps[] = {
adl_clocksource_status_map,
adl_power_gating_status_0_map,
adl_power_gating_status_1_map,
adl_power_gating_status_2_map,
adl_d3_status_0_map,
adl_d3_status_1_map,
adl_d3_status_2_map,
adl_d3_status_3_map,
adl_vnn_req_status_0_map,
adl_vnn_req_status_1_map,
adl_vnn_req_status_2_map,
adl_vnn_req_status_3_map,
adl_vnn_misc_status_map,
tgl_signal_status_map,
NULL
};
const struct pmc_reg_map adl_reg_map = {
.pfear_sts = ext_adl_pfear_map,
.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = adl_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
.lpm_num_modes = ADL_LPM_NUM_MODES,
.lpm_num_maps = ADL_LPM_NUM_MAPS,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.etr3_offset = ETR3_OFFSET,
.lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET,
.lpm_priority_offset = ADL_LPM_PRI_OFFSET,
.lpm_en_offset = ADL_LPM_EN_OFFSET,
.lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET,
.lpm_sts = adl_lpm_maps,
.lpm_status_offset = ADL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET,
.pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,
.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
};
struct pmc_dev_info adl_pmc_dev = {
.map = &adl_reg_map,
.suspend = cnl_suspend,
.resume = cnl_resume,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/arl.c
+754
View File
@@ -0,0 +1,754 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Arrow Lake PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include <linux/pci.h>
#include "core.h"
/* PMC SSRAM PMT Telemetry GUID */
#define IOEP_LPM_REQ_GUID 0x5077612
#define SOCS_LPM_REQ_GUID 0x8478657
#define PCHS_LPM_REQ_GUID 0x9684572
#define SOCM_LPM_REQ_GUID 0x2625030
static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
static const struct pmc_bit_map arl_socs_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
{"ME", CNP_PMC_LTR_ME},
/* EVA is Enterprise Value Add, doesn't really exist on PCH */
{"SATA1", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"SATA2", CNP_PMC_LTR_CAM},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
{"SOUTHPORT_G", MTL_PMC_LTR_SPG},
{"Reserved", ARL_SOCS_PMC_LTR_RESERVED},
{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
{"DMI3", ARL_PMC_LTR_DMI3},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
{}
};
static const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
{"AON2_OFF_STS", BIT(0)},
{"AON3_OFF_STS", BIT(1)},
{"AON4_OFF_STS", BIT(2)},
{"AON5_OFF_STS", BIT(3)},
{"AON1_OFF_STS", BIT(4)},
{"XTAL_LVM_OFF_STS", BIT(5)},
{"AON3_SPL_OFF_STS", BIT(9)},
{"DMI3FPW_0_PLL_OFF_STS", BIT(10)},
{"DMI3FPW_1_PLL_OFF_STS", BIT(11)},
{"G5X16FPW_0_PLL_OFF_STS", BIT(14)},
{"G5X16FPW_1_PLL_OFF_STS", BIT(15)},
{"G5X16FPW_2_PLL_OFF_STS", BIT(16)},
{"XTAL_AGGR_OFF_STS", BIT(17)},
{"USB2_PLL_OFF_STS", BIT(18)},
{"G5X16FPW_3_PLL_OFF_STS", BIT(19)},
{"BCLK_EXT_INJ_CLK_OFF_STS", BIT(20)},
{"PHY_OC_EXT_INJ_CLK_OFF_STS", BIT(21)},
{"FILTER_PLL_OFF_STS", BIT(22)},
{"FABRIC_PLL_OFF_STS", BIT(25)},
{"SOC_PLL_OFF_STS", BIT(26)},
{"PCIEFAB_PLL_OFF_STS", BIT(27)},
{"REF_PLL_OFF_STS", BIT(28)},
{"GENLOCK_FILTER_PLL_OFF_STS", BIT(30)},
{"RTC_PLL_OFF_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
{"PMC_PGD0_PG_STS", BIT(0)},
{"DMI_PGD0_PG_STS", BIT(1)},
{"ESPISPI_PGD0_PG_STS", BIT(2)},
{"XHCI_PGD0_PG_STS", BIT(3)},
{"SPA_PGD0_PG_STS", BIT(4)},
{"SPB_PGD0_PG_STS", BIT(5)},
{"SPC_PGD0_PG_STS", BIT(6)},
{"GBE_PGD0_PG_STS", BIT(7)},
{"SATA_PGD0_PG_STS", BIT(8)},
{"FIACPCB_P5x16_PGD0_PG_STS", BIT(9)},
{"G5x16FPW_PGD0_PG_STS", BIT(10)},
{"FIA_D_PGD0_PG_STS", BIT(11)},
{"MPFPW2_PGD0_PG_STS", BIT(12)},
{"SPD_PGD0_PG_STS", BIT(13)},
{"LPSS_PGD0_PG_STS", BIT(14)},
{"LPC_PGD0_PG_STS", BIT(15)},
{"SMB_PGD0_PG_STS", BIT(16)},
{"ISH_PGD0_PG_STS", BIT(17)},
{"P2S_PGD0_PG_STS", BIT(18)},
{"NPK_PGD0_PG_STS", BIT(19)},
{"DMI3FPW_PGD0_PG_STS", BIT(20)},
{"GBETSN1_PGD0_PG_STS", BIT(21)},
{"FUSE_PGD0_PG_STS", BIT(22)},
{"FIACPCB_D_PGD0_PG_STS", BIT(23)},
{"FUSEGPSB_PGD0_PG_STS", BIT(24)},
{"XDCI_PGD0_PG_STS", BIT(25)},
{"EXI_PGD0_PG_STS", BIT(26)},
{"CSE_PGD0_PG_STS", BIT(27)},
{"KVMCC_PGD0_PG_STS", BIT(28)},
{"PMT_PGD0_PG_STS", BIT(29)},
{"CLINK_PGD0_PG_STS", BIT(30)},
{"PTIO_PGD0_PG_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
{"USBR0_PGD0_PG_STS", BIT(0)},
{"SUSRAM_PGD0_PG_STS", BIT(1)},
{"SMT1_PGD0_PG_STS", BIT(2)},
{"FIACPCB_U_PGD0_PG_STS", BIT(3)},
{"SMS2_PGD0_PG_STS", BIT(4)},
{"SMS1_PGD0_PG_STS", BIT(5)},
{"CSMERTC_PGD0_PG_STS", BIT(6)},
{"CSMEPSF_PGD0_PG_STS", BIT(7)},
{"SBR0_PGD0_PG_STS", BIT(8)},
{"SBR1_PGD0_PG_STS", BIT(9)},
{"SBR2_PGD0_PG_STS", BIT(10)},
{"SBR3_PGD0_PG_STS", BIT(11)},
{"MPFPW1_PGD0_PG_STS", BIT(12)},
{"SBR5_PGD0_PG_STS", BIT(13)},
{"FIA_X_PGD0_PG_STS", BIT(14)},
{"FIACPCB_X_PGD0_PG_STS", BIT(15)},
{"SBRG_PGD0_PG_STS", BIT(16)},
{"SOC_D2D_PGD1_PG_STS", BIT(17)},
{"PSF4_PGD0_PG_STS", BIT(18)},
{"CNVI_PGD0_PG_STS", BIT(19)},
{"UFSX2_PGD0_PG_STS", BIT(20)},
{"ENDBG_PGD0_PG_STS", BIT(21)},
{"DBG_PSF_PGD0_PG_STS", BIT(22)},
{"SBR6_PGD0_PG_STS", BIT(23)},
{"SOC_D2D_PGD2_PG_STS", BIT(24)},
{"NPK_PGD1_PG_STS", BIT(25)},
{"DMI3_PGD0_PG_STS", BIT(26)},
{"DBG_SBR_PGD0_PG_STS", BIT(27)},
{"SOC_D2D_PGD0_PG_STS", BIT(28)},
{"PSF6_PGD0_PG_STS", BIT(29)},
{"PSF7_PGD0_PG_STS", BIT(30)},
{"MPFPW3_PGD0_PG_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
{"PSF8_PGD0_PG_STS", BIT(0)},
{"FIA_PGD0_PG_STS", BIT(1)},
{"SOC_D2D_PGD3_PG_STS", BIT(2)},
{"FIA_U_PGD0_PG_STS", BIT(3)},
{"TAM_PGD0_PG_STS", BIT(4)},
{"GBETSN_PGD0_PG_STS", BIT(5)},
{"TBTLSX_PGD0_PG_STS", BIT(6)},
{"THC0_PGD0_PG_STS", BIT(7)},
{"THC1_PGD0_PG_STS", BIT(8)},
{"PMC_PGD1_PG_STS", BIT(9)},
{"FIA_P5x16_PGD0_PG_STS", BIT(10)},
{"GNA_PGD0_PG_STS", BIT(11)},
{"ACE_PGD0_PG_STS", BIT(12)},
{"ACE_PGD1_PG_STS", BIT(13)},
{"ACE_PGD2_PG_STS", BIT(14)},
{"ACE_PGD3_PG_STS", BIT(15)},
{"ACE_PGD4_PG_STS", BIT(16)},
{"ACE_PGD5_PG_STS", BIT(17)},
{"ACE_PGD6_PG_STS", BIT(18)},
{"ACE_PGD7_PG_STS", BIT(19)},
{"ACE_PGD8_PG_STS", BIT(20)},
{"FIA_PGS_PGD0_PG_STS", BIT(21)},
{"FIACPCB_PGS_PGD0_PG_STS", BIT(22)},
{"FUSEPMSB_PGD0_PG_STS", BIT(23)},
{}
};
static const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
{"CSMERTC_D3_STS", BIT(1)},
{"SUSRAM_D3_STS", BIT(2)},
{"CSE_D3_STS", BIT(4)},
{"KVMCC_D3_STS", BIT(5)},
{"USBR0_D3_STS", BIT(6)},
{"ISH_D3_STS", BIT(7)},
{"SMT1_D3_STS", BIT(8)},
{"SMT2_D3_STS", BIT(9)},
{"SMT3_D3_STS", BIT(10)},
{"GNA_D3_STS", BIT(12)},
{"CLINK_D3_STS", BIT(14)},
{"PTIO_D3_STS", BIT(16)},
{"PMT_D3_STS", BIT(17)},
{"SMS1_D3_STS", BIT(18)},
{"SMS2_D3_STS", BIT(19)},
{}
};
static const struct pmc_bit_map arl_socs_d3_status_3_map[] = {
{"GBETSN_D3_STS", BIT(13)},
{"THC0_D3_STS", BIT(14)},
{"THC1_D3_STS", BIT(15)},
{"ACE_D3_STS", BIT(23)},
{}
};
static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {
{"DTS0_VNN_REQ_STS", BIT(7)},
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
{}
};
static const struct pmc_bit_map *arl_socs_lpm_maps[] = {
arl_socs_clocksource_status_map,
arl_socs_power_gating_status_0_map,
arl_socs_power_gating_status_1_map,
arl_socs_power_gating_status_2_map,
mtl_socm_d3_status_0_map,
mtl_socm_d3_status_1_map,
arl_socs_d3_status_2_map,
arl_socs_d3_status_3_map,
mtl_socm_vnn_req_status_0_map,
mtl_socm_vnn_req_status_1_map,
mtl_socm_vnn_req_status_2_map,
arl_socs_vnn_req_status_3_map,
mtl_socm_vnn_misc_status_map,
mtl_socm_signal_status_map,
NULL
};
static const struct pmc_bit_map arl_socs_pfear_map[] = {
{"RSVD64", BIT(0)},
{"RSVD65", BIT(1)},
{"RSVD66", BIT(2)},
{"RSVD67", BIT(3)},
{"RSVD68", BIT(4)},
{"GBETSN", BIT(5)},
{"TBTLSX", BIT(6)},
{}
};
static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {
mtl_socm_pfear_map,
arl_socs_pfear_map,
NULL
};
static const struct pmc_reg_map arl_socs_reg_map = {
.pfear_sts = ext_arl_socs_pfear_map,
.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.lpm_sts = arl_socs_lpm_maps,
.ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED,
.ltr_show_sts = arl_socs_ltr_show_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = MTL_SOC_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
.lpm_en_offset = MTL_LPM_EN_OFFSET,
.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.lpm_num_maps = ADL_LPM_NUM_MAPS,
.lpm_reg_index = ARL_LPM_REG_INDEX,
.etr3_offset = ETR3_OFFSET,
.pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,
.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
.lpm_req_guid = SOCS_LPM_REQ_GUID,
};
static const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
{"ME", CNP_PMC_LTR_ME},
/* EVA is Enterprise Value Add, doesn't really exist on PCH */
{"SATA1", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"SATA2", CNP_PMC_LTR_CAM},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
{"SOUTHPORT_G", MTL_PMC_LTR_SPG},
{"ESE", MTL_PMC_LTR_ESE},
{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
{"DMI3", ARL_PMC_LTR_DMI3},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
{}
};
static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
{"AON2_OFF_STS", BIT(0)},
{"AON3_OFF_STS", BIT(1)},
{"AON4_OFF_STS", BIT(2)},
{"AON2_SPL_OFF_STS", BIT(3)},
{"AONL_OFF_STS", BIT(4)},
{"XTAL_LVM_OFF_STS", BIT(5)},
{"AON5_ACRO_OFF_STS", BIT(6)},
{"AON6_ACRO_OFF_STS", BIT(7)},
{"USB3_PLL_OFF_STS", BIT(8)},
{"ACRO_OFF_STS", BIT(9)},
{"AUDIO_PLL_OFF_STS", BIT(10)},
{"MAIN_CRO_OFF_STS", BIT(11)},
{"MAIN_DIVIDER_OFF_STS", BIT(12)},
{"REF_PLL_NON_OC_OFF_STS", BIT(13)},
{"DMI_PLL_OFF_STS", BIT(14)},
{"PHY_EXT_INJ_OFF_STS", BIT(15)},
{"AON6_MCRO_OFF_STS", BIT(16)},
{"XTAL_AGGR_OFF_STS", BIT(17)},
{"USB2_PLL_OFF_STS", BIT(18)},
{"TSN0_PLL_OFF_STS", BIT(19)},
{"TSN1_PLL_OFF_STS", BIT(20)},
{"GBE_PLL_OFF_STS", BIT(21)},
{"SATA_PLL_OFF_STS", BIT(22)},
{"PCIE0_PLL_OFF_STS", BIT(23)},
{"PCIE1_PLL_OFF_STS", BIT(24)},
{"PCIE2_PLL_OFF_STS", BIT(26)},
{"PCIE3_PLL_OFF_STS", BIT(27)},
{"REF_PLL_OFF_STS", BIT(28)},
{"PCIE4_PLL_OFF_STS", BIT(29)},
{"PCIE5_PLL_OFF_STS", BIT(30)},
{"REF38P4_PLL_OFF_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
{"PMC_PGD0_PG_STS", BIT(0)},
{"DMI_PGD0_PG_STS", BIT(1)},
{"ESPISPI_PGD0_PG_STS", BIT(2)},
{"XHCI_PGD0_PG_STS", BIT(3)},
{"SPA_PGD0_PG_STS", BIT(4)},
{"SPB_PGD0_PG_STS", BIT(5)},
{"SPC_PGD0_PG_STS", BIT(6)},
{"GBE_PGD0_PG_STS", BIT(7)},
{"SATA_PGD0_PG_STS", BIT(8)},
{"FIA_X_PGD0_PG_STS", BIT(9)},
{"MPFPW4_PGD0_PG_STS", BIT(10)},
{"EAH_PGD0_PG_STS", BIT(11)},
{"MPFPW1_PGD0_PG_STS", BIT(12)},
{"SPD_PGD0_PG_STS", BIT(13)},
{"LPSS_PGD0_PG_STS", BIT(14)},
{"LPC_PGD0_PG_STS", BIT(15)},
{"SMB_PGD0_PG_STS", BIT(16)},
{"ISH_PGD0_PG_STS", BIT(17)},
{"P2S_PGD0_PG_STS", BIT(18)},
{"NPK_PGD0_PG_STS", BIT(19)},
{"U3FPW1_PGD0_PG_STS", BIT(20)},
{"PECI_PGD0_PG_STS", BIT(21)},
{"FUSE_PGD0_PG_STS", BIT(22)},
{"SBR8_PGD0_PG_STS", BIT(23)},
{"EXE_PGD0_PG_STS", BIT(24)},
{"XDCI_PGD0_PG_STS", BIT(25)},
{"EXI_PGD0_PG_STS", BIT(26)},
{"CSE_PGD0_PG_STS", BIT(27)},
{"KVMCC_PGD0_PG_STS", BIT(28)},
{"PMT_PGD0_PG_STS", BIT(29)},
{"CLINK_PGD0_PG_STS", BIT(30)},
{"PTIO_PGD0_PG_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
{"USBR0_PGD0_PG_STS", BIT(0)},
{"SUSRAM_PGD0_PG_STS", BIT(1)},
{"SMT1_PGD0_PG_STS", BIT(2)},
{"SMT4_PGD0_PG_STS", BIT(3)},
{"SMS2_PGD0_PG_STS", BIT(4)},
{"SMS1_PGD0_PG_STS", BIT(5)},
{"CSMERTC_PGD0_PG_STS", BIT(6)},
{"CSMEPSF_PGD0_PG_STS", BIT(7)},
{"SBR0_PGD0_PG_STS", BIT(8)},
{"SBR1_PGD0_PG_STS", BIT(9)},
{"SBR2_PGD0_PG_STS", BIT(10)},
{"SBR3_PGD0_PG_STS", BIT(11)},
{"SBR4_PGD0_PG_STS", BIT(12)},
{"SBR5_PGD0_PG_STS", BIT(13)},
{"MPFPW3_PGD0_PG_STS", BIT(14)},
{"PSF1_PGD0_PG_STS", BIT(15)},
{"PSF2_PGD0_PG_STS", BIT(16)},
{"PSF3_PGD0_PG_STS", BIT(17)},
{"PSF4_PGD0_PG_STS", BIT(18)},
{"CNVI_PGD0_PG_STS", BIT(19)},
{"DMI3_PGD0_PG_STS", BIT(20)},
{"ENDBG_PGD0_PG_STS", BIT(21)},
{"DBG_SBR_PGD0_PG_STS", BIT(22)},
{"SBR6_PGD0_PG_STS", BIT(23)},
{"SBR7_PGD0_PG_STS", BIT(24)},
{"NPK_PGD1_PG_STS", BIT(25)},
{"U3FPW3_PGD0_PG_STS", BIT(26)},
{"MPFPW2_PGD0_PG_STS", BIT(27)},
{"MPFPW7_PGD0_PG_STS", BIT(28)},
{"GBETSN1_PGD0_PG_STS", BIT(29)},
{"PSF7_PGD0_PG_STS", BIT(30)},
{"FIA2_PGD0_PG_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
{"U3FPW2_PGD0_PG_STS", BIT(0)},
{"FIA_PGD0_PG_STS", BIT(1)},
{"FIACPCB_X_PGD0_PG_STS", BIT(2)},
{"FIA1_PGD0_PG_STS", BIT(3)},
{"TAM_PGD0_PG_STS", BIT(4)},
{"GBETSN_PGD0_PG_STS", BIT(5)},
{"SBR9_PGD0_PG_STS", BIT(6)},
{"THC0_PGD0_PG_STS", BIT(7)},
{"THC1_PGD0_PG_STS", BIT(8)},
{"PMC_PGD1_PG_STS", BIT(9)},
{"DBC_PGD0_PG_STS", BIT(10)},
{"DBG_PSF_PGD0_PG_STS", BIT(11)},
{"SPF_PGD0_PG_STS", BIT(12)},
{"ACE_PGD0_PG_STS", BIT(13)},
{"ACE_PGD1_PG_STS", BIT(14)},
{"ACE_PGD2_PG_STS", BIT(15)},
{"ACE_PGD3_PG_STS", BIT(16)},
{"ACE_PGD4_PG_STS", BIT(17)},
{"ACE_PGD5_PG_STS", BIT(18)},
{"ACE_PGD6_PG_STS", BIT(19)},
{"ACE_PGD7_PG_STS", BIT(20)},
{"SPE_PGD0_PG_STS", BIT(21)},
{"MPFPW5_PG_STS", BIT(22)},
{}
};
static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
{"SPF_D3_STS", BIT(0)},
{"LPSS_D3_STS", BIT(3)},
{"XDCI_D3_STS", BIT(4)},
{"XHCI_D3_STS", BIT(5)},
{"SPA_D3_STS", BIT(12)},
{"SPB_D3_STS", BIT(13)},
{"SPC_D3_STS", BIT(14)},
{"SPD_D3_STS", BIT(15)},
{"SPE_D3_STS", BIT(16)},
{"ESPISPI_D3_STS", BIT(18)},
{"SATA_D3_STS", BIT(20)},
{"PSTH_D3_STS", BIT(21)},
{"DMI_D3_STS", BIT(22)},
{}
};
static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
{"GBETSN1_D3_STS", BIT(14)},
{"GBE_D3_STS", BIT(19)},
{"ITSS_D3_STS", BIT(23)},
{"P2S_D3_STS", BIT(24)},
{"CNVI_D3_STS", BIT(27)},
{}
};
static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
{"CSMERTC_D3_STS", BIT(1)},
{"SUSRAM_D3_STS", BIT(2)},
{"CSE_D3_STS", BIT(4)},
{"KVMCC_D3_STS", BIT(5)},
{"USBR0_D3_STS", BIT(6)},
{"ISH_D3_STS", BIT(7)},
{"SMT1_D3_STS", BIT(8)},
{"SMT2_D3_STS", BIT(9)},
{"SMT3_D3_STS", BIT(10)},
{"SMT4_D3_STS", BIT(11)},
{"SMT5_D3_STS", BIT(12)},
{"SMT6_D3_STS", BIT(13)},
{"CLINK_D3_STS", BIT(14)},
{"PTIO_D3_STS", BIT(16)},
{"PMT_D3_STS", BIT(17)},
{"SMS1_D3_STS", BIT(18)},
{"SMS2_D3_STS", BIT(19)},
{}
};
static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
{"ESE_D3_STS", BIT(3)},
{"GBETSN_D3_STS", BIT(13)},
{"THC0_D3_STS", BIT(14)},
{"THC1_D3_STS", BIT(15)},
{"ACE_D3_STS", BIT(23)},
{}
};
static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {
{"FIA_VNN_REQ_STS", BIT(17)},
{"ESPISPI_VNN_REQ_STS", BIT(18)},
{}
};
static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
{"NPK_VNN_REQ_STS", BIT(4)},
{"DFXAGG_VNN_REQ_STS", BIT(8)},
{"EXI_VNN_REQ_STS", BIT(9)},
{"GBE_VNN_REQ_STS", BIT(19)},
{"SMB_VNN_REQ_STS", BIT(25)},
{"LPC_VNN_REQ_STS", BIT(26)},
{"CNVI_VNN_REQ_STS", BIT(27)},
{}
};
static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
{"FIA2_VNN_REQ_STS", BIT(0)},
{"CSMERTC_VNN_REQ_STS", BIT(1)},
{"CSE_VNN_REQ_STS", BIT(4)},
{"ISH_VNN_REQ_STS", BIT(7)},
{"SMT1_VNN_REQ_STS", BIT(8)},
{"SMT4_VNN_REQ_STS", BIT(11)},
{"CLINK_VNN_REQ_STS", BIT(14)},
{"SMS1_VNN_REQ_STS", BIT(18)},
{"SMS2_VNN_REQ_STS", BIT(19)},
{"GPIOCOM4_VNN_REQ_STS", BIT(20)},
{"GPIOCOM3_VNN_REQ_STS", BIT(21)},
{"GPIOCOM2_VNN_REQ_STS", BIT(22)},
{"GPIOCOM1_VNN_REQ_STS", BIT(23)},
{"GPIOCOM0_VNN_REQ_STS", BIT(24)},
{}
};
static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {
{"ESE_VNN_REQ_STS", BIT(3)},
{"DTS0_VNN_REQ_STS", BIT(7)},
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
{"FIA1_VNN_REQ_STS", BIT(12)},
{}
};
static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS", BIT(0)},
{"TS_OFF_REQ_STS", BIT(1)},
{"PNDE_MET_REQ_STS", BIT(2)},
{"PCIE_DEEP_PM_REQ_STS", BIT(3)},
{"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4)},
{"ISH_VNNAON_REQ_STS", BIT(7)},
{"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},
{"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},
{"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},
{"PLT_GREATER_REQ_STS", BIT(11)},
{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
{"PM_SYNC_STATES_REQ_STS", BIT(14)},
{"EA_REQ_STS", BIT(15)},
{"DMI_CLKREQ_B_REQ_STS", BIT(16)},
{"BRK_EV_EN_REQ_STS", BIT(17)},
{"AUTO_DEMO_EN_REQ_STS", BIT(18)},
{"ITSS_CLK_SRC_REQ_STS", BIT(19)},
{"ARC_IDLE_REQ_STS", BIT(21)},
{"DMI_IN_REQ_STS", BIT(22)},
{"FIA_DEEP_PM_REQ_STS", BIT(23)},
{"XDCI_ATTACHED_REQ_STS", BIT(24)},
{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
{"PRE_WAKE0_REQ_STS", BIT(27)},
{"PRE_WAKE1_REQ_STS", BIT(28)},
{"PRE_WAKE2_EN_REQ_STS", BIT(29)},
{"CNVI_V1P05_REQ_STS", BIT(31)},
{}
};
static const struct pmc_bit_map arl_pchs_signal_status_map[] = {
{"LSX_Wake0_STS", BIT(0)},
{"LSX_Wake1_STS", BIT(1)},
{"LSX_Wake2_STS", BIT(2)},
{"LSX_Wake3_STS", BIT(3)},
{"LSX_Wake4_STS", BIT(4)},
{"LSX_Wake5_STS", BIT(5)},
{"LSX_Wake6_STS", BIT(6)},
{"LSX_Wake7_STS", BIT(7)},
{"Int_Timer_SS_Wake0_STS", BIT(8)},
{"Int_Timer_SS_Wake1_STS", BIT(9)},
{"Int_Timer_SS_Wake0_STS", BIT(10)},
{"Int_Timer_SS_Wake1_STS", BIT(11)},
{"Int_Timer_SS_Wake2_STS", BIT(12)},
{"Int_Timer_SS_Wake3_STS", BIT(13)},
{"Int_Timer_SS_Wake4_STS", BIT(14)},
{"Int_Timer_SS_Wake5_STS", BIT(15)},
{}
};
static const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
arl_pchs_clocksource_status_map,
arl_pchs_power_gating_status_0_map,
arl_pchs_power_gating_status_1_map,
arl_pchs_power_gating_status_2_map,
arl_pchs_d3_status_0_map,
arl_pchs_d3_status_1_map,
arl_pchs_d3_status_2_map,
arl_pchs_d3_status_3_map,
arl_pchs_vnn_req_status_0_map,
arl_pchs_vnn_req_status_1_map,
arl_pchs_vnn_req_status_2_map,
arl_pchs_vnn_req_status_3_map,
arl_pchs_vnn_misc_status_map,
arl_pchs_signal_status_map,
NULL
};
static const struct pmc_reg_map arl_pchs_reg_map = {
.pfear_sts = ext_arl_socs_pfear_map,
.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED,
.lpm_sts = arl_pchs_lpm_maps,
.ltr_show_sts = arl_pchs_ltr_show_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = ARL_PCH_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
.lpm_en_offset = MTL_LPM_EN_OFFSET,
.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.lpm_num_maps = ADL_LPM_NUM_MAPS,
.lpm_reg_index = ARL_LPM_REG_INDEX,
.etr3_offset = ETR3_OFFSET,
.lpm_req_guid = PCHS_LPM_REQ_GUID,
};
static struct pmc_info arl_pmc_info_list[] = {
{
.devid = PMC_DEVID_ARL_IOEP,
.map = &mtl_ioep_reg_map,
},
{
.devid = PMC_DEVID_ARL_SOCS,
.map = &arl_socs_reg_map,
},
{
.devid = PMC_DEVID_ARL_PCHS,
.map = &arl_pchs_reg_map,
},
{
.devid = PMC_DEVID_ARL_SOCM,
.map = &mtl_socm_reg_map,
},
{}
};
static const u8 arl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_PCH};
static const u8 arl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE};
#define ARL_NPU_PCI_DEV 0xad1d
#define ARL_GNA_PCI_DEV 0xae4c
#define ARL_H_NPU_PCI_DEV 0x7d1d
#define ARL_H_GNA_PCI_DEV 0x774c
/*
* Set power state of select devices that do not have drivers to D3
* so that they do not block Package C entry.
*/
static void arl_d3_fixup(void)
{
pmc_core_set_device_d3(ARL_NPU_PCI_DEV);
pmc_core_set_device_d3(ARL_GNA_PCI_DEV);
}
static void arl_h_d3_fixup(void)
{
pmc_core_set_device_d3(ARL_H_NPU_PCI_DEV);
pmc_core_set_device_d3(ARL_H_GNA_PCI_DEV);
}
static int arl_resume(struct pmc_dev *pmcdev)
{
arl_d3_fixup();
return cnl_resume(pmcdev);
}
static int arl_h_resume(struct pmc_dev *pmcdev)
{
arl_h_d3_fixup();
return cnl_resume(pmcdev);
}
static int arl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
arl_d3_fixup();
return generic_core_init(pmcdev, pmc_dev_info);
}
static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
arl_h_d3_fixup();
return generic_core_init(pmcdev, pmc_dev_info);
}
static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
struct pmc_dev_info arl_pmc_dev = {
.dmu_guids = ARL_PMT_DMU_GUIDS,
.num_pmcs = ARRAY_SIZE(arl_pmc_list),
.pmc_list = arl_pmc_list,
.regmap_list = arl_pmc_info_list,
.map = &arl_socs_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
.suspend = cnl_suspend,
.resume = arl_resume,
.init = arl_core_init,
.sub_req = pmc_core_pmt_get_lpm_req,
.ssram_hidden = true,
.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
};
static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
struct pmc_dev_info arl_h_pmc_dev = {
.dmu_guids = ARL_H_PMT_DMU_GUIDS,
.num_pmcs = ARRAY_SIZE(arl_h_pmc_list),
.pmc_list = arl_h_pmc_list,
.regmap_list = arl_pmc_info_list,
.map = &mtl_socm_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
.suspend = cnl_suspend,
.resume = arl_h_resume,
.init = arl_h_core_init,
.sub_req = pmc_core_pmt_get_lpm_req,
.ssram_hidden = true,
.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/cnp.c
+283
View File
@@ -0,0 +1,283 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Cannon Lake Point PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include <linux/smp.h>
#include <linux/suspend.h>
#include <asm/msr.h>
#include "core.h"
/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
const struct pmc_bit_map cnp_pfear_map[] = {
{"PMC", BIT(0)},
{"OPI-DMI", BIT(1)},
{"SPI/eSPI", BIT(2)},
{"XHCI", BIT(3)},
{"SPA", BIT(4)},
{"SPB", BIT(5)},
{"SPC", BIT(6)},
{"GBE", BIT(7)},
{"SATA", BIT(0)},
{"HDA_PGD0", BIT(1)},
{"HDA_PGD1", BIT(2)},
{"HDA_PGD2", BIT(3)},
{"HDA_PGD3", BIT(4)},
{"SPD", BIT(5)},
{"LPSS", BIT(6)},
{"LPC", BIT(7)},
{"SMB", BIT(0)},
{"ISH", BIT(1)},
{"P2SB", BIT(2)},
{"NPK_VNN", BIT(3)},
{"SDX", BIT(4)},
{"SPE", BIT(5)},
{"Fuse", BIT(6)},
{"SBR8", BIT(7)},
{"CSME_FSC", BIT(0)},
{"USB3_OTG", BIT(1)},
{"EXI", BIT(2)},
{"CSE", BIT(3)},
{"CSME_KVM", BIT(4)},
{"CSME_PMT", BIT(5)},
{"CSME_CLINK", BIT(6)},
{"CSME_PTIO", BIT(7)},
{"CSME_USBR", BIT(0)},
{"CSME_SUSRAM", BIT(1)},
{"CSME_SMT1", BIT(2)},
{"CSME_SMT4", BIT(3)},
{"CSME_SMS2", BIT(4)},
{"CSME_SMS1", BIT(5)},
{"CSME_RTC", BIT(6)},
{"CSME_PSF", BIT(7)},
{"SBR0", BIT(0)},
{"SBR1", BIT(1)},
{"SBR2", BIT(2)},
{"SBR3", BIT(3)},
{"SBR4", BIT(4)},
{"SBR5", BIT(5)},
{"CSME_PECI", BIT(6)},
{"PSF1", BIT(7)},
{"PSF2", BIT(0)},
{"PSF3", BIT(1)},
{"PSF4", BIT(2)},
{"CNVI", BIT(3)},
{"UFS0", BIT(4)},
{"EMMC", BIT(5)},
{"SPF", BIT(6)},
{"SBR6", BIT(7)},
{"SBR7", BIT(0)},
{"NPK_AON", BIT(1)},
{"HDA_PGD4", BIT(2)},
{"HDA_PGD5", BIT(3)},
{"HDA_PGD6", BIT(4)},
{"PSF6", BIT(5)},
{"PSF7", BIT(6)},
{"PSF8", BIT(7)},
{}
};
static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
cnp_pfear_map,
NULL
};
static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
{"AUDIO_D3", BIT(0)},
{"OTG_D3", BIT(1)},
{"XHCI_D3", BIT(2)},
{"LPIO_D3", BIT(3)},
{"SDX_D3", BIT(4)},
{"SATA_D3", BIT(5)},
{"UFS0_D3", BIT(6)},
{"UFS1_D3", BIT(7)},
{"EMMC_D3", BIT(8)},
{}
};
static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
{"SDIO_PLL_OFF", BIT(0)},
{"USB2_PLL_OFF", BIT(1)},
{"AUDIO_PLL_OFF", BIT(2)},
{"OC_PLL_OFF", BIT(3)},
{"MAIN_PLL_OFF", BIT(4)},
{"XOSC_OFF", BIT(5)},
{"LPC_CLKS_GATED", BIT(6)},
{"PCIE_CLKREQS_IDLE", BIT(7)},
{"AUDIO_ROSC_OFF", BIT(8)},
{"HPET_XOSC_CLK_REQ", BIT(9)},
{"PMC_ROSC_SLOW_CLK", BIT(10)},
{"AON2_ROSC_GATED", BIT(11)},
{"CLKACKS_DEASSERTED", BIT(12)},
{}
};
static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
{"MPHY_CORE_GATED", BIT(0)},
{"CSME_GATED", BIT(1)},
{"USB2_SUS_GATED", BIT(2)},
{"DYN_FLEX_IO_IDLE", BIT(3)},
{"GBE_NO_LINK", BIT(4)},
{"THERM_SEN_DISABLED", BIT(5)},
{"PCIE_LOW_POWER", BIT(6)},
{"ISH_VNNAON_REQ_ACT", BIT(7)},
{"ISH_VNN_REQ_ACT", BIT(8)},
{"CNV_VNNAON_REQ_ACT", BIT(9)},
{"CNV_VNN_REQ_ACT", BIT(10)},
{"NPK_VNNON_REQ_ACT", BIT(11)},
{"PMSYNC_STATE_IDLE", BIT(12)},
{"ALST_GT_THRES", BIT(13)},
{"PMC_ARC_PG_READY", BIT(14)},
{}
};
const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
cnp_slps0_dbg0_map,
cnp_slps0_dbg1_map,
cnp_slps0_dbg2_map,
NULL
};
const struct pmc_bit_map cnp_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"Reserved", CNP_PMC_LTR_RESERVED},
{"ME", CNP_PMC_LTR_ME},
/* EVA is Enterprise Value Add, doesn't really exist on PCH */
{"EVA", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"CAMERA", CNP_PMC_LTR_CAM},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
{}
};
const struct pmc_reg_map cnp_reg_map = {
.pfear_sts = ext_cnp_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
.slps0_dbg_maps = cnp_slps0_dbg_maps,
.ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map,
.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
.etr3_offset = ETR3_OFFSET,
};
/*
* Disable C1 auto-demotion
*
* Aggressive C1 auto-demotion may lead to failure to enter the deepest C-state
* during suspend-to-idle, causing high power consumption. To prevent this, we
* disable C1 auto-demotion during suspend and re-enable on resume.
*
* Note that, although MSR_PKG_CST_CONFIG_CONTROL has 'package' in its name, it
* is actually a per-core MSR on client platforms, affecting only a single CPU.
* Therefore, it must be configured on all online CPUs. The online cpu mask is
* unchanged during the phase of suspend/resume as user space is frozen.
*/
static DEFINE_PER_CPU(u64, pkg_cst_config);
static void disable_c1_auto_demote(void *unused)
{
int cpunum = smp_processor_id();
u64 val;
rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);
per_cpu(pkg_cst_config, cpunum) = val;
val &= ~NHM_C1_AUTO_DEMOTE;
wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);
pr_debug("%s: cpu:%d cst %llx\n", __func__, cpunum, val);
}
static void restore_c1_auto_demote(void *unused)
{
int cpunum = smp_processor_id();
wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, per_cpu(pkg_cst_config, cpunum));
pr_debug("%s: cpu:%d cst %llx\n", __func__, cpunum,
per_cpu(pkg_cst_config, cpunum));
}
static void s2idle_cpu_quirk(smp_call_func_t func)
{
if (pm_suspend_via_firmware())
return;
on_each_cpu(func, NULL, true);
}
void cnl_suspend(struct pmc_dev *pmcdev)
{
s2idle_cpu_quirk(disable_c1_auto_demote);
/*
* Due to a hardware limitation, the GBE LTR blocks PC10
* when a cable is attached. To unblock PC10 during suspend,
* tell the PMC to ignore it.
*/
pmc_core_send_ltr_ignore(pmcdev, 3, 1);
}
int cnl_resume(struct pmc_dev *pmcdev)
{
s2idle_cpu_quirk(restore_c1_auto_demote);
pmc_core_send_ltr_ignore(pmcdev, 3, 0);
return pmc_core_resume_common(pmcdev);
}
struct pmc_dev_info cnp_pmc_dev = {
.map = &cnp_reg_map,
.suspend = cnl_suspend,
.resume = cnl_resume,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/core.c
+2161
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/platform/x86/intel/pmc/core.h
+662
View File
@@ -0,0 +1,662 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel Core SoC Power Management Controller Header File
*
* Copyright (c) 2016, Intel Corporation.
* All Rights Reserved.
*
* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
*/
#ifndef PMC_CORE_H
#define PMC_CORE_H
#include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/cleanup.h>
#include <linux/intel_vsec.h>
#include <linux/platform_device.h>
#include <linux/uuid.h>
struct telem_endpoint;
DEFINE_FREE(pmc_acpi_free, void *, if (_T) ACPI_FREE(_T))
#define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0)
#define PMC_BASE_ADDR_DEFAULT 0xFE000000
#define MAX_NUM_PMC 3
#define S0IX_BLK_SIZE 4
/* PCH query */
#define LPM_HEADER_OFFSET 1
#define LPM_REG_COUNT 28
#define LPM_MODE_OFFSET 1
/* Sunrise Point Power Management Controller PCI Device ID */
#define SPT_PMC_PCI_DEVICE_ID 0x9d21
#define SPT_PMC_BASE_ADDR_OFFSET 0x48
#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
#define SPT_PMC_PM_CFG_OFFSET 0x18
#define SPT_PMC_PM_STS_OFFSET 0x1c
#define SPT_PMC_MTPMC_OFFSET 0x20
#define SPT_PMC_MFPMC_OFFSET 0x38
#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
#define SPT_PMC_VRIC1_OFFSET 0x31c
#define SPT_PMC_MPHY_CORE_STS_0 0x1143
#define SPT_PMC_MPHY_CORE_STS_1 0x1142
#define SPT_PMC_MPHY_COM_STS_0 0x1155
#define SPT_PMC_MMIO_REG_LEN 0x1000
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68
#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
#define MTPMC_MASK 0xffff0000
#define PPFEAR_MAX_NUM_ENTRIES 13
#define SPT_PPFEAR_NUM_ENTRIES 5
#define SPT_PMC_READ_DISABLE_BIT 0x16
#define SPT_PMC_MSG_FULL_STS_BIT 0x18
#define NUM_RETRIES 100
#define SPT_NUM_IP_IGN_ALLOWED 17
#define SPT_PMC_LTR_CUR_PLT 0x350
#define SPT_PMC_LTR_CUR_ASLT 0x354
#define SPT_PMC_LTR_SPA 0x360
#define SPT_PMC_LTR_SPB 0x364
#define SPT_PMC_LTR_SATA 0x368
#define SPT_PMC_LTR_GBE 0x36C
#define SPT_PMC_LTR_XHCI 0x370
#define SPT_PMC_LTR_RESERVED 0x374
#define SPT_PMC_LTR_ME 0x378
#define SPT_PMC_LTR_EVA 0x37C
#define SPT_PMC_LTR_SPC 0x380
#define SPT_PMC_LTR_AZ 0x384
#define SPT_PMC_LTR_LPSS 0x38C
#define SPT_PMC_LTR_CAM 0x390
#define SPT_PMC_LTR_SPD 0x394
#define SPT_PMC_LTR_SPE 0x398
#define SPT_PMC_LTR_ESPI 0x39C
#define SPT_PMC_LTR_SCC 0x3A0
#define SPT_PMC_LTR_ISH 0x3A4
/* Sunrise Point: PGD PFET Enable Ack Status Registers */
enum ppfear_regs {
SPT_PMC_XRAM_PPFEAR0A = 0x590,
SPT_PMC_XRAM_PPFEAR0B,
SPT_PMC_XRAM_PPFEAR0C,
SPT_PMC_XRAM_PPFEAR0D,
SPT_PMC_XRAM_PPFEAR1A,
};
#define SPT_PMC_BIT_PMC BIT(0)
#define SPT_PMC_BIT_OPI BIT(1)
#define SPT_PMC_BIT_SPI BIT(2)
#define SPT_PMC_BIT_XHCI BIT(3)
#define SPT_PMC_BIT_SPA BIT(4)
#define SPT_PMC_BIT_SPB BIT(5)
#define SPT_PMC_BIT_SPC BIT(6)
#define SPT_PMC_BIT_GBE BIT(7)
#define SPT_PMC_BIT_SATA BIT(0)
#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
#define SPT_PMC_BIT_RSVD_0B BIT(5)
#define SPT_PMC_BIT_LPSS BIT(6)
#define SPT_PMC_BIT_LPC BIT(7)
#define SPT_PMC_BIT_SMB BIT(0)
#define SPT_PMC_BIT_ISH BIT(1)
#define SPT_PMC_BIT_P2SB BIT(2)
#define SPT_PMC_BIT_DFX BIT(3)
#define SPT_PMC_BIT_SCC BIT(4)
#define SPT_PMC_BIT_RSVD_0C BIT(5)
#define SPT_PMC_BIT_FUSE BIT(6)
#define SPT_PMC_BIT_CAMREA BIT(7)
#define SPT_PMC_BIT_RSVD_0D BIT(0)
#define SPT_PMC_BIT_USB3_OTG BIT(1)
#define SPT_PMC_BIT_EXI BIT(2)
#define SPT_PMC_BIT_CSE BIT(3)
#define SPT_PMC_BIT_CSME_KVM BIT(4)
#define SPT_PMC_BIT_CSME_PMT BIT(5)
#define SPT_PMC_BIT_CSME_CLINK BIT(6)
#define SPT_PMC_BIT_CSME_PTIO BIT(7)
#define SPT_PMC_BIT_CSME_USBR BIT(0)
#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
#define SPT_PMC_BIT_CSME_SMT BIT(2)
#define SPT_PMC_BIT_RSVD_1A BIT(3)
#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
#define SPT_PMC_BIT_CSME_RTC BIT(6)
#define SPT_PMC_BIT_CSME_PSF BIT(7)
#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
/* Cannonlake Power Management Controller register offsets */
#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
#define CNP_PMC_PM_CFG_OFFSET 0x1818
#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
#define CNP_PMC_HOST_PPFEAR0A 0x1D90
#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
#define CNP_PMC_MMIO_REG_LEN 0x2000
#define CNP_PPFEAR_NUM_ENTRIES 8
#define CNP_PMC_READ_DISABLE_BIT 22
#define CNP_NUM_IP_IGN_ALLOWED 19
#define CNP_PMC_LTR_CUR_PLT 0x1B50
#define CNP_PMC_LTR_CUR_ASLT 0x1B54
#define CNP_PMC_LTR_SPA 0x1B60
#define CNP_PMC_LTR_SPB 0x1B64
#define CNP_PMC_LTR_SATA 0x1B68
#define CNP_PMC_LTR_GBE 0x1B6C
#define CNP_PMC_LTR_XHCI 0x1B70
#define CNP_PMC_LTR_RESERVED 0x1B74
#define CNP_PMC_LTR_ME 0x1B78
#define CNP_PMC_LTR_EVA 0x1B7C
#define CNP_PMC_LTR_SPC 0x1B80
#define CNP_PMC_LTR_AZ 0x1B84
#define CNP_PMC_LTR_LPSS 0x1B8C
#define CNP_PMC_LTR_CAM 0x1B90
#define CNP_PMC_LTR_SPD 0x1B94
#define CNP_PMC_LTR_SPE 0x1B98
#define CNP_PMC_LTR_ESPI 0x1B9C
#define CNP_PMC_LTR_SCC 0x1BA0
#define CNP_PMC_LTR_ISH 0x1BA4
#define CNP_PMC_LTR_CNV 0x1BF0
#define CNP_PMC_LTR_EMMC 0x1BF4
#define CNP_PMC_LTR_UFSX2 0x1BF8
#define LTR_DECODED_VAL GENMASK(9, 0)
#define LTR_DECODED_SCALE GENMASK(12, 10)
#define LTR_REQ_SNOOP BIT(15)
#define LTR_REQ_NONSNOOP BIT(31)
#define ICL_PPFEAR_NUM_ENTRIES 9
#define ICL_NUM_IP_IGN_ALLOWED 20
#define ICL_PMC_LTR_WIGIG 0x1BFC
#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
#define LPM_MAX_NUM_MODES 8
#define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 }
#define GET_X2_COUNTER(v) ((v) >> 1)
#define LPM_STS_LATCH_MODE BIT(31)
#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
#define TGL_PMC_LTR_THC0 0x1C04
#define TGL_PMC_LTR_THC1 0x1C08
#define TGL_NUM_IP_IGN_ALLOWED 23
#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */
#define ADL_PMC_LTR_SPF 0x1C00
#define ADL_NUM_IP_IGN_ALLOWED 23
#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098
/*
* Tigerlake Power Management Controller register offsets
*/
#define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34
#define TGL_LPM_EN_OFFSET 0x1C78
#define TGL_LPM_RESIDENCY_OFFSET 0x1C80
/* Tigerlake Low Power Mode debug registers */
#define TGL_LPM_STATUS_OFFSET 0x1C3C
#define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C
#define TGL_LPM_PRI_OFFSET 0x1C7C
#define TGL_LPM_NUM_MAPS 6
/* Tigerlake PSON residency register */
#define TGL_PSON_RESIDENCY_OFFSET 0x18f8
#define TGL_PSON_RES_COUNTER_STEP 0x7A
/* Extended Test Mode Register 3 (CNL and later) */
#define ETR3_OFFSET 0x1048
#define ETR3_CF9GR BIT(20)
#define ETR3_CF9LOCK BIT(31)
/* Extended Test Mode Register LPM bits (TGL and later */
#define ETR3_CLEAR_LPM_EVENTS BIT(28)
/* Alder Lake Power Management Controller register offsets */
#define ADL_LPM_EN_OFFSET 0x179C
#define ADL_LPM_RESIDENCY_OFFSET 0x17A4
#define ADL_LPM_NUM_MODES 2
#define ADL_LPM_NUM_MAPS 14
/* Alder Lake Low Power Mode debug registers */
#define ADL_LPM_STATUS_OFFSET 0x170C
#define ADL_LPM_PRI_OFFSET 0x17A0
#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704
#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764
/* Meteor Lake Power Management Controller register offsets */
#define MTL_LPM_EN_OFFSET 0x1798
#define MTL_LPM_RESIDENCY_OFFSET 0x17A0
/* Meteor Lake Low Power Mode debug registers */
#define MTL_LPM_PRI_OFFSET 0x179C
#define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8
#define MTL_LPM_STATUS_OFFSET 0x1700
#define MTL_LPM_LIVE_STATUS_OFFSET 0x175C
#define MTL_PMC_LTR_IOE_PMC 0x1C0C
#define MTL_PMC_LTR_ESE 0x1BAC
#define MTL_PMC_LTR_RESERVED 0x1BA4
#define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4
#define MTL_SOCM_NUM_IP_IGN_ALLOWED 25
#define MTL_SOC_PMC_MMIO_REG_LEN 0x2708
#define MTL_PMC_LTR_SPG 0x1B74
#define ARL_SOCS_PMC_LTR_RESERVED 0x1B88
#define ARL_SOCS_NUM_IP_IGN_ALLOWED 26
#define ARL_PMC_LTR_DMI3 0x1BE4
#define ARL_PCH_PMC_MMIO_REG_LEN 0x2720
/* Meteor Lake PGD PFET Enable Ack Status */
#define MTL_SOCM_PPFEAR_NUM_ENTRIES 8
#define MTL_IOE_PPFEAR_NUM_ENTRIES 10
#define ARL_SOCS_PPFEAR_NUM_ENTRIES 9
/* Die C6 from PUNIT telemetry */
#define MTL_PMT_DMU_DIE_C6_OFFSET 15
#define MTL_PMT_DMU_GUID 0x1A067102
#define ARL_PMT_DMU_GUID 0x1A06A102
#define ARL_H_PMT_DMU_GUID 0x1A06A101
#define LNL_PMC_MMIO_REG_LEN 0x2708
#define LNL_PMC_LTR_OSSE 0x1B88
#define LNL_NUM_IP_IGN_ALLOWED 27
#define LNL_PPFEAR_NUM_ENTRIES 12
#define LNL_S0IX_BLOCKER_OFFSET 0x2004
/* Panther Lake Power Management Controller register offsets */
#define PTL_LPM_NUM_MAPS 14
#define PTL_PMC_LTR_SATA2 0x1B90
#define PTL_PMC_LTR_PMC 0x1BA8
#define PTL_PMC_LTR_CUR_ASLT 0x1C28
#define PTL_PMC_LTR_CUR_PLT 0x1C2C
#define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8
#define PTL_NUM_S0IX_BLOCKER 106
#define PTL_BLK_REQ_OFFSET 55
/* Wildcat Lake */
#define WCL_PMC_LTR_RESERVED 0x1B64
#define WCL_PCD_PMC_MMIO_REG_LEN 0x3178
#define WCL_NUM_S0IX_BLOCKER 94
#define WCL_BLK_REQ_OFFSET 50
/* Nova Lake */
#define NVL_PCDH_PPFEAR_NUM_ENTRIES 13
#define NVL_PCDH_PMC_MMIO_REG_LEN 0x363c
#define NVL_PCDS_PMC_MMIO_REG_LEN 0x3118
#define NVL_PCHS_PMC_MMIO_REG_LEN 0x30d8
#define NVL_LPM_PRI_OFFSET 0x17a4
#define NVL_LPM_EN_OFFSET 0x17a0
#define NVL_LPM_RESIDENCY_OFFSET 0x17a8
#define NVL_LPM_LIVE_STATUS_OFFSET 0x1760
#define NVL_LPM_NUM_MAPS 15
#define NVL_PCDH_NUM_S0IX_BLOCKER 107
#define NVL_PCDS_NUM_S0IX_BLOCKER 71
#define NVL_PCHS_NUM_S0IX_BLOCKER 54
#define NVL_PCDS_PMC_LTR_RESERVED 0x1bac
#define NVL_PCDH_BLK_REQ_OFFSET 53
#define NVL_PCDS_BLK_REQ_OFFSET 18
#define NVL_PCHS_BLK_REQ_OFFSET 46
#define NVL_PMT_PC_GUID 0x13000101
#define NVL_PMT_DMU_GUID 0x1a000101
#define NVL_LTR_BLK_OFFSET 64
#define NVL_PKGC_BLK_OFFSET 4
#define NVL_PMT_DMU_DIE_C6_OFFSET 25
/* SSRAM PMC Device ID */
/* LNL */
#define PMC_DEVID_LNL_SOCM 0xa87f
/* PTL */
#define PMC_DEVID_PTL_PCDH 0xe37f
#define PMC_DEVID_PTL_PCDP 0xe47f
/* WCL */
#define PMC_DEVID_WCL_PCDN 0x4d7f
/* ARL */
#define PMC_DEVID_ARL_SOCM 0x777f
#define PMC_DEVID_ARL_SOCS 0xae7f
#define PMC_DEVID_ARL_IOEP 0x7ecf
#define PMC_DEVID_ARL_PCHS 0x7f27
/* MTL */
#define PMC_DEVID_MTL_SOCM 0x7e7f
#define PMC_DEVID_MTL_IOEP 0x7ecf
#define PMC_DEVID_MTL_IOEM 0x7ebf
/* NVL */
#define PMC_DEVID_NVL_PCDH 0xd37e
#define PMC_DEVID_NVL_PCDS 0xd47e
#define PMC_DEVID_NVL_PCHS 0x6e27
extern const char *pmc_lpm_modes[];
struct pmc_bit_map {
const char *name;
u32 bit_mask;
u8 blk;
};
/**
* struct pmc_reg_map - Structure used to define parameter unique to a
PCH family
* @pfear_sts: Maps name of IP block to PPFEAR* bit
* @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
* @pll_sts: Maps name of PLL to corresponding bit status
* @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
* @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
* @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter
* @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
* @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
* @regmap_length: Length of memory to map from PWRMBASE address to access
* @ppfear0_offset: PWRMBASE offset to read PPFEAR*
* @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
* PPFEAR
* @pm_cfg_offset: PWRMBASE offset to PM_CFG register
* @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
* @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
* @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter
* @num_s0ix_blocker: Number of S0ix blockers
* @blocker_req_offset: Telemetry offset to S0ix blocker low power mode substate requirement table
* @lpm_req_guid: Telemetry GUID to read low power mode substate requirement table
*
* Each PCH has unique set of register offsets and bit indexes. This structure
* captures them to have a common implementation.
*/
struct pmc_reg_map {
const struct pmc_bit_map **pfear_sts;
const struct pmc_bit_map *mphy_sts;
const struct pmc_bit_map *pll_sts;
const struct pmc_bit_map **slps0_dbg_maps;
const struct pmc_bit_map *ltr_show_sts;
const struct pmc_bit_map *msr_sts;
const struct pmc_bit_map **lpm_sts;
const struct pmc_bit_map **s0ix_blocker_maps;
const u32 slp_s0_offset;
const int slp_s0_res_counter_step;
const u32 ltr_ignore_offset;
const int regmap_length;
const u32 ppfear0_offset;
const int ppfear_buckets;
const u32 pm_cfg_offset;
const int pm_read_disable_bit;
const u32 slps0_dbg_offset;
const u32 ltr_ignore_max;
const u32 pm_vric1_offset;
const u32 s0ix_blocker_offset;
const u32 num_s0ix_blocker;
const u32 blocker_req_offset;
/* Low Power Mode registers */
const int lpm_num_maps;
const int lpm_num_modes;
const int lpm_res_counter_step_x2;
const u32 lpm_sts_latch_en_offset;
const u32 lpm_en_offset;
const u32 lpm_priority_offset;
const u32 lpm_residency_offset;
const u32 lpm_status_offset;
const u32 lpm_live_status_offset;
const u32 etr3_offset;
const u8 *lpm_reg_index;
const u32 pson_residency_offset;
const u32 pson_residency_counter_step;
/* GUID for telemetry regions */
const u32 lpm_req_guid;
};
/**
* struct pmc_info - Structure to keep pmc info
* @devid: device id of the pmc device
* @map: pointer to a pmc_reg_map struct that contains platform
* specific attributes
*/
struct pmc_info {
u16 devid;
const struct pmc_reg_map *map;
};
/**
* struct pmc - pmc private info structure
* @base_addr: contains pmc base address
* @regbase: pointer to io-remapped memory location
* @map: pointer to pmc_reg_map struct that contains platform
* specific attributes
* @lpm_req_regs: List of substate requirements
* @ltr_ign: Holds LTR ignore data while suspended
* @num_lpm_modes: Count of enabled modes
* @lpm_en_modes: Array of enabled modes from lowest to highest priority
* @devid: Device ID of the SSRAM device
*
* pmc contains info about one power management controller device.
*/
struct pmc {
u64 base_addr;
void __iomem *regbase;
const struct pmc_reg_map *map;
u32 *lpm_req_regs;
u32 ltr_ign;
u8 num_lpm_modes;
u8 lpm_en_modes[LPM_MAX_NUM_MODES];
u16 devid;
};
/**
* struct pmc_dev - pmc device structure
* @devs: pointer to an array of pmc pointers
* @pdev: pointer to platform_device struct
* @crystal_freq: crystal frequency from cpuid
* @dbgfs_dir: path to debugfs interface
* @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
* used to read MPHY PG and PLL status are available
* @mutex_lock: mutex to complete one transcation
* @pkgc_res_cnt: Array of PKGC residency counters
* @num_of_pkgc: Number of PKGC
* @s0ix_counter: S0ix residency (step adjusted)
* @suspend: Function to perform platform specific suspend
* @resume: Function to perform platform specific resume
*
* @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
* @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
* @pkgc_blocker_counters: Array of PKGC blocker counters
* @pkgc_blocker_offset: Offset to PKGC blocker in telemetry region
*
* pmc_dev contains info about power management controller device.
*/
struct pmc_dev {
struct pmc *pmcs[MAX_NUM_PMC];
struct dentry *dbgfs_dir;
struct platform_device *pdev;
unsigned int crystal_freq;
int pmc_xram_read_bit;
struct mutex lock; /* generic mutex lock for PMC Core */
u64 s0ix_counter;
void (*suspend)(struct pmc_dev *pmcdev);
int (*resume)(struct pmc_dev *pmcdev);
u64 *pkgc_res_cnt;
u8 num_of_pkgc;
u32 die_c6_offset;
struct telem_endpoint *pc_ep;
struct telem_endpoint *punit_ep;
struct pmc_info *regmap_list;
const char **pkgc_ltr_blocker_counters;
u32 pkgc_ltr_blocker_offset;
const char **pkgc_blocker_counters;
u32 pkgc_blocker_offset;
};
enum pmc_index {
PMC_IDX_MAIN,
PMC_IDX_IOE,
PMC_IDX_PCH,
PMC_IDX_MAX
};
/**
* struct pmc_dev_info - Structure to keep PMC device info
* @dmu_guids: List of Die Management Unit GUID
* @pc_guid: GUID for telemetry region to read PKGC blocker info
* @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
* @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
* @num_pmcs: Number of entries in @pmc_list
* @pmc_list: Index list of available PMC
* @regmap_list: Pointer to a list of pmc_info structure that could be
* available for the platform. When set, this field implies
* SSRAM support.
* @map: Pointer to a pmc_reg_map struct that contains platform
* specific attributes of the primary PMC
* @sub_req_show: File operations to show substate requirements
* @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
* @pkgc_blocker_counters: Array of PKGC blocker counters
* @suspend: Function to perform platform specific suspend
* @resume: Function to perform platform specific resume
* @init: Function to perform platform specific init action
* @sub_req: Function to achieve low power mode substate requirements
* @ssram_hidden: Some SSRAM devices are hidden on this platform
* @die_c6_offset: Telemetry offset to read Die C6 residency
*/
struct pmc_dev_info {
u32 *dmu_guids;
u32 pc_guid;
u32 pkgc_ltr_blocker_offset;
u32 pkgc_blocker_offset;
u8 num_pmcs;
const u8 *pmc_list;
struct pmc_info *regmap_list;
const struct pmc_reg_map *map;
const struct file_operations *sub_req_show;
const char **pkgc_ltr_blocker_counters;
const char **pkgc_blocker_counters;
void (*suspend)(struct pmc_dev *pmcdev);
int (*resume)(struct pmc_dev *pmcdev);
int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
int (*sub_req)(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endpoint *ep);
bool ssram_hidden;
u32 die_c6_offset;
};
extern const struct pmc_bit_map msr_map[];
extern const struct pmc_bit_map cnp_pfear_map[];
extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];
extern const struct pmc_bit_map cnp_ltr_show_map[];
extern const struct pmc_reg_map cnp_reg_map;
extern const struct pmc_bit_map tgl_signal_status_map[];
extern const struct pmc_reg_map adl_reg_map;
extern const struct pmc_bit_map mtl_socm_pfear_map[];
extern const struct pmc_bit_map mtl_socm_d3_status_0_map[];
extern const struct pmc_bit_map mtl_socm_d3_status_1_map[];
extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[];
extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[];
extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[];
extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[];
extern const struct pmc_bit_map mtl_socm_signal_status_map[];
extern const struct pmc_reg_map mtl_socm_reg_map;
extern const struct pmc_reg_map mtl_ioep_reg_map;
extern const struct pmc_bit_map ptl_pcdp_clocksource_status_map[];
extern const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[];
extern const struct pmc_bit_map ptl_pcdp_signal_status_map[];
extern const struct pmc_bit_map ptl_pcdp_ltr_show_map[];
void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
int pmc_core_resume_common(struct pmc_dev *pmcdev);
int get_primary_reg_base(struct pmc *pmc);
void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
void pmc_core_set_device_d3(unsigned int device);
int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
extern struct pmc_dev_info spt_pmc_dev;
extern struct pmc_dev_info cnp_pmc_dev;
extern struct pmc_dev_info icl_pmc_dev;
extern struct pmc_dev_info tgl_l_pmc_dev;
extern struct pmc_dev_info tgl_pmc_dev;
extern struct pmc_dev_info adl_pmc_dev;
extern struct pmc_dev_info mtl_pmc_dev;
extern struct pmc_dev_info arl_pmc_dev;
extern struct pmc_dev_info arl_h_pmc_dev;
extern struct pmc_dev_info lnl_pmc_dev;
extern struct pmc_dev_info ptl_pmc_dev;
extern struct pmc_dev_info wcl_pmc_dev;
extern struct pmc_dev_info nvl_s_pmc_dev;
extern struct pmc_dev_info nvl_h_pmc_dev;
void cnl_suspend(struct pmc_dev *pmcdev);
int cnl_resume(struct pmc_dev *pmcdev);
int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endpoint *ep);
int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcdev, struct pmc *pmc,
struct telem_endpoint *ep);
extern const struct file_operations pmc_core_substate_req_regs_fops;
extern const struct file_operations pmc_core_substate_blk_req_fops;
extern const guid_t intel_vsec_guid;
#define pmc_for_each_mode(mode, pmc) \
for (unsigned int __i = 0, __cond; \
__cond = __i < (pmc)->num_lpm_modes, \
__cond && ((mode) = (pmc)->lpm_en_modes[__i]), \
__cond; \
__i++)
#define DEFINE_PMC_CORE_ATTR_WRITE(__name) \
static int __name ## _open(struct inode *inode, struct file *file) \
{ \
return single_open(file, __name ## _show, inode->i_private); \
} \
\
static const struct file_operations __name ## _fops = { \
.owner = THIS_MODULE, \
.open = __name ## _open, \
.read = seq_read, \
.write = __name ## _write, \
.release = single_release, \
}
struct intel_vsec_header;
union acpi_object;
/* Avoid checkpatch warning */
typedef u32 (*acpi_disc_t)[PMT_DISC_DWORDS];
acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj,
struct intel_vsec_header *header);
union acpi_object *pmc_find_telem_guid(union acpi_object *dsd);
#endif /* PMC_CORE_H */
linux-7.2.3/drivers/platform/x86/intel/pmc/icl.c
+55
View File
@@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Ice Lake PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include "core.h"
static const struct pmc_bit_map icl_pfear_map[] = {
{"RES_65", BIT(0)},
{"RES_66", BIT(1)},
{"RES_67", BIT(2)},
{"TAM", BIT(3)},
{"GBETSN", BIT(4)},
{"TBTLSX", BIT(5)},
{"RES_71", BIT(6)},
{"RES_72", BIT(7)},
{}
};
static const struct pmc_bit_map *ext_icl_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of icl_reg_map for
* a list of core SoCs using this.
*/
cnp_pfear_map,
icl_pfear_map,
NULL
};
static const struct pmc_reg_map icl_reg_map = {
.pfear_sts = ext_icl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
.slps0_dbg_maps = cnp_slps0_dbg_maps,
.ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map,
.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
.etr3_offset = ETR3_OFFSET,
};
struct pmc_dev_info icl_pmc_dev = {
.map = &icl_reg_map,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/lnl.c
+586
View File
@@ -0,0 +1,586 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Lunar Lake PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include <linux/cpu.h>
#include <linux/pci.h>
#include "core.h"
#define SOCM_LPM_REQ_GUID 0x15099748
static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
static const struct pmc_bit_map lnl_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
{"ME", CNP_PMC_LTR_ME},
/* EVA is Enterprise Value Add, doesn't really exist on PCH */
{"SATA1", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"SATA2", CNP_PMC_LTR_CAM},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
/*
* Check intel_pmc_core_ids[] users of cnp_reg_map for
* a list of core SoCs using this.
*/
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
{"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
{"ESE", MTL_PMC_LTR_ESE},
{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
{"DMI3", ARL_PMC_LTR_DMI3},
{"OSSE", LNL_PMC_LTR_OSSE},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
{}
};
static const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
{"PMC_PGD0_PG_STS", BIT(0), 0},
{"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
{"ESPISPI_PGD0_PG_STS", BIT(2), 0},
{"XHCI_PGD0_PG_STS", BIT(3), 1},
{"SPA_PGD0_PG_STS", BIT(4), 1},
{"SPB_PGD0_PG_STS", BIT(5), 1},
{"SPR16B0_PGD0_PG_STS", BIT(6), 0},
{"GBE_PGD0_PG_STS", BIT(7), 1},
{"SBR8B7_PGD0_PG_STS", BIT(8), 0},
{"SBR8B6_PGD0_PG_STS", BIT(9), 0},
{"SBR16B1_PGD0_PG_STS", BIT(10), 0},
{"SBR8B8_PGD0_PG_STS", BIT(11), 0},
{"ESE_PGD3_PG_STS", BIT(12), 1},
{"D2D_DISP_PGD0_PG_STS", BIT(13), 1},
{"LPSS_PGD0_PG_STS", BIT(14), 1},
{"LPC_PGD0_PG_STS", BIT(15), 0},
{"SMB_PGD0_PG_STS", BIT(16), 0},
{"ISH_PGD0_PG_STS", BIT(17), 0},
{"SBR8B2_PGD0_PG_STS", BIT(18), 0},
{"NPK_PGD0_PG_STS", BIT(19), 0},
{"D2D_NOC_PGD0_PG_STS", BIT(20), 0},
{"SAFSS_PGD0_PG_STS", BIT(21), 0},
{"FUSE_PGD0_PG_STS", BIT(22), 0},
{"D2D_DISP_PGD1_PG_STS", BIT(23), 1},
{"MPFPW1_PGD0_PG_STS", BIT(24), 0},
{"XDCI_PGD0_PG_STS", BIT(25), 1},
{"EXI_PGD0_PG_STS", BIT(26), 0},
{"CSE_PGD0_PG_STS", BIT(27), 1},
{"KVMCC_PGD0_PG_STS", BIT(28), 1},
{"PMT_PGD0_PG_STS", BIT(29), 1},
{"CLINK_PGD0_PG_STS", BIT(30), 1},
{"PTIO_PGD0_PG_STS", BIT(31), 1},
{}
};
static const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
{"USBR0_PGD0_PG_STS", BIT(0), 1},
{"SUSRAM_PGD0_PG_STS", BIT(1), 1},
{"SMT1_PGD0_PG_STS", BIT(2), 1},
{"U3FPW1_PGD0_PG_STS", BIT(3), 0},
{"SMS2_PGD0_PG_STS", BIT(4), 1},
{"SMS1_PGD0_PG_STS", BIT(5), 1},
{"CSMERTC_PGD0_PG_STS", BIT(6), 0},
{"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
{"FIA_PG_PGD0_PG_STS", BIT(8), 0},
{"SBR16B4_PGD0_PG_STS", BIT(9), 0},
{"P2SB8B_PGD0_PG_STS", BIT(10), 1},
{"DBG_SBR_PGD0_PG_STS", BIT(11), 0},
{"SBR8B9_PGD0_PG_STS", BIT(12), 0},
{"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
{"SBR8B10_PGD0_PG_STS", BIT(14), 0},
{"SBR16B3_PGD0_PG_STS", BIT(15), 0},
{"G5FPW1_PGD0_PG_STS", BIT(16), 0},
{"SBRG_PGD0_PG_STS", BIT(17), 0},
{"PSF4_PGD0_PG_STS", BIT(18), 0},
{"CNVI_PGD0_PG_STS", BIT(19), 0},
{"USFX2_PGD0_PG_STS", BIT(20), 1},
{"ENDBG_PGD0_PG_STS", BIT(21), 0},
{"FIACPCB_P5X4_PGD0_PG_STS", BIT(22), 0},
{"SBR8B3_PGD0_PG_STS", BIT(23), 0},
{"SBR8B0_PGD0_PG_STS", BIT(24), 0},
{"NPK_PGD1_PG_STS", BIT(25), 0},
{"OSSE_HOTHAM_PGD0_PG_STS", BIT(26), 1},
{"D2D_NOC_PGD2_PG_STS", BIT(27), 1},
{"SBR8B1_PGD0_PG_STS", BIT(28), 0},
{"PSF6_PGD0_PG_STS", BIT(29), 0},
{"PSF7_PGD0_PG_STS", BIT(30), 0},
{"FIA_U_PGD0_PG_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
{"PSF8_PGD0_PG_STS", BIT(0), 0},
{"SBR16B2_PGD0_PG_STS", BIT(1), 0},
{"D2D_IPU_PGD0_PG_STS", BIT(2), 1},
{"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
{"TAM_PGD0_PG_STS", BIT(4), 1},
{"D2D_NOC_PGD1_PG_STS", BIT(5), 1},
{"TBTLSX_PGD0_PG_STS", BIT(6), 1},
{"THC0_PGD0_PG_STS", BIT(7), 1},
{"THC1_PGD0_PG_STS", BIT(8), 1},
{"PMC_PGD0_PG_STS", BIT(9), 0},
{"SBR8B5_PGD0_PG_STS", BIT(10), 0},
{"UFSPW1_PGD0_PG_STS", BIT(11), 0},
{"DBC_PGD0_PG_STS", BIT(12), 0},
{"TCSS_PGD0_PG_STS", BIT(13), 0},
{"FIA_P5X4_PGD0_PG_STS", BIT(14), 0},
{"DISP_PGA_PGD0_PG_STS", BIT(15), 0},
{"DISP_PSF_PGD0_PG_STS", BIT(16), 0},
{"PSF0_PGD0_PG_STS", BIT(17), 0},
{"P2SB16B_PGD0_PG_STS", BIT(18), 1},
{"ACE_PGD0_PG_STS", BIT(19), 0},
{"ACE_PGD1_PG_STS", BIT(20), 0},
{"ACE_PGD2_PG_STS", BIT(21), 0},
{"ACE_PGD3_PG_STS", BIT(22), 0},
{"ACE_PGD4_PG_STS", BIT(23), 0},
{"ACE_PGD5_PG_STS", BIT(24), 0},
{"ACE_PGD6_PG_STS", BIT(25), 0},
{"ACE_PGD7_PG_STS", BIT(26), 0},
{"ACE_PGD8_PG_STS", BIT(27), 0},
{"ACE_PGD9_PG_STS", BIT(28), 0},
{"ACE_PGD10_PG_STS", BIT(29), 0},
{"FIACPCB_PG_PGD0_PG_STS", BIT(30), 0},
{"OSSE_PGD0_PG_STS", BIT(31), 1},
{}
};
static const struct pmc_bit_map lnl_d3_status_0_map[] = {
{"LPSS_D3_STS", BIT(3), 1},
{"XDCI_D3_STS", BIT(4), 1},
{"XHCI_D3_STS", BIT(5), 1},
{"SPA_D3_STS", BIT(12), 0},
{"SPB_D3_STS", BIT(13), 0},
{"OSSE_D3_STS", BIT(15), 0},
{"ESPISPI_D3_STS", BIT(18), 0},
{"PSTH_D3_STS", BIT(21), 0},
{}
};
static const struct pmc_bit_map lnl_d3_status_1_map[] = {
{"OSSE_SMT1_D3_STS", BIT(7), 0},
{"GBE_D3_STS", BIT(19), 0},
{"ITSS_D3_STS", BIT(23), 0},
{"CNVI_D3_STS", BIT(27), 0},
{"UFSX2_D3_STS", BIT(28), 1},
{"OSSE_HOTHAM_D3_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map lnl_d3_status_2_map[] = {
{"ESE_D3_STS", BIT(0), 0},
{"CSMERTC_D3_STS", BIT(1), 0},
{"SUSRAM_D3_STS", BIT(2), 0},
{"CSE_D3_STS", BIT(4), 0},
{"KVMCC_D3_STS", BIT(5), 0},
{"USBR0_D3_STS", BIT(6), 0},
{"ISH_D3_STS", BIT(7), 0},
{"SMT1_D3_STS", BIT(8), 0},
{"SMT2_D3_STS", BIT(9), 0},
{"SMT3_D3_STS", BIT(10), 0},
{"OSSE_SMT2_D3_STS", BIT(13), 0},
{"CLINK_D3_STS", BIT(14), 0},
{"PTIO_D3_STS", BIT(16), 0},
{"PMT_D3_STS", BIT(17), 0},
{"SMS1_D3_STS", BIT(18), 0},
{"SMS2_D3_STS", BIT(19), 0},
{}
};
static const struct pmc_bit_map lnl_d3_status_3_map[] = {
{"THC0_D3_STS", BIT(14), 1},
{"THC1_D3_STS", BIT(15), 1},
{"OSSE_SMT3_D3_STS", BIT(21), 0},
{"ACE_D3_STS", BIT(23), 0},
{}
};
static const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
{"LPSS_VNN_REQ_STS", BIT(3), 1},
{"OSSE_VNN_REQ_STS", BIT(15), 1},
{"ESPISPI_VNN_REQ_STS", BIT(18), 1},
{}
};
static const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
{"NPK_VNN_REQ_STS", BIT(4), 1},
{"OSSE_SMT1_VNN_REQ_STS", BIT(7), 1},
{"DFXAGG_VNN_REQ_STS", BIT(8), 0},
{"EXI_VNN_REQ_STS", BIT(9), 1},
{"P2D_VNN_REQ_STS", BIT(18), 1},
{"GBE_VNN_REQ_STS", BIT(19), 1},
{"SMB_VNN_REQ_STS", BIT(25), 1},
{"LPC_VNN_REQ_STS", BIT(26), 0},
{}
};
static const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
{"eSE_VNN_REQ_STS", BIT(0), 1},
{"CSMERTC_VNN_REQ_STS", BIT(1), 1},
{"CSE_VNN_REQ_STS", BIT(4), 1},
{"ISH_VNN_REQ_STS", BIT(7), 1},
{"SMT1_VNN_REQ_STS", BIT(8), 1},
{"CLINK_VNN_REQ_STS", BIT(14), 1},
{"SMS1_VNN_REQ_STS", BIT(18), 1},
{"SMS2_VNN_REQ_STS", BIT(19), 1},
{"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
{"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
{"GPIOCOM2_VNN_REQ_STS", BIT(22), 0},
{"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
{"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
{}
};
static const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
{"DISP_SHIM_VNN_REQ_STS", BIT(2), 0},
{"DTS0_VNN_REQ_STS", BIT(7), 0},
{"GPIOCOM5_VNN_REQ_STS", BIT(11), 2},
{}
};
static const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS", BIT(0), 0},
{"TS_OFF_REQ_STS", BIT(1), 0},
{"PNDE_MET_REQ_STS", BIT(2), 1},
{"PCIE_DEEP_PM_REQ_STS", BIT(3), 0},
{"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4), 0},
{"NPK_VNNAON_REQ_STS", BIT(5), 0},
{"VNN_SOC_REQ_STS", BIT(6), 1},
{"ISH_VNNAON_REQ_STS", BIT(7), 0},
{"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
{"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10), 1},
{"PLT_GREATER_REQ_STS", BIT(11), 1},
{"PCIE_CLKREQ_REQ_STS", BIT(12), 0},
{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
{"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
{"EA_REQ_STS", BIT(15), 0},
{"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
{"BRK_EV_EN_REQ_STS", BIT(17), 0},
{"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
{"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
{"LPC_CLK_SRC_REQ_STS", BIT(20), 0},
{"ARC_IDLE_REQ_STS", BIT(21), 0},
{"MPHY_SUS_REQ_STS", BIT(22), 0},
{"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
{"UXD_CONNECTED_REQ_STS", BIT(24), 1},
{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
{"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
{"PRE_WAKE0_REQ_STS", BIT(27), 1},
{"PRE_WAKE1_REQ_STS", BIT(28), 1},
{"PRE_WAKE2_EN_REQ_STS", BIT(29), 1},
{"WOV_REQ_STS", BIT(30), 0},
{"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31), 1},
{}
};
static const struct pmc_bit_map lnl_clocksource_status_map[] = {
{"AON2_OFF_STS", BIT(0), 0},
{"AON3_OFF_STS", BIT(1), 1},
{"AON4_OFF_STS", BIT(2), 1},
{"AON5_OFF_STS", BIT(3), 1},
{"AON1_OFF_STS", BIT(4), 0},
{"MPFPW1_0_PLL_OFF_STS", BIT(6), 1},
{"USB3_PLL_OFF_STS", BIT(8), 1},
{"AON3_SPL_OFF_STS", BIT(9), 1},
{"G5FPW1_PLL_OFF_STS", BIT(15), 1},
{"XTAL_AGGR_OFF_STS", BIT(17), 1},
{"USB2_PLL_OFF_STS", BIT(18), 0},
{"SAF_PLL_OFF_STS", BIT(19), 1},
{"SE_TCSS_PLL_OFF_STS", BIT(20), 1},
{"DDI_PLL_OFF_STS", BIT(21), 1},
{"FILTER_PLL_OFF_STS", BIT(22), 1},
{"ACE_PLL_OFF_STS", BIT(24), 0},
{"FABRIC_PLL_OFF_STS", BIT(25), 1},
{"SOC_PLL_OFF_STS", BIT(26), 1},
{"REF_OFF_STS", BIT(28), 1},
{"IMG_OFF_STS", BIT(29), 1},
{"RTC_PLL_OFF_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map lnl_signal_status_map[] = {
{"LSX_Wake0_STS", BIT(0), 0},
{"LSX_Wake1_STS", BIT(1), 0},
{"LSX_Wake2_STS", BIT(2), 0},
{"LSX_Wake3_STS", BIT(3), 0},
{"LSX_Wake4_STS", BIT(4), 0},
{"LSX_Wake5_STS", BIT(5), 0},
{"LSX_Wake6_STS", BIT(6), 0},
{"LSX_Wake7_STS", BIT(7), 0},
{"LPSS_Wake0_STS", BIT(8), 1},
{"LPSS_Wake1_STS", BIT(9), 1},
{"Int_Timer_SS_Wake0_STS", BIT(10), 1},
{"Int_Timer_SS_Wake1_STS", BIT(11), 1},
{"Int_Timer_SS_Wake2_STS", BIT(12), 1},
{"Int_Timer_SS_Wake3_STS", BIT(13), 1},
{"Int_Timer_SS_Wake4_STS", BIT(14), 1},
{"Int_Timer_SS_Wake5_STS", BIT(15), 1},
{}
};
static const struct pmc_bit_map lnl_rsc_status_map[] = {
{"Memory", 0, 1},
{"PSF0", 0, 1},
{"PSF4", 0, 1},
{"PSF6", 0, 1},
{"PSF7", 0, 1},
{"PSF8", 0, 1},
{"SAF_CFI_LINK", 0, 1},
{"SBR", 0, 1},
{}
};
static const struct pmc_bit_map *lnl_lpm_maps[] = {
lnl_clocksource_status_map,
lnl_power_gating_status_0_map,
lnl_power_gating_status_1_map,
lnl_power_gating_status_2_map,
lnl_d3_status_0_map,
lnl_d3_status_1_map,
lnl_d3_status_2_map,
lnl_d3_status_3_map,
lnl_vnn_req_status_0_map,
lnl_vnn_req_status_1_map,
lnl_vnn_req_status_2_map,
lnl_vnn_req_status_3_map,
lnl_vnn_misc_status_map,
lnl_signal_status_map,
NULL
};
static const struct pmc_bit_map *lnl_blk_maps[] = {
lnl_power_gating_status_0_map,
lnl_power_gating_status_1_map,
lnl_power_gating_status_2_map,
lnl_rsc_status_map,
lnl_vnn_req_status_0_map,
lnl_vnn_req_status_1_map,
lnl_vnn_req_status_2_map,
lnl_vnn_req_status_3_map,
lnl_d3_status_0_map,
lnl_d3_status_1_map,
lnl_d3_status_2_map,
lnl_d3_status_3_map,
lnl_clocksource_status_map,
lnl_vnn_misc_status_map,
lnl_signal_status_map,
NULL
};
static const struct pmc_bit_map lnl_pfear_map[] = {
{"PMC_0", BIT(0)},
{"FUSE_OSSE", BIT(1)},
{"ESPISPI", BIT(2)},
{"XHCI", BIT(3)},
{"SPA", BIT(4)},
{"SPB", BIT(5)},
{"SBR16B0", BIT(6)},
{"GBE", BIT(7)},
{"SBR8B7", BIT(0)},
{"SBR8B6", BIT(1)},
{"SBR16B1", BIT(1)},
{"SBR8B8", BIT(2)},
{"ESE", BIT(3)},
{"SBR8B10", BIT(4)},
{"D2D_DISP_0", BIT(5)},
{"LPSS", BIT(6)},
{"LPC", BIT(7)},
{"SMB", BIT(0)},
{"ISH", BIT(1)},
{"SBR8B2", BIT(2)},
{"NPK_0", BIT(3)},
{"D2D_NOC_0", BIT(4)},
{"SAFSS", BIT(5)},
{"FUSE", BIT(6)},
{"D2D_DISP_1", BIT(7)},
{"MPFPW1", BIT(0)},
{"XDCI", BIT(1)},
{"EXI", BIT(2)},
{"CSE", BIT(3)},
{"KVMCC", BIT(4)},
{"PMT", BIT(5)},
{"CLINK", BIT(6)},
{"PTIO", BIT(7)},
{"USBR", BIT(0)},
{"SUSRAM", BIT(1)},
{"SMT1", BIT(2)},
{"U3FPW1", BIT(3)},
{"SMS2", BIT(4)},
{"SMS1", BIT(5)},
{"CSMERTC", BIT(6)},
{"CSMEPSF", BIT(7)},
{"FIA_PG", BIT(0)},
{"SBR16B4", BIT(1)},
{"P2SB8B", BIT(2)},
{"DBG_SBR", BIT(3)},
{"SBR8B9", BIT(4)},
{"OSSE_SMT1", BIT(5)},
{"SBR8B10", BIT(6)},
{"SBR16B3", BIT(7)},
{"G5FPW1", BIT(0)},
{"SBRG", BIT(1)},
{"PSF4", BIT(2)},
{"CNVI", BIT(3)},
{"UFSX2", BIT(4)},
{"ENDBG", BIT(5)},
{"FIACPCB_P5X4", BIT(6)},
{"SBR8B3", BIT(7)},
{"SBR8B0", BIT(0)},
{"NPK_1", BIT(1)},
{"OSSE_HOTHAM", BIT(2)},
{"D2D_NOC_2", BIT(3)},
{"SBR8B1", BIT(4)},
{"PSF6", BIT(5)},
{"PSF7", BIT(6)},
{"FIA_U", BIT(7)},
{"PSF8", BIT(0)},
{"SBR16B2", BIT(1)},
{"D2D_IPU", BIT(2)},
{"FIACPCB_U", BIT(3)},
{"TAM", BIT(4)},
{"D2D_NOC_1", BIT(5)},
{"TBTLSX", BIT(6)},
{"THC0", BIT(7)},
{"THC1", BIT(0)},
{"PMC_1", BIT(1)},
{"SBR8B5", BIT(2)},
{"UFSPW1", BIT(3)},
{"DBC", BIT(4)},
{"TCSS", BIT(5)},
{"FIA_P5X4", BIT(6)},
{"DISP_PGA", BIT(7)},
{"DBG_PSF", BIT(0)},
{"PSF0", BIT(1)},
{"P2SB16B", BIT(2)},
{"ACE0", BIT(3)},
{"ACE1", BIT(4)},
{"ACE2", BIT(5)},
{"ACE3", BIT(6)},
{"ACE4", BIT(7)},
{"ACE5", BIT(0)},
{"ACE6", BIT(1)},
{"ACE7", BIT(2)},
{"ACE8", BIT(3)},
{"ACE9", BIT(4)},
{"ACE10", BIT(5)},
{"FIACPCB", BIT(6)},
{"OSSE", BIT(7)},
{}
};
static const struct pmc_bit_map *ext_lnl_pfear_map[] = {
lnl_pfear_map,
NULL
};
static const struct pmc_reg_map lnl_socm_reg_map = {
.pfear_sts = ext_lnl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = lnl_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = LNL_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
.lpm_num_maps = ADL_LPM_NUM_MAPS,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.etr3_offset = ETR3_OFFSET,
.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
.lpm_en_offset = MTL_LPM_EN_OFFSET,
.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
.lpm_sts = lnl_lpm_maps,
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.s0ix_blocker_maps = lnl_blk_maps,
.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
.lpm_reg_index = LNL_LPM_REG_INDEX,
.lpm_req_guid = SOCM_LPM_REQ_GUID,
};
static struct pmc_info lnl_pmc_info_list[] = {
{
.devid = PMC_DEVID_LNL_SOCM,
.map = &lnl_socm_reg_map,
},
{}
};
static const u8 lnl_pmc_list[] = {PMC_IDX_MAIN};
#define LNL_NPU_PCI_DEV 0x643e
#define LNL_IPU_PCI_DEV 0x645d
/*
* Set power state of select devices that do not have drivers to D3
* so that they do not block Package C entry.
*/
static void lnl_d3_fixup(void)
{
pmc_core_set_device_d3(LNL_IPU_PCI_DEV);
pmc_core_set_device_d3(LNL_NPU_PCI_DEV);
}
static int lnl_resume(struct pmc_dev *pmcdev)
{
lnl_d3_fixup();
return cnl_resume(pmcdev);
}
static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
lnl_d3_fixup();
return generic_core_init(pmcdev, pmc_dev_info);
}
struct pmc_dev_info lnl_pmc_dev = {
.num_pmcs = ARRAY_SIZE(lnl_pmc_list),
.pmc_list = lnl_pmc_list,
.regmap_list = lnl_pmc_info_list,
.map = &lnl_socm_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
.suspend = cnl_suspend,
.resume = lnl_resume,
.init = lnl_core_init,
.sub_req = pmc_core_pmt_get_lpm_req,
.ssram_hidden = true,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/mtl.c
+1011
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/platform/x86/intel/pmc/nvl.c
+1539
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/platform/x86/intel/pmc/pltdrv.c
+90
View File
@@ -0,0 +1,90 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel PMC Core platform init
* Copyright (c) 2019, Google Inc.
* Author - Rajat Jain
*
* This code instantiates platform devices for intel_pmc_core driver, only
* on supported platforms that may not have the ACPI devices in the ACPI tables.
* No new platforms should be added here, because we expect that new platforms
* should all have the ACPI device, which is the preferred way of enumeration.
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <xen/xen.h>
static void intel_pmc_core_release(struct device *dev)
{
kfree(dev);
}
static struct platform_device *pmc_core_device;
/*
* intel_pmc_core_platform_ids is the list of platforms where we want to
* instantiate the platform_device if not already instantiated. This is
* different than intel_pmc_core_ids in intel_pmc_core.c which is the
* list of platforms that the driver supports for pmc_core device. The
* other list may grow, but this list should not.
*/
static const struct x86_cpu_id intel_pmc_core_platform_ids[] = {
X86_MATCH_VFM(INTEL_SKYLAKE_L, &pmc_core_device),
X86_MATCH_VFM(INTEL_SKYLAKE, &pmc_core_device),
X86_MATCH_VFM(INTEL_KABYLAKE_L, &pmc_core_device),
X86_MATCH_VFM(INTEL_KABYLAKE, &pmc_core_device),
X86_MATCH_VFM(INTEL_CANNONLAKE_L, &pmc_core_device),
X86_MATCH_VFM(INTEL_ICELAKE_L, &pmc_core_device),
X86_MATCH_VFM(INTEL_COMETLAKE, &pmc_core_device),
X86_MATCH_VFM(INTEL_COMETLAKE_L, &pmc_core_device),
{}
};
MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_platform_ids);
static int __init pmc_core_platform_init(void)
{
int retval;
/* Skip creating the platform device if ACPI already has a device */
if (acpi_dev_present("INT33A1", NULL, -1))
return -ENODEV;
/*
* Skip forcefully attaching the device for VMs. Make an exception for
* Xen dom0, which does have full hardware access.
*/
if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR) && !xen_initial_domain())
return -ENODEV;
if (!x86_match_cpu(intel_pmc_core_platform_ids))
return -ENODEV;
pmc_core_device = kzalloc_obj(*pmc_core_device);
if (!pmc_core_device)
return -ENOMEM;
pmc_core_device->name = "intel_pmc_core";
pmc_core_device->dev.release = intel_pmc_core_release;
retval = platform_device_register(pmc_core_device);
if (retval)
platform_device_put(pmc_core_device);
return retval;
}
static void __exit pmc_core_platform_exit(void)
{
platform_device_unregister(pmc_core_device);
}
module_init(pmc_core_platform_init);
module_exit(pmc_core_platform_exit);
MODULE_DESCRIPTION("Intel PMC Core platform driver");
MODULE_LICENSE("GPL v2");
linux-7.2.3/drivers/platform/x86/intel/pmc/ptl.c
+584
View File
@@ -0,0 +1,584 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Panther Lake PCH.
*
* Copyright (c) 2025, Intel Corporation.
*/
#include <linux/pci.h>
#include "core.h"
/* PMC SSRAM PMT Telemetry GUIDS */
#define PCDP_LPM_REQ_GUID 0x47179370
/*
* Die Mapping to Product.
* Product PCDDie
* PTL-H PCD-H
* PTL-P PCD-P
* PTL-U PCD-P
*/
static const struct pmc_bit_map ptl_pcdp_pfear_map[] = {
{"PMC_0", BIT(0)},
{"FUSE_OSSE", BIT(1)},
{"ESPISPI", BIT(2)},
{"XHCI", BIT(3)},
{"SPA", BIT(4)},
{"SPB", BIT(5)},
{"MPFPW2", BIT(6)},
{"GBE", BIT(7)},
{"SBR16B20", BIT(0)},
{"SBR8B20", BIT(1)},
{"SBR16B21", BIT(2)},
{"DBG_SBR16B", BIT(3)},
{"OSSE_HOTHAM", BIT(4)},
{"D2D_DISP_1", BIT(5)},
{"LPSS", BIT(6)},
{"LPC", BIT(7)},
{"SMB", BIT(0)},
{"ISH", BIT(1)},
{"SBR16B2", BIT(2)},
{"NPK_0", BIT(3)},
{"D2D_NOC_1", BIT(4)},
{"SBR8B2", BIT(5)},
{"FUSE", BIT(6)},
{"SBR16B0", BIT(7)},
{"PSF0", BIT(0)},
{"XDCI", BIT(1)},
{"EXI", BIT(2)},
{"CSE", BIT(3)},
{"KVMCC", BIT(4)},
{"PMT", BIT(5)},
{"CLINK", BIT(6)},
{"PTIO", BIT(7)},
{"USBR0", BIT(0)},
{"SUSRAM", BIT(1)},
{"SMT1", BIT(2)},
{"MPFPW1", BIT(3)},
{"SMS2", BIT(4)},
{"SMS1", BIT(5)},
{"CSMERTC", BIT(6)},
{"CSMEPSF", BIT(7)},
{"D2D_NOC_0", BIT(0)},
{"ESE", BIT(1)},
{"P2SB8B", BIT(2)},
{"SBR16B7", BIT(3)},
{"SBR16B3", BIT(4)},
{"OSSE_SMT1", BIT(5)},
{"D2D_DISP", BIT(6)},
{"DBG_SBR", BIT(7)},
{"U3FPW1", BIT(0)},
{"FIA_X", BIT(1)},
{"PSF4", BIT(2)},
{"CNVI", BIT(3)},
{"UFSX2", BIT(4)},
{"ENDBG", BIT(5)},
{"DBC", BIT(6)},
{"FIA_PG", BIT(7)},
{"D2D_IPU", BIT(0)},
{"NPK1", BIT(1)},
{"FIACPCB_X", BIT(2)},
{"SBR8B4", BIT(3)},
{"DBG_PSF", BIT(4)},
{"PSF6", BIT(5)},
{"UFSPW1", BIT(6)},
{"FIA_U", BIT(7)},
{"PSF8", BIT(0)},
{"SBR16B4", BIT(1)},
{"SBR16B5", BIT(2)},
{"FIACPCB_U", BIT(3)},
{"TAM", BIT(4)},
{"D2D_NOC_2", BIT(5)},
{"TBTLSX", BIT(6)},
{"THC0", BIT(7)},
{"THC1", BIT(0)},
{"PMC_1", BIT(1)},
{"SBR8B1", BIT(2)},
{"TCSS", BIT(3)},
{"DISP_PGA", BIT(4)},
{"SBR16B1", BIT(5)},
{"SBRG", BIT(6)},
{"PSF5", BIT(7)},
{"P2SB16B", BIT(0)},
{"ACE_0", BIT(1)},
{"ACE_1", BIT(2)},
{"ACE_2", BIT(3)},
{"ACE_3", BIT(4)},
{"ACE_4", BIT(5)},
{"ACE_5", BIT(6)},
{"ACE_6", BIT(7)},
{"ACE_7", BIT(0)},
{"ACE_8", BIT(1)},
{"ACE_9", BIT(2)},
{"ACE_10", BIT(3)},
{"FIACPCB_PG", BIT(4)},
{"SBR16B6", BIT(5)},
{"OSSE", BIT(6)},
{"SBR8B0", BIT(7)},
{}
};
static const struct pmc_bit_map *ext_ptl_pcdp_pfear_map[] = {
ptl_pcdp_pfear_map,
NULL
};
const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
{"ME", CNP_PMC_LTR_ME},
{"SATA1", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"SATA2", PTL_PMC_LTR_SATA2},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
{"SOUTHPORT_G", MTL_PMC_LTR_SPG},
{"ESE", MTL_PMC_LTR_ESE},
{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
{"DMI3", ARL_PMC_LTR_DMI3},
{"OSSE", LNL_PMC_LTR_OSSE},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT},
{}
};
const struct pmc_bit_map ptl_pcdp_clocksource_status_map[] = {
{"AON2_OFF_STS", BIT(0), 1},
{"AON3_OFF_STS", BIT(1), 0},
{"AON4_OFF_STS", BIT(2), 1},
{"AON5_OFF_STS", BIT(3), 1},
{"AON1_OFF_STS", BIT(4), 0},
{"XTAL_LVM_OFF_STS", BIT(5), 0},
{"MPFPW1_0_PLL_OFF_STS", BIT(6), 1},
{"USB3_PLL_OFF_STS", BIT(8), 1},
{"AON3_SPL_OFF_STS", BIT(9), 1},
{"MPFPW2_0_PLL_OFF_STS", BIT(12), 1},
{"XTAL_AGGR_OFF_STS", BIT(17), 1},
{"USB2_PLL_OFF_STS", BIT(18), 0},
{"SAF_PLL_OFF_STS", BIT(19), 1},
{"SE_TCSS_PLL_OFF_STS", BIT(20), 1},
{"DDI_PLL_OFF_STS", BIT(21), 1},
{"FILTER_PLL_OFF_STS", BIT(22), 1},
{"ACE_PLL_OFF_STS", BIT(24), 0},
{"FABRIC_PLL_OFF_STS", BIT(25), 1},
{"SOC_PLL_OFF_STS", BIT(26), 1},
{"REF_PLL_OFF_STS", BIT(28), 1},
{"IMG_PLL_OFF_STS", BIT(29), 1},
{"RTC_PLL_OFF_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_power_gating_status_0_map[] = {
{"PMC_PGD0_PG_STS", BIT(0), 0},
{"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
{"ESPISPI_PGD0_PG_STS", BIT(2), 0},
{"XHCI_PGD0_PG_STS", BIT(3), 1},
{"SPA_PGD0_PG_STS", BIT(4), 1},
{"SPB_PGD0_PG_STS", BIT(5), 1},
{"MPFPW2_PGD0_PG_STS", BIT(6), 0},
{"GBE_PGD0_PG_STS", BIT(7), 1},
{"SBR16B20_PGD0_PG_STS", BIT(8), 0},
{"SBR8B20_PGD0_PG_STS", BIT(9), 0},
{"SBR16B21_PGD0_PG_STS", BIT(10), 0},
{"DBG_PGD0_PG_STS", BIT(11), 0},
{"OSSE_HOTHAM_PGD0_PG_STS", BIT(12), 1},
{"D2D_DISP_PGD1_PG_STS", BIT(13), 1},
{"LPSS_PGD0_PG_STS", BIT(14), 1},
{"LPC_PGD0_PG_STS", BIT(15), 0},
{"SMB_PGD0_PG_STS", BIT(16), 0},
{"ISH_PGD0_PG_STS", BIT(17), 0},
{"SBR16B2_PGD0_PG_STS", BIT(18), 0},
{"NPK_PGD0_PG_STS", BIT(19), 0},
{"D2D_NOC_PGD1_PG_STS", BIT(20), 1},
{"SBR8B2_PGD0_PG_STS", BIT(21), 0},
{"FUSE_PGD0_PG_STS", BIT(22), 0},
{"SBR16B0_PGD0_PG_STS", BIT(23), 0},
{"PSF0_PGD0_PG_STS", BIT(24), 0},
{"XDCI_PGD0_PG_STS", BIT(25), 1},
{"EXI_PGD0_PG_STS", BIT(26), 0},
{"CSE_PGD0_PG_STS", BIT(27), 1},
{"KVMCC_PGD0_PG_STS", BIT(28), 1},
{"PMT_PGD0_PG_STS", BIT(29), 1},
{"CLINK_PGD0_PG_STS", BIT(30), 1},
{"PTIO_PGD0_PG_STS", BIT(31), 1},
{}
};
static const struct pmc_bit_map ptl_pcdp_power_gating_status_1_map[] = {
{"USBR0_PGD0_PG_STS", BIT(0), 1},
{"SUSRAM_PGD0_PG_STS", BIT(1), 1},
{"SMT1_PGD0_PG_STS", BIT(2), 1},
{"MPFPW1_PGD0_PG_STS", BIT(3), 0},
{"SMS2_PGD0_PG_STS", BIT(4), 1},
{"SMS1_PGD0_PG_STS", BIT(5), 1},
{"CSMERTC_PGD0_PG_STS", BIT(6), 0},
{"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
{"D2D_NOC_PGD0_PG_STS", BIT(8), 0},
{"ESE_PGD0_PG_STS", BIT(9), 1},
{"P2SB8B_PGD0_PG_STS", BIT(10), 1},
{"SBR16B7_PGD0_PG_STS", BIT(11), 0},
{"SBR16B3_PGD0_PG_STS", BIT(12), 0},
{"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
{"D2D_DISP_PGD0_PG_STS", BIT(14), 1},
{"DBG_SBR_PGD0_PG_STS", BIT(15), 0},
{"U3FPW1_PGD0_PG_STS", BIT(16), 0},
{"FIA_X_PGD0_PG_STS", BIT(17), 0},
{"PSF4_PGD0_PG_STS", BIT(18), 0},
{"CNVI_PGD0_PG_STS", BIT(19), 0},
{"UFSX2_PGD0_PG_STS", BIT(20), 1},
{"ENDBG_PGD0_PG_STS", BIT(21), 0},
{"DBC_PGD0_PG_STS", BIT(22), 0},
{"FIA_PG_PGD0_PG_STS", BIT(23), 0},
{"D2D_IPU_PGD0_PG_STS", BIT(24), 1},
{"NPK_PGD1_PG_STS", BIT(25), 0},
{"FIACPCB_X_PGD0_PG_STS", BIT(26), 0},
{"SBR8B4_PGD0_PG_STS", BIT(27), 0},
{"DBG_PSF_PGD0_PG_STS", BIT(28), 0},
{"PSF6_PGD0_PG_STS", BIT(29), 0},
{"UFSPW1_PGD0_PG_STS", BIT(30), 0},
{"FIA_U_PGD0_PG_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_power_gating_status_2_map[] = {
{"PSF8_PGD0_PG_STS", BIT(0), 0},
{"SBR16B4_PGD0_PG_STS", BIT(1), 0},
{"SBR16B5_PGD0_PG_STS", BIT(2), 0},
{"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
{"TAM_PGD0_PG_STS", BIT(4), 1},
{"D2D_NOC_PGD0_PG_STS", BIT(5), 1},
{"TBTLSX_PGD0_PG_STS", BIT(6), 1},
{"THC0_PGD0_PG_STS", BIT(7), 1},
{"THC1_PGD0_PG_STS", BIT(8), 1},
{"PMC_PGD1_PG_STS", BIT(9), 0},
{"SBR8B1_PGD0_PG_STS", BIT(10), 0},
{"TCSS_PGD0_PG_STS", BIT(11), 0},
{"DISP_PGA_PGD0_PG_STS", BIT(12), 0},
{"SBR16B1_PGD0_PG_STS", BIT(13), 0},
{"SBRG_PGD0_PG_STS", BIT(14), 0},
{"PSF5_PGD0_PG_STS", BIT(15), 0},
{"P2SB16B_PGD0_PG_STS", BIT(16), 1},
{"ACE_PGD0_PG_STS", BIT(17), 0},
{"ACE_PGD1_PG_STS", BIT(18), 0},
{"ACE_PGD2_PG_STS", BIT(19), 0},
{"ACE_PGD3_PG_STS", BIT(20), 0},
{"ACE_PGD4_PG_STS", BIT(21), 0},
{"ACE_PGD5_PG_STS", BIT(22), 0},
{"ACE_PGD6_PG_STS", BIT(23), 0},
{"ACE_PGD7_PG_STS", BIT(24), 0},
{"ACE_PGD8_PG_STS", BIT(25), 0},
{"ACE_PGD9_PG_STS", BIT(26), 0},
{"ACE_PGD10_PG_STS", BIT(27), 0},
{"FIACPCB_PG_PGD0_PG_STS", BIT(28), 0},
{"SBR16B6_PGD0_PG_STS", BIT(29), 0},
{"OSSE_PGD0_PG_STS", BIT(30), 1},
{"SBR8B0_PGD0_PG_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_d3_status_0_map[] = {
{"LPSS_D3_STS", BIT(3), 1},
{"XDCI_D3_STS", BIT(4), 1},
{"XHCI_D3_STS", BIT(5), 1},
{"OSSE_D3_STS", BIT(6), 0},
{"SPA_D3_STS", BIT(12), 0},
{"SPB_D3_STS", BIT(13), 0},
{"ESPISPI_D3_STS", BIT(18), 0},
{"PSTH_D3_STS", BIT(21), 0},
{"OSSE_SMT1_D3_STS", BIT(30), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_d3_status_1_map[] = {
{"GBE_D3_STS", BIT(19), 0},
{"ITSS_D3_STS", BIT(23), 0},
{"CNVI_D3_STS", BIT(27), 0},
{"UFSX2_D3_STS", BIT(28), 1},
{"OSSE_HOTHAM_D3_STS", BIT(29), 0},
{"ESE_D3_STS", BIT(30), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_d3_status_2_map[] = {
{"CSMERTC_D3_STS", BIT(1), 0},
{"SUSRAM_D3_STS", BIT(2), 0},
{"CSE_D3_STS", BIT(4), 0},
{"KVMCC_D3_STS", BIT(5), 0},
{"USBR0_D3_STS", BIT(6), 0},
{"ISH_D3_STS", BIT(7), 0},
{"SMT1_D3_STS", BIT(8), 0},
{"SMT2_D3_STS", BIT(9), 0},
{"SMT3_D3_STS", BIT(10), 0},
{"OSSE_SMT2_D3_STS", BIT(12), 0},
{"CLINK_D3_STS", BIT(14), 0},
{"PTIO_D3_STS", BIT(16), 0},
{"PMT_D3_STS", BIT(17), 0},
{"SMS1_D3_STS", BIT(18), 0},
{"SMS2_D3_STS", BIT(19), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_d3_status_3_map[] = {
{"THC0_D3_STS", BIT(14), 1},
{"THC1_D3_STS", BIT(15), 1},
{"OSSE_SMT3_D3_STS", BIT(18), 0},
{"ACE_D3_STS", BIT(23), 0},
{}
};
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_0_map[] = {
{"LPSS_VNN_REQ_STS", BIT(3), 1},
{"OSSE_VNN_REQ_STS", BIT(6), 1},
{"ESPISPI_VNN_REQ_STS", BIT(18), 1},
{"OSSE_SMT1_VNN_REQ_STS", BIT(30), 1},
{}
};
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_1_map[] = {
{"NPK_VNN_REQ_STS", BIT(4), 1},
{"DFXAGG_VNN_REQ_STS", BIT(8), 0},
{"EXI_VNN_REQ_STS", BIT(9), 1},
{"P2D_VNN_REQ_STS", BIT(18), 1},
{"GBE_VNN_REQ_STS", BIT(19), 1},
{"SMB_VNN_REQ_STS", BIT(25), 1},
{"LPC_VNN_REQ_STS", BIT(26), 0},
{"ESE_VNN_REQ_STS", BIT(30), 1},
{}
};
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_2_map[] = {
{"CSMERTC_VNN_REQ_STS", BIT(1), 1},
{"CSE_VNN_REQ_STS", BIT(4), 1},
{"ISH_VNN_REQ_STS", BIT(7), 1},
{"SMT1_VNN_REQ_STS", BIT(8), 1},
{"CLINK_VNN_REQ_STS", BIT(14), 1},
{"SMS1_VNN_REQ_STS", BIT(18), 1},
{"SMS2_VNN_REQ_STS", BIT(19), 1},
{"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
{"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
{"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
{"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
{"DISP_SHIM_VNN_REQ_STS", BIT(26), 1},
{}
};
const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[] = {
{"DTS0_VNN_REQ_STS", BIT(7), 0},
{"GPIOCOM5_VNN_REQ_STS", BIT(11), 1},
{}
};
static const struct pmc_bit_map ptl_pcdp_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS", BIT(0), 0},
{"TS_OFF_REQ_STS", BIT(1), 0},
{"PNDE_MET_REQ_STS", BIT(2), 1},
{"PG5_PMA0_REQ_STS", BIT(3), 0},
{"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0},
{"VNN_SOC_REQ_STS", BIT(6), 1},
{"ISH_VNNAON_REQ_STS", BIT(7), 0},
{"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
{"D2D_IPU_QACTIVE_REQ_STS", BIT(10), 1},
{"PLT_GREATER_REQ_STS", BIT(11), 1},
{"ALL_SBR_IDLE_REQ_STS", BIT(12), 0},
{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
{"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
{"EA_REQ_STS", BIT(15), 0},
{"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
{"BRK_EV_EN_REQ_STS", BIT(17), 0},
{"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
{"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
{"ARC_IDLE_REQ_STS", BIT(21), 0},
{"PG5_PMA1_REQ_STS", BIT(22), 0},
{"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
{"XDCI_ATTACHED_REQ_STS", BIT(24), 1},
{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
{"PRE_WAKE0_REQ_STS", BIT(27), 1},
{"PRE_WAKE1_REQ_STS", BIT(28), 1},
{"PRE_WAKE2_REQ_STS", BIT(29), 1},
{"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1},
{}
};
const struct pmc_bit_map ptl_pcdp_signal_status_map[] = {
{"LSX_Wake0_STS", BIT(0), 0},
{"LSX_Wake1_STS", BIT(1), 0},
{"LSX_Wake2_STS", BIT(2), 0},
{"LSX_Wake3_STS", BIT(3), 0},
{"LSX_Wake4_STS", BIT(4), 0},
{"LSX_Wake5_STS", BIT(5), 0},
{"LSX_Wake6_STS", BIT(6), 0},
{"LSX_Wake7_STS", BIT(7), 0},
{"LPSS_Wake0_STS", BIT(8), 1},
{"LPSS_Wake1_STS", BIT(9), 1},
{"Int_Timer_SS_Wake0_STS", BIT(10), 1},
{"Int_Timer_SS_Wake1_STS", BIT(11), 1},
{"Int_Timer_SS_Wake2_STS", BIT(12), 1},
{"Int_Timer_SS_Wake3_STS", BIT(13), 1},
{"Int_Timer_SS_Wake4_STS", BIT(14), 1},
{"Int_Timer_SS_Wake5_STS", BIT(15), 1},
{}
};
static const struct pmc_bit_map ptl_pcdp_rsc_status_map[] = {
{"Memory", 0, 1},
{"PSF0", 0, 1},
{"PSF4", 0, 1},
{"PSF5", 0, 1},
{"PSF6", 0, 1},
{"PSF8", 0, 1},
{"SAF_CFI_LINK", 0, 1},
{"SB", 0, 1},
{}
};
static const struct pmc_bit_map *ptl_pcdp_lpm_maps[] = {
ptl_pcdp_clocksource_status_map,
ptl_pcdp_power_gating_status_0_map,
ptl_pcdp_power_gating_status_1_map,
ptl_pcdp_power_gating_status_2_map,
ptl_pcdp_d3_status_0_map,
ptl_pcdp_d3_status_1_map,
ptl_pcdp_d3_status_2_map,
ptl_pcdp_d3_status_3_map,
ptl_pcdp_vnn_req_status_0_map,
ptl_pcdp_vnn_req_status_1_map,
ptl_pcdp_vnn_req_status_2_map,
ptl_pcdp_vnn_req_status_3_map,
ptl_pcdp_vnn_misc_status_map,
ptl_pcdp_signal_status_map,
NULL
};
static const struct pmc_bit_map *ptl_pcdp_blk_maps[] = {
ptl_pcdp_power_gating_status_0_map,
ptl_pcdp_power_gating_status_1_map,
ptl_pcdp_power_gating_status_2_map,
ptl_pcdp_rsc_status_map,
ptl_pcdp_vnn_req_status_0_map,
ptl_pcdp_vnn_req_status_1_map,
ptl_pcdp_vnn_req_status_2_map,
ptl_pcdp_vnn_req_status_3_map,
ptl_pcdp_d3_status_0_map,
ptl_pcdp_d3_status_1_map,
ptl_pcdp_d3_status_2_map,
ptl_pcdp_d3_status_3_map,
ptl_pcdp_clocksource_status_map,
ptl_pcdp_vnn_misc_status_map,
ptl_pcdp_signal_status_map,
NULL
};
static const struct pmc_reg_map ptl_pcdp_reg_map = {
.pfear_sts = ext_ptl_pcdp_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = ptl_pcdp_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = PTL_PCD_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.lpm_num_maps = PTL_LPM_NUM_MAPS,
.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.etr3_offset = ETR3_OFFSET,
.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
.lpm_en_offset = MTL_LPM_EN_OFFSET,
.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
.lpm_sts = ptl_pcdp_lpm_maps,
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.s0ix_blocker_maps = ptl_pcdp_blk_maps,
.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
.num_s0ix_blocker = PTL_NUM_S0IX_BLOCKER,
.blocker_req_offset = PTL_BLK_REQ_OFFSET,
.lpm_req_guid = PCDP_LPM_REQ_GUID,
};
static struct pmc_info ptl_pmc_info_list[] = {
{
.devid = PMC_DEVID_PTL_PCDH,
.map = &ptl_pcdp_reg_map,
},
{
.devid = PMC_DEVID_PTL_PCDP,
.map = &ptl_pcdp_reg_map,
},
{}
};
static const u8 ptl_pmc_list[] = {PMC_IDX_MAIN};
#define PTL_NPU_PCI_DEV 0xb03e
#define PTL_IPU_PCI_DEV 0xb05d
/*
* Set power state of select devices that do not have drivers to D3
* so that they do not block Package C entry.
*/
static void ptl_d3_fixup(void)
{
pmc_core_set_device_d3(PTL_IPU_PCI_DEV);
pmc_core_set_device_d3(PTL_NPU_PCI_DEV);
}
static int ptl_resume(struct pmc_dev *pmcdev)
{
ptl_d3_fixup();
return cnl_resume(pmcdev);
}
static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
ptl_d3_fixup();
return generic_core_init(pmcdev, pmc_dev_info);
}
struct pmc_dev_info ptl_pmc_dev = {
.num_pmcs = ARRAY_SIZE(ptl_pmc_list),
.pmc_list = ptl_pmc_list,
.regmap_list = ptl_pmc_info_list,
.map = &ptl_pcdp_reg_map,
.sub_req_show = &pmc_core_substate_blk_req_fops,
.suspend = cnl_suspend,
.resume = ptl_resume,
.init = ptl_core_init,
.sub_req = pmc_core_pmt_get_blk_sub_req,
.ssram_hidden = true,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/pwrm_telemetry.c
+215
View File
@@ -0,0 +1,215 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel PMC PWRM ACPI driver
*
* Copyright (C) 2025, Intel Corporation
*/
#include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/intel_vsec.h>
#include <linux/limits.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/uuid.h>
#include "core.h"
#define ENTRY_LEN 5
/* DWORD2 */
#define DVSEC_ID_MASK GENMASK(15, 0)
#define NUM_ENTRIES_MASK GENMASK(23, 16)
#define ENTRY_SIZE_MASK GENMASK(31, 24)
/* DWORD3 */
#define TBIR_MASK GENMASK(2, 0)
#define DISC_TBL_OFF_MASK GENMASK(31, 3)
const guid_t intel_vsec_guid =
GUID_INIT(0x294903fb, 0x634d, 0x4fc7, 0xaf, 0x1f, 0x0f, 0xb9,
0x56, 0xb0, 0x4f, 0xc1);
static bool is_valid_entry(union acpi_object *pkg)
{
int i;
if (!pkg || pkg->type != ACPI_TYPE_PACKAGE || pkg->package.count != ENTRY_LEN)
return false;
if (pkg->package.elements[0].type != ACPI_TYPE_STRING)
return false;
for (i = 1; i < ENTRY_LEN; i++)
if (pkg->package.elements[i].type != ACPI_TYPE_INTEGER)
return false;
return true;
}
acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj,
struct intel_vsec_header *header)
{
union acpi_object *vsec_pkg;
union acpi_object *disc_pkg;
u64 hdr0, hdr1;
int num_regions;
int i;
if (!header)
return ERR_PTR(-EINVAL);
if (!obj || obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 2)
return ERR_PTR(-EINVAL);
/* First Package is DVSEC info */
vsec_pkg = &obj->package.elements[0];
if (!is_valid_entry(vsec_pkg))
return ERR_PTR(-EINVAL);
hdr0 = vsec_pkg->package.elements[3].integer.value;
hdr1 = vsec_pkg->package.elements[4].integer.value;
header->id = FIELD_GET(DVSEC_ID_MASK, hdr0);
header->num_entries = FIELD_GET(NUM_ENTRIES_MASK, hdr0);
header->entry_size = FIELD_GET(ENTRY_SIZE_MASK, hdr0);
header->tbir = FIELD_GET(TBIR_MASK, hdr1);
header->offset = hdr1 & DISC_TBL_OFF_MASK;
/* Second Package contains the discovery tables */
disc_pkg = &obj->package.elements[1];
if (disc_pkg->type != ACPI_TYPE_PACKAGE || disc_pkg->package.count < 1)
return ERR_PTR(-EINVAL);
num_regions = disc_pkg->package.count;
if (header->num_entries != num_regions)
return ERR_PTR(-EINVAL);
acpi_disc_t disc __free(kfree) = kmalloc_array(num_regions, sizeof(*disc),
GFP_KERNEL);
if (!disc)
return ERR_PTR(-ENOMEM);
for (i = 0; i < num_regions; i++) {
union acpi_object *pkg;
u64 value;
int j;
pkg = &disc_pkg->package.elements[i];
if (!is_valid_entry(pkg))
return ERR_PTR(-EINVAL);
/* Element 0 is a descriptive string; DWORD values start at index 1. */
for (j = 1; j < ENTRY_LEN; j++) {
value = pkg->package.elements[j].integer.value;
if (value > U32_MAX)
return ERR_PTR(-ERANGE);
disc[i][j - 1] = value;
}
}
return no_free_ptr(disc);
}
EXPORT_SYMBOL_NS_GPL(pmc_parse_telem_dsd, "INTEL_PMC_CORE");
union acpi_object *pmc_find_telem_guid(union acpi_object *dsd)
{
int i;
if (!dsd || dsd->type != ACPI_TYPE_PACKAGE)
return NULL;
for (i = 0; i + 1 < dsd->package.count; i += 2) {
union acpi_object *uuid_obj, *data_obj;
guid_t uuid;
uuid_obj = &dsd->package.elements[i];
data_obj = &dsd->package.elements[i + 1];
if (uuid_obj->type != ACPI_TYPE_BUFFER ||
uuid_obj->buffer.length != 16)
continue;
memcpy(&uuid, uuid_obj->buffer.pointer, 16);
if (guid_equal(&uuid, &intel_vsec_guid))
return data_obj;
}
return NULL;
}
EXPORT_SYMBOL_NS_GPL(pmc_find_telem_guid, "INTEL_PMC_CORE");
static int pmc_pwrm_acpi_probe(struct platform_device *pdev)
{
struct intel_vsec_header header;
struct intel_vsec_header *headers[2] = { &header, NULL };
struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL };
struct intel_vsec_platform_info info = { };
struct device *dev = &pdev->dev;
union acpi_object *dsd;
struct resource *res;
acpi_handle handle;
acpi_status status;
handle = ACPI_HANDLE(&pdev->dev);
if (!handle)
return -ENODEV;
status = acpi_evaluate_object(handle, "_DSD", NULL, &buf);
if (ACPI_FAILURE(status)) {
return dev_err_probe(dev, -ENODEV, "Could not evaluate _DSD: %s\n",
acpi_format_exception(status));
}
void *dsd_buf __free(pmc_acpi_free) = buf.pointer;
dsd = pmc_find_telem_guid(dsd_buf);
if (!dsd)
return -ENODEV;
acpi_disc_t acpi_disc __free(kfree) = pmc_parse_telem_dsd(dsd, &header);
if (IS_ERR(acpi_disc))
return PTR_ERR(acpi_disc);
res = platform_get_resource(pdev, IORESOURCE_MEM, header.tbir);
if (!res)
return -EINVAL;
info.headers = headers;
info.caps = VSEC_CAP_TELEMETRY;
info.acpi_disc = acpi_disc;
info.src = INTEL_VSEC_DISC_ACPI;
info.base_addr = res->start;
return intel_vsec_register(&pdev->dev, &info);
}
static const struct acpi_device_id pmc_pwrm_acpi_ids[] = {
{ "INTC1122", 0 }, /* Nova Lake */
{ "INTC1129", 0 }, /* Nova Lake */
{ }
};
MODULE_DEVICE_TABLE(acpi, pmc_pwrm_acpi_ids);
static struct platform_driver pmc_pwrm_acpi_driver = {
.probe = pmc_pwrm_acpi_probe,
.driver = {
.name = "intel_pmc_pwrm_acpi",
.acpi_match_table = ACPI_PTR(pmc_pwrm_acpi_ids),
},
};
module_platform_driver(pmc_pwrm_acpi_driver);
MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
MODULE_DESCRIPTION("Intel PMC PWRM ACPI driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS("INTEL_VSEC");
linux-7.2.3/drivers/platform/x86/intel/pmc/spt.c
+160
View File
@@ -0,0 +1,160 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Sunrise Point PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include <linux/pci.h>
#include "core.h"
static const struct pmc_bit_map spt_pll_map[] = {
{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
{}
};
static const struct pmc_bit_map spt_mphy_map[] = {
{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
{}
};
static const struct pmc_bit_map spt_pfear_map[] = {
{"PMC", SPT_PMC_BIT_PMC},
{"OPI-DMI", SPT_PMC_BIT_OPI},
{"SPI / eSPI", SPT_PMC_BIT_SPI},
{"XHCI", SPT_PMC_BIT_XHCI},
{"SPA", SPT_PMC_BIT_SPA},
{"SPB", SPT_PMC_BIT_SPB},
{"SPC", SPT_PMC_BIT_SPC},
{"GBE", SPT_PMC_BIT_GBE},
{"SATA", SPT_PMC_BIT_SATA},
{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
{"RSVD", SPT_PMC_BIT_RSVD_0B},
{"LPSS", SPT_PMC_BIT_LPSS},
{"LPC", SPT_PMC_BIT_LPC},
{"SMB", SPT_PMC_BIT_SMB},
{"ISH", SPT_PMC_BIT_ISH},
{"P2SB", SPT_PMC_BIT_P2SB},
{"DFX", SPT_PMC_BIT_DFX},
{"SCC", SPT_PMC_BIT_SCC},
{"RSVD", SPT_PMC_BIT_RSVD_0C},
{"FUSE", SPT_PMC_BIT_FUSE},
{"CAMERA", SPT_PMC_BIT_CAMREA},
{"RSVD", SPT_PMC_BIT_RSVD_0D},
{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
{"EXI", SPT_PMC_BIT_EXI},
{"CSE", SPT_PMC_BIT_CSE},
{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
{"RSVD", SPT_PMC_BIT_RSVD_1A},
{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
{}
};
static const struct pmc_bit_map *ext_spt_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of spt_reg_map for
* a list of core SoCs using this.
*/
spt_pfear_map,
NULL
};
static const struct pmc_bit_map spt_ltr_show_map[] = {
{"SOUTHPORT_A", SPT_PMC_LTR_SPA},
{"SOUTHPORT_B", SPT_PMC_LTR_SPB},
{"SATA", SPT_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
{"XHCI", SPT_PMC_LTR_XHCI},
{"Reserved", SPT_PMC_LTR_RESERVED},
{"ME", SPT_PMC_LTR_ME},
/* EVA is Enterprise Value Add, doesn't really exist on PCH */
{"EVA", SPT_PMC_LTR_EVA},
{"SOUTHPORT_C", SPT_PMC_LTR_SPC},
{"HD_AUDIO", SPT_PMC_LTR_AZ},
{"LPSS", SPT_PMC_LTR_LPSS},
{"SOUTHPORT_D", SPT_PMC_LTR_SPD},
{"SOUTHPORT_E", SPT_PMC_LTR_SPE},
{"CAMERA", SPT_PMC_LTR_CAM},
{"ESPI", SPT_PMC_LTR_ESPI},
{"SCC", SPT_PMC_LTR_SCC},
{"ISH", SPT_PMC_LTR_ISH},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
{}
};
static const struct pmc_reg_map spt_reg_map = {
.pfear_sts = ext_spt_pfear_map,
.mphy_sts = spt_mphy_map,
.pll_sts = spt_pll_map,
.ltr_show_sts = spt_ltr_show_map,
.msr_sts = msr_map,
.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
.regmap_length = SPT_PMC_MMIO_REG_LEN,
.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
.pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
};
static const struct pci_device_id spt_pmc_pci_id[] = {
{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
{ }
};
static int spt_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
/*
* Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
* Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
* in this case.
*/
if (!pci_dev_present(spt_pmc_pci_id))
return generic_core_init(pmcdev, &cnp_pmc_dev);
return generic_core_init(pmcdev, pmc_dev_info);
}
struct pmc_dev_info spt_pmc_dev = {
.map = &spt_reg_map,
.init = spt_core_init,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/ssram_telemetry.c
+488
View File
@@ -0,0 +1,488 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel PMC SSRAM TELEMETRY PCI Driver
*
* Copyright (c) 2023, Intel Corporation.
*/
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/bits.h>
#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/intel_vsec.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include "core.h"
#include "ssram_telemetry.h"
#define SSRAM_HDR_SIZE 0x100
#define SSRAM_PWRM_OFFSET 0x14
#define SSRAM_DVSEC_OFFSET 0x1C
#define SSRAM_DVSEC_SIZE 0x10
#define SSRAM_PCH_OFFSET 0x60
#define SSRAM_IOE_OFFSET 0x68
#define SSRAM_DEVID_OFFSET 0x70
#define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3)
#define SSRAM_PCI_PMC_MASK (BIT(PMC_IDX_MAIN) | BIT(PMC_IDX_IOE) | BIT(PMC_IDX_PCH))
DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_T))
enum resource_method {
RES_METHOD_PCI,
RES_METHOD_ACPI,
};
struct ssram_type {
enum resource_method method;
enum pmc_index p_index;
};
static const struct ssram_type pci_main = {
.method = RES_METHOD_PCI,
.p_index = PMC_IDX_MAIN,
};
static const struct ssram_type acpi_main = {
.method = RES_METHOD_ACPI,
.p_index = PMC_IDX_MAIN,
};
static const struct ssram_type acpi_pch = {
.method = RES_METHOD_ACPI,
.p_index = PMC_IDX_PCH,
};
enum pmc_ssram_state {
PMC_SSRAM_UNPROBED = 0,
PMC_SSRAM_PROBING,
PMC_SSRAM_PRESENT,
PMC_SSRAM_ABSENT,
};
static enum pmc_ssram_state pmc_ssram_state[MAX_NUM_PMC];
static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC];
struct pmc_ssram_probe_cache {
/* Per-index values staged by probe before publishing globally. */
struct pmc_ssram_telemetry telems[MAX_NUM_PMC];
/* PMCs this probe instance is responsible for publishing. */
unsigned long owned_mask;
/* Subset of owned_mask that was discovered successfully. */
unsigned long valid_mask;
};
struct pmc_ssram_drvdata {
/* PMCs published by this bound device; used to unpublish on remove. */
unsigned long owned_mask;
};
static inline u64 get_base(void __iomem *addr, u32 offset)
{
return lo_hi_readq(addr + offset) & SSRAM_BASE_ADDR_MASK;
}
static void pmc_ssram_get_devid_pwrmbase(struct pmc_ssram_probe_cache *probe_cache,
void __iomem *ssram, unsigned int pmc_idx)
{
u64 pwrm_base;
u16 devid;
pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET);
devid = readw(ssram + SSRAM_DEVID_OFFSET);
probe_cache->telems[pmc_idx].base_addr = pwrm_base;
probe_cache->telems[pmc_idx].devid = devid;
}
static void pmc_ssram_publish_absent(unsigned int pmc_idx)
{
/*
* Publish only the state without modifying base_addr and devid. This
* lets a reader that already observed PRESENT finish copying the
* previous values even if unbind concurrently publishes ABSENT. Readers
* that observe ABSENT return -ENODEV without accessing data.
*/
smp_store_release(&pmc_ssram_state[pmc_idx], PMC_SSRAM_ABSENT);
}
static void pmc_ssram_publish_present(struct pmc_ssram_probe_cache *probe_cache,
unsigned int pmc_idx)
{
/*
* The devid and base_addr fields are read from hardware MMIO registers
* whose values are stable for a given PMC index. A reader that observed
* PRESENT from an earlier probe can safely copy them while a concurrent
* rebind republishes those fields because both probes read the same
* hardware values.
*/
pmc_ssram_telems[pmc_idx] = probe_cache->telems[pmc_idx];
/*
* Publish base_addr and devid before publishing PRESENT. Pairs with the
* acquire load in the reader that consumes them after observing PRESENT.
*/
smp_store_release(&pmc_ssram_state[pmc_idx], PMC_SSRAM_PRESENT);
}
static void pmc_ssram_mark_probing(unsigned long mask)
{
unsigned long bit;
for_each_set_bit(bit, &mask, MAX_NUM_PMC)
WRITE_ONCE(pmc_ssram_state[bit], PMC_SSRAM_PROBING);
}
static int
pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 ssram_base, void __iomem *ssram)
{
struct intel_vsec_platform_info info = {};
struct intel_vsec_header *headers[2] = {};
struct intel_vsec_header header;
void __iomem *dvsec;
u32 dvsec_offset;
u32 table, hdr;
dvsec_offset = readl(ssram + SSRAM_DVSEC_OFFSET);
dvsec = ioremap(ssram_base + dvsec_offset, SSRAM_DVSEC_SIZE);
if (!dvsec)
return -ENOMEM;
hdr = readl(dvsec + PCI_DVSEC_HEADER1);
header.id = readw(dvsec + PCI_DVSEC_HEADER2);
header.rev = PCI_DVSEC_HEADER1_REV(hdr);
header.length = PCI_DVSEC_HEADER1_LEN(hdr);
header.num_entries = readb(dvsec + INTEL_DVSEC_ENTRIES);
header.entry_size = readb(dvsec + INTEL_DVSEC_SIZE);
table = readl(dvsec + INTEL_DVSEC_TABLE);
header.tbir = INTEL_DVSEC_TABLE_BAR(table);
header.offset = INTEL_DVSEC_TABLE_OFFSET(table);
iounmap(dvsec);
headers[0] = &header;
info.caps = VSEC_CAP_TELEMETRY;
info.headers = headers;
info.base_addr = ssram_base;
info.parent = &pcidev->dev;
return intel_vsec_register(&pcidev->dev, &info);
}
static int
pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev,
struct pmc_ssram_probe_cache *probe_cache,
unsigned int pmc_idx, u32 offset)
{
void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram = NULL;
void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram = NULL;
u64 ssram_base;
int ret;
ssram_base = pci_resource_start(pcidev, 0);
tmp_ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);
if (!tmp_ssram)
return -ENOMEM;
if (pmc_idx != PMC_IDX_MAIN) {
/*
* The secondary PMC BARS (which are behind hidden PCI devices)
* are read from fixed offsets in MMIO of the primary PMC BAR.
* If a device is not present, the value will be 0.
*/
ssram_base = get_base(tmp_ssram, offset);
if (!ssram_base)
return 0;
ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);
if (!ssram)
return -ENOMEM;
} else {
ssram = no_free_ptr(tmp_ssram);
}
pmc_ssram_get_devid_pwrmbase(probe_cache, ssram, pmc_idx);
/* Find and register and PMC telemetry entries */
ret = pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram);
if (ret)
dev_warn(&pcidev->dev, "could not register PMT\n");
probe_cache->valid_mask |= BIT(pmc_idx);
return 0;
}
static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev,
struct pmc_ssram_probe_cache *probe_cache)
{
int ret;
ret = pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_MAIN, 0);
if (ret)
return ret;
/*
* If MAIN PMC enumeration is successful but either IOE or PCH fail,
* don't fail probe as the MAIN PMC is still useful as it provides the
* global reset and slp_s0 counter access. Failed or missing secondary
* PMCs are left out of valid_mask and published as absent.
*/
pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_IOE,
SSRAM_IOE_OFFSET);
pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_PCH,
SSRAM_PCH_OFFSET);
return 0;
}
static int pmc_ssram_telemetry_get_pmc_acpi(struct pci_dev *pcidev,
struct pmc_ssram_probe_cache *probe_cache,
unsigned int pmc_idx)
{
u64 ssram_base;
ssram_base = pci_resource_start(pcidev, 0);
if (!ssram_base)
return -ENODEV;
void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =
ioremap(ssram_base, SSRAM_HDR_SIZE);
if (!ssram)
return -ENOMEM;
pmc_ssram_get_devid_pwrmbase(probe_cache, ssram, pmc_idx);
probe_cache->valid_mask |= BIT(pmc_idx);
return 0;
}
static int pmc_ssram_telemetry_acpi_init(struct pci_dev *pcidev,
struct pmc_ssram_probe_cache *probe_cache,
enum pmc_index index)
{
struct intel_vsec_header header;
struct intel_vsec_header *headers[2] = { &header, NULL };
struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL };
struct intel_vsec_platform_info info = { };
union acpi_object *dsd;
acpi_handle handle;
acpi_status status;
int ret;
handle = ACPI_HANDLE(&pcidev->dev);
if (!handle)
return -ENODEV;
status = acpi_evaluate_object(handle, "_DSD", NULL, &buf);
if (ACPI_FAILURE(status))
return -ENODEV;
void *dsd_buf __free(pmc_acpi_free) = buf.pointer;
dsd = pmc_find_telem_guid(dsd_buf);
if (!dsd)
return -ENODEV;
acpi_disc_t disc __free(kfree) = pmc_parse_telem_dsd(dsd, &header);
if (IS_ERR(disc))
return PTR_ERR(disc);
info.headers = headers;
info.caps = VSEC_CAP_TELEMETRY;
info.acpi_disc = disc;
info.src = INTEL_VSEC_DISC_ACPI;
/* This is an ACPI companion device. PCI BAR will be used for base addr. */
info.base_addr = 0;
ret = intel_vsec_register(&pcidev->dev, &info);
if (ret)
dev_warn(&pcidev->dev, "could not register PMT\n");
return pmc_ssram_telemetry_get_pmc_acpi(pcidev, probe_cache, index);
}
/**
* pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr information
* @pmc_idx: Index of the PMC
* @pmc_ssram_telemetry: pmc_ssram_telemetry structure to store the PMC information
*
* State flow per PMC index:
* - PMC_SSRAM_UNPROBED: Probe has not started for this index.
* - PMC_SSRAM_PROBING: Probe is currently discovering data for this index.
* - PMC_SSRAM_PRESENT: base_addr/devid were published and can be read.
* - PMC_SSRAM_ABSENT: No data is available for this index.
*
* Readers use an acquire load of the state. If state is PRESENT, reads of
* base_addr/devid are ordered after the state observation and pair with the
* writer's release-store when publishing PRESENT.
*
* Return:
* * 0 - Success
* * -EAGAIN - Probe function has not finished yet. Try again.
* * -EINVAL - Invalid pmc_idx
* * -ENODEV - PMC device is not available (hardware absent or driver failed to initialize)
*/
int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx,
struct pmc_ssram_telemetry *pmc_ssram_telemetry)
{
enum pmc_ssram_state state;
if (pmc_idx >= MAX_NUM_PMC)
return -EINVAL;
/*
* PMCs are discovered in probe function. If this function is called before
* probe function complete, the result would be invalid. Use per-PMC state
* to inform the consumer to call again later.
*/
state = smp_load_acquire(&pmc_ssram_state[pmc_idx]);
if (state == PMC_SSRAM_UNPROBED || state == PMC_SSRAM_PROBING)
return -EAGAIN;
if (state == PMC_SSRAM_ABSENT)
return -ENODEV;
/*
* Acquire semantics order reads of devid and base_addr after observing
* PRESENT and pair with the writer's release-store.
*/
pmc_ssram_telemetry->devid = pmc_ssram_telems[pmc_idx].devid;
pmc_ssram_telemetry->base_addr = pmc_ssram_telems[pmc_idx].base_addr;
return 0;
}
EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info);
static void pmc_ssram_publish_absent_mask(unsigned long mask)
{
unsigned long bit;
for_each_set_bit(bit, &mask, MAX_NUM_PMC)
pmc_ssram_publish_absent(bit);
}
static void pmc_ssram_publish_telems(struct pmc_ssram_probe_cache *probe_cache, int ret)
{
unsigned long bit;
/* If probe failed, all owned indexes become absent for readers. */
if (ret) {
pmc_ssram_publish_absent_mask(probe_cache->owned_mask);
return;
}
/* Publish each owned index independently based on discovery result. */
for_each_set_bit(bit, &probe_cache->owned_mask, MAX_NUM_PMC) {
if (probe_cache->valid_mask & BIT(bit))
pmc_ssram_publish_present(probe_cache, bit);
else
pmc_ssram_publish_absent(bit);
}
}
static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct pci_device_id *id)
{
struct pmc_ssram_probe_cache probe_cache = {};
struct pmc_ssram_drvdata *drvdata;
const struct ssram_type *ssram_type;
enum resource_method method;
enum pmc_index index;
int ret;
ssram_type = (const struct ssram_type *)id->driver_data;
if (!ssram_type) {
dev_dbg(&pcidev->dev, "missing driver data\n");
return -EINVAL;
}
index = ssram_type->p_index;
method = ssram_type->method;
if (method == RES_METHOD_PCI)
probe_cache.owned_mask = SSRAM_PCI_PMC_MASK;
else if (method == RES_METHOD_ACPI)
probe_cache.owned_mask = BIT(index);
else
return -EINVAL;
pmc_ssram_mark_probing(probe_cache.owned_mask);
drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata) {
ret = -ENOMEM;
goto probe_finish;
}
ret = pcim_enable_device(pcidev);
if (ret) {
dev_dbg(&pcidev->dev, "failed to enable PMC SSRAM device\n");
goto probe_finish;
}
if (method == RES_METHOD_PCI)
ret = pmc_ssram_telemetry_pci_init(pcidev, &probe_cache);
else if (method == RES_METHOD_ACPI)
ret = pmc_ssram_telemetry_acpi_init(pcidev, &probe_cache, index);
else
ret = -EINVAL;
if (!ret) {
drvdata->owned_mask = probe_cache.owned_mask;
pci_set_drvdata(pcidev, drvdata);
}
probe_finish:
pmc_ssram_publish_telems(&probe_cache, ret);
return ret;
}
static void pmc_ssram_telemetry_remove(struct pci_dev *pcidev)
{
struct pmc_ssram_drvdata *drvdata = pci_get_drvdata(pcidev);
if (drvdata)
pmc_ssram_publish_absent_mask(drvdata->owned_mask);
}
static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN),
.driver_data = (kernel_ulong_t)&pci_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDH),
.driver_data = (kernel_ulong_t)&acpi_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDS),
.driver_data = (kernel_ulong_t)&acpi_main },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCHS),
.driver_data = (kernel_ulong_t)&acpi_pch },
{ }
};
MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids);
static struct pci_driver pmc_ssram_telemetry_driver = {
.name = "intel_pmc_ssram_telemetry",
.id_table = pmc_ssram_telemetry_pci_ids,
.probe = pmc_ssram_telemetry_probe,
.remove = pmc_ssram_telemetry_remove,
};
module_pci_driver(pmc_ssram_telemetry_driver);
MODULE_IMPORT_NS("INTEL_VSEC");
MODULE_IMPORT_NS("INTEL_PMC_CORE");
MODULE_AUTHOR("Xi Pardee <xi.pardee@intel.com>");
MODULE_DESCRIPTION("Intel PMC SSRAM Telemetry driver");
MODULE_LICENSE("GPL");
linux-7.2.3/drivers/platform/x86/intel/pmc/ssram_telemetry.h
+24
View File
@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel PMC SSRAM Telemetry PCI Driver Header File
*
* Copyright (c) 2024, Intel Corporation.
*/
#ifndef PMC_SSRAM_H
#define PMC_SSRAM_H
/**
* struct pmc_ssram_telemetry - Structure to keep pmc info in ssram device
* @devid: device id of the pmc device
* @base_addr: contains PWRM base address
*/
struct pmc_ssram_telemetry {
u16 devid;
u64 base_addr;
};
int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx,
struct pmc_ssram_telemetry *pmc_ssram_telemetry);
#endif /* PMC_SSRAM_H */
linux-7.2.3/drivers/platform/x86/intel/pmc/tgl.c
+312
View File
@@ -0,0 +1,312 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Tiger Lake PCH.
*
* Copyright (c) 2022, Intel Corporation.
* All Rights Reserved.
*
*/
#include "core.h"
#define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
#define ACPI_GET_LOW_MODE_REGISTERS 1
enum pch_type {
PCH_H,
PCH_LP
};
static const struct pmc_bit_map tgl_pfear_map[] = {
{"PSF9", BIT(0)},
{"RES_66", BIT(1)},
{"RES_67", BIT(2)},
{"RES_68", BIT(3)},
{"RES_69", BIT(4)},
{"RES_70", BIT(5)},
{"TBTLSX", BIT(6)},
{}
};
static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
/*
* Check intel_pmc_core_ids[] users of tgl_reg_map for
* a list of core SoCs using this.
*/
cnp_pfear_map,
tgl_pfear_map,
NULL
};
static const struct pmc_bit_map tgl_clocksource_status_map[] = {
{"USB2PLL_OFF_STS", BIT(18)},
{"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
{"PCIe_Gen3PLL_OFF_STS", BIT(20)},
{"OPIOPLL_OFF_STS", BIT(21)},
{"OCPLL_OFF_STS", BIT(22)},
{"MainPLL_OFF_STS", BIT(23)},
{"MIPIPLL_OFF_STS", BIT(24)},
{"Fast_XTAL_Osc_OFF_STS", BIT(25)},
{"AC_Ring_Osc_OFF_STS", BIT(26)},
{"MC_Ring_Osc_OFF_STS", BIT(27)},
{"SATAPLL_OFF_STS", BIT(29)},
{"XTAL_USB2PLL_OFF_STS", BIT(31)},
{}
};
static const struct pmc_bit_map tgl_power_gating_status_map[] = {
{"CSME_PG_STS", BIT(0)},
{"SATA_PG_STS", BIT(1)},
{"xHCI_PG_STS", BIT(2)},
{"UFSX2_PG_STS", BIT(3)},
{"OTG_PG_STS", BIT(5)},
{"SPA_PG_STS", BIT(6)},
{"SPB_PG_STS", BIT(7)},
{"SPC_PG_STS", BIT(8)},
{"SPD_PG_STS", BIT(9)},
{"SPE_PG_STS", BIT(10)},
{"SPF_PG_STS", BIT(11)},
{"LSX_PG_STS", BIT(13)},
{"P2SB_PG_STS", BIT(14)},
{"PSF_PG_STS", BIT(15)},
{"SBR_PG_STS", BIT(16)},
{"OPIDMI_PG_STS", BIT(17)},
{"THC0_PG_STS", BIT(18)},
{"THC1_PG_STS", BIT(19)},
{"GBETSN_PG_STS", BIT(20)},
{"GBE_PG_STS", BIT(21)},
{"LPSS_PG_STS", BIT(22)},
{"MMP_UFSX2_PG_STS", BIT(23)},
{"MMP_UFSX2B_PG_STS", BIT(24)},
{"FIA_PG_STS", BIT(25)},
{}
};
static const struct pmc_bit_map tgl_d3_status_map[] = {
{"ADSP_D3_STS", BIT(0)},
{"SATA_D3_STS", BIT(1)},
{"xHCI0_D3_STS", BIT(2)},
{"xDCI1_D3_STS", BIT(5)},
{"SDX_D3_STS", BIT(6)},
{"EMMC_D3_STS", BIT(7)},
{"IS_D3_STS", BIT(8)},
{"THC0_D3_STS", BIT(9)},
{"THC1_D3_STS", BIT(10)},
{"GBE_D3_STS", BIT(11)},
{"GBE_TSN_D3_STS", BIT(12)},
{}
};
static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
{"GPIO_COM0_VNN_REQ_STS", BIT(1)},
{"GPIO_COM1_VNN_REQ_STS", BIT(2)},
{"GPIO_COM2_VNN_REQ_STS", BIT(3)},
{"GPIO_COM3_VNN_REQ_STS", BIT(4)},
{"GPIO_COM4_VNN_REQ_STS", BIT(5)},
{"GPIO_COM5_VNN_REQ_STS", BIT(6)},
{"Audio_VNN_REQ_STS", BIT(7)},
{"ISH_VNN_REQ_STS", BIT(8)},
{"CNVI_VNN_REQ_STS", BIT(9)},
{"eSPI_VNN_REQ_STS", BIT(10)},
{"Display_VNN_REQ_STS", BIT(11)},
{"DTS_VNN_REQ_STS", BIT(12)},
{"SMBUS_VNN_REQ_STS", BIT(14)},
{"CSME_VNN_REQ_STS", BIT(15)},
{"SMLINK0_VNN_REQ_STS", BIT(16)},
{"SMLINK1_VNN_REQ_STS", BIT(17)},
{"CLINK_VNN_REQ_STS", BIT(20)},
{"DCI_VNN_REQ_STS", BIT(21)},
{"ITH_VNN_REQ_STS", BIT(22)},
{"CSME_VNN_REQ_STS", BIT(24)},
{"GBE_VNN_REQ_STS", BIT(25)},
{}
};
static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS_0", BIT(0)},
{"PCIe_LPM_En_REQ_STS_3", BIT(3)},
{"ITH_REQ_STS_5", BIT(5)},
{"CNVI_REQ_STS_6", BIT(6)},
{"ISH_REQ_STS_7", BIT(7)},
{"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
{"PCIe_Clk_REQ_STS_12", BIT(12)},
{"MPHY_Core_DL_REQ_STS_16", BIT(16)},
{"Break-even_En_REQ_STS_17", BIT(17)},
{"Auto-demo_En_REQ_STS_18", BIT(18)},
{"MPHY_SUS_REQ_STS_22", BIT(22)},
{"xDCI_attached_REQ_STS_24", BIT(24)},
{}
};
const struct pmc_bit_map tgl_signal_status_map[] = {
{"LSX_Wake0_En_STS", BIT(0)},
{"LSX_Wake0_Pol_STS", BIT(1)},
{"LSX_Wake1_En_STS", BIT(2)},
{"LSX_Wake1_Pol_STS", BIT(3)},
{"LSX_Wake2_En_STS", BIT(4)},
{"LSX_Wake2_Pol_STS", BIT(5)},
{"LSX_Wake3_En_STS", BIT(6)},
{"LSX_Wake3_Pol_STS", BIT(7)},
{"LSX_Wake4_En_STS", BIT(8)},
{"LSX_Wake4_Pol_STS", BIT(9)},
{"LSX_Wake5_En_STS", BIT(10)},
{"LSX_Wake5_Pol_STS", BIT(11)},
{"LSX_Wake6_En_STS", BIT(12)},
{"LSX_Wake6_Pol_STS", BIT(13)},
{"LSX_Wake7_En_STS", BIT(14)},
{"LSX_Wake7_Pol_STS", BIT(15)},
{"Intel_Se_IO_Wake0_En_STS", BIT(16)},
{"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
{"Intel_Se_IO_Wake1_En_STS", BIT(18)},
{"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
{"Int_Timer_SS_Wake0_En_STS", BIT(20)},
{"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
{"Int_Timer_SS_Wake1_En_STS", BIT(22)},
{"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
{"Int_Timer_SS_Wake2_En_STS", BIT(24)},
{"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
{"Int_Timer_SS_Wake3_En_STS", BIT(26)},
{"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
{"Int_Timer_SS_Wake4_En_STS", BIT(28)},
{"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
{"Int_Timer_SS_Wake5_En_STS", BIT(30)},
{"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},
{}
};
static const struct pmc_bit_map *tgl_lpm_maps[] = {
tgl_clocksource_status_map,
tgl_power_gating_status_map,
tgl_d3_status_map,
tgl_vnn_req_status_map,
tgl_vnn_misc_status_map,
tgl_signal_status_map,
NULL
};
static const struct pmc_reg_map tgl_reg_map = {
.pfear_sts = ext_tgl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
.lpm_num_maps = TGL_LPM_NUM_MAPS,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
.lpm_en_offset = TGL_LPM_EN_OFFSET,
.lpm_priority_offset = TGL_LPM_PRI_OFFSET,
.lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
.lpm_sts = tgl_lpm_maps,
.lpm_status_offset = TGL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
.etr3_offset = ETR3_OFFSET,
};
static const struct pmc_reg_map tgl_h_reg_map = {
.pfear_sts = ext_tgl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
.lpm_num_maps = TGL_LPM_NUM_MAPS,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
.lpm_en_offset = TGL_LPM_EN_OFFSET,
.lpm_priority_offset = TGL_LPM_PRI_OFFSET,
.lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
.lpm_sts = tgl_lpm_maps,
.lpm_status_offset = TGL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
.etr3_offset = ETR3_OFFSET,
.pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,
.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
};
void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
{
struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
const int num_maps = pmc->map->lpm_num_maps;
u32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;
union acpi_object *out_obj;
struct acpi_device *adev;
guid_t s0ix_dsm_guid;
u32 *lpm_req_regs, *addr;
adev = ACPI_COMPANION(&pdev->dev);
if (!adev)
return;
guid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);
out_obj = acpi_evaluate_dsm_typed(adev->handle, &s0ix_dsm_guid, 0,
ACPI_GET_LOW_MODE_REGISTERS, NULL, ACPI_TYPE_BUFFER);
if (out_obj) {
u32 size = out_obj->buffer.length;
if (size != lpm_size) {
acpi_handle_debug(adev->handle,
"_DSM returned unexpected buffer size, have %u, expect %u\n",
size, lpm_size);
goto free_acpi_obj;
}
} else {
acpi_handle_debug(adev->handle,
"_DSM function 0 evaluation failed\n");
goto free_acpi_obj;
}
addr = (u32 *)out_obj->buffer.pointer;
lpm_req_regs = devm_kcalloc(&pdev->dev, lpm_size, sizeof(u32),
GFP_KERNEL);
if (!lpm_req_regs)
goto free_acpi_obj;
memcpy(lpm_req_regs, addr, lpm_size);
pmc->lpm_req_regs = lpm_req_regs;
free_acpi_obj:
ACPI_FREE(out_obj);
}
static int tgl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
int ret;
ret = generic_core_init(pmcdev, pmc_dev_info);
if (ret)
return ret;
pmc_core_get_tgl_lpm_reqs(pmcdev->pdev);
return 0;
}
struct pmc_dev_info tgl_l_pmc_dev = {
.map = &tgl_reg_map,
.suspend = cnl_suspend,
.resume = cnl_resume,
.init = tgl_core_init,
};
struct pmc_dev_info tgl_pmc_dev = {
.map = &tgl_h_reg_map,
.suspend = cnl_suspend,
.resume = cnl_resume,
.init = tgl_core_init,
};
linux-7.2.3/drivers/platform/x86/intel/pmc/wcl.c
+508
View File
@@ -0,0 +1,508 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains platform specific structure definitions
* and init function used by Wildcat Lake PCH.
*
* Copyright (c) 2025, Intel Corporation.
*/
#include <linux/bits.h>
#include <linux/pci.h>
#include "core.h"
/* PMC SSRAM PMT Telemetry GUIDS */
#define PCDN_LPM_REQ_GUID 0x33747648
static const struct pmc_bit_map wcl_pcdn_pfear_map[] = {
{"PMC_0", BIT(0)},
{"FUSE_OSSE", BIT(1)},
{"ESPISPI", BIT(2)},
{"XHCI", BIT(3)},
{"SPA", BIT(4)},
{"RSVD", BIT(5)},
{"MPFPW2", BIT(6)},
{"GBE", BIT(7)},
{"SBR16B21", BIT(0)},
{"SBR16B5", BIT(1)},
{"SBR8B1", BIT(2)},
{"SBR8B0", BIT(3)},
{"P2SB0", BIT(4)},
{"D2D_DISP_1", BIT(5)},
{"LPSS", BIT(6)},
{"LPC", BIT(7)},
{"SMB", BIT(0)},
{"ISH", BIT(1)},
{"DBG_SBR16B", BIT(2)},
{"NPK_0", BIT(3)},
{"D2D_NOC_1", BIT(4)},
{"FIA_P", BIT(5)},
{"FUSE", BIT(6)},
{"DBG_PSF", BIT(7)},
{"DISP_PGA1", BIT(0)},
{"XDCI", BIT(1)},
{"EXI", BIT(2)},
{"CSE", BIT(3)},
{"KVMCC", BIT(4)},
{"PMT", BIT(5)},
{"CLINK", BIT(6)},
{"PTIO", BIT(7)},
{"USBR0", BIT(0)},
{"SBR16B22", BIT(1)},
{"SMT1", BIT(2)},
{"MPFPW1", BIT(3)},
{"SMS2", BIT(4)},
{"SMS1", BIT(5)},
{"CSMERTC", BIT(6)},
{"CSMEPSF", BIT(7)},
{"D2D_NOC_0", BIT(0)},
{"ESE", BIT(1)},
{"FIACPCB_P", BIT(2)},
{"RSVD", BIT(3)},
{"SBR8B2", BIT(4)},
{"OSSE_SMT1", BIT(5)},
{"D2D_DISP", BIT(6)},
{"P2SB1", BIT(7)},
{"U3FPW1", BIT(0)},
{"SBR16B3", BIT(1)},
{"PSF4", BIT(2)},
{"CNVI", BIT(3)},
{"UFSX2", BIT(4)},
{"ENDBG", BIT(5)},
{"DBC", BIT(6)},
{"SBRG", BIT(7)},
{"RSVD", BIT(0)},
{"NPK1", BIT(1)},
{"SBR16B7", BIT(2)},
{"SBR16B4", BIT(3)},
{"FIA_XG", BIT(4)},
{"PSF6", BIT(5)},
{"UFSPW1", BIT(6)},
{"FIA_U", BIT(7)},
{"PSF8", BIT(0)},
{"PSF0", BIT(1)},
{"RSVD", BIT(2)},
{"FIACPCB_U", BIT(3)},
{"TAM", BIT(4)},
{"SBR16B0", BIT(5)},
{"TBTLSX", BIT(6)},
{"THC0", BIT(7)},
{"THC1", BIT(0)},
{"PMC_1", BIT(1)},
{"FIACPCB_XG", BIT(2)},
{"TCSS", BIT(3)},
{"DISP_PGA", BIT(4)},
{"SBR16B20", BIT(5)},
{"SBR8B20", BIT(6)},
{"DBG_SBR", BIT(7)},
{"SPC", BIT(0)},
{"ACE_0", BIT(1)},
{"ACE_1", BIT(2)},
{"ACE_2", BIT(3)},
{"ACE_3", BIT(4)},
{"ACE_4", BIT(5)},
{"ACE_5", BIT(6)},
{"ACE_6", BIT(7)},
{"ACE_7", BIT(0)},
{"ACE_8", BIT(1)},
{"ACE_9", BIT(2)},
{"ACE_10", BIT(3)},
{"SBR16B2", BIT(4)},
{"SBR8B4", BIT(5)},
{"OSSE", BIT(6)},
{"SBR16B1", BIT(7)},
{}
};
static const struct pmc_bit_map *ext_wcl_pcdn_pfear_map[] = {
wcl_pcdn_pfear_map,
NULL
};
static const struct pmc_bit_map wcl_pcdn_ltr_show_map[] = {
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
{"RSVD", WCL_PMC_LTR_RESERVED},
{"SATA", CNP_PMC_LTR_SATA},
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
{"XHCI", CNP_PMC_LTR_XHCI},
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
{"ME", CNP_PMC_LTR_ME},
{"SATA1", CNP_PMC_LTR_EVA},
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
{"HD_AUDIO", CNP_PMC_LTR_AZ},
{"CNV", CNP_PMC_LTR_CNV},
{"LPSS", CNP_PMC_LTR_LPSS},
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
{"SATA2", PTL_PMC_LTR_SATA2},
{"ESPI", CNP_PMC_LTR_ESPI},
{"SCC", CNP_PMC_LTR_SCC},
{"ISH", CNP_PMC_LTR_ISH},
{"UFSX2", CNP_PMC_LTR_UFSX2},
{"EMMC", CNP_PMC_LTR_EMMC},
{"WIGIG", ICL_PMC_LTR_WIGIG},
{"THC0", TGL_PMC_LTR_THC0},
{"THC1", TGL_PMC_LTR_THC1},
{"SOUTHPORT_G", MTL_PMC_LTR_SPG},
{"ESE", MTL_PMC_LTR_ESE},
{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
{"DMI3", ARL_PMC_LTR_DMI3},
{"OSSE", LNL_PMC_LTR_OSSE},
/* Below two cannot be used for LTR_IGNORE */
{"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT},
{"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT},
{}
};
static const struct pmc_bit_map wcl_pcdn_power_gating_status_0_map[] = {
{"PMC_PGD0_PG_STS", BIT(0), 0},
{"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
{"ESPISPI_PGD0_PG_STS", BIT(2), 0},
{"XHCI_PGD0_PG_STS", BIT(3), 1},
{"SPA_PGD0_PG_STS", BIT(4), 1},
{"RSVD_5", BIT(5), 0},
{"MPFPW2_PGD0_PG_STS", BIT(6), 0},
{"GBE_PGD0_PG_STS", BIT(7), 1},
{"SBR16B21_PGD0_PG_STS", BIT(8), 0},
{"SBR16B5_PGD0_PG_STS", BIT(9), 0},
{"SBR8B1_PGD0_PG_STS", BIT(10), 0},
{"SBR8B0_PGD0_PG_STS", BIT(11), 0},
{"P2SB0_PG_STS", BIT(12), 1},
{"D2D_DISP_PGD1_PG_STS", BIT(13), 0},
{"LPSS_PGD0_PG_STS", BIT(14), 1},
{"LPC_PGD0_PG_STS", BIT(15), 0},
{"SMB_PGD0_PG_STS", BIT(16), 0},
{"ISH_PGD0_PG_STS", BIT(17), 0},
{"DBG_SBR16B_PGD0_PG_STS", BIT(18), 0},
{"NPK_PGD0_PG_STS", BIT(19), 0},
{"D2D_NOC_PGD1_PG_STS", BIT(20), 0},
{"FIA_P_PGD0_PG_STS", BIT(21), 0},
{"FUSE_PGD0_PG_STS", BIT(22), 0},
{"DBG_PSF_PGD0_PG_STS", BIT(23), 0},
{"DISP_PGA1_PGD0_PG_STS", BIT(24), 0},
{"XDCI_PGD0_PG_STS", BIT(25), 1},
{"EXI_PGD0_PG_STS", BIT(26), 0},
{"CSE_PGD0_PG_STS", BIT(27), 1},
{"KVMCC_PGD0_PG_STS", BIT(28), 1},
{"PMT_PGD0_PG_STS", BIT(29), 1},
{"CLINK_PGD0_PG_STS", BIT(30), 1},
{"PTIO_PGD0_PG_STS", BIT(31), 1},
{}
};
static const struct pmc_bit_map wcl_pcdn_power_gating_status_1_map[] = {
{"USBR0_PGD0_PG_STS", BIT(0), 1},
{"SBR16B22_PGD0_PG_STS", BIT(1), 0},
{"SMT1_PGD0_PG_STS", BIT(2), 1},
{"MPFPW1_PGD0_PG_STS", BIT(3), 0},
{"SMS2_PGD0_PG_STS", BIT(4), 1},
{"SMS1_PGD0_PG_STS", BIT(5), 1},
{"CSMERTC_PGD0_PG_STS", BIT(6), 0},
{"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
{"D2D_NOC_PGD0_PG_STS", BIT(8), 0},
{"ESE_PGD0_PG_STS", BIT(9), 1},
{"FIACPCB_P_PGD0_PG_STS", BIT(10), 0},
{"SBR8B2_PGD0_PG_STS", BIT(12), 0},
{"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
{"D2D_DISP_PGD0_PG_STS", BIT(14), 0},
{"P2SB1_PGD0_PG_STS", BIT(15), 1},
{"U3FPW1_PGD0_PG_STS", BIT(16), 0},
{"SBR16B3_PGD0_PG_STS", BIT(17), 0},
{"PSF4_PGD0_PG_STS", BIT(18), 0},
{"CNVI_PGD0_PG_STS", BIT(19), 0},
{"UFSX2_PGD0_PG_STS", BIT(20), 1},
{"ENDBG_PGD0_PG_STS", BIT(21), 0},
{"DBC_PGD0_PG_STS", BIT(22), 0},
{"SBRG_PGD0_PG_STS", BIT(23), 0},
{"NPK_PGD1_PG_STS", BIT(25), 0},
{"SBR16B7_PGD0_PG_STS", BIT(26), 0},
{"SBR16B4_PGD0_PG_STS", BIT(27), 0},
{"FIA_XG_PSF_PGD0_PG_STS", BIT(28), 0},
{"PSF6_PGD0_PG_STS", BIT(29), 0},
{"UFSPW1_PGD0_PG_STS", BIT(30), 0},
{"FIA_U_PGD0_PG_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_power_gating_status_2_map[] = {
{"PSF8_PGD0_PG_STS", BIT(0), 0},
{"PSF0_PGD0_PG_STS", BIT(1), 0},
{"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
{"TAM_PGD0_PG_STS", BIT(4), 1},
{"SBR16B0_PGD0_PG_STS", BIT(5), 0},
{"TBTLSX_PGD0_PG_STS", BIT(6), 1},
{"THC0_PGD0_PG_STS", BIT(7), 1},
{"THC1_PGD0_PG_STS", BIT(8), 1},
{"PMC_PGD1_PG_STS", BIT(9), 0},
{"FIACPCB_XG_PGD0_PG_STS", BIT(10), 0},
{"TCSS_PGD0_PG_STS", BIT(11), 0},
{"DISP_PGA_PGD0_PG_STS", BIT(12), 0},
{"SBR8B4_PGD0_PG_STS", BIT(13), 0},
{"SBR8B20_PGD0_PG_STS", BIT(14), 0},
{"DBG_PGD0_PG_STS", BIT(15), 0},
{"SPC_PGD0_PG_STS", BIT(16), 1},
{"ACE_PGD0_PG_STS", BIT(17), 0},
{"ACE_PGD1_PG_STS", BIT(18), 0},
{"ACE_PGD2_PG_STS", BIT(19), 0},
{"ACE_PGD3_PG_STS", BIT(20), 0},
{"ACE_PGD4_PG_STS", BIT(21), 0},
{"ACE_PGD5_PG_STS", BIT(22), 0},
{"ACE_PGD6_PG_STS", BIT(23), 0},
{"ACE_PGD7_PG_STS", BIT(24), 0},
{"ACE_PGD8_PG_STS", BIT(25), 0},
{"ACE_PGD9_PG_STS", BIT(26), 0},
{"ACE_PGD10_PG_STS", BIT(27), 0},
{"SBR16B2_PG_PGD0_PG_STS", BIT(28), 0},
{"SBR16B20_PGD0_PG_STS", BIT(29), 0},
{"OSSE_PGD0_PG_STS", BIT(30), 1},
{"SBR16B1_PGD0_PG_STS", BIT(31), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_d3_status_0_map[] = {
{"LPSS_D3_STS", BIT(3), 1},
{"XDCI_D3_STS", BIT(4), 1},
{"XHCI_D3_STS", BIT(5), 1},
{"SPA_D3_STS", BIT(12), 0},
{"SPC_D3_STS", BIT(14), 0},
{"OSSE_D3_STS", BIT(15), 0},
{"ESPISPI_D3_STS", BIT(18), 0},
{"PSTH_D3_STS", BIT(21), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_d3_status_1_map[] = {
{"OSSE_SMT1_D3_STS", BIT(16), 0},
{"GBE_D3_STS", BIT(19), 0},
{"ITSS_D3_STS", BIT(23), 0},
{"CNVI_D3_STS", BIT(27), 0},
{"UFSX2_D3_STS", BIT(28), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_d3_status_2_map[] = {
{"CSMERTC_D3_STS", BIT(1), 0},
{"ESE_D3_STS", BIT(2), 0},
{"CSE_D3_STS", BIT(4), 0},
{"KVMCC_D3_STS", BIT(5), 0},
{"USBR0_D3_STS", BIT(6), 0},
{"ISH_D3_STS", BIT(7), 0},
{"SMT1_D3_STS", BIT(8), 0},
{"SMT2_D3_STS", BIT(9), 0},
{"SMT3_D3_STS", BIT(10), 0},
{"CLINK_D3_STS", BIT(14), 0},
{"PTIO_D3_STS", BIT(16), 0},
{"PMT_D3_STS", BIT(17), 0},
{"SMS1_D3_STS", BIT(18), 0},
{"SMS2_D3_STS", BIT(19), 0},
{"OSSE_SMT2_D3_STS", BIT(22), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_d3_status_3_map[] = {
{"THC0_D3_STS", BIT(14), 1},
{"THC1_D3_STS", BIT(15), 1},
{"OSSE_SMT3_D3_STS", BIT(16), 0},
{"ACE_D3_STS", BIT(23), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_vnn_req_status_0_map[] = {
{"LPSS_VNN_REQ_STS", BIT(3), 1},
{"OSSE_VNN_REQ_STS", BIT(15), 1},
{"ESPISPI_VNN_REQ_STS", BIT(18), 1},
{}
};
static const struct pmc_bit_map wcl_pcdn_vnn_req_status_1_map[] = {
{"NPK_VNN_REQ_STS", BIT(4), 1},
{"DFXAGG_VNN_REQ_STS", BIT(8), 0},
{"EXI_VNN_REQ_STS", BIT(9), 1},
{"OSSE_SMT1_VNN_REQ_STS", BIT(16), 1},
{"P2D_VNN_REQ_STS", BIT(18), 1},
{"GBE_VNN_REQ_STS", BIT(19), 1},
{"SMB_VNN_REQ_STS", BIT(25), 1},
{"LPC_VNN_REQ_STS", BIT(26), 0},
{}
};
static const struct pmc_bit_map wcl_pcdn_vnn_req_status_2_map[] = {
{"CSMERTC_VNN_REQ_STS", BIT(1), 1},
{"ESE_VNN_REQ_STS", BIT(2), 1},
{"CSE_VNN_REQ_STS", BIT(4), 1},
{"ISH_VNN_REQ_STS", BIT(7), 1},
{"SMT1_VNN_REQ_STS", BIT(8), 1},
{"CLINK_VNN_REQ_STS", BIT(14), 1},
{"SMS1_VNN_REQ_STS", BIT(18), 1},
{"SMS2_VNN_REQ_STS", BIT(19), 1},
{"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
{"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
{"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
{"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
{"DISP_SHIM_VNN_REQ_STS", BIT(31), 1},
{}
};
static const struct pmc_bit_map wcl_pcdn_vnn_misc_status_map[] = {
{"CPU_C10_REQ_STS", BIT(0), 0},
{"TS_OFF_REQ_STS", BIT(1), 0},
{"PNDE_MET_REQ_STS", BIT(2), 1},
{"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0},
{"VNN_SOC_REQ_STS", BIT(6), 1},
{"ISH_VNNAON_REQ_STS", BIT(7), 0},
{"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
{"PLT_GREATER_REQ_STS", BIT(11), 1},
{"ALL_SBR_IDLE_REQ_STS", BIT(12), 0},
{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
{"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
{"EA_REQ_STS", BIT(15), 0},
{"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
{"BRK_EV_EN_REQ_STS", BIT(17), 0},
{"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
{"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
{"ARC_IDLE_REQ_STS", BIT(21), 0},
{"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
{"XDCI_ATTACHED_REQ_STS", BIT(24), 1},
{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
{"PRE_WAKE0_REQ_STS", BIT(27), 1},
{"PRE_WAKE1_REQ_STS", BIT(28), 1},
{"PRE_WAKE2_REQ_STS", BIT(29), 1},
{}
};
static const struct pmc_bit_map wcl_pcdn_rsc_status_map[] = {
{"Memory", 0, 1},
{"PSF0", 0, 1},
{"PSF6", 0, 1},
{"PSF8", 0, 1},
{"SAF_CFI_LINK", 0, 1},
{"SB", 0, 1},
{}
};
static const struct pmc_bit_map *wcl_pcdn_lpm_maps[] = {
ptl_pcdp_clocksource_status_map,
wcl_pcdn_power_gating_status_0_map,
wcl_pcdn_power_gating_status_1_map,
wcl_pcdn_power_gating_status_2_map,
wcl_pcdn_d3_status_0_map,
wcl_pcdn_d3_status_1_map,
wcl_pcdn_d3_status_2_map,
wcl_pcdn_d3_status_3_map,
wcl_pcdn_vnn_req_status_0_map,
wcl_pcdn_vnn_req_status_1_map,
wcl_pcdn_vnn_req_status_2_map,
ptl_pcdp_vnn_req_status_3_map,
wcl_pcdn_vnn_misc_status_map,
ptl_pcdp_signal_status_map,
NULL
};
static const struct pmc_bit_map *wcl_pcdn_blk_maps[] = {
wcl_pcdn_power_gating_status_0_map,
wcl_pcdn_power_gating_status_1_map,
wcl_pcdn_power_gating_status_2_map,
wcl_pcdn_rsc_status_map,
wcl_pcdn_vnn_req_status_0_map,
wcl_pcdn_vnn_req_status_1_map,
wcl_pcdn_vnn_req_status_2_map,
ptl_pcdp_vnn_req_status_3_map,
wcl_pcdn_d3_status_0_map,
wcl_pcdn_d3_status_1_map,
wcl_pcdn_d3_status_2_map,
wcl_pcdn_d3_status_3_map,
ptl_pcdp_clocksource_status_map,
wcl_pcdn_vnn_misc_status_map,
ptl_pcdp_signal_status_map,
NULL
};
static const struct pmc_reg_map wcl_pcdn_reg_map = {
.pfear_sts = ext_wcl_pcdn_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
.ltr_show_sts = wcl_pcdn_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = WCL_PCD_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.lpm_num_maps = PTL_LPM_NUM_MAPS,
.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
.etr3_offset = ETR3_OFFSET,
.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
.lpm_en_offset = MTL_LPM_EN_OFFSET,
.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
.lpm_sts = wcl_pcdn_lpm_maps,
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.s0ix_blocker_maps = wcl_pcdn_blk_maps,
.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
.num_s0ix_blocker = WCL_NUM_S0IX_BLOCKER,
.blocker_req_offset = WCL_BLK_REQ_OFFSET,
.lpm_req_guid = PCDN_LPM_REQ_GUID,
};
static struct pmc_info wcl_pmc_info_list[] = {
{
.devid = PMC_DEVID_WCL_PCDN,
.map = &wcl_pcdn_reg_map,
},
{}
};
static const u8 wcl_pmc_list[] = {PMC_IDX_MAIN};
#define WCL_NPU_PCI_DEV 0xfd3e
/*
* Set power state of select devices that do not have drivers to D3
* so that they do not block Package C entry.
*/
static void wcl_d3_fixup(void)
{
pmc_core_set_device_d3(WCL_NPU_PCI_DEV);
}
static int wcl_resume(struct pmc_dev *pmcdev)
{
wcl_d3_fixup();
return cnl_resume(pmcdev);
}
static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
{
wcl_d3_fixup();
return generic_core_init(pmcdev, pmc_dev_info);
}
struct pmc_dev_info wcl_pmc_dev = {
.regmap_list = wcl_pmc_info_list,
.num_pmcs = ARRAY_SIZE(wcl_pmc_list),
.pmc_list = wcl_pmc_list,
.map = &wcl_pcdn_reg_map,
.sub_req_show = &pmc_core_substate_blk_req_fops,
.suspend = cnl_suspend,
.resume = wcl_resume,
.init = wcl_core_init,
.sub_req = pmc_core_pmt_get_blk_sub_req,
.ssram_hidden = true,
};