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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/scsi/qla2xxx/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
config SCSI_QLA_FC
tristate "QLogic QLA2XXX Fibre Channel Support"
depends on PCI && HAS_IOPORT && SCSI
depends on SCSI_FC_ATTRS
depends on NVME_FC || !NVME_FC
select FW_LOADER
select BTREE
help
This qla2xxx driver supports all QLogic Fibre Channel
PCI and PCIe host adapters.
By default, firmware for the ISP parts will be loaded
via the Firmware Loader interface.
ISP Firmware Filename
---------- -----------------
21xx ql2100_fw.bin
22xx ql2200_fw.bin
2300, 2312, 6312 ql2300_fw.bin
2322, 6322 ql2322_fw.bin
24xx, 54xx ql2400_fw.bin
25xx ql2500_fw.bin
Upon request, the driver caches the firmware image until
the driver is unloaded.
Firmware images are included in the linux-firmware tree.
config TCM_QLA2XXX
tristate "TCM_QLA2XXX fabric module for QLogic 24xx+ series target mode HBAs"
depends on SCSI_QLA_FC && TARGET_CORE
depends on LIBFC
select BTREE
default n
help
Say Y here to enable the TCM_QLA2XXX fabric module for QLogic 24xx+
series target mode HBAs.
if TCM_QLA2XXX
config TCM_QLA2XXX_DEBUG
bool "TCM_QLA2XXX fabric module DEBUG mode for QLogic 24xx+ series target mode HBAs"
default n
help
Say Y here to enable the TCM_QLA2XXX fabric module DEBUG for
QLogic 24xx+ series target mode HBAs.
This will include code to enable the SCSI command jammer.
endif
linux-7.2.3/drivers/scsi/qla2xxx/Makefile
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# SPDX-License-Identifier: GPL-2.0
qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \
qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o qla_bsg.o \
qla_nx.o qla_mr.o qla_nx2.o qla_target.o qla_tmpl.o qla_nvme.o \
qla_edif.o
obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx.o
obj-$(CONFIG_TCM_QLA2XXX) += tcm_qla2xxx.o
linux-7.2.3/drivers/scsi/qla2xxx/qla_attr.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_bsg.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_bsg.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#ifndef __QLA_BSG_H
#define __QLA_BSG_H
/* BSG Vendor specific commands */
#define QL_VND_LOOPBACK 0x01
#define QL_VND_A84_RESET 0x02
#define QL_VND_A84_UPDATE_FW 0x03
#define QL_VND_A84_MGMT_CMD 0x04
#define QL_VND_IIDMA 0x05
#define QL_VND_FCP_PRIO_CFG_CMD 0x06
#define QL_VND_READ_FLASH 0x07
#define QL_VND_UPDATE_FLASH 0x08
#define QL_VND_SET_FRU_VERSION 0x0B
#define QL_VND_READ_FRU_STATUS 0x0C
#define QL_VND_WRITE_FRU_STATUS 0x0D
#define QL_VND_DIAG_IO_CMD 0x0A
#define QL_VND_WRITE_I2C 0x10
#define QL_VND_READ_I2C 0x11
#define QL_VND_FX00_MGMT_CMD 0x12
#define QL_VND_SERDES_OP 0x13
#define QL_VND_SERDES_OP_EX 0x14
#define QL_VND_GET_FLASH_UPDATE_CAPS 0x15
#define QL_VND_SET_FLASH_UPDATE_CAPS 0x16
#define QL_VND_GET_BBCR_DATA 0x17
#define QL_VND_GET_PRIV_STATS 0x18
#define QL_VND_DPORT_DIAGNOSTICS 0x19
#define QL_VND_GET_PRIV_STATS_EX 0x1A
#define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E
#define QL_VND_EDIF_MGMT 0X1F
#define QL_VND_GET_DRV_ATTR 0x22
#define QL_VND_MANAGE_HOST_STATS 0x23
#define QL_VND_GET_HOST_STATS 0x24
#define QL_VND_GET_TGT_STATS 0x25
#define QL_VND_MANAGE_HOST_PORT 0x26
#define QL_VND_MBX_PASSTHRU 0x2B
#define QL_VND_DPORT_DIAGNOSTICS_V2 0x2C
#define QL_VND_IMG_SET_VALID 0x30
/* BSG Vendor specific subcode returns */
#define EXT_STATUS_OK 0
#define EXT_STATUS_ERR 1
#define EXT_STATUS_BUSY 2
#define EXT_STATUS_INVALID_PARAM 6
#define EXT_STATUS_DATA_OVERRUN 7
#define EXT_STATUS_DATA_UNDERRUN 8
#define EXT_STATUS_MAILBOX 11
#define EXT_STATUS_BUFFER_TOO_SMALL 16
#define EXT_STATUS_NO_MEMORY 17
#define EXT_STATUS_DEVICE_OFFLINE 22
#define EXT_STATUS_IMG_SET_VALID_ERR 47
#define EXT_STATUS_IMG_SET_CONFIG_ERR 48
/*
* To support bidirectional iocb
* BSG Vendor specific returns
*/
#define EXT_STATUS_NOT_SUPPORTED 27
#define EXT_STATUS_INVALID_CFG 28
#define EXT_STATUS_DMA_ERR 29
#define EXT_STATUS_TIMEOUT 30
#define EXT_STATUS_THREAD_FAILED 31
#define EXT_STATUS_DATA_CMP_FAILED 32
#define EXT_STATUS_DPORT_DIAG_ERR 40
#define EXT_STATUS_DPORT_DIAG_IN_PROCESS 41
#define EXT_STATUS_DPORT_DIAG_NOT_RUNNING 42
/* BSG definations for interpreting CommandSent field */
#define INT_DEF_LB_LOOPBACK_CMD 0
#define INT_DEF_LB_ECHO_CMD 1
/* Loopback related definations */
#define INTERNAL_LOOPBACK 0xF1
#define EXTERNAL_LOOPBACK 0xF2
#define ENABLE_INTERNAL_LOOPBACK 0x02
#define ENABLE_EXTERNAL_LOOPBACK 0x04
#define INTERNAL_LOOPBACK_MASK 0x000E
#define MAX_ELS_FRAME_PAYLOAD 252
#define ELS_OPCODE_BYTE 0x10
/* BSG Vendor specific definations */
#define A84_ISSUE_WRITE_TYPE_CMD 0
#define A84_ISSUE_READ_TYPE_CMD 1
#define A84_CLEANUP_CMD 2
#define A84_ISSUE_RESET_OP_FW 3
#define A84_ISSUE_RESET_DIAG_FW 4
#define A84_ISSUE_UPDATE_OPFW_CMD 5
#define A84_ISSUE_UPDATE_DIAGFW_CMD 6
struct qla84_mgmt_param {
union {
struct {
uint32_t start_addr;
} mem; /* for QLA84_MGMT_READ/WRITE_MEM */
struct {
uint32_t id;
#define QLA84_MGMT_CONFIG_ID_UIF 1
#define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
#define QLA84_MGMT_CONFIG_ID_PAUSE 3
#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
uint32_t param0;
uint32_t param1;
} config; /* for QLA84_MGMT_CHNG_CONFIG */
struct {
uint32_t type;
#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
uint32_t context;
/*
* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
*/
#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
/*
* context definitions for QLA84_MGMT_INFO_PORT_STAT
*/
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
/*
* context definitions for QLA84_MGMT_INFO_LIF_STAT
*/
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
} info; /* for QLA84_MGMT_GET_INFO */
} u;
};
struct qla84_msg_mgmt {
uint16_t cmd;
#define QLA84_MGMT_READ_MEM 0x00
#define QLA84_MGMT_WRITE_MEM 0x01
#define QLA84_MGMT_CHNG_CONFIG 0x02
#define QLA84_MGMT_GET_INFO 0x03
uint16_t rsrvd;
struct qla84_mgmt_param mgmtp;/* parameters for cmd */
uint32_t len; /* bytes in payload following this struct */
uint8_t payload[]; /* payload for cmd */
};
struct qla_bsg_a84_mgmt {
struct qla84_msg_mgmt mgmt;
} __attribute__ ((packed));
struct qla_scsi_addr {
uint16_t bus;
uint16_t target;
} __attribute__ ((packed));
struct qla_ext_dest_addr {
union {
uint8_t wwnn[8];
uint8_t wwpn[8];
uint8_t id[4];
struct qla_scsi_addr scsi_addr;
} dest_addr;
uint16_t dest_type;
#define EXT_DEF_TYPE_WWPN 2
uint16_t lun;
uint16_t padding[2];
} __attribute__ ((packed));
struct qla_port_param {
struct qla_ext_dest_addr fc_scsi_addr;
uint16_t mode;
uint16_t speed;
} __attribute__ ((packed));
struct qla_mbx_passthru {
uint16_t reserved1[2];
uint16_t mbx_in[32];
uint16_t mbx_out[32];
uint32_t reserved2[16];
} __packed;
/* FRU VPD */
#define MAX_FRU_SIZE 36
struct qla_field_address {
uint16_t offset;
uint16_t device;
uint16_t option;
} __packed;
struct qla_field_info {
uint8_t version[MAX_FRU_SIZE];
} __packed;
struct qla_image_version {
struct qla_field_address field_address;
struct qla_field_info field_info;
} __packed;
struct qla_image_version_list {
uint32_t count;
struct qla_image_version version[];
} __packed;
struct qla_status_reg {
struct qla_field_address field_address;
uint8_t status_reg;
uint8_t reserved[7];
} __packed;
struct qla_i2c_access {
uint16_t device;
uint16_t offset;
uint16_t option;
uint16_t length;
uint8_t buffer[0x40];
} __packed;
/* 26xx serdes register interface */
/* serdes reg commands */
#define INT_SC_SERDES_READ_REG 1
#define INT_SC_SERDES_WRITE_REG 2
struct qla_serdes_reg {
uint16_t cmd;
uint16_t addr;
uint16_t val;
} __packed;
struct qla_serdes_reg_ex {
uint16_t cmd;
uint32_t addr;
uint32_t val;
} __packed;
struct qla_flash_update_caps {
uint64_t capabilities;
uint32_t outage_duration;
uint8_t reserved[20];
} __packed;
/* BB_CR Status */
#define QLA_BBCR_STATUS_DISABLED 0
#define QLA_BBCR_STATUS_ENABLED 1
#define QLA_BBCR_STATUS_UNKNOWN 2
/* BB_CR State */
#define QLA_BBCR_STATE_OFFLINE 0
#define QLA_BBCR_STATE_ONLINE 1
/* BB_CR Offline Reason Code */
#define QLA_BBCR_REASON_PORT_SPEED 1
#define QLA_BBCR_REASON_PEER_PORT 2
#define QLA_BBCR_REASON_SWITCH 3
#define QLA_BBCR_REASON_LOGIN_REJECT 4
struct qla_bbcr_data {
uint8_t status; /* 1 - enabled, 0 - Disabled */
uint8_t state; /* 1 - online, 0 - offline */
uint8_t configured_bbscn; /* 0-15 */
uint8_t negotiated_bbscn; /* 0-15 */
uint8_t offline_reason_code;
uint16_t mbx1; /* Port state */
uint8_t reserved[9];
} __packed;
struct qla_dport_diag {
uint16_t options;
uint32_t buf[16];
uint8_t unused[62];
} __packed;
#define QLA_GET_DPORT_RESULT_V2 0 /* Get Result */
#define QLA_RESTART_DPORT_TEST_V2 1 /* Restart test */
#define QLA_START_DPORT_TEST_V2 2 /* Start test */
struct qla_dport_diag_v2 {
uint16_t options;
uint16_t mbx1;
uint16_t mbx2;
uint8_t unused[58];
uint8_t buf[1024]; /* Test Result */
} __packed;
/* D_Port options */
#define QLA_DPORT_RESULT 0x0
#define QLA_DPORT_START 0x2
/* active images in flash */
struct qla_active_regions {
uint8_t global_image;
uint8_t board_config;
uint8_t vpd_nvram;
uint8_t npiv_config_0_1;
uint8_t npiv_config_2_3;
uint8_t nvme_params;
uint8_t reserved[31];
} __packed;
struct qla_drv_attr {
uint32_t attributes;
u32 ext_attributes;
#define QLA_IMG_SET_VALID_SUPPORT BIT_4
u32 status_flags;
uint8_t reserved[20];
} __packed;
#include "qla_edif_bsg.h"
#endif
linux-7.2.3/drivers/scsi/qla2xxx/qla_dbg.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_dbg.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#include "qla_def.h"
/*
* Firmware Dump structure definition
*/
struct qla2300_fw_dump {
__be16 hccr;
__be16 pbiu_reg[8];
__be16 risc_host_reg[8];
__be16 mailbox_reg[32];
__be16 resp_dma_reg[32];
__be16 dma_reg[48];
__be16 risc_hdw_reg[16];
__be16 risc_gp0_reg[16];
__be16 risc_gp1_reg[16];
__be16 risc_gp2_reg[16];
__be16 risc_gp3_reg[16];
__be16 risc_gp4_reg[16];
__be16 risc_gp5_reg[16];
__be16 risc_gp6_reg[16];
__be16 risc_gp7_reg[16];
__be16 frame_buf_hdw_reg[64];
__be16 fpm_b0_reg[64];
__be16 fpm_b1_reg[64];
__be16 risc_ram[0xf800];
__be16 stack_ram[0x1000];
__be16 data_ram[1];
};
struct qla2100_fw_dump {
__be16 hccr;
__be16 pbiu_reg[8];
__be16 mailbox_reg[32];
__be16 dma_reg[48];
__be16 risc_hdw_reg[16];
__be16 risc_gp0_reg[16];
__be16 risc_gp1_reg[16];
__be16 risc_gp2_reg[16];
__be16 risc_gp3_reg[16];
__be16 risc_gp4_reg[16];
__be16 risc_gp5_reg[16];
__be16 risc_gp6_reg[16];
__be16 risc_gp7_reg[16];
__be16 frame_buf_hdw_reg[16];
__be16 fpm_b0_reg[64];
__be16 fpm_b1_reg[64];
__be16 risc_ram[0xf000];
u8 queue_dump[];
};
struct qla24xx_fw_dump {
__be32 host_status;
__be32 host_reg[32];
__be32 shadow_reg[7];
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[128];
__be32 xseq_0_reg[16];
__be32 xseq_1_reg[16];
__be32 rseq_gp_reg[128];
__be32 rseq_0_reg[16];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 cmd_dma_reg[16];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[112];
__be32 fpm_hdw_reg[192];
__be32 fb_hdw_reg[176];
__be32 code_ram[0x2000];
__be32 ext_mem[1];
};
struct qla25xx_fw_dump {
__be32 host_status;
__be32 host_risc_reg[32];
__be32 pcie_regs[4];
__be32 host_reg[32];
__be32 shadow_reg[11];
__be32 risc_io_reg;
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[128];
__be32 xseq_0_reg[48];
__be32 xseq_1_reg[16];
__be32 rseq_gp_reg[128];
__be32 rseq_0_reg[32];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 aseq_gp_reg[128];
__be32 aseq_0_reg[32];
__be32 aseq_1_reg[16];
__be32 aseq_2_reg[16];
__be32 cmd_dma_reg[16];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[128];
__be32 fpm_hdw_reg[192];
__be32 fb_hdw_reg[192];
__be32 code_ram[0x2000];
__be32 ext_mem[1];
};
struct qla81xx_fw_dump {
__be32 host_status;
__be32 host_risc_reg[32];
__be32 pcie_regs[4];
__be32 host_reg[32];
__be32 shadow_reg[11];
__be32 risc_io_reg;
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[128];
__be32 xseq_0_reg[48];
__be32 xseq_1_reg[16];
__be32 rseq_gp_reg[128];
__be32 rseq_0_reg[32];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 aseq_gp_reg[128];
__be32 aseq_0_reg[32];
__be32 aseq_1_reg[16];
__be32 aseq_2_reg[16];
__be32 cmd_dma_reg[16];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[128];
__be32 fpm_hdw_reg[224];
__be32 fb_hdw_reg[208];
__be32 code_ram[0x2000];
__be32 ext_mem[1];
};
struct qla83xx_fw_dump {
__be32 host_status;
__be32 host_risc_reg[48];
__be32 pcie_regs[4];
__be32 host_reg[32];
__be32 shadow_reg[11];
__be32 risc_io_reg;
__be16 mailbox_reg[32];
__be32 xseq_gp_reg[256];
__be32 xseq_0_reg[48];
__be32 xseq_1_reg[16];
__be32 xseq_2_reg[16];
__be32 rseq_gp_reg[256];
__be32 rseq_0_reg[32];
__be32 rseq_1_reg[16];
__be32 rseq_2_reg[16];
__be32 rseq_3_reg[16];
__be32 aseq_gp_reg[256];
__be32 aseq_0_reg[32];
__be32 aseq_1_reg[16];
__be32 aseq_2_reg[16];
__be32 aseq_3_reg[16];
__be32 cmd_dma_reg[64];
__be32 req0_dma_reg[15];
__be32 resp0_dma_reg[15];
__be32 req1_dma_reg[15];
__be32 xmt0_dma_reg[32];
__be32 xmt1_dma_reg[32];
__be32 xmt2_dma_reg[32];
__be32 xmt3_dma_reg[32];
__be32 xmt4_dma_reg[32];
__be32 xmt_data_dma_reg[16];
__be32 rcvt0_data_dma_reg[32];
__be32 rcvt1_data_dma_reg[32];
__be32 risc_gp_reg[128];
__be32 lmc_reg[128];
__be32 fpm_hdw_reg[256];
__be32 rq0_array_reg[256];
__be32 rq1_array_reg[256];
__be32 rp0_array_reg[256];
__be32 rp1_array_reg[256];
__be32 queue_control_reg[16];
__be32 fb_hdw_reg[432];
__be32 at0_array_reg[128];
__be32 code_ram[0x2400];
__be32 ext_mem[1];
};
#define EFT_NUM_BUFFERS 4
#define EFT_BYTES_PER_BUFFER 0x4000
#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
#define FCE_NUM_BUFFERS 64
#define FCE_BYTES_PER_BUFFER 0x400
#define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
struct qla2xxx_fce_chain {
__be32 type;
__be32 chain_size;
__be32 size;
__be32 addr_l;
__be32 addr_h;
__be32 eregs[8];
};
/* used by exchange off load and extended login offload */
struct qla2xxx_offld_chain {
__be32 type;
__be32 chain_size;
__be32 size;
__be32 reserved;
__be64 addr;
};
struct qla2xxx_mq_chain {
__be32 type;
__be32 chain_size;
__be32 count;
__be32 qregs[4 * QLA_MQ_SIZE];
};
struct qla2xxx_mqueue_header {
__be32 queue;
#define TYPE_REQUEST_QUEUE 0x1
#define TYPE_RESPONSE_QUEUE 0x2
#define TYPE_ATIO_QUEUE 0x3
__be32 number;
__be32 size;
};
struct qla2xxx_mqueue_chain {
__be32 type;
__be32 chain_size;
};
#define DUMP_CHAIN_VARIANT 0x80000000
#define DUMP_CHAIN_FCE 0x7FFFFAF0
#define DUMP_CHAIN_MQ 0x7FFFFAF1
#define DUMP_CHAIN_QUEUE 0x7FFFFAF2
#define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3
#define DUMP_CHAIN_EXCHG 0x7FFFFAF4
#define DUMP_CHAIN_LAST 0x80000000
struct qla2xxx_fw_dump {
uint8_t signature[4];
__be32 version;
__be32 fw_major_version;
__be32 fw_minor_version;
__be32 fw_subminor_version;
__be32 fw_attributes;
__be32 vendor;
__be32 device;
__be32 subsystem_vendor;
__be32 subsystem_device;
__be32 fixed_size;
__be32 mem_size;
__be32 req_q_size;
__be32 rsp_q_size;
__be32 eft_size;
__be32 eft_addr_l;
__be32 eft_addr_h;
__be32 header_size;
union {
struct qla2100_fw_dump isp21;
struct qla2300_fw_dump isp23;
struct qla24xx_fw_dump isp24;
struct qla25xx_fw_dump isp25;
struct qla81xx_fw_dump isp81;
struct qla83xx_fw_dump isp83;
} isp;
};
#define QL_MSGHDR "qla2xxx"
#define QL_DBG_DEFAULT1_MASK 0x1e600000
#define ql_log_fatal 0 /* display fatal errors */
#define ql_log_warn 1 /* display critical errors */
#define ql_log_info 2 /* display all recovered errors */
#define ql_log_all 3 /* This value is only used by ql_errlev.
* No messages will use this value.
* This should be always highest value
* as compared to other log levels.
*/
extern uint ql_errlev;
void __attribute__((format (printf, 4, 5)))
ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
/* Debug Levels */
/* The 0x40000000 is the max value any debug level can have
* as ql2xextended_error_logging is of type signed int
*/
#define ql_dbg_init 0x40000000 /* Init Debug */
#define ql_dbg_mbx 0x20000000 /* MBX Debug */
#define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
#define ql_dbg_io 0x08000000 /* IO Tracing Debug */
#define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
#define ql_dbg_async 0x02000000 /* Async events Debug */
#define ql_dbg_timer 0x01000000 /* Timer Debug */
#define ql_dbg_user 0x00800000 /* User Space Interations Debug */
#define ql_dbg_taskm 0x00400000 /* Task Management Debug */
#define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
#define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
#define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
#define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
#define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
#define ql_dbg_misc 0x00010000 /* For dumping everything that is not
* not covered by upper categories
*/
#define ql_dbg_verbose 0x00008000 /* More verbosity for each level
* This is to be used with other levels where
* more verbosity is required. It might not
* be applicable to all the levels.
*/
#define ql_dbg_tgt 0x00004000 /* Target mode */
#define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
#define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
#define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */
#define ql_dbg_edif 0x00000400 /* edif and purex debug */
#define ql_dbg_unsol 0x00000100 /* Unsolicited path debug */
extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
uint32_t, void **);
extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *,
uint32_t, void **);
extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
struct qla_hw_data *);
extern int qla24xx_soft_reset(struct qla_hw_data *);
static inline int
ql_mask_match(uint level)
{
if (ql2xextended_error_logging == 1)
ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
return level && ((level & ql2xextended_error_logging) == level);
}
static inline int
ql_mask_match_ext(uint level, int *log_tunable)
{
if (*log_tunable == 1)
*log_tunable = QL_DBG_DEFAULT1_MASK;
return (level & *log_tunable) == level;
}
/* Assumes local variable pbuf and pbuf_ready present. */
#define ql_ktrace(dbg_msg, level, pbuf, pdev, vha, id, fmt) do { \
struct va_format _vaf; \
va_list _va; \
u32 dbg_off = dbg_msg ? ql_dbg_offset : 0; \
\
pbuf[0] = 0; \
if (!trace_ql_dbg_log_enabled()) \
break; \
\
if (dbg_msg && !ql_mask_match_ext(level, \
&ql2xextended_error_logging_ktrace)) \
break; \
\
ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), pdev, vha, id + dbg_off); \
\
va_start(_va, fmt); \
_vaf.fmt = fmt; \
_vaf.va = &_va; \
\
trace_ql_dbg_log(pbuf, &_vaf); \
\
va_end(_va); \
} while (0)
#define QLA_ENABLE_KERNEL_TRACING
#ifdef QLA_ENABLE_KERNEL_TRACING
#define QLA_TRACE_ENABLE(_tr) \
trace_array_set_clr_event(_tr, "qla", NULL, true)
#else /* QLA_ENABLE_KERNEL_TRACING */
#define QLA_TRACE_ENABLE(_tr)
#endif /* QLA_ENABLE_KERNEL_TRACING */
linux-7.2.3/drivers/scsi/qla2xxx/qla_def.h
+5600
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/scsi/qla2xxx/qla_devtbl.h
+100
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@@ -0,0 +1,100 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define QLA_MODEL_NAMES 0x5C
/*
* Adapter model names and descriptions.
*/
static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
"QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
"QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
"QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
"QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
"QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
"QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
"QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
"QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
"QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
"QCP2340", "cPCI to 2Gb FC, Single Channel", /* 0x109 */
"QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
"QCP2342", "Sun - cPCI to 2Gb FC, Dual Channel", /* 0x10b */
"QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
"QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
"QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
" ", " ", /* 0x10f */
" ", " ", /* 0x110 */
" ", " ", /* 0x111 */
" ", " ", /* 0x112 */
" ", " ", /* 0x113 */
" ", " ", /* 0x114 */
"QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
"QLA2362", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x116 */
"QLE2360", "PCI-Express to 2Gb FC, Single Channel", /* 0x117 */
"QLE2362", "PCI-Express to 2Gb FC, Dual Channel", /* 0x118 */
"QLA200", "133MHz PCI-X to 2Gb FC Optical", /* 0x119 */
" ", " ", /* 0x11a */
" ", " ", /* 0x11b */
"QLA200P", "133MHz PCI-X to 2Gb FC SFP", /* 0x11c */
" ", " ", /* 0x11d */
" ", " ", /* 0x11e */
" ", " ", /* 0x11f */
" ", " ", /* 0x120 */
" ", " ", /* 0x121 */
" ", " ", /* 0x122 */
" ", " ", /* 0x123 */
" ", " ", /* 0x124 */
" ", " ", /* 0x125 */
" ", " ", /* 0x126 */
" ", " ", /* 0x127 */
" ", " ", /* 0x128 */
" ", " ", /* 0x129 */
" ", " ", /* 0x12a */
" ", " ", /* 0x12b */
" ", " ", /* 0x12c */
" ", " ", /* 0x12d */
" ", " ", /* 0x12e */
"QLA210", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x12f */
"EMC 250", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x130 */
"HP A7538A", "HP 1p2g PCI-X to 2Gb FC, Single Channel", /* 0x131 */
"QLA210", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x132 */
"QLA2460", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x133 */
"QLA2462", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x134 */
"QMC2462", "IBM eServer BC 4Gb FC Expansion Card", /* 0x135 */
"QMC2462S", "IBM eServer BC 4Gb FC Expansion Card SFF", /* 0x136 */
"QLE2460", "PCI-Express to 4Gb FC, Single Channel", /* 0x137 */
"QLE2462", "PCI-Express to 4Gb FC, Dual Channel", /* 0x138 */
"QME2462", "Dell BS PCI-Express to 4Gb FC, Dual Channel", /* 0x139 */
" ", " ", /* 0x13a */
" ", " ", /* 0x13b */
" ", " ", /* 0x13c */
"QEM2462", "Sun Server I/O Module 4Gb FC, Dual Channel", /* 0x13d */
"QLE210", "PCI-Express to 2Gb FC, Single Channel", /* 0x13e */
"QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x13f */
"QLA2460", "Sun PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x140 */
"QLA2462", "Sun PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x141 */
"QLE2460", "Sun PCI-Express to 2Gb FC, Single Channel", /* 0x142 */
"QLE2462", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x143 */
"QEM2462", "Server I/O Module 4Gb FC, Dual Channel", /* 0x144 */
"QLE2440", "PCI-Express to 4Gb FC, Single Channel", /* 0x145 */
"QLE2464", "PCI-Express to 4Gb FC, Quad Channel", /* 0x146 */
"QLA2440", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x147 */
"HP AE369A", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x148 */
"QLA2340", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x149 */
" ", " ", /* 0x14a */
" ", " ", /* 0x14b */
"QMC2432M", "IBM eServer BC 4Gb FC Expansion Card CFFE", /* 0x14c */
"QMC2422M", "IBM eServer BC 4Gb FC Expansion Card CFFX", /* 0x14d */
"QLE220", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x14e */
" ", " ", /* 0x14f */
" ", " ", /* 0x150 */
" ", " ", /* 0x151 */
"QME2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x152 */
"QMH2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x153 */
" ", " ", /* 0x154 */
"QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x155 */
"QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x156 */
" ", " ", /* 0x157 */
" ", " ", /* 0x158 */
" ", " ", /* 0x159 */
" ", " ", /* 0x15a */
"QME2472", "Dell BS PCI-Express to 4Gb FC, Dual Channel", /* 0x15b */
};
linux-7.2.3/drivers/scsi/qla2xxx/qla_dfs.c
+807
View File
@@ -0,0 +1,807 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#include "qla_def.h"
#include <linux/debugfs.h>
#include <linux/seq_file.h>
static struct dentry *qla2x00_dfs_root;
static atomic_t qla2x00_dfs_root_count;
#define QLA_DFS_RPORT_DEVLOSS_TMO 1
static int
qla_dfs_rport_get(struct fc_port *fp, int attr_id, u64 *val)
{
switch (attr_id) {
case QLA_DFS_RPORT_DEVLOSS_TMO:
/* Only supported for FC-NVMe devices that are registered. */
if (!(fp->nvme_flag & NVME_FLAG_REGISTERED))
return -EIO;
*val = fp->nvme_remote_port->dev_loss_tmo;
break;
default:
return -EINVAL;
}
return 0;
}
static int
qla_dfs_rport_set(struct fc_port *fp, int attr_id, u64 val)
{
switch (attr_id) {
case QLA_DFS_RPORT_DEVLOSS_TMO:
/* Only supported for FC-NVMe devices that are registered. */
if (!(fp->nvme_flag & NVME_FLAG_REGISTERED))
return -EIO;
#if (IS_ENABLED(CONFIG_NVME_FC))
return nvme_fc_set_remoteport_devloss(fp->nvme_remote_port,
val);
#else /* CONFIG_NVME_FC */
return -EINVAL;
#endif /* CONFIG_NVME_FC */
default:
return -EINVAL;
}
return 0;
}
#define DEFINE_QLA_DFS_RPORT_RW_ATTR(_attr_id, _attr) \
static int qla_dfs_rport_##_attr##_get(void *data, u64 *val) \
{ \
struct fc_port *fp = data; \
return qla_dfs_rport_get(fp, _attr_id, val); \
} \
static int qla_dfs_rport_##_attr##_set(void *data, u64 val) \
{ \
struct fc_port *fp = data; \
return qla_dfs_rport_set(fp, _attr_id, val); \
} \
DEFINE_DEBUGFS_ATTRIBUTE(qla_dfs_rport_##_attr##_fops, \
qla_dfs_rport_##_attr##_get, \
qla_dfs_rport_##_attr##_set, "%llu\n")
/*
* Wrapper for getting fc_port fields.
*
* _attr : Attribute name.
* _get_val : Accessor macro to retrieve the value.
*/
#define DEFINE_QLA_DFS_RPORT_FIELD_GET(_attr, _get_val) \
static int qla_dfs_rport_field_##_attr##_get(void *data, u64 *val) \
{ \
struct fc_port *fp = data; \
*val = _get_val; \
return 0; \
} \
DEFINE_DEBUGFS_ATTRIBUTE(qla_dfs_rport_field_##_attr##_fops, \
qla_dfs_rport_field_##_attr##_get, \
NULL, "%llu\n")
#define DEFINE_QLA_DFS_RPORT_ACCESS(_attr, _get_val) \
DEFINE_QLA_DFS_RPORT_FIELD_GET(_attr, _get_val)
#define DEFINE_QLA_DFS_RPORT_FIELD(_attr) \
DEFINE_QLA_DFS_RPORT_FIELD_GET(_attr, fp->_attr)
DEFINE_QLA_DFS_RPORT_RW_ATTR(QLA_DFS_RPORT_DEVLOSS_TMO, dev_loss_tmo);
DEFINE_QLA_DFS_RPORT_FIELD(disc_state);
DEFINE_QLA_DFS_RPORT_FIELD(scan_state);
DEFINE_QLA_DFS_RPORT_FIELD(fw_login_state);
DEFINE_QLA_DFS_RPORT_FIELD(login_pause);
DEFINE_QLA_DFS_RPORT_FIELD(flags);
DEFINE_QLA_DFS_RPORT_FIELD(nvme_flag);
DEFINE_QLA_DFS_RPORT_FIELD(last_rscn_gen);
DEFINE_QLA_DFS_RPORT_FIELD(rscn_gen);
DEFINE_QLA_DFS_RPORT_FIELD(login_gen);
DEFINE_QLA_DFS_RPORT_FIELD(loop_id);
DEFINE_QLA_DFS_RPORT_FIELD_GET(port_id, fp->d_id.b24);
DEFINE_QLA_DFS_RPORT_FIELD_GET(sess_kref, kref_read(&fp->sess_kref));
void
qla2x00_dfs_create_rport(scsi_qla_host_t *vha, struct fc_port *fp)
{
char wwn[32];
#define QLA_CREATE_RPORT_FIELD_ATTR(_attr) \
debugfs_create_file(#_attr, 0400, fp->dfs_rport_dir, \
fp, &qla_dfs_rport_field_##_attr##_fops)
if (!vha->dfs_rport_root || fp->dfs_rport_dir)
return;
sprintf(wwn, "pn-%016llx", wwn_to_u64(fp->port_name));
fp->dfs_rport_dir = debugfs_create_dir(wwn, vha->dfs_rport_root);
if (IS_ERR(fp->dfs_rport_dir))
return;
if (NVME_TARGET(vha->hw, fp))
debugfs_create_file("dev_loss_tmo", 0600, fp->dfs_rport_dir,
fp, &qla_dfs_rport_dev_loss_tmo_fops);
QLA_CREATE_RPORT_FIELD_ATTR(disc_state);
QLA_CREATE_RPORT_FIELD_ATTR(scan_state);
QLA_CREATE_RPORT_FIELD_ATTR(fw_login_state);
QLA_CREATE_RPORT_FIELD_ATTR(login_pause);
QLA_CREATE_RPORT_FIELD_ATTR(flags);
QLA_CREATE_RPORT_FIELD_ATTR(nvme_flag);
QLA_CREATE_RPORT_FIELD_ATTR(last_rscn_gen);
QLA_CREATE_RPORT_FIELD_ATTR(rscn_gen);
QLA_CREATE_RPORT_FIELD_ATTR(login_gen);
QLA_CREATE_RPORT_FIELD_ATTR(loop_id);
QLA_CREATE_RPORT_FIELD_ATTR(port_id);
QLA_CREATE_RPORT_FIELD_ATTR(sess_kref);
}
void
qla2x00_dfs_remove_rport(scsi_qla_host_t *vha, struct fc_port *fp)
{
if (!vha->dfs_rport_root || !fp->dfs_rport_dir)
return;
debugfs_remove_recursive(fp->dfs_rport_dir);
fp->dfs_rport_dir = NULL;
}
static int
qla2x00_dfs_tgt_sess_show(struct seq_file *s, void *unused)
{
scsi_qla_host_t *vha = s->private;
struct qla_hw_data *ha = vha->hw;
unsigned long flags;
struct fc_port *sess = NULL;
struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
seq_printf(s, "%s\n", vha->host_str);
if (tgt) {
seq_puts(s, "Port ID Port Name Handle\n");
spin_lock_irqsave(&ha->tgt.sess_lock, flags);
list_for_each_entry(sess, &vha->vp_fcports, list)
seq_printf(s, "%02x:%02x:%02x %8phC %d\n",
sess->d_id.b.domain, sess->d_id.b.area,
sess->d_id.b.al_pa, sess->port_name,
sess->loop_id);
spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(qla2x00_dfs_tgt_sess);
static int
qla2x00_dfs_tgt_port_database_show(struct seq_file *s, void *unused)
{
scsi_qla_host_t *vha = s->private;
struct qla_hw_data *ha = vha->hw;
struct gid_list_info *gid_list;
dma_addr_t gid_list_dma;
char *id_iter;
int rc, i;
uint16_t entries;
seq_printf(s, "%s\n", vha->host_str);
gid_list = dma_alloc_coherent(&ha->pdev->dev,
qla2x00_gid_list_size(ha),
&gid_list_dma, GFP_KERNEL);
if (!gid_list) {
ql_dbg(ql_dbg_user, vha, 0x7018,
"DMA allocation failed for %u\n",
qla2x00_gid_list_size(ha));
return 0;
}
rc = qla24xx_gidlist_wait(vha, gid_list, gid_list_dma,
&entries);
if (rc != QLA_SUCCESS)
goto out_free_id_list;
id_iter = (char *)gid_list;
seq_puts(s, "Port Name Port ID Loop ID\n");
for (i = 0; i < entries; i++) {
struct gid_list_info *gid = (struct gid_list_info *)id_iter;
rc = qla24xx_print_fc_port_id(vha, s, le16_to_cpu(gid->loop_id));
if (rc != QLA_SUCCESS)
break;
id_iter += ha->gid_list_info_size;
}
out_free_id_list:
dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
gid_list, gid_list_dma);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(qla2x00_dfs_tgt_port_database);
static int
qla_dfs_fw_resource_cnt_show(struct seq_file *s, void *unused)
{
struct scsi_qla_host *vha = s->private;
uint16_t mb[MAX_IOCB_MB_REG];
int rc;
struct qla_hw_data *ha = vha->hw;
u16 iocbs_used, i, exch_used;
rc = qla24xx_res_count_wait(vha, mb, SIZEOF_IOCB_MB_REG);
if (rc != QLA_SUCCESS) {
seq_printf(s, "Mailbox Command failed %d, mb %#x", rc, mb[0]);
} else {
seq_puts(s, "FW Resource count\n\n");
seq_printf(s, "Original TGT exchg count[%d]\n", mb[1]);
seq_printf(s, "Current TGT exchg count[%d]\n", mb[2]);
seq_printf(s, "Current Initiator Exchange count[%d]\n", mb[3]);
seq_printf(s, "Original Initiator Exchange count[%d]\n", mb[6]);
seq_printf(s, "Current IOCB count[%d]\n", mb[7]);
seq_printf(s, "Original IOCB count[%d]\n", mb[10]);
seq_printf(s, "MAX VP count[%d]\n", mb[11]);
seq_printf(s, "MAX FCF count[%d]\n", mb[12]);
seq_printf(s, "Current free pageable XCB buffer cnt[%d]\n",
mb[20]);
seq_printf(s, "Original Initiator fast XCB buffer cnt[%d]\n",
mb[21]);
seq_printf(s, "Current free Initiator fast XCB buffer cnt[%d]\n",
mb[22]);
seq_printf(s, "Original Target fast XCB buffer cnt[%d]\n",
mb[23]);
}
if (ql2xenforce_iocb_limit) {
/* lock is not require. It's an estimate. */
iocbs_used = ha->base_qpair->fwres.iocbs_used;
exch_used = ha->base_qpair->fwres.exch_used;
for (i = 0; i < ha->max_qpairs; i++) {
if (ha->queue_pair_map[i]) {
iocbs_used += ha->queue_pair_map[i]->fwres.iocbs_used;
exch_used += ha->queue_pair_map[i]->fwres.exch_used;
}
}
seq_printf(s, "Driver: estimate iocb used [%d] high water limit [%d]\n",
iocbs_used, ha->base_qpair->fwres.iocbs_limit);
seq_printf(s, "estimate exchange used[%d] high water limit [%d]\n",
exch_used, ha->base_qpair->fwres.exch_limit);
if (ql2xenforce_iocb_limit == 2) {
iocbs_used = atomic_read(&ha->fwres.iocb_used);
exch_used = atomic_read(&ha->fwres.exch_used);
seq_printf(s, " estimate iocb2 used [%d] high water limit [%d]\n",
iocbs_used, ha->fwres.iocb_limit);
seq_printf(s, " estimate exchange2 used[%d] high water limit [%d] \n",
exch_used, ha->fwres.exch_limit);
}
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(qla_dfs_fw_resource_cnt);
static int
qla_dfs_tgt_counters_show(struct seq_file *s, void *unused)
{
struct scsi_qla_host *vha = s->private;
struct qla_qpair *qpair = vha->hw->base_qpair;
uint64_t qla_core_sbt_cmd, core_qla_que_buf, qla_core_ret_ctio,
core_qla_snd_status, qla_core_ret_sta_ctio, core_qla_free_cmd,
num_q_full_sent, num_alloc_iocb_failed, num_term_xchg_sent;
u16 i;
fc_port_t *fcport = NULL;
if (qla2x00_chip_is_down(vha))
return 0;
qla_core_sbt_cmd = qpair->tgt_counters.qla_core_sbt_cmd;
core_qla_que_buf = qpair->tgt_counters.core_qla_que_buf;
qla_core_ret_ctio = qpair->tgt_counters.qla_core_ret_ctio;
core_qla_snd_status = qpair->tgt_counters.core_qla_snd_status;
qla_core_ret_sta_ctio = qpair->tgt_counters.qla_core_ret_sta_ctio;
core_qla_free_cmd = qpair->tgt_counters.core_qla_free_cmd;
num_q_full_sent = qpair->tgt_counters.num_q_full_sent;
num_alloc_iocb_failed = qpair->tgt_counters.num_alloc_iocb_failed;
num_term_xchg_sent = qpair->tgt_counters.num_term_xchg_sent;
for (i = 0; i < vha->hw->max_qpairs; i++) {
qpair = vha->hw->queue_pair_map[i];
if (!qpair)
continue;
qla_core_sbt_cmd += qpair->tgt_counters.qla_core_sbt_cmd;
core_qla_que_buf += qpair->tgt_counters.core_qla_que_buf;
qla_core_ret_ctio += qpair->tgt_counters.qla_core_ret_ctio;
core_qla_snd_status += qpair->tgt_counters.core_qla_snd_status;
qla_core_ret_sta_ctio +=
qpair->tgt_counters.qla_core_ret_sta_ctio;
core_qla_free_cmd += qpair->tgt_counters.core_qla_free_cmd;
num_q_full_sent += qpair->tgt_counters.num_q_full_sent;
num_alloc_iocb_failed +=
qpair->tgt_counters.num_alloc_iocb_failed;
num_term_xchg_sent += qpair->tgt_counters.num_term_xchg_sent;
}
seq_puts(s, "Target Counters\n");
seq_printf(s, "qla_core_sbt_cmd = %lld\n",
qla_core_sbt_cmd);
seq_printf(s, "qla_core_ret_sta_ctio = %lld\n",
qla_core_ret_sta_ctio);
seq_printf(s, "qla_core_ret_ctio = %lld\n",
qla_core_ret_ctio);
seq_printf(s, "core_qla_que_buf = %lld\n",
core_qla_que_buf);
seq_printf(s, "core_qla_snd_status = %lld\n",
core_qla_snd_status);
seq_printf(s, "core_qla_free_cmd = %lld\n",
core_qla_free_cmd);
seq_printf(s, "num alloc iocb failed = %lld\n",
num_alloc_iocb_failed);
seq_printf(s, "num term exchange sent = %lld\n",
num_term_xchg_sent);
seq_printf(s, "num Q full sent = %lld\n",
num_q_full_sent);
/* DIF stats */
seq_printf(s, "DIF Inp Bytes = %lld\n",
vha->qla_stats.qla_dif_stats.dif_input_bytes);
seq_printf(s, "DIF Outp Bytes = %lld\n",
vha->qla_stats.qla_dif_stats.dif_output_bytes);
seq_printf(s, "DIF Inp Req = %lld\n",
vha->qla_stats.qla_dif_stats.dif_input_requests);
seq_printf(s, "DIF Outp Req = %lld\n",
vha->qla_stats.qla_dif_stats.dif_output_requests);
seq_printf(s, "DIF Guard err = %d\n",
vha->qla_stats.qla_dif_stats.dif_guard_err);
seq_printf(s, "DIF Ref tag err = %d\n",
vha->qla_stats.qla_dif_stats.dif_ref_tag_err);
seq_printf(s, "DIF App tag err = %d\n",
vha->qla_stats.qla_dif_stats.dif_app_tag_err);
seq_puts(s, "\n");
seq_puts(s, "Initiator Error Counters\n");
seq_printf(s, "HW Error Count = %14lld\n",
vha->hw_err_cnt);
seq_printf(s, "Link Down Count = %14lld\n",
vha->short_link_down_cnt);
seq_printf(s, "Interface Err Count = %14lld\n",
vha->interface_err_cnt);
seq_printf(s, "Cmd Timeout Count = %14lld\n",
vha->cmd_timeout_cnt);
seq_printf(s, "Reset Count = %14lld\n",
vha->reset_cmd_err_cnt);
seq_puts(s, "\n");
list_for_each_entry(fcport, &vha->vp_fcports, list) {
if (!fcport->rport)
continue;
seq_printf(s, "Target Num = %7d Link Down Count = %14lld\n",
fcport->rport->number, fcport->tgt_short_link_down_cnt);
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(qla_dfs_tgt_counters);
static int
qla2x00_dfs_fce_show(struct seq_file *s, void *unused)
{
scsi_qla_host_t *vha = s->private;
uint32_t cnt;
uint32_t *fce;
uint64_t fce_start;
struct qla_hw_data *ha = vha->hw;
mutex_lock(&ha->fce_mutex);
if (ha->flags.user_enabled_fce) {
seq_puts(s, "FCE Trace Buffer\n");
seq_printf(s, "In Pointer = %llx\n\n", (unsigned long long)ha->fce_wr);
seq_printf(s, "Base = %llx\n\n", (unsigned long long)ha->fce_dma);
seq_puts(s, "FCE Enable Registers\n");
seq_printf(s, "%08x %08x %08x %08x %08x %08x\n",
ha->fce_mb[0], ha->fce_mb[2], ha->fce_mb[3], ha->fce_mb[4],
ha->fce_mb[5], ha->fce_mb[6]);
fce = (uint32_t *)ha->fce;
fce_start = (unsigned long long)ha->fce_dma;
for (cnt = 0; cnt < fce_calc_size(ha->fce_bufs) / 4; cnt++) {
if (cnt % 8 == 0)
seq_printf(s, "\n%llx: ",
(unsigned long long)((cnt * 4) + fce_start));
else
seq_putc(s, ' ');
seq_printf(s, "%08x", *fce++);
}
seq_puts(s, "\nEnd\n");
} else {
seq_puts(s, "FCE Trace is currently not enabled\n");
seq_puts(s, "\techo [ 1 | 0 ] > fce\n");
}
mutex_unlock(&ha->fce_mutex);
return 0;
}
static int
qla2x00_dfs_fce_open(struct inode *inode, struct file *file)
{
scsi_qla_host_t *vha = inode->i_private;
struct qla_hw_data *ha = vha->hw;
int rval;
if (!ha->flags.fce_enabled)
goto out;
mutex_lock(&ha->fce_mutex);
/* Pause tracing to flush FCE buffers. */
rval = qla2x00_disable_fce_trace(vha, &ha->fce_wr, &ha->fce_rd);
if (rval)
ql_dbg(ql_dbg_user, vha, 0x705c,
"DebugFS: Unable to disable FCE (%d).\n", rval);
ha->flags.fce_enabled = 0;
mutex_unlock(&ha->fce_mutex);
out:
return single_open(file, qla2x00_dfs_fce_show, vha);
}
static int
qla2x00_dfs_fce_release(struct inode *inode, struct file *file)
{
scsi_qla_host_t *vha = inode->i_private;
struct qla_hw_data *ha = vha->hw;
int rval;
if (ha->flags.fce_enabled || !ha->fce)
goto out;
mutex_lock(&ha->fce_mutex);
/* Re-enable FCE tracing. */
ha->flags.fce_enabled = 1;
memset(ha->fce, 0, fce_calc_size(ha->fce_bufs));
rval = qla2x00_enable_fce_trace(vha, ha->fce_dma, ha->fce_bufs,
ha->fce_mb, &ha->fce_bufs);
if (rval) {
ql_dbg(ql_dbg_user, vha, 0x700d,
"DebugFS: Unable to reinitialize FCE (%d).\n", rval);
ha->flags.fce_enabled = 0;
}
mutex_unlock(&ha->fce_mutex);
out:
return single_release(inode, file);
}
static ssize_t
qla2x00_dfs_fce_write(struct file *file, const char __user *buffer,
size_t count, loff_t *pos)
{
struct seq_file *s = file->private_data;
struct scsi_qla_host *vha = s->private;
struct qla_hw_data *ha = vha->hw;
char *buf;
int rc = 0;
unsigned long enable;
if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) {
ql_dbg(ql_dbg_user, vha, 0xd034,
"this adapter does not support FCE.");
return -EINVAL;
}
buf = memdup_user_nul(buffer, count);
if (IS_ERR(buf)) {
ql_dbg(ql_dbg_user, vha, 0xd037,
"fail to copy user buffer.");
return PTR_ERR(buf);
}
enable = kstrtoul(buf, 0, 0);
rc = count;
mutex_lock(&ha->fce_mutex);
if (enable) {
if (ha->flags.user_enabled_fce) {
mutex_unlock(&ha->fce_mutex);
goto out_free;
}
ha->flags.user_enabled_fce = 1;
if (!ha->fce) {
rc = qla2x00_alloc_fce_trace(vha);
if (rc) {
ha->flags.user_enabled_fce = 0;
mutex_unlock(&ha->fce_mutex);
goto out_free;
}
/* adjust fw dump buffer to take into account of this feature */
if (!ha->flags.fce_dump_buf_alloced)
qla2x00_alloc_fw_dump(vha);
}
if (!ha->flags.fce_enabled)
qla_enable_fce_trace(vha);
ql_dbg(ql_dbg_user, vha, 0xd045, "User enabled FCE .\n");
} else {
if (!ha->flags.user_enabled_fce) {
mutex_unlock(&ha->fce_mutex);
goto out_free;
}
ha->flags.user_enabled_fce = 0;
if (ha->flags.fce_enabled) {
qla2x00_disable_fce_trace(vha, NULL, NULL);
ha->flags.fce_enabled = 0;
}
qla2x00_free_fce_trace(ha);
/* no need to re-adjust fw dump buffer */
ql_dbg(ql_dbg_user, vha, 0xd04f, "User disabled FCE .\n");
}
mutex_unlock(&ha->fce_mutex);
out_free:
kfree(buf);
return rc;
}
static const struct file_operations dfs_fce_ops = {
.open = qla2x00_dfs_fce_open,
.read = seq_read,
.llseek = seq_lseek,
.release = qla2x00_dfs_fce_release,
.write = qla2x00_dfs_fce_write,
};
static int
qla_dfs_naqp_show(struct seq_file *s, void *unused)
{
struct scsi_qla_host *vha = s->private;
struct qla_hw_data *ha = vha->hw;
seq_printf(s, "%d\n", ha->tgt.num_act_qpairs);
return 0;
}
/*
* Helper macros for setting up debugfs entries.
* _name: The name of the debugfs entry
* _ctx_struct: The context that was passed when creating the debugfs file
*
* QLA_DFS_SETUP_RD could be used when there is only a show function.
* - show function take the name qla_dfs_<sysfs-name>_show
*
* QLA_DFS_SETUP_RW could be used when there are both show and write functions.
* - show function take the name qla_dfs_<sysfs-name>_show
* - write function take the name qla_dfs_<sysfs-name>_write
*
* To have a new debugfs entry, do:
* 1. Create a "struct dentry *" in the appropriate structure in the format
* dfs_<sysfs-name>
* 2. Setup debugfs entries using QLA_DFS_SETUP_RD / QLA_DFS_SETUP_RW
* 3. Create debugfs file in qla2x00_dfs_setup() using QLA_DFS_CREATE_FILE
* or QLA_DFS_ROOT_CREATE_FILE
* 4. Remove debugfs file in qla2x00_dfs_remove() using QLA_DFS_REMOVE_FILE
* or QLA_DFS_ROOT_REMOVE_FILE
*
* Example for creating "TEST" sysfs file:
* 1. struct qla_hw_data { ... struct dentry *dfs_TEST; }
* 2. QLA_DFS_SETUP_RD(TEST);
* 3. In qla2x00_dfs_setup():
* QLA_DFS_CREATE_FILE(ha, TEST, 0600, ha->dfs_dir, vha);
* 4. In qla2x00_dfs_remove():
* QLA_DFS_REMOVE_FILE(ha, TEST);
*/
#define QLA_DFS_SETUP_RD(_name) DEFINE_SHOW_ATTRIBUTE(qla_dfs_##_name)
#define QLA_DFS_SETUP_RW(_name) DEFINE_SHOW_STORE_ATTRIBUTE(qla_dfs_##_name)
#define QLA_DFS_ROOT_CREATE_FILE(_name, _perm, _ctx) \
do { \
if (!qla_dfs_##_name) \
qla_dfs_##_name = debugfs_create_file(#_name, \
_perm, qla2x00_dfs_root, _ctx, \
&qla_dfs_##_name##_fops); \
} while (0)
#define QLA_DFS_ROOT_REMOVE_FILE(_name) \
do { \
if (qla_dfs_##_name) { \
debugfs_remove(qla_dfs_##_name); \
qla_dfs_##_name = NULL; \
} \
} while (0)
#define QLA_DFS_CREATE_FILE(_struct, _name, _perm, _parent, _ctx) \
do { \
(_struct)->dfs_##_name = debugfs_create_file(#_name, \
_perm, _parent, _ctx, \
&qla_dfs_##_name##_fops) \
} while (0)
#define QLA_DFS_REMOVE_FILE(_struct, _name) \
do { \
if ((_struct)->dfs_##_name) { \
debugfs_remove((_struct)->dfs_##_name); \
(_struct)->dfs_##_name = NULL; \
} \
} while (0)
static ssize_t
qla_dfs_naqp_write(struct file *file, const char __user *buffer,
size_t count, loff_t *pos)
{
struct seq_file *s = file->private_data;
struct scsi_qla_host *vha = s->private;
struct qla_hw_data *ha = vha->hw;
char *buf;
int rc = 0;
unsigned long num_act_qp;
if (!(IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))) {
pr_err("host%ld: this adapter does not support Multi Q.",
vha->host_no);
return -EINVAL;
}
if (!vha->flags.qpairs_available) {
pr_err("host%ld: Driver is not setup with Multi Q.",
vha->host_no);
return -EINVAL;
}
buf = memdup_user_nul(buffer, count);
if (IS_ERR(buf)) {
pr_err("host%ld: fail to copy user buffer.",
vha->host_no);
return PTR_ERR(buf);
}
num_act_qp = simple_strtoul(buf, NULL, 0);
if (num_act_qp >= vha->hw->max_qpairs) {
pr_err("User set invalid number of qpairs %lu. Max = %d",
num_act_qp, vha->hw->max_qpairs);
rc = -EINVAL;
goto out_free;
}
if (num_act_qp != ha->tgt.num_act_qpairs) {
ha->tgt.num_act_qpairs = num_act_qp;
qlt_clr_qp_table(vha);
}
rc = count;
out_free:
kfree(buf);
return rc;
}
QLA_DFS_SETUP_RW(naqp);
int
qla2x00_dfs_setup(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
goto out;
if (qla2x00_dfs_root)
goto create_dir;
atomic_set(&qla2x00_dfs_root_count, 0);
qla2x00_dfs_root = debugfs_create_dir(QLA2XXX_DRIVER_NAME, NULL);
create_dir:
if (ha->dfs_dir)
goto create_nodes;
mutex_init(&ha->fce_mutex);
ha->dfs_dir = debugfs_create_dir(vha->host_str, qla2x00_dfs_root);
atomic_inc(&qla2x00_dfs_root_count);
create_nodes:
ha->dfs_fw_resource_cnt = debugfs_create_file("fw_resource_count",
S_IRUSR, ha->dfs_dir, vha, &qla_dfs_fw_resource_cnt_fops);
ha->dfs_tgt_counters = debugfs_create_file("tgt_counters", S_IRUSR,
ha->dfs_dir, vha, &qla_dfs_tgt_counters_fops);
ha->tgt.dfs_tgt_port_database = debugfs_create_file("tgt_port_database",
S_IRUSR, ha->dfs_dir, vha, &qla2x00_dfs_tgt_port_database_fops);
ha->dfs_fce = debugfs_create_file("fce", S_IRUSR, ha->dfs_dir, vha,
&dfs_fce_ops);
ha->tgt.dfs_tgt_sess = debugfs_create_file("tgt_sess",
S_IRUSR, ha->dfs_dir, vha, &qla2x00_dfs_tgt_sess_fops);
if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) {
ha->tgt.dfs_naqp = debugfs_create_file("naqp",
0400, ha->dfs_dir, vha, &qla_dfs_naqp_fops);
if (IS_ERR(ha->tgt.dfs_naqp)) {
ql_log(ql_log_warn, vha, 0xd011,
"Unable to create debugFS naqp node.\n");
goto out;
}
}
vha->dfs_rport_root = debugfs_create_dir("rports", ha->dfs_dir);
if (IS_ERR(vha->dfs_rport_root)) {
ql_log(ql_log_warn, vha, 0xd012,
"Unable to create debugFS rports node.\n");
goto out;
}
out:
return 0;
}
int
qla2x00_dfs_remove(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
if (ha->tgt.dfs_naqp) {
debugfs_remove(ha->tgt.dfs_naqp);
ha->tgt.dfs_naqp = NULL;
}
if (ha->tgt.dfs_tgt_sess) {
debugfs_remove(ha->tgt.dfs_tgt_sess);
ha->tgt.dfs_tgt_sess = NULL;
}
if (ha->tgt.dfs_tgt_port_database) {
debugfs_remove(ha->tgt.dfs_tgt_port_database);
ha->tgt.dfs_tgt_port_database = NULL;
}
if (ha->dfs_fw_resource_cnt) {
debugfs_remove(ha->dfs_fw_resource_cnt);
ha->dfs_fw_resource_cnt = NULL;
}
if (ha->dfs_tgt_counters) {
debugfs_remove(ha->dfs_tgt_counters);
ha->dfs_tgt_counters = NULL;
}
if (ha->dfs_fce) {
debugfs_remove(ha->dfs_fce);
ha->dfs_fce = NULL;
}
if (vha->dfs_rport_root) {
debugfs_remove_recursive(vha->dfs_rport_root);
vha->dfs_rport_root = NULL;
}
if (ha->dfs_dir) {
debugfs_remove(ha->dfs_dir);
ha->dfs_dir = NULL;
atomic_dec(&qla2x00_dfs_root_count);
}
if (atomic_read(&qla2x00_dfs_root_count) == 0 &&
qla2x00_dfs_root) {
debugfs_remove(qla2x00_dfs_root);
qla2x00_dfs_root = NULL;
}
return 0;
}
linux-7.2.3/drivers/scsi/qla2xxx/qla_dsd.h
+32
View File
@@ -0,0 +1,32 @@
#ifndef _QLA_DSD_H_
#define _QLA_DSD_H_
#include <linux/unaligned.h>
/* 32-bit data segment descriptor (8 bytes) */
struct dsd32 {
__le32 address;
__le32 length;
};
static inline void append_dsd32(struct dsd32 **dsd, struct scatterlist *sg)
{
put_unaligned_le32(sg_dma_address(sg), &(*dsd)->address);
put_unaligned_le32(sg_dma_len(sg), &(*dsd)->length);
(*dsd)++;
}
/* 64-bit data segment descriptor (12 bytes) */
struct dsd64 {
__le64 address;
__le32 length;
} __packed;
static inline void append_dsd64(struct dsd64 **dsd, struct scatterlist *sg)
{
put_unaligned_le64(sg_dma_address(sg), &(*dsd)->address);
put_unaligned_le32(sg_dma_len(sg), &(*dsd)->length);
(*dsd)++;
}
#endif
linux-7.2.3/drivers/scsi/qla2xxx/qla_edif.c
+3715
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/scsi/qla2xxx/qla_edif.h
+150
View File
@@ -0,0 +1,150 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Marvell Fibre Channel HBA Driver
* Copyright (c) 2021 Marvell
*/
#ifndef __QLA_EDIF_H
#define __QLA_EDIF_H
struct qla_scsi_host;
#define EDIF_APP_ID 0x73730001
#define EDIF_MAX_INDEX 2048
struct edif_sa_ctl {
struct list_head next;
uint16_t del_index;
uint16_t index;
uint16_t slot;
uint16_t flags;
#define EDIF_SA_CTL_FLG_REPL BIT_0
#define EDIF_SA_CTL_FLG_DEL BIT_1
#define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4
// Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE
unsigned long state;
#define EDIF_SA_CTL_USED 1 /* Active Sa update */
#define EDIF_SA_CTL_PEND 2 /* Waiting for slot */
#define EDIF_SA_CTL_REPL 3 /* Active Replace and Delete */
#define EDIF_SA_CTL_DEL 4 /* Delete Pending */
struct fc_port *fcport;
struct bsg_job *bsg_job;
struct qla_sa_update_frame sa_frame;
};
enum enode_flags_t {
ENODE_ACTIVE = 0x1,
};
struct pur_core {
enum enode_flags_t enode_flags;
spinlock_t pur_lock;
struct list_head head;
};
enum db_flags_t {
EDB_ACTIVE = BIT_0,
};
#define DBELL_ACTIVE(_v) (_v->e_dbell.db_flags & EDB_ACTIVE)
#define DBELL_INACTIVE(_v) (!(_v->e_dbell.db_flags & EDB_ACTIVE))
struct edif_dbell {
enum db_flags_t db_flags;
spinlock_t db_lock;
struct list_head head;
struct bsg_job *dbell_bsg_job;
unsigned long bsg_expire;
};
#define SA_UPDATE_IOCB_TYPE 0x71 /* Security Association Update IOCB entry */
struct sa_update_28xx {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System Defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* IOCB System handle. */
union {
__le16 nport_handle; /* in: N_PORT handle. */
__le16 comp_sts; /* out: completion status */
#define CS_PORT_EDIF_UNAVAIL 0x28
#define CS_PORT_EDIF_LOGOUT 0x29
#define CS_PORT_EDIF_SUPP_NOT_RDY 0x64
#define CS_PORT_EDIF_INV_REQ 0x66
} u;
uint8_t vp_index;
uint8_t reserved_1;
uint8_t port_id[3];
uint8_t flags;
#define SA_FLAG_INVALIDATE BIT_0
#define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
uint8_t sa_key[32]; /* 256 bit key */
__le32 salt;
__le32 spi;
uint8_t sa_control;
#define SA_CNTL_ENC_FCSP (1 << 3)
#define SA_CNTL_ENC_OPD (2 << 3)
#define SA_CNTL_ENC_MSK (3 << 3) // mask bits 4,3
#define SA_CNTL_AES_GMAC (1 << 2)
#define SA_CNTL_KEY256 (2 << 0)
#define SA_CNTL_KEY128 0
uint8_t reserved_2;
__le16 sa_index; // reserve: bit 11-15
__le16 old_sa_info;
__le16 new_sa_info;
};
#define NUM_ENTRIES 256
#define PUR_GET 1
struct dinfo {
int nodecnt;
int lstate;
};
struct pur_ninfo {
port_id_t pur_sid;
port_id_t pur_did;
uint8_t vp_idx;
short pur_bytes_rcvd;
unsigned short pur_nphdl;
unsigned int pur_rx_xchg_address;
};
struct purexevent {
struct pur_ninfo pur_info;
unsigned char *msgp;
u32 msgp_len;
};
#define N_UNDEF 0
#define N_PUREX 1
struct enode {
struct list_head list;
struct dinfo dinfo;
uint32_t ntype;
union {
struct purexevent purexinfo;
} u;
};
#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
#define EDIF_SESSION_DOWN(_s) \
(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
_s->disc_state == DSC_DELETED || \
!_s->edif.app_sess_online))
#define EDIF_NEGOTIATION_PENDING(_fcport) \
(DBELL_ACTIVE(_fcport->vha) && \
(_fcport->disc_state == DSC_LOGIN_AUTH_PEND))
#define EDIF_SESS_DELETE(_s) \
(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
_s->disc_state == DSC_DELETED))
#define EDIF_CAP(_ha) (ql2xsecenable && IS_QLA28XX(_ha))
#endif /* __QLA_EDIF_H */
linux-7.2.3/drivers/scsi/qla2xxx/qla_edif_bsg.h
+271
View File
@@ -0,0 +1,271 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Marvell Fibre Channel HBA Driver
* Copyright (C) 2018- Marvell
*
*/
#ifndef __QLA_EDIF_BSG_H
#define __QLA_EDIF_BSG_H
#define EDIF_VERSION1 1
/* BSG Vendor specific commands */
#define ELS_MAX_PAYLOAD 2112
#ifndef WWN_SIZE
#define WWN_SIZE 8
#endif
#define VND_CMD_APP_RESERVED_SIZE 28
#define VND_CMD_PAD_SIZE 3
enum auth_els_sub_cmd {
SEND_ELS = 0,
SEND_ELS_REPLY,
PULL_ELS,
};
struct extra_auth_els {
enum auth_els_sub_cmd sub_cmd;
uint32_t extra_rx_xchg_address;
uint8_t extra_control_flags;
#define BSG_CTL_FLAG_INIT 0
#define BSG_CTL_FLAG_LS_ACC 1
#define BSG_CTL_FLAG_LS_RJT 2
#define BSG_CTL_FLAG_TRM 3
uint8_t version;
uint8_t pad[2];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct qla_bsg_auth_els_request {
struct fc_bsg_request r;
struct extra_auth_els e;
};
struct qla_bsg_auth_els_reply {
struct fc_bsg_reply r;
uint32_t rx_xchg_address;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
};
struct app_id {
int app_vid;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_start_reply {
uint32_t host_support_edif;
uint32_t edif_enode_active;
uint32_t edif_edb_active;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_start {
struct app_id app_info;
uint8_t app_start_flags;
uint8_t version;
uint8_t pad[2];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_stop {
struct app_id app_info;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_plogi_reply {
uint32_t prli_status;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_pinfo_req {
struct app_id app_info;
uint8_t num_ports;
struct {
#ifdef __BIG_ENDIAN
uint8_t domain;
uint8_t area;
uint8_t al_pa;
#elif defined(__LITTLE_ENDIAN)
uint8_t al_pa;
uint8_t area;
uint8_t domain;
#else
#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
#endif
uint8_t rsvd_1;
} remote_pid;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_pinfo {
port_id_t remote_pid;
uint8_t remote_wwpn[WWN_SIZE];
uint8_t remote_type;
#define VND_CMD_RTYPE_UNKNOWN 0
#define VND_CMD_RTYPE_TARGET 1
#define VND_CMD_RTYPE_INITIATOR 2
uint8_t remote_state;
uint8_t auth_state;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
/* AUTH States */
#define VND_CMD_AUTH_STATE_UNDEF 0
#define VND_CMD_AUTH_STATE_SESSION_SHUTDOWN 1
#define VND_CMD_AUTH_STATE_NEEDED 2
#define VND_CMD_AUTH_STATE_ELS_RCVD 3
#define VND_CMD_AUTH_STATE_SAUPDATE_COMPL 4
struct app_pinfo_reply {
uint8_t port_count;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
struct app_pinfo ports[];
} __packed;
struct app_sinfo_req {
struct app_id app_info;
uint8_t num_ports;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct app_sinfo {
uint8_t remote_wwpn[WWN_SIZE];
int64_t rekey_count;
uint8_t rekey_mode;
int64_t tx_bytes;
int64_t rx_bytes;
} __packed;
struct app_stats_reply {
uint8_t elem_count;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
struct app_sinfo elem[];
} __packed;
struct qla_sa_update_frame {
struct app_id app_info;
uint16_t flags;
#define SAU_FLG_INV 0x01 /* delete key */
#define SAU_FLG_TX 0x02 /* 1=tx, 0 = rx */
#define SAU_FLG_FORCE_DELETE 0x08
#define SAU_FLG_GMAC_MODE 0x20 /*
* GMAC mode is cleartext for the IO
* (i.e. NULL encryption)
*/
#define SAU_FLG_KEY128 0x40
#define SAU_FLG_KEY256 0x80
uint16_t fast_sa_index:10,
reserved:6;
uint32_t salt;
uint32_t spi;
uint8_t sa_key[32];
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
port_id_t port_id;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved2[VND_CMD_APP_RESERVED_SIZE];
} __packed;
#define QL_VND_SC_UNDEF 0
#define QL_VND_SC_SA_UPDATE 1
#define QL_VND_SC_APP_START 2
#define QL_VND_SC_APP_STOP 3
#define QL_VND_SC_AUTH_OK 4
#define QL_VND_SC_AUTH_FAIL 5
#define QL_VND_SC_REKEY_CONFIG 6
#define QL_VND_SC_GET_FCINFO 7
#define QL_VND_SC_GET_STATS 8
#define QL_VND_SC_AEN_COMPLETE 9
#define QL_VND_SC_READ_DBELL 10
/*
* bsg caller to provide empty buffer for doorbell events.
*
* sg_io_v4.din_xferp = empty buffer for door bell events
* sg_io_v4.dout_xferp = struct edif_read_dbell *buf
*/
struct edif_read_dbell {
struct app_id app_info;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
};
/* Application interface data structure for rtn data */
#define EXT_DEF_EVENT_DATA_SIZE 64
struct edif_app_dbell {
uint32_t event_code;
uint32_t event_data_size;
union {
port_id_t port_id;
uint8_t event_data[EXT_DEF_EVENT_DATA_SIZE];
};
} __packed;
struct edif_sa_update_aen {
port_id_t port_id;
uint32_t key_type; /* Tx (1) or RX (2) */
uint32_t status; /* 0 succes, 1 failed, 2 timeout , 3 error */
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
#define QL_VND_SA_STAT_SUCCESS 0
#define QL_VND_SA_STAT_FAILED 1
#define QL_VND_SA_STAT_TIMEOUT 2
#define QL_VND_SA_STAT_ERROR 3
#define QL_VND_RX_SA_KEY 1
#define QL_VND_TX_SA_KEY 2
/* App defines for plogi auth'd ok and plogi auth bad requests */
struct auth_complete_cmd {
struct app_id app_info;
#define PL_TYPE_WWPN 1
#define PL_TYPE_DID 2
uint32_t type;
union {
uint8_t wwpn[WWN_SIZE];
port_id_t d_id;
} u;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
struct aen_complete_cmd {
struct app_id app_info;
port_id_t port_id;
uint32_t event_code;
uint8_t version;
uint8_t pad[VND_CMD_PAD_SIZE];
uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];
} __packed;
#define RX_DELAY_DELETE_TIMEOUT 20
#define FCH_EVT_VENDOR_UNIQUE_VPORT_DOWN 1
#endif /* QLA_EDIF_BSG_H */
linux-7.2.3/drivers/scsi/qla2xxx/qla_fw.h
+2287
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linux-7.2.3/drivers/scsi/qla2xxx/qla_gbl.h
+1025
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linux-7.2.3/drivers/scsi/qla2xxx/qla_gs.c
+3888
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linux-7.2.3/drivers/scsi/qla2xxx/qla_init.c
+10284
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linux-7.2.3/drivers/scsi/qla2xxx/qla_inline.h
+640
View File
@@ -0,0 +1,640 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#include "qla_target.h"
/**
* qla24xx_calc_iocbs() - Determine number of Command Type 3 and
* Continuation Type 1 IOCBs to allocate.
*
* @vha: HA context
* @dsds: number of data segment descriptors needed
*
* Returns the number of IOCB entries needed to store @dsds.
*/
static inline uint16_t
qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds)
{
uint16_t iocbs;
iocbs = 1;
if (dsds > 1) {
iocbs += (dsds - 1) / 5;
if ((dsds - 1) % 5)
iocbs++;
}
return iocbs;
}
/*
* qla2x00_debounce_register
* Debounce register.
*
* Input:
* port = register address.
*
* Returns:
* register value.
*/
static __inline__ uint16_t
qla2x00_debounce_register(volatile __le16 __iomem *addr)
{
volatile uint16_t first;
volatile uint16_t second;
do {
first = rd_reg_word(addr);
barrier();
cpu_relax();
second = rd_reg_word(addr);
} while (first != second);
return (first);
}
static inline void
qla2x00_poll(struct rsp_que *rsp)
{
struct qla_hw_data *ha = rsp->hw;
if (IS_P3P_TYPE(ha))
qla82xx_poll(0, rsp);
else
ha->isp_ops->intr_handler(0, rsp);
}
static inline uint8_t *
host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
{
uint32_t *ifcp = (uint32_t *) fcp;
uint32_t *ofcp = (uint32_t *) fcp;
uint32_t iter = bsize >> 2;
for (; iter ; iter--)
*ofcp++ = swab32(*ifcp++);
return fcp;
}
static inline void
host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize)
{
uint32_t *isrc = (uint32_t *) src;
__le32 *odest = (__le32 *) dst;
uint32_t iter = bsize >> 2;
for ( ; iter--; isrc++)
*odest++ = cpu_to_le32(*isrc);
}
static inline void
qla2x00_clean_dsd_pool(struct qla_hw_data *ha, struct crc_context *ctx)
{
struct dsd_dma *dsd, *tdsd;
/* clean up allocated prev pool */
list_for_each_entry_safe(dsd, tdsd, &ctx->dsd_list, list) {
dma_pool_free(ha->dl_dma_pool, dsd->dsd_addr,
dsd->dsd_list_dma);
list_del(&dsd->list);
kfree(dsd);
}
INIT_LIST_HEAD(&ctx->dsd_list);
}
static inline void
qla2x00_set_fcport_disc_state(fc_port_t *fcport, int state)
{
int old_val;
uint8_t shiftbits, mask;
uint8_t port_dstate_str_sz;
/* This will have to change when the max no. of states > 16 */
shiftbits = 4;
mask = (1 << shiftbits) - 1;
port_dstate_str_sz = sizeof(port_dstate_str) / sizeof(char *);
fcport->disc_state = state;
while (1) {
old_val = atomic_read(&fcport->shadow_disc_state);
if (old_val == atomic_cmpxchg(&fcport->shadow_disc_state,
old_val, (old_val << shiftbits) | state)) {
ql_dbg(ql_dbg_disc, fcport->vha, 0x2134,
"FCPort %8phC disc_state transition: %s to %s - portid=%06x.\n",
fcport->port_name, (old_val & mask) < port_dstate_str_sz ?
port_dstate_str[old_val & mask] : "Unknown",
port_dstate_str[state], fcport->d_id.b24);
return;
}
}
}
static inline int
qla2x00_hba_err_chk_enabled(srb_t *sp)
{
/*
* Uncomment when corresponding SCSI changes are done.
*
if (!sp->cmd->prot_chk)
return 0;
*
*/
switch (scsi_get_prot_op(GET_CMD_SP(sp))) {
case SCSI_PROT_READ_STRIP:
case SCSI_PROT_WRITE_INSERT:
if (ql2xenablehba_err_chk >= 1)
return 1;
break;
case SCSI_PROT_READ_PASS:
case SCSI_PROT_WRITE_PASS:
if (ql2xenablehba_err_chk >= 2)
return 1;
break;
case SCSI_PROT_READ_INSERT:
case SCSI_PROT_WRITE_STRIP:
return 1;
}
return 0;
}
static inline int
qla2x00_reset_active(scsi_qla_host_t *vha)
{
scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev);
/* Test appropriate base-vha and vha flags. */
return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) ||
test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
}
static inline int
qla2x00_chip_is_down(scsi_qla_host_t *vha)
{
return (qla2x00_reset_active(vha) || !vha->hw->flags.fw_started);
}
static void qla2xxx_init_sp(srb_t *sp, scsi_qla_host_t *vha,
struct qla_qpair *qpair, fc_port_t *fcport)
{
memset(sp, 0, sizeof(*sp));
sp->fcport = fcport;
sp->iocbs = 1;
sp->vha = vha;
sp->qpair = qpair;
sp->cmd_type = TYPE_SRB;
/* ref : INIT - normal flow */
kref_init(&sp->cmd_kref);
INIT_LIST_HEAD(&sp->elem);
}
static inline srb_t *
qla2xxx_get_qpair_sp(scsi_qla_host_t *vha, struct qla_qpair *qpair,
fc_port_t *fcport, gfp_t flag)
{
srb_t *sp = NULL;
uint8_t bail;
QLA_QPAIR_MARK_BUSY(qpair, bail);
if (unlikely(bail))
return NULL;
sp = mempool_alloc(qpair->srb_mempool, flag);
if (sp)
qla2xxx_init_sp(sp, vha, qpair, fcport);
else
QLA_QPAIR_MARK_NOT_BUSY(qpair);
return sp;
}
void qla2xxx_rel_done_warning(srb_t *sp, int res);
void qla2xxx_rel_free_warning(srb_t *sp);
static inline void
qla2xxx_rel_qpair_sp(struct qla_qpair *qpair, srb_t *sp)
{
sp->qpair = NULL;
sp->done = qla2xxx_rel_done_warning;
sp->free = qla2xxx_rel_free_warning;
mempool_free(sp, qpair->srb_mempool);
QLA_QPAIR_MARK_NOT_BUSY(qpair);
}
static inline srb_t *
qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag)
{
srb_t *sp = NULL;
struct qla_qpair *qpair;
if (unlikely(qla_vha_mark_busy(vha)))
return NULL;
qpair = vha->hw->base_qpair;
sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, flag);
if (!sp)
goto done;
sp->vha = vha;
done:
if (!sp)
QLA_VHA_MARK_NOT_BUSY(vha);
return sp;
}
static inline void
qla2x00_rel_sp(srb_t *sp)
{
QLA_VHA_MARK_NOT_BUSY(sp->vha);
qla2xxx_rel_qpair_sp(sp->qpair, sp);
}
static inline int
qla2x00_gid_list_size(struct qla_hw_data *ha)
{
if (IS_QLAFX00(ha))
return sizeof(uint32_t) * 32;
else
return sizeof(struct gid_list_info) * ha->max_fibre_devices;
}
static inline void
qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status)
{
if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
(status & MBX_INTERRUPT) && ha->flags.mbox_int) {
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
complete(&ha->mbx_intr_comp);
}
}
static inline void
qla2x00_set_retry_delay_timestamp(fc_port_t *fcport, uint16_t sts_qual)
{
u8 scope;
u16 qual;
#define SQ_SCOPE_MASK 0xc000 /* SAM-6 rev5 5.3.2 */
#define SQ_SCOPE_SHIFT 14
#define SQ_QUAL_MASK 0x3fff
#define SQ_MAX_WAIT_SEC 60 /* Max I/O hold off time in seconds. */
#define SQ_MAX_WAIT_TIME (SQ_MAX_WAIT_SEC * 10) /* in 100ms. */
if (!sts_qual) /* Common case. */
return;
scope = (sts_qual & SQ_SCOPE_MASK) >> SQ_SCOPE_SHIFT;
/* Handle only scope 1 or 2, which is for I-T nexus. */
if (scope != 1 && scope != 2)
return;
/* Skip processing, if retry delay timer is already in effect. */
if (fcport->retry_delay_timestamp &&
time_before(jiffies, fcport->retry_delay_timestamp))
return;
qual = sts_qual & SQ_QUAL_MASK;
if (qual < 1 || qual > 0x3fef)
return;
qual = min(qual, (u16)SQ_MAX_WAIT_TIME);
/* qual is expressed in 100ms increments. */
fcport->retry_delay_timestamp = jiffies + (qual * HZ / 10);
ql_log(ql_log_warn, fcport->vha, 0x5101,
"%8phC: I/O throttling requested (status qualifier = %04xh), holding off I/Os for %ums.\n",
fcport->port_name, sts_qual, qual * 100);
}
static inline bool
qla_is_exch_offld_enabled(struct scsi_qla_host *vha)
{
if (qla_ini_mode_enabled(vha) &&
(vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT))
return true;
else if (qla_tgt_mode_enabled(vha) &&
(vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT))
return true;
else if (qla_dual_mode_enabled(vha) &&
((vha->ql2xiniexchg + vha->ql2xexchoffld) > FW_DEF_EXCHANGES_CNT))
return true;
else
return false;
}
static inline void
qla_cpu_update(struct qla_qpair *qpair, uint16_t cpuid)
{
qpair->cpuid = cpuid;
if (!list_empty(&qpair->hints_list)) {
struct qla_qpair_hint *h;
list_for_each_entry(h, &qpair->hints_list, hint_elem)
h->cpuid = qpair->cpuid;
}
}
static inline struct qla_qpair_hint *
qla_qpair_to_hint(struct qla_tgt *tgt, struct qla_qpair *qpair)
{
struct qla_qpair_hint *h;
u16 i;
for (i = 0; i < tgt->ha->max_qpairs + 1; i++) {
h = &tgt->qphints[i];
if (h->qpair == qpair)
return h;
}
return NULL;
}
static inline void
qla_83xx_start_iocbs(struct qla_qpair *qpair)
{
struct req_que *req = qpair->req;
req->ring_index++;
if (req->ring_index == req->length) {
req->ring_index = 0;
req->ring_ptr = req->ring;
} else
req->ring_ptr++;
wrt_reg_dword(req->req_q_in, req->ring_index);
}
static inline int
qla2xxx_get_fc4_priority(struct scsi_qla_host *vha)
{
uint32_t data;
data =
((uint8_t *)vha->hw->nvram)[NVRAM_DUAL_FCP_NVME_FLAG_OFFSET];
return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME;
}
enum {
RESOURCE_NONE,
RESOURCE_IOCB = BIT_0,
RESOURCE_EXCH = BIT_1, /* exchange */
RESOURCE_FORCE = BIT_2,
RESOURCE_HA = BIT_3,
};
static inline int
qla_get_fw_resources(struct qla_qpair *qp, struct iocb_resource *iores)
{
u16 iocbs_used, i;
u16 exch_used;
struct qla_hw_data *ha = qp->hw;
if (!ql2xenforce_iocb_limit) {
iores->res_type = RESOURCE_NONE;
return 0;
}
if (iores->res_type & RESOURCE_FORCE)
goto force;
if ((iores->iocb_cnt + qp->fwres.iocbs_used) >= qp->fwres.iocbs_qp_limit) {
/* no need to acquire qpair lock. It's just rough calculation */
iocbs_used = ha->base_qpair->fwres.iocbs_used;
for (i = 0; i < ha->max_qpairs; i++) {
if (ha->queue_pair_map[i])
iocbs_used += ha->queue_pair_map[i]->fwres.iocbs_used;
}
if ((iores->iocb_cnt + iocbs_used) >= qp->fwres.iocbs_limit) {
iores->res_type = RESOURCE_NONE;
return -ENOSPC;
}
}
if (iores->res_type & RESOURCE_EXCH) {
exch_used = ha->base_qpair->fwres.exch_used;
for (i = 0; i < ha->max_qpairs; i++) {
if (ha->queue_pair_map[i])
exch_used += ha->queue_pair_map[i]->fwres.exch_used;
}
if ((exch_used + iores->exch_cnt) >= qp->fwres.exch_limit) {
iores->res_type = RESOURCE_NONE;
return -ENOSPC;
}
}
if (ql2xenforce_iocb_limit == 2) {
if ((iores->iocb_cnt + atomic_read(&ha->fwres.iocb_used)) >=
ha->fwres.iocb_limit) {
iores->res_type = RESOURCE_NONE;
return -ENOSPC;
}
if (iores->res_type & RESOURCE_EXCH) {
if ((iores->exch_cnt + atomic_read(&ha->fwres.exch_used)) >=
ha->fwres.exch_limit) {
iores->res_type = RESOURCE_NONE;
return -ENOSPC;
}
}
}
force:
qp->fwres.iocbs_used += iores->iocb_cnt;
qp->fwres.exch_used += iores->exch_cnt;
if (ql2xenforce_iocb_limit == 2) {
atomic_add(iores->iocb_cnt, &ha->fwres.iocb_used);
atomic_add(iores->exch_cnt, &ha->fwres.exch_used);
iores->res_type |= RESOURCE_HA;
}
return 0;
}
/*
* decrement to zero. This routine will not decrement below zero
* @v: pointer of type atomic_t
* @amount: amount to decrement from v
*/
static void qla_atomic_dtz(atomic_t *v, int amount)
{
int c, old, dec;
c = atomic_read(v);
for (;;) {
dec = c - amount;
if (unlikely(dec < 0))
dec = 0;
old = atomic_cmpxchg((v), c, dec);
if (likely(old == c))
break;
c = old;
}
}
static inline void
qla_put_fw_resources(struct qla_qpair *qp, struct iocb_resource *iores)
{
struct qla_hw_data *ha = qp->hw;
if (iores->res_type & RESOURCE_HA) {
if (iores->res_type & RESOURCE_IOCB)
qla_atomic_dtz(&ha->fwres.iocb_used, iores->iocb_cnt);
if (iores->res_type & RESOURCE_EXCH)
qla_atomic_dtz(&ha->fwres.exch_used, iores->exch_cnt);
}
if (iores->res_type & RESOURCE_IOCB) {
if (qp->fwres.iocbs_used >= iores->iocb_cnt) {
qp->fwres.iocbs_used -= iores->iocb_cnt;
} else {
/* should not happen */
qp->fwres.iocbs_used = 0;
}
}
if (iores->res_type & RESOURCE_EXCH) {
if (qp->fwres.exch_used >= iores->exch_cnt) {
qp->fwres.exch_used -= iores->exch_cnt;
} else {
/* should not happen */
qp->fwres.exch_used = 0;
}
}
iores->res_type = RESOURCE_NONE;
}
#define ISP_REG_DISCONNECT 0xffffffffU
/**************************************************************************
* qla2x00_isp_reg_stat
*
* Description:
* Read the host status register of ISP before aborting the command.
*
* Input:
* ha = pointer to host adapter structure.
*
*
* Returns:
* Either true or false.
*
* Note: Return true if there is register disconnect.
**************************************************************************/
static inline
uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
{
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
if (IS_P3P_TYPE(ha))
return ((rd_reg_dword(&reg82->host_int)) == ISP_REG_DISCONNECT);
else
return ((rd_reg_dword(&reg->host_status)) ==
ISP_REG_DISCONNECT);
}
static inline
bool qla_pci_disconnected(struct scsi_qla_host *vha,
struct device_reg_24xx __iomem *reg)
{
uint32_t stat;
bool ret = false;
stat = rd_reg_dword(&reg->host_status);
if (stat == 0xffffffff) {
ql_log(ql_log_info, vha, 0x8041,
"detected PCI disconnect.\n");
qla_schedule_eeh_work(vha);
ret = true;
}
return ret;
}
static inline bool
fcport_is_smaller(fc_port_t *fcport)
{
if (wwn_to_u64(fcport->port_name) <
wwn_to_u64(fcport->vha->port_name))
return true;
else
return false;
}
static inline bool
fcport_is_bigger(fc_port_t *fcport)
{
return !fcport_is_smaller(fcport);
}
static inline struct qla_qpair *
qla_mapq_nvme_select_qpair(struct qla_hw_data *ha, struct qla_qpair *qpair)
{
int cpuid = raw_smp_processor_id();
if (qpair->cpuid != cpuid &&
ha->qp_cpu_map[cpuid]) {
qpair = ha->qp_cpu_map[cpuid];
}
return qpair;
}
static inline void
qla_mapq_init_qp_cpu_map(struct qla_hw_data *ha,
struct qla_msix_entry *msix,
struct qla_qpair *qpair)
{
const struct cpumask *mask;
unsigned int cpu;
if (!ha->qp_cpu_map)
return;
mask = pci_irq_get_affinity(ha->pdev, msix->vector_base0);
if (!mask)
return;
qpair->cpuid = cpumask_first(mask);
for_each_cpu(cpu, mask) {
ha->qp_cpu_map[cpu] = qpair;
}
msix->cpuid = qpair->cpuid;
qpair->cpu_mapped = true;
}
static inline void
qla_mapq_free_qp_cpu_map(struct qla_hw_data *ha)
{
if (ha->qp_cpu_map) {
kfree(ha->qp_cpu_map);
ha->qp_cpu_map = NULL;
}
}
static inline int qla_mapq_alloc_qp_cpu_map(struct qla_hw_data *ha)
{
scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
if (!ha->qp_cpu_map) {
ha->qp_cpu_map = kzalloc_objs(struct qla_qpair *, nr_cpu_ids);
if (!ha->qp_cpu_map) {
ql_log(ql_log_fatal, vha, 0x0180,
"Unable to allocate memory for qp_cpu_map ptrs.\n");
return -1;
}
}
return 0;
}
static inline bool val_is_in_range(u32 val, u32 start, u32 end)
{
if (val >= start && val <= end)
return true;
else
return false;
}
linux-7.2.3/drivers/scsi/qla2xxx/qla_iocb.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_isr.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_mbx.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_mid.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_mr.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_mr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#ifndef __QLA_MR_H
#define __QLA_MR_H
#include "qla_dsd.h"
/*
* The PCI VendorID and DeviceID for our board.
*/
#define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
/* FX00 specific definitions */
#define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */
struct cmd_type_7_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint8_t reserved_0;
uint8_t port_path_ctrl;
uint16_t reserved_1;
__le16 tgt_idx; /* Target Idx. */
uint16_t timeout; /* Command timeout. */
__le16 dseg_count; /* Data segment count. */
uint8_t scsi_rsp_dsd_len;
uint8_t reserved_2;
struct scsi_lun lun; /* LUN (LE). */
uint8_t cntrl_flags;
uint8_t task_mgmt_flags; /* Task management flags. */
uint8_t task;
uint8_t crn;
uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
__le32 byte_count; /* Total byte count. */
struct dsd64 dsd;
};
#define STATUS_TYPE_FX00 0x01 /* Status entry. */
struct sts_entry_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint32_t reserved_3; /* System handle. */
__le16 comp_status; /* Completion status. */
uint16_t reserved_0; /* OX_ID used by the firmware. */
__le32 residual_len; /* FW calc residual transfer length. */
uint16_t reserved_1;
uint16_t state_flags; /* State flags. */
uint16_t reserved_2;
__le16 scsi_status; /* SCSI status. */
uint32_t sense_len; /* FCP SENSE length. */
uint8_t data[32]; /* FCP response/sense information. */
};
#define MAX_HANDLE_COUNT 15
#define MULTI_STATUS_TYPE_FX00 0x0D
struct multi_sts_entry_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t handle_count;
uint8_t entry_status;
__le32 handles[MAX_HANDLE_COUNT];
};
#define TSK_MGMT_IOCB_TYPE_FX00 0x05
struct tsk_mgmt_entry_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define;
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint32_t reserved_0;
__le16 tgt_id; /* Target Idx. */
uint16_t reserved_1;
uint16_t reserved_3;
uint16_t reserved_4;
struct scsi_lun lun; /* LUN (LE). */
__le32 control_flags; /* Control Flags. */
uint8_t reserved_2[32];
};
#define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */
struct abort_iocb_entry_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
__le32 reserved_0;
__le16 tgt_id_sts; /* Completion status. */
__le16 options;
uint32_t abort_handle; /* System handle. */
__le32 reserved_2;
__le16 req_que_no;
uint8_t reserved_1[38];
};
#define IOCTL_IOSB_TYPE_FX00 0x0C
struct ioctl_iocb_entry_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint32_t reserved_0; /* System handle. */
uint16_t comp_func_num;
__le16 fw_iotcl_flags;
__le32 dataword_r; /* Data word returned */
uint32_t adapid; /* Adapter ID */
uint32_t dataword_r_extra;
__le32 seq_no;
uint8_t reserved_2[20];
uint32_t residuallen;
__le32 status;
};
#define STATUS_CONT_TYPE_FX00 0x04
#define FX00_IOCB_TYPE 0x0B
struct fxdisc_entry_fx00 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System Defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
__le32 reserved_0; /* System handle. */
__le16 func_num;
__le16 req_xfrcnt;
__le16 req_dsdcnt;
__le16 rsp_xfrcnt;
__le16 rsp_dsdcnt;
uint8_t flags;
uint8_t reserved_1;
/*
* Use array size 1 below to prevent that Coverity complains about
* the append_dsd64() calls for the two arrays below.
*/
struct dsd64 dseg_rq[1];
struct dsd64 dseg_rsp[1];
__le32 dataword;
__le32 adapid;
__le32 adapid_hi;
__le32 dataword_extra;
};
struct qlafx00_tgt_node_info {
uint8_t tgt_node_wwpn[WWN_SIZE];
uint8_t tgt_node_wwnn[WWN_SIZE];
uint32_t tgt_node_state;
uint8_t reserved[128];
uint32_t reserved_1[8];
uint64_t reserved_2[4];
} __packed;
#define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
#define QLAFX00_LINK_STATUS_DOWN 0x10
#define QLAFX00_LINK_STATUS_UP 0x11
#define QLAFX00_PORT_SPEED_2G 0x2
#define QLAFX00_PORT_SPEED_4G 0x4
#define QLAFX00_PORT_SPEED_8G 0x8
#define QLAFX00_PORT_SPEED_10G 0xa
struct port_info_data {
uint8_t port_state;
uint8_t port_type;
uint16_t port_identifier;
uint32_t up_port_state;
uint8_t fw_ver_num[32];
uint8_t portal_attrib;
uint16_t host_option;
uint8_t reset_delay;
uint8_t pdwn_retry_cnt;
uint16_t max_luns2tgt;
uint8_t risc_ver;
uint8_t pconn_option;
uint16_t risc_option;
uint16_t max_frame_len;
uint16_t max_iocb_alloc;
uint16_t exec_throttle;
uint8_t retry_cnt;
uint8_t retry_delay;
uint8_t port_name[8];
uint8_t port_id[3];
uint8_t link_status;
uint8_t plink_rate;
uint32_t link_config;
uint16_t adap_haddr;
uint8_t tgt_disc;
uint8_t log_tout;
uint8_t node_name[8];
uint16_t erisc_opt1;
uint8_t resp_acc_tmr;
uint8_t intr_del_tmr;
uint8_t erisc_opt2;
uint8_t alt_port_name[8];
uint8_t alt_node_name[8];
uint8_t link_down_tout;
uint8_t conn_type;
uint8_t fc_fw_mode;
uint32_t uiReserved[48];
} __packed;
/* OS Type Designations */
#define OS_TYPE_UNKNOWN 0
#define OS_TYPE_LINUX 2
/* Linux Info */
#define SYSNAME_LENGTH 128
#define NODENAME_LENGTH 64
#define RELEASE_LENGTH 64
#define VERSION_LENGTH 64
#define MACHINE_LENGTH 64
#define DOMNAME_LENGTH 64
struct host_system_info {
uint32_t os_type;
char sysname[SYSNAME_LENGTH];
char nodename[NODENAME_LENGTH];
char release[RELEASE_LENGTH];
char version[VERSION_LENGTH];
char machine[MACHINE_LENGTH];
char domainname[DOMNAME_LENGTH];
char hostdriver[VERSION_LENGTH];
uint32_t reserved[64];
} __packed;
struct register_host_info {
struct host_system_info hsi; /* host system info */
uint64_t utc; /* UTC (system time) */
uint32_t reserved[64]; /* future additions */
} __packed;
#define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
#define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
struct config_info_data {
uint8_t model_num[16] __nonstring;
uint8_t model_description[80] __nonstring;
uint8_t reserved0[160];
uint8_t symbolic_name[64];
uint8_t serial_num[32];
uint8_t hw_version[16];
uint8_t fw_version[16];
uint8_t uboot_version[16];
uint8_t fru_serial_num[32];
uint8_t fc_port_count;
uint8_t iscsi_port_count;
uint8_t reserved1[2];
uint8_t mode;
uint8_t log_level;
uint8_t reserved2[2];
uint32_t log_size;
uint8_t tgt_pres_mode;
uint8_t iqn_flags;
uint8_t lun_mapping;
uint64_t adapter_id;
uint32_t cluster_key_len;
uint8_t cluster_key[16];
uint64_t cluster_master_id;
uint64_t cluster_slave_id;
uint8_t cluster_flags;
uint32_t enabled_capabilities;
uint32_t nominal_temp_value;
} __packed;
#define FXDISC_GET_CONFIG_INFO 0x01
#define FXDISC_GET_PORT_INFO 0x02
#define FXDISC_GET_TGT_NODE_INFO 0x80
#define FXDISC_GET_TGT_NODE_LIST 0x81
#define FXDISC_REG_HOST_INFO 0x99
#define FXDISC_ABORT_IOCTL 0xff
#define QLAFX00_HBA_ICNTRL_REG 0x20B08
#define QLAFX00_ICR_ENB_MASK 0x80000000
#define QLAFX00_ICR_DIS_MASK 0x7fffffff
#define QLAFX00_HST_RST_REG 0x18264
#define QLAFX00_SOC_TEMP_REG 0x184C4
#define QLAFX00_HST_TO_HBA_REG 0x20A04
#define QLAFX00_HBA_TO_HOST_REG 0x21B70
#define QLAFX00_HST_INT_STS_BITS 0x7
#define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
#define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
#define QLAFX00_INTR_MB_CMPLT 0x1
#define QLAFX00_INTR_RSP_CMPLT 0x2
#define QLAFX00_INTR_ASYNC_CMPLT 0x4
#define QLAFX00_MBA_SYSTEM_ERR 0x8002
#define QLAFX00_MBA_TEMP_OVER 0x8005
#define QLAFX00_MBA_TEMP_NORM 0x8006
#define QLAFX00_MBA_TEMP_CRIT 0x8007
#define QLAFX00_MBA_LINK_UP 0x8011
#define QLAFX00_MBA_LINK_DOWN 0x8012
#define QLAFX00_MBA_PORT_UPDATE 0x8014
#define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
#define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
#define SOC_FABRIC_RST_CONTROL_REG 0x0020840
#define SOC_FABRIC_CONTROL_REG 0x0020200
#define SOC_FABRIC_CONFIG_REG 0x0020204
#define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
#define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
#define SOC_CORE_TIMER_REG 0x0021850
#define SOC_IRQ_ACK_REG 0x00218b4
#define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */
#define QLAFX00_SET_HST_INTR(ha, value) \
wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
value)
#define QLAFX00_CLR_HST_INTR(ha, value) \
wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
~value)
#define QLAFX00_RD_INTR_REG(ha) \
rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
#define QLAFX00_CLR_INTR_REG(ha, value) \
wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
~value)
#define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
wrt_reg_dword((ha)->cregbase + off, val)
#define QLAFX00_GET_HBA_SOC_REG(ha, off)\
rd_reg_dword((ha)->cregbase + off)
#define QLAFX00_HBA_RST_REG(ha, val)\
wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
#define QLAFX00_RD_ICNTRL_REG(ha) \
rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
#define QLAFX00_ENABLE_ICNTRL_REG(ha) \
wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
QLAFX00_ICR_ENB_MASK))
#define QLAFX00_DISABLE_ICNTRL_REG(ha) \
wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
QLAFX00_ICR_DIS_MASK))
#define QLAFX00_RD_REG(ha, off) \
rd_reg_dword((ha)->cregbase + off)
#define QLAFX00_WR_REG(ha, off, val) \
wrt_reg_dword((ha)->cregbase + off, val)
struct qla_mt_iocb_rqst_fx00 {
__le32 reserved_0;
__le16 func_type;
uint8_t flags;
uint8_t reserved_1;
__le32 dataword;
__le32 adapid;
__le32 adapid_hi;
__le32 dataword_extra;
__le16 req_len;
__le16 reserved_2;
__le16 rsp_len;
__le16 reserved_3;
};
struct qla_mt_iocb_rsp_fx00 {
uint32_t reserved_1;
uint16_t func_type;
__le16 ioctl_flags;
__le32 ioctl_data;
uint32_t adapid;
uint32_t adapid_hi;
uint32_t reserved_2;
__le32 seq_number;
uint8_t reserved_3[20];
int32_t res_count;
__le32 status;
};
#define MAILBOX_REGISTER_COUNT_FX00 16
#define AEN_MAILBOX_REGISTER_COUNT_FX00 8
#define MAX_FIBRE_DEVICES_FX00 512
#define MAX_LUNS_FX00 0x1024
#define MAX_TARGETS_FX00 MAX_ISA_DEVICES
#define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */
#define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
/*
* Firmware state codes for QLAFX00 adapters
*/
#define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue
* Initialize FW Mbox cmd
*/
#define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by
* the driver
*/
#define FX00_DEF_RATOV 10
struct mr_data_fx00 {
uint8_t symbolic_name[64];
uint8_t serial_num[32];
uint8_t hw_version[16];
uint8_t fw_version[16];
uint8_t uboot_version[16];
uint8_t fru_serial_num[32];
fc_port_t fcport; /* fcport used for requests
* that are not linked
* to a particular target
*/
uint8_t fw_hbt_en;
uint8_t fw_hbt_cnt;
uint8_t fw_hbt_miss_cnt;
uint32_t old_fw_hbt_cnt;
uint16_t fw_reset_timer_tick;
uint8_t fw_reset_timer_exp;
uint16_t fw_critemp_timer_tick;
uint32_t old_aenmbx0_state;
uint32_t critical_temperature;
bool extended_io_enabled;
bool host_info_resend;
uint8_t hinfo_resend_timer_tick;
};
#define QLAFX00_EXTENDED_IO_EN_MASK 0x20
/*
* SoC Junction Temperature is stored in
* bits 9:1 of SoC Junction Temperature Register
* in a firmware specific format format.
* To get the temperature in Celsius degrees
* the value from this bitfiled should be converted
* using this formula:
* Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825)
* where X is the bit field value
* this macro reads the register, extracts the bitfield value,
* performs the calcualtions and returns temperature in Celsius
*/
#define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
#define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */
#define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */
#define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */
#define QLAFX00_RESET_INTERVAL 120 /* number of seconds */
#define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */
#define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */
#define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */
#define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */
/* Max conncurrent IOs that can be queued */
#define QLAFX00_MAX_CANQUEUE 1024
/* IOCTL IOCB abort success */
#define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
#endif
linux-7.2.3/drivers/scsi/qla2xxx/qla_nvme.c
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2017 QLogic Corporation
*/
#ifndef __QLA_NVME_H
#define __QLA_NVME_H
#include <uapi/scsi/fc/fc_fs.h>
#include <uapi/scsi/fc/fc_els.h>
#include <linux/nvme-fc-driver.h>
#include "qla_def.h"
#include "qla_dsd.h"
#define MIN_NVME_HW_QUEUES 1
#define DEF_NVME_HW_QUEUES 8
#define NVME_ATIO_CMD_OFF 32
#define NVME_FIRST_PACKET_CMDLEN (64 - NVME_ATIO_CMD_OFF)
#define Q2T_NVME_NUM_TAGS 2048
#define QLA_MAX_FC_SEGMENTS 64
struct qla_nvme_unsol_ctx;
struct scsi_qla_host;
struct qla_hw_data;
struct req_que;
struct srb;
struct nvme_private {
struct srb *sp;
struct nvmefc_ls_req *fd;
struct work_struct ls_work;
struct work_struct abort_work;
int comp_status;
spinlock_t cmd_lock;
};
struct qla_nvme_rport {
struct fc_port *fcport;
struct qla_nvme_unsol_ctx *uctx;
};
#define COMMAND_NVME 0x88 /* Command Type FC-NVMe IOCB */
struct cmd_nvme {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
__le16 nport_handle; /* N_PORT handle. */
__le16 timeout; /* Command timeout. */
__le16 dseg_count; /* Data segment count. */
__le16 nvme_rsp_dsd_len; /* NVMe RSP DSD length */
uint64_t rsvd;
__le16 control_flags; /* Control Flags */
#define CF_ADMIN_ASYNC_EVENT BIT_13
#define CF_NVME_FIRST_BURST_ENABLE BIT_11
#define CF_DIF_SEG_DESCR_ENABLE BIT_3
#define CF_DATA_SEG_DESCR_ENABLE BIT_2
#define CF_READ_DATA BIT_1
#define CF_WRITE_DATA BIT_0
__le16 nvme_cmnd_dseg_len; /* Data segment length. */
__le64 nvme_cmnd_dseg_address __packed;/* Data segment address. */
__le64 nvme_rsp_dseg_address __packed; /* Data segment address. */
__le32 byte_count; /* Total byte count. */
uint8_t port_id[3]; /* PortID of destination port. */
uint8_t vp_index;
struct dsd64 nvme_dsd;
};
#define PURLS_MSLEEP_INTERVAL 1
#define PURLS_RETRY_COUNT 5
#define PT_LS4_REQUEST 0x89 /* Link Service pass-through IOCB (request) */
struct pt_ls4_request {
uint8_t entry_type;
uint8_t entry_count;
uint8_t sys_define;
uint8_t entry_status;
uint32_t handle;
__le16 status;
__le16 nport_handle;
__le16 tx_dseg_count;
uint8_t vp_index;
uint8_t rsvd;
__le16 timeout;
__le16 control_flags;
#define CF_LS4_SHIFT 13
#define CF_LS4_ORIGINATOR 0
#define CF_LS4_RESPONDER 1
#define CF_LS4_RESPONDER_TERM 2
__le16 rx_dseg_count;
__le16 rsvd2;
__le32 exchange_address;
__le32 rsvd3;
__le32 rx_byte_count;
__le32 tx_byte_count;
struct dsd64 dsd[2];
};
#define PT_LS4_UNSOL 0x56 /* pass-up unsolicited rec FC-NVMe request */
struct pt_ls4_rx_unsol {
uint8_t entry_type;
uint8_t entry_count;
__le16 rsvd0;
__le16 rsvd1;
uint8_t vp_index;
uint8_t rsvd2;
__le16 rsvd3;
__le16 nport_handle;
__le16 frame_size;
__le16 rsvd4;
__le32 exchange_address;
uint8_t d_id[3];
uint8_t r_ctl;
le_id_t s_id;
uint8_t cs_ctl;
uint8_t f_ctl[3];
uint8_t type;
__le16 seq_cnt;
uint8_t df_ctl;
uint8_t seq_id;
__le16 rx_id;
__le16 ox_id;
__le32 desc0;
#define PT_LS4_PAYLOAD_OFFSET 0x2c
#define PT_LS4_FIRST_PACKET_LEN 20
__le32 payload[5];
};
/*
* Global functions prototype in qla_nvme.c source file.
*/
int qla_nvme_register_hba(struct scsi_qla_host *);
int qla_nvme_register_remote(struct scsi_qla_host *, struct fc_port *);
void qla_nvme_delete(struct scsi_qla_host *);
void qla24xx_nvme_ls4_iocb(struct scsi_qla_host *, struct pt_ls4_request *,
struct req_que *);
void qla24xx_async_gffid_sp_done(struct srb *sp, int);
#endif
linux-7.2.3/drivers/scsi/qla2xxx/qla_nx.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_nx.h
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linux-7.2.3/drivers/scsi/qla2xxx/qla_nx2.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_nx2.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#ifndef __QLA_NX2_H
#define __QLA_NX2_H
#define QSNT_ACK_TOV 30
#define INTENT_TO_RECOVER 0x01
#define PROCEED_TO_RECOVER 0x02
#define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
#define IDC_LOCK_RECOVERY_STATE_MASK 0x3
#define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
#define QLA8044_DRV_LOCK_MSLEEP 200
#define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
#define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
#define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
#define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
#define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
#define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
#define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
#define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
MIU_TA_CTL_START)
#define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
/* Imbus address bit used to indicate a host address. This bit is
* eliminated by the pcie bar and bar select before presentation
* over pcie. */
/* host memory via IMBUS */
#define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
#define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
#define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
#define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
#define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
#define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
#define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
#define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
#define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
#define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
#define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
#define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
#define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
#define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
#define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
#define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
#define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
#define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
/* PCI Windowing for DDR regions. */
static inline bool addr_in_range(u64 addr, u64 low, u64 high)
{
return addr <= high && addr >= low;
}
/* Indirectly Mapped Registers */
#define QLA8044_FLASH_SPI_STATUS 0x2808E010
#define QLA8044_FLASH_SPI_CONTROL 0x2808E014
#define QLA8044_FLASH_STATUS 0x42100004
#define QLA8044_FLASH_CONTROL 0x42110004
#define QLA8044_FLASH_ADDR 0x42110008
#define QLA8044_FLASH_WRDATA 0x4211000C
#define QLA8044_FLASH_RDDATA 0x42110018
#define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
#define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
/* Flash access regs */
#define QLA8044_FLASH_LOCK 0x3850
#define QLA8044_FLASH_UNLOCK 0x3854
#define QLA8044_FLASH_LOCK_ID 0x3500
/* Driver Lock regs */
#define QLA8044_DRV_LOCK 0x3868
#define QLA8044_DRV_UNLOCK 0x386C
#define QLA8044_DRV_LOCK_ID 0x3504
#define QLA8044_DRV_LOCKRECOVERY 0x379C
/* IDC version */
#define QLA8044_IDC_VER_MAJ_VALUE 0x1
#define QLA8044_IDC_VER_MIN_VALUE 0x0
/* IDC Registers : Driver Coexistence Defines */
#define QLA8044_CRB_IDC_VER_MAJOR 0x3780
#define QLA8044_CRB_IDC_VER_MINOR 0x3798
#define QLA8044_IDC_DRV_AUDIT 0x3794
#define QLA8044_SRE_SHIM_CONTROL 0x0D200284
#define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
#define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
#define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
#define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
#define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
#define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
#define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
#define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
/* set value to pause threshold value */
#define QLA8044_SET_PAUSE_VAL 0x0
#define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
#define QLA8044_PEG_HALT_STATUS1 0x34A8
#define QLA8044_PEG_HALT_STATUS2 0x34AC
#define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
#define QLA8044_FW_CAPABILITIES 0x3528
#define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
#define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
#define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
#define QLA8044_CRB_DRV_SCRATCH 0x3548
#define QLA8044_CRB_DEV_PART_INFO1 0x37E0
#define QLA8044_CRB_DEV_PART_INFO2 0x37E4
#define QLA8044_FW_VER_MAJOR 0x3550
#define QLA8044_FW_VER_MINOR 0x3554
#define QLA8044_FW_VER_SUB 0x3558
#define QLA8044_NPAR_STATE 0x359C
#define QLA8044_FW_IMAGE_VALID 0x35FC
#define QLA8044_CMDPEG_STATE 0x3650
#define QLA8044_ASIC_TEMP 0x37B4
#define QLA8044_FW_API 0x356C
#define QLA8044_DRV_OP_MODE 0x3570
#define QLA8044_CRB_WIN_BASE 0x3800
#define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
#define QLA8044_SEM_LOCK_BASE 0x3840
#define QLA8044_SEM_UNLOCK_BASE 0x3844
#define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
#define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
#define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
#define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
#define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
#define QLA8044_LINK_SPEED_FACTOR 10
#define QLA8044_FUN7_ACTIVE_INDEX 0x80
/* FLASH API Defines */
#define QLA8044_FLASH_MAX_WAIT_USEC 100
#define QLA8044_FLASH_LOCK_TIMEOUT 10000
#define QLA8044_FLASH_SECTOR_SIZE 65536
#define QLA8044_DRV_LOCK_TIMEOUT 2000
#define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
#define QLA8044_FLASH_WRITE_CMD 0xdacdacda
#define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
#define QLA8044_FLASH_READ_RETRY_COUNT 2000
#define QLA8044_FLASH_STATUS_READY 0x6
#define QLA8044_FLASH_BUFFER_WRITE_MIN 2
#define QLA8044_FLASH_BUFFER_WRITE_MAX 64
#define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
#define QLA8044_ERASE_MODE 1
#define QLA8044_WRITE_MODE 2
#define QLA8044_DWORD_WRITE_MODE 3
#define QLA8044_GLOBAL_RESET 0x38CC
#define QLA8044_WILDCARD 0x38F0
#define QLA8044_INFORMANT 0x38FC
#define QLA8044_HOST_MBX_CTRL 0x3038
#define QLA8044_FW_MBX_CTRL 0x303C
#define QLA8044_BOOTLOADER_ADDR 0x355C
#define QLA8044_BOOTLOADER_SIZE 0x3560
#define QLA8044_FW_IMAGE_ADDR 0x3564
#define QLA8044_MBX_INTR_ENABLE 0x1000
#define QLA8044_MBX_INTR_MASK 0x1200
/* IDC Control Register bit defines */
#define DONTRESET_BIT0 0x1
#define GRACEFUL_RESET_BIT1 0x2
/* ISP8044 PEG_HALT_STATUS1 bits */
#define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
#define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
#define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
/* Firmware image definitions */
#define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
#define QLA8044_BOOT_FROM_FLASH 0
#define QLA8044_IDC_PARAM_ADDR 0x3e8020
/* FLASH related definitions */
#define QLA8044_OPTROM_BURST_SIZE 0x100
#define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
#define QLA8044_MIN_OPTROM_BURST_DWORDS 2
#define QLA8044_SECTOR_SIZE (64 * 1024)
#define QLA8044_FLASH_SPI_CTL 0x4
#define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
#define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
#define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
#define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
#define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
#define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
#define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
#define QLA8044_FLASH_ERASE_SIG 0xFD0300
#define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
/* Reset template definitions */
#define QLA8044_MAX_RESET_SEQ_ENTRIES 16
#define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
#define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
#define QLA8044_RESET_SEQ_VERSION 0x0101
/* Reset template entry opcodes */
#define OPCODE_NOP 0x0000
#define OPCODE_WRITE_LIST 0x0001
#define OPCODE_READ_WRITE_LIST 0x0002
#define OPCODE_POLL_LIST 0x0004
#define OPCODE_POLL_WRITE_LIST 0x0008
#define OPCODE_READ_MODIFY_WRITE 0x0010
#define OPCODE_SEQ_PAUSE 0x0020
#define OPCODE_SEQ_END 0x0040
#define OPCODE_TMPL_END 0x0080
#define OPCODE_POLL_READ_LIST 0x0100
/* Template Header */
#define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
#define QLA8044_IDC_DRV_CTRL 0x3790
#define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
#define MINIDUMP_SIZE_36K 36864
struct qla8044_reset_template_hdr {
uint16_t version;
uint16_t signature;
uint16_t size;
uint16_t entries;
uint16_t hdr_size;
uint16_t checksum;
uint16_t init_seq_offset;
uint16_t start_seq_offset;
} __packed;
/* Common Entry Header. */
struct qla8044_reset_entry_hdr {
uint16_t cmd;
uint16_t size;
uint16_t count;
uint16_t delay;
} __packed;
/* Generic poll entry type. */
struct qla8044_poll {
uint32_t test_mask;
uint32_t test_value;
} __packed;
/* Read modify write entry type. */
struct qla8044_rmw {
uint32_t test_mask;
uint32_t xor_value;
uint32_t or_value;
uint8_t shl;
uint8_t shr;
uint8_t index_a;
uint8_t rsvd;
} __packed;
/* Generic Entry Item with 2 DWords. */
struct qla8044_entry {
uint32_t arg1;
uint32_t arg2;
} __packed;
/* Generic Entry Item with 4 DWords.*/
struct qla8044_quad_entry {
uint32_t dr_addr;
uint32_t dr_value;
uint32_t ar_addr;
uint32_t ar_value;
} __packed;
struct qla8044_reset_template {
int seq_index;
int seq_error;
int array_index;
uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
uint8_t *buff;
uint8_t *stop_offset;
uint8_t *start_offset;
uint8_t *init_offset;
struct qla8044_reset_template_hdr *hdr;
uint8_t seq_end;
uint8_t template_end;
};
/* Driver_code is for driver to write some info about the entry
* currently not used.
*/
struct qla8044_minidump_entry_hdr {
uint32_t entry_type;
uint32_t entry_size;
uint32_t entry_capture_size;
struct {
uint8_t entry_capture_mask;
uint8_t entry_code;
uint8_t driver_code;
uint8_t driver_flags;
} d_ctrl;
} __packed;
/* Read CRB entry header */
struct qla8044_minidump_entry_crb {
struct qla8044_minidump_entry_hdr h;
uint32_t addr;
struct {
uint8_t addr_stride;
uint8_t state_index_a;
uint16_t poll_timeout;
} crb_strd;
uint32_t data_size;
uint32_t op_count;
struct {
uint8_t opcode;
uint8_t state_index_v;
uint8_t shl;
uint8_t shr;
} crb_ctrl;
uint32_t value_1;
uint32_t value_2;
uint32_t value_3;
} __packed;
struct qla8044_minidump_entry_cache {
struct qla8044_minidump_entry_hdr h;
uint32_t tag_reg_addr;
struct {
uint16_t tag_value_stride;
uint16_t init_tag_value;
} addr_ctrl;
uint32_t data_size;
uint32_t op_count;
uint32_t control_addr;
struct {
uint16_t write_value;
uint8_t poll_mask;
uint8_t poll_wait;
} cache_ctrl;
uint32_t read_addr;
struct {
uint8_t read_addr_stride;
uint8_t read_addr_cnt;
uint16_t rsvd_1;
} read_ctrl;
} __packed;
/* Read OCM */
struct qla8044_minidump_entry_rdocm {
struct qla8044_minidump_entry_hdr h;
uint32_t rsvd_0;
uint32_t rsvd_1;
uint32_t data_size;
uint32_t op_count;
uint32_t rsvd_2;
uint32_t rsvd_3;
uint32_t read_addr;
uint32_t read_addr_stride;
} __packed;
/* Read Memory */
struct qla8044_minidump_entry_rdmem {
struct qla8044_minidump_entry_hdr h;
uint32_t rsvd[6];
uint32_t read_addr;
uint32_t read_data_size;
};
/* Read Memory: For Pex-DMA */
struct qla8044_minidump_entry_rdmem_pex_dma {
struct qla8044_minidump_entry_hdr h;
uint32_t desc_card_addr;
uint16_t dma_desc_cmd;
uint8_t rsvd[2];
uint32_t start_dma_cmd;
uint8_t rsvd2[12];
uint32_t read_addr;
uint32_t read_data_size;
} __packed;
/* Read ROM */
struct qla8044_minidump_entry_rdrom {
struct qla8044_minidump_entry_hdr h;
uint32_t rsvd[6];
uint32_t read_addr;
uint32_t read_data_size;
} __packed;
/* Mux entry */
struct qla8044_minidump_entry_mux {
struct qla8044_minidump_entry_hdr h;
uint32_t select_addr;
uint32_t rsvd_0;
uint32_t data_size;
uint32_t op_count;
uint32_t select_value;
uint32_t select_value_stride;
uint32_t read_addr;
uint32_t rsvd_1;
} __packed;
/* Queue entry */
struct qla8044_minidump_entry_queue {
struct qla8044_minidump_entry_hdr h;
uint32_t select_addr;
struct {
uint16_t queue_id_stride;
uint16_t rsvd_0;
} q_strd;
uint32_t data_size;
uint32_t op_count;
uint32_t rsvd_1;
uint32_t rsvd_2;
uint32_t read_addr;
struct {
uint8_t read_addr_stride;
uint8_t read_addr_cnt;
uint16_t rsvd_3;
} rd_strd;
} __packed;
/* POLLRD Entry */
struct qla8044_minidump_entry_pollrd {
struct qla8044_minidump_entry_hdr h;
uint32_t select_addr;
uint32_t read_addr;
uint32_t select_value;
uint16_t select_value_stride;
uint16_t op_count;
uint32_t poll_wait;
uint32_t poll_mask;
uint32_t data_size;
uint32_t rsvd_1;
} __packed;
struct qla8044_minidump_entry_rddfe {
struct qla8044_minidump_entry_hdr h;
uint32_t addr_1;
uint32_t value;
uint8_t stride;
uint8_t stride2;
uint16_t count;
uint32_t poll;
uint32_t mask;
uint32_t modify_mask;
uint32_t data_size;
uint32_t rsvd;
} __packed;
struct qla8044_minidump_entry_rdmdio {
struct qla8044_minidump_entry_hdr h;
uint32_t addr_1;
uint32_t addr_2;
uint32_t value_1;
uint8_t stride_1;
uint8_t stride_2;
uint16_t count;
uint32_t poll;
uint32_t mask;
uint32_t value_2;
uint32_t data_size;
} __packed;
struct qla8044_minidump_entry_pollwr {
struct qla8044_minidump_entry_hdr h;
uint32_t addr_1;
uint32_t addr_2;
uint32_t value_1;
uint32_t value_2;
uint32_t poll;
uint32_t mask;
uint32_t data_size;
uint32_t rsvd;
} __packed;
/* RDMUX2 Entry */
struct qla8044_minidump_entry_rdmux2 {
struct qla8044_minidump_entry_hdr h;
uint32_t select_addr_1;
uint32_t select_addr_2;
uint32_t select_value_1;
uint32_t select_value_2;
uint32_t op_count;
uint32_t select_value_mask;
uint32_t read_addr;
uint8_t select_value_stride;
uint8_t data_size;
uint8_t rsvd[2];
} __packed;
/* POLLRDMWR Entry */
struct qla8044_minidump_entry_pollrdmwr {
struct qla8044_minidump_entry_hdr h;
uint32_t addr_1;
uint32_t addr_2;
uint32_t value_1;
uint32_t value_2;
uint32_t poll_wait;
uint32_t poll_mask;
uint32_t modify_mask;
uint32_t data_size;
} __packed;
/* IDC additional information */
struct qla8044_idc_information {
uint32_t request_desc; /* IDC request descriptor */
uint32_t info1; /* IDC additional info */
uint32_t info2; /* IDC additional info */
uint32_t info3; /* IDC additional info */
} __packed;
enum qla_regs {
QLA8044_PEG_HALT_STATUS1_INDEX = 0,
QLA8044_PEG_HALT_STATUS2_INDEX,
QLA8044_PEG_ALIVE_COUNTER_INDEX,
QLA8044_CRB_DRV_ACTIVE_INDEX,
QLA8044_CRB_DEV_STATE_INDEX,
QLA8044_CRB_DRV_STATE_INDEX,
QLA8044_CRB_DRV_SCRATCH_INDEX,
QLA8044_CRB_DEV_PART_INFO_INDEX,
QLA8044_CRB_DRV_IDC_VERSION_INDEX,
QLA8044_FW_VERSION_MAJOR_INDEX,
QLA8044_FW_VERSION_MINOR_INDEX,
QLA8044_FW_VERSION_SUB_INDEX,
QLA8044_CRB_CMDPEG_STATE_INDEX,
QLA8044_CRB_TEMP_STATE_INDEX,
} __packed;
#define CRB_REG_INDEX_MAX 14
#define CRB_CMDPEG_CHECK_RETRY_COUNT 60
#define CRB_CMDPEG_CHECK_DELAY 500
/* MiniDump Structures */
/* Driver_code is for driver to write some info about the entry
* currently not used.
*/
#define QLA8044_SS_OCM_WNDREG_INDEX 3
#define QLA8044_DBG_STATE_ARRAY_LEN 16
#define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
#define QLA8044_DBG_RSVD_ARRAY_LEN 8
#define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
#define QLA8044_SS_PCI_INDEX 0
#define QLA8044_RDDFE 38
#define QLA8044_RDMDIO 39
#define QLA8044_POLLWR 40
struct qla8044_minidump_template_hdr {
uint32_t entry_type;
uint32_t first_entry_offset;
uint32_t size_of_template;
uint32_t capture_debug_level;
uint32_t num_of_entries;
uint32_t version;
uint32_t driver_timestamp;
uint32_t checksum;
uint32_t driver_capture_mask;
uint32_t driver_info_word2;
uint32_t driver_info_word3;
uint32_t driver_info_word4;
uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
};
struct qla8044_pex_dma_descriptor {
struct {
uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
uint8_t rsvd[2];
uint16_t dma_desc_cmd;
} cmd;
uint64_t src_addr;
uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
uint8_t rsvd[24];
} __packed;
#endif
linux-7.2.3/drivers/scsi/qla2xxx/qla_os.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_settings.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#define MAX_RETRIES_OF_ISP_ABORT 5
/* Max time to wait for the loop to be in LOOP_READY state */
#define MAX_LOOP_TIMEOUT (60 * 5)
#include "qla_version.h"
linux-7.2.3/drivers/scsi/qla2xxx/qla_sup.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_target.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_target.h
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linux-7.2.3/drivers/scsi/qla2xxx/qla_tmpl.c
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linux-7.2.3/drivers/scsi/qla2xxx/qla_tmpl.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#ifndef __QLA_DMP27_H__
#define __QLA_DMP27_H__
#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
struct __packed qla27xx_fwdt_template {
__le32 template_type;
__le32 entry_offset;
__le32 template_size;
uint32_t count; /* borrow field for running/residual count */
__le32 entry_count;
uint32_t template_version;
__le32 capture_timestamp;
uint32_t template_checksum;
uint32_t reserved_2;
__le32 driver_info[3];
uint32_t saved_state[16];
uint32_t reserved_3[8];
__le32 firmware_version[5];
};
#define TEMPLATE_TYPE_FWDUMP 99
#define ENTRY_TYPE_NOP 0
#define ENTRY_TYPE_TMP_END 255
#define ENTRY_TYPE_RD_IOB_T1 256
#define ENTRY_TYPE_WR_IOB_T1 257
#define ENTRY_TYPE_RD_IOB_T2 258
#define ENTRY_TYPE_WR_IOB_T2 259
#define ENTRY_TYPE_RD_PCI 260
#define ENTRY_TYPE_WR_PCI 261
#define ENTRY_TYPE_RD_RAM 262
#define ENTRY_TYPE_GET_QUEUE 263
#define ENTRY_TYPE_GET_FCE 264
#define ENTRY_TYPE_PSE_RISC 265
#define ENTRY_TYPE_RST_RISC 266
#define ENTRY_TYPE_DIS_INTR 267
#define ENTRY_TYPE_GET_HBUF 268
#define ENTRY_TYPE_SCRATCH 269
#define ENTRY_TYPE_RDREMREG 270
#define ENTRY_TYPE_WRREMREG 271
#define ENTRY_TYPE_RDREMRAM 272
#define ENTRY_TYPE_PCICFG 273
#define ENTRY_TYPE_GET_SHADOW 274
#define ENTRY_TYPE_WRITE_BUF 275
#define ENTRY_TYPE_CONDITIONAL 276
#define ENTRY_TYPE_RDPEPREG 277
#define ENTRY_TYPE_WRPEPREG 278
#define CAPTURE_FLAG_PHYS_ONLY BIT_0
#define CAPTURE_FLAG_PHYS_VIRT BIT_1
#define DRIVER_FLAG_SKIP_ENTRY BIT_7
struct __packed qla27xx_fwdt_entry {
struct __packed {
__le32 type;
__le32 size;
uint32_t reserved_1;
uint8_t capture_flags;
uint8_t reserved_2[2];
uint8_t driver_flags;
} hdr;
union __packed {
struct __packed {
} t0;
struct __packed {
} t255;
struct __packed {
__le32 base_addr;
uint8_t reg_width;
__le16 reg_count;
uint8_t pci_offset;
} t256;
struct __packed {
__le32 base_addr;
__le32 write_data;
uint8_t pci_offset;
uint8_t reserved[3];
} t257;
struct __packed {
__le32 base_addr;
uint8_t reg_width;
__le16 reg_count;
uint8_t pci_offset;
uint8_t banksel_offset;
uint8_t reserved[3];
__le32 bank;
} t258;
struct __packed {
__le32 base_addr;
__le32 write_data;
uint8_t reserved[2];
uint8_t pci_offset;
uint8_t banksel_offset;
__le32 bank;
} t259;
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
} t260;
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
__le32 write_data;
} t261;
struct __packed {
uint8_t ram_area;
uint8_t reserved[3];
__le32 start_addr;
__le32 end_addr;
} t262;
struct __packed {
uint32_t num_queues;
uint8_t queue_type;
uint8_t reserved[3];
} t263;
struct __packed {
uint32_t fce_trace_size;
uint64_t write_pointer;
uint64_t base_pointer;
uint32_t fce_enable_mb0;
uint32_t fce_enable_mb2;
uint32_t fce_enable_mb3;
uint32_t fce_enable_mb4;
uint32_t fce_enable_mb5;
uint32_t fce_enable_mb6;
} t264;
struct __packed {
} t265;
struct __packed {
} t266;
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
__le32 data;
} t267;
struct __packed {
uint8_t buf_type;
uint8_t reserved[3];
uint32_t buf_size;
uint64_t start_addr;
} t268;
struct __packed {
uint32_t scratch_size;
} t269;
struct __packed {
__le32 addr;
__le32 count;
} t270;
struct __packed {
__le32 addr;
__le32 data;
} t271;
struct __packed {
__le32 addr;
__le32 count;
} t272;
struct __packed {
__le32 addr;
__le32 count;
} t273;
struct __packed {
uint32_t num_queues;
uint8_t queue_type;
uint8_t reserved[3];
} t274;
struct __packed {
__le32 length;
uint8_t buffer[];
} t275;
struct __packed {
__le32 cond1;
__le32 cond2;
} t276;
struct __packed {
__le32 cmd_addr;
__le32 wr_cmd_data;
__le32 data_addr;
} t277;
struct __packed {
__le32 cmd_addr;
__le32 wr_cmd_data;
__le32 data_addr;
__le32 wr_data;
} t278;
};
};
#define T262_RAM_AREA_CRITICAL_RAM 1
#define T262_RAM_AREA_EXTERNAL_RAM 2
#define T262_RAM_AREA_SHARED_RAM 3
#define T262_RAM_AREA_DDR_RAM 4
#define T262_RAM_AREA_MISC 5
#define T263_QUEUE_TYPE_REQ 1
#define T263_QUEUE_TYPE_RSP 2
#define T263_QUEUE_TYPE_ATIO 3
#define T268_BUF_TYPE_EXTD_TRACE 1
#define T268_BUF_TYPE_EXCH_BUFOFF 2
#define T268_BUF_TYPE_EXTD_LOGIN 3
#define T268_BUF_TYPE_REQ_MIRROR 4
#define T268_BUF_TYPE_RSP_MIRROR 5
#define T274_QUEUE_TYPE_REQ_SHAD 1
#define T274_QUEUE_TYPE_RSP_SHAD 2
#define T274_QUEUE_TYPE_ATIO_SHAD 3
#endif
linux-7.2.3/drivers/scsi/qla2xxx/qla_version.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
/*
* Driver version
*/
#define QLA2XXX_VERSION "10.02.10.100-k"
#define QLA_DRIVER_MAJOR_VER 10
#define QLA_DRIVER_MINOR_VER 02
#define QLA_DRIVER_PATCH_VER 10
#define QLA_DRIVER_BETA_VER 100
linux-7.2.3/drivers/scsi/qla2xxx/tcm_qla2xxx.c
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linux-7.2.3/drivers/scsi/qla2xxx/tcm_qla2xxx.h
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/* SPDX-License-Identifier: GPL-2.0 */
#include <target/target_core_base.h>
#include <linux/btree.h>
/* length of ASCII WWPNs including pad */
#define TCM_QLA2XXX_NAMELEN 32
/*
* Number of pre-allocated per-session tags, based upon the worst-case
* per port number of iocbs
*/
#define TCM_QLA2XXX_DEFAULT_TAGS 2088
#include "qla_target.h"
struct tcm_qla2xxx_nacl {
struct se_node_acl se_node_acl;
/* From libfc struct fc_rport->port_id */
u32 nport_id;
/* Binary World Wide unique Node Name for remote FC Initiator Nport */
u64 nport_wwnn;
/* ASCII formatted WWPN for FC Initiator Nport */
char nport_name[TCM_QLA2XXX_NAMELEN];
/* Pointer to fc_port */
struct fc_port *fc_port;
/* Pointer to TCM FC nexus */
struct se_session *nport_nexus;
};
struct tcm_qla2xxx_tpg_attrib {
int generate_node_acls;
int cache_dynamic_acls;
int demo_mode_write_protect;
int prod_mode_write_protect;
int demo_mode_login_only;
int fabric_prot_type;
int jam_host;
};
struct tcm_qla2xxx_tpg {
/* FC lport target portal group tag for TCM */
u16 lport_tpgt;
/* Atomic bit to determine TPG active status */
atomic_t lport_tpg_enabled;
/* Pointer back to tcm_qla2xxx_lport */
struct tcm_qla2xxx_lport *lport;
/* Used by tcm_qla2xxx_tpg_attrib_cit */
struct tcm_qla2xxx_tpg_attrib tpg_attrib;
/* Returned by tcm_qla2xxx_make_tpg() */
struct se_portal_group se_tpg;
};
struct tcm_qla2xxx_fc_loopid {
struct se_node_acl *se_nacl;
};
struct tcm_qla2xxx_lport {
/* Binary World Wide unique Port Name for FC Target Lport */
u64 lport_wwpn;
/* Binary World Wide unique Port Name for FC NPIV Target Lport */
u64 lport_npiv_wwpn;
/* Binary World Wide unique Node Name for FC NPIV Target Lport */
u64 lport_npiv_wwnn;
/* ASCII formatted WWPN for FC Target Lport */
char lport_name[TCM_QLA2XXX_NAMELEN];
/* ASCII formatted naa WWPN for VPD page 83 etc */
char lport_naa_name[TCM_QLA2XXX_NAMELEN];
/* map for fc_port pointers in 24-bit FC Port ID space */
struct btree_head32 lport_fcport_map;
/* vmalloc-ed memory for fc_port pointers for 16-bit FC loop ID */
struct tcm_qla2xxx_fc_loopid *lport_loopid_map;
/* Pointer to struct scsi_qla_host from qla2xxx LLD */
struct scsi_qla_host *qla_vha;
/* Pointer to struct qla_tgt pointer */
struct qla_tgt lport_qla_tgt;
/* Pointer to TPG=1 for non NPIV mode */
struct tcm_qla2xxx_tpg *tpg_1;
/* Returned by tcm_qla2xxx_make_lport() */
struct se_wwn lport_wwn;
};