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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/include/drm/display/drm_dp.h
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linux-7.2.3/include/drm/display/drm_dp_aux_bus.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2021 Google Inc.
*
* The DP AUX bus is used for devices that are connected over a DisplayPort
* AUX bus. The devices on the far side of the bus are referred to as
* endpoints in this code.
*/
#ifndef _DP_AUX_BUS_H_
#define _DP_AUX_BUS_H_
#include <linux/device.h>
#include <linux/mod_devicetable.h>
/**
* struct dp_aux_ep_device - Main dev structure for DP AUX endpoints
*
* This is used to instantiate devices that are connected via a DP AUX
* bus. Usually the device is a panel, but conceivable other devices could
* be hooked up there.
*/
struct dp_aux_ep_device {
/** @dev: The normal dev pointer */
struct device dev;
/** @aux: Pointer to the aux bus */
struct drm_dp_aux *aux;
};
struct dp_aux_ep_driver {
int (*probe)(struct dp_aux_ep_device *aux_ep);
void (*remove)(struct dp_aux_ep_device *aux_ep);
void (*shutdown)(struct dp_aux_ep_device *aux_ep);
struct device_driver driver;
};
static inline struct dp_aux_ep_device *to_dp_aux_ep_dev(struct device *dev)
{
return container_of(dev, struct dp_aux_ep_device, dev);
}
static inline struct dp_aux_ep_driver *to_dp_aux_ep_drv(struct device_driver *drv)
{
return container_of(drv, struct dp_aux_ep_driver, driver);
}
int of_dp_aux_populate_bus(struct drm_dp_aux *aux,
int (*done_probing)(struct drm_dp_aux *aux));
void of_dp_aux_depopulate_bus(struct drm_dp_aux *aux);
int devm_of_dp_aux_populate_bus(struct drm_dp_aux *aux,
int (*done_probing)(struct drm_dp_aux *aux));
/* Deprecated versions of the above functions. To be removed when no callers. */
static inline int of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux)
{
int ret;
ret = of_dp_aux_populate_bus(aux, NULL);
/* New API returns -ENODEV for no child case; adapt to old assumption */
return (ret != -ENODEV) ? ret : 0;
}
static inline int devm_of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux)
{
int ret;
ret = devm_of_dp_aux_populate_bus(aux, NULL);
/* New API returns -ENODEV for no child case; adapt to old assumption */
return (ret != -ENODEV) ? ret : 0;
}
static inline void of_dp_aux_depopulate_ep_devices(struct drm_dp_aux *aux)
{
of_dp_aux_depopulate_bus(aux);
}
#define dp_aux_dp_driver_register(aux_ep_drv) \
__dp_aux_dp_driver_register(aux_ep_drv, THIS_MODULE)
int __dp_aux_dp_driver_register(struct dp_aux_ep_driver *aux_ep_drv,
struct module *owner);
void dp_aux_dp_driver_unregister(struct dp_aux_ep_driver *aux_ep_drv);
#endif /* _DP_AUX_BUS_H_ */
linux-7.2.3/include/drm/display/drm_dp_dual_mode_helper.h
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/*
* Copyright © 2016 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef DRM_DP_DUAL_MODE_HELPER_H
#define DRM_DP_DUAL_MODE_HELPER_H
#include <linux/types.h>
/*
* Optional for type 1 DVI adaptors
* Mandatory for type 1 HDMI and type 2 adaptors
*/
#define DP_DUAL_MODE_HDMI_ID 0x00 /* 00-0f */
#define DP_DUAL_MODE_HDMI_ID_LEN 16
/*
* Optional for type 1 adaptors
* Mandatory for type 2 adaptors
*/
#define DP_DUAL_MODE_ADAPTOR_ID 0x10
#define DP_DUAL_MODE_REV_MASK 0x07
#define DP_DUAL_MODE_REV_TYPE2 0x00
#define DP_DUAL_MODE_TYPE_MASK 0xf0
#define DP_DUAL_MODE_TYPE_TYPE2 0xa0
/* This field is marked reserved in dual mode spec, used in LSPCON */
#define DP_DUAL_MODE_TYPE_HAS_DPCD 0x08
#define DP_DUAL_MODE_IEEE_OUI 0x11 /* 11-13*/
#define DP_DUAL_IEEE_OUI_LEN 3
#define DP_DUAL_DEVICE_ID 0x14 /* 14-19 */
#define DP_DUAL_DEVICE_ID_LEN 6
#define DP_DUAL_MODE_HARDWARE_REV 0x1a
#define DP_DUAL_MODE_FIRMWARE_MAJOR_REV 0x1b
#define DP_DUAL_MODE_FIRMWARE_MINOR_REV 0x1c
#define DP_DUAL_MODE_MAX_TMDS_CLOCK 0x1d
#define DP_DUAL_MODE_I2C_SPEED_CAP 0x1e
#define DP_DUAL_MODE_TMDS_OEN 0x20
#define DP_DUAL_MODE_TMDS_DISABLE 0x01
#define DP_DUAL_MODE_HDMI_PIN_CTRL 0x21
#define DP_DUAL_MODE_CEC_ENABLE 0x01
#define DP_DUAL_MODE_I2C_SPEED_CTRL 0x22
/* LSPCON specific registers, defined by MCA */
#define DP_DUAL_MODE_LSPCON_MODE_CHANGE 0x40
#define DP_DUAL_MODE_LSPCON_CURRENT_MODE 0x41
#define DP_DUAL_MODE_LSPCON_MODE_PCON 0x1
struct drm_device;
struct i2c_adapter;
ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter,
u8 offset, void *buffer, size_t size);
ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter,
u8 offset, const void *buffer, size_t size);
/**
* enum drm_lspcon_mode
* @DRM_LSPCON_MODE_INVALID: No LSPCON.
* @DRM_LSPCON_MODE_LS: Level shifter mode of LSPCON
* which drives DP++ to HDMI 1.4 conversion.
* @DRM_LSPCON_MODE_PCON: Protocol converter mode of LSPCON
* which drives DP++ to HDMI 2.0 active conversion.
*/
enum drm_lspcon_mode {
DRM_LSPCON_MODE_INVALID,
DRM_LSPCON_MODE_LS,
DRM_LSPCON_MODE_PCON,
};
/**
* enum drm_dp_dual_mode_type - Type of the DP dual mode adaptor
* @DRM_DP_DUAL_MODE_NONE: No DP dual mode adaptor
* @DRM_DP_DUAL_MODE_UNKNOWN: Could be either none or type 1 DVI adaptor
* @DRM_DP_DUAL_MODE_TYPE1_DVI: Type 1 DVI adaptor
* @DRM_DP_DUAL_MODE_TYPE1_HDMI: Type 1 HDMI adaptor
* @DRM_DP_DUAL_MODE_TYPE2_DVI: Type 2 DVI adaptor
* @DRM_DP_DUAL_MODE_TYPE2_HDMI: Type 2 HDMI adaptor
* @DRM_DP_DUAL_MODE_LSPCON: Level shifter / protocol converter
*/
enum drm_dp_dual_mode_type {
DRM_DP_DUAL_MODE_NONE,
DRM_DP_DUAL_MODE_UNKNOWN,
DRM_DP_DUAL_MODE_TYPE1_DVI,
DRM_DP_DUAL_MODE_TYPE1_HDMI,
DRM_DP_DUAL_MODE_TYPE2_DVI,
DRM_DP_DUAL_MODE_TYPE2_HDMI,
DRM_DP_DUAL_MODE_LSPCON,
};
enum drm_dp_dual_mode_type
drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter *adapter);
int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum drm_dp_dual_mode_type type,
struct i2c_adapter *adapter);
int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool *enabled);
int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool enable);
const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type);
int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter *adapter,
enum drm_lspcon_mode *current_mode);
int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter *adapter,
enum drm_lspcon_mode reqd_mode, int time_out);
#endif
linux-7.2.3/include/drm/display/drm_dp_helper.h
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linux-7.2.3/include/drm/display/drm_dp_mst_helper.h
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linux-7.2.3/include/drm/display/drm_dp_tunnel.h
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/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __DRM_DP_TUNNEL_H__
#define __DRM_DP_TUNNEL_H__
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/types.h>
struct drm_dp_aux;
struct drm_device;
struct drm_atomic_commit;
struct drm_dp_tunnel_mgr;
struct drm_dp_tunnel_state;
struct ref_tracker;
struct drm_dp_tunnel_ref {
struct drm_dp_tunnel *tunnel;
struct ref_tracker *tracker;
};
#ifdef CONFIG_DRM_DISPLAY_DP_TUNNEL
struct drm_dp_tunnel *
drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker);
void
drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker);
static inline void drm_dp_tunnel_ref_get(struct drm_dp_tunnel *tunnel,
struct drm_dp_tunnel_ref *tunnel_ref)
{
tunnel_ref->tunnel = drm_dp_tunnel_get(tunnel, &tunnel_ref->tracker);
}
static inline void drm_dp_tunnel_ref_put(struct drm_dp_tunnel_ref *tunnel_ref)
{
drm_dp_tunnel_put(tunnel_ref->tunnel, &tunnel_ref->tracker);
tunnel_ref->tunnel = NULL;
}
struct drm_dp_tunnel *
drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
struct drm_dp_aux *aux);
int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel);
bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel);
void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
struct drm_dp_aux *aux);
int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel);
const char *drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel);
struct drm_dp_tunnel_state *
drm_dp_tunnel_atomic_get_state(struct drm_atomic_commit *state,
struct drm_dp_tunnel *tunnel);
struct drm_dp_tunnel_state *
drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_commit *state,
const struct drm_dp_tunnel *tunnel);
struct drm_dp_tunnel_state *
drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_commit *state,
const struct drm_dp_tunnel *tunnel);
int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_commit *state,
struct drm_dp_tunnel *tunnel,
u8 stream_id, int bw);
int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_commit *state,
const struct drm_dp_tunnel *tunnel,
u32 *stream_mask);
int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_commit *state,
u32 *failed_stream_mask);
int drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state);
struct drm_dp_tunnel_mgr *
drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count);
void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr);
#else
static inline struct drm_dp_tunnel *
drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker)
{
return NULL;
}
static inline void
drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker) {}
static inline void drm_dp_tunnel_ref_get(struct drm_dp_tunnel *tunnel,
struct drm_dp_tunnel_ref *tunnel_ref) {}
static inline void drm_dp_tunnel_ref_put(struct drm_dp_tunnel_ref *tunnel_ref) {}
static inline struct drm_dp_tunnel *
drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
struct drm_dp_aux *aux)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline int
drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel)
{
return 0;
}
static inline int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel)
{
return -EOPNOTSUPP;
}
static inline int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel)
{
return -EOPNOTSUPP;
}
static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
{
return false;
}
static inline bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel)
{
return false;
}
static inline int
drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
{
return -EOPNOTSUPP;
}
static inline int
drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel)
{
return -1;
}
static inline int
drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel)
{
return -EOPNOTSUPP;
}
static inline void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel) {}
static inline int
drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
struct drm_dp_aux *aux)
{
return -EOPNOTSUPP;
}
static inline int
drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)
{
return 0;
}
static inline int
drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel)
{
return 0;
}
static inline int
drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel)
{
return -1;
}
static inline const char *
drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel)
{
return NULL;
}
static inline struct drm_dp_tunnel_state *
drm_dp_tunnel_atomic_get_state(struct drm_atomic_commit *state,
struct drm_dp_tunnel *tunnel)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline struct drm_dp_tunnel_state *
drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_commit *state,
const struct drm_dp_tunnel *tunnel)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline int
drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_commit *state,
struct drm_dp_tunnel *tunnel,
u8 stream_id, int bw)
{
return -EOPNOTSUPP;
}
static inline int
drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_commit *state,
const struct drm_dp_tunnel *tunnel,
u32 *stream_mask)
{
return -EOPNOTSUPP;
}
static inline int
drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_commit *state,
u32 *failed_stream_mask)
{
return -EOPNOTSUPP;
}
static inline int
drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state)
{
return 0;
}
static inline struct drm_dp_tunnel_mgr *
drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline
void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr) {}
#endif /* CONFIG_DRM_DISPLAY_DP_TUNNEL */
#endif /* __DRM_DP_TUNNEL_H__ */
linux-7.2.3/include/drm/display/drm_dsc.h
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/* SPDX-License-Identifier: MIT
* Copyright (C) 2018 Intel Corp.
*
* Authors:
* Manasi Navare <manasi.d.navare@intel.com>
*/
#ifndef DRM_DSC_H_
#define DRM_DSC_H_
#include <drm/display/drm_dp.h>
/* VESA Display Stream Compression DSC 1.2 constants */
#define DSC_NUM_BUF_RANGES 15
#define DSC_MUX_WORD_SIZE_8_10_BPC 48
#define DSC_MUX_WORD_SIZE_12_BPC 64
#define DSC_RC_PIXELS_PER_GROUP 3
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
/* DSC Rate Control Constants */
#define DSC_RC_MODEL_SIZE_CONST 8192
#define DSC_RC_EDGE_FACTOR_CONST 6
#define DSC_RC_TGT_OFFSET_HI_CONST 3
#define DSC_RC_TGT_OFFSET_LO_CONST 3
/* DSC PPS constants and macros */
#define DSC_PPS_VERSION_MAJOR_SHIFT 4
#define DSC_PPS_BPC_SHIFT 4
#define DSC_PPS_MSB_SHIFT 8
#define DSC_PPS_LSB_MASK (0xFF << 0)
#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8)
#define DSC_PPS_VBR_EN_SHIFT 2
#define DSC_PPS_SIMPLE422_SHIFT 3
#define DSC_PPS_CONVERT_RGB_SHIFT 4
#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5
#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8)
#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8)
#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
/**
* struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
*
* This defines different rate control parameters used by the DSC engine
* to compress the frame.
*/
struct drm_dsc_rc_range_parameters {
/**
* @range_min_qp: Min Quantization Parameters allowed for this range
*/
u8 range_min_qp;
/**
* @range_max_qp: Max Quantization Parameters allowed for this range
*/
u8 range_max_qp;
/**
* @range_bpg_offset:
* Bits/group offset to apply to target for this group
*/
u8 range_bpg_offset;
};
/**
* struct drm_dsc_config - Parameters required to configure DSC
*
* Driver populates this structure with all the parameters required
* to configure the display stream compression on the source.
*/
struct drm_dsc_config {
/**
* @line_buf_depth:
* Bits per component for previous reconstructed line buffer
*/
u8 line_buf_depth;
/**
* @bits_per_component: Bits per component to code (8/10/12)
*/
u8 bits_per_component;
/**
* @convert_rgb:
* Flag to indicate if RGB - YCoCg conversion is needed
* True if RGB input, False if YCoCg input
*/
bool convert_rgb;
/**
* @slice_count: Number fo slices per line used by the DSC encoder
*/
u8 slice_count;
/**
* @slice_width: Width of each slice in pixels
*/
u16 slice_width;
/**
* @slice_height: Slice height in pixels
*/
u16 slice_height;
/**
* @simple_422: True if simple 4_2_2 mode is enabled else False
*/
bool simple_422;
/**
* @pic_width: Width of the input display frame in pixels
*/
u16 pic_width;
/**
* @pic_height: Vertical height of the input display frame
*/
u16 pic_height;
/**
* @rc_tgt_offset_high:
* Offset to bits/group used by RC to determine QP adjustment
*/
u8 rc_tgt_offset_high;
/**
* @rc_tgt_offset_low:
* Offset to bits/group used by RC to determine QP adjustment
*/
u8 rc_tgt_offset_low;
/**
* @bits_per_pixel:
* Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
*/
u16 bits_per_pixel;
/**
* @rc_edge_factor:
* Factor to determine if an edge is present based on the bits produced
*/
u8 rc_edge_factor;
/**
* @rc_quant_incr_limit1:
* Slow down incrementing once the range reaches this value
*/
u8 rc_quant_incr_limit1;
/**
* @rc_quant_incr_limit0:
* Slow down incrementing once the range reaches this value
*/
u8 rc_quant_incr_limit0;
/**
* @initial_xmit_delay:
* Number of pixels to delay the initial transmission
*/
u16 initial_xmit_delay;
/**
* @initial_dec_delay:
* Initial decoder delay, number of pixel times that the decoder
* accumulates data in its rate buffer before starting to decode
* and output pixels.
*/
u16 initial_dec_delay;
/**
* @block_pred_enable:
* True if block prediction is used to code any groups within the
* picture. False if BP not used
*/
bool block_pred_enable;
/**
* @first_line_bpg_offset:
* Number of additional bits allocated for each group on the first
* line of slice.
*/
u8 first_line_bpg_offset;
/**
* @initial_offset: Value to use for RC model offset at slice start
*/
u16 initial_offset;
/**
* @rc_buf_thresh: Thresholds defining each of the buffer ranges
*/
u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
/**
* @rc_range_params:
* Parameters for each of the RC ranges defined in
* &struct drm_dsc_rc_range_parameters
*/
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
/**
* @rc_model_size: Total size of RC model
*/
u16 rc_model_size;
/**
* @flatness_min_qp: Minimum QP where flatness information is sent
*/
u8 flatness_min_qp;
/**
* @flatness_max_qp: Maximum QP where flatness information is sent
*/
u8 flatness_max_qp;
/**
* @initial_scale_value: Initial value for the scale factor
*/
u8 initial_scale_value;
/**
* @scale_decrement_interval:
* Specifies number of group times between decrementing the scale factor
* at beginning of a slice.
*/
u16 scale_decrement_interval;
/**
* @scale_increment_interval:
* Number of group times between incrementing the scale factor value
* used at the beginning of a slice.
*/
u16 scale_increment_interval;
/**
* @nfl_bpg_offset: Non first line BPG offset to be used
*/
u16 nfl_bpg_offset;
/**
* @slice_bpg_offset: BPG offset used to enforce slice bit
*/
u16 slice_bpg_offset;
/**
* @final_offset: Final RC linear transformation offset value
*/
u16 final_offset;
/**
* @vbr_enable: True if VBR mode is enabled, false if disabled
*/
bool vbr_enable;
/**
* @mux_word_size: Mux word size (in bits) for SSM mode
*/
u8 mux_word_size;
/**
* @slice_chunk_size:
* The (max) size in bytes of the "chunks" that are used in slice
* multiplexing.
*/
u16 slice_chunk_size;
/**
* @rc_bits: Rate control buffer size in bits
*/
u16 rc_bits;
/**
* @dsc_version_minor: DSC minor version
*/
u8 dsc_version_minor;
/**
* @dsc_version_major: DSC major version
*/
u8 dsc_version_major;
/**
* @native_422: True if Native 4:2:2 supported, else false
*/
bool native_422;
/**
* @native_420: True if Native 4:2:0 supported else false.
*/
bool native_420;
/**
* @second_line_bpg_offset:
* Additional bits/grp for seconnd line of slice for native 4:2:0
*/
u8 second_line_bpg_offset;
/**
* @nsl_bpg_offset:
* Num of bits deallocated for each grp that is not in second line of
* slice
*/
u16 nsl_bpg_offset;
/**
* @second_line_offset_adj:
* Offset adjustment for second line in Native 4:2:0 mode
*/
u16 second_line_offset_adj;
};
/**
* struct drm_dsc_picture_parameter_set - Represents 128 bytes of
* Picture Parameter Set
*
* The VESA DSC standard defines picture parameter set (PPS) which display
* stream compression encoders must communicate to decoders.
* The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
* this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
* The PPS fields that span over more than a byte should be stored in Big Endian
* format.
*/
struct drm_dsc_picture_parameter_set {
/**
* @dsc_version:
* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
* PPS0[7:4] - dsc_version_major: Contains major version of DSC
*/
u8 dsc_version;
/**
* @pps_identifier:
* PPS1[7:0] - Application specific identifier that can be
* used to differentiate between different PPS tables.
*/
u8 pps_identifier;
/**
* @pps_reserved:
* PPS2[7:0]- RESERVED Byte
*/
u8 pps_reserved;
/**
* @pps_3:
* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
* PPS3[7:4] - bits_per_component: Bits per component for the original
* pixels of the encoded picture.
* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
* allowed only when dsc_minor_version = 0x2)
*/
u8 pps_3;
/**
* @pps_4:
* PPS4[1:0] -These are the most significant 2 bits of
* compressed BPP bits_per_pixel[9:0] syntax element.
* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
* PPS4[3] - simple_422: Indicates if decoder drops samples to
* reconstruct the 4:2:2 picture.
* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
* active.
* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
* groups in picture
* PPS4[7:6] - Reseved bits
*/
u8 pps_4;
/**
* @bits_per_pixel_low:
* PPS5[7:0] - This indicates the lower significant 8 bits of
* the compressed BPP bits_per_pixel[9:0] element.
*/
u8 bits_per_pixel_low;
/**
* @pic_height:
* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
* within the raster.
*/
__be16 pic_height;
/**
* @pic_width:
* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
* the raster.
*/
__be16 pic_width;
/**
* @slice_height:
* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
*/
__be16 slice_height;
/**
* @slice_width:
* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
*/
__be16 slice_width;
/**
* @chunk_size:
* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
* that are used for slice multiplexing.
*/
__be16 chunk_size;
/**
* @initial_xmit_delay_high:
* PPS16[1:0] - Most Significant two bits of initial transmission delay.
* It specifies the number of pixel times that the encoder waits before
* transmitting data from its rate buffer.
* PPS16[7:2] - Reserved
*/
u8 initial_xmit_delay_high;
/**
* @initial_xmit_delay_low:
* PPS17[7:0] - Least significant 8 bits of initial transmission delay.
*/
u8 initial_xmit_delay_low;
/**
* @initial_dec_delay:
*
* PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
* of pixel times that the decoder accumulates data in its rate buffer
* before starting to decode and output pixels.
*/
__be16 initial_dec_delay;
/**
* @pps20_reserved:
*
* PPS20[7:0] - Reserved
*/
u8 pps20_reserved;
/**
* @initial_scale_value:
* PPS21[5:0] - Initial rcXformScale factor used at beginning
* of a slice.
* PPS21[7:6] - Reserved
*/
u8 initial_scale_value;
/**
* @scale_increment_interval:
* PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
* the rcXformScale factor at end of a slice.
*/
__be16 scale_increment_interval;
/**
* @scale_decrement_interval_high:
* PPS24[3:0] - Higher 4 bits indicating number of group times between
* decrementing the rcXformScale factor at beginning of a slice.
* PPS24[7:4] - Reserved
*/
u8 scale_decrement_interval_high;
/**
* @scale_decrement_interval_low:
* PPS25[7:0] - Lower 8 bits of scale decrement interval
*/
u8 scale_decrement_interval_low;
/**
* @pps26_reserved:
* PPS26[7:0]
*/
u8 pps26_reserved;
/**
* @first_line_bpg_offset:
* PPS27[4:0] - Number of additional bits that are allocated
* for each group on first line of a slice.
* PPS27[7:5] - Reserved
*/
u8 first_line_bpg_offset;
/**
* @nfl_bpg_offset:
* PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
* deallocated for each group for groups after the first line of slice.
*/
__be16 nfl_bpg_offset;
/**
* @slice_bpg_offset:
* PPS30, PPS31[7:0] - Number of bits that are deallocated for each
* group to enforce the slice constraint.
*/
__be16 slice_bpg_offset;
/**
* @initial_offset:
* PPS32,33[7:0] - Initial value for rcXformOffset
*/
__be16 initial_offset;
/**
* @final_offset:
* PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
*/
__be16 final_offset;
/**
* @flatness_min_qp:
* PPS36[4:0] - Minimum QP at which flatness is signaled and
* flatness QP adjustment is made.
* PPS36[7:5] - Reserved
*/
u8 flatness_min_qp;
/**
* @flatness_max_qp:
* PPS37[4:0] - Max QP at which flatness is signalled and
* the flatness adjustment is made.
* PPS37[7:5] - Reserved
*/
u8 flatness_max_qp;
/**
* @rc_model_size:
* PPS38,39[7:0] - Number of bits within RC Model.
*/
__be16 rc_model_size;
/**
* @rc_edge_factor:
* PPS40[3:0] - Ratio of current activity vs, previous
* activity to determine presence of edge.
* PPS40[7:4] - Reserved
*/
u8 rc_edge_factor;
/**
* @rc_quant_incr_limit0:
* PPS41[4:0] - QP threshold used in short term RC
* PPS41[7:5] - Reserved
*/
u8 rc_quant_incr_limit0;
/**
* @rc_quant_incr_limit1:
* PPS42[4:0] - QP threshold used in short term RC
* PPS42[7:5] - Reserved
*/
u8 rc_quant_incr_limit1;
/**
* @rc_tgt_offset:
* PPS43[3:0] - Lower end of the variability range around the target
* bits per group that is allowed by short term RC.
* PPS43[7:4]- Upper end of the variability range around the target
* bits per group that i allowed by short term rc.
*/
u8 rc_tgt_offset;
/**
* @rc_buf_thresh:
* PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
* the 15 ranges defined by 14 thresholds.
*/
u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
/**
* @rc_range_parameters:
* PPS58[7:0] - PPS87[7:0]
* Parameters that correspond to each of the 15 ranges.
*/
__be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
/**
* @native_422_420:
* PPS88[0] - 0 = Native 4:2:2 not used
* 1 = Native 4:2:2 used
* PPS88[1] - 0 = Native 4:2:0 not use
* 1 = Native 4:2:0 used
* PPS88[7:2] - Reserved 6 bits
*/
u8 native_422_420;
/**
* @second_line_bpg_offset:
* PPS89[4:0] - Additional bits/group budget for the
* second line of a slice in Native 4:2:0 mode.
* Set to 0 if DSC minor version is 1 or native420 is 0.
* PPS89[7:5] - Reserved
*/
u8 second_line_bpg_offset;
/**
* @nsl_bpg_offset:
* PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
* for each group that is not in the second line of a slice.
*/
__be16 nsl_bpg_offset;
/**
* @second_line_offset_adj:
* PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
* line in Native 4:2:0 mode.
*/
__be16 second_line_offset_adj;
/**
* @pps_long_94_reserved:
* PPS 94, 95, 96, 97 - Reserved
*/
u32 pps_long_94_reserved;
/**
* @pps_long_98_reserved:
* PPS 98, 99, 100, 101 - Reserved
*/
u32 pps_long_98_reserved;
/**
* @pps_long_102_reserved:
* PPS 102, 103, 104, 105 - Reserved
*/
u32 pps_long_102_reserved;
/**
* @pps_long_106_reserved:
* PPS 106, 107, 108, 109 - reserved
*/
u32 pps_long_106_reserved;
/**
* @pps_long_110_reserved:
* PPS 110, 111, 112, 113 - reserved
*/
u32 pps_long_110_reserved;
/**
* @pps_long_114_reserved:
* PPS 114 - 117 - reserved
*/
u32 pps_long_114_reserved;
/**
* @pps_long_118_reserved:
* PPS 118 - 121 - reserved
*/
u32 pps_long_118_reserved;
/**
* @pps_long_122_reserved:
* PPS 122- 125 - reserved
*/
u32 pps_long_122_reserved;
/**
* @pps_short_126_reserved:
* PPS 126, 127 - reserved
*/
__be16 pps_short_126_reserved;
} __packed;
/**
* struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
* Set Metadata
*
* This structure represents the DSC PPS infoframe required to send the Picture
* Parameter Set metadata required before enabling VESA Display Stream
* Compression. This is based on the DP Secondary Data Packet structure and
* comprises of SDP Header as defined &struct dp_sdp_header in drm_dp_helper.h
* and PPS payload defined in &struct drm_dsc_picture_parameter_set.
*
* @pps_header: Header for PPS as per DP SDP header format of type
* &struct dp_sdp_header
* @pps_payload: PPS payload fields as per DSC specification Table 4-1
* as represented in &struct drm_dsc_picture_parameter_set
*/
struct drm_dsc_pps_infoframe {
struct dp_sdp_header pps_header;
struct drm_dsc_picture_parameter_set pps_payload;
} __packed;
#endif /* _DRM_DSC_H_ */
linux-7.2.3/include/drm/display/drm_dsc_helper.h
+36
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/* SPDX-License-Identifier: MIT
* Copyright (C) 2018 Intel Corp.
*
* Authors:
* Manasi Navare <manasi.d.navare@intel.com>
*/
#ifndef DRM_DSC_HELPER_H_
#define DRM_DSC_HELPER_H_
#include <drm/display/drm_dsc.h>
enum drm_dsc_params_type {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
DRM_DSC_1_2_422,
DRM_DSC_1_2_420,
};
struct drm_printer;
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg);
void drm_dsc_dump_config(struct drm_printer *p, int indent, const struct drm_dsc_config *cfg);
#endif /* _DRM_DSC_HELPER_H_ */
linux-7.2.3/include/drm/display/drm_hdcp.h
+298
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/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2017 Google, Inc.
*
* Authors:
* Sean Paul <seanpaul@chromium.org>
*/
#ifndef _DRM_HDCP_H_
#define _DRM_HDCP_H_
#include <linux/types.h>
/* Period of hdcp checks (to ensure we're still authenticated) */
#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
#define DRM_HDCP2_CHECK_PERIOD_MS 500
/* Shared lengths/masks between HDMI/DVI/DisplayPort */
#define DRM_HDCP_AN_LEN 8
#define DRM_HDCP_BSTATUS_LEN 2
#define DRM_HDCP_KSV_LEN 5
#define DRM_HDCP_RI_LEN 2
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
/* Slave address for the HDCP registers in the receiver */
#define DRM_HDCP_DDC_ADDR 0x3A
/* Value to use at the end of the SHA-1 bytestream used for repeaters */
#define DRM_HDCP_SHA1_TERMINATOR 0x80
/* HDCP register offsets for HDMI/DVI devices */
#define DRM_HDCP_DDC_BKSV 0x00
#define DRM_HDCP_DDC_RI_PRIME 0x08
#define DRM_HDCP_DDC_AKSV 0x10
#define DRM_HDCP_DDC_AN 0x18
#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
#define DRM_HDCP_DDC_BCAPS 0x40
#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
#define DRM_HDCP_DDC_BSTATUS 0x41
#define DRM_HDCP_DDC_KSV_FIFO 0x43
#define DRM_HDCP_1_4_SRM_ID 0x8
#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
/* Protocol message definition for HDCP2.2 specification */
/*
* Protected content streams are classified into 2 types:
* - Type0: Can be transmitted with HDCP 1.4+
* - Type1: Can be transmitted with HDCP 2.2+
*/
#define HDCP_STREAM_TYPE0 0x00
#define HDCP_STREAM_TYPE1 0x01
/* HDCP2.2 Msg IDs */
#define HDCP_2_2_NULL_MSG 1
#define HDCP_2_2_AKE_INIT 2
#define HDCP_2_2_AKE_SEND_CERT 3
#define HDCP_2_2_AKE_NO_STORED_KM 4
#define HDCP_2_2_AKE_STORED_KM 5
#define HDCP_2_2_AKE_SEND_HPRIME 7
#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
#define HDCP_2_2_LC_INIT 9
#define HDCP_2_2_LC_SEND_LPRIME 10
#define HDCP_2_2_SKE_SEND_EKS 11
#define HDCP_2_2_REP_SEND_RECVID_LIST 12
#define HDCP_2_2_REP_SEND_ACK 15
#define HDCP_2_2_REP_STREAM_MANAGE 16
#define HDCP_2_2_REP_STREAM_READY 17
#define HDCP_2_2_RTX_LEN 8
#define HDCP_2_2_RRX_LEN 8
#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
HDCP_2_2_K_PUB_RX_EXP_E_LEN)
#define HDCP_2_2_DCP_LLC_SIG_LEN 384
#define HDCP_2_2_E_KPUB_KM_LEN 128
#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
#define HDCP_2_2_H_PRIME_LEN 32
#define HDCP_2_2_E_KH_KM_LEN 16
#define HDCP_2_2_RN_LEN 8
#define HDCP_2_2_L_PRIME_LEN 32
#define HDCP_2_2_E_DKEY_KS_LEN 16
#define HDCP_2_2_RIV_LEN 8
#define HDCP_2_2_SEQ_NUM_LEN 3
#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
#define HDCP_2_2_MAX_DEVICE_COUNT 31
#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
HDCP_2_2_MAX_DEVICE_COUNT)
#define HDCP_2_2_MPRIME_LEN 32
/* Following Macros take a byte at a time for bit(s) masking */
/*
* TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
* H/W MST streams capacity.
* This required to be moved out to platform specific header.
*/
#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
#define HDCP_2_2_RXINFO_LEN 2
/* HDCP1.x compliant device in downstream */
#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
/* HDCP2.0 Compliant repeater in downstream */
#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
struct hdcp2_cert_rx {
u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
u8 reserved[2];
u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
} __packed;
struct hdcp2_streamid_type {
u8 stream_id;
u8 stream_type;
} __packed;
/*
* The TxCaps field specified in the HDCP HDMI, DP specs
* This field is big endian as specified in the errata.
*/
struct hdcp2_tx_caps {
/* Transmitter must set this to 0x2 */
u8 version;
/* Reserved for HDCP and DP Spec. Read as Zero */
u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
} __packed;
/* Main structures for HDCP2.2 protocol communication */
struct hdcp2_ake_init {
u8 msg_id;
u8 r_tx[HDCP_2_2_RTX_LEN];
struct hdcp2_tx_caps tx_caps;
} __packed;
struct hdcp2_ake_send_cert {
u8 msg_id;
struct hdcp2_cert_rx cert_rx;
u8 r_rx[HDCP_2_2_RRX_LEN];
u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
} __packed;
struct hdcp2_ake_no_stored_km {
u8 msg_id;
u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
} __packed;
struct hdcp2_ake_stored_km {
u8 msg_id;
u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
} __packed;
struct hdcp2_ake_send_hprime {
u8 msg_id;
u8 h_prime[HDCP_2_2_H_PRIME_LEN];
} __packed;
struct hdcp2_ake_send_pairing_info {
u8 msg_id;
u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
} __packed;
struct hdcp2_lc_init {
u8 msg_id;
u8 r_n[HDCP_2_2_RN_LEN];
} __packed;
struct hdcp2_lc_send_lprime {
u8 msg_id;
u8 l_prime[HDCP_2_2_L_PRIME_LEN];
} __packed;
struct hdcp2_ske_send_eks {
u8 msg_id;
u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
u8 riv[HDCP_2_2_RIV_LEN];
} __packed;
struct hdcp2_rep_send_receiverid_list {
u8 msg_id;
u8 rx_info[HDCP_2_2_RXINFO_LEN];
u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
} __packed;
struct hdcp2_rep_send_ack {
u8 msg_id;
u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
} __packed;
struct hdcp2_rep_stream_manage {
u8 msg_id;
u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
__be16 k;
struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
} __packed;
struct hdcp2_rep_stream_ready {
u8 msg_id;
u8 m_prime[HDCP_2_2_MPRIME_LEN];
} __packed;
/* HDCP2.2 TIMEOUTs in mSec */
#define HDCP_2_2_CERT_TIMEOUT_MS 100
#define HDCP_2_2_DP_CERT_READ_TIMEOUT_MS 110
#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
#define HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS 7
#define HDCP_2_2_PAIRING_TIMEOUT_MS 200
#define HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS 5
#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 16
#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
/* HDMI HDCP2.2 Register Offsets */
#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
/* Below macros take a byte at a time and mask the bit(s) */
#define HDCP_2_2_HDMI_RXSTATUS_LEN 2
#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
/*
* Helper functions to convert 24bit big endian hdcp sequence number to
* host format and back
*/
static inline
u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])
{
return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);
}
static inline
void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
{
seq_num[0] = val >> 16;
seq_num[1] = val >> 8;
seq_num[2] = val;
}
#define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024)
#define DRM_HDCP_1_4_SRM_ID 0x8
#define DRM_HDCP_SRM_ID_MASK (0xF << 4)
#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
#define DRM_HDCP_2_SRM_ID 0x9
#define DRM_HDCP_2_INDICATOR 0x1
#define DRM_HDCP_2_INDICATOR_MASK 0xF
#define DRM_HDCP_2_VRL_LENGTH_SIZE 3
#define DRM_HDCP_2_DCP_SIG_SIZE 384
#define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4
#define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6)
struct hdcp_srm_header {
u8 srm_id;
u8 reserved;
__be16 srm_version;
u8 srm_gen_no;
} __packed;
/* Content Type classification for HDCP2.2 vs others */
#define DRM_MODE_HDCP_CONTENT_TYPE0 0
#define DRM_MODE_HDCP_CONTENT_TYPE1 1
#endif
linux-7.2.3/include/drm/display/drm_hdcp_helper.h
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/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2017 Google, Inc.
*
* Authors:
* Sean Paul <seanpaul@chromium.org>
*/
#ifndef _DRM_HDCP_HELPER_H_INCLUDED_
#define _DRM_HDCP_HELPER_H_INCLUDED_
#include <drm/display/drm_hdcp.h>
struct drm_device;
struct drm_connector;
int drm_hdcp_check_ksvs_revoked(struct drm_device *dev, u8 *ksvs, u32 ksv_count);
int drm_connector_attach_content_protection_property(struct drm_connector *connector,
bool hdcp_content_type);
void drm_hdcp_update_content_protection(struct drm_connector *connector, u64 val);
#endif
linux-7.2.3/include/drm/display/drm_hdmi_audio_helper.h
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/* SPDX-License-Identifier: MIT */
#ifndef DRM_DISPLAY_HDMI_AUDIO_HELPER_H_
#define DRM_DISPLAY_HDMI_AUDIO_HELPER_H_
#include <linux/types.h>
struct drm_connector;
struct drm_connector_hdmi_audio_funcs;
struct device;
int drm_connector_hdmi_audio_init(struct drm_connector *connector,
struct device *hdmi_codec_dev,
const struct drm_connector_hdmi_audio_funcs *funcs,
unsigned int max_i2s_playback_channels,
u64 i2s_formats,
bool spdif_playback,
int sound_dai_port);
void drm_connector_hdmi_audio_plugged_notify(struct drm_connector *connector,
bool plugged);
#endif
linux-7.2.3/include/drm/display/drm_hdmi_cec_helper.h
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/* SPDX-License-Identifier: MIT */
#ifndef DRM_DISPLAY_HDMI_CEC_HELPER
#define DRM_DISPLAY_HDMI_CEC_HELPER
#include <linux/types.h>
struct drm_connector;
struct cec_msg;
struct device;
struct drm_connector_hdmi_cec_funcs {
/**
* @init: perform hardware-specific initialization before registering the CEC adapter
*/
int (*init)(struct drm_connector *connector);
/**
* @uninit: perform hardware-specific teardown for the CEC adapter
*/
void (*uninit)(struct drm_connector *connector);
/**
* @enable: enable or disable CEC adapter
*/
int (*enable)(struct drm_connector *connector, bool enable);
/**
* @log_addr: set adapter's logical address, can be called multiple
* times if adapter supports several LAs
*/
int (*log_addr)(struct drm_connector *connector, u8 logical_addr);
/**
* @transmit: start transmission of the specified CEC message
*/
int (*transmit)(struct drm_connector *connector, u8 attempts,
u32 signal_free_time, struct cec_msg *msg);
};
int drmm_connector_hdmi_cec_register(struct drm_connector *connector,
const struct drm_connector_hdmi_cec_funcs *funcs,
const char *name,
u8 available_las,
struct device *dev);
void drm_connector_hdmi_cec_received_msg(struct drm_connector *connector,
struct cec_msg *msg);
void drm_connector_hdmi_cec_transmit_done(struct drm_connector *connector,
u8 status,
u8 arb_lost_cnt, u8 nack_cnt,
u8 low_drive_cnt, u8 error_cnt);
void drm_connector_hdmi_cec_transmit_attempt_done(struct drm_connector *connector,
u8 status);
#if IS_ENABLED(CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER)
int drmm_connector_hdmi_cec_notifier_register(struct drm_connector *connector,
const char *port_name,
struct device *dev);
#else
static inline int drmm_connector_hdmi_cec_notifier_register(struct drm_connector *connector,
const char *port_name,
struct device *dev)
{
return 0;
}
#endif
#endif
linux-7.2.3/include/drm/display/drm_hdmi_helper.h
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/* SPDX-License-Identifier: MIT */
#ifndef DRM_HDMI_HELPER
#define DRM_HDMI_HELPER
#include <linux/hdmi.h>
struct drm_connector;
struct drm_connector_state;
struct drm_display_mode;
enum drm_output_color_format;
void
drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
int
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
const struct drm_connector_state *conn_state);
void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
unsigned long long
drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode,
unsigned int bpc, enum drm_output_color_format fmt);
void
drm_hdmi_acr_get_n_cts(unsigned long long tmds_char_rate,
unsigned int sample_rate,
unsigned int *out_n,
unsigned int *out_cts);
#endif
linux-7.2.3/include/drm/display/drm_hdmi_state_helper.h
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/* SPDX-License-Identifier: MIT */
#ifndef DRM_HDMI_STATE_HELPER_H_
#define DRM_HDMI_STATE_HELPER_H_
struct drm_atomic_commit;
struct drm_connector;
struct drm_connector_state;
struct drm_display_mode;
struct hdmi_audio_infoframe;
enum drm_connector_status;
void __drm_atomic_helper_connector_hdmi_reset(struct drm_connector *connector,
struct drm_connector_state *new_conn_state);
int drm_atomic_helper_connector_hdmi_check(struct drm_connector *connector,
struct drm_atomic_commit *state);
int drm_atomic_helper_connector_hdmi_update_audio_infoframe(struct drm_connector *connector,
struct hdmi_audio_infoframe *frame);
int drm_atomic_helper_connector_hdmi_clear_audio_infoframe(struct drm_connector *connector);
int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *connector,
struct drm_atomic_commit *state);
void drm_atomic_helper_connector_hdmi_hotplug(struct drm_connector *connector,
enum drm_connector_status status);
void drm_atomic_helper_connector_hdmi_force(struct drm_connector *connector);
enum drm_mode_status
drm_hdmi_connector_mode_valid(struct drm_connector *connector,
const struct drm_display_mode *mode);
#endif // DRM_HDMI_STATE_HELPER_H_
linux-7.2.3/include/drm/display/drm_scdc.h
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/*
* Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DRM_SCDC_H
#define DRM_SCDC_H
#define SCDC_SINK_VERSION 0x01
#define SCDC_SOURCE_VERSION 0x02
#define SCDC_UPDATE_0 0x10
#define SCDC_READ_REQUEST_TEST (1 << 2)
#define SCDC_CED_UPDATE (1 << 1)
#define SCDC_STATUS_UPDATE (1 << 0)
#define SCDC_UPDATE_1 0x11
#define SCDC_TMDS_CONFIG 0x20
#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
#define SCDC_SCRAMBLING_ENABLE (1 << 0)
#define SCDC_SCRAMBLER_STATUS 0x21
#define SCDC_SCRAMBLING_STATUS (1 << 0)
#define SCDC_CONFIG_0 0x30
#define SCDC_READ_REQUEST_ENABLE (1 << 0)
#define SCDC_STATUS_FLAGS_0 0x40
#define SCDC_CH2_LOCK (1 << 3)
#define SCDC_CH1_LOCK (1 << 2)
#define SCDC_CH0_LOCK (1 << 1)
#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
#define SCDC_CLOCK_DETECT (1 << 0)
#define SCDC_STATUS_FLAGS_1 0x41
#define SCDC_ERR_DET_0_L 0x50
#define SCDC_ERR_DET_0_H 0x51
#define SCDC_ERR_DET_1_L 0x52
#define SCDC_ERR_DET_1_H 0x53
#define SCDC_ERR_DET_2_L 0x54
#define SCDC_ERR_DET_2_H 0x55
#define SCDC_CHANNEL_VALID (1 << 7)
#define SCDC_ERR_DET_CHECKSUM 0x56
#define SCDC_TEST_CONFIG_0 0xc0
#define SCDC_TEST_READ_REQUEST (1 << 7)
#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
#define SCDC_MANUFACTURER_IEEE_OUI 0xd0
#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
#define SCDC_DEVICE_ID 0xd3
#define SCDC_DEVICE_ID_SIZE 8
#define SCDC_DEVICE_HARDWARE_REVISION 0xdb
#define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
#define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
#define SCDC_MANUFACTURER_SPECIFIC 0xde
#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
#endif
linux-7.2.3/include/drm/display/drm_scdc_helper.h
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/*
* Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DRM_SCDC_HELPER_H
#define DRM_SCDC_HELPER_H
#include <linux/types.h>
#include <drm/display/drm_scdc.h>
struct drm_connector;
struct i2c_adapter;
ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
size_t size);
ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
const void *buffer, size_t size);
/**
* drm_scdc_readb - read a single byte from SCDC
* @adapter: I2C adapter
* @offset: offset of register to read
* @value: return location for the register value
*
* Reads a single byte from SCDC. This is a convenience wrapper around the
* drm_scdc_read() function.
*
* Returns:
* 0 on success or a negative error code on failure.
*/
static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
u8 *value)
{
return drm_scdc_read(adapter, offset, value, sizeof(*value));
}
/**
* drm_scdc_writeb - write a single byte to SCDC
* @adapter: I2C adapter
* @offset: offset of register to read
* @value: return location for the register value
*
* Writes a single byte to SCDC. This is a convenience wrapper around the
* drm_scdc_write() function.
*
* Returns:
* 0 on success or a negative error code on failure.
*/
static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
u8 value)
{
return drm_scdc_write(adapter, offset, &value, sizeof(value));
}
bool drm_scdc_get_scrambling_status(struct drm_connector *connector);
bool drm_scdc_set_scrambling(struct drm_connector *connector, bool enable);
bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector, bool set);
#endif