lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/include/drm/intel/display_member.h
+42
View File
@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation */
#ifndef __DRM_INTEL_DISPLAY_H__
#define __DRM_INTEL_DISPLAY_H__
#include <linux/build_bug.h>
#include <linux/stddef.h>
#include <linux/stringify.h>
#include <drm/drm_device.h>
struct intel_display;
/*
* A dummy device struct to define the relative offsets of drm and display
* members. With the members identically placed in struct drm_i915_private and
* struct xe_device, this allows figuring out the struct intel_display pointer
* without the definition of either driver specific structure.
*/
struct __intel_generic_device {
struct drm_device drm;
struct intel_display *display;
};
/**
* INTEL_DISPLAY_MEMBER_STATIC_ASSERT() - ensure correct placing of drm and display members
* @type: The struct to check
* @drm_member: Name of the struct drm_device member
* @display_member: Name of the struct intel_display * member.
*
* Use this static assert macro to ensure the struct drm_i915_private and struct
* xe_device struct drm_device and struct intel_display * members are at the
* same relative offsets.
*/
#define INTEL_DISPLAY_MEMBER_STATIC_ASSERT(type, drm_member, display_member) \
static_assert( \
offsetof(struct __intel_generic_device, display) - offsetof(struct __intel_generic_device, drm) == \
offsetof(type, display_member) - offsetof(type, drm_member), \
__stringify(type) " " __stringify(drm_member) " and " __stringify(display_member) " members at invalid offsets")
#endif
linux-7.2.3/include/drm/intel/display_parent_interface.h
+308
View File
@@ -0,0 +1,308 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation x*/
#ifndef __DISPLAY_PARENT_INTERFACE_H__
#define __DISPLAY_PARENT_INTERFACE_H__
#include <linux/types.h>
enum vlv_iosf_sb_unit;
struct dma_fence;
struct drm_device;
struct drm_file;
struct drm_framebuffer;
struct drm_gem_object;
struct drm_mode_fb_cmd2;
struct drm_plane_state;
struct drm_scanout_buffer;
struct fb_info;
struct i915_gtt_view;
struct i915_vma;
struct intel_dpt;
struct intel_dsb_buffer;
struct intel_frontbuffer;
struct intel_hdcp_gsc_context;
struct intel_initial_plane_config;
struct intel_panic;
struct intel_stolen_node;
struct iosys_map;
struct ref_tracker;
struct seq_file;
struct vm_area_struct;
struct intel_fb_pin_params {
const struct i915_gtt_view *view;
unsigned int alignment;
unsigned int phys_alignment;
unsigned int vtd_guard;
bool needs_cpu_lmem_access;
bool needs_low_address;
bool needs_physical;
bool needs_fence;
};
/* Keep struct definitions sorted */
struct intel_display_bo_interface {
bool (*is_tiled)(struct drm_gem_object *obj); /* Optional */
bool (*is_userptr)(struct drm_gem_object *obj); /* Optional */
bool (*is_shmem)(struct drm_gem_object *obj); /* Optional */
bool (*is_protected)(struct drm_gem_object *obj);
int (*key_check)(struct drm_gem_object *obj);
int (*fb_mmap)(struct drm_gem_object *obj, struct vm_area_struct *vma);
int (*read_from_page)(struct drm_gem_object *obj, u64 offset, void *dst, int size);
void (*describe)(struct seq_file *m, struct drm_gem_object *obj); /* Optional */
int (*framebuffer_init)(struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd);
void (*framebuffer_fini)(struct drm_gem_object *obj);
struct drm_gem_object *(*framebuffer_lookup)(struct drm_device *drm,
struct drm_file *filp,
const struct drm_mode_fb_cmd2 *user_mode_cmd);
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
struct drm_gem_object *(*fbdev_create)(struct drm_device *drm, int size);
void (*fbdev_destroy)(struct drm_gem_object *obj);
int (*fbdev_fill_info)(struct drm_gem_object *obj, struct fb_info *info, struct i915_vma *vma);
u32 (*fbdev_pitch_align)(u32 stride);
#endif
};
struct intel_display_dpt_interface {
struct intel_dpt *(*create)(struct drm_gem_object *obj, size_t size);
void (*destroy)(struct intel_dpt *dpt);
void (*suspend)(struct intel_dpt *dpt);
void (*resume)(struct intel_dpt *dpt);
};
struct intel_display_dsb_interface {
u32 (*ggtt_offset)(struct intel_dsb_buffer *dsb_buf);
void (*write)(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val);
u32 (*read)(struct intel_dsb_buffer *dsb_buf, u32 idx);
void (*fill)(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size);
struct intel_dsb_buffer *(*create)(struct drm_device *drm, size_t size);
void (*cleanup)(struct intel_dsb_buffer *dsb_buf);
void (*flush_map)(struct intel_dsb_buffer *dsb_buf);
};
struct intel_display_fb_pin_interface {
int (*ggtt_pin)(struct drm_gem_object *obj,
const struct intel_fb_pin_params *pin_params,
struct i915_vma **out_ggtt_vma,
u32 *out_offset,
int *out_fence_id);
void (*ggtt_unpin)(struct i915_vma *ggtt_vma,
int fence_id);
int (*dpt_pin)(struct drm_gem_object *obj,
struct intel_dpt *dpt,
const struct intel_fb_pin_params *pin_params,
struct i915_vma **out_dpt_vma,
struct i915_vma **out_ggtt_vma,
u32 *out_offset);
void (*dpt_unpin)(struct intel_dpt *dpt,
struct i915_vma *dpt_vma,
struct i915_vma *ggtt_vma);
struct i915_vma *(*reuse_vma)(struct i915_vma *old_ggtt_vma,
struct drm_gem_object *old_obj,
const struct i915_gtt_view *old_view,
struct drm_gem_object *new_obj,
const struct i915_gtt_view *new_view,
u32 *out_offset);
void (*get_map)(struct i915_vma *vma, struct iosys_map *map);
};
struct intel_display_frontbuffer_interface {
struct intel_frontbuffer *(*get)(struct drm_gem_object *obj);
void (*ref)(struct intel_frontbuffer *front);
void (*put)(struct intel_frontbuffer *front);
void (*flush_for_display)(struct intel_frontbuffer *front);
};
struct intel_display_hdcp_interface {
ssize_t (*gsc_msg_send)(struct intel_hdcp_gsc_context *gsc_context,
void *msg_in, size_t msg_in_len,
void *msg_out, size_t msg_out_len);
bool (*gsc_check_status)(struct drm_device *drm);
struct intel_hdcp_gsc_context *(*gsc_context_alloc)(struct drm_device *drm);
void (*gsc_context_free)(struct intel_hdcp_gsc_context *gsc_context);
};
struct intel_display_initial_plane_interface {
struct drm_gem_object *(*alloc_obj)(struct drm_device *drm, struct intel_initial_plane_config *plane_config);
int (*setup)(struct drm_plane_state *plane_state, struct intel_initial_plane_config *plane_config,
struct drm_framebuffer *fb, struct i915_vma *vma);
void (*config_fini)(struct intel_initial_plane_config *plane_config);
};
struct intel_display_irq_interface {
bool (*enabled)(struct drm_device *drm);
void (*synchronize)(struct drm_device *drm);
};
struct intel_display_overlay_interface {
bool (*is_active)(struct drm_device *drm);
int (*overlay_on)(struct drm_device *drm,
u32 frontbuffer_bits);
int (*overlay_continue)(struct drm_device *drm,
struct i915_vma *vma,
bool load_polyphase_filter);
int (*overlay_off)(struct drm_device *drm);
int (*recover_from_interrupt)(struct drm_device *drm);
int (*release_old_vid)(struct drm_device *drm);
void (*reset)(struct drm_device *drm);
struct i915_vma *(*pin_fb)(struct drm_device *drm,
struct drm_gem_object *obj,
u32 *offset);
void (*unpin_fb)(struct drm_device *drm,
struct i915_vma *vma);
struct drm_gem_object *(*obj_lookup)(struct drm_device *drm,
struct drm_file *filp,
u32 handle);
void __iomem *(*setup)(struct drm_device *drm,
bool needs_physical);
void (*cleanup)(struct drm_device *drm);
};
struct intel_display_panic_interface {
struct intel_panic *(*alloc)(void);
int (*setup)(struct intel_panic *panic, struct drm_scanout_buffer *sb);
void (*finish)(struct intel_panic *panic);
};
struct intel_display_pc8_interface {
void (*block)(struct drm_device *drm);
void (*unblock)(struct drm_device *drm);
};
struct intel_display_pcode_interface {
int (*read)(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
int (*write)(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
int (*request)(struct drm_device *drm, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
};
struct intel_display_rpm_interface {
struct ref_tracker *(*get)(const struct drm_device *drm);
struct ref_tracker *(*get_raw)(const struct drm_device *drm);
struct ref_tracker *(*get_if_in_use)(const struct drm_device *drm);
struct ref_tracker *(*get_noresume)(const struct drm_device *drm);
void (*put)(const struct drm_device *drm, struct ref_tracker *wakeref);
void (*put_raw)(const struct drm_device *drm, struct ref_tracker *wakeref);
void (*put_unchecked)(const struct drm_device *drm);
bool (*suspended)(const struct drm_device *drm);
void (*assert_held)(const struct drm_device *drm);
void (*assert_block)(const struct drm_device *drm);
void (*assert_unblock)(const struct drm_device *drm);
};
struct intel_display_rps_interface {
void (*boost_if_not_started)(struct dma_fence *fence);
void (*mark_interactive)(struct drm_device *drm, bool interactive);
void (*ilk_irq_handler)(struct drm_device *drm);
};
struct intel_display_stolen_interface {
int (*insert_node_in_range)(struct intel_stolen_node *node, u64 size,
unsigned int align, u64 start, u64 end);
int (*insert_node)(struct intel_stolen_node *node, u64 size, unsigned int align); /* Optional */
void (*remove_node)(struct intel_stolen_node *node);
bool (*initialized)(struct drm_device *drm);
bool (*node_allocated)(const struct intel_stolen_node *node);
u64 (*node_offset)(const struct intel_stolen_node *node);
u64 (*area_address)(struct drm_device *drm); /* Optional */
u64 (*area_size)(struct drm_device *drm); /* Optional */
u64 (*node_address)(const struct intel_stolen_node *node);
u64 (*node_size)(const struct intel_stolen_node *node);
struct intel_stolen_node *(*node_alloc)(struct drm_device *drm);
void (*node_free)(const struct intel_stolen_node *node);
};
struct intel_display_vlv_iosf_interface {
void (*get)(struct drm_device *drm, unsigned long unit_mask);
void (*put)(struct drm_device *drm, unsigned long unit_mask);
u32 (*read)(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr);
int (*write)(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val);
};
/**
* struct intel_display_parent_interface - services parent driver provides to display
*
* The parent, or core, driver provides a pointer to this structure to display
* driver when calling intel_display_device_probe(). The display driver uses it
* to access services provided by the parent driver. The structure may contain
* sub-struct pointers to group function pointers by functionality.
*
* All function and sub-struct pointers must be initialized and callable unless
* explicitly marked as "optional" below. The display driver will only NULL
* check the optional pointers.
*/
struct intel_display_parent_interface {
/** @bo: BO interface */
const struct intel_display_bo_interface *bo;
/** @dpt: DPT interface. Optional. */
const struct intel_display_dpt_interface *dpt;
/** @dsb: DSB buffer interface */
const struct intel_display_dsb_interface *dsb;
/** @fb_pin: Framebuffer pin interface */
const struct intel_display_fb_pin_interface *fb_pin;
/** @frontbuffer: Frontbuffer interface */
const struct intel_display_frontbuffer_interface *frontbuffer;
/** @hdcp: HDCP GSC interface */
const struct intel_display_hdcp_interface *hdcp;
/** @initial_plane: Initial plane interface */
const struct intel_display_initial_plane_interface *initial_plane;
/** @irq: IRQ interface */
const struct intel_display_irq_interface *irq;
/** @panic: Panic interface */
const struct intel_display_panic_interface *panic;
/** @overlay: Overlay. Optional. */
const struct intel_display_overlay_interface *overlay;
/** @pc8: PC8 interface. Optional. */
const struct intel_display_pc8_interface *pc8;
/** @pcode: Pcode interface */
const struct intel_display_pcode_interface *pcode;
/** @rpm: Runtime PM functions */
const struct intel_display_rpm_interface *rpm;
/** @rps: RPS interface. Optional. */
const struct intel_display_rps_interface *rps;
/** @stolen: Stolen memory. */
const struct intel_display_stolen_interface *stolen;
/** @vlv_iosf: VLV IOSF sideband. Optional. */
const struct intel_display_vlv_iosf_interface *vlv_iosf;
/* Generic independent functions */
struct {
/** @fence_priority_display: Set display priority. Optional. */
void (*fence_priority_display)(struct dma_fence *fence);
/** @has_auxccs: Are AuxCCS formats supported by the parent. Optional. */
bool (*has_auxccs)(struct drm_device *drm);
/** @has_fenced_regions: Support legacy fencing? Optional. */
bool (*has_fenced_regions)(struct drm_device *drm);
/** @vgpu_active: Is vGPU active? Optional. */
bool (*vgpu_active)(struct drm_device *drm);
};
};
#endif
linux-7.2.3/include/drm/intel/i915_component.h
+57
View File
@@ -0,0 +1,57 @@
/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _I915_COMPONENT_H_
#define _I915_COMPONENT_H_
#include <drm/drm_audio_component.h>
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
I915_COMPONENT_PXP,
I915_COMPONENT_GSC_PROXY,
INTEL_COMPONENT_LB,
};
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
#define MAX_PORTS 9
/**
* struct i915_audio_component - Used for direct communication between i915 and hda drivers
*/
struct i915_audio_component {
/**
* @base: the drm_audio_component base class
*/
struct drm_audio_component base;
/**
* @aud_sample_rate: the array of audio sample rate per port
*/
int aud_sample_rate[MAX_PORTS];
};
#endif /* _I915_COMPONENT_H_ */
linux-7.2.3/include/drm/intel/i915_drm.h
+102
View File
@@ -0,0 +1,102 @@
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _I915_DRM_H_
#define _I915_DRM_H_
#include <linux/types.h>
/* For use by IPS driver */
unsigned long i915_read_mch_val(void);
bool i915_gpu_raise(void);
bool i915_gpu_lower(void);
bool i915_gpu_busy(void);
bool i915_gpu_turbo_disable(void);
/* Exported from arch/x86/kernel/early-quirks.c */
extern struct resource intel_graphics_stolen_res;
/*
* The bridge device's (device 0) PCI config space has information
* about the fb aperture size and the amount of pre-reserved memory.
*/
/* device 2 has a read-only mirror */
#define SNB_GMCH_CTRL 0x50
#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
#define SNB_GMCH_GGMS_MASK 0x3
#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
#define SNB_GMCH_GMS_MASK 0x1f
#define BDW_GMCH_GGMS_SHIFT 6
#define BDW_GMCH_GGMS_MASK 0x3
#define BDW_GMCH_GMS_SHIFT 8
#define BDW_GMCH_GMS_MASK 0xff
/* device 2 has a read-only mirror from i85x/i865 onwards */
#define I830_GMCH_CTRL 0x52
#define I830_GMCH_GMS_MASK (0x7 << 4)
#define I830_GMCH_GMS_LOCAL (0x1 << 4)
#define I830_GMCH_GMS_STOLEN_512 (0x2 << 4)
#define I830_GMCH_GMS_STOLEN_1024 (0x3 << 4)
#define I830_GMCH_GMS_STOLEN_8192 (0x4 << 4)
#define I855_GMCH_GMS_MASK (0xF << 4)
#define I855_GMCH_GMS_STOLEN_0M (0x0 << 4)
#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
/* valid for both I830_GMCH_CTRL and SNB_GMCH_CTRL */
#define INTEL_GMCH_VGA_DISABLE (1 << 1)
#define I830_DRB3 0x63
#define I85X_DRB3 0x43
#define I865_TOUD 0xc4
#define I830_ESMRAMC 0x91
#define I845_ESMRAMC 0x9e
#define I85X_ESMRAMC 0x61
#define TSEG_ENABLE (1 << 0)
#define I830_TSEG_SIZE_512K (0 << 1)
#define I830_TSEG_SIZE_1M (1 << 1)
#define I845_TSEG_SIZE_MASK (3 << 1)
#define I845_TSEG_SIZE_512K (2 << 1)
#define I845_TSEG_SIZE_1M (3 << 1)
#define INTEL_BSM 0x5c
#define INTEL_GEN11_BSM_DW0 0xc0
#define INTEL_GEN11_BSM_DW1 0xc4
#define INTEL_BSM_MASK (-(1u << 20))
#endif /* _I915_DRM_H_ */
linux-7.2.3/include/drm/intel/i915_gsc_proxy_mei_interface.h
+53
View File
@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2022-2023 Intel Corporation
*/
#ifndef _I915_GSC_PROXY_MEI_INTERFACE_H_
#define _I915_GSC_PROXY_MEI_INTERFACE_H_
#include <linux/types.h>
struct device;
struct module;
/**
* struct i915_gsc_proxy_component_ops - ops for GSC Proxy services.
* @owner: Module providing the ops
* @send: sends a proxy message from GSC FW to ME FW
* @recv: receives a proxy message for GSC FW from ME FW
*/
struct i915_gsc_proxy_component_ops {
struct module *owner;
/**
* @send: Sends a proxy message to ME FW.
* @dev: device struct corresponding to the mei device
* @buf: message buffer to send
* @size: size of the message
* Return: bytes sent on success, negative errno value on failure
*/
int (*send)(struct device *dev, const void *buf, size_t size);
/**
* @recv: Receives a proxy message from ME FW.
* @dev: device struct corresponding to the mei device
* @buf: message buffer to contain the received message
* @size: size of the buffer
* Return: bytes received on success, negative errno value on failure
*/
int (*recv)(struct device *dev, void *buf, size_t size);
};
/**
* struct i915_gsc_proxy_component - Used for communication between i915 and
* MEI drivers for GSC proxy services
* @mei_dev: device that provide the GSC proxy service.
* @ops: Ops implemented by GSC proxy driver, used by i915 driver.
*/
struct i915_gsc_proxy_component {
struct device *mei_dev;
const struct i915_gsc_proxy_component_ops *ops;
};
#endif /* _I915_GSC_PROXY_MEI_INTERFACE_H_ */
linux-7.2.3/include/drm/intel/i915_hdcp_interface.h
+547
View File
@@ -0,0 +1,547 @@
/* SPDX-License-Identifier: (GPL-2.0+) */
/*
* Copyright © 2017-2019 Intel Corporation
*
* Authors:
* Ramalingam C <ramalingam.c@intel.com>
*/
#ifndef _I915_HDCP_INTERFACE_H_
#define _I915_HDCP_INTERFACE_H_
#include <linux/mutex.h>
#include <linux/device.h>
#include <drm/display/drm_hdcp.h>
/**
* enum hdcp_port_type - HDCP port implementation type defined by ME/GSC FW
* @HDCP_PORT_TYPE_INVALID: Invalid hdcp port type
* @HDCP_PORT_TYPE_INTEGRATED: In-Host HDCP2.x port
* @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON
* (HDMI 2.0) solution
* @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3)
* solution
*/
enum hdcp_port_type {
HDCP_PORT_TYPE_INVALID,
HDCP_PORT_TYPE_INTEGRATED,
HDCP_PORT_TYPE_LSPCON,
HDCP_PORT_TYPE_CPDP
};
/**
* enum hdcp_wired_protocol - HDCP adaptation used on the port
* @HDCP_PROTOCOL_INVALID: Invalid HDCP adaptation protocol
* @HDCP_PROTOCOL_HDMI: HDMI adaptation of HDCP used on the port
* @HDCP_PROTOCOL_DP: DP adaptation of HDCP used on the port
*/
enum hdcp_wired_protocol {
HDCP_PROTOCOL_INVALID,
HDCP_PROTOCOL_HDMI,
HDCP_PROTOCOL_DP
};
enum hdcp_ddi {
HDCP_DDI_INVALID_PORT = 0x0,
HDCP_DDI_B = 1,
HDCP_DDI_C,
HDCP_DDI_D,
HDCP_DDI_E,
HDCP_DDI_F,
HDCP_DDI_A = 7,
HDCP_DDI_RANGE_END = HDCP_DDI_A,
};
/**
* enum hdcp_transcoder - ME/GSC Firmware defined index for transcoders
* @HDCP_INVALID_TRANSCODER: Index for Invalid transcoder
* @HDCP_TRANSCODER_EDP: Index for EDP Transcoder
* @HDCP_TRANSCODER_DSI0: Index for DSI0 Transcoder
* @HDCP_TRANSCODER_DSI1: Index for DSI1 Transcoder
* @HDCP_TRANSCODER_A: Index for Transcoder A
* @HDCP_TRANSCODER_B: Index for Transcoder B
* @HDCP_TRANSCODER_C: Index for Transcoder C
* @HDCP_TRANSCODER_D: Index for Transcoder D
*/
enum hdcp_transcoder {
HDCP_INVALID_TRANSCODER = 0x00,
HDCP_TRANSCODER_EDP,
HDCP_TRANSCODER_DSI0,
HDCP_TRANSCODER_DSI1,
HDCP_TRANSCODER_A = 0x10,
HDCP_TRANSCODER_B,
HDCP_TRANSCODER_C,
HDCP_TRANSCODER_D
};
/**
* struct hdcp_port_data - intel specific HDCP port data
* @hdcp_ddi: ddi index as per ME/GSC FW
* @hdcp_transcoder: transcoder index as per ME/GSC FW
* @port_type: HDCP port type as per ME/GSC FW classification
* @protocol: HDCP adaptation as per ME/GSC FW
* @k: No of streams transmitted on a port. Only on DP MST this is != 1
* @seq_num_m: Count of RepeaterAuth_Stream_Manage msg propagated.
* Initialized to 0 on AKE_INIT. Incremented after every successful
* transmission of RepeaterAuth_Stream_Manage message. When it rolls
* over re-Auth has to be triggered.
* @streams: struct hdcp2_streamid_type[k]. Defines the type and id for the
* streams
*/
struct hdcp_port_data {
enum hdcp_ddi hdcp_ddi;
enum hdcp_transcoder hdcp_transcoder;
u8 port_type;
u8 protocol;
u16 k;
u32 seq_num_m;
struct hdcp2_streamid_type *streams;
};
/**
* struct i915_hdcp_ops- ops for HDCP2.2 services.
* @owner: Module providing the ops
* @initiate_hdcp2_session: Initiate a Wired HDCP2.2 Tx Session.
* And Prepare AKE_Init.
* @verify_receiver_cert_prepare_km: Verify the Receiver Certificate
* AKE_Send_Cert and prepare
* AKE_Stored_Km/AKE_No_Stored_Km
* @verify_hprime: Verify AKE_Send_H_prime
* @store_pairing_info: Store pairing info received
* @initiate_locality_check: Prepare LC_Init
* @verify_lprime: Verify lprime
* @get_session_key: Prepare SKE_Send_Eks
* @repeater_check_flow_prepare_ack: Validate the Downstream topology
* and prepare rep_ack
* @verify_mprime: Verify mprime
* @enable_hdcp_authentication: Mark a port as authenticated.
* @close_hdcp_session: Close the Wired HDCP Tx session per port.
* This also disables the authenticated state of the port.
*/
struct i915_hdcp_ops {
/**
* @owner: hdcp module
*/
struct module *owner;
int (*initiate_hdcp2_session)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_init *ake_data);
int (*verify_receiver_cert_prepare_km)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_cert
*rx_cert,
bool *km_stored,
struct hdcp2_ake_no_stored_km
*ek_pub_km,
size_t *msg_sz);
int (*verify_hprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_hprime *rx_hprime);
int (*store_pairing_info)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ake_send_pairing_info
*pairing_info);
int (*initiate_locality_check)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_init *lc_init_data);
int (*verify_lprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_send_lprime *rx_lprime);
int (*get_session_key)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ske_send_eks *ske_data);
int (*repeater_check_flow_prepare_ack)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_rep_send_receiverid_list
*rep_topology,
struct hdcp2_rep_send_ack
*rep_send_ack);
int (*verify_mprime)(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_rep_stream_ready *stream_ready);
int (*enable_hdcp_authentication)(struct device *dev,
struct hdcp_port_data *data);
int (*close_hdcp_session)(struct device *dev,
struct hdcp_port_data *data);
};
/**
* struct i915_hdcp_arbiter - Used for communication between i915
* and hdcp drivers for the HDCP2.2 services
*/
struct i915_hdcp_arbiter {
/**
* @hdcp_dev: device that provides the HDCP2.2 service from MEI Bus.
*/
struct device *hdcp_dev;
/**
* @ops: Ops implemented by hdcp driver or intel_hdcp_gsc, used by i915
* driver.
*/
const struct i915_hdcp_ops *ops;
/**
* @mutex: To protect the above members.
*/
struct mutex mutex;
};
/* fw_hdcp_status: Enumeration of all HDCP Status Codes */
enum fw_hdcp_status {
FW_HDCP_STATUS_SUCCESS = 0x0000,
/* WiDi Generic Status Codes */
FW_HDCP_STATUS_INTERNAL_ERROR = 0x1000,
FW_HDCP_STATUS_UNKNOWN_ERROR = 0x1001,
FW_HDCP_STATUS_INCORRECT_API_VERSION = 0x1002,
FW_HDCP_STATUS_INVALID_FUNCTION = 0x1003,
FW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 0x1004,
FW_HDCP_STATUS_INVALID_PARAMS = 0x1005,
FW_HDCP_STATUS_AUTHENTICATION_FAILED = 0x1006,
/* WiDi Status Codes */
FW_HDCP_INVALID_SESSION_STATE = 0x6000,
FW_HDCP_SRM_FRAGMENT_UNEXPECTED = 0x6001,
FW_HDCP_SRM_INVALID_LENGTH = 0x6002,
FW_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 0x6003,
FW_HDCP_SRM_VERIFICATION_FAILED = 0x6004,
FW_HDCP_SRM_VERSION_TOO_OLD = 0x6005,
FW_HDCP_RX_CERT_VERIFICATION_FAILED = 0x6006,
FW_HDCP_RX_REVOKED = 0x6007,
FW_HDCP_H_VERIFICATION_FAILED = 0x6008,
FW_HDCP_REPEATER_CHECK_UNEXPECTED = 0x6009,
FW_HDCP_TOPOLOGY_MAX_EXCEEDED = 0x600A,
FW_HDCP_V_VERIFICATION_FAILED = 0x600B,
FW_HDCP_L_VERIFICATION_FAILED = 0x600C,
FW_HDCP_STREAM_KEY_ALLOC_FAILED = 0x600D,
FW_HDCP_BASE_KEY_RESET_FAILED = 0x600E,
FW_HDCP_NONCE_GENERATION_FAILED = 0x600F,
FW_HDCP_STATUS_INVALID_E_KEY_STATE = 0x6010,
FW_HDCP_STATUS_INVALID_CS_ICV = 0x6011,
FW_HDCP_STATUS_INVALID_KB_KEY_STATE = 0x6012,
FW_HDCP_STATUS_INVALID_PAVP_MODE_ICV = 0x6013,
FW_HDCP_STATUS_INVALID_PAVP_MODE = 0x6014,
FW_HDCP_STATUS_LC_MAX_ATTEMPTS = 0x6015,
/* New status for HDCP 2.1 */
FW_HDCP_STATUS_MISMATCH_IN_M = 0x6016,
/* New status code for HDCP 2.2 Rx */
FW_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 0x6017,
FW_HDCP_STATUS_RX_PROV_WRONG_SUBJECT = 0x6018,
FW_HDCP_RX_NEEDS_PROVISIONING = 0x6019,
FW_HDCP_BKSV_ICV_AUTH_FAILED = 0x6020,
FW_HDCP_STATUS_INVALID_STREAM_ID = 0x6021,
FW_HDCP_STATUS_CHAIN_NOT_INITIALIZED = 0x6022,
FW_HDCP_FAIL_NOT_EXPECTED = 0x6023,
FW_HDCP_FAIL_HDCP_OFF = 0x6024,
FW_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 0x6025,
FW_HDCP_FAIL_AES_ECB_FAILURE = 0x6026,
FW_HDCP_FEATURE_NOT_SUPPORTED = 0x6027,
FW_HDCP_DMA_READ_ERROR = 0x6028,
FW_HDCP_DMA_WRITE_ERROR = 0x6029,
FW_HDCP_FAIL_INVALID_PACKET_SIZE = 0x6030,
FW_HDCP_H264_PARSING_ERROR = 0x6031,
FW_HDCP_HDCP2_ERRATA_VIDEO_VIOLATION = 0x6032,
FW_HDCP_HDCP2_ERRATA_AUDIO_VIOLATION = 0x6033,
FW_HDCP_TX_ACTIVE_ERROR = 0x6034,
FW_HDCP_MODE_CHANGE_ERROR = 0x6035,
FW_HDCP_STREAM_TYPE_ERROR = 0x6036,
FW_HDCP_STREAM_MANAGE_NOT_POSSIBLE = 0x6037,
FW_HDCP_STATUS_PORT_INVALID_COMMAND = 0x6038,
FW_HDCP_STATUS_UNSUPPORTED_PROTOCOL = 0x6039,
FW_HDCP_STATUS_INVALID_PORT_INDEX = 0x603a,
FW_HDCP_STATUS_TX_AUTH_NEEDED = 0x603b,
FW_HDCP_STATUS_NOT_INTEGRATED_PORT = 0x603c,
FW_HDCP_STATUS_SESSION_MAX_REACHED = 0x603d,
/* hdcp capable bit is not set in rx_caps(error is unique to DP) */
FW_HDCP_STATUS_NOT_HDCP_CAPABLE = 0x6041,
FW_HDCP_STATUS_INVALID_STREAM_COUNT = 0x6042,
};
#define HDCP_API_VERSION 0x00010000
#define HDCP_M_LEN 16
#define HDCP_KH_LEN 16
/* Payload Buffer size(Excluding Header) for CMDs and corresponding response */
/* Wired_Tx_AKE */
#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN (4 + 1)
#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_OUT (4 + 8 + 3)
#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN (4 + 522 + 8 + 3)
#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MIN_OUT (4 + 1 + 3 + 16 + 16)
#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MAX_OUT (4 + 1 + 3 + 128)
#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN (4 + 32)
#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_OUT (4)
#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN (4 + 16)
#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_OUT (4)
#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN (4)
#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_OUT (4)
/* Wired_Tx_LC */
#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN (4)
#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_OUT (4 + 8)
#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN (4 + 32)
#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_OUT (4)
/* Wired_Tx_SKE */
#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN (4)
#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_OUT (4 + 16 + 8)
/* Wired_Tx_SKE */
#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN (4 + 1)
#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_OUT (4)
/* Wired_Tx_Repeater */
#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN (4 + 2 + 3 + 16 + 155)
#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_OUT (4 + 1 + 16)
#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN (4 + 3 + \
32 + 2 + 2)
#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_OUT (4)
/* hdcp_command_id: Enumeration of all WIRED HDCP Command IDs */
enum hdcp_command_id {
_WIDI_COMMAND_BASE = 0x00030000,
WIDI_INITIATE_HDCP2_SESSION = _WIDI_COMMAND_BASE,
HDCP_GET_SRM_STATUS,
HDCP_SEND_SRM_FRAGMENT,
/* The wired HDCP Tx commands */
_WIRED_COMMAND_BASE = 0x00031000,
WIRED_INITIATE_HDCP2_SESSION = _WIRED_COMMAND_BASE,
WIRED_VERIFY_RECEIVER_CERT,
WIRED_AKE_SEND_HPRIME,
WIRED_AKE_SEND_PAIRING_INFO,
WIRED_INIT_LOCALITY_CHECK,
WIRED_VALIDATE_LOCALITY,
WIRED_GET_SESSION_KEY,
WIRED_ENABLE_AUTH,
WIRED_VERIFY_REPEATER,
WIRED_REPEATER_AUTH_STREAM_REQ,
WIRED_CLOSE_SESSION,
_WIRED_COMMANDS_COUNT,
};
union encrypted_buff {
u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
struct {
u8 e_kh_km[HDCP_KH_LEN];
u8 m[HDCP_M_LEN];
} __packed;
};
/* HDCP HECI message header. All header values are little endian. */
struct hdcp_cmd_header {
u32 api_version;
u32 command_id;
enum fw_hdcp_status status;
/* Length of the HECI message (excluding the header) */
u32 buffer_len;
} __packed;
/* Empty command request or response. No data follows the header. */
struct hdcp_cmd_no_data {
struct hdcp_cmd_header header;
} __packed;
/* Uniquely identifies the hdcp port being addressed for a given command. */
struct hdcp_port_id {
u8 integrated_port_type;
/* physical_port is used until Gen11.5. Must be zero for Gen11.5+ */
u8 physical_port;
/* attached_transcoder is for Gen11.5+. Set to zero for <Gen11.5 */
u8 attached_transcoder;
u8 reserved;
} __packed;
/*
* Data structures for integrated wired HDCP2 Tx in
* support of the AKE protocol
*/
/* HECI struct for integrated wired HDCP Tx session initiation. */
struct wired_cmd_initiate_hdcp2_session_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 protocol; /* for HDMI vs DP */
} __packed;
struct wired_cmd_initiate_hdcp2_session_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 r_tx[HDCP_2_2_RTX_LEN];
struct hdcp2_tx_caps tx_caps;
} __packed;
/* HECI struct for ending an integrated wired HDCP Tx session. */
struct wired_cmd_close_session_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
struct wired_cmd_close_session_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/* HECI struct for integrated wired HDCP Tx Rx Cert verification. */
struct wired_cmd_verify_receiver_cert_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
struct hdcp2_cert_rx cert_rx;
u8 r_rx[HDCP_2_2_RRX_LEN];
u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
} __packed;
struct wired_cmd_verify_receiver_cert_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 km_stored;
u8 reserved[3];
union encrypted_buff ekm_buff;
} __packed;
/* HECI struct for verification of Rx's Hprime in a HDCP Tx session */
struct wired_cmd_ake_send_hprime_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 h_prime[HDCP_2_2_H_PRIME_LEN];
} __packed;
struct wired_cmd_ake_send_hprime_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/*
* HECI struct for sending in AKE pairing data generated by the Rx in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_ake_send_pairing_info_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
} __packed;
struct wired_cmd_ake_send_pairing_info_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/* Data structures for integrated wired HDCP2 Tx in support of the LC protocol*/
/*
* HECI struct for initiating locality check with an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_init_locality_check_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
struct wired_cmd_init_locality_check_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 r_n[HDCP_2_2_RN_LEN];
} __packed;
/*
* HECI struct for validating an Rx's LPrime value in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_validate_locality_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 l_prime[HDCP_2_2_L_PRIME_LEN];
} __packed;
struct wired_cmd_validate_locality_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/*
* Data structures for integrated wired HDCP2 Tx in support of the
* SKE protocol
*/
/* HECI struct for creating session key */
struct wired_cmd_get_session_key_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
struct wired_cmd_get_session_key_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
u8 r_iv[HDCP_2_2_RIV_LEN];
} __packed;
/* HECI struct for the Tx enable authentication command */
struct wired_cmd_enable_auth_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 stream_type;
} __packed;
struct wired_cmd_enable_auth_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
/*
* Data structures for integrated wired HDCP2 Tx in support of
* the repeater protocols
*/
/*
* HECI struct for verifying the downstream repeater's HDCP topology in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_verify_repeater_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 rx_info[HDCP_2_2_RXINFO_LEN];
u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
} __packed;
struct wired_cmd_verify_repeater_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 content_type_supported;
u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
} __packed;
/*
* HECI struct in support of stream management in an
* integrated wired HDCP Tx session.
*/
struct wired_cmd_repeater_auth_stream_req_in {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
u8 m_prime[HDCP_2_2_MPRIME_LEN];
__be16 k;
struct hdcp2_streamid_type streams[];
} __packed;
struct wired_cmd_repeater_auth_stream_req_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
#endif /* _I915_HDCP_INTERFACE_H_ */
linux-7.2.3/include/drm/intel/i915_pxp_tee_interface.h
+62
View File
@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2020 Intel Corporation
*/
#ifndef _I915_PXP_TEE_INTERFACE_H_
#define _I915_PXP_TEE_INTERFACE_H_
#include <linux/mutex.h>
#include <linux/device.h>
struct scatterlist;
/**
* struct i915_pxp_component_ops - ops for PXP services.
*/
struct i915_pxp_component_ops {
/**
* @owner: Module providing the ops.
*/
struct module *owner;
/**
* @send: Send a PXP message.
*/
int (*send)(struct device *dev, const void *message, size_t size,
unsigned long timeout_ms);
/**
* @recv: Receive a PXP message.
*/
int (*recv)(struct device *dev, void *buffer, size_t size,
unsigned long timeout_ms);
/**
* @gsc_command: Send a GSC command.
*/
ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,
struct scatterlist *sg_in, size_t total_in_len,
struct scatterlist *sg_out);
};
/**
* struct i915_pxp_component - Used for communication between i915 and TEE
* drivers for the PXP services
*/
struct i915_pxp_component {
/**
* @tee_dev: device that provide the PXP service from TEE Bus.
*/
struct device *tee_dev;
/**
* @ops: Ops implemented by TEE driver, used by i915 driver.
*/
const struct i915_pxp_component_ops *ops;
/**
* @mutex: To protect the above members.
*/
struct mutex mutex;
};
#endif /* _I915_TEE_PXP_INTERFACE_H_ */
linux-7.2.3/include/drm/intel/intel-gtt.h
+41
View File
@@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Common header for intel-gtt.ko and i915.ko */
#ifndef _DRM_INTEL_GTT_H
#define _DRM_INTEL_GTT_H
#include <linux/types.h>
struct agp_bridge_data;
struct pci_dev;
struct sg_table;
void intel_gmch_gtt_get(u64 *gtt_total,
phys_addr_t *mappable_base,
resource_size_t *mappable_end);
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
struct agp_bridge_data *bridge);
void intel_gmch_remove(void);
bool intel_gmch_enable_gtt(void);
void intel_gmch_gtt_flush(void);
void intel_gmch_gtt_insert_page(dma_addr_t addr,
unsigned int pg,
unsigned int flags);
void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
unsigned int pg_start,
unsigned int flags);
void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
dma_addr_t intel_gmch_gtt_read_entry(unsigned int pg,
bool *is_present, bool *is_local);
/* Special gtt memory types */
#define AGP_DCACHE_MEMORY 1
#define AGP_PHYS_MEMORY 2
/* flag for GFDT type */
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
#endif
linux-7.2.3/include/drm/intel/intel_gmd_interrupt_regs.h
+92
View File
@@ -0,0 +1,92 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2026 Intel Corporation */
#ifndef _INTEL_GMD_INTERRUPT_REGS_H_
#define _INTEL_GMD_INTERRUPT_REGS_H_
#define I915_PM_INTERRUPT (1 << 31)
#define I915_ISP_INTERRUPT (1 << 22)
#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
#define I915_MIPIC_INTERRUPT (1 << 19)
#define I915_MIPIA_INTERRUPT (1 << 18)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
#define I915_HWB_OOM_INTERRUPT (1 << 13)
#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
#define I915_MISC_INTERRUPT (1 << 11)
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
#define I915_DEBUG_INTERRUPT (1 << 2)
#define I915_WINVALID_INTERRUPT (1 << 1)
#define I915_USER_INTERRUPT (1 << 1)
#define I915_ASLE_INTERRUPT (1 << 0)
#define I915_BSD_USER_INTERRUPT (1 << 25)
#define GEN8_MASTER_IRQ _MMIO(0x44200)
#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
#define GEN8_PCU_IRQ (1 << 30)
#define GEN8_DE_PCH_IRQ (1 << 23)
#define GEN8_DE_MISC_IRQ (1 << 22)
#define GEN8_DE_PORT_IRQ (1 << 20)
#define GEN8_DE_PIPE_C_IRQ (1 << 18)
#define GEN8_DE_PIPE_B_IRQ (1 << 17)
#define GEN8_DE_PIPE_A_IRQ (1 << 16)
#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
#define GEN8_GT_VECS_IRQ (1 << 6)
#define GEN8_GT_GUC_IRQ (1 << 5)
#define GEN8_GT_PM_IRQ (1 << 4)
#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
#define GEN8_GT_BCS_IRQ (1 << 1)
#define GEN8_GT_RCS_IRQ (1 << 0)
#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
#define GEN11_GU_MISC_IER _MMIO(0x444fc)
#define GEN11_GU_MISC_GSE (1 << 27)
#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
GEN11_GU_MISC_IER, \
GEN11_GU_MISC_IIR)
#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
#define GEN11_MASTER_IRQ (1 << 31)
#define GEN11_PCU_IRQ (1 << 30)
#define GEN11_GU_MISC_IRQ (1 << 29)
#define GEN11_DISPLAY_IRQ (1 << 16)
#define GEN11_GT_DW_IRQ(x) (1 << (x))
#define GEN11_GT_DW1_IRQ (1 << 1)
#define GEN11_GT_DW0_IRQ (1 << 0)
#define SCPD0 _MMIO(0x209c) /* 915+ only */
#define SCPD_FBC_IGNORE_3D (1 << 6)
#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
#define VLV_PCBR_ADDR_SHIFT 12
#endif
linux-7.2.3/include/drm/intel/intel_gmd_misc_regs.h
+21
View File
@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2026 Intel Corporation */
#ifndef _INTEL_GMD_MISC_REGS_H_
#define _INTEL_GMD_MISC_REGS_H_
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
#define DISP_FBC_WM_DIS REG_BIT(15)
#define INSTPM _MMIO(0x20c0)
#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
will not assert AGPBUSY# and will only
be delivered when out of C3. */
#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
#define INSTPM_TLB_INVALIDATE (1 << 9)
#define INSTPM_SYNC_FLUSH (1 << 5)
#endif
linux-7.2.3/include/drm/intel/intel_lb_mei_interface.h
+104
View File
@@ -0,0 +1,104 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2025 Intel Corporation
*/
#ifndef _INTEL_LB_MEI_INTERFACE_H_
#define _INTEL_LB_MEI_INTERFACE_H_
#include <linux/bits.h>
#include <linux/types.h>
struct device;
/**
* define INTEL_LB_FLAG_IS_PERSISTENT - Mark the payload as persistent
*
* This flag indicates that the late binding payload should be stored
* persistently in flash across warm resets.
*/
#define INTEL_LB_FLAG_IS_PERSISTENT BIT(0)
/**
* enum intel_lb_type - enum to determine late binding payload type
* @INTEL_LB_TYPE_FAN_CONTROL: Fan controller configuration
* @INTEL_LB_TYPE_OCODE: Ocode firmware
*/
enum intel_lb_type {
INTEL_LB_TYPE_FAN_CONTROL = 1,
INTEL_LB_TYPE_OCODE = 3,
};
/**
* enum intel_lb_status - Status codes returned on late binding transmissions
* @INTEL_LB_STATUS_SUCCESS: Operation completed successfully
* @INTEL_LB_STATUS_4ID_MISMATCH: Mismatch in the expected 4ID (firmware identity/token)
* @INTEL_LB_STATUS_ARB_FAILURE: Arbitration failure (e.g. conflicting access or state)
* @INTEL_LB_STATUS_GENERAL_ERROR: General firmware error not covered by other codes
* @INTEL_LB_STATUS_INVALID_PARAMS: One or more input parameters are invalid
* @INTEL_LB_STATUS_INVALID_SIGNATURE: Payload has an invalid or untrusted signature
* @INTEL_LB_STATUS_INVALID_PAYLOAD: Payload contents are not accepted by firmware
* @INTEL_LB_STATUS_TIMEOUT: Operation timed out before completion
* @INTEL_LB_STATUS_BUFFER_TOO_SMALL: Buffer provided is smaller when expected
* @INTEL_LB_STATUS_INTERNAL_ERROR: Internal firmware error
* @INTEL_LB_STATUS_INVALID_FPT_TABLE: Invalid firmware format table
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_VERIFICATION_ERROR: Error in signature verification
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_INVALID_CPD: Invalid CPD
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_FW_VERSION_MISMATCH: Firmware version mismatch
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_INVALID_MANIFEST: Invalid firmware manifest
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_INVALID_HASH: Wrong hash in signature
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_BINDING_TYPE_MISMATCH: Wrong firmware type provided
* @INTEL_LB_STATUS_SIGNED_PAYLOAD_HANDLE_SVN_FAILED: SVN check failed
* @INTEL_LB_STATUS_DESTINATION_MBOX_FAILURE: Failed to send datat to destination
* @INTEL_LB_STATUS_MISSING_LOADING_PATCH: No loading patch found
* @INTEL_LB_STATUS_INVALID_COMMAND: Invalid command number
* @INTEL_LB_STATUS_INVALID_HECI_HEADER: Invalid transport header
* @INTEL_LB_STATUS_IP_ERROR_START: Base for internal errors
*/
enum intel_lb_status {
INTEL_LB_STATUS_SUCCESS = 0,
INTEL_LB_STATUS_4ID_MISMATCH = 1,
INTEL_LB_STATUS_ARB_FAILURE = 2,
INTEL_LB_STATUS_GENERAL_ERROR = 3,
INTEL_LB_STATUS_INVALID_PARAMS = 4,
INTEL_LB_STATUS_INVALID_SIGNATURE = 5,
INTEL_LB_STATUS_INVALID_PAYLOAD = 6,
INTEL_LB_STATUS_TIMEOUT = 7,
INTEL_LB_STATUS_BUFFER_TOO_SMALL = 8,
INTEL_LB_STATUS_INTERNAL_ERROR = 9,
INTEL_LB_STATUS_INVALID_FPT_TABLE = 10,
INTEL_LB_STATUS_SIGNED_PAYLOAD_VERIFICATION_ERROR = 11,
INTEL_LB_STATUS_SIGNED_PAYLOAD_INVALID_CPD = 12,
INTEL_LB_STATUS_SIGNED_PAYLOAD_FW_VERSION_MISMATCH = 13,
INTEL_LB_STATUS_SIGNED_PAYLOAD_INVALID_MANIFEST = 14,
INTEL_LB_STATUS_SIGNED_PAYLOAD_INVALID_HASH = 15,
INTEL_LB_STATUS_SIGNED_PAYLOAD_BINDING_TYPE_MISMATCH = 16,
INTEL_LB_STATUS_SIGNED_PAYLOAD_HANDLE_SVN_FAILED = 17,
INTEL_LB_STATUS_DESTINATION_MBOX_FAILURE = 18,
INTEL_LB_STATUS_MISSING_LOADING_PATCH = 19,
INTEL_LB_STATUS_INVALID_COMMAND = 20,
INTEL_LB_STATUS_INVALID_HECI_HEADER = 21,
INTEL_LB_STATUS_IP_ERROR_START = BIT(31),
};
/**
* struct intel_lb_component_ops - Ops for late binding services
*/
struct intel_lb_component_ops {
/**
* @push_payload: Sends a payload to the authentication firmware
*
* @dev: Device struct corresponding to the mei device
* @type: Payload type (see &enum intel_lb_type)
* @flags: Payload flags bitmap (e.g. %INTEL_LB_FLAGS_IS_PERSISTENT)
* @payload: Pointer to payload buffer
* @payload_size: Payload buffer size in bytes
*
* Return: 0 success, negative errno value on transport failure,
* positive error status returned by firmware
*/
int (*push_payload)(struct device *dev, u32 type, u32 flags,
const void *payload, size_t payload_size);
};
#endif /* _INTEL_LB_MEI_INTERFACE_H_ */
linux-7.2.3/include/drm/intel/intel_lpe_audio.h
+51
View File
@@ -0,0 +1,51 @@
/*
* Copyright © 2016 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _INTEL_LPE_AUDIO_H_
#define _INTEL_LPE_AUDIO_H_
#include <linux/types.h>
#include <linux/spinlock_types.h>
struct platform_device;
#define HDMI_MAX_ELD_BYTES 128
struct intel_hdmi_lpe_audio_port_pdata {
u8 eld[HDMI_MAX_ELD_BYTES];
int port;
int pipe;
int ls_clock;
bool dp_output;
};
struct intel_hdmi_lpe_audio_pdata {
struct intel_hdmi_lpe_audio_port_pdata port[3]; /* for ports B,C,D */
int num_ports;
int num_pipes;
void (*notify_audio_lpe)(struct platform_device *pdev, int port); /* port: 0==B,1==C,2==D */
spinlock_t lpe_audio_slock;
};
#endif /* _I915_LPE_AUDIO_H_ */
linux-7.2.3/include/drm/intel/intel_pcode_regs.h
+108
View File
@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2026 Intel Corporation */
#ifndef _INTEL_PCODE_REGS_H_
#define _INTEL_PCODE_REGS_H_
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
#define GEN6_PCODE_ERROR_MASK 0xFF
#define GEN6_PCODE_SUCCESS 0x0
#define GEN6_PCODE_ILLEGAL_CMD 0x1
#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
#define GEN6_PCODE_TIMEOUT 0x3
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
#define GEN7_PCODE_TIMEOUT 0x2
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
#define GEN9_PCODE_READ_MEM_LATENCY 0x6
#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
#define SKL_PCODE_CDCLK_CONTROL 0x7
#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
#define SKL_CDCLK_READY_FOR_CHANGE 0x1
#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
#define GEN6_READ_OC_PARAMS 0xc
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define ICL_PCODE_EXIT_TCCOLD 0x12
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
#define TGL_PCODE_TCCOLD 0x26
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
/* See also IPS_CTL */
#define IPS_PCODE_CONTROL (1 << 30)
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN9_PCODE_SAGV_CONTROL 0x21
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define DG1_PCODE_STATUS 0x7E
#define DG1_UNCORE_GET_INIT_STATUS 0x0
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
#define PCODE_POWER_SETUP 0x7C
#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
#define POWER_SETUP_I1_WATTS REG_BIT(31)
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
#define PCODE_MBOX_DOMAIN_NONE 0x0
#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
#endif
linux-7.2.3/include/drm/intel/mchbar_regs.h
+273
View File
@@ -0,0 +1,273 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_MCHBAR_REGS__
#define __INTEL_MCHBAR_REGS__
#include "i915_reg_defs.h"
/*
* MCHBAR mirror.
*
* This mirrors the MCHBAR MMIO space whose location is determined by
* device 0 function 0's pci config register 0x44 or 0x48 and matches it in
* every way. It is not accessible from the CP register read instructions.
*
* Starting from Haswell, you can't write registers using the MCHBAR mirror,
* just read. On MTL+ the mirror no longer exists.
*/
#define MCHBAR_MIRROR_BASE 0x10000
#define MCHBAR_MIRROR_END 0x13fff
#define MCHBAR_MIRROR_BASE_SNB 0x140000
#define MCHBAR_MIRROR_END_SNB 0x147fff
#define MCHBAR_MIRROR_END_ICL_RKL 0x14ffff
#define MCHBAR_MIRROR_END_TGL 0x15ffff
#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
/* Pineview MCH register contains DDR3 setting */
#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
#define CSHRDDR3CTL_DDR3 (1 << 2)
/* 915-945 and GM965 MCH register controlling DRAM channel access */
#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
#define DCC_ADDRESSING_MODE_MASK (3 << 0)
#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
/* 965 MCH register controlling DRAM channel configuration */
#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
/* Clocking configuration register */
#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */
#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */
#define CLKCFG_FSB_MASK (7 << 0)
#define CLKCFG_MEM_533 (1 << 4)
#define CLKCFG_MEM_667 (2 << 4)
#define CLKCFG_MEM_800 (3 << 4)
#define CLKCFG_MEM_MASK (7 << 4)
#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
#define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)
#define TSE (1 << 0)
#define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)
#define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)
#define TSFS_SLOPE_MASK 0x0000ff00
#define TSFS_SLOPE_SHIFT 8
#define TSFS_INTR_MASK 0x000000ff
/* Memory latency timer register */
#define MLTR_ILK _MMIO(MCHBAR_MIRROR_BASE + 0x1222)
/* the unit of memory self-refresh latency time is 0.5us */
#define MLTR_WM2_MASK REG_GENMASK(13, 8)
#define MLTR_WM1_MASK REG_GENMASK(5, 0)
#define CSIPLL0 _MMIO(MCHBAR_MIRROR_BASE + 0x2c10)
#define DDRMPLL1 _MMIO(MCHBAR_MIRROR_BASE + 0x2c20)
#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
#define ILK_GRDOM_FULL (0 << 1)
#define ILK_GRDOM_RENDER (1 << 1)
#define ILK_GRDOM_MEDIA (3 << 1)
#define ILK_GRDOM_MASK (3 << 1)
#define ILK_GRDOM_RESET_ENABLE (1 << 0)
#define BXT_D_CR_DRP0_DUNIT8 0x1000
#define BXT_D_CR_DRP0_DUNIT9 0x1200
#define BXT_D_CR_DRP0_DUNIT_START 8
#define BXT_D_CR_DRP0_DUNIT_END 11
#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
_PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
BXT_D_CR_DRP0_DUNIT9))
#define BXT_DRAM_RANK_MASK 0x3
#define BXT_DRAM_RANK_SINGLE 0x1
#define BXT_DRAM_RANK_DUAL 0x3
#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
#define BXT_DRAM_WIDTH_SHIFT 4
#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
#define BXT_DRAM_SIZE_MASK (0x7 << 6)
#define BXT_DRAM_SIZE_SHIFT 6
#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
#define BXT_DRAM_TYPE_MASK (0x7 << 22)
#define BXT_DRAM_TYPE_SHIFT 22
#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
#define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
#define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
#define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
#define SKL_DRAM_DDR_TYPE_MASK REG_GENMASK(1, 0)
#define SKL_DRAM_DDR_TYPE_DDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 0)
#define SKL_DRAM_DDR_TYPE_DDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 1)
#define SKL_DRAM_DDR_TYPE_LPDDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 2)
#define SKL_DRAM_DDR_TYPE_LPDDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 3)
/* snb MCH registers for reading the DRAM channel configuration */
#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define MAD_DIMM_ECC_MASK (0x3 << 24)
#define MAD_DIMM_ECC_OFF (0x0 << 24)
#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
#define MAD_DIMM_ECC_ON (0x3 << 24)
#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
#define MAD_DIMM_A_SELECT (0x1 << 16)
/* DIMM sizes are in multiples of 256mb. */
#define MAD_DIMM_B_SIZE_SHIFT 8
#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
#define MAD_DIMM_A_SIZE_SHIFT 0
#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
#define SKL_DIMM_S_RANK_MASK REG_GENMASK(26, 26)
#define SKL_DIMM_S_RANK_1 REG_FIELD_PREP(SKL_DIMM_S_RANK_MASK, 0)
#define SKL_DIMM_S_RANK_2 REG_FIELD_PREP(SKL_DIMM_S_RANK_MASK, 1)
#define SKL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24)
#define SKL_DIMM_S_WIDTH_X8 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 0)
#define SKL_DIMM_S_WIDTH_X16 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 1)
#define SKL_DIMM_S_WIDTH_X32 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 2)
#define SKL_DIMM_S_SIZE_MASK REG_GENMASK(21, 16)
#define SKL_DIMM_L_RANK_MASK REG_GENMASK(10, 10)
#define SKL_DIMM_L_RANK_1 REG_FIELD_PREP(SKL_DIMM_L_RANK_MASK, 0)
#define SKL_DIMM_L_RANK_2 REG_FIELD_PREP(SKL_DIMM_L_RANK_MASK, 1)
#define SKL_DIMM_L_WIDTH_MASK REG_GENMASK(9, 8)
#define SKL_DIMM_L_WIDTH_X8 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 0)
#define SKL_DIMM_L_WIDTH_X16 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 1)
#define SKL_DIMM_L_WIDTH_X32 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 2)
#define SKL_DIMM_L_SIZE_MASK REG_GENMASK(5, 0)
#define ICL_DIMM_S_RANK_MASK REG_GENMASK(27, 26)
#define ICL_DIMM_S_RANK_1 REG_FIELD_PREP(ICL_DIMM_S_RANK_MASK, 0)
#define ICL_DIMM_S_RANK_2 REG_FIELD_PREP(ICL_DIMM_S_RANK_MASK, 1)
#define ICL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24)
#define ICL_DIMM_S_WIDTH_X8 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 0)
#define ICL_DIMM_S_WIDTH_X16 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 1)
#define ICL_DIMM_S_WIDTH_X32 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 2)
#define ICL_DIMM_S_SIZE_MASK REG_GENMASK(22, 16)
#define ICL_DIMM_L_RANK_MASK REG_GENMASK(10, 9)
#define ICL_DIMM_L_RANK_1 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 0)
#define ICL_DIMM_L_RANK_2 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 1)
#define ICL_DIMM_L_RANK_3 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 2)
#define ICL_DIMM_L_RANK_4 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 3)
#define ICL_DIMM_L_WIDTH_MASK REG_GENMASK(8, 7)
#define ICL_DIMM_L_WIDTH_X8 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 0)
#define ICL_DIMM_L_WIDTH_X16 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 1)
#define ICL_DIMM_L_WIDTH_X32 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 2)
#define ICL_DIMM_L_SIZE_MASK REG_GENMASK(6, 0)
#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
#define DG1_QCLK_REFERENCE REG_BIT(10)
/*
* *_PACKAGE_POWER_SKU - SKU power and timing parameters.
*/
#define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930)
#define PKG_PKG_TDP GENMASK_ULL(14, 0)
#define PKG_MIN_PWR GENMASK_ULL(30, 16)
#define PKG_MAX_PWR GENMASK_ULL(46, 32)
#define PKG_MAX_WIN GENMASK_ULL(54, 48)
#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
#define PKG_TIME_UNIT REG_GENMASK(19, 16)
#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
#define PCU_PACKAGE_TEMPERATURE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978)
#define TEMP_MASK REG_GENMASK(7, 0)
#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
#define RP0_CAP_MASK REG_GENMASK(7, 0)
#define RP1_CAP_MASK REG_GENMASK(15, 8)
#define RPN_CAP_MASK REG_GENMASK(23, 16)
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
#define PKG_PWR_LIM_1_EN REG_BIT(15)
#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
#define SSKPD_WM4_MASK_HSW REG_GENMASK64(40, 32)
#define SSKPD_WM3_MASK_HSW REG_GENMASK64(28, 20)
#define SSKPD_WM2_MASK_HSW REG_GENMASK64(19, 12)
#define SSKPD_WM1_MASK_HSW REG_GENMASK64(11, 4)
#define SSKPD_OLD_WM0_MASK_HSW REG_GENMASK64(3, 0)
#define SSKPD_WM3_MASK_SNB REG_GENMASK(29, 24)
#define SSKPD_WM2_MASK_SNB REG_GENMASK(21, 16)
#define SSKPD_WM1_MASK_SNB REG_GENMASK(13, 8)
#define SSKPD_WM0_MASK_SNB REG_GENMASK(5, 0)
/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
#define DG1_GEAR_TYPE REG_BIT(16)
/*
* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
* since on HSW we can't write to it using intel_uncore_write.
*/
#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)
#define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
#define D_COMP_COMP_FORCE (1 << 8)
#define D_COMP_COMP_DISABLE (1 << 0)
#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
#endif /* __INTEL_MCHBAR_REGS */
linux-7.2.3/include/drm/intel/pci_config.h
+110
View File
@@ -0,0 +1,110 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_PCI_CONFIG_H__
#define __INTEL_PCI_CONFIG_H__
/* PCI BARs */
#define GEN2_GMADR_BAR 0
#define GEN2_MMADR_BAR 1 /* MMIO+GTT, despite the name */
#define GEN2_IO_BAR 2 /* 85x/865 */
#define GEN3_MMADR_BAR 0 /* MMIO only */
#define GEN3_IO_BAR 1
#define GEN3_GMADR_BAR 2
#define GEN3_GTTADR_BAR 3 /* GTT only */
#define GEN4_GTTMMADR_BAR 0 /* MMIO+GTT */
#define GEN4_GMADR_BAR 2
#define GEN4_IO_BAR 4
#define GEN12_LMEM_BAR 2
static inline int intel_mmio_bar(int graphics_ver)
{
switch (graphics_ver) {
case 2: return GEN2_MMADR_BAR;
case 3: return GEN3_MMADR_BAR;
default: return GEN4_GTTMMADR_BAR;
}
}
/* BSM in include/drm/intel/i915_drm.h */
#define MCHBAR_I915 0x44
#define MCHBAR_I965 0x48
#define MCHBAR_SIZE (4 * 4096)
#define DEVEN 0x54
#define DEVEN_MCHBAR_EN (1 << 28)
#define HPLLCC 0xc0 /* 85x only */
#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
#define GC_CLOCK_133_200 (0 << 0)
#define GC_CLOCK_100_200 (1 << 0)
#define GC_CLOCK_100_133 (2 << 0)
#define GC_CLOCK_133_266 (3 << 0)
#define GC_CLOCK_133_200_2 (4 << 0)
#define GC_CLOCK_133_266_2 (5 << 0)
#define GC_CLOCK_166_266 (6 << 0)
#define GC_CLOCK_166_250 (7 << 0)
#define I915_GDRST 0xc0
#define GRDOM_FULL (0 << 2)
#define GRDOM_RENDER (1 << 2)
#define GRDOM_MEDIA (3 << 2)
#define GRDOM_MASK (3 << 2)
#define GRDOM_RESET_STATUS (1 << 1)
#define GRDOM_RESET_ENABLE (1 << 0)
/* BSpec only has register offset, PCI device and bit found empirically */
#define I830_CLOCK_GATE 0xc8 /* device 0 */
#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
#define GCDGMBUS 0xcc
#define GCFGC2 0xda
#define GCFGC 0xf0 /* 915+ only */
#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
#define GC_DISPLAY_CLOCK_MASK (7 << 4)
#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
#define ASLE 0xe4
#define ASLS 0xfc
#define SWSCI 0xe8
#define SWSCI_SCISEL (1 << 15)
#define SWSCI_GSSCIE (1 << 0)
/* legacy/combination backlight modes, also called LBB */
#define LBPC 0xf4
#endif /* __INTEL_PCI_CONFIG_H__ */
linux-7.2.3/include/drm/intel/pciids.h
+919
View File
@@ -0,0 +1,919 @@
/*
* Copyright 2013 Intel Corporation
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __PCIIDS_H__
#define __PCIIDS_H__
#ifdef __KERNEL__
#define INTEL_PCI_DEVICE(_id, _info) { \
PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \
.driver_data = (kernel_ulong_t)(_info), \
}
#define INTEL_VGA_DEVICE(_id, _info) { \
PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \
.class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \
.driver_data = (kernel_ulong_t)(_info), \
}
#define INTEL_QUANTA_VGA_DEVICE(_info) { \
.vendor = PCI_VENDOR_ID_INTEL, .device = 0x16a, \
.subvendor = 0x152d, .subdevice = 0x8990, \
.class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \
.driver_data = (kernel_ulong_t)(_info), \
}
#endif
#define INTEL_I810_IDS(MACRO__, ...) \
MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
#define INTEL_I815_IDS(MACRO__, ...) \
MACRO__(0x1132, ## __VA_ARGS__) /* I815*/
#define INTEL_I830_IDS(MACRO__, ...) \
MACRO__(0x3577, ## __VA_ARGS__)
#define INTEL_I845G_IDS(MACRO__, ...) \
MACRO__(0x2562, ## __VA_ARGS__)
#define INTEL_I85X_IDS(MACRO__, ...) \
MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
MACRO__(0x358e, ## __VA_ARGS__)
#define INTEL_I865G_IDS(MACRO__, ...) \
MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */
#define INTEL_I915G_IDS(MACRO__, ...) \
MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
#define INTEL_I915GM_IDS(MACRO__, ...) \
MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */
#define INTEL_I945G_IDS(MACRO__, ...) \
MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */
#define INTEL_I945GM_IDS(MACRO__, ...) \
MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
#define INTEL_I965G_IDS(MACRO__, ...) \
MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
#define INTEL_G33_IDS(MACRO__, ...) \
MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
#define INTEL_I965GM_IDS(MACRO__, ...) \
MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
#define INTEL_GM45_IDS(MACRO__, ...) \
MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */
#define INTEL_G45_IDS(MACRO__, ...) \
MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
#define INTEL_PNV_G_IDS(MACRO__, ...) \
MACRO__(0xa001, ## __VA_ARGS__)
#define INTEL_PNV_M_IDS(MACRO__, ...) \
MACRO__(0xa011, ## __VA_ARGS__)
#define INTEL_PNV_IDS(MACRO__, ...) \
INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_ILK_D_IDS(MACRO__, ...) \
MACRO__(0x0042, ## __VA_ARGS__)
#define INTEL_ILK_M_IDS(MACRO__, ...) \
MACRO__(0x0046, ## __VA_ARGS__)
#define INTEL_ILK_IDS(MACRO__, ...) \
INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
MACRO__(0x0102, ## __VA_ARGS__), \
MACRO__(0x010A, ## __VA_ARGS__)
#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
MACRO__(0x0112, ## __VA_ARGS__), \
MACRO__(0x0122, ## __VA_ARGS__)
#define INTEL_SNB_D_IDS(MACRO__, ...) \
INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \
MACRO__(0x0106, ## __VA_ARGS__)
#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
MACRO__(0x0116, ## __VA_ARGS__), \
MACRO__(0x0126, ## __VA_ARGS__)
#define INTEL_SNB_M_IDS(MACRO__, ...) \
INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_SNB_IDS(MACRO__, ...) \
INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \
MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */
#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \
MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */
#define INTEL_IVB_M_IDS(MACRO__, ...) \
INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
#define INTEL_IVB_D_IDS(MACRO__, ...) \
INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_IVB_IDS(MACRO__, ...) \
INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_IVB_Q_IDS(MACRO__, ...) \
INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */
#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \
MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */
#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \
MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \
#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
#define INTEL_HSW_IDS(MACRO__, ...) \
INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_VLV_IDS(MACRO__, ...) \
MACRO__(0x0f30, ## __VA_ARGS__), \
MACRO__(0x0f31, ## __VA_ARGS__), \
MACRO__(0x0f32, ## __VA_ARGS__), \
MACRO__(0x0f33, ## __VA_ARGS__)
#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \
MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */
#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \
MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */
#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \
MACRO__(0x162E, ## __VA_ARGS__) /* ULX */
#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \
MACRO__(0x163E, ## __VA_ARGS__) /* ULX */
#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
#define INTEL_BDW_IDS(MACRO__, ...) \
INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_CHV_IDS(MACRO__, ...) \
MACRO__(0x22b0, ## __VA_ARGS__), \
MACRO__(0x22b1, ## __VA_ARGS__), \
MACRO__(0x22b2, ## __VA_ARGS__), \
MACRO__(0x22b3, ## __VA_ARGS__)
#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \
MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */
#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
#define INTEL_SKL_IDS(MACRO__, ...) \
INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_BXT_IDS(MACRO__, ...) \
MACRO__(0x0A84, ## __VA_ARGS__), \
MACRO__(0x1A84, ## __VA_ARGS__), \
MACRO__(0x1A85, ## __VA_ARGS__), \
MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
#define INTEL_GLK_IDS(MACRO__, ...) \
MACRO__(0x3184, ## __VA_ARGS__), \
MACRO__(0x3185, ## __VA_ARGS__)
#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \
MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */
#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \
MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */
#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
#define INTEL_KBL_GT4_IDS(MACRO__, ...) \
MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */
/* AML/KBL Y GT2 */
#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
/* AML/CFL Y GT2 */
#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \
MACRO__(0x87CA, ## __VA_ARGS__)
/* CML GT1 */
#define INTEL_CML_GT1_IDS(MACRO__, ...) \
MACRO__(0x9BA2, ## __VA_ARGS__), \
MACRO__(0x9BA4, ## __VA_ARGS__), \
MACRO__(0x9BA5, ## __VA_ARGS__), \
MACRO__(0x9BA8, ## __VA_ARGS__)
#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
MACRO__(0x9B21, ## __VA_ARGS__), \
MACRO__(0x9BAA, ## __VA_ARGS__), \
MACRO__(0x9BAC, ## __VA_ARGS__)
/* CML GT2 */
#define INTEL_CML_GT2_IDS(MACRO__, ...) \
MACRO__(0x9BC2, ## __VA_ARGS__), \
MACRO__(0x9BC4, ## __VA_ARGS__), \
MACRO__(0x9BC5, ## __VA_ARGS__), \
MACRO__(0x9BC6, ## __VA_ARGS__), \
MACRO__(0x9BC8, ## __VA_ARGS__), \
MACRO__(0x9BE6, ## __VA_ARGS__), \
MACRO__(0x9BF6, ## __VA_ARGS__)
#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
MACRO__(0x9B41, ## __VA_ARGS__), \
MACRO__(0x9BCA, ## __VA_ARGS__), \
MACRO__(0x9BCC, ## __VA_ARGS__)
#define INTEL_CML_IDS(MACRO__, ...) \
INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_KBL_IDS(MACRO__, ...) \
INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
/* CFL S */
#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
/* CFL H */
#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \
MACRO__(0x3E9C, ## __VA_ARGS__)
#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
/* CFL U GT2 */
#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \
MACRO__(0x3EA9, ## __VA_ARGS__)
/* CFL U GT3 */
#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
#define INTEL_CFL_IDS(MACRO__, ...) \
INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
/* WHL/CFL U GT1 */
#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
MACRO__(0x3EA1, ## __VA_ARGS__), \
MACRO__(0x3EA4, ## __VA_ARGS__)
/* WHL/CFL U GT2 */
#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
MACRO__(0x3EA0, ## __VA_ARGS__), \
MACRO__(0x3EA3, ## __VA_ARGS__)
/* WHL/CFL U GT3 */
#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \
MACRO__(0x3EA2, ## __VA_ARGS__)
#define INTEL_WHL_IDS(MACRO__, ...) \
INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
MACRO__(0x5A44, ## __VA_ARGS__), \
MACRO__(0x5A4C, ## __VA_ARGS__), \
MACRO__(0x5A54, ## __VA_ARGS__), \
MACRO__(0x5A5C, ## __VA_ARGS__)
#define INTEL_CNL_IDS(MACRO__, ...) \
INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x5A40, ## __VA_ARGS__), \
MACRO__(0x5A41, ## __VA_ARGS__), \
MACRO__(0x5A42, ## __VA_ARGS__), \
MACRO__(0x5A49, ## __VA_ARGS__), \
MACRO__(0x5A4A, ## __VA_ARGS__), \
MACRO__(0x5A50, ## __VA_ARGS__), \
MACRO__(0x5A51, ## __VA_ARGS__), \
MACRO__(0x5A52, ## __VA_ARGS__), \
MACRO__(0x5A59, ## __VA_ARGS__), \
MACRO__(0x5A5A, ## __VA_ARGS__)
/* ICL */
#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
MACRO__(0x8A50, ## __VA_ARGS__), \
MACRO__(0x8A52, ## __VA_ARGS__), \
MACRO__(0x8A53, ## __VA_ARGS__), \
MACRO__(0x8A54, ## __VA_ARGS__), \
MACRO__(0x8A56, ## __VA_ARGS__), \
MACRO__(0x8A57, ## __VA_ARGS__), \
MACRO__(0x8A58, ## __VA_ARGS__), \
MACRO__(0x8A59, ## __VA_ARGS__), \
MACRO__(0x8A5A, ## __VA_ARGS__), \
MACRO__(0x8A5B, ## __VA_ARGS__), \
MACRO__(0x8A5C, ## __VA_ARGS__), \
MACRO__(0x8A70, ## __VA_ARGS__), \
MACRO__(0x8A71, ## __VA_ARGS__)
#define INTEL_ICL_IDS(MACRO__, ...) \
INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x8A51, ## __VA_ARGS__), \
MACRO__(0x8A5D, ## __VA_ARGS__)
/* EHL */
#define INTEL_EHL_IDS(MACRO__, ...) \
MACRO__(0x4541, ## __VA_ARGS__), \
MACRO__(0x4551, ## __VA_ARGS__), \
MACRO__(0x4555, ## __VA_ARGS__), \
MACRO__(0x4557, ## __VA_ARGS__), \
MACRO__(0x4570, ## __VA_ARGS__), \
MACRO__(0x4571, ## __VA_ARGS__)
/* JSL */
#define INTEL_JSL_IDS(MACRO__, ...) \
MACRO__(0x4E51, ## __VA_ARGS__), \
MACRO__(0x4E55, ## __VA_ARGS__), \
MACRO__(0x4E57, ## __VA_ARGS__), \
MACRO__(0x4E61, ## __VA_ARGS__), \
MACRO__(0x4E71, ## __VA_ARGS__)
/* TGL */
#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
MACRO__(0x9A60, ## __VA_ARGS__), \
MACRO__(0x9A68, ## __VA_ARGS__), \
MACRO__(0x9A70, ## __VA_ARGS__)
#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
MACRO__(0x9A40, ## __VA_ARGS__), \
MACRO__(0x9A49, ## __VA_ARGS__), \
MACRO__(0x9A59, ## __VA_ARGS__), \
MACRO__(0x9A78, ## __VA_ARGS__), \
MACRO__(0x9AC0, ## __VA_ARGS__), \
MACRO__(0x9AC9, ## __VA_ARGS__), \
MACRO__(0x9AD9, ## __VA_ARGS__), \
MACRO__(0x9AF8, ## __VA_ARGS__)
#define INTEL_TGL_IDS(MACRO__, ...) \
INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
/* RKL */
#define INTEL_RKL_IDS(MACRO__, ...) \
MACRO__(0x4C80, ## __VA_ARGS__), \
MACRO__(0x4C8A, ## __VA_ARGS__), \
MACRO__(0x4C8B, ## __VA_ARGS__), \
MACRO__(0x4C8C, ## __VA_ARGS__), \
MACRO__(0x4C90, ## __VA_ARGS__), \
MACRO__(0x4C9A, ## __VA_ARGS__)
/* DG1 */
#define INTEL_DG1_IDS(MACRO__, ...) \
MACRO__(0x4905, ## __VA_ARGS__), \
MACRO__(0x4906, ## __VA_ARGS__), \
MACRO__(0x4907, ## __VA_ARGS__), \
MACRO__(0x4908, ## __VA_ARGS__), \
MACRO__(0x4909, ## __VA_ARGS__)
/* ADL-S */
#define INTEL_ADLS_IDS(MACRO__, ...) \
MACRO__(0x4680, ## __VA_ARGS__), \
MACRO__(0x4682, ## __VA_ARGS__), \
MACRO__(0x4688, ## __VA_ARGS__), \
MACRO__(0x468A, ## __VA_ARGS__), \
MACRO__(0x468B, ## __VA_ARGS__), \
MACRO__(0x4690, ## __VA_ARGS__), \
MACRO__(0x4692, ## __VA_ARGS__), \
MACRO__(0x4693, ## __VA_ARGS__)
/* ADL-P */
#define INTEL_ADLP_IDS(MACRO__, ...) \
MACRO__(0x46A0, ## __VA_ARGS__), \
MACRO__(0x46A1, ## __VA_ARGS__), \
MACRO__(0x46A2, ## __VA_ARGS__), \
MACRO__(0x46A3, ## __VA_ARGS__), \
MACRO__(0x46A6, ## __VA_ARGS__), \
MACRO__(0x46A8, ## __VA_ARGS__), \
MACRO__(0x46AA, ## __VA_ARGS__), \
MACRO__(0x462A, ## __VA_ARGS__), \
MACRO__(0x4626, ## __VA_ARGS__), \
MACRO__(0x4628, ## __VA_ARGS__), \
MACRO__(0x46B0, ## __VA_ARGS__), \
MACRO__(0x46B1, ## __VA_ARGS__), \
MACRO__(0x46B2, ## __VA_ARGS__), \
MACRO__(0x46B3, ## __VA_ARGS__), \
MACRO__(0x46C0, ## __VA_ARGS__), \
MACRO__(0x46C1, ## __VA_ARGS__), \
MACRO__(0x46C2, ## __VA_ARGS__), \
MACRO__(0x46C3, ## __VA_ARGS__)
/* ADL-N */
#define INTEL_ADLN_IDS(MACRO__, ...) \
MACRO__(0x46D0, ## __VA_ARGS__), \
MACRO__(0x46D1, ## __VA_ARGS__), \
MACRO__(0x46D2, ## __VA_ARGS__), \
MACRO__(0x46D3, ## __VA_ARGS__), \
MACRO__(0x46D4, ## __VA_ARGS__)
/* RPL-S */
#define INTEL_RPLS_IDS(MACRO__, ...) \
MACRO__(0xA780, ## __VA_ARGS__), \
MACRO__(0xA781, ## __VA_ARGS__), \
MACRO__(0xA782, ## __VA_ARGS__), \
MACRO__(0xA783, ## __VA_ARGS__), \
MACRO__(0xA788, ## __VA_ARGS__), \
MACRO__(0xA789, ## __VA_ARGS__), \
MACRO__(0xA78A, ## __VA_ARGS__), \
MACRO__(0xA78B, ## __VA_ARGS__)
/* RPL-U */
#define INTEL_RPLU_IDS(MACRO__, ...) \
MACRO__(0xA721, ## __VA_ARGS__), \
MACRO__(0xA7A1, ## __VA_ARGS__), \
MACRO__(0xA7A9, ## __VA_ARGS__), \
MACRO__(0xA7AC, ## __VA_ARGS__), \
MACRO__(0xA7AD, ## __VA_ARGS__)
/* RPL-P */
#define INTEL_RPLP_IDS(MACRO__, ...) \
MACRO__(0xA720, ## __VA_ARGS__), \
MACRO__(0xA7A0, ## __VA_ARGS__), \
MACRO__(0xA7A8, ## __VA_ARGS__), \
MACRO__(0xA7AA, ## __VA_ARGS__), \
MACRO__(0xA7AB, ## __VA_ARGS__)
/* DG2 */
#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
MACRO__(0x56A0, ## __VA_ARGS__), \
MACRO__(0x56A1, ## __VA_ARGS__), \
MACRO__(0x56A2, ## __VA_ARGS__)
#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
MACRO__(0x56BE, ## __VA_ARGS__), \
MACRO__(0x56BF, ## __VA_ARGS__)
#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
MACRO__(0x5690, ## __VA_ARGS__), \
MACRO__(0x5691, ## __VA_ARGS__), \
MACRO__(0x5692, ## __VA_ARGS__)
#define INTEL_DG2_G10_IDS(MACRO__, ...) \
INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
MACRO__(0x56A5, ## __VA_ARGS__), \
MACRO__(0x56A6, ## __VA_ARGS__), \
MACRO__(0x56B0, ## __VA_ARGS__), \
MACRO__(0x56B1, ## __VA_ARGS__)
#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
MACRO__(0x56BA, ## __VA_ARGS__), \
MACRO__(0x56BB, ## __VA_ARGS__), \
MACRO__(0x56BC, ## __VA_ARGS__), \
MACRO__(0x56BD, ## __VA_ARGS__)
#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
MACRO__(0x5693, ## __VA_ARGS__), \
MACRO__(0x5694, ## __VA_ARGS__), \
MACRO__(0x5695, ## __VA_ARGS__)
#define INTEL_DG2_G11_IDS(MACRO__, ...) \
INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
MACRO__(0x56A3, ## __VA_ARGS__), \
MACRO__(0x56A4, ## __VA_ARGS__), \
MACRO__(0x56B2, ## __VA_ARGS__), \
MACRO__(0x56B3, ## __VA_ARGS__)
#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
MACRO__(0x5696, ## __VA_ARGS__), \
MACRO__(0x5697, ## __VA_ARGS__)
#define INTEL_DG2_G12_IDS(MACRO__, ...) \
INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_DG2_D_IDS(MACRO__, ...) \
INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_DG2_IDS(MACRO__, ...) \
INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
#define INTEL_ATS_M150_IDS(MACRO__, ...) \
MACRO__(0x56C0, ## __VA_ARGS__), \
MACRO__(0x56C2, ## __VA_ARGS__)
#define INTEL_ATS_M75_IDS(MACRO__, ...) \
MACRO__(0x56C1, ## __VA_ARGS__)
#define INTEL_ATS_M_IDS(MACRO__, ...) \
INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
/* ARL */
#define INTEL_ARL_H_IDS(MACRO__, ...) \
MACRO__(0x7D51, ## __VA_ARGS__), \
MACRO__(0x7DD1, ## __VA_ARGS__)
#define INTEL_ARL_U_IDS(MACRO__, ...) \
MACRO__(0x7D41, ## __VA_ARGS__) \
#define INTEL_ARL_S_IDS(MACRO__, ...) \
MACRO__(0x7D67, ## __VA_ARGS__), \
MACRO__(0xB640, ## __VA_ARGS__)
#define INTEL_ARL_IDS(MACRO__, ...) \
INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \
INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
/* MTL */
#define INTEL_MTL_U_IDS(MACRO__, ...) \
MACRO__(0x7D40, ## __VA_ARGS__), \
MACRO__(0x7D45, ## __VA_ARGS__)
#define INTEL_MTL_IDS(MACRO__, ...) \
INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x7D55, ## __VA_ARGS__), \
MACRO__(0x7D60, ## __VA_ARGS__), \
MACRO__(0x7DD5, ## __VA_ARGS__)
/* PVC */
#define INTEL_PVC_IDS(MACRO__, ...) \
MACRO__(0x0B69, ## __VA_ARGS__), \
MACRO__(0x0B6E, ## __VA_ARGS__), \
MACRO__(0x0BD4, ## __VA_ARGS__), \
MACRO__(0x0BD5, ## __VA_ARGS__), \
MACRO__(0x0BD6, ## __VA_ARGS__), \
MACRO__(0x0BD7, ## __VA_ARGS__), \
MACRO__(0x0BD8, ## __VA_ARGS__), \
MACRO__(0x0BD9, ## __VA_ARGS__), \
MACRO__(0x0BDA, ## __VA_ARGS__), \
MACRO__(0x0BDB, ## __VA_ARGS__), \
MACRO__(0x0BE0, ## __VA_ARGS__), \
MACRO__(0x0BE1, ## __VA_ARGS__), \
MACRO__(0x0BE5, ## __VA_ARGS__)
/* LNL */
#define INTEL_LNL_IDS(MACRO__, ...) \
MACRO__(0x6420, ## __VA_ARGS__), \
MACRO__(0x64A0, ## __VA_ARGS__), \
MACRO__(0x64B0, ## __VA_ARGS__)
/* BMG */
#define INTEL_BMG_G21_IDS(MACRO__, ...) \
MACRO__(0xE202, ## __VA_ARGS__), \
MACRO__(0xE209, ## __VA_ARGS__), \
MACRO__(0xE20B, ## __VA_ARGS__), \
MACRO__(0xE20C, ## __VA_ARGS__), \
MACRO__(0xE20D, ## __VA_ARGS__), \
MACRO__(0xE210, ## __VA_ARGS__), \
MACRO__(0xE211, ## __VA_ARGS__), \
MACRO__(0xE212, ## __VA_ARGS__), \
MACRO__(0xE216, ## __VA_ARGS__)
#define INTEL_BMG_IDS(MACRO__, ...) \
INTEL_BMG_G21_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0xE220, ## __VA_ARGS__), \
MACRO__(0xE221, ## __VA_ARGS__), \
MACRO__(0xE222, ## __VA_ARGS__), \
MACRO__(0xE223, ## __VA_ARGS__)
/* PTL */
#define INTEL_PTL_IDS(MACRO__, ...) \
MACRO__(0xB080, ## __VA_ARGS__), \
MACRO__(0xB081, ## __VA_ARGS__), \
MACRO__(0xB082, ## __VA_ARGS__), \
MACRO__(0xB083, ## __VA_ARGS__), \
MACRO__(0xB084, ## __VA_ARGS__), \
MACRO__(0xB085, ## __VA_ARGS__), \
MACRO__(0xB086, ## __VA_ARGS__), \
MACRO__(0xB087, ## __VA_ARGS__), \
MACRO__(0xB08F, ## __VA_ARGS__), \
MACRO__(0xB090, ## __VA_ARGS__), \
MACRO__(0xB0A0, ## __VA_ARGS__), \
MACRO__(0xB0B0, ## __VA_ARGS__)
/* WCL */
#define INTEL_WCL_IDS(MACRO__, ...) \
MACRO__(0xFD80, ## __VA_ARGS__), \
MACRO__(0xFD81, ## __VA_ARGS__)
/* NVL-S */
#define INTEL_NVLS_IDS(MACRO__, ...) \
MACRO__(0xD740, ## __VA_ARGS__), \
MACRO__(0xD741, ## __VA_ARGS__), \
MACRO__(0xD742, ## __VA_ARGS__), \
MACRO__(0xD743, ## __VA_ARGS__), \
MACRO__(0xD744, ## __VA_ARGS__), \
MACRO__(0xD745, ## __VA_ARGS__)
/* CRI */
#define INTEL_CRI_IDS(MACRO__, ...) \
MACRO__(0x674C, ## __VA_ARGS__), \
MACRO__(0x674D, ## __VA_ARGS__), \
MACRO__(0x674E, ## __VA_ARGS__), \
MACRO__(0x674F, ## __VA_ARGS__), \
MACRO__(0x6750, ## __VA_ARGS__)
/* NVL-P */
#define INTEL_NVLP_IDS(MACRO__, ...) \
MACRO__(0xD750, ## __VA_ARGS__), \
MACRO__(0xD751, ## __VA_ARGS__), \
MACRO__(0xD752, ## __VA_ARGS__), \
MACRO__(0xD753, ## __VA_ARGS__), \
MACRO__(0XD754, ## __VA_ARGS__), \
MACRO__(0XD755, ## __VA_ARGS__), \
MACRO__(0XD756, ## __VA_ARGS__), \
MACRO__(0XD757, ## __VA_ARGS__), \
MACRO__(0xD75F, ## __VA_ARGS__)
#endif /* __PCIIDS_H__ */
linux-7.2.3/include/drm/intel/pick.h
+51
View File
@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2026 Intel Corporation */
#ifndef _PICK_H_
#define _PICK_H_
/*
* Given the first two numbers __a and __b of arbitrarily many evenly spaced
* numbers, pick the 0-based __index'th value.
*
* Always prefer this over _PICK() if the numbers are evenly spaced.
*/
#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
/*
* Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
* @__c_index corresponds to the index in which the second range starts to be
* used. Using math interval notation, the first range is used for indexes [ 0,
* @__c_index), while the second range is used for [ @__c_index, ... ). Example:
*
* #define _FOO_A 0xf000
* #define _FOO_B 0xf004
* #define _FOO_C 0xf008
* #define _SUPER_FOO_A 0xa000
* #define _SUPER_FOO_B 0xa100
* #define FOO(x) _MMIO(_PICK_EVEN_2RANGES(x, 3, \
* _FOO_A, _FOO_B, \
* _SUPER_FOO_A, _SUPER_FOO_B))
*
* This expands to:
* 0: 0xf000,
* 1: 0xf004,
* 2: 0xf008,
* 3: 0xa000,
* 4: 0xa100,
* 5: 0xa200,
* ...
*/
#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \
(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \
((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \
_PICK_EVEN((__index) - (__c_index), __c, __d)))
/*
* Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
*
* Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
*/
#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
#endif
linux-7.2.3/include/drm/intel/reg_bits.h
+139
View File
@@ -0,0 +1,139 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2026 Intel Corporation */
#ifndef _REG_BITS_H_
#define _REG_BITS_H_
#include <linux/bitfield.h>
#include <linux/bits.h>
/*
* Wrappers over the generic fixed width BIT_U*() and GENMASK_U*()
* implementations, for compatibility reasons with previous implementation.
*/
#define REG_GENMASK(high, low) GENMASK_U32(high, low)
#define REG_GENMASK64(high, low) GENMASK_U64(high, low)
#define REG_GENMASK16(high, low) GENMASK_U16(high, low)
#define REG_GENMASK8(high, low) GENMASK_U8(high, low)
#define REG_BIT(n) BIT_U32(n)
#define REG_BIT64(n) BIT_U64(n)
#define REG_BIT16(n) BIT_U16(n)
#define REG_BIT8(n) BIT_U8(n)
/*
* Local integer constant expression version of is_power_of_2().
*/
#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
/**
* REG_FIELD_PREP8() - Prepare a u8 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
*
* Local copy of FIELD_PREP() to generate an integer constant expression, force
* u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
#define REG_FIELD_PREP8(__mask, __val) \
((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
/**
* REG_FIELD_PREP16() - Prepare a u16 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
*
* Local copy of FIELD_PREP16() to generate an integer constant
* expression, force u8 and for consistency with
* REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
#define REG_FIELD_PREP16(__mask, __val) \
((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
/**
* REG_FIELD_PREP() - Prepare a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
*
* Local copy of FIELD_PREP() to generate an integer constant expression, force
* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
#define REG_FIELD_PREP(__mask, __val) \
((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
/**
* REG_FIELD_GET8() - Extract a u8 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to extract the bitfield value from
*
* Local wrapper for FIELD_GET() to force u8 and for consistency with
* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to extract the bitfield value from
*
* Local wrapper for FIELD_GET() to force u32 and for consistency with
* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
/**
* REG_FIELD_GET64() - Extract a u64 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to extract the bitfield value from
*
* Local wrapper for FIELD_GET() to force u64 and for consistency with
* REG_GENMASK64().
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
/**
* REG_FIELD_MAX() - produce the maximum value representable by a field
* @__mask: shifted mask defining the field's length and position
*
* Local wrapper for FIELD_MAX() to return the maximum bit value that can
* be held in the field specified by @_mask, cast to u32 for consistency
* with other macros.
*/
#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask))
#define REG_MASKED_FIELD(mask, value) \
(BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \
((mask) << 16 | (value)))
#define REG_MASKED_FIELD_ENABLE(a) \
(__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); })))
#define REG_MASKED_FIELD_DISABLE(a) \
(REG_MASKED_FIELD((a), 0))
#endif
linux-7.2.3/include/drm/intel/step.h
+62
View File
@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2026 Intel Corporation */
#ifndef __STEP_H__
#define __STEP_H__
#define STEP_ENUM_VAL(name) STEP_##name,
#define STEP_NAME_LIST(func) \
func(A0) \
func(A1) \
func(A2) \
func(A3) \
func(B0) \
func(B1) \
func(B2) \
func(B3) \
func(C0) \
func(C1) \
func(C2) \
func(C3) \
func(D0) \
func(D1) \
func(D2) \
func(D3) \
func(E0) \
func(E1) \
func(E2) \
func(E3) \
func(F0) \
func(F1) \
func(F2) \
func(F3) \
func(G0) \
func(G1) \
func(G2) \
func(G3) \
func(H0) \
func(H1) \
func(H2) \
func(H3) \
func(I0) \
func(I1) \
func(I2) \
func(I3) \
func(J0) \
func(J1) \
func(J2) \
func(J3)
/*
* Symbolic steppings that do not match the hardware. These are valid both as gt
* and display steppings as symbolic names.
*/
enum intel_step {
STEP_NONE = 0,
STEP_NAME_LIST(STEP_ENUM_VAL)
STEP_FUTURE,
STEP_FOREVER,
};
#endif /* __STEP_H__ */
linux-7.2.3/include/drm/intel/vlv_iosf_sb_regs.h
+192
View File
@@ -0,0 +1,192 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef _VLV_IOSF_SB_REGS_H_
#define _VLV_IOSF_SB_REGS_H_
enum vlv_iosf_sb_unit {
VLV_IOSF_SB_BUNIT,
VLV_IOSF_SB_CCK,
VLV_IOSF_SB_CCU,
VLV_IOSF_SB_DPIO,
VLV_IOSF_SB_DPIO_2,
VLV_IOSF_SB_FLISDSI,
VLV_IOSF_SB_GPIO,
VLV_IOSF_SB_NC,
VLV_IOSF_SB_PUNIT,
};
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
/* PUNIT_REG_*SSPM0 */
#define _SSPM0_SSC(val) ((val) << 0)
#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
#define _SSPM0_SSS(val) ((val) << 24)
#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
/* PUNIT_REG_*SSPM1 */
#define SSPM1_FREQSTAT_SHIFT 24
#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
#define SSPM1_FREQGUAR_SHIFT 8
#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
#define SSPM1_FREQ_SHIFT 0
#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
#define PUNIT_REG_VEDSSPM0 0x32
#define PUNIT_REG_VEDSSPM1 0x33
#define PUNIT_REG_DSPSSPM 0x36
#define DSPFREQSTAT_SHIFT_CHV 24
#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
#define DSPFREQGUAR_SHIFT_CHV 8
#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
#define DSPFREQSTAT_SHIFT 30
#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
#define DSPFREQGUAR_SHIFT 14
#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
#define PUNIT_REG_ISPSSPM0 0x39
#define PUNIT_REG_ISPSSPM1 0x3a
#define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61
#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
#define PUNIT_PWGT_IDX_RENDER 0
#define PUNIT_PWGT_IDX_MEDIA 1
#define PUNIT_PWGT_IDX_DISP2D 3
#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
#define PUNIT_PWGT_IDX_DPIO_RX0 10
#define PUNIT_PWGT_IDX_DPIO_RX1 11
#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
#define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4
#define PUNIT_REG_GPU_FREQ_STS 0xd8
#define GPLLENABLE (1 << 4)
#define GENFREQSTATUS (1 << 0)
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
#define PUNIT_REG_CZ_TIMESTAMP 0xce
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
#define FB_GFX_FREQ_FUSE_MASK 0xff
#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
#define PUNIT_REG_DDR_SETUP2 0x139
#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
#define FORCE_DDR_LOW_FREQ (1 << 1)
#define FORCE_DDR_HIGH_FREQ (1 << 0)
#define PUNIT_GPU_STATUS_REG 0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
#define VLV_TURBO_SOC_OVERRIDE 0x04
#define VLV_OVERRIDE_EN 1
#define VLV_SOC_TDP_EN (1 << 1)
#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
/* vlv2 north clock has */
#define CCK_FUSE_REG 0x8
#define CCK_FUSE_HPLL_FREQ_MASK 0x3
#define CCK_REG_DSI_PLL_FUSE 0x44
#define CCK_REG_DSI_PLL_CONTROL 0x48
#define DSI_PLL_VCO_EN (1 << 31)
#define DSI_PLL_LDO_GATE (1 << 30)
#define DSI_PLL_P1_POST_DIV_SHIFT 17
#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
#define DSI_PLL_MUX_MASK (3 << 9)
#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
#define DSI_PLL_LOCK (1 << 0)
#define CCK_REG_DSI_PLL_DIVIDER 0x4c
#define DSI_PLL_LFSR (1 << 31)
#define DSI_PLL_FRACTION_EN (1 << 30)
#define DSI_PLL_FRAC_COUNTER_SHIFT 27
#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
#define DSI_PLL_USYNC_CNT_SHIFT 18
#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
#define DSI_PLL_N1_DIV_SHIFT 16
#define DSI_PLL_N1_DIV_MASK (3 << 16)
#define DSI_PLL_M1_DIV_SHIFT 0
#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
#define CCK_CZ_CLOCK_CONTROL 0x62
#define CCK_GPLL_CLOCK_CONTROL 0x67
#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
#define CCK_TRUNK_FORCE_ON (1 << 17)
#define CCK_TRUNK_FORCE_OFF (1 << 16)
#define CCK_FREQUENCY_STATUS (0x1f << 8)
#define CCK_FREQUENCY_STATUS_SHIFT 8
#define CCK_FREQUENCY_VALUES (0x1f << 0)
#endif /* _VLV_IOSF_SB_REGS_H_ */
linux-7.2.3/include/drm/intel/xe_sriov_vfio.h
+154
View File
@@ -0,0 +1,154 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2025 Intel Corporation
*/
#ifndef _XE_SRIOV_VFIO_H_
#define _XE_SRIOV_VFIO_H_
#include <linux/types.h>
struct pci_dev;
struct xe_device;
/**
* xe_sriov_vfio_get_pf() - Get PF &xe_device.
* @pdev: the VF &pci_dev device
*
* Return: pointer to PF &xe_device, NULL otherwise.
*/
struct xe_device *xe_sriov_vfio_get_pf(struct pci_dev *pdev);
/**
* xe_sriov_vfio_migration_supported() - Check if migration is supported.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
*
* Return: true if migration is supported, false otherwise.
*/
bool xe_sriov_vfio_migration_supported(struct xe_device *xe);
/**
* xe_sriov_vfio_flr_prepare() - Notify PF that VF FLR prepare has started.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* This function marks VF FLR as pending before PF receives GuC FLR event.
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_flr_prepare(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_wait_flr_done() - Wait for VF FLR completion.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* This function will wait until VF FLR is processed by PF on all tiles (or
* until timeout occurs).
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_wait_flr_done(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_suspend_device() - Suspend VF.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* This function will pause VF on all tiles/GTs.
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_suspend_device(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_resume_device() - Resume VF.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* This function will resume VF on all tiles.
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_resume_device(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_stop_copy_enter() - Initiate a VF device migration data save.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_stop_copy_enter(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_stop_copy_exit() - Finish a VF device migration data save.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_stop_copy_exit(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_resume_data_enter() - Initiate a VF device migration data restore.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_resume_data_enter(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_resume_data_exit() - Finish a VF device migration data restore.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_resume_data_exit(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_error() - Move VF device to error state.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* Reset is needed to move it out of error state.
*
* Return: 0 on success or a negative error code on failure.
*/
int xe_sriov_vfio_error(struct xe_device *xe, unsigned int vfid);
/**
* xe_sriov_vfio_data_read() - Read migration data from the VF device.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
* @buf: start address of userspace buffer
* @len: requested read size from userspace
*
* Return: number of bytes that has been successfully read,
* 0 if no more migration data is available, -errno on failure.
*/
ssize_t xe_sriov_vfio_data_read(struct xe_device *xe, unsigned int vfid,
char __user *buf, size_t len);
/**
* xe_sriov_vfio_data_write() - Write migration data to the VF device.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
* @buf: start address of userspace buffer
* @len: requested write size from userspace
*
* Return: number of bytes that has been successfully written, -errno on failure.
*/
ssize_t xe_sriov_vfio_data_write(struct xe_device *xe, unsigned int vfid,
const char __user *buf, size_t len);
/**
* xe_sriov_vfio_stop_copy_size() - Get a size estimate of VF device migration data.
* @xe: the PF &xe_device obtained by calling xe_sriov_vfio_get_pf()
* @vfid: the VF identifier (can't be 0)
*
* Return: migration data size in bytes or a negative error code on failure.
*/
ssize_t xe_sriov_vfio_stop_copy_size(struct xe_device *xe, unsigned int vfid);
#endif