Resguardo inicial

linux-7.2.3/include/dt-bindings/arm/coresight-cti-dt.h

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the defined trigger signal
+ * types on CoreSight CTI.
+ */
+
+#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
+#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
+
+#define GEN_IO		0
+#define GEN_INTREQ	1
+#define GEN_INTACK	2
+#define GEN_HALTREQ	3
+#define GEN_RESTARTREQ	4
+#define PE_EDBGREQ	5
+#define PE_DBGRESTART	6
+#define PE_CTIIRQ	7
+#define PE_PMUIRQ	8
+#define PE_DBGTRIGGER	9
+#define ETM_EXTOUT	10
+#define ETM_EXTIN	11
+#define SNK_FULL	12
+#define SNK_ACQCOMP	13
+#define SNK_FLUSHCOMP	14
+#define SNK_FLUSHIN	15
+#define SNK_TRIGIN	16
+#define STM_ASYNCOUT	17
+#define STM_TOUT_SPTE	18
+#define STM_TOUT_SW	19
+#define STM_TOUT_HETE	20
+#define STM_HWEVENT	21
+#define ELA_TSTART	22
+#define ELA_TSTOP	23
+#define ELA_DBGREQ	24
+#define CTI_TRIG_MAX	25
+
+#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */

linux-7.2.3/include/dt-bindings/arm/mhuv3-dt.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for the defined MHUv3 types.
+ */
+
+#ifndef _DT_BINDINGS_ARM_MHUV3_DT_H
+#define _DT_BINDINGS_ARM_MHUV3_DT_H
+
+#define DBE_EXT		0
+#define FCE_EXT		1
+#define FE_EXT		2
+
+#endif /* _DT_BINDINGS_ARM_MHUV3_DT_H */

linux-7.2.3/include/dt-bindings/arm/qcom,ids.h

@@ -0,0 +1,331 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
+ */
+#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
+#define _DT_BINDINGS_ARM_QCOM_IDS_H
+
+/*
+ * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for
+ * older chipsets (qcom,msm-id) and in socinfo driver:
+ */
+#define QCOM_ID_MSM8260			70
+#define QCOM_ID_MSM8660			71
+#define QCOM_ID_APQ8060			86
+#define QCOM_ID_MSM8960			87
+#define QCOM_ID_APQ8064			109
+#define QCOM_ID_MSM8930			116
+#define QCOM_ID_MSM8630			117
+#define QCOM_ID_MSM8230			118
+#define QCOM_ID_APQ8030			119
+#define QCOM_ID_MSM8627			120
+#define QCOM_ID_MSM8227			121
+#define QCOM_ID_MSM8660A		122
+#define QCOM_ID_MSM8260A		123
+#define QCOM_ID_APQ8060A		124
+#define QCOM_ID_MSM8974			126
+#define QCOM_ID_MSM8225			127
+#define QCOM_ID_MSM8625			129
+#define QCOM_ID_MPQ8064			130
+#define QCOM_ID_MSM8960AB		138
+#define QCOM_ID_APQ8060AB		139
+#define QCOM_ID_MSM8260AB		140
+#define QCOM_ID_MSM8660AB		141
+#define QCOM_ID_MSM8930AA		142
+#define QCOM_ID_MSM8630AA		143
+#define QCOM_ID_MSM8230AA		144
+#define QCOM_ID_MSM8626			145
+#define QCOM_ID_MSM8610			147
+#define QCOM_ID_APQ8064AB		153
+#define QCOM_ID_MSM8930AB		154
+#define QCOM_ID_MSM8630AB		155
+#define QCOM_ID_MSM8230AB		156
+#define QCOM_ID_APQ8030AB		157
+#define QCOM_ID_MSM8226			158
+#define QCOM_ID_MSM8526			159
+#define QCOM_ID_APQ8030AA		160
+#define QCOM_ID_MSM8110			161
+#define QCOM_ID_MSM8210			162
+#define QCOM_ID_MSM8810			163
+#define QCOM_ID_MSM8212			164
+#define QCOM_ID_MSM8612			165
+#define QCOM_ID_MSM8112			166
+#define QCOM_ID_MSM8125			167
+#define QCOM_ID_MSM8225Q		168
+#define QCOM_ID_MSM8625Q		169
+#define QCOM_ID_MSM8125Q		170
+#define QCOM_ID_APQ8064AA		172
+#define QCOM_ID_APQ8084			178
+#define QCOM_ID_MSM8130			179
+#define QCOM_ID_MSM8130AA		180
+#define QCOM_ID_MSM8130AB		181
+#define QCOM_ID_MSM8627AA		182
+#define QCOM_ID_MSM8227AA		183
+#define QCOM_ID_APQ8074			184
+#define QCOM_ID_MSM8274			185
+#define QCOM_ID_MSM8674			186
+#define QCOM_ID_MDM9635			187
+#define QCOM_ID_MSM8974PRO_AC		194
+#define QCOM_ID_MSM8126			198
+#define QCOM_ID_APQ8026			199
+#define QCOM_ID_MSM8926			200
+#define QCOM_ID_IPQ8062			201
+#define QCOM_ID_IPQ8064			202
+#define QCOM_ID_IPQ8066			203
+#define QCOM_ID_IPQ8068			204
+#define QCOM_ID_MSM8326			205
+#define QCOM_ID_MSM8916			206
+#define QCOM_ID_MSM8994			207
+#define QCOM_ID_APQ8074PRO_AA		208
+#define QCOM_ID_APQ8074PRO_AB		209
+#define QCOM_ID_APQ8074PRO_AC		210
+#define QCOM_ID_MSM8274PRO_AA		211
+#define QCOM_ID_MSM8274PRO_AB		212
+#define QCOM_ID_MSM8274PRO_AC		213
+#define QCOM_ID_MSM8674PRO_AA		214
+#define QCOM_ID_MSM8674PRO_AB		215
+#define QCOM_ID_MSM8674PRO_AC		216
+#define QCOM_ID_MSM8974PRO_AA		217
+#define QCOM_ID_MSM8974PRO_AB		218
+#define QCOM_ID_APQ8028			219
+#define QCOM_ID_MSM8128			220
+#define QCOM_ID_MSM8228			221
+#define QCOM_ID_MSM8528			222
+#define QCOM_ID_MSM8628			223
+#define QCOM_ID_MSM8928			224
+#define QCOM_ID_MSM8510			225
+#define QCOM_ID_MSM8512			226
+#define QCOM_ID_MSM8936			233
+#define QCOM_ID_MDM9640			234
+#define QCOM_ID_MSM8939			239
+#define QCOM_ID_APQ8036			240
+#define QCOM_ID_APQ8039			241
+#define QCOM_ID_MSM8236			242
+#define QCOM_ID_MSM8636			243
+#define QCOM_ID_MSM8909			245
+#define QCOM_ID_MSM8996			246
+#define QCOM_ID_APQ8016			247
+#define QCOM_ID_MSM8216			248
+#define QCOM_ID_MSM8116			249
+#define QCOM_ID_MSM8616			250
+#define QCOM_ID_MSM8992			251
+#define QCOM_ID_APQ8092			252
+#define QCOM_ID_APQ8094			253
+#define QCOM_ID_MSM8209			258
+#define QCOM_ID_MSM8208			259
+#define QCOM_ID_MDM9209			260
+#define QCOM_ID_MDM9309			261
+#define QCOM_ID_MDM9609			262
+#define QCOM_ID_MSM8239			263
+#define QCOM_ID_MSM8952			264
+#define QCOM_ID_APQ8009			265
+#define QCOM_ID_MSM8956			266
+#define QCOM_ID_MSM8929			268
+#define QCOM_ID_MSM8629			269
+#define QCOM_ID_MSM8229			270
+#define QCOM_ID_APQ8029			271
+#define QCOM_ID_APQ8056			274
+#define QCOM_ID_MSM8609			275
+#define QCOM_ID_APQ8076			277
+#define QCOM_ID_MSM8976			278
+#define QCOM_ID_MDM9650			279
+#define QCOM_ID_IPQ8065			280
+#define QCOM_ID_IPQ8069			281
+#define QCOM_ID_MDM9655			283
+#define QCOM_ID_MDM9250			284
+#define QCOM_ID_MDM9255			285
+#define QCOM_ID_MDM9350			286
+#define QCOM_ID_APQ8052			289
+#define QCOM_ID_MDM9607			290
+#define QCOM_ID_APQ8096			291
+#define QCOM_ID_MSM8998			292
+#define QCOM_ID_MSM8953			293
+#define QCOM_ID_MSM8937			294
+#define QCOM_ID_APQ8037			295
+#define QCOM_ID_MDM8207			296
+#define QCOM_ID_MDM9207			297
+#define QCOM_ID_MDM9307			298
+#define QCOM_ID_MDM9628			299
+#define QCOM_ID_MSM8909W		300
+#define QCOM_ID_APQ8009W		301
+#define QCOM_ID_MSM8996L		302
+#define QCOM_ID_MSM8917			303
+#define QCOM_ID_APQ8053			304
+#define QCOM_ID_MSM8996SG		305
+#define QCOM_ID_APQ8017			307
+#define QCOM_ID_MSM8217			308
+#define QCOM_ID_MSM8617			309
+#define QCOM_ID_MSM8996AU		310
+#define QCOM_ID_APQ8096AU		311
+#define QCOM_ID_APQ8096SG		312
+#define QCOM_ID_MSM8940			313
+#define QCOM_ID_SDX201			314
+#define QCOM_ID_SDM660			317
+#define QCOM_ID_SDM630			318
+#define QCOM_ID_APQ8098			319
+#define QCOM_ID_MSM8920			320
+#define QCOM_ID_SDM845			321
+#define QCOM_ID_MDM9206			322
+#define QCOM_ID_IPQ8074			323
+#define QCOM_ID_SDA660			324
+#define QCOM_ID_SDM658			325
+#define QCOM_ID_SDA658			326
+#define QCOM_ID_SDA630			327
+#define QCOM_ID_MSM8905			331
+#define QCOM_ID_SDX202			333
+#define QCOM_ID_SDM670			336
+#define QCOM_ID_SDM450			338
+#define QCOM_ID_SM8150			339
+#define QCOM_ID_SDA845			341
+#define QCOM_ID_IPQ8072			342
+#define QCOM_ID_IPQ8076			343
+#define QCOM_ID_IPQ8078			344
+#define QCOM_ID_SDM636			345
+#define QCOM_ID_SDA636			346
+#define QCOM_ID_SDM632			349
+#define QCOM_ID_SDA632			350
+#define QCOM_ID_SDA450			351
+#define QCOM_ID_SDM439			353
+#define QCOM_ID_SDM429			354
+#define QCOM_ID_SM8250			356
+#define QCOM_ID_SA8155			362
+#define QCOM_ID_SDA439			363
+#define QCOM_ID_SDA429			364
+#define QCOM_ID_SM7150			365
+#define QCOM_ID_SM7150P			366
+#define QCOM_ID_IPQ8070			375
+#define QCOM_ID_IPQ8071			376
+#define QCOM_ID_QM215			386
+#define QCOM_ID_IPQ8072A		389
+#define QCOM_ID_IPQ8074A		390
+#define QCOM_ID_IPQ8076A		391
+#define QCOM_ID_IPQ8078A		392
+#define QCOM_ID_SM6125			394
+#define QCOM_ID_IPQ8070A		395
+#define QCOM_ID_IPQ8071A		396
+#define QCOM_ID_IPQ8172			397
+#define QCOM_ID_IPQ8173			398
+#define QCOM_ID_IPQ8174			399
+#define QCOM_ID_IPQ6018			402
+#define QCOM_ID_IPQ6028			403
+#define QCOM_ID_SDM429W			416
+#define QCOM_ID_SM4250			417
+#define QCOM_ID_IPQ6000			421
+#define QCOM_ID_IPQ6010			422
+#define QCOM_ID_SC7180			425
+#define QCOM_ID_SM6350			434
+#define QCOM_ID_QCM2150			436
+#define QCOM_ID_SDA429W			437
+#define QCOM_ID_SM8350			439
+#define QCOM_ID_QCM2290			441
+#define QCOM_ID_SM7125			443
+#define QCOM_ID_SM6115			444
+#define QCOM_ID_IPQ5010			446
+#define QCOM_ID_IPQ5018			447
+#define QCOM_ID_IPQ5028			448
+#define QCOM_ID_SC8280XP		449
+#define QCOM_ID_IPQ6005			453
+#define QCOM_ID_QRB5165			455
+#define QCOM_ID_SM8450			457
+#define QCOM_ID_SM7225			459
+#define QCOM_ID_SA8295P			460
+#define QCOM_ID_SA8540P			461
+#define QCOM_ID_QCM4290			469
+#define QCOM_ID_QCS4290			470
+#define QCOM_ID_SM7325			475
+#define QCOM_ID_SM8450_2		480
+#define QCOM_ID_SM8450_3		482
+#define QCOM_ID_SC7280			487
+#define QCOM_ID_SC7180P			495
+#define QCOM_ID_QCM6490			497
+#define QCOM_ID_QCS6490			498
+#define QCOM_ID_SM7325P			499
+#define QCOM_ID_IPQ5000			503
+#define QCOM_ID_IPQ0509			504
+#define QCOM_ID_IPQ0518			505
+#define QCOM_ID_SM7450			506
+#define QCOM_ID_SM6375			507
+#define QCOM_ID_IPQ9514			510
+#define QCOM_ID_IPQ9550			511
+#define QCOM_ID_IPQ9554			512
+#define QCOM_ID_IPQ9570			513
+#define QCOM_ID_IPQ9574			514
+#define QCOM_ID_SM8550			519
+#define QCOM_ID_IPQ5016			520
+#define QCOM_ID_IPQ9510			521
+#define QCOM_ID_QRB4210			523
+#define QCOM_ID_QRB2210			524
+#define QCOM_ID_SAR2130P		525
+#define QCOM_ID_SM8475			530
+#define QCOM_ID_SM8475P			531
+#define QCOM_ID_SA8255P			532
+#define QCOM_ID_SA8650P			533
+#define QCOM_ID_SA8775P			534
+#define QCOM_ID_QRU1000			539
+#define QCOM_ID_SM8475_2		540
+#define QCOM_ID_QDU1000			545
+#define QCOM_ID_SM7450P			547
+#define QCOM_ID_X1E80100		555
+#define QCOM_ID_SM8650			557
+#define QCOM_ID_SM4450			568
+#define QCOM_ID_SAR1130P		579
+#define QCOM_ID_QDU1010			587
+#define QCOM_ID_QRU1032			588
+#define QCOM_ID_QRU1052			589
+#define QCOM_ID_QRU1062			590
+#define QCOM_ID_IPQ5332			592
+#define QCOM_ID_IPQ5322			593
+#define QCOM_ID_IPQ5312			594
+#define QCOM_ID_IPQ5302			595
+#define QCOM_ID_QCS8550			603
+#define QCOM_ID_QCM8550			604
+#define QCOM_ID_SM8750			618
+#define QCOM_ID_IPQ5300			624
+#define QCOM_ID_SM7635			636
+#define QCOM_ID_SM6650			640
+#define QCOM_ID_SM6650P			641
+#define QCOM_ID_IPQ5321			650
+#define QCOM_ID_IPQ5424			651
+#define QCOM_ID_QCM6690			657
+#define QCOM_ID_QCS6690			658
+#define QCOM_ID_SM7750			659
+#define QCOM_ID_SM8850			660
+#define QCOM_ID_IPQ5404			671
+#define QCOM_ID_QCS9100			667
+#define QCOM_ID_QCS8300			674
+#define QCOM_ID_QCS8275			675
+#define QCOM_ID_QCS9075			676
+#define QCOM_ID_QCS615			680
+#define QCOM_ID_SA8797P			690
+#define QCOM_ID_CQ7790M			731
+#define QCOM_ID_CQ7790S			732
+#define QCOM_ID_CQ2390M			756
+#define QCOM_ID_CQ2390S			758
+#define QCOM_ID_IQ2390S			759
+#define QCOM_ID_IPQ5200			765
+#define QCOM_ID_IPQ5210			766
+#define QCOM_ID_QCF2200			767
+#define QCOM_ID_QCF3200			768
+#define QCOM_ID_QCF3210			769
+#define QCOM_ID_IPQ9620			770
+#define QCOM_ID_IPQ9650			771
+#define QCOM_ID_IPQ9610			778
+#define QCOM_ID_IPQ9630			779
+#define QCOM_ID_IPQ9640			780
+#define QCOM_ID_IPQ9670			781
+
+/*
+ * The board type and revision information, used by Qualcomm bootloaders and
+ * DTS for older chipsets (qcom,board-id):
+ */
+#define QCOM_BOARD_ID(a, major, minor) \
+	(((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BOARD_ID_##a)
+
+#define QCOM_BOARD_ID_MTP			8
+#define QCOM_BOARD_ID_DRAGONBOARD		10
+#define QCOM_BOARD_ID_QRD			11
+#define QCOM_BOARD_ID_SBC			24
+
+#endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */

linux-7.2.3/include/dt-bindings/arm/ux500_pm_domains.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ */
+#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+
+#define DOMAIN_VAPE		0
+
+/* Number of PM domains. */
+#define NR_DOMAINS		(DOMAIN_VAPE + 1)
+
+#endif

linux-7.2.3/include/dt-bindings/ata/ahci.h

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * This header provides constants for most AHCI bindings.
+ */
+
+#ifndef _DT_BINDINGS_ATA_AHCI_H
+#define _DT_BINDINGS_ATA_AHCI_H
+
+/* Host Bus Adapter generic platform capabilities */
+#define HBA_SSS		(1 << 27)
+#define HBA_SMPS	(1 << 28)
+
+/* Host Bus Adapter port-specific platform capabilities */
+#define HBA_PORT_HPCP	(1 << 18)
+#define HBA_PORT_MPSP	(1 << 19)
+#define HBA_PORT_CPD	(1 << 20)
+#define HBA_PORT_ESP	(1 << 21)
+#define HBA_PORT_FBSCP	(1 << 22)
+
+#endif

linux-7.2.3/include/dt-bindings/bus/moxtet.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Constant for device tree bindings for Turris Mox module configuration bus
+ *
+ * Copyright (C) 2019 Marek Behún <kabel@kernel.org>
+ */
+
+#ifndef _DT_BINDINGS_BUS_MOXTET_H
+#define _DT_BINDINGS_BUS_MOXTET_H
+
+#define MOXTET_IRQ_PCI		0
+#define MOXTET_IRQ_USB3		4
+#define MOXTET_IRQ_PERIDOT(n)	(8 + (n))
+#define MOXTET_IRQ_TOPAZ	12
+
+#endif /* _DT_BINDINGS_BUS_MOXTET_H */

linux-7.2.3/include/dt-bindings/bus/ti-sysc.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* TI sysc interconnect target module defines */
+
+/* Generic sysc found on omap2 and later, also known as type1 */
+#define SYSC_OMAP2_CLOCKACTIVITY	(3 << 8)
+#define SYSC_OMAP2_EMUFREE		(1 << 5)
+#define SYSC_OMAP2_ENAWAKEUP		(1 << 2)
+#define SYSC_OMAP2_SOFTRESET		(1 << 1)
+#define SYSC_OMAP2_AUTOIDLE		(1 << 0)
+
+/* Generic sysc found on omap4 and later, also known as type2 */
+#define SYSC_OMAP4_DMADISABLE		(1 << 16)
+#define SYSC_OMAP4_FREEEMU		(1 << 1)	/* Also known as EMUFREE */
+#define SYSC_OMAP4_SOFTRESET		(1 << 0)
+
+/* SmartReflex sysc found on 36xx and later */
+#define SYSC_OMAP3_SR_ENAWAKEUP		(1 << 26)
+
+#define SYSC_DRA7_MCAN_ENAWAKEUP	(1 << 4)
+
+/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */
+#define SYSC_PRUSS_SUB_MWAIT		(1 << 5)
+#define SYSC_PRUSS_STANDBY_INIT		(1 << 4)
+
+/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
+#define SYSC_IDLE_FORCE			0
+#define SYSC_IDLE_NO			1
+#define SYSC_IDLE_SMART			2
+#define SYSC_IDLE_SMART_WKUP		3

linux-7.2.3/include/dt-bindings/clock/actions,s500-cmu.h

@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Actions Semi S500 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Copyright (c) 2018 LSI-TEC - Caninos Loucos
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H
+#define __DT_BINDINGS_CLOCK_S500_CMU_H
+
+#define CLK_NONE		0
+
+/* fixed rate clocks */
+#define CLK_LOSC		1
+#define CLK_HOSC		2
+
+/* pll clocks */
+#define CLK_CORE_PLL		3
+#define CLK_DEV_PLL		4
+#define CLK_DDR_PLL		5
+#define CLK_NAND_PLL		6
+#define CLK_DISPLAY_PLL		7
+#define CLK_ETHERNET_PLL	8
+#define CLK_AUDIO_PLL		9
+
+/* system clock */
+#define CLK_DEV			10
+#define CLK_H			11
+#define CLK_AHBPREDIV		12
+#define CLK_AHB			13
+#define CLK_DE			14
+#define CLK_BISP		15
+#define CLK_VCE			16
+#define CLK_VDE			17
+
+/* peripheral device clock */
+#define CLK_TIMER		18
+#define CLK_I2C0		19
+#define CLK_I2C1		20
+#define CLK_I2C2		21
+#define CLK_I2C3		22
+#define CLK_PWM0		23
+#define CLK_PWM1		24
+#define CLK_PWM2		25
+#define CLK_PWM3		26
+#define CLK_PWM4		27
+#define CLK_PWM5		28
+#define CLK_SD0			29
+#define CLK_SD1			30
+#define CLK_SD2			31
+#define CLK_SENSOR0		32
+#define CLK_SENSOR1		33
+#define CLK_SPI0		34
+#define CLK_SPI1		35
+#define CLK_SPI2		36
+#define CLK_SPI3		37
+#define CLK_UART0		38
+#define CLK_UART1		39
+#define CLK_UART2		40
+#define CLK_UART3		41
+#define CLK_UART4		42
+#define CLK_UART5		43
+#define CLK_UART6		44
+#define CLK_DE1			45
+#define CLK_DE2			46
+#define CLK_I2SRX		47
+#define CLK_I2STX		48
+#define CLK_HDMI_AUDIO		49
+#define CLK_HDMI		50
+#define CLK_SPDIF		51
+#define CLK_NAND		52
+#define CLK_ECC			53
+#define CLK_RMII_REF		54
+#define CLK_GPIO		55
+
+/* additional clocks */
+#define CLK_APB			56
+#define CLK_DMAC		57
+#define CLK_NIC			58
+#define CLK_ETHERNET		59
+
+#define CLK_NR_CLKS		(CLK_ETHERNET + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */

linux-7.2.3/include/dt-bindings/clock/actions,s700-cmu.h

@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Device Tree binding constants for Actions Semi S700 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Author: Pathiban Nallathambi <pn@denx.de>
+ * Author: Saravanan Sekar <sravanhome@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE			0
+
+/* pll clocks */
+#define CLK_CORE_PLL			1
+#define CLK_DEV_PLL			2
+#define CLK_DDR_PLL			3
+#define CLK_NAND_PLL			4
+#define CLK_DISPLAY_PLL			5
+#define CLK_TVOUT_PLL			6
+#define CLK_CVBS_PLL			7
+#define CLK_AUDIO_PLL			8
+#define CLK_ETHERNET_PLL		9
+
+/* system clock */
+#define CLK_CPU				10
+#define CLK_DEV				11
+#define CLK_AHB				12
+#define CLK_APB				13
+#define CLK_DMAC			14
+#define CLK_NOC0_CLK_MUX		15
+#define CLK_NOC1_CLK_MUX		16
+#define CLK_HP_CLK_MUX			17
+#define CLK_HP_CLK_DIV			18
+#define CLK_NOC1_CLK_DIV		19
+#define CLK_NOC0			20
+#define CLK_NOC1			21
+#define CLK_SENOR_SRC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+#define CLK_TIMER			24
+#define CLK_DSI				25
+#define CLK_CSI				26
+#define CLK_SI				27
+#define CLK_DE				28
+#define CLK_HDE				29
+#define CLK_VDE				30
+#define CLK_VCE				31
+#define CLK_NAND			32
+#define CLK_SD0				33
+#define CLK_SD1				34
+#define CLK_SD2				35
+
+#define CLK_UART0			36
+#define CLK_UART1			37
+#define CLK_UART2			38
+#define CLK_UART3			39
+#define CLK_UART4			40
+#define CLK_UART5			41
+#define CLK_UART6			42
+
+#define CLK_PWM0			43
+#define CLK_PWM1			44
+#define CLK_PWM2			45
+#define CLK_PWM3			46
+#define CLK_PWM4			47
+#define CLK_PWM5			48
+#define CLK_GPU3D			49
+
+#define CLK_I2C0			50
+#define CLK_I2C1			51
+#define CLK_I2C2			52
+#define CLK_I2C3			53
+
+#define CLK_SPI0			54
+#define CLK_SPI1			55
+#define CLK_SPI2			56
+#define CLK_SPI3			57
+
+#define CLK_USB3_480MPLL0		58
+#define CLK_USB3_480MPHY0		59
+#define CLK_USB3_5GPHY			60
+#define CLK_USB3_CCE			61
+#define CLK_USB3_MAC			62
+
+#define CLK_LCD				63
+#define CLK_HDMI_AUDIO			64
+#define CLK_I2SRX			65
+#define CLK_I2STX			66
+
+#define CLK_SENSOR0			67
+#define CLK_SENSOR1			68
+
+#define CLK_HDMI_DEV			69
+
+#define CLK_ETHERNET			70
+#define CLK_RMII_REF			71
+
+#define CLK_USB2H0_PLLEN		72
+#define CLK_USB2H0_PHY			73
+#define CLK_USB2H0_CCE			74
+#define CLK_USB2H1_PLLEN		75
+#define CLK_USB2H1_PHY			76
+#define CLK_USB2H1_CCE			77
+
+#define CLK_TVOUT			78
+
+#define CLK_THERMAL_SENSOR		79
+
+#define CLK_IRC_SWITCH			80
+#define CLK_PCM1			81
+#define CLK_NR_CLKS			(CLK_PCM1 + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */

linux-7.2.3/include/dt-bindings/clock/actions,s900-cmu.h

@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE			0
+
+/* fixed rate clocks */
+#define CLK_LOSC			1
+#define CLK_HOSC			2
+
+/* pll clocks */
+#define CLK_CORE_PLL			3
+#define CLK_DEV_PLL			4
+#define CLK_DDR_PLL			5
+#define CLK_NAND_PLL			6
+#define CLK_DISPLAY_PLL			7
+#define CLK_DSI_PLL			8
+#define CLK_ASSIST_PLL			9
+#define CLK_AUDIO_PLL			10
+
+/* system clock */
+#define CLK_CPU				15
+#define CLK_DEV				16
+#define CLK_NOC				17
+#define CLK_NOC_MUX			18
+#define CLK_NOC_DIV			19
+#define CLK_AHB				20
+#define CLK_APB				21
+#define CLK_DMAC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+
+#define CLK_BISP			24
+#define CLK_CSI0			25
+#define CLK_CSI1			26
+
+#define CLK_DE0				27
+#define CLK_DE1				28
+#define CLK_DE2				29
+#define CLK_DE3				30
+#define CLK_DSI				32
+
+#define CLK_GPU				33
+#define CLK_GPU_CORE			34
+#define CLK_GPU_MEM			35
+#define CLK_GPU_SYS			36
+
+#define CLK_HDE				37
+#define CLK_I2C0			38
+#define CLK_I2C1			39
+#define CLK_I2C2			40
+#define CLK_I2C3			41
+#define CLK_I2C4			42
+#define CLK_I2C5			43
+#define CLK_I2SRX			44
+#define CLK_I2STX			45
+#define CLK_IMX				46
+#define CLK_LCD				47
+#define CLK_NAND0			48
+#define CLK_NAND1			49
+#define CLK_PWM0			50
+#define CLK_PWM1			51
+#define CLK_PWM2			52
+#define CLK_PWM3			53
+#define CLK_PWM4			54
+#define CLK_PWM5			55
+#define CLK_SD0				56
+#define CLK_SD1				57
+#define CLK_SD2				58
+#define CLK_SD3				59
+#define CLK_SENSOR			60
+#define CLK_SPEED_SENSOR		61
+#define CLK_SPI0			62
+#define CLK_SPI1			63
+#define CLK_SPI2			64
+#define CLK_SPI3			65
+#define CLK_THERMAL_SENSOR		66
+#define CLK_UART0			67
+#define CLK_UART1			68
+#define CLK_UART2			69
+#define CLK_UART3			70
+#define CLK_UART4			71
+#define CLK_UART5			72
+#define CLK_UART6			73
+#define CLK_VCE				74
+#define CLK_VDE				75
+
+#define CLK_USB3_480MPLL0		76
+#define CLK_USB3_480MPHY0		77
+#define CLK_USB3_5GPHY			78
+#define CLK_USB3_CCE			79
+#define CLK_USB3_MAC			80
+
+#define CLK_TIMER			83
+
+#define CLK_HDMI_AUDIO			84
+
+#define CLK_24M				85
+
+#define CLK_EDP				86
+
+#define CLK_24M_EDP			87
+#define CLK_EDP_PLL			88
+#define CLK_EDP_LINK			89
+
+#define CLK_USB2H0_PLLEN		90
+#define CLK_USB2H0_PHY			91
+#define CLK_USB2H0_CCE			92
+#define CLK_USB2H1_PLLEN		93
+#define CLK_USB2H1_PHY			94
+#define CLK_USB2H1_CCE			95
+
+#define CLK_DDR0			96
+#define CLK_DDR1			97
+#define CLK_DMM				98
+
+#define CLK_ETH_MAC			99
+#define CLK_RMII_REF			100
+
+#define CLK_NR_CLKS			(CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */

linux-7.2.3/include/dt-bindings/clock/agilex-clock.h

@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC1			0
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK	1
+#define AGILEX_CB_INTOSC_LS_CLK		2
+#define AGILEX_L4_SYS_FREE_CLK		3
+#define AGILEX_F2S_FREE_CLK		4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK		5
+#define AGILEX_MAIN_PLL_C0_CLK		6
+#define AGILEX_MAIN_PLL_C1_CLK		7
+#define AGILEX_MAIN_PLL_C2_CLK		8
+#define AGILEX_MAIN_PLL_C3_CLK		9
+#define AGILEX_PERIPH_PLL_CLK		10
+#define AGILEX_PERIPH_PLL_C0_CLK	11
+#define AGILEX_PERIPH_PLL_C1_CLK	12
+#define AGILEX_PERIPH_PLL_C2_CLK	13
+#define AGILEX_PERIPH_PLL_C3_CLK	14
+#define AGILEX_MPU_FREE_CLK		15
+#define AGILEX_MPU_CCU_CLK		16
+#define AGILEX_BOOT_CLK			17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK		18
+#define AGILEX_NOC_FREE_CLK		19
+#define AGILEX_S2F_USR0_CLK		20
+#define AGILEX_NOC_CLK			21
+#define AGILEX_EMAC_A_FREE_CLK		22
+#define AGILEX_EMAC_B_FREE_CLK		23
+#define AGILEX_EMAC_PTP_FREE_CLK	24
+#define AGILEX_GPIO_DB_FREE_CLK		25
+#define AGILEX_SDMMC_FREE_CLK		26
+#define AGILEX_S2F_USER0_FREE_CLK	27
+#define AGILEX_S2F_USER1_FREE_CLK	28
+#define AGILEX_PSI_REF_FREE_CLK		29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK			30
+#define AGILEX_MPU_L2RAM_CLK		31
+#define AGILEX_MPU_PERIPH_CLK		32
+#define AGILEX_L4_MAIN_CLK		33
+#define AGILEX_L4_MP_CLK		34
+#define AGILEX_L4_SP_CLK		35
+#define AGILEX_CS_AT_CLK		36
+#define AGILEX_CS_TRACE_CLK		37
+#define AGILEX_CS_PDBG_CLK		38
+#define AGILEX_CS_TIMER_CLK		39
+#define AGILEX_S2F_USER0_CLK		40
+#define AGILEX_EMAC0_CLK		41
+#define AGILEX_EMAC1_CLK		43
+#define AGILEX_EMAC2_CLK		44
+#define AGILEX_EMAC_PTP_CLK		45
+#define AGILEX_GPIO_DB_CLK		46
+#define AGILEX_NAND_CLK			47
+#define AGILEX_PSI_REF_CLK		48
+#define AGILEX_S2F_USER1_CLK		49
+#define AGILEX_SDMMC_CLK		50
+#define AGILEX_SPI_M_CLK		51
+#define AGILEX_USB_CLK			52
+#define AGILEX_NAND_X_CLK		53
+#define AGILEX_NAND_ECC_CLK		54
+#define AGILEX_NUM_CLKS			55
+
+#endif	/* __AGILEX_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/alphascale,asm9260.h

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ASM9260_H
+#define _DT_BINDINGS_CLK_ASM9260_H
+
+/* ahb gate */
+#define CLKID_AHB_ROM		0
+#define CLKID_AHB_RAM		1
+#define CLKID_AHB_GPIO		2
+#define CLKID_AHB_MAC		3
+#define CLKID_AHB_EMI		4
+#define CLKID_AHB_USB0		5
+#define CLKID_AHB_USB1		6
+#define CLKID_AHB_DMA0		7
+#define CLKID_AHB_DMA1		8
+#define CLKID_AHB_UART0		9
+#define CLKID_AHB_UART1		10
+#define CLKID_AHB_UART2		11
+#define CLKID_AHB_UART3		12
+#define CLKID_AHB_UART4		13
+#define CLKID_AHB_UART5		14
+#define CLKID_AHB_UART6		15
+#define CLKID_AHB_UART7		16
+#define CLKID_AHB_UART8		17
+#define CLKID_AHB_UART9		18
+#define CLKID_AHB_I2S0		19
+#define CLKID_AHB_I2C0		20
+#define CLKID_AHB_I2C1		21
+#define CLKID_AHB_SSP0		22
+#define CLKID_AHB_IOCONFIG	23
+#define CLKID_AHB_WDT		24
+#define CLKID_AHB_CAN0		25
+#define CLKID_AHB_CAN1		26
+#define CLKID_AHB_MPWM		27
+#define CLKID_AHB_SPI0		28
+#define CLKID_AHB_SPI1		29
+#define CLKID_AHB_QEI		30
+#define CLKID_AHB_QUADSPI0	31
+#define CLKID_AHB_CAMIF		32
+#define CLKID_AHB_LCDIF		33
+#define CLKID_AHB_TIMER0	34
+#define CLKID_AHB_TIMER1	35
+#define CLKID_AHB_TIMER2	36
+#define CLKID_AHB_TIMER3	37
+#define CLKID_AHB_IRQ		38
+#define CLKID_AHB_RTC		39
+#define CLKID_AHB_NAND		40
+#define CLKID_AHB_ADC0		41
+#define CLKID_AHB_LED		42
+#define CLKID_AHB_DAC0		43
+#define CLKID_AHB_LCD		44
+#define CLKID_AHB_I2S1		45
+#define CLKID_AHB_MAC1		46
+
+/* divider */
+#define CLKID_SYS_CPU		47
+#define CLKID_SYS_AHB		48
+#define CLKID_SYS_I2S0M		49
+#define CLKID_SYS_I2S0S		50
+#define CLKID_SYS_I2S1M		51
+#define CLKID_SYS_I2S1S		52
+#define CLKID_SYS_UART0		53
+#define CLKID_SYS_UART1		54
+#define CLKID_SYS_UART2		55
+#define CLKID_SYS_UART3		56
+#define CLKID_SYS_UART4		56
+#define CLKID_SYS_UART5		57
+#define CLKID_SYS_UART6		58
+#define CLKID_SYS_UART7		59
+#define CLKID_SYS_UART8		60
+#define CLKID_SYS_UART9		61
+#define CLKID_SYS_SPI0		62
+#define CLKID_SYS_SPI1		63
+#define CLKID_SYS_QUADSPI	64
+#define CLKID_SYS_SSP0		65
+#define CLKID_SYS_NAND		66
+#define CLKID_SYS_TRACE		67
+#define CLKID_SYS_CAMM		68
+#define CLKID_SYS_WDT		69
+#define CLKID_SYS_CLKOUT	70
+#define CLKID_SYS_MAC		71
+#define CLKID_SYS_LCD		72
+#define CLKID_SYS_ADCANA	73
+
+#define MAX_CLKS		74
+#endif

linux-7.2.3/include/dt-bindings/clock/am3.h

@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET	0x0
+#define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
+
+/* l4ls clocks */
+#define AM3_L4LS_CLKCTRL_OFFSET	0x38
+#define AM3_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4LS_CLKCTRL_OFFSET)
+#define AM3_L4LS_UART6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x38)
+#define AM3_L4LS_MMC1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x3c)
+#define AM3_L4LS_ELM_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x40)
+#define AM3_L4LS_I2C3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x44)
+#define AM3_L4LS_I2C2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x48)
+#define AM3_L4LS_SPI0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x4c)
+#define AM3_L4LS_SPI1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x50)
+#define AM3_L4LS_L4_LS_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x60)
+#define AM3_L4LS_UART2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x6c)
+#define AM3_L4LS_UART3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x70)
+#define AM3_L4LS_UART4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x74)
+#define AM3_L4LS_UART5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x78)
+#define AM3_L4LS_TIMER7_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x7c)
+#define AM3_L4LS_TIMER2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x80)
+#define AM3_L4LS_TIMER3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x84)
+#define AM3_L4LS_TIMER4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x88)
+#define AM3_L4LS_RNG_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x90)
+#define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
+#define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
+#define AM3_L4LS_GPIO4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
+#define AM3_L4LS_D_CAN0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc0)
+#define AM3_L4LS_D_CAN1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc4)
+#define AM3_L4LS_EPWMSS1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xcc)
+#define AM3_L4LS_EPWMSS0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd4)
+#define AM3_L4LS_EPWMSS2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd8)
+#define AM3_L4LS_TIMER5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xec)
+#define AM3_L4LS_TIMER6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf0)
+#define AM3_L4LS_MMC2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf4)
+#define AM3_L4LS_SPINLOCK_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x10c)
+#define AM3_L4LS_MAILBOX_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x110)
+#define AM3_L4LS_OCPWP_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x130)
+
+/* l3s clocks */
+#define AM3_L3S_CLKCTRL_OFFSET	0x1c
+#define AM3_L3S_CLKCTRL_INDEX(offset)	((offset) - AM3_L3S_CLKCTRL_OFFSET)
+#define AM3_L3S_USB_OTG_HS_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x1c)
+#define AM3_L3S_GPMC_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x30)
+#define AM3_L3S_MCASP0_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x34)
+#define AM3_L3S_MCASP1_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x68)
+#define AM3_L3S_MMC3_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0xf8)
+
+/* l3 clocks */
+#define AM3_L3_CLKCTRL_OFFSET	0x24
+#define AM3_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_CLKCTRL_OFFSET)
+#define AM3_L3_TPTC0_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x24)
+#define AM3_L3_EMIF_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x28)
+#define AM3_L3_OCMCRAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x2c)
+#define AM3_L3_AES_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x94)
+#define AM3_L3_SHAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xa0)
+#define AM3_L3_TPCC_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xbc)
+#define AM3_L3_L3_INSTR_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_L3_MAIN_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xe0)
+#define AM3_L3_TPTC1_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xfc)
+#define AM3_L3_TPTC2_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x100)
+
+/* l4hs clocks */
+#define AM3_L4HS_CLKCTRL_OFFSET	0x120
+#define AM3_L4HS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4HS_CLKCTRL_OFFSET)
+#define AM3_L4HS_L4_HS_CLKCTRL	AM3_L4HS_CLKCTRL_INDEX(0x120)
+
+/* pruss_ocp clocks */
+#define AM3_PRUSS_OCP_CLKCTRL_OFFSET	0xe8
+#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
+#define AM3_PRUSS_OCP_PRUSS_CLKCTRL	AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
+
+/* cpsw_125mhz clocks */
+#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM3_CLKCTRL_INDEX(0x14)
+
+/* lcdc clocks */
+#define AM3_LCDC_CLKCTRL_OFFSET	0x18
+#define AM3_LCDC_CLKCTRL_INDEX(offset)	((offset) - AM3_LCDC_CLKCTRL_OFFSET)
+#define AM3_LCDC_LCDC_CLKCTRL	AM3_LCDC_CLKCTRL_INDEX(0x18)
+
+/* clk_24mhz clocks */
+#define AM3_CLK_24MHZ_CLKCTRL_OFFSET	0x14c
+#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)	((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
+#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL	AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CONTROL_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+#define AM3_L4_WKUP_GPIO1_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_L4_WKUP_CLKCTRL	AM3_CLKCTRL_INDEX(0xc)
+#define AM3_L4_WKUP_UART1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb4)
+#define AM3_L4_WKUP_I2C1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb8)
+#define AM3_L4_WKUP_ADC_TSC_CLKCTRL	AM3_CLKCTRL_INDEX(0xbc)
+#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM3_CLKCTRL_INDEX(0xc0)
+#define AM3_L4_WKUP_TIMER1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc4)
+#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc8)
+#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL	AM3_CLKCTRL_INDEX(0xd4)
+
+/* l3_aon clocks */
+#define AM3_L3_AON_CLKCTRL_OFFSET	0x14
+#define AM3_L3_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
+#define AM3_L3_AON_DEBUGSS_CLKCTRL	AM3_L3_AON_CLKCTRL_INDEX(0x14)
+
+/* l4_wkup_aon clocks */
+#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET	0xb0
+#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
+#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
+
+/* mpu clocks */
+#define AM3_MPU_MPU_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_L4_RTC_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_GFX_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL	AM3_CLKCTRL_INDEX(0x20)
+
+#endif

linux-7.2.3/include/dt-bindings/clock/am4.h

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_AM4_H
+#define __DT_BINDINGS_CLK_AM4_H
+
+#define AM4_CLKCTRL_OFFSET	0x20
+#define AM4_CLKCTRL_INDEX(offset)	((offset) - AM4_CLKCTRL_OFFSET)
+
+/* l3s_tsc clocks */
+#define AM4_L3S_TSC_CLKCTRL_OFFSET	0x120
+#define AM4_L3S_TSC_CLKCTRL_INDEX(offset)	((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
+#define AM4_L3S_TSC_ADC_TSC_CLKCTRL	AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
+
+/* l4_wkup_aon clocks */
+#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET	0x228
+#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
+#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
+#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL	AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
+
+/* l4_wkup clocks */
+#define AM4_L4_WKUP_CLKCTRL_OFFSET	0x220
+#define AM4_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
+#define AM4_L4_WKUP_L4_WKUP_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
+#define AM4_L4_WKUP_TIMER1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
+#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
+#define AM4_L4_WKUP_I2C1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
+#define AM4_L4_WKUP_UART1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
+#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
+#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
+#define AM4_L4_WKUP_CONTROL_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
+#define AM4_L4_WKUP_GPIO1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
+
+/* mpu clocks */
+#define AM4_MPU_MPU_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* gfx_l3 clocks */
+#define AM4_GFX_L3_GFX_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_rtc clocks */
+#define AM4_L4_RTC_RTC_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* l3 clocks */
+#define AM4_L3_L3_MAIN_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+#define AM4_L3_AES_CLKCTRL	AM4_CLKCTRL_INDEX(0x28)
+#define AM4_L3_DES_CLKCTRL	AM4_CLKCTRL_INDEX(0x30)
+#define AM4_L3_L3_INSTR_CLKCTRL	AM4_CLKCTRL_INDEX(0x40)
+#define AM4_L3_OCMCRAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x50)
+#define AM4_L3_SHAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x58)
+#define AM4_L3_TPCC_CLKCTRL	AM4_CLKCTRL_INDEX(0x78)
+#define AM4_L3_TPTC0_CLKCTRL	AM4_CLKCTRL_INDEX(0x80)
+#define AM4_L3_TPTC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x88)
+#define AM4_L3_TPTC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x90)
+#define AM4_L3_L4_HS_CLKCTRL	AM4_CLKCTRL_INDEX(0xa0)
+
+/* l3s clocks */
+#define AM4_L3S_CLKCTRL_OFFSET	0x68
+#define AM4_L3S_CLKCTRL_INDEX(offset)	((offset) - AM4_L3S_CLKCTRL_OFFSET)
+#define AM4_L3S_VPFE0_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x68)
+#define AM4_L3S_VPFE1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x70)
+#define AM4_L3S_GPMC_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x220)
+#define AM4_L3S_ADC1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x230)
+#define AM4_L3S_MCASP0_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x238)
+#define AM4_L3S_MCASP1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x240)
+#define AM4_L3S_MMC3_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x248)
+#define AM4_L3S_QSPI_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x258)
+#define AM4_L3S_USB_OTG_SS0_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x260)
+#define AM4_L3S_USB_OTG_SS1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x268)
+
+/* pruss_ocp clocks */
+#define AM4_PRUSS_OCP_CLKCTRL_OFFSET	0x320
+#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
+#define AM4_PRUSS_OCP_PRUSS_CLKCTRL	AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
+
+/* l4ls clocks */
+#define AM4_L4LS_CLKCTRL_OFFSET	0x420
+#define AM4_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM4_L4LS_CLKCTRL_OFFSET)
+#define AM4_L4LS_L4_LS_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x420)
+#define AM4_L4LS_D_CAN0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x428)
+#define AM4_L4LS_D_CAN1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x430)
+#define AM4_L4LS_EPWMSS0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x438)
+#define AM4_L4LS_EPWMSS1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x440)
+#define AM4_L4LS_EPWMSS2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x448)
+#define AM4_L4LS_EPWMSS3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x450)
+#define AM4_L4LS_EPWMSS4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x458)
+#define AM4_L4LS_EPWMSS5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x460)
+#define AM4_L4LS_ELM_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x468)
+#define AM4_L4LS_GPIO2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x478)
+#define AM4_L4LS_GPIO3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x480)
+#define AM4_L4LS_GPIO4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x488)
+#define AM4_L4LS_GPIO5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x490)
+#define AM4_L4LS_GPIO6_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x498)
+#define AM4_L4LS_HDQ1W_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4a0)
+#define AM4_L4LS_I2C2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4a8)
+#define AM4_L4LS_I2C3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4b0)
+#define AM4_L4LS_MAILBOX_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4b8)
+#define AM4_L4LS_MMC1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4c0)
+#define AM4_L4LS_MMC2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4c8)
+#define AM4_L4LS_RNG_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4e0)
+#define AM4_L4LS_SPI0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x500)
+#define AM4_L4LS_SPI1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x508)
+#define AM4_L4LS_SPI2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x510)
+#define AM4_L4LS_SPI3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x518)
+#define AM4_L4LS_SPI4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x520)
+#define AM4_L4LS_SPINLOCK_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x528)
+#define AM4_L4LS_TIMER2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x530)
+#define AM4_L4LS_TIMER3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x538)
+#define AM4_L4LS_TIMER4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x540)
+#define AM4_L4LS_TIMER5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x548)
+#define AM4_L4LS_TIMER6_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x550)
+#define AM4_L4LS_TIMER7_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x558)
+#define AM4_L4LS_TIMER8_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x560)
+#define AM4_L4LS_TIMER9_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x568)
+#define AM4_L4LS_TIMER10_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x570)
+#define AM4_L4LS_TIMER11_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x578)
+#define AM4_L4LS_UART2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x580)
+#define AM4_L4LS_UART3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x588)
+#define AM4_L4LS_UART4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x590)
+#define AM4_L4LS_UART5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x598)
+#define AM4_L4LS_UART6_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x5a0)
+#define AM4_L4LS_OCP2SCP0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x5b8)
+#define AM4_L4LS_OCP2SCP1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x5c0)
+
+/* emif clocks */
+#define AM4_EMIF_CLKCTRL_OFFSET	0x720
+#define AM4_EMIF_CLKCTRL_INDEX(offset)	((offset) - AM4_EMIF_CLKCTRL_OFFSET)
+#define AM4_EMIF_EMIF_CLKCTRL	AM4_EMIF_CLKCTRL_INDEX(0x720)
+
+/* dss clocks */
+#define AM4_DSS_CLKCTRL_OFFSET	0xa20
+#define AM4_DSS_CLKCTRL_INDEX(offset)	((offset) - AM4_DSS_CLKCTRL_OFFSET)
+#define AM4_DSS_DSS_CORE_CLKCTRL	AM4_DSS_CLKCTRL_INDEX(0xa20)
+
+/* cpsw_125mhz clocks */
+#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET	0xb20
+#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset)	((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
+#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
+
+#endif

linux-7.2.3/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h

@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
+ */
+
+#ifndef __A1_PERIPHERALS_CLKC_H
+#define __A1_PERIPHERALS_CLKC_H
+
+#define CLKID_XTAL_IN		0
+#define CLKID_FIXPLL_IN		1
+#define CLKID_USB_PHY_IN	2
+#define CLKID_USB_CTRL_IN	3
+#define CLKID_HIFIPLL_IN	4
+#define CLKID_SYSPLL_IN		5
+#define CLKID_DDS_IN		6
+#define CLKID_SYS		7
+#define CLKID_CLKTREE		8
+#define CLKID_RESET_CTRL	9
+#define CLKID_ANALOG_CTRL	10
+#define CLKID_PWR_CTRL		11
+#define CLKID_PAD_CTRL		12
+#define CLKID_SYS_CTRL		13
+#define CLKID_TEMP_SENSOR	14
+#define CLKID_AM2AXI_DIV	15
+#define CLKID_SPICC_B		16
+#define CLKID_SPICC_A		17
+#define CLKID_MSR		18
+#define CLKID_AUDIO		19
+#define CLKID_JTAG_CTRL		20
+#define CLKID_SARADC_EN		21
+#define CLKID_PWM_EF		22
+#define CLKID_PWM_CD		23
+#define CLKID_PWM_AB		24
+#define CLKID_CEC		25
+#define CLKID_I2C_S		26
+#define CLKID_IR_CTRL		27
+#define CLKID_I2C_M_D		28
+#define CLKID_I2C_M_C		29
+#define CLKID_I2C_M_B		30
+#define CLKID_I2C_M_A		31
+#define CLKID_ACODEC		32
+#define CLKID_OTP		33
+#define CLKID_SD_EMMC_A		34
+#define CLKID_USB_PHY		35
+#define CLKID_USB_CTRL		36
+#define CLKID_SYS_DSPB		37
+#define CLKID_SYS_DSPA		38
+#define CLKID_DMA		39
+#define CLKID_IRQ_CTRL		40
+#define CLKID_NIC		41
+#define CLKID_GIC		42
+#define CLKID_UART_C		43
+#define CLKID_UART_B		44
+#define CLKID_UART_A		45
+#define CLKID_SYS_PSRAM		46
+#define CLKID_RSA		47
+#define CLKID_CORESIGHT		48
+#define CLKID_AM2AXI_VAD	49
+#define CLKID_AUDIO_VAD		50
+#define CLKID_AXI_DMC		51
+#define CLKID_AXI_PSRAM		52
+#define CLKID_RAMB		53
+#define CLKID_RAMA		54
+#define CLKID_AXI_SPIFC		55
+#define CLKID_AXI_NIC		56
+#define CLKID_AXI_DMA		57
+#define CLKID_CPU_CTRL		58
+#define CLKID_ROM		59
+#define CLKID_PROC_I2C		60
+#define CLKID_DSPA_SEL		61
+#define CLKID_DSPB_SEL		62
+#define CLKID_DSPA_EN		63
+#define CLKID_DSPA_EN_NIC	64
+#define CLKID_DSPB_EN		65
+#define CLKID_DSPB_EN_NIC	66
+#define CLKID_RTC		67
+#define CLKID_CECA_32K		68
+#define CLKID_CECB_32K		69
+#define CLKID_24M		70
+#define CLKID_12M		71
+#define CLKID_FCLK_DIV2_DIVN	72
+#define CLKID_GEN		73
+#define CLKID_SARADC_SEL	74
+#define CLKID_SARADC		75
+#define CLKID_PWM_A		76
+#define CLKID_PWM_B		77
+#define CLKID_PWM_C		78
+#define CLKID_PWM_D		79
+#define CLKID_PWM_E		80
+#define CLKID_PWM_F		81
+#define CLKID_SPICC		82
+#define CLKID_TS		83
+#define CLKID_SPIFC		84
+#define CLKID_USB_BUS		85
+#define CLKID_SD_EMMC		86
+#define CLKID_PSRAM		87
+#define CLKID_DMC		88
+#define CLKID_SYS_A_SEL		89
+#define CLKID_SYS_A_DIV		90
+#define CLKID_SYS_A		91
+#define CLKID_SYS_B_SEL		92
+#define CLKID_SYS_B_DIV		93
+#define CLKID_SYS_B		94
+#define CLKID_DSPA_A_SEL	95
+#define CLKID_DSPA_A_DIV	96
+#define CLKID_DSPA_A		97
+#define CLKID_DSPA_B_SEL	98
+#define CLKID_DSPA_B_DIV	99
+#define CLKID_DSPA_B		100
+#define CLKID_DSPB_A_SEL	101
+#define CLKID_DSPB_A_DIV	102
+#define CLKID_DSPB_A		103
+#define CLKID_DSPB_B_SEL	104
+#define CLKID_DSPB_B_DIV	105
+#define CLKID_DSPB_B		106
+#define CLKID_RTC_32K_IN	107
+#define CLKID_RTC_32K_DIV	108
+#define CLKID_RTC_32K_XTAL	109
+#define CLKID_RTC_32K_SEL	110
+#define CLKID_CECB_32K_IN	111
+#define CLKID_CECB_32K_DIV	112
+#define CLKID_CECB_32K_SEL_PRE	113
+#define CLKID_CECB_32K_SEL	114
+#define CLKID_CECA_32K_IN	115
+#define CLKID_CECA_32K_DIV	116
+#define CLKID_CECA_32K_SEL_PRE	117
+#define CLKID_CECA_32K_SEL	118
+#define CLKID_DIV2_PRE		119
+#define CLKID_24M_DIV2		120
+#define CLKID_GEN_SEL		121
+#define CLKID_GEN_DIV		122
+#define CLKID_SARADC_DIV	123
+#define CLKID_PWM_A_SEL		124
+#define CLKID_PWM_A_DIV		125
+#define CLKID_PWM_B_SEL		126
+#define CLKID_PWM_B_DIV		127
+#define CLKID_PWM_C_SEL		128
+#define CLKID_PWM_C_DIV		129
+#define CLKID_PWM_D_SEL		130
+#define CLKID_PWM_D_DIV		131
+#define CLKID_PWM_E_SEL		132
+#define CLKID_PWM_E_DIV		133
+#define CLKID_PWM_F_SEL		134
+#define CLKID_PWM_F_DIV		135
+#define CLKID_SPICC_SEL		136
+#define CLKID_SPICC_DIV		137
+#define CLKID_SPICC_SEL2	138
+#define CLKID_TS_DIV		139
+#define CLKID_SPIFC_SEL		140
+#define CLKID_SPIFC_DIV		141
+#define CLKID_SPIFC_SEL2	142
+#define CLKID_USB_BUS_SEL	143
+#define CLKID_USB_BUS_DIV	144
+#define CLKID_SD_EMMC_SEL	145
+#define CLKID_SD_EMMC_DIV	146
+#define CLKID_SD_EMMC_SEL2	147
+#define CLKID_PSRAM_SEL		148
+#define CLKID_PSRAM_DIV		149
+#define CLKID_PSRAM_SEL2	150
+#define CLKID_DMC_SEL		151
+#define CLKID_DMC_DIV		152
+#define CLKID_DMC_SEL2		153
+#define CLKID_SYS_PLL_DIV16	154
+
+#endif /* __A1_PERIPHERALS_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,a1-pll-clkc.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
+ */
+
+#ifndef __A1_PLL_CLKC_H
+#define __A1_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL_DCO	0
+#define CLKID_FIXED_PLL		1
+#define CLKID_FCLK_DIV2_DIV	2
+#define CLKID_FCLK_DIV3_DIV	3
+#define CLKID_FCLK_DIV5_DIV	4
+#define CLKID_FCLK_DIV7_DIV	5
+#define CLKID_FCLK_DIV2		6
+#define CLKID_FCLK_DIV3		7
+#define CLKID_FCLK_DIV5		8
+#define CLKID_FCLK_DIV7		9
+#define CLKID_HIFI_PLL		10
+#define CLKID_SYS_PLL		11
+
+#endif /* __A1_PLL_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h

@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_XTAL_CLKIN			0
+#define CLKID_RTC_32K_DIV			1
+#define CLKID_RTC_32K_MUX			2
+#define CLKID_RTC_32K				3
+#define CLKID_RTC_CLK				4
+#define CLKID_SYS_RESET_CTRL			5
+#define CLKID_SYS_PWR_CTRL			6
+#define CLKID_SYS_PAD_CTRL			7
+#define CLKID_SYS_CTRL				8
+#define CLKID_SYS_TS_PLL			9
+#define CLKID_SYS_DEV_ARB			10
+#define CLKID_SYS_MMC_PCLK			11
+#define CLKID_SYS_CPU_CTRL			12
+#define CLKID_SYS_JTAG_CTRL			13
+#define CLKID_SYS_IR_CTRL			14
+#define CLKID_SYS_IRQ_CTRL			15
+#define CLKID_SYS_MSR_CLK			16
+#define CLKID_SYS_ROM				17
+#define CLKID_SYS_UART_F			18
+#define CLKID_SYS_CPU_ARB			19
+#define CLKID_SYS_RSA				20
+#define CLKID_SYS_SAR_ADC			21
+#define CLKID_SYS_STARTUP			22
+#define CLKID_SYS_SECURE			23
+#define CLKID_SYS_SPIFC				24
+#define CLKID_SYS_NNA				25
+#define CLKID_SYS_ETH_MAC			26
+#define CLKID_SYS_GIC				27
+#define CLKID_SYS_RAMA				28
+#define CLKID_SYS_BIG_NIC			29
+#define CLKID_SYS_RAMB				30
+#define CLKID_SYS_AUDIO_PCLK			31
+#define CLKID_SYS_PWM_KL			32
+#define CLKID_SYS_PWM_IJ			33
+#define CLKID_SYS_USB				34
+#define CLKID_SYS_SD_EMMC_A			35
+#define CLKID_SYS_SD_EMMC_C			36
+#define CLKID_SYS_PWM_AB			37
+#define CLKID_SYS_PWM_CD			38
+#define CLKID_SYS_PWM_EF			39
+#define CLKID_SYS_PWM_GH			40
+#define CLKID_SYS_SPICC_1			41
+#define CLKID_SYS_SPICC_0			42
+#define CLKID_SYS_UART_A			43
+#define CLKID_SYS_UART_B			44
+#define CLKID_SYS_UART_C			45
+#define CLKID_SYS_UART_D			46
+#define CLKID_SYS_UART_E			47
+#define CLKID_SYS_I2C_M_A			48
+#define CLKID_SYS_I2C_M_B			49
+#define CLKID_SYS_I2C_M_C			50
+#define CLKID_SYS_I2C_M_D			51
+#define CLKID_SYS_I2S_S_A			52
+#define CLKID_SYS_RTC				53
+#define CLKID_SYS_GE2D				54
+#define CLKID_SYS_ISP				55
+#define CLKID_SYS_GPV_ISP_NIC			56
+#define CLKID_SYS_GPV_CVE_NIC			57
+#define CLKID_SYS_MIPI_DSI_HOST			58
+#define CLKID_SYS_MIPI_DSI_PHY			59
+#define CLKID_SYS_ETH_PHY			60
+#define CLKID_SYS_ACODEC			61
+#define CLKID_SYS_DWAP				62
+#define CLKID_SYS_DOS				63
+#define CLKID_SYS_CVE				64
+#define CLKID_SYS_VOUT				65
+#define CLKID_SYS_VC9000E			66
+#define CLKID_SYS_PWM_MN			67
+#define CLKID_SYS_SD_EMMC_B			68
+#define CLKID_AXI_SYS_NIC			69
+#define CLKID_AXI_ISP_NIC			70
+#define CLKID_AXI_CVE_NIC			71
+#define CLKID_AXI_RAMB				72
+#define CLKID_AXI_RAMA				73
+#define CLKID_AXI_CPU_DMC			74
+#define CLKID_AXI_NIC				75
+#define CLKID_AXI_DMA				76
+#define CLKID_AXI_MUX_NIC			77
+#define CLKID_AXI_CVE				78
+#define CLKID_AXI_DEV1_DMC			79
+#define CLKID_AXI_DEV0_DMC			80
+#define CLKID_AXI_DSP_DMC			81
+#define CLKID_12_24M_IN				82
+#define CLKID_12M_24M				83
+#define CLKID_FCLK_25M_DIV			84
+#define CLKID_FCLK_25M				85
+#define CLKID_GEN_SEL				86
+#define CLKID_GEN_DIV				87
+#define CLKID_GEN				88
+#define CLKID_SARADC_SEL			89
+#define CLKID_SARADC_DIV			90
+#define CLKID_SARADC				91
+#define CLKID_PWM_A_SEL				92
+#define CLKID_PWM_A_DIV				93
+#define CLKID_PWM_A				94
+#define CLKID_PWM_B_SEL				95
+#define CLKID_PWM_B_DIV				96
+#define CLKID_PWM_B				97
+#define CLKID_PWM_C_SEL				98
+#define CLKID_PWM_C_DIV				99
+#define CLKID_PWM_C				100
+#define CLKID_PWM_D_SEL				101
+#define CLKID_PWM_D_DIV				102
+#define CLKID_PWM_D				103
+#define CLKID_PWM_E_SEL				104
+#define CLKID_PWM_E_DIV				105
+#define CLKID_PWM_E				106
+#define CLKID_PWM_F_SEL				107
+#define CLKID_PWM_F_DIV				108
+#define CLKID_PWM_F				109
+#define CLKID_PWM_G_SEL				110
+#define CLKID_PWM_G_DIV				111
+#define CLKID_PWM_G				112
+#define CLKID_PWM_H_SEL				113
+#define CLKID_PWM_H_DIV				114
+#define CLKID_PWM_H				115
+#define CLKID_PWM_I_SEL				116
+#define CLKID_PWM_I_DIV				117
+#define CLKID_PWM_I				118
+#define CLKID_PWM_J_SEL				119
+#define CLKID_PWM_J_DIV				120
+#define CLKID_PWM_J				121
+#define CLKID_PWM_K_SEL				122
+#define CLKID_PWM_K_DIV				123
+#define CLKID_PWM_K				124
+#define CLKID_PWM_L_SEL				125
+#define CLKID_PWM_L_DIV				126
+#define CLKID_PWM_L				127
+#define CLKID_PWM_M_SEL				128
+#define CLKID_PWM_M_DIV				129
+#define CLKID_PWM_M				130
+#define CLKID_PWM_N_SEL				131
+#define CLKID_PWM_N_DIV				132
+#define CLKID_PWM_N				133
+#define CLKID_SPICC_A_SEL			134
+#define CLKID_SPICC_A_DIV			135
+#define CLKID_SPICC_A				136
+#define CLKID_SPICC_B_SEL			137
+#define CLKID_SPICC_B_DIV			138
+#define CLKID_SPICC_B				139
+#define CLKID_SPIFC_SEL				140
+#define CLKID_SPIFC_DIV				141
+#define CLKID_SPIFC				142
+#define CLKID_SD_EMMC_A_SEL			143
+#define CLKID_SD_EMMC_A_DIV			144
+#define CLKID_SD_EMMC_A				145
+#define CLKID_SD_EMMC_B_SEL			146
+#define CLKID_SD_EMMC_B_DIV			147
+#define CLKID_SD_EMMC_B				148
+#define CLKID_SD_EMMC_C_SEL			149
+#define CLKID_SD_EMMC_C_DIV			150
+#define CLKID_SD_EMMC_C				151
+#define CLKID_TS_DIV				152
+#define CLKID_TS				153
+#define CLKID_ETH_125M_DIV			154
+#define CLKID_ETH_125M				155
+#define CLKID_ETH_RMII_DIV			156
+#define CLKID_ETH_RMII				157
+#define CLKID_MIPI_DSI_MEAS_SEL			158
+#define CLKID_MIPI_DSI_MEAS_DIV			159
+#define CLKID_MIPI_DSI_MEAS			160
+#define CLKID_DSI_PHY_SEL			161
+#define CLKID_DSI_PHY_DIV			162
+#define CLKID_DSI_PHY				163
+#define CLKID_VOUT_MCLK_SEL			164
+#define CLKID_VOUT_MCLK_DIV			165
+#define CLKID_VOUT_MCLK				166
+#define CLKID_VOUT_ENC_SEL			167
+#define CLKID_VOUT_ENC_DIV			168
+#define CLKID_VOUT_ENC				169
+#define CLKID_HCODEC_0_SEL			170
+#define CLKID_HCODEC_0_DIV			171
+#define CLKID_HCODEC_0				172
+#define CLKID_HCODEC_1_SEL			173
+#define CLKID_HCODEC_1_DIV			174
+#define CLKID_HCODEC_1				175
+#define CLKID_HCODEC				176
+#define CLKID_VC9000E_ACLK_SEL			177
+#define CLKID_VC9000E_ACLK_DIV			178
+#define CLKID_VC9000E_ACLK			179
+#define CLKID_VC9000E_CORE_SEL			180
+#define CLKID_VC9000E_CORE_DIV			181
+#define CLKID_VC9000E_CORE			182
+#define CLKID_CSI_PHY0_SEL			183
+#define CLKID_CSI_PHY0_DIV			184
+#define CLKID_CSI_PHY0				185
+#define CLKID_DEWARPA_SEL			186
+#define CLKID_DEWARPA_DIV			187
+#define CLKID_DEWARPA				188
+#define CLKID_ISP0_SEL				189
+#define CLKID_ISP0_DIV				190
+#define CLKID_ISP0				191
+#define CLKID_NNA_CORE_SEL			192
+#define CLKID_NNA_CORE_DIV			193
+#define CLKID_NNA_CORE				194
+#define CLKID_GE2D_SEL				195
+#define CLKID_GE2D_DIV				196
+#define CLKID_GE2D				197
+#define CLKID_VAPB_SEL				198
+#define CLKID_VAPB_DIV				199
+#define CLKID_VAPB				200
+
+#endif  /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,c3-pll-clkc.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+
+#define CLKID_FCLK_50M_EN			0
+#define CLKID_FCLK_50M				1
+#define CLKID_FCLK_DIV2_DIV			2
+#define CLKID_FCLK_DIV2				3
+#define CLKID_FCLK_DIV2P5_DIV			4
+#define CLKID_FCLK_DIV2P5			5
+#define CLKID_FCLK_DIV3_DIV			6
+#define CLKID_FCLK_DIV3				7
+#define CLKID_FCLK_DIV4_DIV			8
+#define CLKID_FCLK_DIV4				9
+#define CLKID_FCLK_DIV5_DIV			10
+#define CLKID_FCLK_DIV5				11
+#define CLKID_FCLK_DIV7_DIV			12
+#define CLKID_FCLK_DIV7				13
+#define CLKID_GP0_PLL_DCO			14
+#define CLKID_GP0_PLL				15
+#define CLKID_HIFI_PLL_DCO			16
+#define CLKID_HIFI_PLL				17
+#define CLKID_MCLK_PLL_DCO			18
+#define CLKID_MCLK_PLL_OD			19
+#define CLKID_MCLK_PLL				20
+#define CLKID_MCLK0_SEL				21
+#define CLKID_MCLK0_SEL_EN			22
+#define CLKID_MCLK0_DIV				23
+#define CLKID_MCLK0				24
+#define CLKID_MCLK1_SEL				25
+#define CLKID_MCLK1_SEL_EN			26
+#define CLKID_MCLK1_DIV				27
+#define CLKID_MCLK1				28
+
+#endif  /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_C3_SCMI_CLKC_H
+#define __AMLOGIC_C3_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC			0
+#define CLKID_DDR_PHY				1
+#define CLKID_TOP_PLL_OSC			2
+#define CLKID_USB_PLL_OSC			3
+#define CLKID_MIPIISP_VOUT			4
+#define CLKID_MCLK_PLL_OSC			5
+#define CLKID_USB_CTRL				6
+#define CLKID_ETH_PLL_OSC			7
+#define CLKID_OSC				8
+#define CLKID_SYS_CLK				9
+#define CLKID_AXI_CLK				10
+#define CLKID_CPU_CLK				11
+#define CLKID_FIXED_PLL_OSC			12
+#define CLKID_GP1_PLL_OSC			13
+#define CLKID_SYS_PLL_DIV16			14
+#define CLKID_CPU_CLK_DIV16			15
+
+#endif /* __AMLOGIC_C3_SCMI_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h

@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_32K_CLKIN		0
+#define CLKID_RTC_32K_DIV		1
+#define CLKID_RTC_32K_SEL		2
+#define CLKID_RTC_32K_XATL		3
+#define CLKID_RTC			4
+#define CLKID_SYS_CLK_B_SEL		5
+#define CLKID_SYS_CLK_B_DIV		6
+#define CLKID_SYS_CLK_B			7
+#define CLKID_SYS_CLK_A_SEL		8
+#define CLKID_SYS_CLK_A_DIV		9
+#define CLKID_SYS_CLK_A			10
+#define CLKID_SYS			11
+#define CLKID_CECA_32K_CLKIN		12
+#define CLKID_CECA_32K_DIV		13
+#define CLKID_CECA_32K_SEL_PRE		14
+#define CLKID_CECA_32K_SEL		15
+#define CLKID_CECA_32K_CLKOUT		16
+#define CLKID_CECB_32K_CLKIN		17
+#define CLKID_CECB_32K_DIV		18
+#define CLKID_CECB_32K_SEL_PRE		19
+#define CLKID_CECB_32K_SEL		20
+#define CLKID_CECB_32K_CLKOUT		21
+#define CLKID_SC_CLK_SEL		22
+#define CLKID_SC_CLK_DIV		23
+#define CLKID_SC			24
+#define CLKID_12_24M			25
+#define CLKID_12M_CLK_DIV		26
+#define CLKID_12_24M_CLK_SEL		27
+#define CLKID_VID_PLL_DIV		28
+#define CLKID_VID_PLL_SEL		29
+#define CLKID_VID_PLL			30
+#define CLKID_VCLK_SEL			31
+#define CLKID_VCLK2_SEL			32
+#define CLKID_VCLK_INPUT		33
+#define CLKID_VCLK2_INPUT		34
+#define CLKID_VCLK_DIV			35
+#define CLKID_VCLK2_DIV			36
+#define CLKID_VCLK			37
+#define CLKID_VCLK2			38
+#define CLKID_VCLK_DIV1			39
+#define CLKID_VCLK_DIV2_EN		40
+#define CLKID_VCLK_DIV4_EN		41
+#define CLKID_VCLK_DIV6_EN		42
+#define CLKID_VCLK_DIV12_EN		43
+#define CLKID_VCLK2_DIV1		44
+#define CLKID_VCLK2_DIV2_EN		45
+#define CLKID_VCLK2_DIV4_EN		46
+#define CLKID_VCLK2_DIV6_EN		47
+#define CLKID_VCLK2_DIV12_EN		48
+#define CLKID_VCLK_DIV2			49
+#define CLKID_VCLK_DIV4			50
+#define CLKID_VCLK_DIV6			51
+#define CLKID_VCLK_DIV12		52
+#define CLKID_VCLK2_DIV2		53
+#define CLKID_VCLK2_DIV4		54
+#define CLKID_VCLK2_DIV6		55
+#define CLKID_VCLK2_DIV12		56
+#define CLKID_CTS_ENCI_SEL		57
+#define CLKID_CTS_ENCP_SEL		58
+#define CLKID_CTS_VDAC_SEL		59
+#define CLKID_HDMI_TX_SEL		60
+#define CLKID_CTS_ENCI			61
+#define CLKID_CTS_ENCP			62
+#define CLKID_CTS_VDAC			63
+#define CLKID_HDMI_TX			64
+#define CLKID_HDMI_SEL			65
+#define CLKID_HDMI_DIV			66
+#define CLKID_HDMI			67
+#define CLKID_TS_CLK_DIV		68
+#define CLKID_TS			69
+#define CLKID_MALI_0_SEL		70
+#define CLKID_MALI_0_DIV		71
+#define CLKID_MALI_0			72
+#define CLKID_MALI_1_SEL		73
+#define CLKID_MALI_1_DIV		74
+#define CLKID_MALI_1			75
+#define CLKID_MALI_SEL			76
+#define CLKID_VDEC_P0_SEL		77
+#define CLKID_VDEC_P0_DIV		78
+#define CLKID_VDEC_P0			79
+#define CLKID_VDEC_P1_SEL		80
+#define CLKID_VDEC_P1_DIV		81
+#define CLKID_VDEC_P1			82
+#define CLKID_VDEC_SEL			83
+#define CLKID_HEVCF_P0_SEL		84
+#define CLKID_HEVCF_P0_DIV		85
+#define CLKID_HEVCF_P0			86
+#define CLKID_HEVCF_P1_SEL		87
+#define CLKID_HEVCF_P1_DIV		88
+#define CLKID_HEVCF_P1			89
+#define CLKID_HEVCF_SEL			90
+#define CLKID_VPU_0_SEL			91
+#define CLKID_VPU_0_DIV			92
+#define CLKID_VPU_0			93
+#define CLKID_VPU_1_SEL			94
+#define CLKID_VPU_1_DIV			95
+#define CLKID_VPU_1			96
+#define CLKID_VPU			97
+#define CLKID_VPU_CLKB_TMP_SEL		98
+#define CLKID_VPU_CLKB_TMP_DIV		99
+#define CLKID_VPU_CLKB_TMP		100
+#define CLKID_VPU_CLKB_DIV		101
+#define CLKID_VPU_CLKB			102
+#define CLKID_VPU_CLKC_P0_SEL		103
+#define CLKID_VPU_CLKC_P0_DIV		104
+#define CLKID_VPU_CLKC_P0		105
+#define CLKID_VPU_CLKC_P1_SEL		106
+#define CLKID_VPU_CLKC_P1_DIV		107
+#define CLKID_VPU_CLKC_P1		108
+#define CLKID_VPU_CLKC_SEL		109
+#define CLKID_VAPB_0_SEL		110
+#define CLKID_VAPB_0_DIV		111
+#define CLKID_VAPB_0			112
+#define CLKID_VAPB_1_SEL		113
+#define CLKID_VAPB_1_DIV		114
+#define CLKID_VAPB_1			115
+#define CLKID_VAPB			116
+#define CLKID_GE2D			117
+#define CLKID_VDIN_MEAS_SEL		118
+#define CLKID_VDIN_MEAS_DIV		119
+#define CLKID_VDIN_MEAS			120
+#define CLKID_SD_EMMC_C_CLK_SEL		121
+#define CLKID_SD_EMMC_C_CLK_DIV		122
+#define CLKID_SD_EMMC_C			123
+#define CLKID_SD_EMMC_A_CLK_SEL		124
+#define CLKID_SD_EMMC_A_CLK_DIV		125
+#define CLKID_SD_EMMC_A			126
+#define CLKID_SD_EMMC_B_CLK_SEL		127
+#define CLKID_SD_EMMC_B_CLK_DIV		128
+#define CLKID_SD_EMMC_B			129
+#define CLKID_SPICC0_SEL		130
+#define CLKID_SPICC0_DIV		131
+#define CLKID_SPICC0_EN			132
+#define CLKID_PWM_A_SEL			133
+#define CLKID_PWM_A_DIV			134
+#define CLKID_PWM_A			135
+#define CLKID_PWM_B_SEL			136
+#define CLKID_PWM_B_DIV			137
+#define CLKID_PWM_B			138
+#define CLKID_PWM_C_SEL			139
+#define CLKID_PWM_C_DIV			140
+#define CLKID_PWM_C			141
+#define CLKID_PWM_D_SEL			142
+#define CLKID_PWM_D_DIV			143
+#define CLKID_PWM_D			144
+#define CLKID_PWM_E_SEL			145
+#define CLKID_PWM_E_DIV			146
+#define CLKID_PWM_E			147
+#define CLKID_PWM_F_SEL			148
+#define CLKID_PWM_F_DIV			149
+#define CLKID_PWM_F			150
+#define CLKID_PWM_G_SEL			151
+#define CLKID_PWM_G_DIV			152
+#define CLKID_PWM_G			153
+#define CLKID_PWM_H_SEL			154
+#define CLKID_PWM_H_DIV			155
+#define CLKID_PWM_H			156
+#define CLKID_PWM_I_SEL			157
+#define CLKID_PWM_I_DIV			158
+#define CLKID_PWM_I			159
+#define CLKID_PWM_J_SEL			160
+#define CLKID_PWM_J_DIV			161
+#define CLKID_PWM_J			162
+#define CLKID_SARADC_SEL		163
+#define CLKID_SARADC_DIV		164
+#define CLKID_SARADC			165
+#define CLKID_GEN_SEL			166
+#define CLKID_GEN_DIV			167
+#define CLKID_GEN			168
+#define CLKID_DDR			169
+#define CLKID_DOS			170
+#define CLKID_ETHPHY			171
+#define CLKID_MALI			172
+#define CLKID_AOCPU			173
+#define CLKID_AUCPU			174
+#define CLKID_CEC			175
+#define CLKID_SDEMMC_A			176
+#define CLKID_SDEMMC_B			177
+#define CLKID_NAND			178
+#define CLKID_SMARTCARD			179
+#define CLKID_ACODEC			180
+#define CLKID_SPIFC			181
+#define CLKID_MSR			182
+#define CLKID_IR_CTRL			183
+#define CLKID_AUDIO			184
+#define CLKID_ETH			185
+#define CLKID_UART_A			186
+#define CLKID_UART_B			187
+#define CLKID_UART_C			188
+#define CLKID_UART_D			189
+#define CLKID_UART_E			190
+#define CLKID_AIFIFO			191
+#define CLKID_TS_DDR			192
+#define CLKID_TS_PLL			193
+#define CLKID_G2D			194
+#define CLKID_SPICC0			195
+#define CLKID_SPICC1			196
+#define CLKID_USB			197
+#define CLKID_I2C_M_A			198
+#define CLKID_I2C_M_B			199
+#define CLKID_I2C_M_C			200
+#define CLKID_I2C_M_D			201
+#define CLKID_I2C_M_E			202
+#define CLKID_HDMITX_APB		203
+#define CLKID_I2C_S_A			204
+#define CLKID_USB1_TO_DDR		205
+#define CLKID_HDCP22			206
+#define CLKID_MMC_APB			207
+#define CLKID_RSA			208
+#define CLKID_CPU_DEBUG			209
+#define CLKID_VPU_INTR			210
+#define CLKID_DEMOD			211
+#define CLKID_SAR_ADC			212
+#define CLKID_GIC			213
+#define CLKID_PWM_AB			214
+#define CLKID_PWM_CD			215
+#define CLKID_PWM_EF			216
+#define CLKID_PWM_GH			217
+#define CLKID_PWM_IJ			218
+#define CLKID_HDCP22_ESMCLK_SEL		219
+#define CLKID_HDCP22_ESMCLK_DIV		220
+#define CLKID_HDCP22_ESMCLK		221
+#define CLKID_HDCP22_SKPCLK_SEL		222
+#define CLKID_HDCP22_SKPCLK_DIV		223
+#define CLKID_HDCP22_SKPCLK		224
+#define CLKID_CTS_ENCL_SEL		225
+#define CLKID_CTS_ENCL			226
+#define CLKID_CDAC_SEL			227
+#define CLKID_CDAC_DIV			228
+#define CLKID_CDAC			229
+#define CLKID_DEMOD_CORE_SEL		230
+#define CLKID_DEMOD_CORE_DIV		231
+#define CLKID_DEMOD_CORE		232
+#define CLKID_ADC_EXTCLK_IN_SEL		233
+#define CLKID_ADC_EXTCLK_IN_DIV		234
+#define CLKID_ADC_EXTCLK_IN		235
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,s4-pll-clkc.h

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL_DCO		0
+#define CLKID_FIXED_PLL			1
+#define CLKID_FCLK_DIV2_DIV		2
+#define CLKID_FCLK_DIV2			3
+#define CLKID_FCLK_DIV3_DIV		4
+#define CLKID_FCLK_DIV3			5
+#define CLKID_FCLK_DIV4_DIV		6
+#define CLKID_FCLK_DIV4			7
+#define CLKID_FCLK_DIV5_DIV		8
+#define CLKID_FCLK_DIV5			9
+#define CLKID_FCLK_DIV7_DIV		10
+#define CLKID_FCLK_DIV7			11
+#define CLKID_FCLK_DIV2P5_DIV		12
+#define CLKID_FCLK_DIV2P5		13
+#define CLKID_GP0_PLL_DCO		14
+#define CLKID_GP0_PLL			15
+#define CLKID_HIFI_PLL_DCO		16
+#define CLKID_HIFI_PLL			17
+#define CLKID_HDMI_PLL_DCO		18
+#define CLKID_HDMI_PLL_OD		19
+#define CLKID_HDMI_PLL			20
+#define CLKID_MPLL_50M_DIV		21
+#define CLKID_MPLL_50M			22
+#define CLKID_MPLL_PREDIV		23
+#define CLKID_MPLL0_DIV			24
+#define CLKID_MPLL0			25
+#define CLKID_MPLL1_DIV			26
+#define CLKID_MPLL1			27
+#define CLKID_MPLL2_DIV			28
+#define CLKID_MPLL2			29
+#define CLKID_MPLL3_DIV			30
+#define CLKID_MPLL3			31
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h

@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PERIPHERALS_CLKC_H
+#define __T7_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_DUALDIV_IN		0
+#define CLKID_RTC_DUALDIV_DIV		1
+#define CLKID_RTC_DUALDIV_SEL		2
+#define CLKID_RTC_DUALDIV		3
+#define CLKID_RTC			4
+#define CLKID_CECA_DUALDIV_IN		5
+#define CLKID_CECA_DUALDIV_DIV		6
+#define CLKID_CECA_DUALDIV_SEL		7
+#define CLKID_CECA_DUALDIV		8
+#define CLKID_CECA			9
+#define CLKID_CECB_DUALDIV_IN		10
+#define CLKID_CECB_DUALDIV_DIV		11
+#define CLKID_CECB_DUALDIV_SEL		12
+#define CLKID_CECB_DUALDIV		13
+#define CLKID_CECB			14
+#define CLKID_SC_SEL			15
+#define CLKID_SC_DIV			16
+#define CLKID_SC			17
+#define CLKID_DSPA_0_SEL		18
+#define CLKID_DSPA_0_DIV		19
+#define CLKID_DSPA_0			20
+#define CLKID_DSPA_1_SEL		21
+#define CLKID_DSPA_1_DIV		22
+#define CLKID_DSPA_1			23
+#define CLKID_DSPA			24
+#define CLKID_DSPB_0_SEL		25
+#define CLKID_DSPB_0_DIV		26
+#define CLKID_DSPB_0			27
+#define CLKID_DSPB_1_SEL		28
+#define CLKID_DSPB_1_DIV		29
+#define CLKID_DSPB_1			30
+#define CLKID_DSPB			31
+#define CLKID_24M			32
+#define CLKID_24M_DIV2			33
+#define CLKID_12M			34
+#define CLKID_25M_DIV			35
+#define CLKID_25M			36
+#define CLKID_ANAKIN_0_SEL		37
+#define CLKID_ANAKIN_0_DIV		38
+#define CLKID_ANAKIN_0			39
+#define CLKID_ANAKIN_1_SEL		40
+#define CLKID_ANAKIN_1_DIV		41
+#define CLKID_ANAKIN_1			42
+#define CLKID_ANAKIN_01_SEL		43
+#define CLKID_ANAKIN			44
+#define CLKID_TS_DIV			45
+#define CLKID_TS			46
+#define CLKID_MIPI_CSI_PHY_0_SEL	47
+#define CLKID_MIPI_CSI_PHY_0_DIV	48
+#define CLKID_MIPI_CSI_PHY_0		49
+#define CLKID_MIPI_CSI_PHY_1_SEL	50
+#define CLKID_MIPI_CSI_PHY_1_DIV	51
+#define CLKID_MIPI_CSI_PHY_1		52
+#define CLKID_MIPI_CSI_PHY		53
+#define CLKID_MIPI_ISP_SEL		54
+#define CLKID_MIPI_ISP_DIV		55
+#define CLKID_MIPI_ISP			56
+#define CLKID_MALI_0_SEL		57
+#define CLKID_MALI_0_DIV		58
+#define CLKID_MALI_0			59
+#define CLKID_MALI_1_SEL		60
+#define CLKID_MALI_1_DIV		61
+#define CLKID_MALI_1			62
+#define CLKID_MALI			63
+#define CLKID_ETH_RMII_SEL		64
+#define CLKID_ETH_RMII_DIV		65
+#define CLKID_ETH_RMII			66
+#define CLKID_FCLK_DIV2_DIV8		67
+#define CLKID_ETH_125M			68
+#define CLKID_SD_EMMC_A_SEL		69
+#define CLKID_SD_EMMC_A_DIV		70
+#define CLKID_SD_EMMC_A			71
+#define CLKID_SD_EMMC_B_SEL		72
+#define CLKID_SD_EMMC_B_DIV		73
+#define CLKID_SD_EMMC_B			74
+#define CLKID_SD_EMMC_C_SEL		75
+#define CLKID_SD_EMMC_C_DIV		76
+#define CLKID_SD_EMMC_C			77
+#define CLKID_SPICC0_SEL		78
+#define CLKID_SPICC0_DIV		79
+#define CLKID_SPICC0			80
+#define CLKID_SPICC1_SEL		81
+#define CLKID_SPICC1_DIV		82
+#define CLKID_SPICC1			83
+#define CLKID_SPICC2_SEL		84
+#define CLKID_SPICC2_DIV		85
+#define CLKID_SPICC2			86
+#define CLKID_SPICC3_SEL		87
+#define CLKID_SPICC3_DIV		88
+#define CLKID_SPICC3			89
+#define CLKID_SPICC4_SEL		90
+#define CLKID_SPICC4_DIV		91
+#define CLKID_SPICC4			92
+#define CLKID_SPICC5_SEL		93
+#define CLKID_SPICC5_DIV		94
+#define CLKID_SPICC5			95
+#define CLKID_SARADC_SEL		96
+#define CLKID_SARADC_DIV		97
+#define CLKID_SARADC			98
+#define CLKID_PWM_A_SEL			99
+#define CLKID_PWM_A_DIV			100
+#define CLKID_PWM_A			101
+#define CLKID_PWM_B_SEL			102
+#define CLKID_PWM_B_DIV			103
+#define CLKID_PWM_B			104
+#define CLKID_PWM_C_SEL			105
+#define CLKID_PWM_C_DIV			106
+#define CLKID_PWM_C			107
+#define CLKID_PWM_D_SEL			108
+#define CLKID_PWM_D_DIV			109
+#define CLKID_PWM_D			110
+#define CLKID_PWM_E_SEL			111
+#define CLKID_PWM_E_DIV			112
+#define CLKID_PWM_E			113
+#define CLKID_PWM_F_SEL			114
+#define CLKID_PWM_F_DIV			115
+#define CLKID_PWM_F			116
+#define CLKID_PWM_AO_A_SEL		117
+#define CLKID_PWM_AO_A_DIV		118
+#define CLKID_PWM_AO_A			119
+#define CLKID_PWM_AO_B_SEL		120
+#define CLKID_PWM_AO_B_DIV		121
+#define CLKID_PWM_AO_B			122
+#define CLKID_PWM_AO_C_SEL		123
+#define CLKID_PWM_AO_C_DIV		124
+#define CLKID_PWM_AO_C			125
+#define CLKID_PWM_AO_D_SEL		126
+#define CLKID_PWM_AO_D_DIV		127
+#define CLKID_PWM_AO_D			128
+#define CLKID_PWM_AO_E_SEL		129
+#define CLKID_PWM_AO_E_DIV		130
+#define CLKID_PWM_AO_E			131
+#define CLKID_PWM_AO_F_SEL		132
+#define CLKID_PWM_AO_F_DIV		133
+#define CLKID_PWM_AO_F			134
+#define CLKID_PWM_AO_G_SEL		135
+#define CLKID_PWM_AO_G_DIV		136
+#define CLKID_PWM_AO_G			137
+#define CLKID_PWM_AO_H_SEL		138
+#define CLKID_PWM_AO_H_DIV		139
+#define CLKID_PWM_AO_H			140
+#define CLKID_SYS_DDR			141
+#define CLKID_SYS_DOS			142
+#define CLKID_SYS_MIPI_DSI_A		143
+#define CLKID_SYS_MIPI_DSI_B		144
+#define CLKID_SYS_ETHPHY		145
+#define CLKID_SYS_MALI			146
+#define CLKID_SYS_AOCPU			147
+#define CLKID_SYS_AUCPU			148
+#define CLKID_SYS_CEC			149
+#define CLKID_SYS_GDC			150
+#define CLKID_SYS_DESWARP		151
+#define CLKID_SYS_AMPIPE_NAND		152
+#define CLKID_SYS_AMPIPE_ETH		153
+#define CLKID_SYS_AM2AXI0		154
+#define CLKID_SYS_AM2AXI1		155
+#define CLKID_SYS_AM2AXI2		156
+#define CLKID_SYS_SD_EMMC_A		157
+#define CLKID_SYS_SD_EMMC_B		158
+#define CLKID_SYS_SD_EMMC_C		159
+#define CLKID_SYS_SMARTCARD		160
+#define CLKID_SYS_ACODEC		161
+#define CLKID_SYS_SPIFC			162
+#define CLKID_SYS_MSR_CLK		163
+#define CLKID_SYS_IR_CTRL		164
+#define CLKID_SYS_AUDIO			165
+#define CLKID_SYS_ETH			166
+#define CLKID_SYS_UART_A		167
+#define CLKID_SYS_UART_B		168
+#define CLKID_SYS_UART_C		169
+#define CLKID_SYS_UART_D		170
+#define CLKID_SYS_UART_E		171
+#define CLKID_SYS_UART_F		172
+#define CLKID_SYS_AIFIFO		173
+#define CLKID_SYS_SPICC2		174
+#define CLKID_SYS_SPICC3		175
+#define CLKID_SYS_SPICC4		176
+#define CLKID_SYS_TS_A73		177
+#define CLKID_SYS_TS_A53		178
+#define CLKID_SYS_SPICC5		179
+#define CLKID_SYS_G2D			180
+#define CLKID_SYS_SPICC0		181
+#define CLKID_SYS_SPICC1		182
+#define CLKID_SYS_PCIE			183
+#define CLKID_SYS_USB			184
+#define CLKID_SYS_PCIE_PHY		185
+#define CLKID_SYS_I2C_AO_A		186
+#define CLKID_SYS_I2C_AO_B		187
+#define CLKID_SYS_I2C_M_A		188
+#define CLKID_SYS_I2C_M_B		189
+#define CLKID_SYS_I2C_M_C		190
+#define CLKID_SYS_I2C_M_D		191
+#define CLKID_SYS_I2C_M_E		192
+#define CLKID_SYS_I2C_M_F		193
+#define CLKID_SYS_HDMITX_APB		194
+#define CLKID_SYS_I2C_S_A		195
+#define CLKID_SYS_HDMIRX_PCLK		196
+#define CLKID_SYS_MMC_APB		197
+#define CLKID_SYS_MIPI_ISP_PCLK		198
+#define CLKID_SYS_RSA			199
+#define CLKID_SYS_PCLK_SYS_APB		200
+#define CLKID_SYS_A73PCLK_APB		201
+#define CLKID_SYS_DSPA			202
+#define CLKID_SYS_DSPB			203
+#define CLKID_SYS_VPU_INTR		204
+#define CLKID_SYS_SAR_ADC		205
+#define CLKID_SYS_GIC			206
+#define CLKID_SYS_TS_GPU		207
+#define CLKID_SYS_TS_NNA		208
+#define CLKID_SYS_TS_VPU		209
+#define CLKID_SYS_TS_HEVC		210
+#define CLKID_SYS_PWM_AB		211
+#define CLKID_SYS_PWM_CD		212
+#define CLKID_SYS_PWM_EF		213
+#define CLKID_SYS_PWM_AO_AB		214
+#define CLKID_SYS_PWM_AO_CD		215
+#define CLKID_SYS_PWM_AO_EF		216
+#define CLKID_SYS_PWM_AO_GH		217
+
+#endif /* __T7_PERIPHERALS_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,t7-pll-clkc.h

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PLL_CLKC_H
+#define __T7_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_PLL_DCO	0
+#define CLKID_GP0_PLL		1
+
+/* GP1 */
+#define CLKID_GP1_PLL_DCO	0
+#define CLKID_GP1_PLL		1
+
+/* HIFI */
+#define CLKID_HIFI_PLL_DCO	0
+#define CLKID_HIFI_PLL		1
+
+/* PCIE */
+#define CLKID_PCIE_PLL_DCO	0
+#define CLKID_PCIE_PLL_DCO_DIV2	1
+#define CLKID_PCIE_PLL_OD	2
+#define CLKID_PCIE_PLL		3
+
+/* MPLL */
+#define CLKID_MPLL_PREDIV	0
+#define CLKID_MPLL0_DIV		1
+#define CLKID_MPLL0		2
+#define CLKID_MPLL1_DIV		3
+#define CLKID_MPLL1		4
+#define CLKID_MPLL2_DIV		5
+#define CLKID_MPLL2		6
+#define CLKID_MPLL3_DIV		7
+#define CLKID_MPLL3		8
+
+/* HDMI */
+#define CLKID_HDMI_PLL_DCO	0
+#define CLKID_HDMI_PLL_OD	1
+#define CLKID_HDMI_PLL		2
+
+/* MCLK */
+#define CLKID_MCLK_PLL_DCO	0
+#define CLKID_MCLK_PRE		1
+#define CLKID_MCLK_PLL		2
+#define CLKID_MCLK_0_SEL	3
+#define CLKID_MCLK_0_DIV2	4
+#define CLKID_MCLK_0_PRE	5
+#define CLKID_MCLK_0		6
+#define CLKID_MCLK_1_SEL	7
+#define CLKID_MCLK_1_DIV2	8
+#define CLKID_MCLK_1_PRE	9
+#define CLKID_MCLK_1		10
+
+#endif /* __T7_PLL_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/amlogic,t7-scmi.h

@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_SCMI_CLKC_H
+#define __T7_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC			0
+#define CLKID_AUD_PLL_OSC			1
+#define CLKID_TOP_PLL_OSC			2
+#define CLKID_TCON_PLL_OSC			3
+#define CLKID_USB_PLL0_OSC			4
+#define CLKID_USB_PLL1_OSC			5
+#define CLKID_MCLK_PLL_OSC			6
+#define CLKID_PCIE_OSC				7
+#define CLKID_ETH_PLL_OSC			8
+#define CLKID_PCIE_REFCLK_PLL_OSC		9
+#define CLKID_EARC_OSC				10
+#define CLKID_SYS1_PLL_OSC			11
+#define CLKID_HDMI_PLL_OSC			12
+#define CLKID_SYS_CLK				13
+#define CLKID_AXI_CLK				14
+#define CLKID_FIXED_PLL_DCO			15
+#define CLKID_FIXED_PLL				16
+#define CLKID_FCLK_DIV2_DIV			17
+#define CLKID_FCLK_DIV2				18
+#define CLKID_FCLK_DIV2P5_DIV			19
+#define CLKID_FCLK_DIV2P5			20
+#define CLKID_FCLK_DIV3_DIV			21
+#define CLKID_FCLK_DIV3				22
+#define CLKID_FCLK_DIV4_DIV			23
+#define CLKID_FCLK_DIV4				24
+#define CLKID_FCLK_DIV5_DIV			25
+#define CLKID_FCLK_DIV5				26
+#define CLKID_FCLK_DIV7_DIV			27
+#define CLKID_FCLK_DIV7				28
+#define CLKID_FCLK_50M_DIV			29
+#define CLKID_FCLK_50M				30
+#define CLKID_CPU_CLK				31
+#define CLKID_A73_CLK				32
+#define CLKID_CPU_CLK_DIV16_DIV			33
+#define CLKID_CPU_CLK_DIV16			34
+#define CLKID_A73_CLK_DIV16_DIV			35
+#define CLKID_A73_CLK_DIV16			36
+
+#endif /* __T7_SCMI_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/aspeed,ast2700-scu.h

@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 clock controller.
+ *
+ * Copyright (c) 2024 Aspeed Technology Inc.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_AST2700_H
+#define __DT_BINDINGS_CLOCK_AST2700_H
+
+/* SOC0 clk */
+#define SCU0_CLKIN		0
+#define SCU0_CLK_24M		1
+#define SCU0_CLK_192M		2
+#define SCU0_CLK_UART		3
+#define SCU0_CLK_UART_DIV13	3
+#define SCU0_CLK_PSP		4
+#define SCU0_CLK_HPLL		5
+#define SCU0_CLK_HPLL_DIV2	6
+#define SCU0_CLK_HPLL_DIV4	7
+#define SCU0_CLK_HPLL_DIV_AHB	8
+#define SCU0_CLK_DPLL		9
+#define SCU0_CLK_MPLL		10
+#define SCU0_CLK_MPLL_DIV2	11
+#define SCU0_CLK_MPLL_DIV4	12
+#define SCU0_CLK_MPLL_DIV8	13
+#define SCU0_CLK_MPLL_DIV_AHB	14
+#define SCU0_CLK_D0		15
+#define SCU0_CLK_D1		16
+#define SCU0_CLK_CRT0		17
+#define SCU0_CLK_CRT1		18
+#define SCU0_CLK_MPHY		19
+#define SCU0_CLK_AXI0		20
+#define SCU0_CLK_AXI1		21
+#define SCU0_CLK_AHB		22
+#define SCU0_CLK_APB		23
+#define SCU0_CLK_UART4		24
+#define SCU0_CLK_EMMCMUX	25
+#define SCU0_CLK_EMMC		26
+#define SCU0_CLK_U2PHY_CLK12M	27
+#define SCU0_CLK_U2PHY_REFCLK	28
+
+/* SOC0 clk-gate */
+#define SCU0_CLK_GATE_MCLK	29
+#define SCU0_CLK_GATE_ECLK	30
+#define SCU0_CLK_GATE_2DCLK	31
+#define SCU0_CLK_GATE_VCLK	32
+#define SCU0_CLK_GATE_BCLK	33
+#define SCU0_CLK_GATE_VGA0CLK	34
+#define SCU0_CLK_GATE_REFCLK	35
+#define SCU0_CLK_GATE_PORTBUSB2CLK	36
+#define SCU0_CLK_GATE_UHCICLK	37
+#define SCU0_CLK_GATE_VGA1CLK	38
+#define SCU0_CLK_GATE_DDRPHYCLK	39
+#define SCU0_CLK_GATE_E2M0CLK	40
+#define SCU0_CLK_GATE_HACCLK	41
+#define SCU0_CLK_GATE_PORTAUSB2CLK	42
+#define SCU0_CLK_GATE_UART4CLK	43
+#define SCU0_CLK_GATE_SLICLK	44
+#define SCU0_CLK_GATE_DACCLK	45
+#define SCU0_CLK_GATE_DP	46
+#define SCU0_CLK_GATE_E2M1CLK	47
+#define SCU0_CLK_GATE_CRT0CLK	48
+#define SCU0_CLK_GATE_CRT1CLK	49
+#define SCU0_CLK_GATE_ECDSACLK	50
+#define SCU0_CLK_GATE_RSACLK	51
+#define SCU0_CLK_GATE_RVAS0CLK	52
+#define SCU0_CLK_GATE_UFSCLK	53
+#define SCU0_CLK_GATE_EMMCCLK	54
+#define SCU0_CLK_GATE_RVAS1CLK	55
+#define SCU0_CLK_U2PHY_REFCLKSRC 56
+#define SCU0_CLK_AHBMUX			57
+#define SCU0_CLK_MPHYSRC		58
+
+/* SOC1 clk */
+#define SCU1_CLKIN		0
+#define SCU1_CLK_HPLL		1
+#define SCU1_CLK_APLL		2
+#define SCU1_CLK_APLL_DIV2	3
+#define SCU1_CLK_APLL_DIV4	4
+#define SCU1_CLK_DPLL		5
+#define SCU1_CLK_UXCLK		6
+#define SCU1_CLK_HUXCLK		7
+#define SCU1_CLK_UARTX		8
+#define SCU1_CLK_HUARTX		9
+#define SCU1_CLK_AHB		10
+#define SCU1_CLK_APB		11
+#define SCU1_CLK_UART0		12
+#define SCU1_CLK_UART1		13
+#define SCU1_CLK_UART2		14
+#define SCU1_CLK_UART3		15
+#define SCU1_CLK_UART5		16
+#define SCU1_CLK_UART6		17
+#define SCU1_CLK_UART7		18
+#define SCU1_CLK_UART8		19
+#define SCU1_CLK_UART9		20
+#define SCU1_CLK_UART10		21
+#define SCU1_CLK_UART11		22
+#define SCU1_CLK_UART12		23
+#define SCU1_CLK_UART13		24
+#define SCU1_CLK_UART14		25
+#define SCU1_CLK_APLL_DIVN	26
+#define SCU1_CLK_SDMUX		27
+#define SCU1_CLK_SDCLK		28
+#define SCU1_CLK_RMII		29
+#define SCU1_CLK_RGMII		30
+#define SCU1_CLK_MACHCLK	31
+#define SCU1_CLK_MAC0RCLK	32
+#define SCU1_CLK_MAC1RCLK	33
+#define SCU1_CLK_CAN		34
+
+/* SOC1 clk gate */
+#define SCU1_CLK_GATE_LCLK0		35
+#define SCU1_CLK_GATE_LCLK1		36
+#define SCU1_CLK_GATE_ESPI0CLK		37
+#define SCU1_CLK_GATE_ESPI1CLK		38
+#define SCU1_CLK_GATE_SDCLK		39
+#define SCU1_CLK_GATE_IPEREFCLK		40
+#define SCU1_CLK_GATE_REFCLK		41
+#define SCU1_CLK_GATE_LPCHCLK		42
+#define SCU1_CLK_GATE_MAC0CLK		43
+#define SCU1_CLK_GATE_MAC1CLK		44
+#define SCU1_CLK_GATE_MAC2CLK		45
+#define SCU1_CLK_GATE_UART0CLK		46
+#define SCU1_CLK_GATE_UART1CLK		47
+#define SCU1_CLK_GATE_UART2CLK		48
+#define SCU1_CLK_GATE_UART3CLK		49
+#define SCU1_CLK_GATE_I2CCLK		50
+#define SCU1_CLK_GATE_I3C0CLK		51
+#define SCU1_CLK_GATE_I3C1CLK		52
+#define SCU1_CLK_GATE_I3C2CLK		53
+#define SCU1_CLK_GATE_I3C3CLK		54
+#define SCU1_CLK_GATE_I3C4CLK		55
+#define SCU1_CLK_GATE_I3C5CLK		56
+#define SCU1_CLK_GATE_I3C6CLK		57
+#define SCU1_CLK_GATE_I3C7CLK		58
+#define SCU1_CLK_GATE_I3C8CLK		59
+#define SCU1_CLK_GATE_I3C9CLK		60
+#define SCU1_CLK_GATE_I3C10CLK		61
+#define SCU1_CLK_GATE_I3C11CLK		62
+#define SCU1_CLK_GATE_I3C12CLK		63
+#define SCU1_CLK_GATE_I3C13CLK		64
+#define SCU1_CLK_GATE_I3C14CLK		65
+#define SCU1_CLK_GATE_I3C15CLK		66
+#define SCU1_CLK_GATE_UART5CLK		67
+#define SCU1_CLK_GATE_UART6CLK		68
+#define SCU1_CLK_GATE_UART7CLK		69
+#define SCU1_CLK_GATE_UART8CLK		70
+#define SCU1_CLK_GATE_UART9CLK		71
+#define SCU1_CLK_GATE_UART10CLK		72
+#define SCU1_CLK_GATE_UART11CLK		73
+#define SCU1_CLK_GATE_UART12CLK		74
+#define SCU1_CLK_GATE_FSICLK		75
+#define SCU1_CLK_GATE_LTPIPHYCLK	76
+#define SCU1_CLK_GATE_LTPICLK		77
+#define SCU1_CLK_GATE_VGALCLK		78
+#define SCU1_CLK_GATE_UHCICLK		79
+#define SCU1_CLK_GATE_CANCLK		80
+#define SCU1_CLK_GATE_PCICLK		81
+#define SCU1_CLK_GATE_SLICLK		82
+#define SCU1_CLK_GATE_E2MCLK		83
+#define SCU1_CLK_GATE_PORTCUSB2CLK	84
+#define SCU1_CLK_GATE_PORTDUSB2CLK	85
+#define SCU1_CLK_GATE_LTPI1TXCLK	86
+#define SCU1_CLK_I3C				87
+
+#endif

linux-7.2.3/include/dt-bindings/clock/aspeed-clock.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_ASPEED_CLOCK_H
+#define DT_BINDINGS_ASPEED_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+#define ASPEED_CLK_GATE_MCLK		2
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+#define ASPEED_CLK_GATE_REFCLK		6
+#define ASPEED_CLK_GATE_USBPORT2CLK	7
+#define ASPEED_CLK_GATE_LCLK		8
+#define ASPEED_CLK_GATE_USBUHCICLK	9
+#define ASPEED_CLK_GATE_D1CLK		10
+#define ASPEED_CLK_GATE_YCLK		11
+#define ASPEED_CLK_GATE_USBPORT1CLK	12
+#define ASPEED_CLK_GATE_UART1CLK	13
+#define ASPEED_CLK_GATE_UART2CLK	14
+#define ASPEED_CLK_GATE_UART5CLK	15
+#define ASPEED_CLK_GATE_ESPICLK		16
+#define ASPEED_CLK_GATE_MAC1CLK		17
+#define ASPEED_CLK_GATE_MAC2CLK		18
+#define ASPEED_CLK_GATE_RSACLK		19
+#define ASPEED_CLK_GATE_UART3CLK	20
+#define ASPEED_CLK_GATE_UART4CLK	21
+#define ASPEED_CLK_GATE_SDCLK		22
+#define ASPEED_CLK_GATE_LHCCLK		23
+#define ASPEED_CLK_HPLL			24
+#define ASPEED_CLK_AHB			25
+#define ASPEED_CLK_APB			26
+#define ASPEED_CLK_UART			27
+#define ASPEED_CLK_SDIO			28
+#define ASPEED_CLK_ECLK			29
+#define ASPEED_CLK_ECLK_MUX		30
+#define ASPEED_CLK_LHCLK		31
+#define ASPEED_CLK_MAC			32
+#define ASPEED_CLK_BCLK			33
+#define ASPEED_CLK_MPLL			34
+#define ASPEED_CLK_24M			35
+#define ASPEED_CLK_MAC1RCLK		36
+#define ASPEED_CLK_MAC2RCLK		37
+
+#define ASPEED_RESET_XDMA		0
+#define ASPEED_RESET_MCTP		1
+#define ASPEED_RESET_ADC		2
+#define ASPEED_RESET_JTAG_MASTER	3
+#define ASPEED_RESET_MIC		4
+#define ASPEED_RESET_PWM		5
+#define ASPEED_RESET_PECI		6
+#define ASPEED_RESET_I2C		7
+#define ASPEED_RESET_AHB		8
+#define ASPEED_RESET_CRT1		9
+#define ASPEED_RESET_HACE		10
+#define ASPEED_RESET_VIDEO		11
+
+#endif

linux-7.2.3/include/dt-bindings/clock/ast2600-clock.h

@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
+#ifndef DT_BINDINGS_AST2600_CLOCK_H
+#define DT_BINDINGS_AST2600_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+
+#define ASPEED_CLK_GATE_MCLK		2
+
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+
+#define ASPEED_CLK_GATE_LCLK		6
+#define ASPEED_CLK_GATE_LHCCLK		7
+
+#define ASPEED_CLK_GATE_D1CLK		8
+#define ASPEED_CLK_GATE_YCLK		9
+
+#define ASPEED_CLK_GATE_REF0CLK		10
+#define ASPEED_CLK_GATE_REF1CLK		11
+
+#define ASPEED_CLK_GATE_ESPICLK		12
+
+#define ASPEED_CLK_GATE_USBUHCICLK	13
+#define ASPEED_CLK_GATE_USBPORT1CLK	14
+#define ASPEED_CLK_GATE_USBPORT2CLK	15
+
+#define ASPEED_CLK_GATE_RSACLK		16
+#define ASPEED_CLK_GATE_RVASCLK		17
+
+#define ASPEED_CLK_GATE_MAC1CLK		18
+#define ASPEED_CLK_GATE_MAC2CLK		19
+#define ASPEED_CLK_GATE_MAC3CLK		20
+#define ASPEED_CLK_GATE_MAC4CLK		21
+
+#define ASPEED_CLK_GATE_UART1CLK	22
+#define ASPEED_CLK_GATE_UART2CLK	23
+#define ASPEED_CLK_GATE_UART3CLK	24
+#define ASPEED_CLK_GATE_UART4CLK	25
+#define ASPEED_CLK_GATE_UART5CLK	26
+#define ASPEED_CLK_GATE_UART6CLK	27
+#define ASPEED_CLK_GATE_UART7CLK	28
+#define ASPEED_CLK_GATE_UART8CLK	29
+#define ASPEED_CLK_GATE_UART9CLK	30
+#define ASPEED_CLK_GATE_UART10CLK	31
+#define ASPEED_CLK_GATE_UART11CLK	32
+#define ASPEED_CLK_GATE_UART12CLK	33
+#define ASPEED_CLK_GATE_UART13CLK	34
+
+#define ASPEED_CLK_GATE_SDCLK		35
+#define ASPEED_CLK_GATE_EMMCCLK		36
+
+#define ASPEED_CLK_GATE_I3C0CLK		37
+#define ASPEED_CLK_GATE_I3C1CLK		38
+#define ASPEED_CLK_GATE_I3C2CLK		39
+#define ASPEED_CLK_GATE_I3C3CLK		40
+#define ASPEED_CLK_GATE_I3C4CLK		41
+#define ASPEED_CLK_GATE_I3C5CLK		42
+
+#define ASPEED_CLK_GATE_FSICLK		45
+
+#define ASPEED_CLK_HPLL			46
+#define ASPEED_CLK_MPLL			47
+#define ASPEED_CLK_DPLL			48
+#define ASPEED_CLK_EPLL			49
+#define ASPEED_CLK_APLL			50
+#define ASPEED_CLK_AHB			51
+#define ASPEED_CLK_APB1			52
+#define ASPEED_CLK_APB2			53
+#define ASPEED_CLK_BCLK			54
+#define ASPEED_CLK_D1CLK		55
+#define ASPEED_CLK_VCLK			56
+#define ASPEED_CLK_LHCLK		57
+#define ASPEED_CLK_UART			58
+#define ASPEED_CLK_UARTX		59
+#define ASPEED_CLK_SDIO			60
+#define ASPEED_CLK_EMMC			61
+#define ASPEED_CLK_ECLK			62
+#define ASPEED_CLK_ECLK_MUX		63
+#define ASPEED_CLK_MAC12		64
+#define ASPEED_CLK_MAC34		65
+#define ASPEED_CLK_USBPHY_40M		66
+#define ASPEED_CLK_MAC1RCLK		67
+#define ASPEED_CLK_MAC2RCLK		68
+#define ASPEED_CLK_MAC3RCLK		69
+#define ASPEED_CLK_MAC4RCLK		70
+#define ASPEED_CLK_I3C			71
+#define ASPEED_CLK_FSI			72
+
+/* Only list resets here that are not part of a clock gate + reset pair */
+#define ASPEED_RESET_ADC		55
+#define ASPEED_RESET_JTAG_MASTER2	54
+
+#define ASPEED_RESET_MAC4		53
+#define ASPEED_RESET_MAC3		52
+
+#define ASPEED_RESET_I3C5		45
+#define ASPEED_RESET_I3C4		44
+#define ASPEED_RESET_I3C3		43
+#define ASPEED_RESET_I3C2		42
+#define ASPEED_RESET_I3C1		41
+#define ASPEED_RESET_I3C0		40
+#define ASPEED_RESET_I3C		39
+#define ASPEED_RESET_I3C_DMA		39
+
+#define ASPEED_RESET_PWM		37
+#define ASPEED_RESET_PECI		36
+#define ASPEED_RESET_MII		35
+#define ASPEED_RESET_I2C		34
+#define ASPEED_RESET_H2X		31
+#define ASPEED_RESET_GP_MCU		30
+#define ASPEED_RESET_DP_MCU		29
+#define ASPEED_RESET_DP			28
+#define ASPEED_RESET_RC_XDMA		27
+#define ASPEED_RESET_GRAPHICS		26
+#define ASPEED_RESET_DEV_XDMA		25
+#define ASPEED_RESET_DEV_MCTP		24
+#define ASPEED_RESET_RC_MCTP		23
+#define ASPEED_RESET_JTAG_MASTER	22
+#define ASPEED_RESET_PCIE_DEV_O		21
+#define ASPEED_RESET_PCIE_DEV_OEN	20
+#define ASPEED_RESET_PCIE_RC_O		19
+#define ASPEED_RESET_PCIE_RC_OEN	18
+#define ASPEED_RESET_MAC2		12
+#define ASPEED_RESET_MAC1		11
+#define ASPEED_RESET_PCI_DP		5
+#define ASPEED_RESET_HACE		4
+#define ASPEED_RESET_AHB		1
+#define ASPEED_RESET_SDRAM		0
+
+#endif

linux-7.2.3/include/dt-bindings/clock/at91.h

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define PMC_TYPE_CORE		0
+#define PMC_TYPE_SYSTEM		1
+#define PMC_TYPE_PERIPHERAL	2
+#define PMC_TYPE_GCK		3
+#define PMC_TYPE_PROGRAMMABLE	4
+
+#define PMC_SLOW		0
+#define PMC_MCK			1
+#define PMC_UTMI		2
+#define PMC_MAIN		3
+#define PMC_MCK2		4
+#define PMC_I2S0_MUX		5
+#define PMC_I2S1_MUX		6
+#define PMC_PLLACK		7
+#define PMC_PLLBCK		8
+#define PMC_AUDIOPLLCK		9
+#define PMC_AUDIOPINCK		10
+
+/* SAMA7G5 */
+#define PMC_CPUPLL		(PMC_MAIN + 1)
+#define PMC_SYSPLL		(PMC_MAIN + 2)
+#define PMC_DDRPLL		(PMC_MAIN + 3)
+#define PMC_IMGPLL		(PMC_MAIN + 4)
+#define PMC_BAUDPLL		(PMC_MAIN + 5)
+#define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
+#define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
+#define PMC_ETHPLL		(PMC_MAIN + 8)
+#define PMC_CPU			(PMC_MAIN + 9)
+#define PMC_MCK1		(PMC_MAIN + 10)
+
+/* SAM9X7 */
+#define PMC_PLLADIV2		(PMC_MAIN + 11)
+#define PMC_LVDSPLL		(PMC_MAIN + 12)
+
+/* SAMA7D65 */
+#define PMC_MCK3		(PMC_MAIN + 13)
+#define PMC_MCK5		(PMC_MAIN + 14)
+
+#ifndef AT91_PMC_MOSCS
+#define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+#define AT91_PMC_LOCKA		1		/* PLLA Lock */
+#define AT91_PMC_LOCKB		2		/* PLLB Lock */
+#define AT91_PMC_MCKRDY		3		/* Master Clock */
+#define AT91_PMC_LOCKU		6		/* UPLL Lock */
+#define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
+#define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
+#define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY		24		/* Generated Clocks */
+#endif
+
+/* Slow clock. */
+#define SCKC_MD_SLCK		0
+#define SCKC_TD_SLCK		1
+
+#endif

linux-7.2.3/include/dt-bindings/clock/ath79-clk.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_CPU		0
+#define ATH79_CLK_DDR		1
+#define ATH79_CLK_AHB		2
+#define ATH79_CLK_REF		3
+#define ATH79_CLK_MDIO		4
+
+#define ATH79_CLK_END		5
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */

linux-7.2.3/include/dt-bindings/clock/axg-aoclkc.h

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_CTS_OSCIN	11
+#define CLKID_AO_32K_PRE	12
+#define CLKID_AO_32K_DIV	13
+#define CLKID_AO_32K_SEL	14
+#define CLKID_AO_32K		15
+#define CLKID_AO_CTS_RTC_OSCIN	16
+
+#endif

linux-7.2.3/include/dt-bindings/clock/axg-audio-clkc.h

@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_MCLK_SEL	59
+#define AUD_CLKID_MST_B_MCLK_SEL	60
+#define AUD_CLKID_MST_C_MCLK_SEL	61
+#define AUD_CLKID_MST_D_MCLK_SEL	62
+#define AUD_CLKID_MST_E_MCLK_SEL	63
+#define AUD_CLKID_MST_F_MCLK_SEL	64
+#define AUD_CLKID_MST_A_MCLK_DIV	65
+#define AUD_CLKID_MST_B_MCLK_DIV	66
+#define AUD_CLKID_MST_C_MCLK_DIV	67
+#define AUD_CLKID_MST_D_MCLK_DIV	68
+#define AUD_CLKID_MST_E_MCLK_DIV	69
+#define AUD_CLKID_MST_F_MCLK_DIV	70
+#define AUD_CLKID_SPDIFOUT_CLK_SEL	71
+#define AUD_CLKID_SPDIFOUT_CLK_DIV	72
+#define AUD_CLKID_SPDIFIN_CLK_SEL	73
+#define AUD_CLKID_SPDIFIN_CLK_DIV	74
+#define AUD_CLKID_PDM_DCLK_SEL		75
+#define AUD_CLKID_PDM_DCLK_DIV		76
+#define AUD_CLKID_PDM_SYSCLK_SEL	77
+#define AUD_CLKID_PDM_SYSCLK_DIV	78
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_MST_A_SCLK_PRE_EN	92
+#define AUD_CLKID_MST_B_SCLK_PRE_EN	93
+#define AUD_CLKID_MST_C_SCLK_PRE_EN	94
+#define AUD_CLKID_MST_D_SCLK_PRE_EN	95
+#define AUD_CLKID_MST_E_SCLK_PRE_EN	96
+#define AUD_CLKID_MST_F_SCLK_PRE_EN	97
+#define AUD_CLKID_MST_A_SCLK_DIV	98
+#define AUD_CLKID_MST_B_SCLK_DIV	99
+#define AUD_CLKID_MST_C_SCLK_DIV	100
+#define AUD_CLKID_MST_D_SCLK_DIV	101
+#define AUD_CLKID_MST_E_SCLK_DIV	102
+#define AUD_CLKID_MST_F_SCLK_DIV	103
+#define AUD_CLKID_MST_A_SCLK_POST_EN	104
+#define AUD_CLKID_MST_B_SCLK_POST_EN	105
+#define AUD_CLKID_MST_C_SCLK_POST_EN	106
+#define AUD_CLKID_MST_D_SCLK_POST_EN	107
+#define AUD_CLKID_MST_E_SCLK_POST_EN	108
+#define AUD_CLKID_MST_F_SCLK_POST_EN	109
+#define AUD_CLKID_MST_A_LRCLK_DIV	110
+#define AUD_CLKID_MST_B_LRCLK_DIV	111
+#define AUD_CLKID_MST_C_LRCLK_DIV	112
+#define AUD_CLKID_MST_D_LRCLK_DIV	113
+#define AUD_CLKID_MST_E_LRCLK_DIV	114
+#define AUD_CLKID_MST_F_LRCLK_DIV	115
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN	137
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN	138
+#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN	139
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN	140
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN	141
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN	142
+#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN	143
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN	144
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN	145
+#define AUD_CLKID_TDMIN_C_SCLK_POST_EN	146
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN	147
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN	148
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN	149
+#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN	150
+#define AUD_CLKID_SPDIFOUT_B		151
+#define AUD_CLKID_SPDIFOUT_B_CLK	152
+#define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153
+#define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154
+#define AUD_CLKID_TDM_MCLK_PAD0		155
+#define AUD_CLKID_TDM_MCLK_PAD1		156
+#define AUD_CLKID_TDM_LRCLK_PAD0	157
+#define AUD_CLKID_TDM_LRCLK_PAD1	158
+#define AUD_CLKID_TDM_LRCLK_PAD2	159
+#define AUD_CLKID_TDM_SCLK_PAD0		160
+#define AUD_CLKID_TDM_SCLK_PAD1		161
+#define AUD_CLKID_TDM_SCLK_PAD2		162
+#define AUD_CLKID_TOP			163
+#define AUD_CLKID_TORAM			164
+#define AUD_CLKID_EQDRC			165
+#define AUD_CLKID_RESAMPLE_B		166
+#define AUD_CLKID_TOVAD			167
+#define AUD_CLKID_LOCKER		168
+#define AUD_CLKID_SPDIFIN_LB		169
+#define AUD_CLKID_FRDDR_D		170
+#define AUD_CLKID_TODDR_D		171
+#define AUD_CLKID_LOOPBACK_B		172
+#define AUD_CLKID_CLK81_EN		173
+#define AUD_CLKID_SYSCLK_A_DIV		174
+#define AUD_CLKID_SYSCLK_B_DIV		175
+#define AUD_CLKID_SYSCLK_A_EN		176
+#define AUD_CLKID_SYSCLK_B_EN		177
+#define AUD_CLKID_EARCRX		178
+#define AUD_CLKID_EARCRX_CMDC_SEL	179
+#define AUD_CLKID_EARCRX_CMDC_DIV	180
+#define AUD_CLKID_EARCRX_CMDC		181
+#define AUD_CLKID_EARCRX_DMAC_SEL	182
+#define AUD_CLKID_EARCRX_DMAC_DIV	183
+#define AUD_CLKID_EARCRX_DMAC		184
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

linux-7.2.3/include/dt-bindings/clock/axg-clkc.h

@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_MPEG_SEL				8
+#define CLKID_MPEG_DIV				9
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_SD_EMMC_B_CLK0_SEL		61
+#define CLKID_SD_EMMC_B_CLK0_DIV		62
+#define CLKID_SD_EMMC_C_CLK0_SEL		63
+#define CLKID_SD_EMMC_C_CLK0_DIV		64
+#define CLKID_MPLL0_DIV				65
+#define CLKID_MPLL1_DIV				66
+#define CLKID_MPLL2_DIV				67
+#define CLKID_MPLL3_DIV				68
+#define CLKID_HIFI_PLL				69
+#define CLKID_MPLL_PREDIV			70
+#define CLKID_FCLK_DIV2_DIV			71
+#define CLKID_FCLK_DIV3_DIV			72
+#define CLKID_FCLK_DIV4_DIV			73
+#define CLKID_FCLK_DIV5_DIV			74
+#define CLKID_FCLK_DIV7_DIV			75
+#define CLKID_PCIE_PLL				76
+#define CLKID_PCIE_MUX				77
+#define CLKID_PCIE_REF				78
+#define CLKID_PCIE_CML_EN0			79
+#define CLKID_PCIE_CML_EN1			80
+#define CLKID_GEN_CLK_SEL			82
+#define CLKID_GEN_CLK_DIV			83
+#define CLKID_GEN_CLK				84
+#define CLKID_SYS_PLL_DCO			85
+#define CLKID_FIXED_PLL_DCO			86
+#define CLKID_GP0_PLL_DCO			87
+#define CLKID_HIFI_PLL_DCO			88
+#define CLKID_PCIE_PLL_DCO			89
+#define CLKID_PCIE_PLL_OD			90
+#define CLKID_VPU_0_DIV				91
+#define CLKID_VPU_0_SEL				92
+#define CLKID_VPU_0				93
+#define CLKID_VPU_1_DIV				94
+#define CLKID_VPU_1_SEL				95
+#define CLKID_VPU_1				96
+#define CLKID_VPU				97
+#define CLKID_VAPB_0_DIV			98
+#define CLKID_VAPB_0_SEL			99
+#define CLKID_VAPB_0				100
+#define CLKID_VAPB_1_DIV			101
+#define CLKID_VAPB_1_SEL			102
+#define CLKID_VAPB_1				103
+#define CLKID_VAPB_SEL				104
+#define CLKID_VAPB				105
+#define CLKID_VCLK				106
+#define CLKID_VCLK2				107
+#define CLKID_VCLK_SEL				108
+#define CLKID_VCLK2_SEL				109
+#define CLKID_VCLK_INPUT			110
+#define CLKID_VCLK2_INPUT			111
+#define CLKID_VCLK_DIV				112
+#define CLKID_VCLK2_DIV				113
+#define CLKID_VCLK_DIV2_EN			114
+#define CLKID_VCLK_DIV4_EN			115
+#define CLKID_VCLK_DIV6_EN			116
+#define CLKID_VCLK_DIV12_EN			117
+#define CLKID_VCLK2_DIV2_EN			118
+#define CLKID_VCLK2_DIV4_EN			119
+#define CLKID_VCLK2_DIV6_EN			120
+#define CLKID_VCLK2_DIV12_EN			121
+#define CLKID_VCLK_DIV1				122
+#define CLKID_VCLK_DIV2				123
+#define CLKID_VCLK_DIV4				124
+#define CLKID_VCLK_DIV6				125
+#define CLKID_VCLK_DIV12			126
+#define CLKID_VCLK2_DIV1			127
+#define CLKID_VCLK2_DIV2			128
+#define CLKID_VCLK2_DIV4			129
+#define CLKID_VCLK2_DIV6			130
+#define CLKID_VCLK2_DIV12			131
+#define CLKID_CTS_ENCL_SEL			132
+#define CLKID_CTS_ENCL				133
+#define CLKID_VDIN_MEAS_SEL			134
+#define CLKID_VDIN_MEAS_DIV			135
+#define CLKID_VDIN_MEAS				136
+
+#endif /* __AXG_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/axis,artpec6-clkctrl.h

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Communications AB.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU			0
+#define ARTPEC6_CLK_CPU_PERIPH		1
+#define ARTPEC6_CLK_NAND_CLKA		2
+#define ARTPEC6_CLK_NAND_CLKB		3
+#define ARTPEC6_CLK_ETH_ACLK		4
+#define ARTPEC6_CLK_DMA_ACLK		5
+#define ARTPEC6_CLK_PTP_REF		6
+#define ARTPEC6_CLK_SD_PCLK		7
+#define ARTPEC6_CLK_SD_IMCLK		8
+#define ARTPEC6_CLK_I2S_HST		9
+#define ARTPEC6_CLK_I2S0_CLK		10
+#define ARTPEC6_CLK_I2S1_CLK		11
+#define ARTPEC6_CLK_UART_PCLK		12
+#define ARTPEC6_CLK_UART_REFCLK		13
+#define ARTPEC6_CLK_I2C			14
+#define ARTPEC6_CLK_SPI_PCLK		15
+#define ARTPEC6_CLK_SPI_SSPCLK		16
+#define ARTPEC6_CLK_SYS_TIMER		17
+#define ARTPEC6_CLK_FRACDIV_IN		18
+#define ARTPEC6_CLK_DBG_PCLK		19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS		20
+
+#endif

linux-7.2.3/include/dt-bindings/clock/axis,artpec8-clk.h

@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025 Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-8 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
+#define _DT_BINDINGS_CLOCK_ARTPEC8_H
+
+/* CMU_CMU */
+#define CLK_FOUT_SHARED0_PLL					1
+#define CLK_DOUT_SHARED0_DIV2					2
+#define CLK_DOUT_SHARED0_DIV3					3
+#define CLK_DOUT_SHARED0_DIV4					4
+#define CLK_FOUT_SHARED1_PLL					5
+#define CLK_DOUT_SHARED1_DIV2					6
+#define CLK_DOUT_SHARED1_DIV3					7
+#define CLK_DOUT_SHARED1_DIV4					8
+#define CLK_FOUT_AUDIO_PLL					9
+#define CLK_DOUT_CMU_BUS					10
+#define CLK_DOUT_CMU_BUS_DLP					11
+#define CLK_DOUT_CMU_CDC_CORE					12
+#define CLK_DOUT_CMU_OTP					13
+#define CLK_DOUT_CMU_CORE_MAIN					14
+#define CLK_DOUT_CMU_CORE_DLP					15
+#define CLK_DOUT_CMU_CPUCL_SWITCH				16
+#define CLK_DOUT_CMU_DLP_CORE					17
+#define CLK_DOUT_CMU_FSYS_BUS					18
+#define CLK_DOUT_CMU_FSYS_IP					19
+#define CLK_DOUT_CMU_FSYS_SCAN0					20
+#define CLK_DOUT_CMU_FSYS_SCAN1					21
+#define CLK_DOUT_CMU_GPU_3D					22
+#define CLK_DOUT_CMU_GPU_2D					23
+#define CLK_DOUT_CMU_IMEM_ACLK					24
+#define CLK_DOUT_CMU_IMEM_JPEG					25
+#define CLK_DOUT_CMU_MIF_SWITCH					26
+#define CLK_DOUT_CMU_MIF_BUSP					27
+#define CLK_DOUT_CMU_PERI_DISP					28
+#define CLK_DOUT_CMU_PERI_IP					29
+#define CLK_DOUT_CMU_PERI_AUDIO					30
+#define CLK_DOUT_CMU_RSP_CORE					31
+#define CLK_DOUT_CMU_TRFM_CORE					32
+#define CLK_DOUT_CMU_VCA_ACE					33
+#define CLK_DOUT_CMU_VCA_OD					34
+#define CLK_DOUT_CMU_VIO_CORE					35
+#define CLK_DOUT_CMU_VIO_AUDIO					36
+#define CLK_DOUT_CMU_VIP0_CORE					37
+#define CLK_DOUT_CMU_VIP1_CORE					38
+#define CLK_DOUT_CMU_VPP_CORE					39
+
+/* CMU_BUS */
+#define CLK_MOUT_BUS_ACLK_USER					1
+#define CLK_MOUT_BUS_DLP_USER					2
+#define CLK_DOUT_BUS_PCLK					3
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_ACLK_USER					1
+#define CLK_MOUT_CORE_DLP_USER					2
+#define CLK_DOUT_CORE_PCLK					3
+
+/* CMU_CPUCL */
+#define CLK_FOUT_CPUCL_PLL					1
+#define CLK_MOUT_CPUCL_PLL					2
+#define CLK_MOUT_CPUCL_SWITCH_USER				3
+#define CLK_DOUT_CPUCL_CPU					4
+#define CLK_DOUT_CPUCL_CLUSTER_ACLK				5
+#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG				6
+#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK				7
+#define CLK_DOUT_CPUCL_CLUSTER_ATCLK				8
+#define CLK_DOUT_CPUCL_PCLK					9
+#define CLK_DOUT_CPUCL_CMUREF					10
+#define CLK_DOUT_CPUCL_DBG					11
+#define CLK_DOUT_CPUCL_PCLKDBG					12
+#define CLK_GOUT_CPUCL_CLUSTER_CPU				13
+#define CLK_GOUT_CPUCL_SHORTSTOP				14
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG			15
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK			16
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_PLL					1
+#define CLK_MOUT_FSYS_SCAN0_USER				2
+#define CLK_MOUT_FSYS_SCAN1_USER				3
+#define CLK_MOUT_FSYS_BUS_USER					4
+#define CLK_MOUT_FSYS_MMC_USER					5
+#define CLK_DOUT_FSYS_PCIE_PIPE					6
+#define CLK_DOUT_FSYS_ADC					7
+#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL			8
+#define CLK_DOUT_FSYS_EQOS_INT125				9
+#define CLK_DOUT_FSYS_OTP_MEM					10
+#define CLK_DOUT_FSYS_SCLK_UART					11
+#define CLK_DOUT_FSYS_EQOS_25					12
+#define CLK_DOUT_FSYS_EQOS_2p5					13
+#define CLK_DOUT_FSYS_BUS300					14
+#define CLK_DOUT_FSYS_BUS_QSPI					15
+#define CLK_DOUT_FSYS_MMC_CARD0					16
+#define CLK_DOUT_FSYS_MMC_CARD1					17
+#define CLK_DOUT_SCAN_CLK_FSYS_125				18
+#define CLK_DOUT_FSYS_QSPI					19
+#define CLK_DOUT_FSYS_SFMC_NAND					20
+#define CLK_DOUT_FSYS_SCAN_CLK_MMC				21
+#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20	22
+#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY		23
+#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK			24
+#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK			25
+#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK			26
+#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK			27
+#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0			28
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG		29
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG		30
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG		31
+#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK		32
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I			33
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I		34
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5	35
+#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND		36
+#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN			37
+#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK			38
+#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN			39
+#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK			40
+#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN			41
+#define CLK_GOUT_FSYS_UART0_PCLK				42
+#define CLK_GOUT_FSYS_UART0_SCLK_UART				43
+#define CLK_GOUT_FSYS_BUS_QSPI					44
+#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK			45
+#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK			46
+
+/* CMU_IMEM */
+#define CLK_MOUT_IMEM_ACLK_USER					1
+#define CLK_MOUT_IMEM_GIC_CA53					2
+#define CLK_MOUT_IMEM_GIC_CA5					3
+#define CLK_MOUT_IMEM_JPEG_USER					4
+#define CLK_GOUT_IMEM_MCT_PCLK					5
+#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF				6
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_IP_USER					1
+#define CLK_MOUT_PERI_AUDIO_USER				2
+#define CLK_MOUT_PERI_I2S0					3
+#define CLK_MOUT_PERI_I2S1					4
+#define CLK_MOUT_PERI_DISP_USER					5
+#define CLK_DOUT_PERI_SPI					6
+#define CLK_DOUT_PERI_UART1					7
+#define CLK_DOUT_PERI_UART2					8
+#define CLK_DOUT_PERI_PCLK					9
+#define CLK_DOUT_PERI_I2S0					10
+#define CLK_DOUT_PERI_I2S1					11
+#define CLK_DOUT_PERI_DSIM					12
+#define CLK_GOUT_PERI_UART1_PCLK				13
+#define CLK_GOUT_PERI_UART1_SCLK_UART				14
+#define CLK_GOUT_PERI_UART2_PCLK				15
+#define CLK_GOUT_PERI_UART2_SCLK_UART				16
+#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK			17
+#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK			18
+#define CLK_GOUT_PERI_SPI0_PCLK					19
+#define CLK_GOUT_PERI_SPI0_SCLK_SPI				20
+#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS		21
+#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST			22
+#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST			23
+#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK			24
+#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK			25
+#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK			26
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK		27
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK		28
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */

linux-7.2.3/include/dt-bindings/clock/axis,artpec9-clk.h

@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025  Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-9 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H
+#define _DT_BINDINGS_CLOCK_ARTPEC9_H
+
+/* CMU_CMU */
+#define CLK_FOUT_SHARED0_PLL						1
+#define CLK_DOUT_SHARED0_DIV2						2
+#define CLK_DOUT_SHARED0_DIV3						3
+#define CLK_DOUT_SHARED0_DIV4						4
+#define CLK_FOUT_SHARED1_PLL						5
+#define CLK_DOUT_SHARED1_DIV2						6
+#define CLK_DOUT_SHARED1_DIV3						7
+#define CLK_DOUT_SHARED1_DIV4						8
+#define CLK_FOUT_AUDIO_PLL						9
+#define CLK_DOUT_CMU_ADD						10
+#define CLK_DOUT_CMU_BUS						11
+#define CLK_DOUT_CMU_CDC_CORE						12
+#define CLK_DOUT_CMU_CORE_MAIN						13
+#define CLK_DOUT_CMU_CPUCL_SWITCH					14
+#define CLK_DOUT_CMU_DLP_CORE						15
+#define CLK_DOUT_CMU_FSYS0_BUS						16
+#define CLK_DOUT_CMU_FSYS0_IP						17
+#define CLK_DOUT_CMU_FSYS1_BUS						18
+#define CLK_DOUT_CMU_FSYS1_SCAN0					19
+#define CLK_DOUT_CMU_FSYS1_SCAN1					20
+#define CLK_DOUT_CMU_GPU_3D						21
+#define CLK_DOUT_CMU_GPU_2D						22
+#define CLK_DOUT_CMU_IMEM_ACLK						23
+#define CLK_DOUT_CMU_IMEM_CA5						24
+#define CLK_DOUT_CMU_IMEM_JPEG						25
+#define CLK_DOUT_CMU_IMEM_SSS						26
+#define CLK_DOUT_CMU_IPA_CORE						27
+#define CLK_DOUT_CMU_LCPU						28
+#define CLK_DOUT_CMU_MIF_SWITCH						29
+#define CLK_DOUT_CMU_MIF_BUSP						30
+#define CLK_DOUT_CMU_PERI_DISP						31
+#define CLK_DOUT_CMU_PERI_IP						32
+#define CLK_DOUT_CMU_RSP_CORE						33
+#define CLK_DOUT_CMU_TRFM						34
+#define CLK_DOUT_CMU_VIO_CORE_L						35
+#define CLK_DOUT_CMU_VIO_CORE						36
+#define CLK_DOUT_CMU_VIP0						37
+#define CLK_DOUT_CMU_VIP1						38
+#define CLK_DOUT_CMU_VPP_CORE						39
+#define CLK_DOUT_CMU_VIO_AUDIO						40
+
+/* CMU_BUS */
+#define CLK_MOUT_BUS_ACLK_USER						1
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_ACLK_USER						1
+
+/* CMU_CPUCL */
+#define CLK_FOUT_CPUCL_PLL0						1
+#define CLK_MOUT_CPUCL_PLL0						2
+#define CLK_FOUT_CPUCL_PLL1						3
+#define CLK_MOUT_CPUCL_PLL_SCU						4
+#define CLK_MOUT_CPUCL_SWITCH_SCU_USER					5
+#define CLK_MOUT_CPUCL_SWITCH_USER					6
+#define CLK_DOUT_CPUCL_CPU						7
+#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK				8
+#define CLK_DOUT_CPUCL_CLUSTER_GICCLK					9
+#define CLK_DOUT_CPUCL_CLUSTER_PCLK					10
+#define CLK_DOUT_CPUCL_CMUREF						11
+#define CLK_DOUT_CPUCL_CLUSTER_ATCLK					12
+#define CLK_DOUT_CPUCL_CLUSTER_SCU					13
+#define CLK_DOUT_CPUCL_DBG						14
+#define CLK_GOUT_CPUCL_SHORTSTOP					15
+#define CLK_GOUT_CPUCL_CLUSTER_CPU					16
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK				17
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG				18
+
+/* CMU_FSYS0 */
+#define CLK_MOUT_FSYS0_BUS_USER						1
+#define CLK_MOUT_FSYS0_IP_USER						2
+#define CLK_MOUT_FSYS0_MAIN_USER					3
+#define CLK_DOUT_FSYS0_125						4
+#define CLK_DOUT_FSYS0_ADC						5
+#define CLK_DOUT_FSYS0_BUS_300						6
+#define CLK_DOUT_FSYS0_EQOS0						7
+#define CLK_DOUT_FSYS0_EQOS1						8
+#define CLK_DOUT_FSYS0_MMC_CARD0					9
+#define CLK_DOUT_FSYS0_MMC_CARD1					10
+#define CLK_DOUT_FSYS0_MMC_CARD2					11
+#define CLK_DOUT_FSYS0_QSPI						12
+#define CLK_DOUT_FSYS0_SFMC_NAND					13
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I			14
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I			15
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250	16
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK		17
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250	18
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK		19
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I			20
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I			21
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK			22
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK			23
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK				24
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK			25
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK			26
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK			27
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK				28
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK			29
+#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN				30
+#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN				31
+#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN				32
+#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK				33
+#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK				34
+#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND			35
+#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK				36
+#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK				37
+#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK				38
+#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK				39
+#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK				40
+#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0				41
+
+/* CMU_FSYS1 */
+#define CLK_FOUT_FSYS1_PLL						1
+#define CLK_MOUT_FSYS1_SCAN0_USER					2
+#define CLK_MOUT_FSYS1_SCAN1_USER					3
+#define CLK_MOUT_FSYS1_BUS_USER						4
+#define CLK_DOUT_FSYS1_200						5
+#define CLK_DOUT_FSYS1_BUS_300						6
+#define CLK_DOUT_FSYS1_OTP_MEM						7
+#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL				8
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100		9
+#define CLK_GOUT_FSYS1_UART0_PCLK					10
+#define CLK_GOUT_FSYS1_UART0_SCLK_UART					11
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300		12
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC		13
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC		14
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC		15
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC		16
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC		17
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC		18
+#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20		19
+#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY			20
+#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK			21
+#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK				22
+
+/* CMU_IMEM */
+#define CLK_MOUT_IMEM_ACLK_USER						1
+#define CLK_MOUT_IMEM_CA5_USER						2
+#define CLK_MOUT_IMEM_SSS_USER						3
+#define CLK_MOUT_IMEM_JPEG_USER						4
+#define CLK_DOUT_IMEM_PCLK						5
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK				6
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN				7
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG				8
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK				9
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN				10
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG				11
+#define CLK_GOUT_IMEM_MCT0_PCLK						12
+#define CLK_GOUT_IMEM_MCT1_PCLK						13
+#define CLK_GOUT_IMEM_MCT2_PCLK						14
+#define CLK_GOUT_IMEM_MCT3_PCLK						15
+#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF					16
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_IP_USER						1
+#define CLK_MOUT_PERI_DISP_USER						2
+#define CLK_DOUT_PERI_125						3
+#define CLK_DOUT_PERI_PCLK						4
+#define CLK_DOUT_PERI_SPI						5
+#define CLK_DOUT_PERI_UART1						6
+#define CLK_DOUT_PERI_UART2						7
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK			8
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK			9
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK			10
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK				11
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK				12
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK			13
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK			14
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK				15
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK				16
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK			17
+#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS			18
+#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK				19
+#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK				20
+#define CLK_GOUT_PERI_SPI0_PCLK						21
+#define CLK_GOUT_PERI_SPI0_SCLK_SPI					22
+#define CLK_GOUT_PERI_UART1_PCLK					23
+#define CLK_GOUT_PERI_UART1_SCLK_UART					24
+#define CLK_GOUT_PERI_UART2_PCLK					25
+#define CLK_GOUT_PERI_UART2_SCLK_UART					26
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */

linux-7.2.3/include/dt-bindings/clock/bcm-cygnus.h

@@ -0,0 +1,74 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_CYGNUS_H
+#define _CLOCK_BCM_CYGNUS_H
+
+/* GENPLL clock ID */
+#define BCM_CYGNUS_GENPLL                     0
+#define BCM_CYGNUS_GENPLL_AXI21_CLK           1
+#define BCM_CYGNUS_GENPLL_250MHZ_CLK          2
+#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK       3
+#define BCM_CYGNUS_GENPLL_ENET_SW_CLK         4
+#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK       5
+#define BCM_CYGNUS_GENPLL_CAN_CLK             6
+
+/* LCPLL0 clock ID */
+#define BCM_CYGNUS_LCPLL0                     0
+#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK    1
+#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK         2
+#define BCM_CYGNUS_LCPLL0_SDIO_CLK            3
+#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK     4
+#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK      5
+#define BCM_CYGNUS_LCPLL0_CH5_UNUSED          6
+
+/* MIPI PLL clock ID */
+#define BCM_CYGNUS_MIPIPLL                    0
+#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED         1
+#define BCM_CYGNUS_MIPIPLL_CH1_LCD            2
+#define BCM_CYGNUS_MIPIPLL_CH2_V3D            3
+#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED         4
+#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED         5
+#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED         6
+
+/* ASIU clock ID */
+#define BCM_CYGNUS_ASIU_KEYPAD_CLK    0
+#define BCM_CYGNUS_ASIU_ADC_CLK       1
+#define BCM_CYGNUS_ASIU_PWM_CLK       2
+
+/* AUDIO clock ID */
+#define BCM_CYGNUS_AUDIOPLL           0
+#define BCM_CYGNUS_AUDIOPLL_CH0       1
+#define BCM_CYGNUS_AUDIOPLL_CH1       2
+#define BCM_CYGNUS_AUDIOPLL_CH2       3
+
+#endif /* _CLOCK_BCM_CYGNUS_H */

linux-7.2.3/include/dt-bindings/clock/bcm-ns2.h

@@ -0,0 +1,72 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NS2_H
+#define _CLOCK_BCM_NS2_H
+
+/* GENPLL SCR clock channel ID */
+#define BCM_NS2_GENPLL_SCR		0
+#define BCM_NS2_GENPLL_SCR_SCR_CLK	1
+#define BCM_NS2_GENPLL_SCR_FS_CLK	2
+#define BCM_NS2_GENPLL_SCR_AUDIO_CLK	3
+#define BCM_NS2_GENPLL_SCR_CH3_UNUSED	4
+#define BCM_NS2_GENPLL_SCR_CH4_UNUSED	5
+#define BCM_NS2_GENPLL_SCR_CH5_UNUSED	6
+
+/* GENPLL SW clock channel ID */
+#define BCM_NS2_GENPLL_SW		0
+#define BCM_NS2_GENPLL_SW_RPE_CLK	1
+#define BCM_NS2_GENPLL_SW_250_CLK	2
+#define BCM_NS2_GENPLL_SW_NIC_CLK	3
+#define BCM_NS2_GENPLL_SW_CHIMP_CLK	4
+#define BCM_NS2_GENPLL_SW_PORT_CLK	5
+#define BCM_NS2_GENPLL_SW_SDIO_CLK	6
+
+/* LCPLL DDR clock channel ID */
+#define BCM_NS2_LCPLL_DDR		0
+#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK	1
+#define BCM_NS2_LCPLL_DDR_DDR_CLK	2
+#define BCM_NS2_LCPLL_DDR_CH2_UNUSED	3
+#define BCM_NS2_LCPLL_DDR_CH3_UNUSED	4
+#define BCM_NS2_LCPLL_DDR_CH4_UNUSED	5
+#define BCM_NS2_LCPLL_DDR_CH5_UNUSED	6
+
+/* LCPLL PORTS clock channel ID */
+#define BCM_NS2_LCPLL_PORTS		0
+#define BCM_NS2_LCPLL_PORTS_WAN_CLK	1
+#define BCM_NS2_LCPLL_PORTS_RGMII_CLK	2
+#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED	3
+#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED	4
+#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED	5
+#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED	6
+
+#endif /* _CLOCK_BCM_NS2_H */

linux-7.2.3/include/dt-bindings/clock/bcm-nsp.h

@@ -0,0 +1,51 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *	* Redistributions of source code must retain the above copyright
+ *	  notice, this list of conditions and the following disclaimer.
+ *	* Redistributions in binary form must reproduce the above copyright
+ *	  notice, this list of conditions and the following disclaimer in
+ *	  the documentation and/or other materials provided with the
+ *	  distribution.
+ *	* Neither the name of Broadcom Corporation nor the names of its
+ *	  contributors may be used to endorse or promote products derived
+ *	  from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL			0
+#define BCM_NSP_GENPLL_PHY_CLK		1
+#define BCM_NSP_GENPLL_ENET_SW_CLK	2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK	4
+#define BCM_NSP_GENPLL_SATA1_CLK	5
+#define BCM_NSP_GENPLL_SATA2_CLK	6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0			0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1
+#define BCM_NSP_LCPLL0_SDIO_CLK		2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3
+
+#endif /* _CLOCK_BCM_NSP_H */

linux-7.2.3/include/dt-bindings/clock/bcm-sr.h

@@ -0,0 +1,111 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_SR_H
+#define _CLOCK_BCM_SR_H
+
+/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
+#define BCM_SR_GENPLL0			0
+#define BCM_SR_GENPLL0_125M_CLK		1
+#define BCM_SR_GENPLL0_SCR_CLK		2
+#define BCM_SR_GENPLL0_250M_CLK		3
+#define BCM_SR_GENPLL0_PCIE_AXI_CLK	4
+#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK	5
+#define BCM_SR_GENPLL0_PAXC_AXI_CLK	6
+
+/* GENPLL 1 clock channel ID MHB PCIE NITRO */
+#define BCM_SR_GENPLL1			0
+#define BCM_SR_GENPLL1_PCIE_TL_CLK	1
+#define BCM_SR_GENPLL1_MHB_APB_CLK	2
+
+/* GENPLL 2 clock channel ID NITRO MHB*/
+#define BCM_SR_GENPLL2			0
+#define BCM_SR_GENPLL2_NIC_CLK		1
+#define BCM_SR_GENPLL2_TS_500_CLK	2
+#define BCM_SR_GENPLL2_125_NITRO_CLK	3
+#define BCM_SR_GENPLL2_CHIMP_CLK	4
+#define BCM_SR_GENPLL2_NIC_FLASH_CLK	5
+#define BCM_SR_GENPLL2_FS4_CLK		6
+
+/* GENPLL 3 HSLS clock channel ID */
+#define BCM_SR_GENPLL3			0
+#define BCM_SR_GENPLL3_HSLS_CLK		1
+#define BCM_SR_GENPLL3_SDIO_CLK		2
+
+/* GENPLL 4 SCR clock channel ID */
+#define BCM_SR_GENPLL4			0
+#define BCM_SR_GENPLL4_CCN_CLK		1
+#define BCM_SR_GENPLL4_TPIU_PLL_CLK	2
+#define BCM_SR_GENPLL4_NOC_CLK		3
+#define BCM_SR_GENPLL4_CHCLK_FS4_CLK	4
+#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK	5
+
+/* GENPLL 5 FS4 clock channel ID */
+#define BCM_SR_GENPLL5			0
+#define BCM_SR_GENPLL5_FS4_HF_CLK	1
+#define BCM_SR_GENPLL5_CRYPTO_AE_CLK	2
+#define BCM_SR_GENPLL5_RAID_AE_CLK	3
+
+/* GENPLL 6 NITRO clock channel ID */
+#define BCM_SR_GENPLL6			0
+#define BCM_SR_GENPLL6_48_USB_CLK	1
+
+/* LCPLL0  clock channel ID */
+#define BCM_SR_LCPLL0			0
+#define BCM_SR_LCPLL0_SATA_REFP_CLK	1
+#define BCM_SR_LCPLL0_SATA_REFN_CLK	2
+#define BCM_SR_LCPLL0_SATA_350_CLK	3
+#define BCM_SR_LCPLL0_SATA_500_CLK	4
+
+/* LCPLL1  clock channel ID */
+#define BCM_SR_LCPLL1			0
+#define BCM_SR_LCPLL1_WAN_CLK		1
+#define BCM_SR_LCPLL1_USB_REF_CLK	2
+#define BCM_SR_LCPLL1_CRMU_TS_CLK	3
+
+/* LCPLL PCIE  clock channel ID */
+#define BCM_SR_LCPLL_PCIE		0
+#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL0			0
+#define BCM_SR_EMEMPLL0_EMEM_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL1			0
+#define BCM_SR_EMEMPLL1_EMEM_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL2			0
+#define BCM_SR_EMEMPLL2_EMEM_CLK	1
+
+#endif /* _CLOCK_BCM_SR_H */

linux-7.2.3/include/dt-bindings/clock/bcm21664.h

@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ */
+
+#ifndef _CLOCK_BCM21664_H
+#define _CLOCK_BCM21664_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
+ */
+
+/* bcm21664 CCU device tree "compatible" strings */
+#define BCM21664_DT_ROOT_CCU_COMPAT	"brcm,bcm21664-root-ccu"
+#define BCM21664_DT_AON_CCU_COMPAT	"brcm,bcm21664-aon-ccu"
+#define BCM21664_DT_MASTER_CCU_COMPAT	"brcm,bcm21664-master-ccu"
+#define BCM21664_DT_SLAVE_CCU_COMPAT	"brcm,bcm21664-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM21664_ROOT_CCU_FRAC_1M		0
+#define BCM21664_ROOT_CCU_CLOCK_COUNT		1
+
+/* aon CCU clock ids */
+
+#define BCM21664_AON_CCU_HUB_TIMER		0
+#define BCM21664_AON_CCU_CLOCK_COUNT		1
+
+/* master CCU clock ids */
+
+#define BCM21664_MASTER_CCU_SDIO1		0
+#define BCM21664_MASTER_CCU_SDIO2		1
+#define BCM21664_MASTER_CCU_SDIO3		2
+#define BCM21664_MASTER_CCU_SDIO4		3
+#define BCM21664_MASTER_CCU_SDIO1_SLEEP		4
+#define BCM21664_MASTER_CCU_SDIO2_SLEEP		5
+#define BCM21664_MASTER_CCU_SDIO3_SLEEP		6
+#define BCM21664_MASTER_CCU_SDIO4_SLEEP		7
+#define BCM21664_MASTER_CCU_CLOCK_COUNT		8
+
+/* slave CCU clock ids */
+
+#define BCM21664_SLAVE_CCU_UARTB		0
+#define BCM21664_SLAVE_CCU_UARTB2		1
+#define BCM21664_SLAVE_CCU_UARTB3		2
+#define BCM21664_SLAVE_CCU_BSC1			3
+#define BCM21664_SLAVE_CCU_BSC2			4
+#define BCM21664_SLAVE_CCU_BSC3			5
+#define BCM21664_SLAVE_CCU_BSC4			6
+#define BCM21664_SLAVE_CCU_CLOCK_COUNT		7
+
+#endif /* _CLOCK_BCM21664_H */

linux-7.2.3/include/dt-bindings/clock/bcm281xx.h

@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ */
+
+#ifndef _CLOCK_BCM281XX_H
+#define _CLOCK_BCM281XX_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
+ */
+
+/*
+ * These are the bcm281xx CCU device tree "compatible" strings.
+ * We're stuck with using "bcm11351" in the string because wild
+ * cards aren't allowed, and that name was the first one defined
+ * in this family of devices.
+ */
+#define BCM281XX_DT_ROOT_CCU_COMPAT	"brcm,bcm11351-root-ccu"
+#define BCM281XX_DT_AON_CCU_COMPAT	"brcm,bcm11351-aon-ccu"
+#define BCM281XX_DT_HUB_CCU_COMPAT	"brcm,bcm11351-hub-ccu"
+#define BCM281XX_DT_MASTER_CCU_COMPAT	"brcm,bcm11351-master-ccu"
+#define BCM281XX_DT_SLAVE_CCU_COMPAT	"brcm,bcm11351-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM281XX_ROOT_CCU_FRAC_1M		0
+#define BCM281XX_ROOT_CCU_CLOCK_COUNT		1
+
+/* aon CCU clock ids */
+
+#define BCM281XX_AON_CCU_HUB_TIMER		0
+#define BCM281XX_AON_CCU_PMU_BSC		1
+#define BCM281XX_AON_CCU_PMU_BSC_VAR		2
+#define BCM281XX_AON_CCU_CLOCK_COUNT		3
+
+/* hub CCU clock ids */
+
+#define BCM281XX_HUB_CCU_TMON_1M		0
+#define BCM281XX_HUB_CCU_CLOCK_COUNT		1
+
+/* master CCU clock ids */
+
+#define BCM281XX_MASTER_CCU_SDIO1		0
+#define BCM281XX_MASTER_CCU_SDIO2		1
+#define BCM281XX_MASTER_CCU_SDIO3		2
+#define BCM281XX_MASTER_CCU_SDIO4		3
+#define BCM281XX_MASTER_CCU_USB_IC		4
+#define BCM281XX_MASTER_CCU_HSIC2_48M		5
+#define BCM281XX_MASTER_CCU_HSIC2_12M		6
+#define BCM281XX_MASTER_CCU_CLOCK_COUNT		7
+
+/* slave CCU clock ids */
+
+#define BCM281XX_SLAVE_CCU_UARTB		0
+#define BCM281XX_SLAVE_CCU_UARTB2		1
+#define BCM281XX_SLAVE_CCU_UARTB3		2
+#define BCM281XX_SLAVE_CCU_UARTB4		3
+#define BCM281XX_SLAVE_CCU_SSP0			4
+#define BCM281XX_SLAVE_CCU_SSP2			5
+#define BCM281XX_SLAVE_CCU_BSC1			6
+#define BCM281XX_SLAVE_CCU_BSC2			7
+#define BCM281XX_SLAVE_CCU_BSC3			8
+#define BCM281XX_SLAVE_CCU_PWM			9
+#define BCM281XX_SLAVE_CCU_CLOCK_COUNT		10
+
+#endif /* _CLOCK_BCM281XX_H */

linux-7.2.3/include/dt-bindings/clock/bcm2835-aux.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ */
+
+#define BCM2835_AUX_CLOCK_UART		0
+#define BCM2835_AUX_CLOCK_SPI1		1
+#define BCM2835_AUX_CLOCK_SPI2		2
+#define BCM2835_AUX_CLOCK_COUNT		3

linux-7.2.3/include/dt-bindings/clock/bcm2835.h

@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ */
+
+#define BCM2835_PLLA			0
+#define BCM2835_PLLB			1
+#define BCM2835_PLLC			2
+#define BCM2835_PLLD			3
+#define BCM2835_PLLH			4
+
+#define BCM2835_PLLA_CORE		5
+#define BCM2835_PLLA_PER		6
+#define BCM2835_PLLB_ARM		7
+#define BCM2835_PLLC_CORE0		8
+#define BCM2835_PLLC_CORE1		9
+#define BCM2835_PLLC_CORE2		10
+#define BCM2835_PLLC_PER		11
+#define BCM2835_PLLD_CORE		12
+#define BCM2835_PLLD_PER		13
+#define BCM2835_PLLH_RCAL		14
+#define BCM2835_PLLH_AUX		15
+#define BCM2835_PLLH_PIX		16
+
+#define BCM2835_CLOCK_TIMER		17
+#define BCM2835_CLOCK_OTP		18
+#define BCM2835_CLOCK_UART		19
+#define BCM2835_CLOCK_VPU		20
+#define BCM2835_CLOCK_V3D		21
+#define BCM2835_CLOCK_ISP		22
+#define BCM2835_CLOCK_H264		23
+#define BCM2835_CLOCK_VEC		24
+#define BCM2835_CLOCK_HSM		25
+#define BCM2835_CLOCK_SDRAM		26
+#define BCM2835_CLOCK_TSENS		27
+#define BCM2835_CLOCK_EMMC		28
+#define BCM2835_CLOCK_PERI_IMAGE	29
+#define BCM2835_CLOCK_PWM		30
+#define BCM2835_CLOCK_PCM		31
+
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLD_DSI0		34
+#define BCM2835_PLLD_DSI1		35
+
+#define BCM2835_CLOCK_AVEO		36
+#define BCM2835_CLOCK_DFT		37
+#define BCM2835_CLOCK_GP0		38
+#define BCM2835_CLOCK_GP1		39
+#define BCM2835_CLOCK_GP2		40
+#define BCM2835_CLOCK_SLIM		41
+#define BCM2835_CLOCK_SMI		42
+#define BCM2835_CLOCK_TEC		43
+#define BCM2835_CLOCK_DPI		44
+#define BCM2835_CLOCK_CAM0		45
+#define BCM2835_CLOCK_CAM1		46
+#define BCM2835_CLOCK_DSI0E		47
+#define BCM2835_CLOCK_DSI1E		48
+#define BCM2835_CLOCK_DSI0P		49
+#define BCM2835_CLOCK_DSI1P		50
+
+#define BCM2711_CLOCK_EMMC2		51

linux-7.2.3/include/dt-bindings/clock/bcm3368-clock.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3368_H
+#define __DT_BINDINGS_CLOCK_BCM3368_H
+
+#define BCM3368_CLK_MAC 	3
+#define BCM3368_CLK_TC         	5
+#define BCM3368_CLK_US_TOP	6
+#define BCM3368_CLK_DS_TOP	7
+#define BCM3368_CLK_ACM 	8
+#define BCM3368_CLK_SPI	        9
+#define BCM3368_CLK_USBS	10
+#define BCM3368_CLK_BMU         11
+#define BCM3368_CLK_PCM         12
+#define BCM3368_CLK_NTP         13
+#define BCM3368_CLK_ACP_B       14
+#define BCM3368_CLK_ACP_A       15
+#define BCM3368_CLK_EMUSB       17
+#define BCM3368_CLK_ENET0       18
+#define BCM3368_CLK_ENET1       19
+#define BCM3368_CLK_USBSU       20
+#define BCM3368_CLK_EPHY        21
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3368_H */

linux-7.2.3/include/dt-bindings/clock/bcm6318-clock.h

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
+#define __DT_BINDINGS_CLOCK_BCM6318_H
+
+#define BCM6318_CLK_ADSL_ASB	0
+#define BCM6318_CLK_USB_ASB	1
+#define BCM6318_CLK_MIPS_ASB	2
+#define BCM6318_CLK_PCIE_ASB	3
+#define BCM6318_CLK_PHYMIPS_ASB	4
+#define BCM6318_CLK_ROBOSW_ASB	5
+#define BCM6318_CLK_SAR_ASB	6
+#define BCM6318_CLK_SDR_ASB	7
+#define BCM6318_CLK_SWREG_ASB	8
+#define BCM6318_CLK_PERIPH_ASB	9
+#define BCM6318_CLK_CPUBUS160	10
+#define BCM6318_CLK_ADSL	11
+#define BCM6318_CLK_SAR125	12
+#define BCM6318_CLK_MIPS	13
+#define BCM6318_CLK_PCIE	14
+#define BCM6318_CLK_ROBOSW250	16
+#define BCM6318_CLK_ROBOSW025	17
+#define BCM6318_CLK_SDR		19
+#define BCM6318_CLK_USBD	20
+#define BCM6318_CLK_HSSPI	25
+#define BCM6318_CLK_PCIE25	27
+#define BCM6318_CLK_PHYMIPS	28
+#define BCM6318_CLK_AFE		29
+#define BCM6318_CLK_QPROC	30
+
+#define BCM6318_UCLK_ADSL	0
+#define BCM6318_UCLK_ARB	1
+#define BCM6318_UCLK_MIPS	2
+#define BCM6318_UCLK_PCIE	3
+#define BCM6318_UCLK_PERIPH	4
+#define BCM6318_UCLK_PHYMIPS	5
+#define BCM6318_UCLK_ROBOSW	6
+#define BCM6318_UCLK_SAR	7
+#define BCM6318_UCLK_SDR	8
+#define BCM6318_UCLK_USB	9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */

linux-7.2.3/include/dt-bindings/clock/bcm63268-clock.h

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM63268_H
+#define __DT_BINDINGS_CLOCK_BCM63268_H
+
+#define BCM63268_CLK_DIS_GLESS	0
+#define BCM63268_CLK_VDSL_QPROC	1
+#define BCM63268_CLK_VDSL_AFE	2
+#define BCM63268_CLK_VDSL	3
+#define BCM63268_CLK_MIPS	4
+#define BCM63268_CLK_WLAN_OCP	5
+#define BCM63268_CLK_DECT	6
+#define BCM63268_CLK_FAP0	7
+#define BCM63268_CLK_FAP1	8
+#define BCM63268_CLK_SAR	9
+#define BCM63268_CLK_ROBOSW	10
+#define BCM63268_CLK_PCM	11
+#define BCM63268_CLK_USBD	12
+#define BCM63268_CLK_USBH	13
+#define BCM63268_CLK_IPSEC	14
+#define BCM63268_CLK_SPI	15
+#define BCM63268_CLK_HSSPI	16
+#define BCM63268_CLK_PCIE	17
+#define BCM63268_CLK_PHYMIPS	18
+#define BCM63268_CLK_GMAC	19
+#define BCM63268_CLK_NAND	20
+#define BCM63268_CLK_TBUS	27
+#define BCM63268_CLK_ROBOSW250	31
+
+#define BCM63268_TCLK_EPHY1		0
+#define BCM63268_TCLK_EPHY2		1
+#define BCM63268_TCLK_EPHY3		2
+#define BCM63268_TCLK_GPHY1		3
+#define BCM63268_TCLK_DSL		4
+#define BCM63268_TCLK_WAKEON_EPHY	6
+#define BCM63268_TCLK_WAKEON_DSL	7
+#define BCM63268_TCLK_FAP1		11
+#define BCM63268_TCLK_FAP2		15
+#define BCM63268_TCLK_UTO_50		16
+#define BCM63268_TCLK_UTO_EXTIN		17
+#define BCM63268_TCLK_USB_REF		18
+
+#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */

linux-7.2.3/include/dt-bindings/clock/bcm6328-clock.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6328_H
+#define __DT_BINDINGS_CLOCK_BCM6328_H
+
+#define BCM6328_CLK_PHYMIPS	0
+#define BCM6328_CLK_ADSL_QPROC	1
+#define BCM6328_CLK_ADSL_AFE	2
+#define BCM6328_CLK_ADSL	3
+#define BCM6328_CLK_MIPS	4
+#define BCM6328_CLK_SAR		5
+#define BCM6328_CLK_PCM		6
+#define BCM6328_CLK_USBD	7
+#define BCM6328_CLK_USBH	8
+#define BCM6328_CLK_HSSPI	9
+#define BCM6328_CLK_PCIE	10
+#define BCM6328_CLK_ROBOSW	11
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */

linux-7.2.3/include/dt-bindings/clock/bcm6358-clock.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6358_H
+#define __DT_BINDINGS_CLOCK_BCM6358_H
+
+#define BCM6358_CLK_ENET	4
+#define BCM6358_CLK_ADSLPHY	5
+#define BCM6358_CLK_PCM		8
+#define BCM6358_CLK_SPI		9
+#define BCM6358_CLK_USBS	10
+#define BCM6358_CLK_SAR		11
+#define BCM6358_CLK_EMUSB	17
+#define BCM6358_CLK_ENET0	18
+#define BCM6358_CLK_ENET1	19
+#define BCM6358_CLK_USBSU	20
+#define BCM6358_CLK_EPHY	21
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */

linux-7.2.3/include/dt-bindings/clock/bcm6362-clock.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
+#define __DT_BINDINGS_CLOCK_BCM6362_H
+
+#define BCM6362_CLK_ADSL_QPROC	1
+#define BCM6362_CLK_ADSL_AFE	2
+#define BCM6362_CLK_ADSL	3
+#define BCM6362_CLK_MIPS	4
+#define BCM6362_CLK_WLAN_OCP	5
+#define BCM6362_CLK_SWPKT_USB	7
+#define BCM6362_CLK_SWPKT_SAR	8
+#define BCM6362_CLK_SAR		9
+#define BCM6362_CLK_ROBOSW	10
+#define BCM6362_CLK_PCM		11
+#define BCM6362_CLK_USBD	12
+#define BCM6362_CLK_USBH	13
+#define BCM6362_CLK_IPSEC	14
+#define BCM6362_CLK_SPI		15
+#define BCM6362_CLK_HSSPI	16
+#define BCM6362_CLK_PCIE	17
+#define BCM6362_CLK_FAP		18
+#define BCM6362_CLK_PHYMIPS	19
+#define BCM6362_CLK_NAND	20
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */

linux-7.2.3/include/dt-bindings/clock/bcm6368-clock.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
+#define __DT_BINDINGS_CLOCK_BCM6368_H
+
+#define BCM6368_CLK_VDSL_QPROC		2
+#define BCM6368_CLK_VDSL_AFE		3
+#define BCM6368_CLK_VDSL_BONDING	4
+#define BCM6368_CLK_VDSL		5
+#define BCM6368_CLK_PHYMIPS		6
+#define BCM6368_CLK_SWPKT_USB		7
+#define BCM6368_CLK_SWPKT_SAR		8
+#define BCM6368_CLK_SPI			9
+#define BCM6368_CLK_USBD		10
+#define BCM6368_CLK_SAR			11
+#define BCM6368_CLK_ROBOSW		12
+#define BCM6368_CLK_UTOPIA		13
+#define BCM6368_CLK_PCM			14
+#define BCM6368_CLK_USBH		15
+#define BCM6368_CLK_DIS_GLESS		16
+#define BCM6368_CLK_NAND		17
+#define BCM6368_CLK_IPSEC		18
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */

linux-7.2.3/include/dt-bindings/clock/berlin2.h

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Berlin2 BG2/BG2CD clock tree IDs
+ */
+
+#define CLKID_SYS		0
+#define CLKID_CPU		1
+#define CLKID_DRMFIGO		2
+#define CLKID_CFG		3
+#define CLKID_GFX		4
+#define CLKID_ZSP		5
+#define CLKID_PERIF		6
+#define CLKID_PCUBE		7
+#define CLKID_VSCOPE		8
+#define CLKID_NFC_ECC		9
+#define CLKID_VPP		10
+#define CLKID_APP		11
+#define CLKID_AUDIO0		12
+#define CLKID_AUDIO2		13
+#define CLKID_AUDIO3		14
+#define CLKID_AUDIO1		15
+#define CLKID_GFX3D_CORE	16
+#define CLKID_GFX3D_SYS		17
+#define CLKID_ARC		18
+#define CLKID_VIP		19
+#define CLKID_SDIO0XIN		20
+#define CLKID_SDIO1XIN		21
+#define CLKID_GFX3D_EXTRA	22
+#define CLKID_GC360		23
+#define CLKID_SDIO_DLLMST	24
+#define CLKID_GETH0		25
+#define CLKID_GETH1		26
+#define CLKID_SATA		27
+#define CLKID_AHBAPB		28
+#define CLKID_USB0		29
+#define CLKID_USB1		30
+#define CLKID_PBRIDGE		31
+#define CLKID_SDIO0		32
+#define CLKID_SDIO1		33
+#define CLKID_NFC		34
+#define CLKID_SMEMC		35
+#define CLKID_AUDIOHD		36
+#define CLKID_VIDEO0		37
+#define CLKID_VIDEO1		38
+#define CLKID_VIDEO2		39
+#define CLKID_TWD		40

linux-7.2.3/include/dt-bindings/clock/berlin2q.h

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Berlin2 BG2Q clock tree IDs
+ */
+
+#define CLKID_SYS		0
+#define CLKID_DRMFIGO		1
+#define CLKID_CFG		2
+#define CLKID_GFX2D		3
+#define CLKID_ZSP		4
+#define CLKID_PERIF		5
+#define CLKID_PCUBE		6
+#define CLKID_VSCOPE		7
+#define CLKID_NFC_ECC		8
+#define CLKID_VPP		9
+#define CLKID_APP		10
+#define CLKID_SDIO0XIN		11
+#define CLKID_SDIO1XIN		12
+#define CLKID_GFX2DAXI		13
+#define CLKID_GETH0		14
+#define CLKID_SATA		15
+#define CLKID_AHBAPB		16
+#define CLKID_USB0		17
+#define CLKID_USB1		18
+#define CLKID_USB2		19
+#define CLKID_USB3		20
+#define CLKID_PBRIDGE		21
+#define CLKID_SDIO		22
+#define CLKID_NFC		23
+#define CLKID_SMEMC		24
+#define CLKID_PCIE		25
+#define CLKID_TWD		26
+#define CLKID_CPU		27

linux-7.2.3/include/dt-bindings/clock/bm1880-clock.h

@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Bitmain BM1880 SoC
+ *
+ * Copyright (c) 2019 Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BM1880_H
+#define __DT_BINDINGS_CLOCK_BM1880_H
+
+#define BM1880_CLK_OSC			0
+#define BM1880_CLK_MPLL			1
+#define BM1880_CLK_SPLL			2
+#define BM1880_CLK_FPLL			3
+#define BM1880_CLK_DDRPLL		4
+#define BM1880_CLK_A53			5
+#define BM1880_CLK_50M_A53		6
+#define BM1880_CLK_AHB_ROM		7
+#define BM1880_CLK_AXI_SRAM		8
+#define BM1880_CLK_DDR_AXI		9
+#define BM1880_CLK_EFUSE		10
+#define BM1880_CLK_APB_EFUSE		11
+#define BM1880_CLK_AXI5_EMMC		12
+#define BM1880_CLK_EMMC			13
+#define BM1880_CLK_100K_EMMC		14
+#define BM1880_CLK_AXI5_SD		15
+#define BM1880_CLK_SD			16
+#define BM1880_CLK_100K_SD		17
+#define BM1880_CLK_500M_ETH0		18
+#define BM1880_CLK_AXI4_ETH0		19
+#define BM1880_CLK_500M_ETH1		20
+#define BM1880_CLK_AXI4_ETH1		21
+#define BM1880_CLK_AXI1_GDMA		22
+#define BM1880_CLK_APB_GPIO		23
+#define BM1880_CLK_APB_GPIO_INTR	24
+#define BM1880_CLK_GPIO_DB		25
+#define BM1880_CLK_AXI1_MINER		26
+#define BM1880_CLK_AHB_SF		27
+#define BM1880_CLK_SDMA_AXI		28
+#define BM1880_CLK_SDMA_AUD		29
+#define BM1880_CLK_APB_I2C		30
+#define BM1880_CLK_APB_WDT		31
+#define BM1880_CLK_APB_JPEG		32
+#define BM1880_CLK_JPEG_AXI		33
+#define BM1880_CLK_AXI5_NF		34
+#define BM1880_CLK_APB_NF		35
+#define BM1880_CLK_NF			36
+#define BM1880_CLK_APB_PWM		37
+#define BM1880_CLK_DIV_0_RV		38
+#define BM1880_CLK_DIV_1_RV		39
+#define BM1880_CLK_MUX_RV		40
+#define BM1880_CLK_RV			41
+#define BM1880_CLK_APB_SPI		42
+#define BM1880_CLK_TPU_AXI		43
+#define BM1880_CLK_DIV_UART_500M	44
+#define BM1880_CLK_UART_500M		45
+#define BM1880_CLK_APB_UART		46
+#define BM1880_CLK_APB_I2S		47
+#define BM1880_CLK_AXI4_USB		48
+#define BM1880_CLK_APB_USB		49
+#define BM1880_CLK_125M_USB		50
+#define BM1880_CLK_33K_USB		51
+#define BM1880_CLK_DIV_12M_USB		52
+#define BM1880_CLK_12M_USB		53
+#define BM1880_CLK_APB_VIDEO		54
+#define BM1880_CLK_VIDEO_AXI		55
+#define BM1880_CLK_VPP_AXI		56
+#define BM1880_CLK_APB_VPP		57
+#define BM1880_CLK_DIV_0_AXI1		58
+#define BM1880_CLK_DIV_1_AXI1		59
+#define BM1880_CLK_AXI1			60
+#define BM1880_CLK_AXI2			61
+#define BM1880_CLK_AXI3			62
+#define BM1880_CLK_AXI4			63
+#define BM1880_CLK_AXI5			64
+#define BM1880_CLK_DIV_0_AXI6		65
+#define BM1880_CLK_DIV_1_AXI6		66
+#define BM1880_CLK_MUX_AXI6		67
+#define BM1880_CLK_AXI6			68
+#define BM1880_NR_CLKS			69
+
+#endif /* __DT_BINDINGS_CLOCK_BM1880_H */

linux-7.2.3/include/dt-bindings/clock/boston-clock.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_INPUT 0
+#define BOSTON_CLK_SYS 1
+#define BOSTON_CLK_CPU 2
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */

linux-7.2.3/include/dt-bindings/clock/canaan,k230-clk.h

@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Kendryte Canaan K230 Clock Drivers
+ *
+ * Author: Xukai Wang <kingxukai@zohomail.com>
+ */
+
+#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__
+#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__
+
+#define K230_CPU0_SRC_GATE			0
+#define K230_CPU0_PLIC_GATE			1
+#define K230_CPU0_NOC_DDRCP4_GATE		2
+#define K230_CPU0_APB_GATE			3
+#define K230_CPU0_SRC_RATE			4
+#define K230_CPU0_AXI_RATE			5
+#define K230_CPU0_PLIC_RATE			6
+#define K230_CPU0_APB_RATE			7
+#define K230_HS_SSI0_MUX			8
+#define K230_HS_USB_REF_MUX			9
+#define K230_HS_HCLK_HIGH_GATE			10
+#define K230_HS_HCLK_GATE			11
+#define K230_HS_SD0_AHB_GATE			12
+#define K230_HS_SD1_AHB_GATE			13
+#define K230_HS_SSI1_AHB_GATE			14
+#define K230_HS_SSI2_AHB_GATE			15
+#define K230_HS_USB0_AHB_GATE			16
+#define K230_HS_USB1_AHB_GATE			17
+#define K230_HS_SSI0_AXI_GATE			18
+#define K230_HS_SSI1_GATE			19
+#define K230_HS_SSI2_GATE			20
+#define K230_HS_QSPI_AXI_SRC_GATE		21
+#define K230_HS_SSI1_AXI_GATE			22
+#define K230_HS_SSI2_AXI_GATE			23
+#define K230_HS_SD_CARD_SRC_GATE		24
+#define K230_HS_SD0_CARD_GATE			25
+#define K230_HS_SD1_CARD_GATE			26
+#define K230_HS_SD_AXI_SRC_GATE			27
+#define K230_HS_SD0_AXI_GATE			28
+#define K230_HS_SD1_AXI_GATE			29
+#define K230_HS_SD0_BASE_GATE			30
+#define K230_HS_SD1_BASE_GATE			31
+#define K230_HS_SSI0_GATE			32
+#define K230_HS_SD_TIMER_SRC_GATE		33
+#define K230_HS_SD0_TIMER_GATE			34
+#define K230_HS_SD1_TIMER_GATE			35
+#define K230_HS_USB0_REF_GATE			36
+#define K230_HS_USB1_REF_GATE			37
+#define K230_HS_HCLK_HIGH_RATE			38
+#define K230_HS_HCLK_RATE			39
+#define K230_HS_SSI0_AXI_RATE			40
+#define K230_HS_SSI1_RATE			41
+#define K230_HS_SSI2_RATE			42
+#define K230_HS_QSPI_AXI_SRC_RATE		43
+#define K230_HS_SD_CARD_SRC_RATE		44
+#define K230_HS_SD_AXI_SRC_RATE			45
+#define K230_HS_USB_REF_50M_RATE		46
+#define K230_HS_SD_TIMER_SRC_RATE		47
+#define K230_TIMER0_MUX				48
+#define K230_TIMER1_MUX				49
+#define K230_TIMER2_MUX				50
+#define K230_TIMER3_MUX				51
+#define K230_TIMER4_MUX				52
+#define K230_TIMER5_MUX				53
+#define K230_SHRM_SRAM_MUX			54
+#define K230_DDRC_SRC_MUX			55
+#define K230_AI_SRC_MUX				56
+#define K230_CAMERA0_MUX			57
+#define K230_CAMERA1_MUX			58
+#define K230_CAMERA2_MUX			59
+#define K230_CPU1_SRC_MUX			60
+#define K230_CPU1_SRC_GATE			61
+#define K230_CPU1_PLIC_GATE			62
+#define K230_CPU1_APB_GATE			63
+#define K230_CPU1_SRC_RATE			64
+#define K230_CPU1_AXI_RATE			65
+#define K230_CPU1_PLIC_RATE			66
+#define K230_PMU_APB_GATE			67
+#define K230_LS_APB_SRC_GATE			68
+#define K230_LS_UART0_APB_GATE			69
+#define K230_LS_UART1_APB_GATE			70
+#define K230_LS_UART2_APB_GATE			71
+#define K230_LS_UART3_APB_GATE			72
+#define K230_LS_UART4_APB_GATE			73
+#define K230_LS_I2C0_APB_GATE			74
+#define K230_LS_I2C1_APB_GATE			75
+#define K230_LS_I2C2_APB_GATE			76
+#define K230_LS_I2C3_APB_GATE			77
+#define K230_LS_I2C4_APB_GATE			78
+#define K230_LS_GPIO_APB_GATE			79
+#define K230_LS_PWM_APB_GATE			80
+#define K230_LS_JAMLINK0_APB_GATE		81
+#define K230_LS_JAMLINK1_APB_GATE		82
+#define K230_LS_JAMLINK2_APB_GATE		83
+#define K230_LS_JAMLINK3_APB_GATE		84
+#define K230_LS_AUDIO_APB_GATE			85
+#define K230_LS_ADC_APB_GATE			86
+#define K230_LS_CODEC_APB_GATE			87
+#define K230_LS_I2C0_GATE			88
+#define K230_LS_I2C1_GATE			89
+#define K230_LS_I2C2_GATE			90
+#define K230_LS_I2C3_GATE			91
+#define K230_LS_I2C4_GATE			92
+#define K230_LS_CODEC_ADC_GATE			93
+#define K230_LS_CODEC_DAC_GATE			94
+#define K230_LS_AUDIO_DEV_GATE			95
+#define K230_LS_PDM_GATE			96
+#define K230_LS_ADC_GATE			97
+#define K230_LS_UART0_GATE			98
+#define K230_LS_UART1_GATE			99
+#define K230_LS_UART2_GATE			100
+#define K230_LS_UART3_GATE			101
+#define K230_LS_UART4_GATE			102
+#define K230_LS_JAMLINK0CO_GATE			103
+#define K230_LS_JAMLINK1CO_GATE			104
+#define K230_LS_JAMLINK2CO_GATE			105
+#define K230_LS_JAMLINK3CO_GATE			106
+#define K230_LS_GPIO_DEBOUNCE_GATE		107
+#define K230_SYSCTL_WDT0_APB_GATE		108
+#define K230_SYSCTL_WDT1_APB_GATE		109
+#define K230_SYSCTL_TIMER_APB_GATE		110
+#define K230_SYSCTL_IOMUX_APB_GATE		111
+#define K230_SYSCTL_MAILBOX_APB_GATE		112
+#define K230_SYSCTL_HDI_GATE			113
+#define K230_SYSCTL_TIME_STAMP_GATE		114
+#define K230_SYSCTL_WDT0_GATE			115
+#define K230_SYSCTL_WDT1_GATE			116
+#define K230_TIMER0_GATE			117
+#define K230_TIMER1_GATE			118
+#define K230_TIMER2_GATE			119
+#define K230_TIMER3_GATE			120
+#define K230_TIMER4_GATE			121
+#define K230_TIMER5_GATE			122
+#define K230_SHRM_APB_GATE			123
+#define K230_SHRM_AXI_GATE			124
+#define K230_SHRM_AXI_SLAVE_GATE		125
+#define K230_SHRM_NONAI2D_AXI_GATE		126
+#define K230_SHRM_SRAM_GATE			127
+#define K230_SHRM_DECOMPRESS_AXI_GATE		128
+#define K230_SHRM_SDMA_AXI_GATE			129
+#define K230_SHRM_PDMA_AXI_GATE			130
+#define K230_DDRC_SRC_GATE			131
+#define K230_DDRC_BYPASS_GATE			132
+#define K230_DDRC_APB_GATE			133
+#define K230_DISPLAY_AHB_GATE			134
+#define K230_DISPLAY_AXI_GATE			135
+#define K230_DISPLAY_GPU_GATE			136
+#define K230_DISPLAY_DPIP_GATE			137
+#define K230_DISPLAY_CFG_GATE			138
+#define K230_DISPLAY_REF_GATE			139
+#define K230_USB_480M_GATE			140
+#define K230_USB_100M_GATE			141
+#define K230_DPHY_DFT_GATE			142
+#define K230_SPI2AXI_GATE			143
+#define K230_AI_SRC_GATE			144
+#define K230_AI_AXI_GATE			145
+#define K230_AI_SRC_RATE			146
+#define K230_CAMERA0_GATE			147
+#define K230_CAMERA1_GATE			148
+#define K230_CAMERA2_GATE			149
+#define K230_LS_APB_SRC_RATE			150
+#define K230_LS_I2C0_RATE			151
+#define K230_LS_I2C1_RATE			152
+#define K230_LS_I2C2_RATE			153
+#define K230_LS_I2C3_RATE			154
+#define K230_LS_I2C4_RATE			155
+#define K230_LS_CODEC_ADC_RATE			156
+#define K230_LS_CODEC_DAC_RATE			157
+#define K230_LS_AUDIO_DEV_RATE			158
+#define K230_LS_PDM_RATE			159
+#define K230_LS_ADC_RATE			160
+#define K230_LS_UART0_RATE			161
+#define K230_LS_UART1_RATE			162
+#define K230_LS_UART2_RATE			163
+#define K230_LS_UART3_RATE			164
+#define K230_LS_UART4_RATE			165
+#define K230_LS_JAMLINKCO_SRC_RATE		166
+#define K230_LS_GPIO_DEBOUNCE_RATE		167
+#define K230_SYSCTL_HDI_RATE			168
+#define K230_SYSCTL_TIME_STAMP_RATE		169
+#define K230_SYSCTL_TEMP_SENSOR_RATE		170
+#define K230_SYSCTL_WDT0_RATE			171
+#define K230_SYSCTL_WDT1_RATE			172
+#define K230_TIMER0_SRC_RATE			173
+#define K230_TIMER1_SRC_RATE			174
+#define K230_TIMER2_SRC_RATE			175
+#define K230_TIMER3_SRC_RATE			176
+#define K230_TIMER4_SRC_RATE			177
+#define K230_TIMER5_SRC_RATE			178
+#define K230_SHRM_APB_RATE			179
+#define K230_DDRC_SRC_RATE			180
+#define K230_DDRC_APB_RATE			181
+#define K230_DISPLAY_AHB_RATE			182
+#define K230_DISPLAY_CLKEXT_RATE		183
+#define K230_DISPLAY_GPU_RATE			184
+#define K230_DISPLAY_DPIP_RATE			185
+#define K230_DISPLAY_CFG_RATE			186
+#define K230_VPU_SRC_GATE			187
+#define K230_VPU_AXI_GATE			188
+#define K230_VPU_DDRCP2_GATE			189
+#define K230_VPU_CFG_GATE			190
+#define K230_VPU_SRC_RATE			191
+#define K230_VPU_AXI_SRC_RATE			192
+#define K230_VPU_CFG_RATE			193
+#define K230_SEC_APB_GATE			194
+#define K230_SEC_FIX_GATE			195
+#define K230_SEC_AXI_GATE			196
+#define K230_SEC_APB_RATE			197
+#define K230_SEC_FIX_RATE			198
+#define K230_SEC_AXI_RATE			199
+#define K230_USB_480M_RATE			200
+#define K230_USB_100M_RATE			201
+#define K230_DPHY_DFT_RATE			202
+#define K230_SPI2AXI_RATE			203
+#define K230_CAMERA0_RATE			204
+#define K230_CAMERA1_RATE			205
+#define K230_CAMERA2_RATE			206
+#define K230_SHRM_SRAM_DIV2			207
+
+#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */

linux-7.2.3/include/dt-bindings/clock/cirrus,cs2000-cp.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 Daniel Mack
+ */
+
+#ifndef __DT_BINDINGS_CS2000CP_CLK_H
+#define __DT_BINDINGS_CS2000CP_CLK_H
+
+#define CS2000CP_AUX_OUTPUT_REF_CLK	0
+#define CS2000CP_AUX_OUTPUT_CLK_IN	1
+#define CS2000CP_AUX_OUTPUT_CLK_OUT	2
+#define CS2000CP_AUX_OUTPUT_PLL_LOCK	3
+
+#endif /* __DT_BINDINGS_CS2000CP_CLK_H */

linux-7.2.3/include/dt-bindings/clock/cirrus,ep9301-syscon.h

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+#ifndef DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H
+#define DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H
+
+#define EP93XX_CLK_PLL1		0
+#define EP93XX_CLK_PLL2		1
+
+#define EP93XX_CLK_FCLK		2
+#define EP93XX_CLK_HCLK		3
+#define EP93XX_CLK_PCLK		4
+
+#define EP93XX_CLK_UART		5
+#define EP93XX_CLK_SPI		6
+#define EP93XX_CLK_PWM		7
+#define EP93XX_CLK_USB		8
+
+#define EP93XX_CLK_M2M0		9
+#define EP93XX_CLK_M2M1		10
+
+#define EP93XX_CLK_M2P0		11
+#define EP93XX_CLK_M2P1		12
+#define EP93XX_CLK_M2P2		13
+#define EP93XX_CLK_M2P3		14
+#define EP93XX_CLK_M2P4		15
+#define EP93XX_CLK_M2P5		16
+#define EP93XX_CLK_M2P6		17
+#define EP93XX_CLK_M2P7		18
+#define EP93XX_CLK_M2P8		19
+#define EP93XX_CLK_M2P9		20
+
+#define EP93XX_CLK_UART1	21
+#define EP93XX_CLK_UART2	22
+#define EP93XX_CLK_UART3	23
+
+#define EP93XX_CLK_ADC		24
+#define EP93XX_CLK_ADC_EN	25
+
+#define EP93XX_CLK_KEYPAD	26
+
+#define EP93XX_CLK_VIDEO	27
+
+#define EP93XX_CLK_I2S_MCLK	28
+#define EP93XX_CLK_I2S_SCLK	29
+#define EP93XX_CLK_I2S_LRCLK	30
+
+#endif /* DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/cix,sky1.h

@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2024-2025 Cix Technology Group Co., Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H
+#define _DT_BINDINGS_CLK_CIX_SKY1_H
+
+#define CLK_TREE_CPU_GICxCLK			0
+#define CLK_TREE_CPU_PPUCLK			1
+#define CLK_TREE_CPU_PERIPHCLK			2
+#define CLK_TREE_DSU_CLK			3
+#define CLK_TREE_DSU_PCLK			4
+#define CLK_TREE_CPU_CLK_BC0			5
+#define CLK_TREE_CPU_CLK_BC1			6
+#define CLK_TREE_CPU_CLK_BC2			7
+#define CLK_TREE_CPU_CLK_BC3			8
+#define CLK_TREE_CPU_CLK_MC0			9
+#define CLK_TREE_CPU_CLK_MC1			10
+#define CLK_TREE_CPU_CLK_MC2			11
+#define CLK_TREE_CPU_CLK_MC3			12
+#define CLK_TREE_CPU_CLK_LC0			13
+#define CLK_TREE_CPU_CLK_LC1			14
+#define CLK_TREE_CPU_CLK_LC2			15
+#define CLK_TREE_CPU_CLK_LC3			16
+#define CLK_TREE_CSI_CTRL0_PCLK			17
+#define CLK_TREE_CSI_CTRL1_PCLK			18
+#define CLK_TREE_CSI_CTRL2_PCLK			19
+#define CLK_TREE_CSI_CTRL3_PCLK			20
+#define CLK_TREE_CSI_DMA0_PCLK			21
+#define CLK_TREE_CSI_DMA1_PCLK			22
+#define CLK_TREE_CSI_DMA2_PCLK			23
+#define CLK_TREE_CSI_DMA3_PCLK			24
+#define CLK_TREE_CSI_PHY0_PSM			25
+#define CLK_TREE_CSI_PHY1_PSM			26
+#define CLK_TREE_CSI_PHY0_APBCLK		27
+#define CLK_TREE_CSI_PHY1_APBCLK		28
+#define CLK_TREE_FCH_APB_CLK			29
+#define CLK_TREE_GPU_CLK_400M			30
+#define CLK_TREE_GPU_CLK_CORE			31
+#define CLK_TREE_GPU_CLK_STACKS			32
+#define CLK_TREE_DP0_PIXEL0			33
+#define CLK_TREE_DP0_PIXEL1			34
+#define CLK_TREE_DP1_PIXEL0			35
+#define CLK_TREE_DP1_PIXEL1			36
+#define CLK_TREE_DP2_PIXEL0			37
+#define CLK_TREE_DP2_PIXEL1			38
+#define CLK_TREE_DP3_PIXEL0			39
+#define CLK_TREE_DP3_PIXEL1			40
+#define CLK_TREE_DP4_PIXEL0			41
+#define CLK_TREE_DP4_PIXEL1			42
+#define CLK_TREE_DPU_CLK			43
+#define CLK_TREE_DPU0_ACLK			44
+#define CLK_TREE_DPU1_ACLK			45
+#define CLK_TREE_DPU2_ACLK			46
+#define CLK_TREE_DPU3_ACLK			47
+#define CLK_TREE_DPU4_ACLK			48
+#define CLK_TREE_DPC0_VIDCLK0			49
+#define CLK_TREE_DPC0_VIDCLK1			50
+#define CLK_TREE_DPC1_VIDCLK0			51
+#define CLK_TREE_DPC1_VIDCLK1			52
+#define CLK_TREE_DPC2_VIDCLK0			53
+#define CLK_TREE_DPC2_VIDCLK1			54
+#define CLK_TREE_DPC3_VIDCLK0			55
+#define CLK_TREE_DPC3_VIDCLK1			56
+#define CLK_TREE_DPC4_VIDCLK0			57
+#define CLK_TREE_DPC4_VIDCLK1			58
+#define CLK_TREE_DPC0_APBCLK			59
+#define CLK_TREE_DPC1_APBCLK			60
+#define CLK_TREE_DPC2_APBCLK			61
+#define CLK_TREE_DPC3_APBCLK			62
+#define CLK_TREE_DPC4_APBCLK			63
+#define CLK_TREE_NPU_MEMCLK			64
+#define CLK_TREE_NPU_SYSCLK			65
+#define CLK_TREE_NPU_DBGCLK			66
+#define CLK_TREE_VPU_APBCLK			67
+#define CLK_TREE_ISP_ACLK			68
+#define CLK_TREE_ISP_SCLK			69
+#define CLK_TREE_AUDIO_CLK4			70
+#define CLK_TREE_AUDIO_CLK5			71
+#define CLK_TREE_CAMERA_MCLK0			72
+#define CLK_TREE_CAMERA_MCLK1			73
+#define CLK_TREE_CAMERA_MCLK2			74
+#define CLK_TREE_CAMERA_MCLK3			75
+#define CLK_TREE_AUDIO_CLK0			76
+#define CLK_TREE_AUDIO_CLK1			77
+#define CLK_TREE_AUDIO_CLK2			78
+#define CLK_TREE_AUDIO_CLK3			79
+#define CLK_TREE_MM_NI700_CLK			80
+#define CLK_TREE_SYS_NI700_CLK			81
+#define CLK_TREE_GMAC0_ACLK			82
+#define CLK_TREE_GMAC1_ACLK			83
+#define CLK_TREE_GMAC0_DIV_ACLK			84
+#define CLK_TREE_GMAC0_DIV_TXCLK		85
+#define CLK_TREE_GMAC0_RGMII0_TXCLK		86
+#define CLK_TREE_GMAC1_DIV_ACLK			87
+#define CLK_TREE_GMAC1_DIV_TXCLK		88
+#define CLK_TREE_GMAC1_RGMII0_TXCLK		89
+#define CLK_TREE_GMAC0_PCLK			90
+#define CLK_TREE_GMAC1_PCLK			91
+#define CLK_TREE_USB2_0_AXI_GATE		92
+#define CLK_TREE_USB2_0_APB_GATE		93
+#define CLK_TREE_USB2_1_AXI_GATE		94
+#define CLK_TREE_USB2_1_APB_GATE		95
+#define CLK_TREE_USB2_2_AXI_GATE		96
+#define CLK_TREE_USB2_2_APB_GATE		97
+#define CLK_TREE_USB2_3_AXI_GATE		98
+#define CLK_TREE_USB2_3_APB_GATE		99
+#define CLK_TREE_USB2_0_PHY_GATE		100
+#define CLK_TREE_USB2_1_PHY_GATE		101
+#define CLK_TREE_USB2_2_PHY_GATE		102
+#define CLK_TREE_USB2_3_PHY_GATE		103
+#define CLK_TREE_USB3C_DRD_AXI_GATE		104
+#define CLK_TREE_USB3C_DRD_APB_GATE		105
+#define CLK_TREE_USB3C_DRD_PHY2_GATE		106
+#define CLK_TREE_USB3C_DRD_PHY3_GATE		107
+#define CLK_TREE_USB3C_0_AXI_GATE		108
+#define CLK_TREE_USB3C_0_APB_GATE		109
+#define CLK_TREE_USB3C_0_PHY2_GATE		110
+#define CLK_TREE_USB3C_0_PHY3_GATE		111
+#define CLK_TREE_USB3C_1_AXI_GATE		112
+#define CLK_TREE_USB3C_1_APB_GATE		113
+#define CLK_TREE_USB3C_1_PHY2_GATE		114
+#define CLK_TREE_USB3C_1_PHY3_GATE		115
+#define CLK_TREE_USB3C_2_AXI_GATE		116
+#define CLK_TREE_USB3C_2_APB_GATE		117
+#define CLK_TREE_USB3C_2_PHY2_GATE		118
+#define CLK_TREE_USB3C_2_PHY3_GATE		119
+#define CLK_TREE_USB3A_0_AXI_GATE		120
+#define CLK_TREE_USB3A_0_APB_GATE		121
+#define CLK_TREE_USB3A_0_PHY2_GATE		122
+#define CLK_TREE_USB3A_1_AXI_GATE		123
+#define CLK_TREE_USB3A_1_APB_GATE		124
+#define CLK_TREE_USB3A_1_PHY2_GATE		125
+#define CLK_TREE_USB3A_PHY3_GATE		126
+#define CLK_TREE_USB2_0_CLK_SOF			127
+#define CLK_TREE_USB2_1_CLK_SOF			128
+#define CLK_TREE_USB2_2_CLK_SOF			129
+#define CLK_TREE_USB2_3_CLK_SOF			130
+#define CLK_TREE_USB3C_DRD_CLK_SOF		131
+#define CLK_TREE_USB3C_H0_CLK_SOF		132
+#define CLK_TREE_USB3C_H1_CLK_SOF		133
+#define CLK_TREE_USB3C_H2_CLK_SOF		134
+#define CLK_TREE_USB3A_H0_CLK_SOF		135
+#define CLK_TREE_USB3A_H1_CLK_SOF		136
+#define CLK_TREE_USB2_0_CLK_LPM			137
+#define CLK_TREE_USB2_1_CLK_LPM			138
+#define CLK_TREE_USB2_2_CLK_LPM			139
+#define CLK_TREE_USB2_3_CLK_LPM			140
+#define CLK_TREE_USB3C_DRD_CLK_LPM		141
+#define CLK_TREE_USB3C_H0_CLK_LPM		142
+#define CLK_TREE_USB3C_H1_CLK_LPM		143
+#define CLK_TREE_USB3C_H2_CLK_LPM		144
+#define CLK_TREE_USB3A_H0_CLK_LPM		145
+#define CLK_TREE_USB3A_H1_CLK_LPM		146
+#define CLK_TREE_USB2_0_PHY_REF			147
+#define CLK_TREE_USB2_1_PHY_REF			148
+#define CLK_TREE_USB2_2_PHY_REF			149
+#define CLK_TREE_USB2_3_PHY_REF			150
+#define CLK_TREE_USB3C_DRD_PHY_REF		151
+#define CLK_TREE_USB3C_H0_PHY_REF		152
+#define CLK_TREE_USB3C_H1_PHY_REF		153
+#define CLK_TREE_USB3C_H2_PHY_REF		154
+#define CLK_TREE_USB3A_H0_PHY_REF		155
+#define CLK_TREE_USB3A_H1_PHY_REF		156
+#define CLK_TREE_USB3C_DRD_PHY_x4_REF		157
+#define CLK_TREE_USB3C_H0_PHY_x4_REF		158
+#define CLK_TREE_USB3C_H1_PHY_x4_REF		159
+#define CLK_TREE_USB3C_H2_PHY_x4_REF		160
+#define CLK_TREE_USB3A_PHY_x2_REF		161
+#define CLK_TREE_PCIE_X8CTRL_APB		162
+#define CLK_TREE_PCIE_X4CTRL_APB		163
+#define CLK_TREE_PCIE_X2CTRL_APB		164
+#define CLK_TREE_PCIE_X1_0CTRL_APB		165
+#define CLK_TREE_PCIE_X1_1CTRL_APB		166
+#define CLK_TREE_PCIE_X8_PHY_APB		167
+#define CLK_TREE_PCIE_X4_PHY_APB		168
+#define CLK_TREE_PCIE_X211_PHY_APB		169
+#define CLK_TREE_PCIE_NI700_CLK			170
+#define CLK_TREE_PCIE_CTRL0_CLK			171
+#define CLK_TREE_PCIE_CTRL1_CLK			172
+#define CLK_TREE_PCIE_CTRL2_CLK			173
+#define CLK_TREE_PCIE_CTRL3_CLK			174
+#define CLK_TREE_PCIE_CTRL4_CLK			175
+#define CLK_TREE_CSI_CTRL0_SYSCLK		176
+#define CLK_TREE_CSI_CTRL1_SYSCLK		177
+#define CLK_TREE_CSI_CTRL2_SYSCLK		178
+#define CLK_TREE_CSI_CTRL3_SYSCLK		179
+#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK		180
+#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK		181
+#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK		182
+#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK		183
+#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK		184
+#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK		185
+#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK		186
+#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK		187
+#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK		188
+#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK		189
+#define CLK_TREE_CI700_GCLK0			190
+#define CLK_TREE_DDRC0_ACLK_CLK			191
+#define CLK_TREE_DDRC1_ACLK_CLK			192
+#define CLK_TREE_DDRC2_ACLK_CLK			193
+#define CLK_TREE_DDRC3_ACLK_CLK			194
+#define CLK_TREE_DDRC0_DFICLK_CLK		195
+#define CLK_TREE_DDRC1_DFICLK_CLK		196
+#define CLK_TREE_DDRC2_DFICLK_CLK		197
+#define CLK_TREE_DDRC3_DFICLK_CLK		198
+#define CLK_TREE_PHY0_SYNC_CLK			199
+#define CLK_TREE_PHY1_SYNC_CLK			200
+#define CLK_TREE_PHY2_SYNC_CLK			201
+#define CLK_TREE_PHY3_SYNC_CLK			202
+#define CLK_TREE_PHY0_BYPASS_CLK		203
+#define CLK_TREE_PHY1_BYPASS_CLK		204
+#define CLK_TREE_PHY2_BYPASS_CLK		205
+#define CLK_TREE_PHY3_BYPASS_CLK		206
+#define CLK_TREE_DDRC_0_APB			207
+#define CLK_TREE_DDRC_1_APB			208
+#define CLK_TREE_DDRC_2_APB			209
+#define CLK_TREE_DDRC_3_APB			210
+#define CLK_TREE_TZC400_0_APB			211
+#define CLK_TREE_TZC400_1_APB			212
+#define CLK_TREE_TZC400_2_APB			213
+#define CLK_TREE_TZC400_3_APB			214
+#define CLK_TREE_S5_SENSOR_HUB_25M		215
+#define CLK_TREE_S5_SENSOR_HUB_400M		216
+#define CLK_TREE_S5_CSS600_100M			217
+#define CLK_TREE_S5_DFD_800M			218
+#define CLK_TREE_S5_CSU_SE_800M			219
+#define CLK_TREE_S5_CSU_PM_800M			220
+#define CLK_TREE_PCIE_REF_B0			221
+#define CLK_TREE_PCIE_REF_B1			222
+#define CLK_TREE_PCIE_REF_B2			223
+#define CLK_TREE_PCIE_REF_B3			224
+#define CLK_TREE_PCIE_REF_B4			225
+#define CLK_TREE_PCIE_REF_PHY_X8		226
+#define CLK_TREE_PCIE_REF_PHY_X4		227
+#define CLK_TREE_PCIE_REF_PHY_X211		228
+#define CLK_TREE_GMAC_REC_CLK			229
+#define CLK_TREE_GPUTOP_PLL			230
+#define CLK_TREE_GPUCORE_PLL			231
+#define CLK_TREE_CPU_PLL_LIT			232
+#define CLK_TREE_CPU_PLL0			233
+#define CLK_TREE_CPU_PLL1			234
+#define CLK_TREE_CPU_PLL2			235
+#define CLK_TREE_CPU_PLL3			236
+#define CLK_TREE_FCH_I3C0_FUNC			237
+#define CLK_TREE_FCH_I3C1_FUNC			238
+#define CLK_TREE_FCH_DMA_ACLK			239
+#define CLK_TREE_FCH_XSPI_FUNC			240
+#define CLK_TREE_FCH_XSPI_MACLK			241
+#define CLK_TREE_FCH_TIMER_FUN			242
+#define CLK_TREE_FCH_APB_IO_S0			243
+#define CLK_TREE_FCH_I3C0_APB			244
+#define CLK_TREE_FCH_I3C1_APB			245
+#define CLK_TREE_FCH_UART0_APB			246
+#define CLK_TREE_FCH_UART1_APB			247
+#define CLK_TREE_FCH_UART2_APB			248
+#define CLK_TREE_FCH_UART3_APB			249
+#define CLK_TREE_FCH_SPI0_APB			250
+#define CLK_TREE_FCH_SPI1_APB			251
+#define CLK_TREE_FCH_XSPI_APB			252
+#define CLK_TREE_FCH_I2C0_APB			253
+#define CLK_TREE_FCH_I2C1_APB			254
+#define CLK_TREE_FCH_I2C2_APB			255
+#define CLK_TREE_FCH_I2C3_APB			256
+#define CLK_TREE_FCH_I2C4_APB			257
+#define CLK_TREE_FCH_I2C5_APB			258
+#define CLK_TREE_FCH_I2C6_APB			259
+#define CLK_TREE_FCH_I2C7_APB			260
+#define CLK_TREE_FCH_TIMER_APB			261
+#define CLK_TREE_FCH_GPIO_APB			262
+#define CLK_TREE_FCH_UART0_FUNC			263
+#define CLK_TREE_FCH_UART1_FUNC			264
+#define CLK_TREE_FCH_UART2_FUNC			265
+#define CLK_TREE_FCH_UART3_FUNC			266
+/* 267~271 not used by AP, skip */
+#define CLK_TREE_GPU_CLK_200M			272
+
+#endif

linux-7.2.3/include/dt-bindings/clock/clps711x-clock.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
+#define __DT_BINDINGS_CLOCK_CLPS711X_H
+
+#define CLPS711X_CLK_DUMMY	0
+#define CLPS711X_CLK_CPU	1
+#define CLPS711X_CLK_BUS	2
+#define CLPS711X_CLK_PLL	3
+#define CLPS711X_CLK_TIMERREF	4
+#define CLPS711X_CLK_TIMER1	5
+#define CLPS711X_CLK_TIMER2	6
+#define CLPS711X_CLK_PWM	7
+#define CLPS711X_CLK_SPIREF	8
+#define CLPS711X_CLK_SPI	9
+#define CLPS711X_CLK_UART	10
+#define CLPS711X_CLK_TICK	11
+#define CLPS711X_CLK_MAX	12
+
+#endif

linux-7.2.3/include/dt-bindings/clock/cortina,gemini-clock.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+
+/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */
+#define GEMINI_NUM_CLKS 20
+
+#define GEMINI_CLK_RTC 0
+#define GEMINI_CLK_AHB 1
+#define GEMINI_CLK_APB 2
+#define GEMINI_CLK_CPU 3
+#define GEMINI_CLK_PCI 4
+#define GEMINI_CLK_TVC 5
+#define GEMINI_CLK_UART 6
+#define GEMINI_CLK_GATES 7
+#define GEMINI_CLK_GATE_SECURITY 7
+#define GEMINI_CLK_GATE_GMAC0 8
+#define GEMINI_CLK_GATE_GMAC1 9
+#define GEMINI_CLK_GATE_SATA0 10
+#define GEMINI_CLK_GATE_SATA1 11
+#define GEMINI_CLK_GATE_USB0 12
+#define GEMINI_CLK_GATE_USB1 13
+#define GEMINI_CLK_GATE_IDE 14
+#define GEMINI_CLK_GATE_PCI 15
+#define GEMINI_CLK_GATE_DDR 16
+#define GEMINI_CLK_GATE_FLASH 17
+#define GEMINI_CLK_GATE_TVC 18
+#define GEMINI_CLK_GATE_BOOT 19
+
+#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/dm814.h

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_DM814_H
+#define __DT_BINDINGS_CLK_DM814_H
+
+#define DM814_CLKCTRL_OFFSET	0x0
+#define DM814_CLKCTRL_INDEX(offset)	((offset) - DM814_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM814_USB_OTG_HS_CLKCTRL	DM814_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM814_UART1_CLKCTRL	DM814_CLKCTRL_INDEX(0x150)
+#define DM814_UART2_CLKCTRL	DM814_CLKCTRL_INDEX(0x154)
+#define DM814_UART3_CLKCTRL	DM814_CLKCTRL_INDEX(0x158)
+#define DM814_GPIO1_CLKCTRL	DM814_CLKCTRL_INDEX(0x15c)
+#define DM814_GPIO2_CLKCTRL	DM814_CLKCTRL_INDEX(0x160)
+#define DM814_I2C1_CLKCTRL	DM814_CLKCTRL_INDEX(0x164)
+#define DM814_I2C2_CLKCTRL	DM814_CLKCTRL_INDEX(0x168)
+#define DM814_WD_TIMER_CLKCTRL	DM814_CLKCTRL_INDEX(0x18c)
+#define DM814_MCSPI1_CLKCTRL	DM814_CLKCTRL_INDEX(0x190)
+#define DM814_GPMC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d0)
+#define DM814_CPGMAC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d4)
+#define DM814_MPU_CLKCTRL	DM814_CLKCTRL_INDEX(0x1dc)
+#define DM814_RTC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f0)
+#define DM814_TPCC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f4)
+#define DM814_TPTC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f8)
+#define DM814_TPTC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x1fc)
+#define DM814_TPTC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x200)
+#define DM814_TPTC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x204)
+#define DM814_MMC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x21c)
+#define DM814_MMC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x220)
+#define DM814_MMC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x224)
+
+/* alwon_ethernet clocks */
+#define DM814_ETHERNET_CLKCTRL_OFFSET	0x1d4
+#define DM814_ETHERNET_CLKCTRL_INDEX(offset)	((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
+#define DM814_ETHERNET_CPGMAC0_CLKCTRL	DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
+
+#endif

linux-7.2.3/include/dt-bindings/clock/dm816.h

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_DM816_H
+#define __DT_BINDINGS_CLK_DM816_H
+
+#define DM816_CLKCTRL_OFFSET	0x0
+#define DM816_CLKCTRL_INDEX(offset)	((offset) - DM816_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM816_USB_OTG_HS_CLKCTRL	DM816_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM816_UART1_CLKCTRL	DM816_CLKCTRL_INDEX(0x150)
+#define DM816_UART2_CLKCTRL	DM816_CLKCTRL_INDEX(0x154)
+#define DM816_UART3_CLKCTRL	DM816_CLKCTRL_INDEX(0x158)
+#define DM816_GPIO1_CLKCTRL	DM816_CLKCTRL_INDEX(0x15c)
+#define DM816_GPIO2_CLKCTRL	DM816_CLKCTRL_INDEX(0x160)
+#define DM816_I2C1_CLKCTRL	DM816_CLKCTRL_INDEX(0x164)
+#define DM816_I2C2_CLKCTRL	DM816_CLKCTRL_INDEX(0x168)
+#define DM816_TIMER1_CLKCTRL	DM816_CLKCTRL_INDEX(0x170)
+#define DM816_TIMER2_CLKCTRL	DM816_CLKCTRL_INDEX(0x174)
+#define DM816_TIMER3_CLKCTRL	DM816_CLKCTRL_INDEX(0x178)
+#define DM816_TIMER4_CLKCTRL	DM816_CLKCTRL_INDEX(0x17c)
+#define DM816_TIMER5_CLKCTRL	DM816_CLKCTRL_INDEX(0x180)
+#define DM816_TIMER6_CLKCTRL	DM816_CLKCTRL_INDEX(0x184)
+#define DM816_TIMER7_CLKCTRL	DM816_CLKCTRL_INDEX(0x188)
+#define DM816_WD_TIMER_CLKCTRL	DM816_CLKCTRL_INDEX(0x18c)
+#define DM816_MCSPI1_CLKCTRL	DM816_CLKCTRL_INDEX(0x190)
+#define DM816_MAILBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x194)
+#define DM816_SPINBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x198)
+#define DM816_MMC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1b0)
+#define DM816_GPMC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d0)
+#define DM816_DAVINCI_MDIO_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d4)
+#define DM816_EMAC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d8)
+#define DM816_MPU_CLKCTRL	DM816_CLKCTRL_INDEX(0x1dc)
+#define DM816_RTC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f0)
+#define DM816_TPCC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f4)
+#define DM816_TPTC0_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f8)
+#define DM816_TPTC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1fc)
+#define DM816_TPTC2_CLKCTRL	DM816_CLKCTRL_INDEX(0x200)
+#define DM816_TPTC3_CLKCTRL	DM816_CLKCTRL_INDEX(0x204)
+
+#endif

linux-7.2.3/include/dt-bindings/clock/dra7.h

@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ */
+#ifndef __DT_BINDINGS_CLK_DRA7_H
+#define __DT_BINDINGS_CLK_DRA7_H
+
+#define DRA7_CLKCTRL_OFFSET	0x20
+#define DRA7_CLKCTRL_INDEX(offset)	((offset) - DRA7_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define DRA7_MPU_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* dsp1 clocks */
+#define DRA7_DSP1_MMU0_DSP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* ipu1 clocks */
+#define DRA7_IPU1_MMU_IPU1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define DRA7_IPU_CLKCTRL_OFFSET	0x50
+#define DRA7_IPU_CLKCTRL_INDEX(offset)	((offset) - DRA7_IPU_CLKCTRL_OFFSET)
+#define DRA7_IPU_MCASP1_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x50)
+#define DRA7_IPU_TIMER5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x58)
+#define DRA7_IPU_TIMER6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x60)
+#define DRA7_IPU_TIMER7_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x68)
+#define DRA7_IPU_TIMER8_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x70)
+#define DRA7_IPU_I2C5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x78)
+#define DRA7_IPU_UART6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x80)
+
+/* dsp2 clocks */
+#define DRA7_DSP2_MMU0_DSP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* rtc clocks */
+#define DRA7_RTC_RTCSS_CLKCTRL	DRA7_CLKCTRL_INDEX(0x44)
+
+/* vip clocks */
+#define DRA7_CAM_VIP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_CAM_VIP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_CAM_VIP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+
+/* vpe clocks */
+#define DRA7_VPE_CLKCTRL_OFFSET	0x60
+#define DRA7_VPE_CLKCTRL_INDEX(offset)	((offset) - DRA7_VPE_CLKCTRL_OFFSET)
+#define DRA7_VPE_VPE_CLKCTRL	DRA7_VPE_CLKCTRL_INDEX(0x64)
+
+/* coreaon clocks */
+#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
+
+/* l3main1 clocks */
+#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L3MAIN1_GPMC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_L3MAIN1_TPCC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_L3MAIN1_TPTC0_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_L3MAIN1_TPTC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_L3MAIN1_VCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_L3MAIN1_VCP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
+
+/* ipu2 clocks */
+#define DRA7_IPU2_MMU_IPU2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* dma clocks */
+#define DRA7_DMA_DMA_SYSTEM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define DRA7_EMIF_DMM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* atl clocks */
+#define DRA7_ATL_CLKCTRL_OFFSET	0x0
+#define DRA7_ATL_CLKCTRL_INDEX(offset)	((offset) - DRA7_ATL_CLKCTRL_OFFSET)
+#define DRA7_ATL_ATL_CLKCTRL	DRA7_ATL_CLKCTRL_INDEX(0x0)
+
+/* l4cfg clocks */
+#define DRA7_L4CFG_L4_CFG_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L4CFG_SPINLOCK_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_L4CFG_MAILBOX1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_L4CFG_MAILBOX2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_L4CFG_MAILBOX3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_L4CFG_MAILBOX4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x58)
+#define DRA7_L4CFG_MAILBOX5_CLKCTRL	DRA7_CLKCTRL_INDEX(0x60)
+#define DRA7_L4CFG_MAILBOX6_CLKCTRL	DRA7_CLKCTRL_INDEX(0x68)
+#define DRA7_L4CFG_MAILBOX7_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_L4CFG_MAILBOX8_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_L4CFG_MAILBOX9_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_L4CFG_MAILBOX10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_L4CFG_MAILBOX11_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
+#define DRA7_L4CFG_MAILBOX12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x98)
+#define DRA7_L4CFG_MAILBOX13_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
+
+/* l3instr clocks */
+#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L3INSTR_L3_INSTR_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+
+/* iva clocks */
+#define DRA7_IVA_CLKCTRL		DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_SL2IF_CLKCTRL		DRA7_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define DRA7_DSS_DSS_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_DSS_BB2D_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+
+/* gpu clocks */
+#define DRA7_GPU_CLKCTRL		DRA7_CLKCTRL_INDEX(0x20)
+
+/* l3init clocks */
+#define DRA7_L3INIT_MMC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_L3INIT_MMC2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_L3INIT_SATA_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_L3INIT_OCP2SCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe0)
+#define DRA7_L3INIT_OCP2SCP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe8)
+#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xf0)
+
+/* pcie clocks */
+#define DRA7_PCIE_CLKCTRL_OFFSET	0xb0
+#define DRA7_PCIE_CLKCTRL_INDEX(offset)	((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
+#define DRA7_PCIE_PCIE1_CLKCTRL	DRA7_PCIE_CLKCTRL_INDEX(0xb0)
+#define DRA7_PCIE_PCIE2_CLKCTRL	DRA7_PCIE_CLKCTRL_INDEX(0xb8)
+
+/* gmac clocks */
+#define DRA7_GMAC_CLKCTRL_OFFSET	0xd0
+#define DRA7_GMAC_CLKCTRL_INDEX(offset)	((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
+#define DRA7_GMAC_GMAC_CLKCTRL	DRA7_GMAC_CLKCTRL_INDEX(0xd0)
+
+/* l4per clocks */
+#define DRA7_L4PER_CLKCTRL_OFFSET	0x28
+#define DRA7_L4PER_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
+#define DRA7_L4PER_TIMER10_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x28)
+#define DRA7_L4PER_TIMER11_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x30)
+#define DRA7_L4PER_TIMER2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x38)
+#define DRA7_L4PER_TIMER3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x40)
+#define DRA7_L4PER_TIMER4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x48)
+#define DRA7_L4PER_TIMER9_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x50)
+#define DRA7_L4PER_ELM_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x58)
+#define DRA7_L4PER_GPIO2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x60)
+#define DRA7_L4PER_GPIO3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x68)
+#define DRA7_L4PER_GPIO4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x70)
+#define DRA7_L4PER_GPIO5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x78)
+#define DRA7_L4PER_GPIO6_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x80)
+#define DRA7_L4PER_HDQ1W_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x88)
+#define DRA7_L4PER_I2C1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa0)
+#define DRA7_L4PER_I2C2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa8)
+#define DRA7_L4PER_I2C3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb0)
+#define DRA7_L4PER_I2C4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb8)
+#define DRA7_L4PER_L4_PER1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc0)
+#define DRA7_L4PER_MCSPI1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf0)
+#define DRA7_L4PER_MCSPI2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf8)
+#define DRA7_L4PER_MCSPI3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x100)
+#define DRA7_L4PER_MCSPI4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x108)
+#define DRA7_L4PER_GPIO7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x110)
+#define DRA7_L4PER_GPIO8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x118)
+#define DRA7_L4PER_MMC3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x120)
+#define DRA7_L4PER_MMC4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x128)
+#define DRA7_L4PER_UART1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x140)
+#define DRA7_L4PER_UART2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x148)
+#define DRA7_L4PER_UART3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x150)
+#define DRA7_L4PER_UART4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x158)
+#define DRA7_L4PER_UART5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x170)
+
+/* l4sec clocks */
+#define DRA7_L4SEC_CLKCTRL_OFFSET	0x1a0
+#define DRA7_L4SEC_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
+#define DRA7_L4SEC_AES1_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
+#define DRA7_L4SEC_AES2_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
+#define DRA7_L4SEC_DES_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
+#define DRA7_L4SEC_RNG_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
+#define DRA7_L4SEC_SHAM_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
+#define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
+
+/* l4per2 clocks */
+#define DRA7_L4PER2_CLKCTRL_OFFSET	0xc
+#define DRA7_L4PER2_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
+#define DRA7_L4PER2_L4_PER2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0xc)
+#define DRA7_L4PER2_PRUSS1_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x18)
+#define DRA7_L4PER2_PRUSS2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x20)
+#define DRA7_L4PER2_EPWMSS1_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x90)
+#define DRA7_L4PER2_EPWMSS2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x98)
+#define DRA7_L4PER2_EPWMSS0_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
+#define DRA7_L4PER2_QSPI_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x138)
+#define DRA7_L4PER2_MCASP2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x160)
+#define DRA7_L4PER2_MCASP3_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x168)
+#define DRA7_L4PER2_MCASP5_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x178)
+#define DRA7_L4PER2_MCASP8_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x190)
+#define DRA7_L4PER2_MCASP4_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x198)
+#define DRA7_L4PER2_UART7_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
+#define DRA7_L4PER2_UART8_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
+#define DRA7_L4PER2_UART9_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
+#define DRA7_L4PER2_DCAN2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
+#define DRA7_L4PER2_MCASP6_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x204)
+#define DRA7_L4PER2_MCASP7_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x208)
+
+/* l4per3 clocks */
+#define DRA7_L4PER3_CLKCTRL_OFFSET	0x14
+#define DRA7_L4PER3_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
+#define DRA7_L4PER3_L4_PER3_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0x14)
+#define DRA7_L4PER3_TIMER13_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
+#define DRA7_L4PER3_TIMER14_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
+#define DRA7_L4PER3_TIMER15_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
+#define DRA7_L4PER3_TIMER16_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0x130)
+
+/* wkupaon clocks */
+#define DRA7_WKUPAON_L4_WKUP_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_WKUPAON_GPIO1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
+#define DRA7_WKUPAON_TIMER1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_WKUPAON_TIMER12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_WKUPAON_UART10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_WKUPAON_DCAN1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_WKUPAON_ADC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
+
+#endif

linux-7.2.3/include/dt-bindings/clock/econet,en751221-scu.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+
+#define EN751221_CLK_PCIE	0
+#define EN751221_CLK_SPI	1
+#define EN751221_CLK_BUS	2
+#define EN751221_CLK_CPU	3
+#define EN751221_CLK_GSW	4
+
+#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */

linux-7.2.3/include/dt-bindings/clock/en7523-clk.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
+#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
+
+#define EN7523_CLK_GSW		0
+#define EN7523_CLK_EMI		1
+#define EN7523_CLK_BUS		2
+#define EN7523_CLK_SLIC		3
+#define EN7523_CLK_SPI		4
+#define EN7523_CLK_NPU		5
+#define EN7523_CLK_CRYPTO	6
+#define EN7523_CLK_PCIE		7
+
+#define EN7581_CLK_EMMC		8
+
+#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */

linux-7.2.3/include/dt-bindings/clock/eswin,eic7700-clock.h

@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 clock controller.
+ *
+ * Authors:
+ *	Yifeng Huang <huangyifeng@eswincomputing.com>
+ *	Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+
+#define EIC7700_CLK_XTAL_32K				0
+#define EIC7700_CLK_PLL_CPU				1
+#define EIC7700_CLK_SPLL0_FOUT1				2
+#define EIC7700_CLK_SPLL0_FOUT2				3
+#define EIC7700_CLK_SPLL0_FOUT3				4
+#define EIC7700_CLK_SPLL1_FOUT1				5
+#define EIC7700_CLK_SPLL1_FOUT2				6
+#define EIC7700_CLK_SPLL1_FOUT3				7
+#define EIC7700_CLK_SPLL2_FOUT1				8
+#define EIC7700_CLK_SPLL2_FOUT2				9
+#define EIC7700_CLK_SPLL2_FOUT3				10
+#define EIC7700_CLK_VPLL_FOUT1				11
+#define EIC7700_CLK_VPLL_FOUT2				12
+#define EIC7700_CLK_VPLL_FOUT3				13
+#define EIC7700_CLK_APLL_FOUT1				14
+#define EIC7700_CLK_APLL_FOUT2				15
+#define EIC7700_CLK_APLL_FOUT3				16
+#define EIC7700_CLK_EXT_MCLK				17
+#define EIC7700_CLK_LPDDR_REF_BAK			18
+#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE		19
+#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE		20
+#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE	21
+#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE	22
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0		23
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1		24
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2		25
+#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE		26
+#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE		27
+#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE	28
+#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE		29
+#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE	30
+#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE	31
+#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1		32
+#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE		33
+#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE		34
+#define EIC7700_CLK_MUX_SATA_PHY_2MUX1			35
+#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE		36
+#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE	37
+#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE	38
+#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK		39
+#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE	40
+#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE		41
+#define EIC7700_CLK_MUX_RMII_REF_2MUX			42
+#define EIC7700_CLK_MUX_ETH_CORE_2MUX1			43
+#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1		44
+#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE		45
+#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE	46
+#define EIC7700_CLK_DIV_SYS_CFG_DYNM			47
+#define EIC7700_CLK_DIV_NOC_NSP_DYNM			48
+#define EIC7700_CLK_DIV_BOOTSPI_DYNM			49
+#define EIC7700_CLK_DIV_SCPU_CORE_DYNM			50
+#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM			51
+#define EIC7700_CLK_DIV_GPU_ACLK_DYNM			52
+#define EIC7700_CLK_DIV_DSP_ACLK_DYNM			53
+#define EIC7700_CLK_DIV_D2D_ACLK_DYNM			54
+#define EIC7700_CLK_DIV_HSP_ACLK_DYNM			55
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0		56
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1		57
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0		58
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1		59
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2		60
+#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM			61
+#define EIC7700_CLK_DIV_NPU_ACLK_DYNM			62
+#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM		63
+#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM		64
+#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM		65
+#define EIC7700_CLK_DIV_VI_ACLK_DYNM			66
+#define EIC7700_CLK_DIV_VI_DVP_DYNM			67
+#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM			68
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0		69
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1		70
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2		71
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3		72
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4		73
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5		74
+#define EIC7700_CLK_DIV_VO_ACLK_DYNM			75
+#define EIC7700_CLK_DIV_IESMCLK_DYNM			76
+#define EIC7700_CLK_DIV_VO_PIXEL_DYNM			77
+#define EIC7700_CLK_DIV_VO_MCLK_DYNM			78
+#define EIC7700_CLK_DIV_VC_ACLK_DYNM			79
+#define EIC7700_CLK_DIV_JD_DYNM				80
+#define EIC7700_CLK_DIV_JE_DYNM				81
+#define EIC7700_CLK_DIV_VE_DYNM				82
+#define EIC7700_CLK_DIV_VD_DYNM				83
+#define EIC7700_CLK_DIV_G2D_DYNM			84
+#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM			85
+#define EIC7700_CLK_DIV_CRYPTO_DYNM			86
+#define EIC7700_CLK_DIV_VI_DW_DYNM			87
+#define EIC7700_CLK_DIV_NPU_E31_DYNM			88
+#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM		89
+#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM			90
+#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM			91
+#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM			92
+#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM			93
+#define EIC7700_CLK_DIV_DDR_ACLK_DYNM			94
+#define EIC7700_CLK_DIV_AON_RTC_DYNM			95
+#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM		96
+#define EIC7700_CLK_DIV_VO_CEC_DYNM			97
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0		98
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1		99
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2		100
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3		101
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0		102
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1		103
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2		104
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3		105
+#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK		106
+#define EIC7700_CLK_GATE_SPLL0_FOUT2			107
+#define EIC7700_CLK_GATE_NOC_NSP_CLK			108
+#define EIC7700_CLK_GATE_BOOTSPI			109
+#define EIC7700_CLK_GATE_BOOTSPI_CFG			110
+#define EIC7700_CLK_GATE_SCPU_CORE			111
+#define EIC7700_CLK_GATE_SCPU_BUS			112
+#define EIC7700_CLK_GATE_LPCPU_CORE			113
+#define EIC7700_CLK_GATE_LPCPU_BUS			114
+#define EIC7700_CLK_GATE_GPU_ACLK			115
+#define EIC7700_CLK_GATE_GPU_GRAY_CLK			116
+#define EIC7700_CLK_GATE_GPU_CFG_CLK			117
+#define EIC7700_CLK_GATE_DSPT_ACLK			118
+#define EIC7700_CLK_GATE_DSPT_CFG_CLK			119
+#define EIC7700_CLK_GATE_D2D_ACLK			120
+#define EIC7700_CLK_GATE_D2D_CFG_CLK			121
+#define EIC7700_CLK_GATE_TCU_ACLK			122
+#define EIC7700_CLK_GATE_TCU_CFG_CLK			123
+#define EIC7700_CLK_GATE_DDRT_CFG_CLK			124
+#define EIC7700_CLK_GATE_DDRT0_P0_ACLK			125
+#define EIC7700_CLK_GATE_DDRT0_P1_ACLK			126
+#define EIC7700_CLK_GATE_DDRT0_P2_ACLK			127
+#define EIC7700_CLK_GATE_DDRT0_P3_ACLK			128
+#define EIC7700_CLK_GATE_DDRT0_P4_ACLK			129
+#define EIC7700_CLK_GATE_DDRT1_P0_ACLK			130
+#define EIC7700_CLK_GATE_DDRT1_P1_ACLK			131
+#define EIC7700_CLK_GATE_DDRT1_P2_ACLK			132
+#define EIC7700_CLK_GATE_DDRT1_P3_ACLK			133
+#define EIC7700_CLK_GATE_DDRT1_P4_ACLK			134
+#define EIC7700_CLK_GATE_TIMER_CLK_0			135
+#define EIC7700_CLK_GATE_TIMER_CLK_1			136
+#define EIC7700_CLK_GATE_TIMER_CLK_2			137
+#define EIC7700_CLK_GATE_TIMER_CLK_3			138
+#define EIC7700_CLK_GATE_TIMER_PCLK_0			139
+#define EIC7700_CLK_GATE_TIMER_PCLK_1			140
+#define EIC7700_CLK_GATE_TIMER_PCLK_2			141
+#define EIC7700_CLK_GATE_TIMER_PCLK_3			142
+#define EIC7700_CLK_GATE_TIMER3_CLK8			143
+#define EIC7700_CLK_GATE_PCIET_ACLK			144
+#define EIC7700_CLK_GATE_PCIET_CFG_CLK			145
+#define EIC7700_CLK_GATE_PCIET_CR_CLK			146
+#define EIC7700_CLK_GATE_PCIET_AUX_CLK			147
+#define EIC7700_CLK_GATE_NPU_ACLK			148
+#define EIC7700_CLK_GATE_NPU_CFG_CLK			149
+#define EIC7700_CLK_GATE_NPU_LLC_ACLK			150
+#define EIC7700_CLK_GATE_NPU_CLK			151
+#define EIC7700_CLK_GATE_NPU_E31_CLK			152
+#define EIC7700_CLK_GATE_VI_ACLK			153
+#define EIC7700_CLK_GATE_VI_DVP_CLK			154
+#define EIC7700_CLK_GATE_VI_CFG_CLK			155
+#define EIC7700_CLK_GATE_VI_DIG_DW_CLK			156
+#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK			157
+#define EIC7700_CLK_GATE_VI_SHUTTER_0			158
+#define EIC7700_CLK_GATE_VI_SHUTTER_1			159
+#define EIC7700_CLK_GATE_VI_SHUTTER_2			160
+#define EIC7700_CLK_GATE_VI_SHUTTER_3			161
+#define EIC7700_CLK_GATE_VI_SHUTTER_4			162
+#define EIC7700_CLK_GATE_VI_SHUTTER_5			163
+#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC		164
+#define EIC7700_CLK_GATE_VI_PHY_CFG			165
+#define EIC7700_CLK_GATE_VO_ACLK			166
+#define EIC7700_CLK_GATE_VO_CFG_CLK			167
+#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK		168
+#define EIC7700_CLK_GATE_VO_PIXEL_CLK			169
+#define EIC7700_CLK_GATE_VO_I2S_MCLK			170
+#define EIC7700_CLK_GATE_HSP_CFG_CLK			171
+#define EIC7700_CLK_GATE_VC_ACLK			172
+#define EIC7700_CLK_GATE_VC_CFG_CLK			173
+#define EIC7700_CLK_GATE_VC_JE_CLK			174
+#define EIC7700_CLK_GATE_VC_JD_CLK			175
+#define EIC7700_CLK_GATE_VC_VE_CLK			176
+#define EIC7700_CLK_GATE_VC_VD_CLK			177
+#define EIC7700_CLK_GATE_G2D_CFG_CLK			178
+#define EIC7700_CLK_GATE_G2D_CLK			179
+#define EIC7700_CLK_GATE_G2D_ACLK			180
+#define EIC7700_CLK_GATE_AONDMA_CFG			181
+#define EIC7700_CLK_GATE_AONDMA_ACLK			182
+#define EIC7700_CLK_GATE_AON_ACLK			183
+#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK		184
+#define EIC7700_CLK_GATE_VO_CR_CLK			185
+#define EIC7700_CLK_GATE_HSP_ACLK			186
+#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK		187
+#define EIC7700_CLK_GATE_RTC_CFG			188
+#define EIC7700_CLK_GATE_RTC				189
+#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK		190
+#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK		191
+#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK		192
+#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK		193
+#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK		194
+#define EIC7700_CLK_GATE_HSP_RMII_REF_0			195
+#define EIC7700_CLK_GATE_HSP_RMII_REF_1			196
+#define EIC7700_CLK_GATE_PKA_CFG			197
+#define EIC7700_CLK_GATE_SPACC_CFG			198
+#define EIC7700_CLK_GATE_CRYPTO				199
+#define EIC7700_CLK_GATE_TRNG_CFG			200
+#define EIC7700_CLK_GATE_OTP_CFG			201
+#define EIC7700_CLK_GATE_MAILBOX_0			202
+#define EIC7700_CLK_GATE_MAILBOX_1			203
+#define EIC7700_CLK_GATE_MAILBOX_2			204
+#define EIC7700_CLK_GATE_MAILBOX_3			205
+#define EIC7700_CLK_GATE_MAILBOX_4			206
+#define EIC7700_CLK_GATE_MAILBOX_5			207
+#define EIC7700_CLK_GATE_MAILBOX_6			208
+#define EIC7700_CLK_GATE_MAILBOX_7			209
+#define EIC7700_CLK_GATE_MAILBOX_8			210
+#define EIC7700_CLK_GATE_MAILBOX_9			211
+#define EIC7700_CLK_GATE_MAILBOX_10			212
+#define EIC7700_CLK_GATE_MAILBOX_11			213
+#define EIC7700_CLK_GATE_MAILBOX_12			214
+#define EIC7700_CLK_GATE_MAILBOX_13			215
+#define EIC7700_CLK_GATE_MAILBOX_14			216
+#define EIC7700_CLK_GATE_MAILBOX_15			217
+#define EIC7700_CLK_GATE_LSP_I2C0_PCLK			218
+#define EIC7700_CLK_GATE_LSP_I2C1_PCLK			219
+#define EIC7700_CLK_GATE_LSP_I2C2_PCLK			220
+#define EIC7700_CLK_GATE_LSP_I2C3_PCLK			221
+#define EIC7700_CLK_GATE_LSP_I2C4_PCLK			222
+#define EIC7700_CLK_GATE_LSP_I2C5_PCLK			223
+#define EIC7700_CLK_GATE_LSP_I2C6_PCLK			224
+#define EIC7700_CLK_GATE_LSP_I2C7_PCLK			225
+#define EIC7700_CLK_GATE_LSP_I2C8_PCLK			226
+#define EIC7700_CLK_GATE_LSP_I2C9_PCLK			227
+#define EIC7700_CLK_GATE_LSP_WDT0_PCLK			228
+#define EIC7700_CLK_GATE_LSP_WDT1_PCLK			229
+#define EIC7700_CLK_GATE_LSP_WDT2_PCLK			230
+#define EIC7700_CLK_GATE_LSP_WDT3_PCLK			231
+#define EIC7700_CLK_GATE_LSP_SSI0_PCLK			232
+#define EIC7700_CLK_GATE_LSP_SSI1_PCLK			233
+#define EIC7700_CLK_GATE_LSP_PVT_PCLK			234
+#define EIC7700_CLK_GATE_AON_I2C0_PCLK			235
+#define EIC7700_CLK_GATE_AON_I2C1_PCLK			236
+#define EIC7700_CLK_GATE_LSP_UART0_PCLK			237
+#define EIC7700_CLK_GATE_LSP_UART1_PCLK			238
+#define EIC7700_CLK_GATE_LSP_UART2_PCLK			239
+#define EIC7700_CLK_GATE_LSP_UART3_PCLK			240
+#define EIC7700_CLK_GATE_LSP_UART4_PCLK			241
+#define EIC7700_CLK_GATE_LSP_TIMER_PCLK			242
+#define EIC7700_CLK_GATE_LSP_FAN_PCLK			243
+#define EIC7700_CLK_GATE_LSP_PVT0_CLK			244
+#define EIC7700_CLK_GATE_LSP_PVT1_CLK			245
+#define EIC7700_CLK_GATE_VC_JE_PCLK			246
+#define EIC7700_CLK_GATE_VC_JD_PCLK			247
+#define EIC7700_CLK_GATE_VC_VE_PCLK			248
+#define EIC7700_CLK_GATE_VC_VD_PCLK			249
+#define EIC7700_CLK_GATE_VC_MON_PCLK			250
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK			251
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST		252
+#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2		253
+#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24		254
+#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10	255
+#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2	256
+#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2		257
+#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2		258
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2		259
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4		260
+#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20		261
+#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6	262
+#define EIC7700_CLK_DIV_NOC_WDREF_DYNM			263
+#define EIC7700_CLK_GATE_DDR0_TRACE			264
+#define EIC7700_CLK_GATE_DDR1_TRACE			265
+#define EIC7700_CLK_GATE_RNOC_NSP			266
+#define EIC7700_CLK_GATE_NOC_WDREF			267
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */

linux-7.2.3/include/dt-bindings/clock/exynos-audss-clk.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS	0
+#define EXYNOS_MOUT_I2S	1
+#define EXYNOS_DOUT_SRP	2
+#define EXYNOS_DOUT_AUD_BUS	3
+#define EXYNOS_DOUT_I2S	4
+#define EXYNOS_SRP_CLK		5
+#define EXYNOS_I2S_BUS		6
+#define EXYNOS_SCLK_I2S	7
+#define EXYNOS_PCM_BUS		8
+#define EXYNOS_SCLK_PCM	9
+#define EXYNOS_ADMA		10
+
+#define EXYNOS_AUDSS_MAX_CLKS	11
+
+#endif

linux-7.2.3/include/dt-bindings/clock/exynos3250.h

@@ -0,0 +1,335 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * 	Author: Tomasz Figa <t.figa@samsung.com>
+ *
+ * Device Tree binding constants for Samsung Exynos3250 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL			1
+#define CLK_FIN_PLL			2
+#define CLK_FOUT_APLL			3
+#define CLK_FOUT_VPLL			4
+#define CLK_FOUT_UPLL			5
+#define CLK_FOUT_MPLL			6
+#define CLK_ARM_CLK			7
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L		16
+#define CLK_MOUT_GDL			17
+#define CLK_MOUT_MPLL_USER_R		18
+#define CLK_MOUT_GDR			19
+#define CLK_MOUT_EBI			20
+#define CLK_MOUT_ACLK_200		21
+#define CLK_MOUT_ACLK_160		22
+#define CLK_MOUT_ACLK_100		23
+#define CLK_MOUT_ACLK_266_1		24
+#define CLK_MOUT_ACLK_266_0		25
+#define CLK_MOUT_ACLK_266		26
+#define CLK_MOUT_VPLL			27
+#define CLK_MOUT_EPLL_USER		28
+#define CLK_MOUT_EBI_1			29
+#define CLK_MOUT_UPLL			30
+#define CLK_MOUT_ACLK_400_MCUISP_SUB	31
+#define CLK_MOUT_MPLL			32
+#define CLK_MOUT_ACLK_400_MCUISP	33
+#define CLK_MOUT_VPLLSRC		34
+#define CLK_MOUT_CAM1			35
+#define CLK_MOUT_CAM_BLK		36
+#define CLK_MOUT_MFC			37
+#define CLK_MOUT_MFC_1			38
+#define CLK_MOUT_MFC_0			39
+#define CLK_MOUT_G3D			40
+#define CLK_MOUT_G3D_1			41
+#define CLK_MOUT_G3D_0			42
+#define CLK_MOUT_MIPI0			43
+#define CLK_MOUT_FIMD0			44
+#define CLK_MOUT_UART_ISP		45
+#define CLK_MOUT_SPI1_ISP		46
+#define CLK_MOUT_SPI0_ISP		47
+#define CLK_MOUT_TSADC			48
+#define CLK_MOUT_MMC1			49
+#define CLK_MOUT_MMC0			50
+#define CLK_MOUT_UART1			51
+#define CLK_MOUT_UART0			52
+#define CLK_MOUT_SPI1			53
+#define CLK_MOUT_SPI0			54
+#define CLK_MOUT_AUDIO			55
+#define CLK_MOUT_MPLL_USER_C		56
+#define CLK_MOUT_HPM			57
+#define CLK_MOUT_CORE			58
+#define CLK_MOUT_APLL			59
+#define CLK_MOUT_ACLK_266_SUB		60
+#define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
+
+/* Dividers */
+#define CLK_DIV_GPL			64
+#define CLK_DIV_GDL			65
+#define CLK_DIV_GPR			66
+#define CLK_DIV_GDR			67
+#define CLK_DIV_MPLL_PRE		68
+#define CLK_DIV_ACLK_400_MCUISP		69
+#define CLK_DIV_EBI			70
+#define CLK_DIV_ACLK_200		71
+#define CLK_DIV_ACLK_160		72
+#define CLK_DIV_ACLK_100		73
+#define CLK_DIV_ACLK_266		74
+#define CLK_DIV_CAM1			75
+#define CLK_DIV_CAM_BLK			76
+#define CLK_DIV_MFC			77
+#define CLK_DIV_G3D			78
+#define CLK_DIV_MIPI0_PRE		79
+#define CLK_DIV_MIPI0			80
+#define CLK_DIV_FIMD0			81
+#define CLK_DIV_UART_ISP		82
+#define CLK_DIV_SPI1_ISP_PRE		83
+#define CLK_DIV_SPI1_ISP		84
+#define CLK_DIV_SPI0_ISP_PRE		85
+#define CLK_DIV_SPI0_ISP		86
+#define CLK_DIV_TSADC_PRE		87
+#define CLK_DIV_TSADC			88
+#define CLK_DIV_MMC1_PRE		89
+#define CLK_DIV_MMC1			90
+#define CLK_DIV_MMC0_PRE		91
+#define CLK_DIV_MMC0			92
+#define CLK_DIV_UART1			93
+#define CLK_DIV_UART0			94
+#define CLK_DIV_SPI1_PRE		95
+#define CLK_DIV_SPI1			96
+#define CLK_DIV_SPI0_PRE		97
+#define CLK_DIV_SPI0			98
+#define CLK_DIV_PCM			99
+#define CLK_DIV_AUDIO			100
+#define CLK_DIV_I2S			101
+#define CLK_DIV_CORE2			102
+#define CLK_DIV_APLL			103
+#define CLK_DIV_PCLK_DBG		104
+#define CLK_DIV_ATB			105
+#define CLK_DIV_COREM			106
+#define CLK_DIV_CORE			107
+#define CLK_DIV_HPM			108
+#define CLK_DIV_COPY			109
+#define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
+
+/* Gates */
+#define CLK_ASYNC_G3D			128
+#define CLK_ASYNC_MFCL			129
+#define CLK_PPMULEFT			130
+#define CLK_GPIO_LEFT			131
+#define CLK_ASYNC_ISPMX			132
+#define CLK_ASYNC_FSYSD			133
+#define CLK_ASYNC_LCD0X			134
+#define CLK_ASYNC_CAMX			135
+#define CLK_PPMURIGHT			136
+#define CLK_GPIO_RIGHT			137
+#define CLK_MONOCNT			138
+#define CLK_TZPC6			139
+#define CLK_PROVISIONKEY1		140
+#define CLK_PROVISIONKEY0		141
+#define CLK_CMU_ISPPART			142
+#define CLK_TMU_APBIF			143
+#define CLK_KEYIF			144
+#define CLK_RTC				145
+#define CLK_WDT				146
+#define CLK_MCT				147
+#define CLK_SECKEY			148
+#define CLK_TZPC5			149
+#define CLK_TZPC4			150
+#define CLK_TZPC3			151
+#define CLK_TZPC2			152
+#define CLK_TZPC1			153
+#define CLK_TZPC0			154
+#define CLK_CMU_COREPART		155
+#define CLK_CMU_TOPPART			156
+#define CLK_PMU_APBIF			157
+#define CLK_SYSREG			158
+#define CLK_CHIP_ID			159
+#define CLK_QEJPEG			160
+#define CLK_PIXELASYNCM1		161
+#define CLK_PIXELASYNCM0		162
+#define CLK_PPMUCAMIF			163
+#define CLK_QEM2MSCALER			164
+#define CLK_QEGSCALER1			165
+#define CLK_QEGSCALER0			166
+#define CLK_SMMUJPEG			167
+#define CLK_SMMUM2M2SCALER		168
+#define CLK_SMMUGSCALER1		169
+#define CLK_SMMUGSCALER0		170
+#define CLK_JPEG			171
+#define CLK_M2MSCALER			172
+#define CLK_GSCALER1			173
+#define CLK_GSCALER0			174
+#define CLK_QEMFC			175
+#define CLK_PPMUMFC_L			176
+#define CLK_SMMUMFC_L			177
+#define CLK_MFC				178
+#define CLK_SMMUG3D			179
+#define CLK_QEG3D			180
+#define CLK_PPMUG3D			181
+#define CLK_G3D				182
+#define CLK_QE_CH1_LCD			183
+#define CLK_QE_CH0_LCD			184
+#define CLK_PPMULCD0			185
+#define CLK_SMMUFIMD0			186
+#define CLK_DSIM0			187
+#define CLK_FIMD0			188
+#define CLK_CAM1			189
+#define CLK_UART_ISP_TOP		190
+#define CLK_SPI1_ISP_TOP		191
+#define CLK_SPI0_ISP_TOP		192
+#define CLK_TSADC			193
+#define CLK_PPMUFILE			194
+#define CLK_USBOTG			195
+#define CLK_USBHOST			196
+#define CLK_SROMC			197
+#define CLK_SDMMC1			198
+#define CLK_SDMMC0			199
+#define CLK_PDMA1			200
+#define CLK_PDMA0			201
+#define CLK_PWM				202
+#define CLK_PCM				203
+#define CLK_I2S				204
+#define CLK_SPI1			205
+#define CLK_SPI0			206
+#define CLK_I2C7			207
+#define CLK_I2C6			208
+#define CLK_I2C5			209
+#define CLK_I2C4			210
+#define CLK_I2C3			211
+#define CLK_I2C2			212
+#define CLK_I2C1			213
+#define CLK_I2C0			214
+#define CLK_UART1			215
+#define CLK_UART0			216
+#define CLK_BLOCK_LCD			217
+#define CLK_BLOCK_G3D			218
+#define CLK_BLOCK_MFC			219
+#define CLK_BLOCK_CAM			220
+#define CLK_SMIES			221
+#define CLK_UART2			222
+#define CLK_SDMMC2			223
+
+/* Special clocks */
+#define CLK_SCLK_JPEG			224
+#define CLK_SCLK_M2MSCALER		225
+#define CLK_SCLK_GSCALER1		226
+#define CLK_SCLK_GSCALER0		227
+#define CLK_SCLK_MFC			228
+#define CLK_SCLK_G3D			229
+#define CLK_SCLK_MIPIDPHY2L		230
+#define CLK_SCLK_MIPI0			231
+#define CLK_SCLK_FIMD0			232
+#define CLK_SCLK_CAM1			233
+#define CLK_SCLK_UART_ISP		234
+#define CLK_SCLK_SPI1_ISP		235
+#define CLK_SCLK_SPI0_ISP		236
+#define CLK_SCLK_UPLL			237
+#define CLK_SCLK_TSADC			238
+#define CLK_SCLK_EBI			239
+#define CLK_SCLK_MMC1			240
+#define CLK_SCLK_MMC0			241
+#define CLK_SCLK_I2S			242
+#define CLK_SCLK_PCM			243
+#define CLK_SCLK_SPI1			244
+#define CLK_SCLK_SPI0			245
+#define CLK_SCLK_UART1			246
+#define CLK_SCLK_UART0			247
+#define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
+
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL			1
+#define CLK_FOUT_EPLL			2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF		8
+#define CLK_MOUT_BPLL			9
+#define CLK_MOUT_DPHY			10
+#define CLK_MOUT_DMC_BUS		11
+#define CLK_MOUT_EPLL			12
+
+/* Dividers */
+#define CLK_DIV_DMC			16
+#define CLK_DIV_DPHY			17
+#define CLK_DIV_DMC_PRE			18
+#define CLK_DIV_DMCP			19
+#define CLK_DIV_DMCD			20
+
+/*
+ * CMU ISP
+ */
+
+/* Dividers */
+
+#define CLK_DIV_ISP1			1
+#define CLK_DIV_ISP0			2
+#define CLK_DIV_MCUISP1			3
+#define CLK_DIV_MCUISP0			4
+#define CLK_DIV_MPWM			5
+
+/* Gates */
+
+#define CLK_UART_ISP			8
+#define CLK_WDT_ISP			9
+#define CLK_PWM_ISP			10
+#define CLK_I2C1_ISP			11
+#define CLK_I2C0_ISP			12
+#define CLK_MPWM_ISP			13
+#define CLK_MCUCTL_ISP			14
+#define CLK_PPMUISPX			15
+#define CLK_PPMUISPMX			16
+#define CLK_QE_LITE1			17
+#define CLK_QE_LITE0			18
+#define CLK_QE_FD			19
+#define CLK_QE_DRC			20
+#define CLK_QE_ISP			21
+#define CLK_CSIS1			22
+#define CLK_SMMU_LITE1			23
+#define CLK_SMMU_LITE0			24
+#define CLK_SMMU_FD			25
+#define CLK_SMMU_DRC			26
+#define CLK_SMMU_ISP			27
+#define CLK_GICISP			28
+#define CLK_CSIS0			29
+#define CLK_MCUISP			30
+#define CLK_LITE1			31
+#define CLK_LITE0			32
+#define CLK_FD				33
+#define CLK_DRC				34
+#define CLK_ISP				35
+#define CLK_QE_ISPCX			36
+#define CLK_QE_SCALERP			37
+#define CLK_QE_SCALERC			38
+#define CLK_SMMU_SCALERP		39
+#define CLK_SMMU_SCALERC		40
+#define CLK_SCALERP			41
+#define CLK_SCALERC			42
+#define CLK_SPI1_ISP			43
+#define CLK_SPI0_ISP			44
+#define CLK_SMMU_ISPCX			45
+#define CLK_ASYNCAXIM			46
+#define CLK_SCLK_MPWM_ISP		47
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/exynos4.h

@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * Device Tree binding constants for Exynos4 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
+
+/* core clocks */
+#define CLK_XXTI		1
+#define CLK_XUSBXTI		2
+#define CLK_FIN_PLL		3
+#define CLK_FOUT_APLL		4
+#define CLK_FOUT_MPLL		5
+#define CLK_FOUT_EPLL		6
+#define CLK_FOUT_VPLL		7
+#define CLK_SCLK_APLL		8
+#define CLK_SCLK_MPLL		9
+#define CLK_SCLK_EPLL		10
+#define CLK_SCLK_VPLL		11
+#define CLK_ARM_CLK		12
+#define CLK_ACLK200		13
+#define CLK_ACLK100		14
+#define CLK_ACLK160		15
+#define CLK_ACLK133		16
+#define CLK_MOUT_MPLL_USER_T	17 /* Exynos4x12 only */
+#define CLK_MOUT_MPLL_USER_C	18 /* Exynos4x12 only */
+#define CLK_MOUT_CORE		19
+#define CLK_MOUT_APLL		20
+#define CLK_SCLK_HDMIPHY	22
+#define CLK_OUT_DMC		23
+#define CLK_OUT_TOP		24
+#define CLK_OUT_LEFTBUS		25
+#define CLK_OUT_RIGHTBUS	26
+#define CLK_OUT_CPU		27
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_FIMC0		128
+#define CLK_SCLK_FIMC1		129
+#define CLK_SCLK_FIMC2		130
+#define CLK_SCLK_FIMC3		131
+#define CLK_SCLK_CAM0		132
+#define CLK_SCLK_CAM1		133
+#define CLK_SCLK_CSIS0		134
+#define CLK_SCLK_CSIS1		135
+#define CLK_SCLK_HDMI		136
+#define CLK_SCLK_MIXER		137
+#define CLK_SCLK_DAC		138
+#define CLK_SCLK_PIXEL		139
+#define CLK_SCLK_FIMD0		140
+#define CLK_SCLK_MDNIE0		141 /* Exynos4412 only */
+#define CLK_SCLK_MDNIE_PWM0	142
+#define CLK_SCLK_MIPI0		143
+#define CLK_SCLK_AUDIO0		144
+#define CLK_SCLK_MMC0		145
+#define CLK_SCLK_MMC1		146
+#define CLK_SCLK_MMC2		147
+#define CLK_SCLK_MMC3		148
+#define CLK_SCLK_MMC4		149
+#define CLK_SCLK_SATA		150 /* Exynos4210 only */
+#define CLK_SCLK_UART0		151
+#define CLK_SCLK_UART1		152
+#define CLK_SCLK_UART2		153
+#define CLK_SCLK_UART3		154
+#define CLK_SCLK_UART4		155
+#define CLK_SCLK_AUDIO1		156
+#define CLK_SCLK_AUDIO2		157
+#define CLK_SCLK_SPDIF		158
+#define CLK_SCLK_SPI0		159
+#define CLK_SCLK_SPI1		160
+#define CLK_SCLK_SPI2		161
+#define CLK_SCLK_SLIMBUS	162
+#define CLK_SCLK_FIMD1		163 /* Exynos4210 only */
+#define CLK_SCLK_MIPI1		164 /* Exynos4210 only */
+#define CLK_SCLK_PCM1		165
+#define CLK_SCLK_PCM2		166
+#define CLK_SCLK_I2S1		167
+#define CLK_SCLK_I2S2		168
+#define CLK_SCLK_MIPIHSI	169 /* Exynos4412 only */
+#define CLK_SCLK_MFC		170
+#define CLK_SCLK_PCM0		171
+#define CLK_SCLK_G3D		172
+#define CLK_SCLK_PWM_ISP	173 /* Exynos4x12 only */
+#define CLK_SCLK_SPI0_ISP	174 /* Exynos4x12 only */
+#define CLK_SCLK_SPI1_ISP	175 /* Exynos4x12 only */
+#define CLK_SCLK_UART_ISP	176 /* Exynos4x12 only */
+#define CLK_SCLK_FIMG2D		177
+
+/* gate clocks */
+#define CLK_SSS			255
+#define CLK_FIMC0		256
+#define CLK_FIMC1		257
+#define CLK_FIMC2		258
+#define CLK_FIMC3		259
+#define CLK_CSIS0		260
+#define CLK_CSIS1		261
+#define CLK_JPEG		262
+#define CLK_SMMU_FIMC0		263
+#define CLK_SMMU_FIMC1		264
+#define CLK_SMMU_FIMC2		265
+#define CLK_SMMU_FIMC3		266
+#define CLK_SMMU_JPEG		267
+#define CLK_VP			268
+#define CLK_MIXER		269
+#define CLK_TVENC		270 /* Exynos4210 only */
+#define CLK_HDMI		271
+#define CLK_SMMU_TV		272
+#define CLK_MFC			273
+#define CLK_SMMU_MFCL		274
+#define CLK_SMMU_MFCR		275
+#define CLK_G3D			276
+#define CLK_G2D			277
+#define CLK_ROTATOR		278
+#define CLK_MDMA		279
+#define CLK_SMMU_G2D		280
+#define CLK_SMMU_ROTATOR	281
+#define CLK_SMMU_MDMA		282
+#define CLK_FIMD0		283
+#define CLK_MIE0		284
+#define CLK_MDNIE0		285 /* Exynos4412 only */
+#define CLK_DSIM0		286
+#define CLK_SMMU_FIMD0		287
+#define CLK_FIMD1		288 /* Exynos4210 only */
+#define CLK_MIE1		289 /* Exynos4210 only */
+#define CLK_DSIM1		290 /* Exynos4210 only */
+#define CLK_SMMU_FIMD1		291 /* Exynos4210 only */
+#define CLK_PDMA0		292
+#define CLK_PDMA1		293
+#define CLK_PCIE_PHY		294
+#define CLK_SATA_PHY		295 /* Exynos4210 only */
+#define CLK_TSI			296
+#define CLK_SDMMC0		297
+#define CLK_SDMMC1		298
+#define CLK_SDMMC2		299
+#define CLK_SDMMC3		300
+#define CLK_SDMMC4		301
+#define CLK_SATA		302 /* Exynos4210 only */
+#define CLK_SROMC		303
+#define CLK_USB_HOST		304
+#define CLK_USB_DEVICE		305
+#define CLK_PCIE		306
+#define CLK_ONENAND		307
+#define CLK_NFCON		308
+#define CLK_SMMU_PCIE		309
+#define CLK_GPS			310
+#define CLK_SMMU_GPS		311
+#define CLK_UART0		312
+#define CLK_UART1		313
+#define CLK_UART2		314
+#define CLK_UART3		315
+#define CLK_UART4		316
+#define CLK_I2C0		317
+#define CLK_I2C1		318
+#define CLK_I2C2		319
+#define CLK_I2C3		320
+#define CLK_I2C4		321
+#define CLK_I2C5		322
+#define CLK_I2C6		323
+#define CLK_I2C7		324
+#define CLK_I2C_HDMI		325
+#define CLK_TSADC		326
+#define CLK_SPI0		327
+#define CLK_SPI1		328
+#define CLK_SPI2		329
+#define CLK_I2S1		330
+#define CLK_I2S2		331
+#define CLK_PCM0		332
+#define CLK_I2S0		333
+#define CLK_PCM1		334
+#define CLK_PCM2		335
+#define CLK_PWM			336
+#define CLK_SLIMBUS		337
+#define CLK_SPDIF		338
+#define CLK_AC97		339
+#define CLK_MODEMIF		340
+#define CLK_CHIPID		341
+#define CLK_SYSREG		342
+#define CLK_HDMI_CEC		343
+#define CLK_MCT			344
+#define CLK_WDT			345
+#define CLK_RTC			346
+#define CLK_KEYIF		347
+#define CLK_AUDSS		348
+#define CLK_MIPI_HSI		349 /* Exynos4210 only */
+#define CLK_PIXELASYNCM0	351
+#define CLK_PIXELASYNCM1	352
+#define CLK_ASYNC_G3D		353 /* Exynos4x12 only */
+#define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */
+#define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */
+#define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */
+#define CLK_UART_ISP_SCLK	382 /* Exynos4x12 only */
+#define CLK_TMU_APBIF		383
+
+/* mux clocks */
+#define CLK_MOUT_FIMC0		384
+#define CLK_MOUT_FIMC1		385
+#define CLK_MOUT_FIMC2		386
+#define CLK_MOUT_FIMC3		387
+#define CLK_MOUT_CAM0		388
+#define CLK_MOUT_CAM1		389
+#define CLK_MOUT_CSIS0		390
+#define CLK_MOUT_CSIS1		391
+#define CLK_MOUT_G3D0		392
+#define CLK_MOUT_G3D1		393
+#define CLK_MOUT_G3D		394
+#define CLK_ACLK400_MCUISP	395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI		396
+#define CLK_MOUT_MIXER		397
+#define CLK_MOUT_VPLLSRC	398
+
+/* gate clocks - ppmu */
+#define CLK_PPMULEFT		400
+#define CLK_PPMURIGHT		401
+#define CLK_PPMUCAMIF		402
+#define CLK_PPMUTV		403
+#define CLK_PPMUMFC_L		404
+#define CLK_PPMUMFC_R		405
+#define CLK_PPMUG3D		406
+#define CLK_PPMUIMAGE		407
+#define CLK_PPMULCD0		408
+#define CLK_PPMULCD1		409 /* Exynos4210 only */
+#define CLK_PPMUFILE		410
+#define CLK_PPMUGPS		411
+#define CLK_PPMUDMC0		412
+#define CLK_PPMUDMC1		413
+#define CLK_PPMUCPU		414
+#define CLK_PPMUACP		415
+
+/* div clocks */
+#define CLK_DIV_ACLK200		454 /* Exynos4x12 only */
+#define CLK_DIV_ACLK400_MCUISP	455 /* Exynos4x12 only */
+#define CLK_DIV_ACP		456
+#define CLK_DIV_DMC		457
+#define CLK_DIV_C2C		458 /* Exynos4x12 only */
+#define CLK_DIV_GDL		459
+#define CLK_DIV_GDR		460
+#define CLK_DIV_CORE2		461
+
+/* Exynos4x12 ISP clocks */
+#define CLK_ISP_FIMC_ISP		 1
+#define CLK_ISP_FIMC_DRC		 2
+#define CLK_ISP_FIMC_FD			 3
+#define CLK_ISP_FIMC_LITE0		 4
+#define CLK_ISP_FIMC_LITE1		 5
+#define CLK_ISP_MCUISP			 6
+#define CLK_ISP_GICISP			 7
+#define CLK_ISP_SMMU_ISP		 8
+#define CLK_ISP_SMMU_DRC		 9
+#define CLK_ISP_SMMU_FD			10
+#define CLK_ISP_SMMU_LITE0		11
+#define CLK_ISP_SMMU_LITE1		12
+#define CLK_ISP_PPMUISPMX		13
+#define CLK_ISP_PPMUISPX		14
+#define CLK_ISP_MCUCTL_ISP		15
+#define CLK_ISP_MPWM_ISP		16
+#define CLK_ISP_I2C0_ISP		17
+#define CLK_ISP_I2C1_ISP		18
+#define CLK_ISP_MTCADC_ISP		19
+#define CLK_ISP_PWM_ISP			20
+#define CLK_ISP_WDT_ISP			21
+#define CLK_ISP_UART_ISP		22
+#define CLK_ISP_ASYNCAXIM		23
+#define CLK_ISP_SMMU_ISPCX		24
+#define CLK_ISP_SPI0_ISP		25
+#define CLK_ISP_SPI1_ISP		26
+
+#define CLK_ISP_DIV_ISP0		27
+#define CLK_ISP_DIV_ISP1		28
+#define CLK_ISP_DIV_MCUISP0		29
+#define CLK_ISP_DIV_MCUISP1		30
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */

linux-7.2.3/include/dt-bindings/clock/exynos5250.h

@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * Device Tree binding constants for Exynos5250 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_MPLL		3
+#define CLK_FOUT_BPLL		4
+#define CLK_FOUT_GPLL		5
+#define CLK_FOUT_CPLL		6
+#define CLK_FOUT_EPLL		7
+#define CLK_FOUT_VPLL		8
+#define CLK_ARM_CLK		9
+#define CLK_DIV_ARM2		10
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_CAM_BAYER	128
+#define CLK_SCLK_CAM0		129
+#define CLK_SCLK_CAM1		130
+#define CLK_SCLK_GSCL_WA	131
+#define CLK_SCLK_GSCL_WB	132
+#define CLK_SCLK_FIMD1		133
+#define CLK_SCLK_MIPI1		134
+#define CLK_SCLK_DP		135
+#define CLK_SCLK_HDMI		136
+#define CLK_SCLK_PIXEL		137
+#define CLK_SCLK_AUDIO0		138
+#define CLK_SCLK_MMC0		139
+#define CLK_SCLK_MMC1		140
+#define CLK_SCLK_MMC2		141
+#define CLK_SCLK_MMC3		142
+#define CLK_SCLK_SATA		143
+#define CLK_SCLK_USB3		144
+#define CLK_SCLK_JPEG		145
+#define CLK_SCLK_UART0		146
+#define CLK_SCLK_UART1		147
+#define CLK_SCLK_UART2		148
+#define CLK_SCLK_UART3		149
+#define CLK_SCLK_PWM		150
+#define CLK_SCLK_AUDIO1		151
+#define CLK_SCLK_AUDIO2		152
+#define CLK_SCLK_SPDIF		153
+#define CLK_SCLK_SPI0		154
+#define CLK_SCLK_SPI1		155
+#define CLK_SCLK_SPI2		156
+#define CLK_DIV_I2S1		157
+#define CLK_DIV_I2S2		158
+#define CLK_SCLK_HDMIPHY	159
+#define CLK_DIV_PCM0		160
+
+/* gate clocks */
+#define CLK_GSCL0		256
+#define CLK_GSCL1		257
+#define CLK_GSCL2		258
+#define CLK_GSCL3		259
+#define CLK_GSCL_WA		260
+#define CLK_GSCL_WB		261
+#define CLK_SMMU_GSCL0		262
+#define CLK_SMMU_GSCL1		263
+#define CLK_SMMU_GSCL2		264
+#define CLK_SMMU_GSCL3		265
+#define CLK_MFC			266
+#define CLK_SMMU_MFCL		267
+#define CLK_SMMU_MFCR		268
+#define CLK_ROTATOR		269
+#define CLK_JPEG		270
+#define CLK_MDMA1		271
+#define CLK_SMMU_ROTATOR	272
+#define CLK_SMMU_JPEG		273
+#define CLK_SMMU_MDMA1		274
+#define CLK_PDMA0		275
+#define CLK_PDMA1		276
+#define CLK_SATA		277
+#define CLK_USBOTG		278
+#define CLK_MIPI_HSI		279
+#define CLK_SDMMC0		280
+#define CLK_SDMMC1		281
+#define CLK_SDMMC2		282
+#define CLK_SDMMC3		283
+#define CLK_SROMC		284
+#define CLK_USB2		285
+#define CLK_USB3		286
+#define CLK_SATA_PHYCTRL	287
+#define CLK_SATA_PHYI2C		288
+#define CLK_UART0		289
+#define CLK_UART1		290
+#define CLK_UART2		291
+#define CLK_UART3		292
+#define CLK_UART4		293
+#define CLK_I2C0		294
+#define CLK_I2C1		295
+#define CLK_I2C2		296
+#define CLK_I2C3		297
+#define CLK_I2C4		298
+#define CLK_I2C5		299
+#define CLK_I2C6		300
+#define CLK_I2C7		301
+#define CLK_I2C_HDMI		302
+#define CLK_ADC			303
+#define CLK_SPI0		304
+#define CLK_SPI1		305
+#define CLK_SPI2		306
+#define CLK_I2S1		307
+#define CLK_I2S2		308
+#define CLK_PCM1		309
+#define CLK_PCM2		310
+#define CLK_PWM			311
+#define CLK_SPDIF		312
+#define CLK_AC97		313
+#define CLK_HSI2C0		314
+#define CLK_HSI2C1		315
+#define CLK_HSI2C2		316
+#define CLK_HSI2C3		317
+#define CLK_CHIPID		318
+#define CLK_SYSREG		319
+#define CLK_PMU			320
+#define CLK_CMU_TOP		321
+#define CLK_CMU_CORE		322
+#define CLK_CMU_MEM		323
+#define CLK_TZPC0		324
+#define CLK_TZPC1		325
+#define CLK_TZPC2		326
+#define CLK_TZPC3		327
+#define CLK_TZPC4		328
+#define CLK_TZPC5		329
+#define CLK_TZPC6		330
+#define CLK_TZPC7		331
+#define CLK_TZPC8		332
+#define CLK_TZPC9		333
+#define CLK_HDMI_CEC		334
+#define CLK_MCT			335
+#define CLK_WDT			336
+#define CLK_RTC			337
+#define CLK_TMU			338
+#define CLK_FIMD1		339
+#define CLK_MIE1		340
+#define CLK_DSIM0		341
+#define CLK_DP			342
+#define CLK_MIXER		343
+#define CLK_HDMI		344
+#define CLK_G2D			345
+#define CLK_MDMA0		346
+#define CLK_SMMU_MDMA0		347
+#define CLK_SSS			348
+#define CLK_G3D			349
+#define CLK_SMMU_TV		350
+#define CLK_SMMU_FIMD1		351
+#define CLK_SMMU_2D		352
+#define CLK_SMMU_FIMC_ISP	353
+#define CLK_SMMU_FIMC_DRC	354
+#define CLK_SMMU_FIMC_SCC	355
+#define CLK_SMMU_FIMC_SCP	356
+#define CLK_SMMU_FIMC_FD	357
+#define CLK_SMMU_FIMC_MCU	358
+#define CLK_SMMU_FIMC_ODC	359
+#define CLK_SMMU_FIMC_DIS0	360
+#define CLK_SMMU_FIMC_DIS1	361
+#define CLK_SMMU_FIMC_3DNR	362
+#define CLK_SMMU_FIMC_LITE0	363
+#define CLK_SMMU_FIMC_LITE1	364
+#define CLK_CAMIF_TOP		365
+
+/* mux clocks */
+#define CLK_MOUT_HDMI		1024
+#define CLK_MOUT_GPLL		1025
+#define CLK_MOUT_ACLK200_DISP1_SUB	1026
+#define CLK_MOUT_ACLK300_DISP1_SUB	1027
+#define CLK_MOUT_APLL		1028
+#define CLK_MOUT_MPLL		1029
+#define CLK_MOUT_VPLLSRC	1030
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

linux-7.2.3/include/dt-bindings/clock/exynos5260-clk.h

@@ -0,0 +1,441 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Rahul Sharma <rahul.sharma@samsung.com>
+ *
+ * Provides Constants for Exynos5260 clocks.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/* Clock names: <cmu><type><IP> */
+
+/* List Of Clocks For CMU_TOP */
+
+#define TOP_FOUT_DISP_PLL				1
+#define TOP_FOUT_AUD_PLL				2
+#define TOP_MOUT_AUDTOP_PLL_USER			3
+#define TOP_MOUT_AUD_PLL				4
+#define TOP_MOUT_DISP_PLL				5
+#define TOP_MOUT_BUSTOP_PLL_USER			6
+#define TOP_MOUT_MEMTOP_PLL_USER			7
+#define TOP_MOUT_MEDIATOP_PLL_USER			8
+#define TOP_MOUT_DISP_DISP_333				9
+#define TOP_MOUT_ACLK_DISP_333				10
+#define TOP_MOUT_DISP_DISP_222				11
+#define TOP_MOUT_ACLK_DISP_222				12
+#define TOP_MOUT_DISP_MEDIA_PIXEL			13
+#define TOP_MOUT_FIMD1					14
+#define TOP_MOUT_SCLK_PERI_SPI0_CLK			15
+#define TOP_MOUT_SCLK_PERI_SPI1_CLK			16
+#define TOP_MOUT_SCLK_PERI_SPI2_CLK			17
+#define TOP_MOUT_SCLK_PERI_UART0_UCLK			18
+#define TOP_MOUT_SCLK_PERI_UART2_UCLK			19
+#define TOP_MOUT_SCLK_PERI_UART1_UCLK			20
+#define TOP_MOUT_BUS4_BUSTOP_100			21
+#define TOP_MOUT_BUS4_BUSTOP_400			22
+#define TOP_MOUT_BUS3_BUSTOP_100			23
+#define TOP_MOUT_BUS3_BUSTOP_400			24
+#define TOP_MOUT_BUS2_BUSTOP_400			25
+#define TOP_MOUT_BUS2_BUSTOP_100			26
+#define TOP_MOUT_BUS1_BUSTOP_100			27
+#define TOP_MOUT_BUS1_BUSTOP_400			28
+#define TOP_MOUT_SCLK_FSYS_USB				29
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A		30
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A		31
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A		32
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B		33
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B		34
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B		35
+#define TOP_MOUT_ACLK_ISP1_266				36
+#define TOP_MOUT_ISP1_MEDIA_266				37
+#define TOP_MOUT_ACLK_ISP1_400				38
+#define TOP_MOUT_ISP1_MEDIA_400				39
+#define TOP_MOUT_SCLK_ISP1_SPI0				40
+#define TOP_MOUT_SCLK_ISP1_SPI1				41
+#define TOP_MOUT_SCLK_ISP1_UART				42
+#define TOP_MOUT_SCLK_ISP1_SENSOR2			43
+#define TOP_MOUT_SCLK_ISP1_SENSOR1			44
+#define TOP_MOUT_SCLK_ISP1_SENSOR0			45
+#define TOP_MOUT_ACLK_MFC_333				46
+#define TOP_MOUT_MFC_BUSTOP_333				47
+#define TOP_MOUT_ACLK_G2D_333				48
+#define TOP_MOUT_G2D_BUSTOP_333				49
+#define TOP_MOUT_ACLK_GSCL_FIMC				50
+#define TOP_MOUT_GSCL_BUSTOP_FIMC			51
+#define TOP_MOUT_ACLK_GSCL_333				52
+#define TOP_MOUT_GSCL_BUSTOP_333			53
+#define TOP_MOUT_ACLK_GSCL_400				54
+#define TOP_MOUT_M2M_MEDIATOP_400			55
+#define TOP_DOUT_ACLK_MFC_333				56
+#define TOP_DOUT_ACLK_G2D_333				57
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_A			58
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_A			59
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_A			60
+#define TOP_DOUT_ACLK_GSCL_FIMC				61
+#define TOP_DOUT_ACLK_GSCL_400				62
+#define TOP_DOUT_ACLK_GSCL_333				63
+#define TOP_DOUT_SCLK_ISP1_SPI0_B			64
+#define TOP_DOUT_SCLK_ISP1_SPI0_A			65
+#define TOP_DOUT_ACLK_ISP1_400				66
+#define TOP_DOUT_ACLK_ISP1_266				67
+#define TOP_DOUT_SCLK_ISP1_UART				68
+#define TOP_DOUT_SCLK_ISP1_SPI1_B			69
+#define TOP_DOUT_SCLK_ISP1_SPI1_A			70
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_B			71
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_B			72
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_B			73
+#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK			74
+#define TOP_DOUT_SCLK_DISP_PIXEL			75
+#define TOP_DOUT_ACLK_DISP_222				76
+#define TOP_DOUT_ACLK_DISP_333				77
+#define TOP_DOUT_ACLK_BUS4_100				78
+#define TOP_DOUT_ACLK_BUS4_400				79
+#define TOP_DOUT_ACLK_BUS3_100				80
+#define TOP_DOUT_ACLK_BUS3_400				81
+#define TOP_DOUT_ACLK_BUS2_100				82
+#define TOP_DOUT_ACLK_BUS2_400				83
+#define TOP_DOUT_ACLK_BUS1_100				84
+#define TOP_DOUT_ACLK_BUS1_400				85
+#define TOP_DOUT_SCLK_PERI_SPI1_B			86
+#define TOP_DOUT_SCLK_PERI_SPI1_A			87
+#define TOP_DOUT_SCLK_PERI_SPI0_B			88
+#define TOP_DOUT_SCLK_PERI_SPI0_A			89
+#define TOP_DOUT_SCLK_PERI_UART0			90
+#define TOP_DOUT_SCLK_PERI_UART2			91
+#define TOP_DOUT_SCLK_PERI_UART1			92
+#define TOP_DOUT_SCLK_PERI_SPI2_B			93
+#define TOP_DOUT_SCLK_PERI_SPI2_A			94
+#define TOP_DOUT_ACLK_PERI_AUD				95
+#define TOP_DOUT_ACLK_PERI_66				96
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B		97
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A		98
+#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK		99
+#define TOP_DOUT_ACLK_FSYS_200				100
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B		101
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A		102
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B		103
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A		104
+#define TOP_SCLK_FIMD1					105
+#define TOP_SCLK_MMC2					106
+#define TOP_SCLK_MMC1					107
+#define TOP_SCLK_MMC0					108
+#define PHYCLK_DPTX_PHY_CH3_TXD_CLK			109
+#define PHYCLK_DPTX_PHY_CH2_TXD_CLK			110
+#define PHYCLK_DPTX_PHY_CH1_TXD_CLK			111
+#define PHYCLK_DPTX_PHY_CH0_TXD_CLK			112
+#define phyclk_hdmi_phy_tmds_clko			113
+#define PHYCLK_HDMI_PHY_PIXEL_CLKO			114
+#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI			115
+#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS		116
+#define PHYCLK_DPTX_PHY_O_REF_CLK_24M			117
+#define PHYCLK_DPTX_PHY_CLK_DIV2			118
+#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0			119
+#define PHYCLK_USBHOST20_PHY_PHYCLOCK			120
+#define PHYCLK_USBHOST20_PHY_FREECLK			121
+#define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
+#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
+#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
+
+/* List Of Clocks For CMU_EGL */
+
+#define EGL_FOUT_EGL_PLL				1
+#define EGL_FOUT_EGL_DPLL				2
+#define EGL_MOUT_EGL_B					3
+#define EGL_MOUT_EGL_PLL				4
+#define EGL_DOUT_EGL_PLL				5
+#define EGL_DOUT_EGL_PCLK_DBG				6
+#define EGL_DOUT_EGL_ATCLK				7
+#define EGL_DOUT_PCLK_EGL				8
+#define EGL_DOUT_ACLK_EGL				9
+#define EGL_DOUT_EGL2					10
+#define EGL_DOUT_EGL1					11
+
+/* List Of Clocks For CMU_KFC */
+
+#define KFC_FOUT_KFC_PLL				1
+#define KFC_MOUT_KFC_PLL				2
+#define KFC_MOUT_KFC					3
+#define KFC_DOUT_KFC_PLL				4
+#define KFC_DOUT_PCLK_KFC				5
+#define KFC_DOUT_ACLK_KFC				6
+#define KFC_DOUT_KFC_PCLK_DBG				7
+#define KFC_DOUT_KFC_ATCLK				8
+#define KFC_DOUT_KFC2					9
+#define KFC_DOUT_KFC1					10
+
+/* List Of Clocks For CMU_MIF */
+
+#define MIF_FOUT_MEM_PLL				1
+#define MIF_FOUT_MEDIA_PLL				2
+#define MIF_FOUT_BUS_PLL				3
+#define MIF_MOUT_CLK2X_PHY				4
+#define MIF_MOUT_MIF_DREX2X				5
+#define MIF_MOUT_CLKM_PHY				6
+#define MIF_MOUT_MIF_DREX				7
+#define MIF_MOUT_MEDIA_PLL				8
+#define MIF_MOUT_BUS_PLL				9
+#define MIF_MOUT_MEM_PLL				10
+#define MIF_DOUT_ACLK_BUS_100				11
+#define MIF_DOUT_ACLK_BUS_200				12
+#define MIF_DOUT_ACLK_MIF_466				13
+#define MIF_DOUT_CLK2X_PHY				14
+#define MIF_DOUT_CLKM_PHY				15
+#define MIF_DOUT_BUS_PLL				16
+#define MIF_DOUT_MEM_PLL				17
+#define MIF_DOUT_MEDIA_PLL				18
+#define MIF_CLK_LPDDR3PHY_WRAP1				19
+#define MIF_CLK_LPDDR3PHY_WRAP0				20
+#define MIF_CLK_MONOCNT					21
+#define MIF_CLK_MIF_RTC					22
+#define MIF_CLK_DREX1					23
+#define MIF_CLK_DREX0					24
+#define MIF_CLK_INTMEM					25
+#define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
+#define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
+
+/* List Of Clocks For CMU_G3D */
+
+#define G3D_FOUT_G3D_PLL				1
+#define G3D_MOUT_G3D_PLL				2
+#define G3D_DOUT_PCLK_G3D				3
+#define G3D_DOUT_ACLK_G3D				4
+#define G3D_CLK_G3D_HPM					5
+#define G3D_CLK_G3D					6
+
+/* List Of Clocks For CMU_AUD */
+
+#define AUD_MOUT_SCLK_AUD_PCM				1
+#define AUD_MOUT_SCLK_AUD_I2S				2
+#define AUD_MOUT_AUD_PLL_USER				3
+#define AUD_DOUT_ACLK_AUD_131				4
+#define AUD_DOUT_SCLK_AUD_UART				5
+#define AUD_DOUT_SCLK_AUD_PCM				6
+#define AUD_DOUT_SCLK_AUD_I2S				7
+#define AUD_CLK_AUD_UART				8
+#define AUD_CLK_PCM					9
+#define AUD_CLK_I2S					10
+#define AUD_CLK_DMAC					11
+#define AUD_CLK_SRAMC					12
+#define AUD_SCLK_AUD_UART				13
+#define AUD_SCLK_PCM					14
+#define AUD_SCLK_I2S					15
+
+/* List Of Clocks For CMU_MFC */
+
+#define MFC_MOUT_ACLK_MFC_333_USER			1
+#define MFC_DOUT_PCLK_MFC_83				2
+#define MFC_CLK_MFC					3
+#define MFC_CLK_SMMU2_MFCM1				4
+#define MFC_CLK_SMMU2_MFCM0				5
+
+/* List Of Clocks For CMU_GSCL */
+
+#define GSCL_MOUT_ACLK_CSIS				1
+#define GSCL_MOUT_ACLK_GSCL_FIMC_USER			2
+#define GSCL_MOUT_ACLK_M2M_400_USER			3
+#define GSCL_MOUT_ACLK_GSCL_333_USER			4
+#define GSCL_DOUT_ACLK_CSIS_200				5
+#define GSCL_DOUT_PCLK_M2M_100				6
+#define GSCL_CLK_PIXEL_GSCL1				7
+#define GSCL_CLK_PIXEL_GSCL0				8
+#define GSCL_CLK_MSCL1					9
+#define GSCL_CLK_MSCL0					10
+#define GSCL_CLK_GSCL1					11
+#define GSCL_CLK_GSCL0					12
+#define GSCL_CLK_FIMC_LITE_D				13
+#define GSCL_CLK_FIMC_LITE_B				14
+#define GSCL_CLK_FIMC_LITE_A				15
+#define GSCL_CLK_CSIS1					16
+#define GSCL_CLK_CSIS0					17
+#define GSCL_CLK_SMMU3_LITE_D				18
+#define GSCL_CLK_SMMU3_LITE_B				19
+#define GSCL_CLK_SMMU3_LITE_A				20
+#define GSCL_CLK_SMMU3_GSCL0				21
+#define GSCL_CLK_SMMU3_GSCL1				22
+#define GSCL_CLK_SMMU3_MSCL0				23
+#define GSCL_CLK_SMMU3_MSCL1				24
+#define GSCL_SCLK_CSIS1_WRAP				25
+#define GSCL_SCLK_CSIS0_WRAP				26
+
+/* List Of Clocks For CMU_FSYS */
+
+#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER		1
+#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER		2
+#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER	3
+#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER	4
+#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER		5
+#define FSYS_CLK_TSI					6
+#define FSYS_CLK_USBLINK				7
+#define FSYS_CLK_USBHOST20				8
+#define FSYS_CLK_USBDRD30				9
+#define FSYS_CLK_SROMC					10
+#define FSYS_CLK_PDMA					11
+#define FSYS_CLK_MMC2					12
+#define FSYS_CLK_MMC1					13
+#define FSYS_CLK_MMC0					14
+#define FSYS_CLK_RTIC					15
+#define FSYS_CLK_SMMU_RTIC				16
+#define FSYS_PHYCLK_USBDRD30				17
+#define FSYS_PHYCLK_USBHOST20				18
+
+/* List Of Clocks For CMU_PERI */
+
+#define PERI_MOUT_SCLK_SPDIF				1
+#define PERI_MOUT_SCLK_I2SCOD				2
+#define PERI_MOUT_SCLK_PCM				3
+#define PERI_DOUT_I2S					4
+#define PERI_DOUT_PCM					5
+#define PERI_CLK_WDT_KFC				6
+#define PERI_CLK_WDT_EGL				7
+#define PERI_CLK_HSIC3					8
+#define PERI_CLK_HSIC2					9
+#define PERI_CLK_HSIC1					10
+#define PERI_CLK_HSIC0					11
+#define PERI_CLK_PCM					12
+#define PERI_CLK_MCT					13
+#define PERI_CLK_I2S					14
+#define PERI_CLK_I2CHDMI				15
+#define PERI_CLK_I2C7					16
+#define PERI_CLK_I2C6					17
+#define PERI_CLK_I2C5					18
+#define PERI_CLK_I2C4					19
+#define PERI_CLK_I2C9					20
+#define PERI_CLK_I2C8					21
+#define PERI_CLK_I2C11					22
+#define PERI_CLK_I2C10					23
+#define PERI_CLK_HDMICEC				24
+#define PERI_CLK_EFUSE_WRITER				25
+#define PERI_CLK_ABB					26
+#define PERI_CLK_UART2					27
+#define PERI_CLK_UART1					28
+#define PERI_CLK_UART0					29
+#define PERI_CLK_ADC					30
+#define PERI_CLK_TMU4					31
+#define PERI_CLK_TMU3					32
+#define PERI_CLK_TMU2					33
+#define PERI_CLK_TMU1					34
+#define PERI_CLK_TMU0					35
+#define PERI_CLK_SPI2					36
+#define PERI_CLK_SPI1					37
+#define PERI_CLK_SPI0					38
+#define PERI_CLK_SPDIF					39
+#define PERI_CLK_PWM					40
+#define PERI_CLK_UART4					41
+#define PERI_CLK_CHIPID					42
+#define PERI_CLK_PROVKEY0				43
+#define PERI_CLK_PROVKEY1				44
+#define PERI_CLK_SECKEY					45
+#define PERI_CLK_TOP_RTC				46
+#define PERI_CLK_TZPC10					47
+#define PERI_CLK_TZPC9					48
+#define PERI_CLK_TZPC8					49
+#define PERI_CLK_TZPC7					50
+#define PERI_CLK_TZPC6					51
+#define PERI_CLK_TZPC5					52
+#define PERI_CLK_TZPC4					53
+#define PERI_CLK_TZPC3					54
+#define PERI_CLK_TZPC2					55
+#define PERI_CLK_TZPC1					56
+#define PERI_CLK_TZPC0					57
+#define PERI_SCLK_UART2					58
+#define PERI_SCLK_UART1					59
+#define PERI_SCLK_UART0					60
+#define PERI_SCLK_SPI2					61
+#define PERI_SCLK_SPI1					62
+#define PERI_SCLK_SPI0					63
+#define PERI_SCLK_SPDIF					64
+#define PERI_SCLK_I2S					65
+#define PERI_SCLK_PCM1					66
+
+/* List Of Clocks For CMU_DISP */
+
+#define DISP_MOUT_SCLK_HDMI_SPDIF			1
+#define DISP_MOUT_SCLK_HDMI_PIXEL			2
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER	3
+#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER	4
+#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER		5
+#define DISP_MOUT_HDMI_PHY_PIXEL			6
+#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER	7
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS	8
+#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER	9
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER		10
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER	11
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER	12
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER	13
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER	14
+#define DISP_MOUT_ACLK_DISP_222_USER			15
+#define DISP_MOUT_SCLK_DISP_PIXEL_USER			16
+#define DISP_MOUT_ACLK_DISP_333_USER			17
+#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI		18
+#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL			19
+#define DISP_DOUT_PCLK_DISP_111				20
+#define DISP_CLK_SMMU_TV				21
+#define DISP_CLK_SMMU_FIMD1M1				22
+#define DISP_CLK_SMMU_FIMD1M0				23
+#define DISP_CLK_PIXEL_MIXER				24
+#define DISP_CLK_PIXEL_DISP				25
+#define DISP_CLK_MIXER					26
+#define DISP_CLK_MIPIPHY				27
+#define DISP_CLK_HDMIPHY				28
+#define DISP_CLK_HDMI					29
+#define DISP_CLK_FIMD1					30
+#define DISP_CLK_DSIM1					31
+#define DISP_CLK_DPPHY					32
+#define DISP_CLK_DP					33
+#define DISP_SCLK_PIXEL					34
+#define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
+
+/* List Of Clocks For CMU_G2D */
+
+#define G2D_MOUT_ACLK_G2D_333_USER			1
+#define G2D_DOUT_PCLK_G2D_83				2
+#define G2D_CLK_SMMU3_JPEG				3
+#define G2D_CLK_MDMA					4
+#define G2D_CLK_JPEG					5
+#define G2D_CLK_G2D					6
+#define G2D_CLK_SSS					7
+#define G2D_CLK_SLIM_SSS				8
+#define G2D_CLK_SMMU_SLIM_SSS				9
+#define G2D_CLK_SMMU_SSS				10
+#define G2D_CLK_SMMU_MDMA				11
+#define G2D_CLK_SMMU3_G2D				12
+
+/* List Of Clocks For CMU_ISP */
+
+#define ISP_MOUT_ISP_400_USER				1
+#define ISP_MOUT_ISP_266_USER				2
+#define ISP_DOUT_SCLK_MPWM				3
+#define ISP_DOUT_CA5_PCLKDBG				4
+#define ISP_DOUT_CA5_ATCLKIN				5
+#define ISP_DOUT_PCLK_ISP_133				6
+#define ISP_DOUT_PCLK_ISP_66				7
+#define ISP_CLK_GIC					8
+#define ISP_CLK_WDT					9
+#define ISP_CLK_UART					10
+#define ISP_CLK_SPI1					11
+#define ISP_CLK_SPI0					12
+#define ISP_CLK_SMMU_SCALERP				13
+#define ISP_CLK_SMMU_SCALERC				14
+#define ISP_CLK_SMMU_ISPCX				15
+#define ISP_CLK_SMMU_ISP				16
+#define ISP_CLK_SMMU_FD					17
+#define ISP_CLK_SMMU_DRC				18
+#define ISP_CLK_PWM					19
+#define ISP_CLK_MTCADC					20
+#define ISP_CLK_MPWM					21
+#define ISP_CLK_MCUCTL					22
+#define ISP_CLK_I2C1					23
+#define ISP_CLK_I2C0					24
+#define ISP_CLK_FIMC_SCALERP				25
+#define ISP_CLK_FIMC_SCALERC				26
+#define ISP_CLK_FIMC					27
+#define ISP_CLK_FIMC_FD					28
+#define ISP_CLK_FIMC_DRC				29
+#define ISP_CLK_CA5					30
+#define ISP_SCLK_SPI0_EXT				31
+#define ISP_SCLK_SPI1_EXT				32
+#define ISP_SCLK_UART_EXT				33
+
+#endif

linux-7.2.3/include/dt-bindings/clock/exynos5410.h

@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * Device Tree binding constants for Exynos5421 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_MPLL		4
+#define CLK_FOUT_BPLL		5
+#define CLK_FOUT_KPLL		6
+#define CLK_FOUT_EPLL		7
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_PWM		155
+
+/* gate clocks */
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_UART3		260
+#define CLK_I2C0		261
+#define CLK_I2C1		262
+#define CLK_I2C2		263
+#define CLK_I2C3		264
+#define CLK_USI0		265
+#define CLK_USI1		266
+#define CLK_USI2		267
+#define CLK_USI3		268
+#define CLK_TSADC		270
+#define CLK_PWM			279
+#define CLK_MCT			315
+#define CLK_WDT			316
+#define CLK_RTC			317
+#define CLK_TMU			318
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
+#define CLK_PDMA0		362
+#define CLK_PDMA1		363
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
+#define CLK_SSS			471
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */

linux-7.2.3/include/dt-bindings/clock/exynos5420.h

@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * Device Tree binding constants for Exynos5420 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_DPLL		4
+#define CLK_FOUT_EPLL		5
+#define CLK_FOUT_RPLL		6
+#define CLK_FOUT_IPLL		7
+#define CLK_FOUT_SPLL		8
+#define CLK_FOUT_VPLL		9
+#define CLK_FOUT_MPLL		10
+#define CLK_FOUT_BPLL		11
+#define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
+#define CLK_SCLK_SPI0		135
+#define CLK_SCLK_SPI1		136
+#define CLK_SCLK_SPI2		137
+#define CLK_SCLK_I2S1		138
+#define CLK_SCLK_I2S2		139
+#define CLK_SCLK_PCM1		140
+#define CLK_SCLK_PCM2		141
+#define CLK_SCLK_SPDIF		142
+#define CLK_SCLK_HDMI		143
+#define CLK_SCLK_PIXEL		144
+#define CLK_SCLK_DP1		145
+#define CLK_SCLK_MIPI1		146
+#define CLK_SCLK_FIMD1		147
+#define CLK_SCLK_MAUDIO0	148
+#define CLK_SCLK_MAUPCM0	149
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_UNIPRO		154
+#define CLK_SCLK_PWM		155
+#define CLK_SCLK_GSCL_WA	156
+#define CLK_SCLK_GSCL_WB	157
+#define CLK_SCLK_HDMIPHY	158
+#define CLK_MAU_EPLL		159
+#define CLK_SCLK_HSIC_12M	160
+#define CLK_SCLK_MPHY_IXTAL24	161
+#define CLK_SCLK_BPLL		162
+
+/* gate clocks */
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_UART3		260
+#define CLK_I2C0		261
+#define CLK_I2C1		262
+#define CLK_I2C2		263
+#define CLK_I2C3		264
+#define CLK_USI0		265
+#define CLK_USI1		266
+#define CLK_USI2		267
+#define CLK_USI3		268
+#define CLK_I2C_HDMI		269
+#define CLK_TSADC		270
+#define CLK_SPI0		271
+#define CLK_SPI1		272
+#define CLK_SPI2		273
+#define CLK_KEYIF		274
+#define CLK_I2S1		275
+#define CLK_I2S2		276
+#define CLK_PCM1		277
+#define CLK_PCM2		278
+#define CLK_PWM			279
+#define CLK_SPDIF		280
+#define CLK_USI4		281
+#define CLK_USI5		282
+#define CLK_USI6		283
+#define CLK_ACLK66_PSGEN	300
+#define CLK_CHIPID		301
+#define CLK_SYSREG		302
+#define CLK_TZPC0		303
+#define CLK_TZPC1		304
+#define CLK_TZPC2		305
+#define CLK_TZPC3		306
+#define CLK_TZPC4		307
+#define CLK_TZPC5		308
+#define CLK_TZPC6		309
+#define CLK_TZPC7		310
+#define CLK_TZPC8		311
+#define CLK_TZPC9		312
+#define CLK_HDMI_CEC		313
+#define CLK_SECKEY		314
+#define CLK_MCT			315
+#define CLK_WDT			316
+#define CLK_RTC			317
+#define CLK_TMU			318
+#define CLK_TMU_GPU		319
+#define CLK_PCLK66_GPIO		330
+#define CLK_ACLK200_FSYS2	350
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
+#define CLK_SROMC		354
+#define CLK_UFS			355
+#define CLK_ACLK200_FSYS	360
+#define CLK_TSI			361
+#define CLK_PDMA0		362
+#define CLK_PDMA1		363
+#define CLK_RTIC		364
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
+#define CLK_ACLK400_MSCL	380
+#define CLK_MSCL0		381
+#define CLK_MSCL1		382
+#define CLK_MSCL2		383
+#define CLK_SMMU_MSCL0		384
+#define CLK_SMMU_MSCL1		385
+#define CLK_SMMU_MSCL2		386
+#define CLK_ACLK333		400
+#define CLK_MFC			401
+#define CLK_SMMU_MFCL		402
+#define CLK_SMMU_MFCR		403
+#define CLK_ACLK200_DISP1	410
+#define CLK_DSIM1		411
+#define CLK_DP1			412
+#define CLK_HDMI		413
+#define CLK_ACLK300_DISP1	420
+#define CLK_FIMD1		421
+#define CLK_SMMU_FIMD1M0	422
+#define CLK_SMMU_FIMD1M1	423
+#define CLK_ACLK166		430
+#define CLK_MIXER		431
+#define CLK_ACLK266		440
+#define CLK_ROTATOR		441
+#define CLK_MDMA1		442
+#define CLK_SMMU_ROTATOR	443
+#define CLK_SMMU_MDMA1		444
+#define CLK_ACLK300_JPEG	450
+#define CLK_JPEG		451
+#define CLK_JPEG2		452
+#define CLK_SMMU_JPEG		453
+#define CLK_SMMU_JPEG2		454
+#define CLK_ACLK300_GSCL	460
+#define CLK_SMMU_GSCL0		461
+#define CLK_SMMU_GSCL1		462
+#define CLK_GSCL_WA		463
+#define CLK_GSCL_WB		464
+#define CLK_GSCL0		465
+#define CLK_GSCL1		466
+#define CLK_FIMC_3AA		467
+#define CLK_ACLK266_G2D		470
+#define CLK_SSS			471
+#define CLK_SLIM_SSS		472
+#define CLK_MDMA0		473
+#define CLK_ACLK333_G2D		480
+#define CLK_G2D			481
+#define CLK_ACLK333_432_GSCL	490
+#define CLK_SMMU_3AA		491
+#define CLK_SMMU_FIMCL0		492
+#define CLK_SMMU_FIMCL1		493
+#define CLK_SMMU_FIMCL3		494
+#define CLK_FIMC_LITE3		495
+#define CLK_FIMC_LITE0		496
+#define CLK_FIMC_LITE1		497
+#define CLK_ACLK_G3D		500
+#define CLK_G3D			501
+#define CLK_SMMU_MIXER		502
+#define CLK_SMMU_G2D		503
+#define CLK_SMMU_MDMA0		504
+#define CLK_MC			505
+#define CLK_TOP_RTC		506
+#define CLK_SCLK_UART_ISP	510
+#define CLK_SCLK_SPI0_ISP	511
+#define CLK_SCLK_SPI1_ISP	512
+#define CLK_SCLK_PWM_ISP	513
+#define CLK_SCLK_ISP_SENSOR0	514
+#define CLK_SCLK_ISP_SENSOR1	515
+#define CLK_SCLK_ISP_SENSOR2	516
+#define CLK_ACLK432_SCALER	517
+#define CLK_ACLK432_CAM		518
+#define CLK_ACLK_FL1550_CAM	519
+#define CLK_ACLK550_CAM		520
+#define CLK_CLKM_PHY0		521
+#define CLK_CLKM_PHY1		522
+#define CLK_ACLK_PPMU_DREX0_0	523
+#define CLK_ACLK_PPMU_DREX0_1	524
+#define CLK_ACLK_PPMU_DREX1_0	525
+#define CLK_ACLK_PPMU_DREX1_1	526
+#define CLK_PCLK_PPMU_DREX0_0	527
+#define CLK_PCLK_PPMU_DREX0_1	528
+#define CLK_PCLK_PPMU_DREX1_0	529
+#define CLK_PCLK_PPMU_DREX1_1	530
+
+/* mux clocks */
+#define CLK_MOUT_HDMI		640
+#define CLK_MOUT_G3D		641
+#define CLK_MOUT_VPLL		642
+#define CLK_MOUT_MAUDIO0	643
+#define CLK_MOUT_USER_ACLK333	644
+#define CLK_MOUT_SW_ACLK333	645
+#define CLK_MOUT_USER_ACLK200_DISP1	646
+#define CLK_MOUT_SW_ACLK200	647
+#define CLK_MOUT_USER_ACLK300_DISP1     648
+#define CLK_MOUT_SW_ACLK300     649
+#define CLK_MOUT_USER_ACLK400_DISP1     650
+#define CLK_MOUT_SW_ACLK400     651
+#define CLK_MOUT_USER_ACLK300_GSCL	652
+#define CLK_MOUT_SW_ACLK300_GSCL	653
+#define CLK_MOUT_MCLK_CDREX	654
+#define CLK_MOUT_BPLL		655
+#define CLK_MOUT_MX_MSPLL_CCORE	656
+#define CLK_MOUT_EPLL		657
+#define CLK_MOUT_MAU_EPLL	658
+#define CLK_MOUT_USER_MAU_EPLL	659
+#define CLK_MOUT_SCLK_SPLL	660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
+#define CLK_MOUT_SW_ACLK_G3D	662
+#define CLK_MOUT_APLL		663
+#define CLK_MOUT_MSPLL_CPU	664
+#define CLK_MOUT_KPLL		665
+#define CLK_MOUT_MSPLL_KFC	666
+
+
+/* divider clocks */
+#define CLK_DOUT_PIXEL		768
+#define CLK_DOUT_ACLK400_WCORE	769
+#define CLK_DOUT_ACLK400_ISP	770
+#define CLK_DOUT_ACLK400_MSCL	771
+#define CLK_DOUT_ACLK200	772
+#define CLK_DOUT_ACLK200_FSYS2	773
+#define CLK_DOUT_ACLK100_NOC	774
+#define CLK_DOUT_PCLK200_FSYS	775
+#define CLK_DOUT_ACLK200_FSYS	776
+#define CLK_DOUT_ACLK333_432_GSCL	777
+#define CLK_DOUT_ACLK333_432_ISP	778
+#define CLK_DOUT_ACLK66		779
+#define CLK_DOUT_ACLK333_432_ISP0	780
+#define CLK_DOUT_ACLK266	781
+#define CLK_DOUT_ACLK166	782
+#define CLK_DOUT_ACLK333	783
+#define CLK_DOUT_ACLK333_G2D	784
+#define CLK_DOUT_ACLK266_G2D	785
+#define CLK_DOUT_ACLK_G3D	786
+#define CLK_DOUT_ACLK300_JPEG	787
+#define CLK_DOUT_ACLK300_DISP1	788
+#define CLK_DOUT_ACLK300_GSCL	789
+#define CLK_DOUT_ACLK400_DISP1	790
+#define CLK_DOUT_PCLK_CDREX	791
+#define CLK_DOUT_SCLK_CDREX	792
+#define CLK_DOUT_ACLK_CDREX1	793
+#define CLK_DOUT_CCLK_DREX0	794
+#define CLK_DOUT_CLK2X_PHY0	795
+#define CLK_DOUT_PCLK_CORE_MEM	796
+#define CLK_FF_DOUT_SPLL2	797
+#define CLK_DOUT_PCLK_DREX0	798
+#define CLK_DOUT_PCLK_DREX1	799
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */

linux-7.2.3/include/dt-bindings/clock/exynos7-clk.h

@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define DOUT_SCLK_AUD_PLL		9
+#define FOUT_AUD_PLL			10
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define ACLK_CCORE_133			20
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define CLK_SCLK_SPI0			7
+#define CLK_SCLK_SPI1			8
+#define CLK_SCLK_SPI2			9
+#define CLK_SCLK_SPI3			10
+#define CLK_SCLK_SPI4			11
+#define CLK_SCLK_SPDIF			12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_ACLK_PERIC0_66		15
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define CLK_ACLK_FSYS0_200		9
+#define CLK_ACLK_FSYS1_200		10
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PCLK_SPI0			12
+#define PCLK_SPI1			13
+#define PCLK_SPI2			14
+#define PCLK_SPI3			15
+#define PCLK_SPI4			16
+#define SCLK_SPI0			17
+#define SCLK_SPI1			18
+#define SCLK_SPI2			19
+#define SCLK_SPI3			20
+#define SCLK_SPI4			21
+#define PCLK_I2S1			22
+#define PCLK_PCM1			23
+#define PCLK_SPDIF			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			26
+#define SCLK_SPDIF			27
+#define PERIC1_NR_CLK			28
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
+/* AUD */
+#define SCLK_I2S			1
+#define SCLK_PCM			2
+#define PCLK_I2S			3
+#define PCLK_PCM			4
+#define ACLK_ADMA			5
+#define AUD_NR_CLK			6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */

linux-7.2.3/include/dt-bindings/clock/exynos7885.h

@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 Dávid Virág
+ *
+ * Device Tree binding constants for Exynos7885 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_DOUT_SHARED0_DIV2		3
+#define CLK_DOUT_SHARED0_DIV3		4
+#define CLK_DOUT_SHARED0_DIV4		5
+#define CLK_DOUT_SHARED0_DIV5		6
+#define CLK_DOUT_SHARED1_DIV2		7
+#define CLK_DOUT_SHARED1_DIV3		8
+#define CLK_DOUT_SHARED1_DIV4		9
+#define CLK_MOUT_CORE_BUS		10
+#define CLK_MOUT_CORE_CCI		11
+#define CLK_MOUT_CORE_G3D		12
+#define CLK_DOUT_CORE_BUS		13
+#define CLK_DOUT_CORE_CCI		14
+#define CLK_DOUT_CORE_G3D		15
+#define CLK_GOUT_CORE_BUS		16
+#define CLK_GOUT_CORE_CCI		17
+#define CLK_GOUT_CORE_G3D		18
+#define CLK_MOUT_PERI_BUS		19
+#define CLK_MOUT_PERI_SPI0		20
+#define CLK_MOUT_PERI_SPI1		21
+#define CLK_MOUT_PERI_UART0		22
+#define CLK_MOUT_PERI_UART1		23
+#define CLK_MOUT_PERI_UART2		24
+#define CLK_MOUT_PERI_USI0		25
+#define CLK_MOUT_PERI_USI1		26
+#define CLK_MOUT_PERI_USI2		27
+#define CLK_DOUT_PERI_BUS		28
+#define CLK_DOUT_PERI_SPI0		29
+#define CLK_DOUT_PERI_SPI1		30
+#define CLK_DOUT_PERI_UART0		31
+#define CLK_DOUT_PERI_UART1		32
+#define CLK_DOUT_PERI_UART2		33
+#define CLK_DOUT_PERI_USI0		34
+#define CLK_DOUT_PERI_USI1		35
+#define CLK_DOUT_PERI_USI2		36
+#define CLK_GOUT_PERI_BUS		37
+#define CLK_GOUT_PERI_SPI0		38
+#define CLK_GOUT_PERI_SPI1		39
+#define CLK_GOUT_PERI_UART0		40
+#define CLK_GOUT_PERI_UART1		41
+#define CLK_GOUT_PERI_UART2		42
+#define CLK_GOUT_PERI_USI0		43
+#define CLK_GOUT_PERI_USI1		44
+#define CLK_GOUT_PERI_USI2		45
+#define CLK_MOUT_FSYS_BUS		46
+#define CLK_MOUT_FSYS_MMC_CARD		47
+#define CLK_MOUT_FSYS_MMC_EMBD		48
+#define CLK_MOUT_FSYS_MMC_SDIO		49
+#define CLK_MOUT_FSYS_USB30DRD		50
+#define CLK_DOUT_FSYS_BUS		51
+#define CLK_DOUT_FSYS_MMC_CARD		52
+#define CLK_DOUT_FSYS_MMC_EMBD		53
+#define CLK_DOUT_FSYS_MMC_SDIO		54
+#define CLK_DOUT_FSYS_USB30DRD		55
+#define CLK_GOUT_FSYS_BUS		56
+#define CLK_GOUT_FSYS_MMC_CARD		57
+#define CLK_GOUT_FSYS_MMC_EMBD		58
+#define CLK_GOUT_FSYS_MMC_SDIO		59
+#define CLK_GOUT_FSYS_USB30DRD		60
+#define CLK_MOUT_SHARED0_PLL		61
+#define CLK_MOUT_SHARED1_PLL		62
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_BUS_USER			1
+#define CLK_MOUT_CORE_CCI_USER			2
+#define CLK_MOUT_CORE_G3D_USER			3
+#define CLK_MOUT_CORE_GIC			4
+#define CLK_DOUT_CORE_BUSP			5
+#define CLK_GOUT_CCI_ACLK			6
+#define CLK_GOUT_GIC400_CLK			7
+#define CLK_GOUT_TREX_D_CORE_ACLK		8
+#define CLK_GOUT_TREX_D_CORE_GCLK		9
+#define CLK_GOUT_TREX_D_CORE_PCLK		10
+#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE	11
+#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12
+#define CLK_GOUT_TREX_P_CORE_PCLK		13
+#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_BUS_USER		1
+#define CLK_MOUT_PERI_SPI0_USER		2
+#define CLK_MOUT_PERI_SPI1_USER		3
+#define CLK_MOUT_PERI_UART0_USER	4
+#define CLK_MOUT_PERI_UART1_USER	5
+#define CLK_MOUT_PERI_UART2_USER	6
+#define CLK_MOUT_PERI_USI0_USER		7
+#define CLK_MOUT_PERI_USI1_USER		8
+#define CLK_MOUT_PERI_USI2_USER		9
+#define CLK_GOUT_GPIO_TOP_PCLK		10
+#define CLK_GOUT_HSI2C0_PCLK		11
+#define CLK_GOUT_HSI2C1_PCLK		12
+#define CLK_GOUT_HSI2C2_PCLK		13
+#define CLK_GOUT_HSI2C3_PCLK		14
+#define CLK_GOUT_I2C0_PCLK		15
+#define CLK_GOUT_I2C1_PCLK		16
+#define CLK_GOUT_I2C2_PCLK		17
+#define CLK_GOUT_I2C3_PCLK		18
+#define CLK_GOUT_I2C4_PCLK		19
+#define CLK_GOUT_I2C5_PCLK		20
+#define CLK_GOUT_I2C6_PCLK		21
+#define CLK_GOUT_I2C7_PCLK		22
+#define CLK_GOUT_PWM_MOTOR_PCLK		23
+#define CLK_GOUT_SPI0_PCLK		24
+#define CLK_GOUT_SPI0_EXT_CLK		25
+#define CLK_GOUT_SPI1_PCLK		26
+#define CLK_GOUT_SPI1_EXT_CLK		27
+#define CLK_GOUT_UART0_EXT_UCLK		28
+#define CLK_GOUT_UART0_PCLK		29
+#define CLK_GOUT_UART1_EXT_UCLK		30
+#define CLK_GOUT_UART1_PCLK		31
+#define CLK_GOUT_UART2_EXT_UCLK		32
+#define CLK_GOUT_UART2_PCLK		33
+#define CLK_GOUT_USI0_PCLK		34
+#define CLK_GOUT_USI0_SCLK		35
+#define CLK_GOUT_USI1_PCLK		36
+#define CLK_GOUT_USI1_SCLK		37
+#define CLK_GOUT_USI2_PCLK		38
+#define CLK_GOUT_USI2_SCLK		39
+#define CLK_GOUT_MCT_PCLK		40
+#define CLK_GOUT_SYSREG_PERI_PCLK	41
+#define CLK_GOUT_WDT0_PCLK		42
+#define CLK_GOUT_WDT1_PCLK		43
+
+/* CMU_FSYS */
+#define CLK_MOUT_FSYS_BUS_USER			1
+#define CLK_MOUT_FSYS_MMC_CARD_USER		2
+#define CLK_MOUT_FSYS_MMC_EMBD_USER		3
+#define CLK_MOUT_FSYS_MMC_SDIO_USER		4
+#define CLK_GOUT_MMC_CARD_ACLK			5
+#define CLK_GOUT_MMC_CARD_SDCLKIN		6
+#define CLK_GOUT_MMC_EMBD_ACLK			7
+#define CLK_GOUT_MMC_EMBD_SDCLKIN		8
+#define CLK_GOUT_MMC_SDIO_ACLK			9
+#define CLK_GOUT_MMC_SDIO_SDCLKIN		10
+#define CLK_MOUT_FSYS_USB30DRD_USER		11
+#define CLK_MOUT_USB_PLL			12
+#define CLK_FOUT_USB_PLL			13
+#define CLK_FSYS_USB20PHY_CLKCORE		14
+#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL	15
+#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0	16
+#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1	17
+#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY		18
+#define CLK_FSYS_USB30DRD_REF_CLK		19
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */

linux-7.2.3/include/dt-bindings/clock/exynos850.h

@@ -0,0 +1,395 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Device Tree binding constants for Exynos850 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_MMC_PLL		3
+#define CLK_MOUT_SHARED0_PLL		4
+#define CLK_MOUT_SHARED1_PLL		5
+#define CLK_MOUT_MMC_PLL		6
+#define CLK_MOUT_CORE_BUS		7
+#define CLK_MOUT_CORE_CCI		8
+#define CLK_MOUT_CORE_MMC_EMBD		9
+#define CLK_MOUT_CORE_SSS		10
+#define CLK_MOUT_DPU			11
+#define CLK_MOUT_HSI_BUS		12
+#define CLK_MOUT_HSI_MMC_CARD		13
+#define CLK_MOUT_HSI_USB20DRD		14
+#define CLK_MOUT_PERI_BUS		15
+#define CLK_MOUT_PERI_UART		16
+#define CLK_MOUT_PERI_IP		17
+#define CLK_DOUT_SHARED0_DIV3		18
+#define CLK_DOUT_SHARED0_DIV2		19
+#define CLK_DOUT_SHARED1_DIV3		20
+#define CLK_DOUT_SHARED1_DIV2		21
+#define CLK_DOUT_SHARED0_DIV4		22
+#define CLK_DOUT_SHARED1_DIV4		23
+#define CLK_DOUT_CORE_BUS		24
+#define CLK_DOUT_CORE_CCI		25
+#define CLK_DOUT_CORE_MMC_EMBD		26
+#define CLK_DOUT_CORE_SSS		27
+#define CLK_DOUT_DPU			28
+#define CLK_DOUT_HSI_BUS		29
+#define CLK_DOUT_HSI_MMC_CARD		30
+#define CLK_DOUT_HSI_USB20DRD		31
+#define CLK_DOUT_PERI_BUS		32
+#define CLK_DOUT_PERI_UART		33
+#define CLK_DOUT_PERI_IP		34
+#define CLK_GOUT_CORE_BUS		35
+#define CLK_GOUT_CORE_CCI		36
+#define CLK_GOUT_CORE_MMC_EMBD		37
+#define CLK_GOUT_CORE_SSS		38
+#define CLK_GOUT_DPU			39
+#define CLK_GOUT_HSI_BUS		40
+#define CLK_GOUT_HSI_MMC_CARD		41
+#define CLK_GOUT_HSI_USB20DRD		42
+#define CLK_GOUT_PERI_BUS		43
+#define CLK_GOUT_PERI_UART		44
+#define CLK_GOUT_PERI_IP		45
+#define CLK_MOUT_CLKCMU_APM_BUS		46
+#define CLK_DOUT_CLKCMU_APM_BUS		47
+#define CLK_GOUT_CLKCMU_APM_BUS		48
+#define CLK_MOUT_AUD			49
+#define CLK_GOUT_AUD			50
+#define CLK_DOUT_AUD			51
+#define CLK_MOUT_IS_BUS			52
+#define CLK_MOUT_IS_ITP			53
+#define CLK_MOUT_IS_VRA			54
+#define CLK_MOUT_IS_GDC			55
+#define CLK_GOUT_IS_BUS			56
+#define CLK_GOUT_IS_ITP			57
+#define CLK_GOUT_IS_VRA			58
+#define CLK_GOUT_IS_GDC			59
+#define CLK_DOUT_IS_BUS			60
+#define CLK_DOUT_IS_ITP			61
+#define CLK_DOUT_IS_VRA			62
+#define CLK_DOUT_IS_GDC			63
+#define CLK_MOUT_MFCMSCL_MFC		64
+#define CLK_MOUT_MFCMSCL_M2M		65
+#define CLK_MOUT_MFCMSCL_MCSC		66
+#define CLK_MOUT_MFCMSCL_JPEG		67
+#define CLK_GOUT_MFCMSCL_MFC		68
+#define CLK_GOUT_MFCMSCL_M2M		69
+#define CLK_GOUT_MFCMSCL_MCSC		70
+#define CLK_GOUT_MFCMSCL_JPEG		71
+#define CLK_DOUT_MFCMSCL_MFC		72
+#define CLK_DOUT_MFCMSCL_M2M		73
+#define CLK_DOUT_MFCMSCL_MCSC		74
+#define CLK_DOUT_MFCMSCL_JPEG		75
+#define CLK_MOUT_G3D_SWITCH		76
+#define CLK_GOUT_G3D_SWITCH		77
+#define CLK_DOUT_G3D_SWITCH		78
+#define CLK_MOUT_CPUCL0_DBG		79
+#define CLK_MOUT_CPUCL0_SWITCH		80
+#define CLK_GOUT_CPUCL0_DBG		81
+#define CLK_GOUT_CPUCL0_SWITCH		82
+#define CLK_DOUT_CPUCL0_DBG		83
+#define CLK_DOUT_CPUCL0_SWITCH		84
+#define CLK_MOUT_CPUCL1_DBG		85
+#define CLK_MOUT_CPUCL1_SWITCH		86
+#define CLK_GOUT_CPUCL1_DBG		87
+#define CLK_GOUT_CPUCL1_SWITCH		88
+#define CLK_DOUT_CPUCL1_DBG		89
+#define CLK_DOUT_CPUCL1_SWITCH		90
+
+/* CMU_APM */
+#define CLK_RCO_I3C_PMIC		1
+#define OSCCLK_RCO_APM			2
+#define CLK_RCO_APM__ALV		3
+#define CLK_DLL_DCO			4
+#define CLK_MOUT_APM_BUS_USER		5
+#define CLK_MOUT_RCO_APM_I3C_USER	6
+#define CLK_MOUT_RCO_APM_USER		7
+#define CLK_MOUT_DLL_USER		8
+#define CLK_MOUT_CLKCMU_CHUB_BUS	9
+#define CLK_MOUT_APM_BUS		10
+#define CLK_MOUT_APM_I3C		11
+#define CLK_DOUT_CLKCMU_CHUB_BUS	12
+#define CLK_DOUT_APM_BUS		13
+#define CLK_DOUT_APM_I3C		14
+#define CLK_GOUT_CLKCMU_CMGP_BUS	15
+#define CLK_GOUT_CLKCMU_CHUB_BUS	16
+#define CLK_GOUT_RTC_PCLK		17
+#define CLK_GOUT_TOP_RTC_PCLK		18
+#define CLK_GOUT_I3C_PCLK		19
+#define CLK_GOUT_I3C_SCLK		20
+#define CLK_GOUT_SPEEDY_PCLK		21
+#define CLK_GOUT_GPIO_ALIVE_PCLK	22
+#define CLK_GOUT_PMU_ALIVE_PCLK		23
+#define CLK_GOUT_SYSREG_APM_PCLK	24
+#define CLK_GOUT_MAILBOX_APM_AP_PCLK	25
+
+/* CMU_AUD */
+#define CLK_DOUT_AUD_AUDIF		1
+#define CLK_DOUT_AUD_BUSD		2
+#define CLK_DOUT_AUD_BUSP		3
+#define CLK_DOUT_AUD_CNT		4
+#define CLK_DOUT_AUD_CPU		5
+#define CLK_DOUT_AUD_CPU_ACLK		6
+#define CLK_DOUT_AUD_CPU_PCLKDBG	7
+#define CLK_DOUT_AUD_FM			8
+#define CLK_DOUT_AUD_FM_SPDY		9
+#define CLK_DOUT_AUD_MCLK		10
+#define CLK_DOUT_AUD_UAIF0		11
+#define CLK_DOUT_AUD_UAIF1		12
+#define CLK_DOUT_AUD_UAIF2		13
+#define CLK_DOUT_AUD_UAIF3		14
+#define CLK_DOUT_AUD_UAIF4		15
+#define CLK_DOUT_AUD_UAIF5		16
+#define CLK_DOUT_AUD_UAIF6		17
+#define CLK_FOUT_AUD_PLL		18
+#define CLK_GOUT_AUD_ABOX_ACLK		19
+#define CLK_GOUT_AUD_ASB_CCLK		20
+#define CLK_GOUT_AUD_CA32_CCLK		21
+#define CLK_GOUT_AUD_CNT_BCLK		22
+#define CLK_GOUT_AUD_CODEC_MCLK		23
+#define CLK_GOUT_AUD_DAP_CCLK		24
+#define CLK_GOUT_AUD_GPIO_PCLK		25
+#define CLK_GOUT_AUD_PPMU_ACLK		26
+#define CLK_GOUT_AUD_PPMU_PCLK		27
+#define CLK_GOUT_AUD_SPDY_BCLK		28
+#define CLK_GOUT_AUD_SYSMMU_CLK		29
+#define CLK_GOUT_AUD_SYSREG_PCLK	30
+#define CLK_GOUT_AUD_TZPC_PCLK		31
+#define CLK_GOUT_AUD_UAIF0_BCLK		32
+#define CLK_GOUT_AUD_UAIF1_BCLK		33
+#define CLK_GOUT_AUD_UAIF2_BCLK		34
+#define CLK_GOUT_AUD_UAIF3_BCLK		35
+#define CLK_GOUT_AUD_UAIF4_BCLK		36
+#define CLK_GOUT_AUD_UAIF5_BCLK		37
+#define CLK_GOUT_AUD_UAIF6_BCLK		38
+#define CLK_GOUT_AUD_WDT_PCLK		39
+#define CLK_MOUT_AUD_CPU		40
+#define CLK_MOUT_AUD_CPU_HCH		41
+#define CLK_MOUT_AUD_CPU_USER		42
+#define CLK_MOUT_AUD_FM			43
+#define CLK_MOUT_AUD_PLL		44
+#define CLK_MOUT_AUD_TICK_USB_USER	45
+#define CLK_MOUT_AUD_UAIF0		46
+#define CLK_MOUT_AUD_UAIF1		47
+#define CLK_MOUT_AUD_UAIF2		48
+#define CLK_MOUT_AUD_UAIF3		49
+#define CLK_MOUT_AUD_UAIF4		50
+#define CLK_MOUT_AUD_UAIF5		51
+#define CLK_MOUT_AUD_UAIF6		52
+#define IOCLK_AUDIOCDCLK0		53
+#define IOCLK_AUDIOCDCLK1		54
+#define IOCLK_AUDIOCDCLK2		55
+#define IOCLK_AUDIOCDCLK3		56
+#define IOCLK_AUDIOCDCLK4		57
+#define IOCLK_AUDIOCDCLK5		58
+#define IOCLK_AUDIOCDCLK6		59
+#define TICK_USB			60
+#define CLK_GOUT_AUD_CMU_AUD_PCLK	61
+
+/* CMU_CMGP */
+#define CLK_RCO_CMGP			1
+#define CLK_MOUT_CMGP_ADC		2
+#define CLK_MOUT_CMGP_USI0		3
+#define CLK_MOUT_CMGP_USI1		4
+#define CLK_DOUT_CMGP_ADC		5
+#define CLK_DOUT_CMGP_USI0		6
+#define CLK_DOUT_CMGP_USI1		7
+#define CLK_GOUT_CMGP_ADC_S0_PCLK	8
+#define CLK_GOUT_CMGP_ADC_S1_PCLK	9
+#define CLK_GOUT_CMGP_GPIO_PCLK		10
+#define CLK_GOUT_CMGP_USI0_IPCLK	11
+#define CLK_GOUT_CMGP_USI0_PCLK		12
+#define CLK_GOUT_CMGP_USI1_IPCLK	13
+#define CLK_GOUT_CMGP_USI1_PCLK		14
+#define CLK_GOUT_SYSREG_CMGP_PCLK	15
+
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL		1
+#define CLK_MOUT_PLL_CPUCL0		2
+#define CLK_MOUT_CPUCL0_SWITCH_USER	3
+#define CLK_MOUT_CPUCL0_DBG_USER	4
+#define CLK_MOUT_CPUCL0_PLL		5
+#define CLK_DOUT_CPUCL0_CPU		6
+#define CLK_DOUT_CPUCL0_CMUREF		7
+#define CLK_DOUT_CPUCL0_PCLK		8
+#define CLK_DOUT_CLUSTER0_ACLK		9
+#define CLK_DOUT_CLUSTER0_ATCLK		10
+#define CLK_DOUT_CLUSTER0_PCLKDBG	11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK	12
+#define CLK_GOUT_CLUSTER0_ATCLK		13
+#define CLK_GOUT_CLUSTER0_PCLK		14
+#define CLK_GOUT_CLUSTER0_PERIPHCLK	15
+#define CLK_GOUT_CLUSTER0_SCLK		16
+#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK	17
+#define CLK_GOUT_CLUSTER0_CPU		18
+#define CLK_CLUSTER0_SCLK		19
+
+/* CMU_CPUCL1 */
+#define CLK_FOUT_CPUCL1_PLL		1
+#define CLK_MOUT_PLL_CPUCL1		2
+#define CLK_MOUT_CPUCL1_SWITCH_USER	3
+#define CLK_MOUT_CPUCL1_DBG_USER	4
+#define CLK_MOUT_CPUCL1_PLL		5
+#define CLK_DOUT_CPUCL1_CPU		6
+#define CLK_DOUT_CPUCL1_CMUREF		7
+#define CLK_DOUT_CPUCL1_PCLK		8
+#define CLK_DOUT_CLUSTER1_ACLK		9
+#define CLK_DOUT_CLUSTER1_ATCLK		10
+#define CLK_DOUT_CLUSTER1_PCLKDBG	11
+#define CLK_DOUT_CLUSTER1_PERIPHCLK	12
+#define CLK_GOUT_CLUSTER1_ATCLK		13
+#define CLK_GOUT_CLUSTER1_PCLK		14
+#define CLK_GOUT_CLUSTER1_PERIPHCLK	15
+#define CLK_GOUT_CLUSTER1_SCLK		16
+#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK	17
+#define CLK_GOUT_CLUSTER1_CPU		18
+#define CLK_CLUSTER1_SCLK		19
+
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL		1
+#define CLK_MOUT_G3D_PLL		2
+#define CLK_MOUT_G3D_SWITCH_USER	3
+#define CLK_MOUT_G3D_BUSD		4
+#define CLK_DOUT_G3D_BUSP		5
+#define CLK_GOUT_G3D_CMU_G3D_PCLK	6
+#define CLK_GOUT_G3D_GPU_CLK		7
+#define CLK_GOUT_G3D_TZPC_PCLK		8
+#define CLK_GOUT_G3D_GRAY2BIN_CLK	9
+#define CLK_GOUT_G3D_BUSD_CLK		10
+#define CLK_GOUT_G3D_BUSP_CLK		11
+#define CLK_GOUT_G3D_SYSREG_PCLK	12
+
+/* CMU_HSI */
+#define CLK_MOUT_HSI_BUS_USER		1
+#define CLK_MOUT_HSI_MMC_CARD_USER	2
+#define CLK_MOUT_HSI_USB20DRD_USER	3
+#define CLK_MOUT_HSI_RTC		4
+#define CLK_GOUT_USB_RTC_CLK		5
+#define CLK_GOUT_USB_REF_CLK		6
+#define CLK_GOUT_USB_PHY_REF_CLK	7
+#define CLK_GOUT_USB_PHY_ACLK		8
+#define CLK_GOUT_USB_BUS_EARLY_CLK	9
+#define CLK_GOUT_GPIO_HSI_PCLK		10
+#define CLK_GOUT_MMC_CARD_ACLK		11
+#define CLK_GOUT_MMC_CARD_SDCLKIN	12
+#define CLK_GOUT_SYSREG_HSI_PCLK	13
+#define CLK_GOUT_HSI_PPMU_ACLK		14
+#define CLK_GOUT_HSI_PPMU_PCLK		15
+#define CLK_GOUT_HSI_CMU_HSI_PCLK	16
+
+/* CMU_IS */
+#define CLK_MOUT_IS_BUS_USER		1
+#define CLK_MOUT_IS_ITP_USER		2
+#define CLK_MOUT_IS_VRA_USER		3
+#define CLK_MOUT_IS_GDC_USER		4
+#define CLK_DOUT_IS_BUSP		5
+#define CLK_GOUT_IS_CMU_IS_PCLK		6
+#define CLK_GOUT_IS_CSIS0_ACLK		7
+#define CLK_GOUT_IS_CSIS1_ACLK		8
+#define CLK_GOUT_IS_CSIS2_ACLK		9
+#define CLK_GOUT_IS_TZPC_PCLK		10
+#define CLK_GOUT_IS_CSIS_DMA_CLK	11
+#define CLK_GOUT_IS_GDC_CLK		12
+#define CLK_GOUT_IS_IPP_CLK		13
+#define CLK_GOUT_IS_ITP_CLK		14
+#define CLK_GOUT_IS_MCSC_CLK		15
+#define CLK_GOUT_IS_VRA_CLK		16
+#define CLK_GOUT_IS_PPMU_IS0_ACLK	17
+#define CLK_GOUT_IS_PPMU_IS0_PCLK	18
+#define CLK_GOUT_IS_PPMU_IS1_ACLK	19
+#define CLK_GOUT_IS_PPMU_IS1_PCLK	20
+#define CLK_GOUT_IS_SYSMMU_IS0_CLK	21
+#define CLK_GOUT_IS_SYSMMU_IS1_CLK	22
+#define CLK_GOUT_IS_SYSREG_PCLK		23
+
+/* CMU_MFCMSCL */
+#define CLK_MOUT_MFCMSCL_MFC_USER		1
+#define CLK_MOUT_MFCMSCL_M2M_USER		2
+#define CLK_MOUT_MFCMSCL_MCSC_USER		3
+#define CLK_MOUT_MFCMSCL_JPEG_USER		4
+#define CLK_DOUT_MFCMSCL_BUSP			5
+#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK	6
+#define CLK_GOUT_MFCMSCL_TZPC_PCLK		7
+#define CLK_GOUT_MFCMSCL_JPEG_ACLK		8
+#define CLK_GOUT_MFCMSCL_M2M_ACLK		9
+#define CLK_GOUT_MFCMSCL_MCSC_CLK		10
+#define CLK_GOUT_MFCMSCL_MFC_ACLK		11
+#define CLK_GOUT_MFCMSCL_PPMU_ACLK		12
+#define CLK_GOUT_MFCMSCL_PPMU_PCLK		13
+#define CLK_GOUT_MFCMSCL_SYSMMU_CLK		14
+#define CLK_GOUT_MFCMSCL_SYSREG_PCLK		15
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_BUS_USER		1
+#define CLK_MOUT_PERI_UART_USER		2
+#define CLK_MOUT_PERI_HSI2C_USER	3
+#define CLK_MOUT_PERI_SPI_USER		4
+#define CLK_DOUT_PERI_HSI2C0		5
+#define CLK_DOUT_PERI_HSI2C1		6
+#define CLK_DOUT_PERI_HSI2C2		7
+#define CLK_DOUT_PERI_SPI0		8
+#define CLK_GOUT_PERI_HSI2C0		9
+#define CLK_GOUT_PERI_HSI2C1		10
+#define CLK_GOUT_PERI_HSI2C2		11
+#define CLK_GOUT_GPIO_PERI_PCLK		12
+#define CLK_GOUT_HSI2C0_IPCLK		13
+#define CLK_GOUT_HSI2C0_PCLK		14
+#define CLK_GOUT_HSI2C1_IPCLK		15
+#define CLK_GOUT_HSI2C1_PCLK		16
+#define CLK_GOUT_HSI2C2_IPCLK		17
+#define CLK_GOUT_HSI2C2_PCLK		18
+#define CLK_GOUT_I2C0_PCLK		19
+#define CLK_GOUT_I2C1_PCLK		20
+#define CLK_GOUT_I2C2_PCLK		21
+#define CLK_GOUT_I2C3_PCLK		22
+#define CLK_GOUT_I2C4_PCLK		23
+#define CLK_GOUT_I2C5_PCLK		24
+#define CLK_GOUT_I2C6_PCLK		25
+#define CLK_GOUT_MCT_PCLK		26
+#define CLK_GOUT_PWM_MOTOR_PCLK		27
+#define CLK_GOUT_SPI0_IPCLK		28
+#define CLK_GOUT_SPI0_PCLK		29
+#define CLK_GOUT_SYSREG_PERI_PCLK	30
+#define CLK_GOUT_UART_IPCLK		31
+#define CLK_GOUT_UART_PCLK		32
+#define CLK_GOUT_WDT0_PCLK		33
+#define CLK_GOUT_WDT1_PCLK		34
+#define CLK_GOUT_BUSIF_TMU_PCLK		35
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_BUS_USER		1
+#define CLK_MOUT_CORE_CCI_USER		2
+#define CLK_MOUT_CORE_MMC_EMBD_USER	3
+#define CLK_MOUT_CORE_SSS_USER		4
+#define CLK_MOUT_CORE_GIC		5
+#define CLK_DOUT_CORE_BUSP		6
+#define CLK_GOUT_CCI_ACLK		7
+#define CLK_GOUT_GIC_CLK		8
+#define CLK_GOUT_MMC_EMBD_ACLK		9
+#define CLK_GOUT_MMC_EMBD_SDCLKIN	10
+#define CLK_GOUT_SSS_ACLK		11
+#define CLK_GOUT_SSS_PCLK		12
+#define CLK_GOUT_GPIO_CORE_PCLK		13
+#define CLK_GOUT_SYSREG_CORE_PCLK	14
+#define CLK_GOUT_PDMA_CORE_ACLK		15
+#define CLK_GOUT_SPDMA_CORE_ACLK	16
+
+/* CMU_DPU */
+#define CLK_MOUT_DPU_USER		1
+#define CLK_DOUT_DPU_BUSP		2
+#define CLK_GOUT_DPU_CMU_DPU_PCLK	3
+#define CLK_GOUT_DPU_DECON0_ACLK	4
+#define CLK_GOUT_DPU_DMA_ACLK		5
+#define CLK_GOUT_DPU_DPP_ACLK		6
+#define CLK_GOUT_DPU_PPMU_ACLK		7
+#define CLK_GOUT_DPU_PPMU_PCLK		8
+#define CLK_GOUT_DPU_SMMU_CLK		9
+#define CLK_GOUT_DPU_SYSREG_PCLK	10
+#define DPU_NR_CLK			11
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */

linux-7.2.3/include/dt-bindings/clock/fsd-clk.h

@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ *             https://www.tesla.com
+ *
+ * The constants defined in this header are being used in dts
+ * and fsd platform driver.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_FSD_H
+#define _DT_BINDINGS_CLOCK_FSD_H
+
+/* CMU */
+#define DOUT_CMU_PLL_SHARED0_DIV4		1
+#define DOUT_CMU_PERIC_SHARED1DIV36		2
+#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK	3
+#define DOUT_CMU_PERIC_SHARED0DIV20		4
+#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK	5
+#define DOUT_CMU_PLL_SHARED0_DIV6		6
+#define DOUT_CMU_FSYS0_SHARED1DIV4		7
+#define DOUT_CMU_FSYS0_SHARED0DIV4		8
+#define DOUT_CMU_FSYS1_SHARED0DIV8		9
+#define DOUT_CMU_FSYS1_SHARED0DIV4		10
+#define CMU_CPUCL_SWITCH_GATE			11
+#define DOUT_CMU_IMEM_TCUCLK			12
+#define DOUT_CMU_IMEM_ACLK			13
+#define DOUT_CMU_IMEM_DMACLK			14
+#define GAT_CMU_FSYS0_SHARED0DIV4		15
+
+/* PERIC */
+#define PERIC_SCLK_UART0			1
+#define PERIC_PCLK_UART0			2
+#define PERIC_SCLK_UART1			3
+#define PERIC_PCLK_UART1			4
+#define PERIC_DMA0_IPCLKPORT_ACLK		5
+#define PERIC_DMA1_IPCLKPORT_ACLK		6
+#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0		7
+#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0		8
+#define PERIC_PCLK_SPI0                         9
+#define PERIC_SCLK_SPI0                         10
+#define PERIC_PCLK_SPI1                         11
+#define PERIC_SCLK_SPI1                         12
+#define PERIC_PCLK_SPI2                         13
+#define PERIC_SCLK_SPI2                         14
+#define PERIC_PCLK_TDM0                         15
+#define PERIC_PCLK_HSI2C0			16
+#define PERIC_PCLK_HSI2C1			17
+#define PERIC_PCLK_HSI2C2			18
+#define PERIC_PCLK_HSI2C3			19
+#define PERIC_PCLK_HSI2C4			20
+#define PERIC_PCLK_HSI2C5			21
+#define PERIC_PCLK_HSI2C6			22
+#define PERIC_PCLK_HSI2C7			23
+#define PERIC_MCAN0_IPCLKPORT_CCLK		24
+#define PERIC_MCAN0_IPCLKPORT_PCLK		25
+#define PERIC_MCAN1_IPCLKPORT_CCLK		26
+#define PERIC_MCAN1_IPCLKPORT_PCLK		27
+#define PERIC_MCAN2_IPCLKPORT_CCLK		28
+#define PERIC_MCAN2_IPCLKPORT_PCLK		29
+#define PERIC_MCAN3_IPCLKPORT_CCLK		30
+#define PERIC_MCAN3_IPCLKPORT_PCLK		31
+#define PERIC_PCLK_ADCIF			32
+#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I  33
+#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I		34
+#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I		35
+#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I	36
+#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I	37
+#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK	38
+#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK	39
+#define PERIC_HCLK_TDM0				40
+#define PERIC_PCLK_TDM1				41
+#define PERIC_HCLK_TDM1				42
+#define PERIC_EQOS_PHYRXCLK_MUX			43
+#define PERIC_EQOS_PHYRXCLK			44
+#define PERIC_DOUT_RGMII_CLK			45
+
+/* FSYS0 */
+#define UFS0_MPHY_REFCLK_IXTAL24		1
+#define UFS0_MPHY_REFCLK_IXTAL26		2
+#define UFS1_MPHY_REFCLK_IXTAL24		3
+#define UFS1_MPHY_REFCLK_IXTAL26		4
+#define UFS0_TOP0_HCLK_BUS			5
+#define UFS0_TOP0_ACLK				6
+#define UFS0_TOP0_CLK_UNIPRO			7
+#define UFS0_TOP0_FMP_CLK			8
+#define UFS1_TOP1_HCLK_BUS			9
+#define UFS1_TOP1_ACLK				10
+#define UFS1_TOP1_CLK_UNIPRO			11
+#define UFS1_TOP1_FMP_CLK			12
+#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC		13
+#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC		14
+#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC	15
+#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC		16
+#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
+#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I	18
+#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I	19
+#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I	20
+#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I	21
+#define FSYS0_DOUT_FSYS0_PERIBUS_GRP		22
+
+/* FSYS1 */
+#define PCIE_LINK0_IPCLKPORT_DBI_ACLK		1
+#define PCIE_LINK0_IPCLKPORT_AUX_ACLK		2
+#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK		3
+#define PCIE_LINK0_IPCLKPORT_SLV_ACLK		4
+#define PCIE_LINK1_IPCLKPORT_DBI_ACLK		5
+#define PCIE_LINK1_IPCLKPORT_AUX_ACLK		6
+#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK		7
+#define PCIE_LINK1_IPCLKPORT_SLV_ACLK		8
+
+/* IMEM */
+#define IMEM_DMA0_IPCLKPORT_ACLK		1
+#define IMEM_DMA1_IPCLKPORT_ACLK		2
+#define IMEM_WDT0_IPCLKPORT_PCLK		3
+#define IMEM_WDT1_IPCLKPORT_PCLK		4
+#define IMEM_WDT2_IPCLKPORT_PCLK		5
+#define IMEM_MCT_PCLK				6
+#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS	7
+#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS	8
+#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS		9
+#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS		10
+#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS		11
+
+/* MFC */
+#define MFC_MFC_IPCLKPORT_ACLK			1
+
+/* CAM_CSI */
+#define CAM_CSI0_0_IPCLKPORT_I_ACLK		1
+#define CAM_CSI0_1_IPCLKPORT_I_ACLK		2
+#define CAM_CSI0_2_IPCLKPORT_I_ACLK		3
+#define CAM_CSI0_3_IPCLKPORT_I_ACLK		4
+#define CAM_CSI1_0_IPCLKPORT_I_ACLK		5
+#define CAM_CSI1_1_IPCLKPORT_I_ACLK		6
+#define CAM_CSI1_2_IPCLKPORT_I_ACLK		7
+#define CAM_CSI1_3_IPCLKPORT_I_ACLK		8
+#define CAM_CSI2_0_IPCLKPORT_I_ACLK		9
+#define CAM_CSI2_1_IPCLKPORT_I_ACLK		10
+#define CAM_CSI2_2_IPCLKPORT_I_ACLK		11
+#define CAM_CSI2_3_IPCLKPORT_I_ACLK		12
+#define CAM_CSI_PLL				13
+#define CAM_CSI0_0_IPCLKPORT_I_PCLK		14
+#define CAM_CSI0_1_IPCLKPORT_I_PCLK		15
+#define CAM_CSI0_2_IPCLKPORT_I_PCLK		16
+#define CAM_CSI0_3_IPCLKPORT_I_PCLK		17
+#define CAM_CSI1_0_IPCLKPORT_I_PCLK		18
+#define CAM_CSI1_1_IPCLKPORT_I_PCLK		19
+#define CAM_CSI1_2_IPCLKPORT_I_PCLK		20
+#define CAM_CSI1_3_IPCLKPORT_I_PCLK		21
+#define CAM_CSI2_0_IPCLKPORT_I_PCLK		22
+#define CAM_CSI2_1_IPCLKPORT_I_PCLK		23
+#define CAM_CSI2_2_IPCLKPORT_I_PCLK		24
+#define CAM_CSI2_3_IPCLKPORT_I_PCLK		25
+
+#endif /*_DT_BINDINGS_CLOCK_FSD_H */

linux-7.2.3/include/dt-bindings/clock/fsl,qoriq-clockgen.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK	0
+#define QORIQ_CLK_CMUX		1
+#define QORIQ_CLK_HWACCEL	2
+#define QORIQ_CLK_FMAN		3
+#define QORIQ_CLK_PLATFORM_PLL	4
+#define QORIQ_CLK_CORECLK	5
+
+#define QORIQ_CLK_PLL_DIV(x)	((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */

linux-7.2.3/include/dt-bindings/clock/g12a-aoclkc.h

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+
+#define CLKID_AO_AHB		0
+#define CLKID_AO_IR_IN		1
+#define CLKID_AO_I2C_M0		2
+#define CLKID_AO_I2C_S0		3
+#define CLKID_AO_UART		4
+#define CLKID_AO_PROD_I2C	5
+#define CLKID_AO_UART2		6
+#define CLKID_AO_IR_OUT		7
+#define CLKID_AO_SAR_ADC	8
+#define CLKID_AO_MAILBOX	9
+#define CLKID_AO_M3		10
+#define CLKID_AO_AHB_SRAM	11
+#define CLKID_AO_RTI		12
+#define CLKID_AO_M4_FCLK	13
+#define CLKID_AO_M4_HCLK	14
+#define CLKID_AO_CLK81		15
+#define CLKID_AO_SAR_ADC_DIV	17
+#define CLKID_AO_SAR_ADC_SEL	16
+#define CLKID_AO_SAR_ADC_CLK	18
+#define CLKID_AO_CTS_OSCIN	19
+#define CLKID_AO_32K_PRE	20
+#define CLKID_AO_32K_DIV	21
+#define CLKID_AO_32K_SEL	22
+#define CLKID_AO_32K		23
+#define CLKID_AO_CEC_PRE	24
+#define CLKID_AO_CEC_DIV	25
+#define CLKID_AO_CEC_SEL	26
+#define CLKID_AO_CEC		27
+#define CLKID_AO_CTS_RTC_OSCIN	28
+
+#endif

linux-7.2.3/include/dt-bindings/clock/g12a-clkc.h

@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Meson-G12A clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __G12A_CLKC_H
+#define __G12A_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_MPEG_SEL				8
+#define CLKID_MPEG_DIV				9
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_DOS				16
+#define CLKID_AUDIO_LOCKER			17
+#define CLKID_MIPI_DSI_HOST			18
+#define CLKID_ETH_PHY				19
+#define CLKID_ISA				20
+#define CLKID_PL301				21
+#define CLKID_PERIPHS				22
+#define CLKID_SPICC0				23
+#define CLKID_I2C				24
+#define CLKID_SANA				25
+#define CLKID_SD				26
+#define CLKID_RNG0				27
+#define CLKID_UART0				28
+#define CLKID_SPICC1				29
+#define CLKID_HIU_IFACE				30
+#define CLKID_MIPI_DSI_PHY			31
+#define CLKID_ASSIST_MISC			32
+#define CLKID_SD_EMMC_A				33
+#define CLKID_SD_EMMC_B				34
+#define CLKID_SD_EMMC_C				35
+#define CLKID_AUDIO_CODEC			36
+#define CLKID_AUDIO				37
+#define CLKID_ETH				38
+#define CLKID_DEMUX				39
+#define CLKID_AUDIO_IFIFO			40
+#define CLKID_ADC				41
+#define CLKID_UART1				42
+#define CLKID_G2D				43
+#define CLKID_RESET				44
+#define CLKID_PCIE_COMB				45
+#define CLKID_PARSER				46
+#define CLKID_USB				47
+#define CLKID_PCIE_PHY				48
+#define CLKID_AHB_ARB0				49
+#define CLKID_AHB_DATA_BUS			50
+#define CLKID_AHB_CTRL_BUS			51
+#define CLKID_HTX_HDCP22			52
+#define CLKID_HTX_PCLK				53
+#define CLKID_BT656				54
+#define CLKID_USB1_DDR_BRIDGE			55
+#define CLKID_MMC_PCLK				56
+#define CLKID_UART2				57
+#define CLKID_VPU_INTR				58
+#define CLKID_GIC				59
+#define CLKID_SD_EMMC_A_CLK0			60
+#define CLKID_SD_EMMC_B_CLK0			61
+#define CLKID_SD_EMMC_C_CLK0			62
+#define CLKID_SD_EMMC_A_CLK0_SEL		63
+#define CLKID_SD_EMMC_A_CLK0_DIV		64
+#define CLKID_SD_EMMC_B_CLK0_SEL		65
+#define CLKID_SD_EMMC_B_CLK0_DIV		66
+#define CLKID_SD_EMMC_C_CLK0_SEL		67
+#define CLKID_SD_EMMC_C_CLK0_DIV		68
+#define CLKID_MPLL0_DIV				69
+#define CLKID_MPLL1_DIV				70
+#define CLKID_MPLL2_DIV				71
+#define CLKID_MPLL3_DIV				72
+#define CLKID_MPLL_PREDIV			73
+#define CLKID_HIFI_PLL				74
+#define CLKID_FCLK_DIV2_DIV			75
+#define CLKID_FCLK_DIV3_DIV			76
+#define CLKID_FCLK_DIV4_DIV			77
+#define CLKID_FCLK_DIV5_DIV			78
+#define CLKID_FCLK_DIV7_DIV			79
+#define CLKID_VCLK2_VENCI0			80
+#define CLKID_VCLK2_VENCI1			81
+#define CLKID_VCLK2_VENCP0			82
+#define CLKID_VCLK2_VENCP1			83
+#define CLKID_VCLK2_VENCT0			84
+#define CLKID_VCLK2_VENCT1			85
+#define CLKID_VCLK2_OTHER			86
+#define CLKID_VCLK2_ENCI			87
+#define CLKID_VCLK2_ENCP			88
+#define CLKID_DAC_CLK				89
+#define CLKID_AOCLK				90
+#define CLKID_IEC958				91
+#define CLKID_ENC480P				92
+#define CLKID_RNG1				93
+#define CLKID_VCLK2_ENCT			94
+#define CLKID_VCLK2_ENCL			95
+#define CLKID_VCLK2_VENCLMMC			96
+#define CLKID_VCLK2_VENCL			97
+#define CLKID_VCLK2_OTHER1			98
+#define CLKID_FCLK_DIV2P5			99
+#define CLKID_FCLK_DIV2P5_DIV			100
+#define CLKID_FIXED_PLL_DCO			101
+#define CLKID_SYS_PLL_DCO			102
+#define CLKID_GP0_PLL_DCO			103
+#define CLKID_HIFI_PLL_DCO			104
+#define CLKID_DMA				105
+#define CLKID_EFUSE				106
+#define CLKID_ROM_BOOT				107
+#define CLKID_RESET_SEC				108
+#define CLKID_SEC_AHB_APB3			109
+#define CLKID_VPU_0_SEL				110
+#define CLKID_VPU_0_DIV				111
+#define CLKID_VPU_0				112
+#define CLKID_VPU_1_SEL				113
+#define CLKID_VPU_1_DIV				114
+#define CLKID_VPU_1				115
+#define CLKID_VPU				116
+#define CLKID_VAPB_0_SEL			117
+#define CLKID_VAPB_0_DIV			118
+#define CLKID_VAPB_0				119
+#define CLKID_VAPB_1_SEL			120
+#define CLKID_VAPB_1_DIV			121
+#define CLKID_VAPB_1				122
+#define CLKID_VAPB_SEL				123
+#define CLKID_VAPB				124
+#define CLKID_HDMI_PLL_DCO			125
+#define CLKID_HDMI_PLL_OD			126
+#define CLKID_HDMI_PLL_OD2			127
+#define CLKID_HDMI_PLL				128
+#define CLKID_VID_PLL				129
+#define CLKID_VID_PLL_SEL			130
+#define CLKID_VID_PLL_DIV			131
+#define CLKID_VCLK_SEL				132
+#define CLKID_VCLK2_SEL				133
+#define CLKID_VCLK_INPUT			134
+#define CLKID_VCLK2_INPUT			135
+#define CLKID_VCLK_DIV				136
+#define CLKID_VCLK2_DIV				137
+#define CLKID_VCLK				138
+#define CLKID_VCLK2				139
+#define CLKID_VCLK_DIV2_EN			140
+#define CLKID_VCLK_DIV4_EN			141
+#define CLKID_VCLK_DIV6_EN			142
+#define CLKID_VCLK_DIV12_EN			143
+#define CLKID_VCLK2_DIV2_EN			144
+#define CLKID_VCLK2_DIV4_EN			145
+#define CLKID_VCLK2_DIV6_EN			146
+#define CLKID_VCLK2_DIV12_EN			147
+#define CLKID_VCLK_DIV1				148
+#define CLKID_VCLK_DIV2				149
+#define CLKID_VCLK_DIV4				150
+#define CLKID_VCLK_DIV6				151
+#define CLKID_VCLK_DIV12			152
+#define CLKID_VCLK2_DIV1			153
+#define CLKID_VCLK2_DIV2			154
+#define CLKID_VCLK2_DIV4			155
+#define CLKID_VCLK2_DIV6			156
+#define CLKID_VCLK2_DIV12			157
+#define CLKID_CTS_ENCI_SEL			158
+#define CLKID_CTS_ENCP_SEL			159
+#define CLKID_CTS_VDAC_SEL			160
+#define CLKID_HDMI_TX_SEL			161
+#define CLKID_CTS_ENCI				162
+#define CLKID_CTS_ENCP				163
+#define CLKID_CTS_VDAC				164
+#define CLKID_HDMI_TX				165
+#define CLKID_HDMI_SEL				166
+#define CLKID_HDMI_DIV				167
+#define CLKID_HDMI				168
+#define CLKID_MALI_0_SEL			169
+#define CLKID_MALI_0_DIV			170
+#define CLKID_MALI_0				171
+#define CLKID_MALI_1_SEL			172
+#define CLKID_MALI_1_DIV			173
+#define CLKID_MALI_1				174
+#define CLKID_MALI				175
+#define CLKID_MPLL_50M_DIV			176
+#define CLKID_MPLL_50M				177
+#define CLKID_SYS_PLL_DIV16_EN			178
+#define CLKID_SYS_PLL_DIV16			179
+#define CLKID_CPU_CLK_DYN0_SEL			180
+#define CLKID_CPU_CLK_DYN0_DIV			181
+#define CLKID_CPU_CLK_DYN0			182
+#define CLKID_CPU_CLK_DYN1_SEL			183
+#define CLKID_CPU_CLK_DYN1_DIV			184
+#define CLKID_CPU_CLK_DYN1			185
+#define CLKID_CPU_CLK_DYN			186
+#define CLKID_CPU_CLK				187
+#define CLKID_CPU_CLK_DIV16_EN			188
+#define CLKID_CPU_CLK_DIV16			189
+#define CLKID_CPU_CLK_APB_DIV			190
+#define CLKID_CPU_CLK_APB			191
+#define CLKID_CPU_CLK_ATB_DIV			192
+#define CLKID_CPU_CLK_ATB			193
+#define CLKID_CPU_CLK_AXI_DIV			194
+#define CLKID_CPU_CLK_AXI			195
+#define CLKID_CPU_CLK_TRACE_DIV			196
+#define CLKID_CPU_CLK_TRACE			197
+#define CLKID_PCIE_PLL_DCO			198
+#define CLKID_PCIE_PLL_DCO_DIV2			199
+#define CLKID_PCIE_PLL_OD			200
+#define CLKID_PCIE_PLL				201
+#define CLKID_VDEC_1_SEL			202
+#define CLKID_VDEC_1_DIV			203
+#define CLKID_VDEC_1				204
+#define CLKID_VDEC_HEVC_SEL			205
+#define CLKID_VDEC_HEVC_DIV			206
+#define CLKID_VDEC_HEVC				207
+#define CLKID_VDEC_HEVCF_SEL			208
+#define CLKID_VDEC_HEVCF_DIV			209
+#define CLKID_VDEC_HEVCF			210
+#define CLKID_TS_DIV				211
+#define CLKID_TS				212
+#define CLKID_SYS1_PLL_DCO			213
+#define CLKID_SYS1_PLL				214
+#define CLKID_SYS1_PLL_DIV16_EN			215
+#define CLKID_SYS1_PLL_DIV16			216
+#define CLKID_CPUB_CLK_DYN0_SEL			217
+#define CLKID_CPUB_CLK_DYN0_DIV			218
+#define CLKID_CPUB_CLK_DYN0			219
+#define CLKID_CPUB_CLK_DYN1_SEL			220
+#define CLKID_CPUB_CLK_DYN1_DIV			221
+#define CLKID_CPUB_CLK_DYN1			222
+#define CLKID_CPUB_CLK_DYN			223
+#define CLKID_CPUB_CLK				224
+#define CLKID_CPUB_CLK_DIV16_EN			225
+#define CLKID_CPUB_CLK_DIV16			226
+#define CLKID_CPUB_CLK_DIV2			227
+#define CLKID_CPUB_CLK_DIV3			228
+#define CLKID_CPUB_CLK_DIV4			229
+#define CLKID_CPUB_CLK_DIV5			230
+#define CLKID_CPUB_CLK_DIV6			231
+#define CLKID_CPUB_CLK_DIV7			232
+#define CLKID_CPUB_CLK_DIV8			233
+#define CLKID_CPUB_CLK_APB_SEL			234
+#define CLKID_CPUB_CLK_APB			235
+#define CLKID_CPUB_CLK_ATB_SEL			236
+#define CLKID_CPUB_CLK_ATB			237
+#define CLKID_CPUB_CLK_AXI_SEL			238
+#define CLKID_CPUB_CLK_AXI			239
+#define CLKID_CPUB_CLK_TRACE_SEL		240
+#define CLKID_CPUB_CLK_TRACE			241
+#define CLKID_GP1_PLL_DCO			242
+#define CLKID_GP1_PLL				243
+#define CLKID_DSU_CLK_DYN0_SEL			244
+#define CLKID_DSU_CLK_DYN0_DIV			245
+#define CLKID_DSU_CLK_DYN0			246
+#define CLKID_DSU_CLK_DYN1_SEL			247
+#define CLKID_DSU_CLK_DYN1_DIV			248
+#define CLKID_DSU_CLK_DYN1			249
+#define CLKID_DSU_CLK_DYN			250
+#define CLKID_DSU_CLK_FINAL			251
+#define CLKID_DSU_CLK				252
+#define CLKID_CPU1_CLK				253
+#define CLKID_CPU2_CLK				254
+#define CLKID_CPU3_CLK				255
+#define CLKID_SPICC0_SCLK_SEL			256
+#define CLKID_SPICC0_SCLK_DIV			257
+#define CLKID_SPICC0_SCLK			258
+#define CLKID_SPICC1_SCLK_SEL			259
+#define CLKID_SPICC1_SCLK_DIV			260
+#define CLKID_SPICC1_SCLK			261
+#define CLKID_NNA_AXI_CLK_SEL			262
+#define CLKID_NNA_AXI_CLK_DIV			263
+#define CLKID_NNA_AXI_CLK			264
+#define CLKID_NNA_CORE_CLK_SEL			265
+#define CLKID_NNA_CORE_CLK_DIV			266
+#define CLKID_NNA_CORE_CLK			267
+#define CLKID_MIPI_DSI_PXCLK_DIV		268
+#define CLKID_MIPI_DSI_PXCLK_SEL		269
+#define CLKID_MIPI_DSI_PXCLK			270
+#define CLKID_CTS_ENCL				271
+#define CLKID_CTS_ENCL_SEL			272
+#define CLKID_MIPI_ISP_DIV			273
+#define CLKID_MIPI_ISP_SEL			274
+#define CLKID_MIPI_ISP				275
+#define CLKID_MIPI_ISP_GATE			276
+#define CLKID_MIPI_ISP_CSI_PHY0			277
+#define CLKID_MIPI_ISP_CSI_PHY1			278
+
+#endif /* __G12A_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/google,gs101-acpm.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025 Linaro Ltd.
+ *
+ * Device Tree binding constants for Google gs101 ACPM clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H
+
+#define GS101_CLK_ACPM_DVFS_MIF				0
+#define GS101_CLK_ACPM_DVFS_INT				1
+#define GS101_CLK_ACPM_DVFS_CPUCL0			2
+#define GS101_CLK_ACPM_DVFS_CPUCL1			3
+#define GS101_CLK_ACPM_DVFS_CPUCL2			4
+#define GS101_CLK_ACPM_DVFS_G3D				5
+#define GS101_CLK_ACPM_DVFS_G3DL2			6
+#define GS101_CLK_ACPM_DVFS_TPU				7
+#define GS101_CLK_ACPM_DVFS_INTCAM			8
+#define GS101_CLK_ACPM_DVFS_TNR				9
+#define GS101_CLK_ACPM_DVFS_CAM				10
+#define GS101_CLK_ACPM_DVFS_MFC				11
+#define GS101_CLK_ACPM_DVFS_DISP			12
+#define GS101_CLK_ACPM_DVFS_BO				13
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */

linux-7.2.3/include/dt-bindings/clock/google,gs101.h

@@ -0,0 +1,673 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_SHARED2_PLL		3
+#define CLK_FOUT_SHARED3_PLL		4
+#define CLK_FOUT_SPARE_PLL		5
+
+/* CMU_TOP MUX */
+#define CLK_MOUT_PLL_SHARED0		6
+#define CLK_MOUT_PLL_SHARED1		7
+#define CLK_MOUT_PLL_SHARED2		8
+#define CLK_MOUT_PLL_SHARED3		9
+#define CLK_MOUT_PLL_SPARE		10
+#define CLK_MOUT_CMU_BO_BUS		11
+#define CLK_MOUT_CMU_BUS0_BUS		12
+#define CLK_MOUT_CMU_BUS1_BUS		13
+#define CLK_MOUT_CMU_BUS2_BUS		14
+#define CLK_MOUT_CMU_CIS_CLK0		15
+#define CLK_MOUT_CMU_CIS_CLK1		16
+#define CLK_MOUT_CMU_CIS_CLK2		17
+#define CLK_MOUT_CMU_CIS_CLK3		18
+#define CLK_MOUT_CMU_CIS_CLK4		19
+#define CLK_MOUT_CMU_CIS_CLK5		20
+#define CLK_MOUT_CMU_CIS_CLK6		21
+#define CLK_MOUT_CMU_CIS_CLK7		22
+#define CLK_MOUT_CMU_CMU_BOOST		23
+#define CLK_MOUT_CMU_BOOST_OPTION1	24
+#define CLK_MOUT_CMU_CORE_BUS		25
+#define CLK_MOUT_CMU_CPUCL0_DBG		26
+#define CLK_MOUT_CMU_CPUCL0_SWITCH	27
+#define CLK_MOUT_CMU_CPUCL1_SWITCH	28
+#define CLK_MOUT_CMU_CPUCL2_SWITCH	29
+#define CLK_MOUT_CMU_CSIS_BUS		30
+#define CLK_MOUT_CMU_DISP_BUS		31
+#define CLK_MOUT_CMU_DNS_BUS		32
+#define CLK_MOUT_CMU_DPU_BUS		33
+#define CLK_MOUT_CMU_EH_BUS		34
+#define CLK_MOUT_CMU_G2D_G2D		35
+#define CLK_MOUT_CMU_G2D_MSCL		36
+#define CLK_MOUT_CMU_G3AA_G3AA		37
+#define CLK_MOUT_CMU_G3D_BUSD		38
+#define CLK_MOUT_CMU_G3D_GLB		39
+#define CLK_MOUT_CMU_G3D_SWITCH		40
+#define CLK_MOUT_CMU_GDC_GDC0		41
+#define CLK_MOUT_CMU_GDC_GDC1		42
+#define CLK_MOUT_CMU_GDC_SCSC		43
+#define CLK_MOUT_CMU_HPM		44
+#define CLK_MOUT_CMU_HSI0_BUS		45
+#define CLK_MOUT_CMU_HSI0_DPGTC		46
+#define CLK_MOUT_CMU_HSI0_USB31DRD	47
+#define CLK_MOUT_CMU_HSI0_USBDPDBG	48
+#define CLK_MOUT_CMU_HSI1_BUS		49
+#define CLK_MOUT_CMU_HSI1_PCIE		50
+#define CLK_MOUT_CMU_HSI2_BUS		51
+#define CLK_MOUT_CMU_HSI2_MMC_CARD	52
+#define CLK_MOUT_CMU_HSI2_PCIE		53
+#define CLK_MOUT_CMU_HSI2_UFS_EMBD	54
+#define CLK_MOUT_CMU_IPP_BUS		55
+#define CLK_MOUT_CMU_ITP_BUS		56
+#define CLK_MOUT_CMU_MCSC_ITSC		57
+#define CLK_MOUT_CMU_MCSC_MCSC		58
+#define CLK_MOUT_CMU_MFC_MFC		59
+#define CLK_MOUT_CMU_MIF_BUSP		60
+#define CLK_MOUT_CMU_MIF_SWITCH		61
+#define CLK_MOUT_CMU_MISC_BUS		62
+#define CLK_MOUT_CMU_MISC_SSS		63
+#define CLK_MOUT_CMU_PDP_BUS		64
+#define CLK_MOUT_CMU_PDP_VRA		65
+#define CLK_MOUT_CMU_PERIC0_BUS		66
+#define CLK_MOUT_CMU_PERIC0_IP		67
+#define CLK_MOUT_CMU_PERIC1_BUS		68
+#define CLK_MOUT_CMU_PERIC1_IP		69
+#define CLK_MOUT_CMU_TNR_BUS		70
+#define CLK_MOUT_CMU_TOP_BOOST_OPTION1	71
+#define CLK_MOUT_CMU_TOP_CMUREF		72
+#define CLK_MOUT_CMU_TPU_BUS		73
+#define CLK_MOUT_CMU_TPU_TPU		74
+#define CLK_MOUT_CMU_TPU_TPUCTL		75
+#define CLK_MOUT_CMU_TPU_UART		76
+#define CLK_MOUT_CMU_CMUREF		77
+
+/* CMU_TOP Dividers */
+#define CLK_DOUT_CMU_BO_BUS		78
+#define CLK_DOUT_CMU_BUS0_BUS		79
+#define CLK_DOUT_CMU_BUS1_BUS		80
+#define CLK_DOUT_CMU_BUS2_BUS		81
+#define CLK_DOUT_CMU_CIS_CLK0		82
+#define CLK_DOUT_CMU_CIS_CLK1		83
+#define CLK_DOUT_CMU_CIS_CLK2		84
+#define CLK_DOUT_CMU_CIS_CLK3		85
+#define CLK_DOUT_CMU_CIS_CLK4		86
+#define CLK_DOUT_CMU_CIS_CLK5		87
+#define CLK_DOUT_CMU_CIS_CLK6		88
+#define CLK_DOUT_CMU_CIS_CLK7		89
+#define CLK_DOUT_CMU_CORE_BUS		90
+#define CLK_DOUT_CMU_CPUCL0_DBG		91
+#define CLK_DOUT_CMU_CPUCL0_SWITCH	92
+#define CLK_DOUT_CMU_CPUCL1_SWITCH	93
+#define CLK_DOUT_CMU_CPUCL2_SWITCH	94
+#define CLK_DOUT_CMU_CSIS_BUS		95
+#define CLK_DOUT_CMU_DISP_BUS		96
+#define CLK_DOUT_CMU_DNS_BUS		97
+#define CLK_DOUT_CMU_DPU_BUS		98
+#define CLK_DOUT_CMU_EH_BUS		99
+#define CLK_DOUT_CMU_G2D_G2D		100
+#define CLK_DOUT_CMU_G2D_MSCL		101
+#define CLK_DOUT_CMU_G3AA_G3AA		102
+#define CLK_DOUT_CMU_G3D_BUSD		103
+#define CLK_DOUT_CMU_G3D_GLB		104
+#define CLK_DOUT_CMU_G3D_SWITCH		105
+#define CLK_DOUT_CMU_GDC_GDC0		106
+#define CLK_DOUT_CMU_GDC_GDC1		107
+#define CLK_DOUT_CMU_GDC_SCSC		108
+#define CLK_DOUT_CMU_CMU_HPM		109
+#define CLK_DOUT_CMU_HSI0_BUS		110
+#define CLK_DOUT_CMU_HSI0_DPGTC		111
+#define CLK_DOUT_CMU_HSI0_USB31DRD	112
+#define CLK_DOUT_CMU_HSI0_USBDPDBG	113
+#define CLK_DOUT_CMU_HSI1_BUS		114
+#define CLK_DOUT_CMU_HSI1_PCIE		115
+#define CLK_DOUT_CMU_HSI2_BUS		116
+#define CLK_DOUT_CMU_HSI2_MMC_CARD	117
+#define CLK_DOUT_CMU_HSI2_PCIE		118
+#define CLK_DOUT_CMU_HSI2_UFS_EMBD	119
+#define CLK_DOUT_CMU_IPP_BUS		120
+#define CLK_DOUT_CMU_ITP_BUS		121
+#define CLK_DOUT_CMU_MCSC_ITSC		122
+#define CLK_DOUT_CMU_MCSC_MCSC		123
+#define CLK_DOUT_CMU_MFC_MFC		124
+#define CLK_DOUT_CMU_MIF_BUSP		125
+#define CLK_DOUT_CMU_MISC_BUS		126
+#define CLK_DOUT_CMU_MISC_SSS		127
+#define CLK_DOUT_CMU_OTP		128
+#define CLK_DOUT_CMU_PDP_BUS		129
+#define CLK_DOUT_CMU_PDP_VRA		130
+#define CLK_DOUT_CMU_PERIC0_BUS		131
+#define CLK_DOUT_CMU_PERIC0_IP		132
+#define CLK_DOUT_CMU_PERIC1_BUS		133
+#define CLK_DOUT_CMU_PERIC1_IP		134
+#define CLK_DOUT_CMU_TNR_BUS		135
+#define CLK_DOUT_CMU_TPU_BUS		136
+#define CLK_DOUT_CMU_TPU_TPU		137
+#define CLK_DOUT_CMU_TPU_TPUCTL		138
+#define CLK_DOUT_CMU_TPU_UART		139
+#define CLK_DOUT_CMU_CMU_BOOST		140
+#define CLK_DOUT_CMU_CMU_CMUREF		141
+#define CLK_DOUT_CMU_SHARED0_DIV2	142
+#define CLK_DOUT_CMU_SHARED0_DIV3	143
+#define CLK_DOUT_CMU_SHARED0_DIV4	144
+#define CLK_DOUT_CMU_SHARED0_DIV5	145
+#define CLK_DOUT_CMU_SHARED1_DIV2	146
+#define CLK_DOUT_CMU_SHARED1_DIV3	147
+#define CLK_DOUT_CMU_SHARED1_DIV4	148
+#define CLK_DOUT_CMU_SHARED2_DIV2	149
+#define CLK_DOUT_CMU_SHARED3_DIV2	150
+
+/* CMU_TOP Gates */
+#define CLK_GOUT_CMU_BUS0_BOOST		151
+#define CLK_GOUT_CMU_BUS1_BOOST		152
+#define CLK_GOUT_CMU_BUS2_BOOST		153
+#define CLK_GOUT_CMU_CORE_BOOST		154
+#define CLK_GOUT_CMU_CPUCL0_BOOST	155
+#define CLK_GOUT_CMU_CPUCL1_BOOST	156
+#define CLK_GOUT_CMU_CPUCL2_BOOST	157
+#define CLK_GOUT_CMU_MIF_BOOST		158
+#define CLK_GOUT_CMU_MIF_SWITCH		159
+#define CLK_GOUT_CMU_BO_BUS		160
+#define CLK_GOUT_CMU_BUS0_BUS		161
+#define CLK_GOUT_CMU_BUS1_BUS		162
+#define CLK_GOUT_CMU_BUS2_BUS		163
+#define CLK_GOUT_CMU_CIS_CLK0		164
+#define CLK_GOUT_CMU_CIS_CLK1		165
+#define CLK_GOUT_CMU_CIS_CLK2		166
+#define CLK_GOUT_CMU_CIS_CLK3		167
+#define CLK_GOUT_CMU_CIS_CLK4		168
+#define CLK_GOUT_CMU_CIS_CLK5		169
+#define CLK_GOUT_CMU_CIS_CLK6		170
+#define CLK_GOUT_CMU_CIS_CLK7		171
+#define CLK_GOUT_CMU_CMU_BOOST		172
+#define CLK_GOUT_CMU_CORE_BUS		173
+#define CLK_GOUT_CMU_CPUCL0_DBG		174
+#define CLK_GOUT_CMU_CPUCL0_SWITCH	175
+#define CLK_GOUT_CMU_CPUCL1_SWITCH	176
+#define CLK_GOUT_CMU_CPUCL2_SWITCH	177
+#define CLK_GOUT_CMU_CSIS_BUS		178
+#define CLK_GOUT_CMU_DISP_BUS		179
+#define CLK_GOUT_CMU_DNS_BUS		180
+#define CLK_GOUT_CMU_DPU_BUS		181
+#define CLK_GOUT_CMU_EH_BUS		182
+#define CLK_GOUT_CMU_G2D_G2D		183
+#define CLK_GOUT_CMU_G2D_MSCL		184
+#define CLK_GOUT_CMU_G3AA_G3AA		185
+#define CLK_GOUT_CMU_G3D_BUSD		186
+#define CLK_GOUT_CMU_G3D_GLB		187
+#define CLK_GOUT_CMU_G3D_SWITCH		188
+#define CLK_GOUT_CMU_GDC_GDC0		189
+#define CLK_GOUT_CMU_GDC_GDC1		190
+#define CLK_GOUT_CMU_GDC_SCSC		191
+#define CLK_GOUT_CMU_HPM		192
+#define CLK_GOUT_CMU_HSI0_BUS		193
+#define CLK_GOUT_CMU_HSI0_DPGTC		194
+#define CLK_GOUT_CMU_HSI0_USB31DRD	195
+#define CLK_GOUT_CMU_HSI0_USBDPDBG	196
+#define CLK_GOUT_CMU_HSI1_BUS		197
+#define CLK_GOUT_CMU_HSI1_PCIE		198
+#define CLK_GOUT_CMU_HSI2_BUS		199
+#define CLK_GOUT_CMU_HSI2_MMC_CARD	200
+#define CLK_GOUT_CMU_HSI2_PCIE		201
+#define CLK_GOUT_CMU_HSI2_UFS_EMBD	202
+#define CLK_GOUT_CMU_IPP_BUS		203
+#define CLK_GOUT_CMU_ITP_BUS		204
+#define CLK_GOUT_CMU_MCSC_ITSC		205
+#define CLK_GOUT_CMU_MCSC_MCSC		206
+#define CLK_GOUT_CMU_MFC_MFC		207
+#define CLK_GOUT_CMU_MIF_BUSP		208
+#define CLK_GOUT_CMU_MISC_BUS		209
+#define CLK_GOUT_CMU_MISC_SSS		210
+#define CLK_GOUT_CMU_PDP_BUS		211
+#define CLK_GOUT_CMU_PDP_VRA		212
+#define CLK_GOUT_CMU_G3AA		213
+#define CLK_GOUT_CMU_PERIC0_BUS		214
+#define CLK_GOUT_CMU_PERIC0_IP		215
+#define CLK_GOUT_CMU_PERIC1_BUS		216
+#define CLK_GOUT_CMU_PERIC1_IP		217
+#define CLK_GOUT_CMU_TNR_BUS		218
+#define CLK_GOUT_CMU_TOP_CMUREF		219
+#define CLK_GOUT_CMU_TPU_BUS		220
+#define CLK_GOUT_CMU_TPU_TPU		221
+#define CLK_GOUT_CMU_TPU_TPUCTL		222
+#define CLK_GOUT_CMU_TPU_UART		223
+
+/* CMU_APM */
+#define CLK_MOUT_APM_FUNC				1
+#define CLK_MOUT_APM_FUNCSRC				2
+#define CLK_DOUT_APM_BOOST				3
+#define CLK_DOUT_APM_USI0_UART				4
+#define CLK_DOUT_APM_USI0_USI				5
+#define CLK_DOUT_APM_USI1_UART				6
+#define CLK_GOUT_APM_APM_CMU_APM_PCLK			7
+#define CLK_GOUT_BUS0_BOOST_OPTION1			8
+#define CLK_GOUT_CMU_BOOST_OPTION1			9
+#define CLK_GOUT_CORE_BOOST_OPTION1			10
+#define CLK_GOUT_APM_FUNC				11
+#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK		12
+#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK		13
+#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK		14
+#define CLK_GOUT_APM_APBIF_RTC_PCLK			15
+#define CLK_GOUT_APM_APBIF_TRTC_PCLK			16
+#define CLK_GOUT_APM_APM_USI0_UART_IPCLK		17
+#define CLK_GOUT_APM_APM_USI0_UART_PCLK			18
+#define CLK_GOUT_APM_APM_USI0_USI_IPCLK			19
+#define CLK_GOUT_APM_APM_USI0_USI_PCLK			20
+#define CLK_GOUT_APM_APM_USI1_UART_IPCLK		21
+#define CLK_GOUT_APM_APM_USI1_UART_PCLK			22
+#define CLK_GOUT_APM_D_TZPC_APM_PCLK			23
+#define CLK_GOUT_APM_GPC_APM_PCLK			24
+#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK		25
+#define CLK_GOUT_APM_INTMEM_ACLK			26
+#define CLK_GOUT_APM_INTMEM_PCLK			27
+#define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK		28
+#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK		29
+#define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK		30
+#define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK		31
+#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK		32
+#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK		33
+#define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK		34
+#define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK		35
+#define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK		36
+#define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK		37
+#define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK		38
+#define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK		39
+#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK		40
+#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK			41
+#define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK		42
+#define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK		43
+#define CLK_GOUT_APM_CLK_APM_BUS_CLK			44
+#define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK		45
+#define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK		46
+#define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK		47
+#define CLK_GOUT_APM_SPEEDY_APM_PCLK			48
+#define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK		49
+#define CLK_GOUT_APM_SSMT_D_APM_ACLK			50
+#define CLK_GOUT_APM_SSMT_D_APM_PCLK			51
+#define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK		52
+#define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK		53
+#define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK		54
+#define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2		55
+#define CLK_GOUT_APM_SYSREG_APM_PCLK			56
+#define CLK_GOUT_APM_UASC_APM_ACLK			57
+#define CLK_GOUT_APM_UASC_APM_PCLK			58
+#define CLK_GOUT_APM_UASC_DBGCORE_ACLK			59
+#define CLK_GOUT_APM_UASC_DBGCORE_PCLK			60
+#define CLK_GOUT_APM_UASC_G_SWD_ACLK			61
+#define CLK_GOUT_APM_UASC_G_SWD_PCLK			62
+#define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK			63
+#define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK			64
+#define CLK_GOUT_APM_UASC_P_APM_ACLK			65
+#define CLK_GOUT_APM_UASC_P_APM_PCLK			66
+#define CLK_GOUT_APM_WDT_APM_PCLK			67
+#define CLK_GOUT_APM_XIU_DP_APM_ACLK			68
+#define CLK_APM_PLL_DIV2_APM				69
+#define CLK_APM_PLL_DIV4_APM				70
+#define CLK_APM_PLL_DIV16_APM				71
+
+/* CMU_DPU */
+#define CLK_MOUT_DPU_BUS_USER				1
+#define CLK_DOUT_DPU_BUSP				2
+#define CLK_GOUT_DPU_PCLK				3
+#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK			4
+#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM		5
+#define CLK_GOUT_DPU_DPUF_ACLK_DMA			6
+#define CLK_GOUT_DPU_DPUF_ACLK_DPP			7
+#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK			8
+#define CLK_GOUT_DPU_GPC_DPU_PCLK			9
+#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK		10
+#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK		11
+#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK		12
+#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK		13
+#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK			14
+#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK			15
+#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK			16
+#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK			17
+#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK			18
+#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK			19
+#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK			20
+#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK			21
+#define CLK_GOUT_DPU_SSMT_DPU0_ACLK			22
+#define CLK_GOUT_DPU_SSMT_DPU0_PCLK			23
+#define CLK_GOUT_DPU_SSMT_DPU1_ACLK			24
+#define CLK_GOUT_DPU_SSMT_DPU1_PCLK			25
+#define CLK_GOUT_DPU_SSMT_DPU2_ACLK			26
+#define CLK_GOUT_DPU_SSMT_DPU2_PCLK			27
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1		28
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2		29
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1		30
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2		31
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1		32
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2		33
+#define CLK_GOUT_DPU_SYSREG_DPU_PCLK			34
+
+/* CMU_HSI0 */
+#define CLK_FOUT_USB_PLL					1
+#define CLK_MOUT_PLL_USB					2
+#define CLK_MOUT_HSI0_ALT_USER					3
+#define CLK_MOUT_HSI0_BUS_USER					4
+#define CLK_MOUT_HSI0_DPGTC_USER				5
+#define CLK_MOUT_HSI0_TCXO_USER					6
+#define CLK_MOUT_HSI0_USB20_USER				7
+#define CLK_MOUT_HSI0_USB31DRD_USER				8
+#define CLK_MOUT_HSI0_USBDPDBG_USER				9
+#define CLK_MOUT_HSI0_BUS					10
+#define CLK_MOUT_HSI0_USB20_REF					11
+#define CLK_MOUT_HSI0_USB31DRD					12
+#define CLK_DOUT_HSI0_USB31DRD					13
+#define CLK_GOUT_HSI0_PCLK					14
+#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26	15
+#define CLK_GOUT_HSI0_CLK_HSI0_ALT				16
+#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK			17
+#define CLK_GOUT_HSI0_DP_LINK_I_PCLK				18
+#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK				19
+#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK				20
+#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK				21
+#define CLK_GOUT_HSI0_GPC_HSI0_PCLK				22
+#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK			23
+#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK			24
+#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK			25
+#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK			26
+#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK			27
+#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK			28
+#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK			29
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK			30
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK			31
+#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK				32
+#define CLK_GOUT_HSI0_SSMT_USB_ACLK				33
+#define CLK_GOUT_HSI0_SSMT_USB_PCLK				34
+#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2				35
+#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK				36
+#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK			37
+#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK			38
+#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK			39
+#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK			40
+#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL			41
+#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY			42
+#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26		43
+#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40		44
+#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL		45
+#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK		46
+#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK			47
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK			48
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK		49
+#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK				50
+#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK				51
+#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK				52
+
+/* CMU_HSI2 */
+#define CLK_MOUT_HSI2_BUS_USER						1
+#define CLK_MOUT_HSI2_MMC_CARD_USER					2
+#define CLK_MOUT_HSI2_PCIE_USER						3
+#define CLK_MOUT_HSI2_UFS_EMBD_USER					4
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN		5
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN		6
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK				7
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK				8
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK				9
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK				10
+#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK					11
+#define CLK_GOUT_HSI2_GPC_HSI2_PCLK					12
+#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK					13
+#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK				14
+#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK				15
+#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK				16
+#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK					17
+#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN					18
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG			19
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG			20
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG			21
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK		22
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG			23
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG			24
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG			25
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK		26
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK		27
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK	28
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK	29
+#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK				30
+#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK				31
+#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK					32
+#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK					33
+#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK				34
+#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK				35
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK				36
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK				37
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK				38
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK				39
+#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK				40
+#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK				41
+#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK					42
+#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK				43
+#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK					44
+#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK					45
+#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2				46
+#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK					47
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK			48
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK			49
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK			50
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK			51
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK			52
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK			53
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK			54
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK			55
+#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK					56
+#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO				57
+#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK				58
+#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK					59
+#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK					60
+
+/* CMU_MISC */
+#define CLK_MOUT_MISC_BUS_USER				1
+#define CLK_MOUT_MISC_SSS_USER				2
+#define CLK_MOUT_MISC_GIC				3
+#define CLK_DOUT_MISC_BUSP				4
+#define CLK_DOUT_MISC_GIC				5
+#define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK		6
+#define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK		7
+#define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK		8
+#define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK		9
+#define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK		10
+#define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM			11
+#define CLK_GOUT_MISC_AD_APB_DIT_PCLKM			12
+#define CLK_GOUT_MISC_AD_APB_PUF_PCLKM			13
+#define CLK_GOUT_MISC_DIT_ICLKL2A			14
+#define CLK_GOUT_MISC_D_TZPC_MISC_PCLK			15
+#define CLK_GOUT_MISC_GIC_GICCLK			16
+#define CLK_GOUT_MISC_GPC_MISC_PCLK			17
+#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK		18
+#define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK		19
+#define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK		20
+#define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK		21
+#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK		22
+#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK		23
+#define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK		24
+#define CLK_GOUT_MISC_MCT_PCLK				25
+#define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK			26
+#define CLK_GOUT_MISC_OTP_CON_BISR_PCLK			27
+#define CLK_GOUT_MISC_OTP_CON_TOP_PCLK			28
+#define CLK_GOUT_MISC_PDMA_ACLK				29
+#define CLK_GOUT_MISC_PPMU_DMA_ACLK			30
+#define CLK_GOUT_MISC_PPMU_MISC_ACLK			31
+#define CLK_GOUT_MISC_PPMU_MISC_PCLK			32
+#define CLK_GOUT_MISC_PUF_I_CLK				33
+#define CLK_GOUT_MISC_QE_DIT_ACLK			34
+#define CLK_GOUT_MISC_QE_DIT_PCLK			35
+#define CLK_GOUT_MISC_QE_PDMA_ACLK			36
+#define CLK_GOUT_MISC_QE_PDMA_PCLK			37
+#define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK			38
+#define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK			39
+#define CLK_GOUT_MISC_QE_RTIC_ACLK			40
+#define CLK_GOUT_MISC_QE_RTIC_PCLK			41
+#define CLK_GOUT_MISC_QE_SPDMA_ACLK			42
+#define CLK_GOUT_MISC_QE_SPDMA_PCLK			43
+#define CLK_GOUT_MISC_QE_SSS_ACLK			44
+#define CLK_GOUT_MISC_QE_SSS_PCLK			45
+#define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK			46
+#define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK			47
+#define CLK_GOUT_MISC_CLK_MISC_GIC_CLK			48
+#define CLK_GOUT_MISC_CLK_MISC_SSS_CLK			49
+#define CLK_GOUT_MISC_RTIC_I_ACLK			50
+#define CLK_GOUT_MISC_RTIC_I_PCLK			51
+#define CLK_GOUT_MISC_SPDMA_ACLK			52
+#define CLK_GOUT_MISC_SSMT_DIT_ACLK			53
+#define CLK_GOUT_MISC_SSMT_DIT_PCLK			54
+#define CLK_GOUT_MISC_SSMT_PDMA_ACLK			55
+#define CLK_GOUT_MISC_SSMT_PDMA_PCLK			56
+#define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK		57
+#define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK		58
+#define CLK_GOUT_MISC_SSMT_RTIC_ACLK			59
+#define CLK_GOUT_MISC_SSMT_RTIC_PCLK			60
+#define CLK_GOUT_MISC_SSMT_SPDMA_ACLK			61
+#define CLK_GOUT_MISC_SSMT_SPDMA_PCLK			62
+#define CLK_GOUT_MISC_SSMT_SSS_ACLK			63
+#define CLK_GOUT_MISC_SSMT_SSS_PCLK			64
+#define CLK_GOUT_MISC_SSS_I_ACLK			65
+#define CLK_GOUT_MISC_SSS_I_PCLK			66
+#define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2		67
+#define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1			68
+#define CLK_GOUT_MISC_SYSREG_MISC_PCLK			69
+#define CLK_GOUT_MISC_TMU_SUB_PCLK			70
+#define CLK_GOUT_MISC_TMU_TOP_PCLK			71
+#define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK			72
+#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK			73
+#define CLK_GOUT_MISC_XIU_D_MISC_ACLK			74
+
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_BUS_USER			1
+#define CLK_MOUT_PERIC0_I3C_USER			2
+#define CLK_MOUT_PERIC0_USI0_UART_USER			3
+#define CLK_MOUT_PERIC0_USI14_USI_USER			4
+#define CLK_MOUT_PERIC0_USI1_USI_USER			5
+#define CLK_MOUT_PERIC0_USI2_USI_USER			6
+#define CLK_MOUT_PERIC0_USI3_USI_USER			7
+#define CLK_MOUT_PERIC0_USI4_USI_USER			8
+#define CLK_MOUT_PERIC0_USI5_USI_USER			9
+#define CLK_MOUT_PERIC0_USI6_USI_USER			10
+#define CLK_MOUT_PERIC0_USI7_USI_USER			11
+#define CLK_MOUT_PERIC0_USI8_USI_USER			12
+#define CLK_DOUT_PERIC0_I3C				13
+#define CLK_DOUT_PERIC0_USI0_UART			14
+#define CLK_DOUT_PERIC0_USI14_USI			15
+#define CLK_DOUT_PERIC0_USI1_USI			16
+#define CLK_DOUT_PERIC0_USI2_USI			17
+#define CLK_DOUT_PERIC0_USI3_USI			18
+#define CLK_DOUT_PERIC0_USI4_USI			19
+#define CLK_DOUT_PERIC0_USI5_USI			20
+#define CLK_DOUT_PERIC0_USI6_USI			21
+#define CLK_DOUT_PERIC0_USI7_USI			22
+#define CLK_DOUT_PERIC0_USI8_USI			23
+#define CLK_GOUT_PERIC0_IP				24
+#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK		25
+#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK		26
+#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK		27
+#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK			28
+#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK		29
+#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK		30
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0		31
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1		32
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10		33
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11		34
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12		35
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13		36
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14		37
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15		38
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2		39
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3		40
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4		41
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5		42
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6		43
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7		44
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8		45
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9		46
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0		47
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1		48
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10		49
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11		50
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12		51
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13		52
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14		53
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15		54
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2		55
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3		56
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4		57
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5		58
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6		59
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7		60
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8		61
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9		62
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0		63
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2		64
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0		65
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2		66
+#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK		67
+#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK		68
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK	69
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK	70
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK		71
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK		72
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK		73
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK		74
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK		75
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK		76
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK		77
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK		78
+#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK		79
+
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_BUS_USER			1
+#define CLK_MOUT_PERIC1_I3C_USER			2
+#define CLK_MOUT_PERIC1_USI0_USI_USER			3
+#define CLK_MOUT_PERIC1_USI10_USI_USER			4
+#define CLK_MOUT_PERIC1_USI11_USI_USER			5
+#define CLK_MOUT_PERIC1_USI12_USI_USER			6
+#define CLK_MOUT_PERIC1_USI13_USI_USER			7
+#define CLK_MOUT_PERIC1_USI9_USI_USER			8
+#define CLK_DOUT_PERIC1_I3C				9
+#define CLK_DOUT_PERIC1_USI0_USI			10
+#define CLK_DOUT_PERIC1_USI10_USI			11
+#define CLK_DOUT_PERIC1_USI11_USI			12
+#define CLK_DOUT_PERIC1_USI12_USI			13
+#define CLK_DOUT_PERIC1_USI13_USI			14
+#define CLK_DOUT_PERIC1_USI9_USI			15
+#define CLK_GOUT_PERIC1_IP				16
+#define CLK_GOUT_PERIC1_PCLK				17
+#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK		18
+#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK		19
+#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK		20
+#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK			21
+#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK		22
+#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK		23
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1		24
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2		25
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3		26
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4		27
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5		28
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6		29
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8		30
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1		31
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15		32
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2		33
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3		34
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4		35
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5		36
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6		37
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8		38
+#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK		39
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK		40
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK	41
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK	42
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK	43
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK	44
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK		45
+#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK		46
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */

linux-7.2.3/include/dt-bindings/clock/gxbb-aoclkc.h

@@ -0,0 +1,74 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_CEC_32K	6
+#define CLKID_AO_CTS_OSCIN	7
+#define CLKID_AO_32K_PRE	8
+#define CLKID_AO_32K_DIV	9
+#define CLKID_AO_32K_SEL	10
+#define CLKID_AO_32K		11
+#define CLKID_AO_CTS_RTC_OSCIN	12
+#define CLKID_AO_CLK81		13
+
+#endif

linux-7.2.3/include/dt-bindings/clock/gxbb-clkc.h

@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * GXBB clock tree IDs
+ */
+
+#ifndef __GXBB_CLKC_H
+#define __GXBB_CLKC_H
+
+#define CLKID_SYS_PLL		0
+#define CLKID_HDMI_PLL		2
+#define CLKID_FIXED_PLL		3
+#define CLKID_FCLK_DIV2		4
+#define CLKID_FCLK_DIV3		5
+#define CLKID_FCLK_DIV4		6
+#define CLKID_FCLK_DIV5		7
+#define CLKID_FCLK_DIV7		8
+#define CLKID_GP0_PLL		9
+#define CLKID_MPEG_SEL		10
+#define CLKID_MPEG_DIV		11
+#define CLKID_CLK81		12
+#define CLKID_MPLL0		13
+#define CLKID_MPLL1		14
+#define CLKID_MPLL2		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_ETH		36
+#define CLKID_I2S_SPDIF		35
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT0	77
+#define CLKID_GCLK_VENCI_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCI_INT1	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
+#define CLKID_AO_I2C		93
+#define CLKID_SD_EMMC_A		94
+#define CLKID_SD_EMMC_B		95
+#define CLKID_SD_EMMC_C		96
+#define CLKID_SAR_ADC_CLK	97
+#define CLKID_SAR_ADC_SEL	98
+#define CLKID_SAR_ADC_DIV	99
+#define CLKID_MALI_0_SEL	100
+#define CLKID_MALI_0_DIV	101
+#define CLKID_MALI_0		102
+#define CLKID_MALI_1_SEL	103
+#define CLKID_MALI_1_DIV	104
+#define CLKID_MALI_1		105
+#define CLKID_MALI		106
+#define CLKID_CTS_AMCLK		107
+#define CLKID_CTS_AMCLK_SEL	108
+#define CLKID_CTS_AMCLK_DIV	109
+#define CLKID_CTS_MCLK_I958	110
+#define CLKID_CTS_MCLK_I958_SEL	111
+#define CLKID_CTS_MCLK_I958_DIV 112
+#define CLKID_CTS_I958		113
+#define CLKID_32K_CLK		114
+#define CLKID_32K_CLK_SEL	115
+#define CLKID_32K_CLK_DIV	116
+#define CLKID_SD_EMMC_A_CLK0_SEL 117
+#define CLKID_SD_EMMC_A_CLK0_DIV 118
+#define CLKID_SD_EMMC_A_CLK0	119
+#define CLKID_SD_EMMC_B_CLK0_SEL 120
+#define CLKID_SD_EMMC_B_CLK0_DIV 121
+#define CLKID_SD_EMMC_B_CLK0	122
+#define CLKID_SD_EMMC_C_CLK0_SEL 123
+#define CLKID_SD_EMMC_C_CLK0_DIV 124
+#define CLKID_SD_EMMC_C_CLK0	125
+#define CLKID_VPU_0_SEL		126
+#define CLKID_VPU_0_DIV		127
+#define CLKID_VPU_0		128
+#define CLKID_VPU_1_SEL		129
+#define CLKID_VPU_1_DIV		130
+#define CLKID_VPU_1		131
+#define CLKID_VPU		132
+#define CLKID_VAPB_0_SEL	133
+#define CLKID_VAPB_0_DIV	134
+#define CLKID_VAPB_0		135
+#define CLKID_VAPB_1_SEL	136
+#define CLKID_VAPB_1_DIV	137
+#define CLKID_VAPB_1		138
+#define CLKID_VAPB_SEL		139
+#define CLKID_VAPB		140
+#define CLKID_HDMI_PLL_PRE_MULT	141
+#define CLKID_MPLL0_DIV		142
+#define CLKID_MPLL1_DIV		143
+#define CLKID_MPLL2_DIV		144
+#define CLKID_MPLL_PREDIV	145
+#define CLKID_FCLK_DIV2_DIV	146
+#define CLKID_FCLK_DIV3_DIV	147
+#define CLKID_FCLK_DIV4_DIV	148
+#define CLKID_FCLK_DIV5_DIV	149
+#define CLKID_FCLK_DIV7_DIV	150
+#define CLKID_VDEC_1_SEL	151
+#define CLKID_VDEC_1_DIV	152
+#define CLKID_VDEC_1		153
+#define CLKID_VDEC_HEVC_SEL	154
+#define CLKID_VDEC_HEVC_DIV	155
+#define CLKID_VDEC_HEVC		156
+#define CLKID_GEN_CLK_SEL	157
+#define CLKID_GEN_CLK_DIV	158
+#define CLKID_GEN_CLK		159
+#define CLKID_FIXED_PLL_DCO	160
+#define CLKID_HDMI_PLL_DCO	161
+#define CLKID_HDMI_PLL_OD	162
+#define CLKID_HDMI_PLL_OD2	163
+#define CLKID_SYS_PLL_DCO	164
+#define CLKID_GP0_PLL_DCO	165
+#define CLKID_VID_PLL		166
+#define CLKID_VID_PLL_SEL	167
+#define CLKID_VID_PLL_DIV	168
+#define CLKID_VCLK_SEL		169
+#define CLKID_VCLK2_SEL		170
+#define CLKID_VCLK_INPUT	171
+#define CLKID_VCLK2_INPUT	172
+#define CLKID_VCLK_DIV		173
+#define CLKID_VCLK2_DIV		174
+#define CLKID_VCLK		175
+#define CLKID_VCLK2		176
+#define CLKID_VCLK_DIV2_EN	177
+#define CLKID_VCLK_DIV4_EN	178
+#define CLKID_VCLK_DIV6_EN	179
+#define CLKID_VCLK_DIV12_EN	180
+#define CLKID_VCLK2_DIV2_EN	181
+#define CLKID_VCLK2_DIV4_EN	182
+#define CLKID_VCLK2_DIV6_EN	183
+#define CLKID_VCLK2_DIV12_EN	184
+#define CLKID_VCLK_DIV1		185
+#define CLKID_VCLK_DIV2		186
+#define CLKID_VCLK_DIV4		187
+#define CLKID_VCLK_DIV6		188
+#define CLKID_VCLK_DIV12	189
+#define CLKID_VCLK2_DIV1	190
+#define CLKID_VCLK2_DIV2	191
+#define CLKID_VCLK2_DIV4	192
+#define CLKID_VCLK2_DIV6	193
+#define CLKID_VCLK2_DIV12	194
+#define CLKID_CTS_ENCI_SEL	195
+#define CLKID_CTS_ENCP_SEL	196
+#define CLKID_CTS_VDAC_SEL	197
+#define CLKID_HDMI_TX_SEL	198
+#define CLKID_CTS_ENCI		199
+#define CLKID_CTS_ENCP		200
+#define CLKID_CTS_VDAC		201
+#define CLKID_HDMI_TX		202
+#define CLKID_HDMI_SEL		203
+#define CLKID_HDMI_DIV		204
+#define CLKID_HDMI		205
+#define CLKID_ACODEC		206
+
+#endif /* __GXBB_CLKC_H */

linux-7.2.3/include/dt-bindings/clock/hi3516cv300-clock.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ */
+
+#ifndef __DTS_HI3516CV300_CLOCK_H
+#define __DTS_HI3516CV300_CLOCK_H
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_APB_CLK		0
+#define HI3516CV300_UART0_CLK		1
+#define HI3516CV300_UART1_CLK		2
+#define HI3516CV300_UART2_CLK		3
+#define HI3516CV300_SPI0_CLK		4
+#define HI3516CV300_SPI1_CLK		5
+#define HI3516CV300_FMC_CLK		6
+#define HI3516CV300_MMC0_CLK		7
+#define HI3516CV300_MMC1_CLK		8
+#define HI3516CV300_MMC2_CLK		9
+#define HI3516CV300_MMC3_CLK		10
+#define HI3516CV300_ETH_CLK		11
+#define HI3516CV300_ETH_MACIF_CLK	12
+#define HI3516CV300_DMAC_CLK		13
+#define HI3516CV300_PWM_CLK		14
+#define HI3516CV300_USB2_BUS_CLK	15
+#define HI3516CV300_USB2_OHCI48M_CLK	16
+#define HI3516CV300_USB2_OHCI12M_CLK	17
+#define HI3516CV300_USB2_OTG_UTMI_CLK	18
+#define HI3516CV300_USB2_HST_PHY_CLK	19
+#define HI3516CV300_USB2_UTMI0_CLK	20
+#define HI3516CV300_USB2_PHY_CLK	21
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_WDT_CLK		1
+
+#endif	/* __DTS_HI3516CV300_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/hi3519-clock.h

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FMC_CLK			1
+#define HI3519_SPI0_CLK			2
+#define HI3519_SPI1_CLK			3
+#define HI3519_SPI2_CLK			4
+#define HI3519_UART0_CLK		5
+#define HI3519_UART1_CLK		6
+#define HI3519_UART2_CLK		7
+#define HI3519_UART3_CLK		8
+#define HI3519_UART4_CLK		9
+#define HI3519_PWM_CLK			10
+#define HI3519_DMA_CLK			11
+#define HI3519_IR_CLK			12
+#define HI3519_ETH_PHY_CLK		13
+#define HI3519_ETH_MAC_CLK		14
+#define HI3519_ETH_MACIF_CLK		15
+#define HI3519_USB2_BUS_CLK		16
+#define HI3519_USB2_PORT_CLK		17
+#define HI3519_USB3_CLK			18
+
+#endif	/* __DTS_HI3519_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/hi3559av100-clock.h

@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */
+/*
+ * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ */
+
+#ifndef __DTS_HI3559AV100_CLOCK_H
+#define __DTS_HI3559AV100_CLOCK_H
+
+/*  fixed   rate    */
+#define HI3559AV100_FIXED_1188M     1
+#define HI3559AV100_FIXED_1000M     2
+#define HI3559AV100_FIXED_842M      3
+#define HI3559AV100_FIXED_792M      4
+#define HI3559AV100_FIXED_750M      5
+#define HI3559AV100_FIXED_710M      6
+#define HI3559AV100_FIXED_680M      7
+#define HI3559AV100_FIXED_667M      8
+#define HI3559AV100_FIXED_631M      9
+#define HI3559AV100_FIXED_600M      10
+#define HI3559AV100_FIXED_568M      11
+#define HI3559AV100_FIXED_500M      12
+#define HI3559AV100_FIXED_475M      13
+#define HI3559AV100_FIXED_428M      14
+#define HI3559AV100_FIXED_400M      15
+#define HI3559AV100_FIXED_396M      16
+#define HI3559AV100_FIXED_300M      17
+#define HI3559AV100_FIXED_250M      18
+#define HI3559AV100_FIXED_198M      19
+#define HI3559AV100_FIXED_187p5M    20
+#define HI3559AV100_FIXED_150M      21
+#define HI3559AV100_FIXED_148p5M    22
+#define HI3559AV100_FIXED_125M      23
+#define HI3559AV100_FIXED_107M      24
+#define HI3559AV100_FIXED_100M      25
+#define HI3559AV100_FIXED_99M       26
+#define HI3559AV100_FIXED_74p25M    27
+#define HI3559AV100_FIXED_72M       28
+#define HI3559AV100_FIXED_60M       29
+#define HI3559AV100_FIXED_54M       30
+#define HI3559AV100_FIXED_50M       31
+#define HI3559AV100_FIXED_49p5M     32
+#define HI3559AV100_FIXED_37p125M   33
+#define HI3559AV100_FIXED_36M       34
+#define HI3559AV100_FIXED_32p4M     35
+#define HI3559AV100_FIXED_27M       36
+#define HI3559AV100_FIXED_25M       37
+#define HI3559AV100_FIXED_24M       38
+#define HI3559AV100_FIXED_12M       39
+#define HI3559AV100_FIXED_3M        40
+#define HI3559AV100_FIXED_1p6M      41
+#define HI3559AV100_FIXED_400K      42
+#define HI3559AV100_FIXED_100K      43
+#define HI3559AV100_FIXED_200M      44
+#define HI3559AV100_FIXED_75M       75
+
+#define HI3559AV100_I2C0_CLK    50
+#define HI3559AV100_I2C1_CLK    51
+#define HI3559AV100_I2C2_CLK    52
+#define HI3559AV100_I2C3_CLK    53
+#define HI3559AV100_I2C4_CLK    54
+#define HI3559AV100_I2C5_CLK    55
+#define HI3559AV100_I2C6_CLK    56
+#define HI3559AV100_I2C7_CLK    57
+#define HI3559AV100_I2C8_CLK    58
+#define HI3559AV100_I2C9_CLK    59
+#define HI3559AV100_I2C10_CLK   60
+#define HI3559AV100_I2C11_CLK   61
+
+#define HI3559AV100_SPI0_CLK    62
+#define HI3559AV100_SPI1_CLK    63
+#define HI3559AV100_SPI2_CLK    64
+#define HI3559AV100_SPI3_CLK    65
+#define HI3559AV100_SPI4_CLK    66
+#define HI3559AV100_SPI5_CLK    67
+#define HI3559AV100_SPI6_CLK    68
+
+#define HI3559AV100_EDMAC_CLK     69
+#define HI3559AV100_EDMAC_AXICLK  70
+#define HI3559AV100_EDMAC1_CLK    71
+#define HI3559AV100_EDMAC1_AXICLK 72
+#define HI3559AV100_VDMAC_CLK     73
+
+/*  mux clocks  */
+#define HI3559AV100_FMC_MUX     80
+#define HI3559AV100_SYSAPB_MUX  81
+#define HI3559AV100_UART_MUX    82
+#define HI3559AV100_SYSBUS_MUX  83
+#define HI3559AV100_A73_MUX     84
+#define HI3559AV100_MMC0_MUX    85
+#define HI3559AV100_MMC1_MUX    86
+#define HI3559AV100_MMC2_MUX    87
+#define HI3559AV100_MMC3_MUX    88
+
+/*  gate    clocks  */
+#define HI3559AV100_FMC_CLK     90
+#define HI3559AV100_UART0_CLK   91
+#define HI3559AV100_UART1_CLK   92
+#define HI3559AV100_UART2_CLK   93
+#define HI3559AV100_UART3_CLK   94
+#define HI3559AV100_UART4_CLK   95
+#define HI3559AV100_MMC0_CLK    96
+#define HI3559AV100_MMC1_CLK    97
+#define HI3559AV100_MMC2_CLK    98
+#define HI3559AV100_MMC3_CLK    99
+
+#define HI3559AV100_ETH_CLK         100
+#define HI3559AV100_ETH_MACIF_CLK   101
+#define HI3559AV100_ETH1_CLK        102
+#define HI3559AV100_ETH1_MACIF_CLK  103
+
+/*  complex */
+#define HI3559AV100_MAC0_CLK                110
+#define HI3559AV100_MAC1_CLK                111
+#define HI3559AV100_SATA_CLK                112
+#define HI3559AV100_USB_CLK                 113
+#define HI3559AV100_USB1_CLK                114
+
+/* pll clocks */
+#define HI3559AV100_APLL_CLK                250
+#define HI3559AV100_GPLL_CLK                251
+
+#define HI3559AV100_CRG_NR_CLKS	            256
+
+#define HI3559AV100_SHUB_SOURCE_SOC_24M	    0
+#define HI3559AV100_SHUB_SOURCE_SOC_200M    1
+#define HI3559AV100_SHUB_SOURCE_SOC_300M    2
+#define HI3559AV100_SHUB_SOURCE_PLL         3
+#define HI3559AV100_SHUB_SOURCE_CLK         4
+
+#define HI3559AV100_SHUB_I2C0_CLK           10
+#define HI3559AV100_SHUB_I2C1_CLK           11
+#define HI3559AV100_SHUB_I2C2_CLK           12
+#define HI3559AV100_SHUB_I2C3_CLK           13
+#define HI3559AV100_SHUB_I2C4_CLK           14
+#define HI3559AV100_SHUB_I2C5_CLK           15
+#define HI3559AV100_SHUB_I2C6_CLK           16
+#define HI3559AV100_SHUB_I2C7_CLK           17
+
+#define HI3559AV100_SHUB_SPI_SOURCE_CLK     20
+#define HI3559AV100_SHUB_SPI4_SOURCE_CLK    21
+#define HI3559AV100_SHUB_SPI0_CLK           22
+#define HI3559AV100_SHUB_SPI1_CLK           23
+#define HI3559AV100_SHUB_SPI2_CLK           24
+#define HI3559AV100_SHUB_SPI3_CLK           25
+#define HI3559AV100_SHUB_SPI4_CLK           26
+
+#define HI3559AV100_SHUB_UART_CLK_32K       30
+#define HI3559AV100_SHUB_UART_SOURCE_CLK    31
+#define HI3559AV100_SHUB_UART_DIV_CLK       32
+#define HI3559AV100_SHUB_UART0_CLK          33
+#define HI3559AV100_SHUB_UART1_CLK          34
+#define HI3559AV100_SHUB_UART2_CLK          35
+#define HI3559AV100_SHUB_UART3_CLK          36
+#define HI3559AV100_SHUB_UART4_CLK          37
+#define HI3559AV100_SHUB_UART5_CLK          38
+#define HI3559AV100_SHUB_UART6_CLK          39
+
+#define HI3559AV100_SHUB_EDMAC_CLK          40
+
+#define HI3559AV100_SHUB_NR_CLKS            50
+
+#endif  /* __DTS_HI3559AV100_CLOCK_H */
+

linux-7.2.3/include/dt-bindings/clock/hi3620-clock.h

@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *	   Xin Li <li.xin@linaro.org>
+ */
+
+#ifndef __DTS_HI3620_CLOCK_H
+#define __DTS_HI3620_CLOCK_H
+
+#define HI3620_NONE_CLOCK	0
+
+/* fixed rate & fixed factor clocks */
+#define HI3620_OSC32K		1
+#define HI3620_OSC26M		2
+#define HI3620_PCLK		3
+#define HI3620_PLL_ARM0		4
+#define HI3620_PLL_ARM1		5
+#define HI3620_PLL_PERI		6
+#define HI3620_PLL_USB		7
+#define HI3620_PLL_HDMI		8
+#define HI3620_PLL_GPU		9
+#define HI3620_RCLK_TCXO	10
+#define HI3620_RCLK_CFGAXI	11
+#define HI3620_RCLK_PICO	12
+
+/* mux clocks */
+#define HI3620_TIMER0_MUX	32
+#define HI3620_TIMER1_MUX	33
+#define HI3620_TIMER2_MUX	34
+#define HI3620_TIMER3_MUX	35
+#define HI3620_TIMER4_MUX	36
+#define HI3620_TIMER5_MUX	37
+#define HI3620_TIMER6_MUX	38
+#define HI3620_TIMER7_MUX	39
+#define HI3620_TIMER8_MUX	40
+#define HI3620_TIMER9_MUX	41
+#define HI3620_UART0_MUX	42
+#define HI3620_UART1_MUX	43
+#define HI3620_UART2_MUX	44
+#define HI3620_UART3_MUX	45
+#define HI3620_UART4_MUX	46
+#define HI3620_SPI0_MUX		47
+#define HI3620_SPI1_MUX		48
+#define HI3620_SPI2_MUX		49
+#define HI3620_SAXI_MUX		50
+#define HI3620_PWM0_MUX		51
+#define HI3620_PWM1_MUX		52
+#define HI3620_SD_MUX		53
+#define HI3620_MMC1_MUX		54
+#define HI3620_MMC1_MUX2	55
+#define HI3620_G2D_MUX		56
+#define HI3620_VENC_MUX		57
+#define HI3620_VDEC_MUX		58
+#define HI3620_VPP_MUX		59
+#define HI3620_EDC0_MUX		60
+#define HI3620_LDI0_MUX		61
+#define HI3620_EDC1_MUX		62
+#define HI3620_LDI1_MUX		63
+#define HI3620_RCLK_HSIC	64
+#define HI3620_MMC2_MUX		65
+#define HI3620_MMC3_MUX		66
+
+/* divider clocks */
+#define HI3620_SHAREAXI_DIV	128
+#define HI3620_CFGAXI_DIV	129
+#define HI3620_SD_DIV		130
+#define HI3620_MMC1_DIV		131
+#define HI3620_HSIC_DIV		132
+#define HI3620_MMC2_DIV		133
+#define HI3620_MMC3_DIV		134
+
+/* gate clocks */
+#define HI3620_TIMERCLK01	160
+#define HI3620_TIMER_RCLK01	161
+#define HI3620_TIMERCLK23	162
+#define HI3620_TIMER_RCLK23	163
+#define HI3620_TIMERCLK45	164
+#define HI3620_TIMERCLK67	165
+#define HI3620_TIMERCLK89	166
+#define HI3620_RTCCLK		167
+#define HI3620_KPC_CLK		168
+#define HI3620_GPIOCLK0		169
+#define HI3620_GPIOCLK1		170
+#define HI3620_GPIOCLK2		171
+#define HI3620_GPIOCLK3		172
+#define HI3620_GPIOCLK4		173
+#define HI3620_GPIOCLK5		174
+#define HI3620_GPIOCLK6		175
+#define HI3620_GPIOCLK7		176
+#define HI3620_GPIOCLK8		177
+#define HI3620_GPIOCLK9		178
+#define HI3620_GPIOCLK10	179
+#define HI3620_GPIOCLK11	180
+#define HI3620_GPIOCLK12	181
+#define HI3620_GPIOCLK13	182
+#define HI3620_GPIOCLK14	183
+#define HI3620_GPIOCLK15	184
+#define HI3620_GPIOCLK16	185
+#define HI3620_GPIOCLK17	186
+#define HI3620_GPIOCLK18	187
+#define HI3620_GPIOCLK19	188
+#define HI3620_GPIOCLK20	189
+#define HI3620_GPIOCLK21	190
+#define HI3620_DPHY0_CLK	191
+#define HI3620_DPHY1_CLK	192
+#define HI3620_DPHY2_CLK	193
+#define HI3620_USBPHY_CLK	194
+#define HI3620_ACP_CLK		195
+#define HI3620_PWMCLK0		196
+#define HI3620_PWMCLK1		197
+#define HI3620_UARTCLK0		198
+#define HI3620_UARTCLK1		199
+#define HI3620_UARTCLK2		200
+#define HI3620_UARTCLK3		201
+#define HI3620_UARTCLK4		202
+#define HI3620_SPICLK0		203
+#define HI3620_SPICLK1		204
+#define HI3620_SPICLK2		205
+#define HI3620_I2CCLK0		206
+#define HI3620_I2CCLK1		207
+#define HI3620_I2CCLK2		208
+#define HI3620_I2CCLK3		209
+#define HI3620_SCI_CLK		210
+#define HI3620_DDRC_PER_CLK	211
+#define HI3620_DMAC_CLK		212
+#define HI3620_USB2DVC_CLK	213
+#define HI3620_SD_CLK		214
+#define HI3620_MMC_CLK1		215
+#define HI3620_MMC_CLK2		216
+#define HI3620_MMC_CLK3		217
+#define HI3620_MCU_CLK		218
+
+#define HI3620_SD_CIUCLK	0
+#define HI3620_MMC_CIUCLK1	1
+#define HI3620_MMC_CIUCLK2	2
+#define HI3620_MMC_CIUCLK3	3
+
+#define HI3620_NR_CLKS		219
+
+#endif	/* __DTS_HI3620_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/hi3660-clock.h

@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ */
+
+#ifndef __DTS_HI3660_CLOCK_H
+#define __DTS_HI3660_CLOCK_H
+
+/* fixed rate clocks */
+#define HI3660_CLKIN_SYS		0
+#define HI3660_CLKIN_REF		1
+#define HI3660_CLK_FLL_SRC		2
+#define HI3660_CLK_PPLL0		3
+#define HI3660_CLK_PPLL1		4
+#define HI3660_CLK_PPLL2		5
+#define HI3660_CLK_PPLL3		6
+#define HI3660_CLK_SCPLL		7
+#define HI3660_PCLK			8
+#define HI3660_CLK_UART0_DBG		9
+#define HI3660_CLK_UART6		10
+#define HI3660_OSC32K			11
+#define HI3660_OSC19M			12
+#define HI3660_CLK_480M			13
+#define HI3660_CLK_INV			14
+
+/* clk in crgctrl */
+#define HI3660_FACTOR_UART3		15
+#define HI3660_CLK_FACTOR_MMC		16
+#define HI3660_CLK_GATE_I2C0		17
+#define HI3660_CLK_GATE_I2C1		18
+#define HI3660_CLK_GATE_I2C2		19
+#define HI3660_CLK_GATE_I2C6		20
+#define HI3660_CLK_DIV_SYSBUS		21
+#define HI3660_CLK_DIV_320M		22
+#define HI3660_CLK_DIV_A53		23
+#define HI3660_CLK_GATE_SPI0		24
+#define HI3660_CLK_GATE_SPI2		25
+#define HI3660_PCIEPHY_REF		26
+#define HI3660_CLK_ABB_USB		27
+#define HI3660_HCLK_GATE_SDIO0		28
+#define HI3660_HCLK_GATE_SD		29
+#define HI3660_CLK_GATE_AOMM		30
+#define HI3660_PCLK_GPIO0		31
+#define HI3660_PCLK_GPIO1		32
+#define HI3660_PCLK_GPIO2		33
+#define HI3660_PCLK_GPIO3		34
+#define HI3660_PCLK_GPIO4		35
+#define HI3660_PCLK_GPIO5		36
+#define HI3660_PCLK_GPIO6		37
+#define HI3660_PCLK_GPIO7		38
+#define HI3660_PCLK_GPIO8		39
+#define HI3660_PCLK_GPIO9		40
+#define HI3660_PCLK_GPIO10		41
+#define HI3660_PCLK_GPIO11		42
+#define HI3660_PCLK_GPIO12		43
+#define HI3660_PCLK_GPIO13		44
+#define HI3660_PCLK_GPIO14		45
+#define HI3660_PCLK_GPIO15		46
+#define HI3660_PCLK_GPIO16		47
+#define HI3660_PCLK_GPIO17		48
+#define HI3660_PCLK_GPIO18		49
+#define HI3660_PCLK_GPIO19		50
+#define HI3660_PCLK_GPIO20		51
+#define HI3660_PCLK_GPIO21		52
+#define HI3660_CLK_GATE_SPI3		53
+#define HI3660_CLK_GATE_I2C7		54
+#define HI3660_CLK_GATE_I2C3		55
+#define HI3660_CLK_GATE_SPI1		56
+#define HI3660_CLK_GATE_UART1		57
+#define HI3660_CLK_GATE_UART2		58
+#define HI3660_CLK_GATE_UART4		59
+#define HI3660_CLK_GATE_UART5		60
+#define HI3660_CLK_GATE_I2C4		61
+#define HI3660_CLK_GATE_DMAC		62
+#define HI3660_PCLK_GATE_DSS		63
+#define HI3660_ACLK_GATE_DSS		64
+#define HI3660_CLK_GATE_LDI1		65
+#define HI3660_CLK_GATE_LDI0		66
+#define HI3660_CLK_GATE_VIVOBUS		67
+#define HI3660_CLK_GATE_EDC0		68
+#define HI3660_CLK_GATE_TXDPHY0_CFG	69
+#define HI3660_CLK_GATE_TXDPHY0_REF	70
+#define HI3660_CLK_GATE_TXDPHY1_CFG	71
+#define HI3660_CLK_GATE_TXDPHY1_REF	72
+#define HI3660_ACLK_GATE_USB3OTG	73
+#define HI3660_CLK_GATE_SPI4		74
+#define HI3660_CLK_GATE_SD		75
+#define HI3660_CLK_GATE_SDIO0		76
+#define HI3660_CLK_GATE_UFS_SUBSYS	77
+#define HI3660_PCLK_GATE_DSI0		78
+#define HI3660_PCLK_GATE_DSI1		79
+#define HI3660_ACLK_GATE_PCIE		80
+#define HI3660_PCLK_GATE_PCIE_SYS       81
+#define HI3660_CLK_GATE_PCIEAUX		82
+#define HI3660_PCLK_GATE_PCIE_PHY	83
+#define HI3660_CLK_ANDGT_LDI0		84
+#define HI3660_CLK_ANDGT_LDI1		85
+#define HI3660_CLK_ANDGT_EDC0		86
+#define HI3660_CLK_GATE_UFSPHY_GT	87
+#define HI3660_CLK_ANDGT_MMC		88
+#define HI3660_CLK_ANDGT_SD		89
+#define HI3660_CLK_A53HPM_ANDGT		90
+#define HI3660_CLK_ANDGT_SDIO		91
+#define HI3660_CLK_ANDGT_UART0		92
+#define HI3660_CLK_ANDGT_UART1		93
+#define HI3660_CLK_ANDGT_UARTH		94
+#define HI3660_CLK_ANDGT_SPI		95
+#define HI3660_CLK_VIVOBUS_ANDGT	96
+#define HI3660_CLK_AOMM_ANDGT		97
+#define HI3660_CLK_320M_PLL_GT		98
+#define HI3660_AUTODIV_EMMC0BUS		99
+#define HI3660_AUTODIV_SYSBUS		100
+#define HI3660_CLK_GATE_UFSPHY_CFG	101
+#define HI3660_CLK_GATE_UFSIO_REF	102
+#define HI3660_CLK_MUX_SYSBUS		103
+#define HI3660_CLK_MUX_UART0		104
+#define HI3660_CLK_MUX_UART1		105
+#define HI3660_CLK_MUX_UARTH		106
+#define HI3660_CLK_MUX_SPI		107
+#define HI3660_CLK_MUX_I2C		108
+#define HI3660_CLK_MUX_MMC_PLL		109
+#define HI3660_CLK_MUX_LDI1		110
+#define HI3660_CLK_MUX_LDI0		111
+#define HI3660_CLK_MUX_SD_PLL		112
+#define HI3660_CLK_MUX_SD_SYS		113
+#define HI3660_CLK_MUX_EDC0		114
+#define HI3660_CLK_MUX_SDIO_SYS		115
+#define HI3660_CLK_MUX_SDIO_PLL		116
+#define HI3660_CLK_MUX_VIVOBUS		117
+#define HI3660_CLK_MUX_A53HPM		118
+#define HI3660_CLK_MUX_320M		119
+#define HI3660_CLK_MUX_IOPERI		120
+#define HI3660_CLK_DIV_UART0		121
+#define HI3660_CLK_DIV_UART1		122
+#define HI3660_CLK_DIV_UARTH		123
+#define HI3660_CLK_DIV_MMC		124
+#define HI3660_CLK_DIV_SD		125
+#define HI3660_CLK_DIV_EDC0		126
+#define HI3660_CLK_DIV_LDI0		127
+#define HI3660_CLK_DIV_SDIO		128
+#define HI3660_CLK_DIV_LDI1		129
+#define HI3660_CLK_DIV_SPI		130
+#define HI3660_CLK_DIV_VIVOBUS		131
+#define HI3660_CLK_DIV_I2C		132
+#define HI3660_CLK_DIV_UFSPHY		133
+#define HI3660_CLK_DIV_CFGBUS		134
+#define HI3660_CLK_DIV_MMC0BUS		135
+#define HI3660_CLK_DIV_MMC1BUS		136
+#define HI3660_CLK_DIV_UFSPERI		137
+#define HI3660_CLK_DIV_AOMM		138
+#define HI3660_CLK_DIV_IOPERI		139
+#define HI3660_VENC_VOLT_HOLD		140
+#define HI3660_PERI_VOLT_HOLD		141
+#define HI3660_CLK_GATE_VENC		142
+#define HI3660_CLK_GATE_VDEC		143
+#define HI3660_CLK_ANDGT_VENC		144
+#define HI3660_CLK_ANDGT_VDEC		145
+#define HI3660_CLK_MUX_VENC		146
+#define HI3660_CLK_MUX_VDEC		147
+#define HI3660_CLK_DIV_VENC		148
+#define HI3660_CLK_DIV_VDEC		149
+#define HI3660_CLK_FAC_ISP_SNCLK	150
+#define HI3660_CLK_GATE_ISP_SNCLK0	151
+#define HI3660_CLK_GATE_ISP_SNCLK1	152
+#define HI3660_CLK_GATE_ISP_SNCLK2	153
+#define HI3660_CLK_ANGT_ISP_SNCLK	154
+#define HI3660_CLK_MUX_ISP_SNCLK	155
+#define HI3660_CLK_DIV_ISP_SNCLK	156
+
+/* clk in pmuctrl */
+#define HI3660_GATE_ABB_192		0
+
+/* clk in pctrl */
+#define HI3660_GATE_UFS_TCXO_EN		0
+#define HI3660_GATE_USB_TCXO_EN		1
+
+/* clk in sctrl */
+#define HI3660_PCLK_AO_GPIO0		0
+#define HI3660_PCLK_AO_GPIO1		1
+#define HI3660_PCLK_AO_GPIO2		2
+#define HI3660_PCLK_AO_GPIO3		3
+#define HI3660_PCLK_AO_GPIO4		4
+#define HI3660_PCLK_AO_GPIO5		5
+#define HI3660_PCLK_AO_GPIO6		6
+#define HI3660_PCLK_GATE_MMBUF		7
+#define HI3660_CLK_GATE_DSS_AXI_MM	8
+#define HI3660_PCLK_MMBUF_ANDGT		9
+#define HI3660_CLK_MMBUF_PLL_ANDGT	10
+#define HI3660_CLK_FLL_MMBUF_ANDGT	11
+#define HI3660_CLK_SYS_MMBUF_ANDGT	12
+#define HI3660_CLK_GATE_PCIEPHY_GT	13
+#define HI3660_ACLK_MUX_MMBUF		14
+#define HI3660_CLK_SW_MMBUF		15
+#define HI3660_CLK_DIV_AOBUS		16
+#define HI3660_PCLK_DIV_MMBUF		17
+#define HI3660_ACLK_DIV_MMBUF		18
+#define HI3660_CLK_DIV_PCIEPHY		19
+
+/* clk in iomcu */
+#define HI3660_CLK_I2C0_IOMCU		0
+#define HI3660_CLK_I2C1_IOMCU		1
+#define HI3660_CLK_I2C2_IOMCU		2
+#define HI3660_CLK_I2C6_IOMCU		3
+#define HI3660_CLK_IOMCU_PERI0		4
+
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0	0
+#define HI3660_CLK_STUB_CLUSTER1	1
+#define HI3660_CLK_STUB_GPU		2
+#define HI3660_CLK_STUB_DDR		3
+#define HI3660_CLK_STUB_NUM		4
+
+#endif	/* __DTS_HI3660_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/hi3670-clock.h

@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree binding constants for HiSilicon Hi3670 SoC
+ *
+ * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
+ * Copyright (c) 2018 Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI3670_H
+#define __DT_BINDINGS_CLOCK_HI3670_H
+
+/* clk in stub clock */
+#define HI3670_CLK_STUB_CLUSTER0		0
+#define HI3670_CLK_STUB_CLUSTER1		1
+#define HI3670_CLK_STUB_GPU			2
+#define HI3670_CLK_STUB_DDR			3
+#define HI3670_CLK_STUB_DDR_VOTE		4
+#define HI3670_CLK_STUB_DDR_LIMIT		5
+#define HI3670_CLK_STUB_NUM			6
+
+/* clk in crg clock */
+#define HI3670_CLKIN_SYS			0
+#define HI3670_CLKIN_REF			1
+#define HI3670_CLK_FLL_SRC			2
+#define HI3670_CLK_PPLL0			3
+#define HI3670_CLK_PPLL1			4
+#define HI3670_CLK_PPLL2			5
+#define HI3670_CLK_PPLL3			6
+#define HI3670_CLK_PPLL4			7
+#define HI3670_CLK_PPLL6			8
+#define HI3670_CLK_PPLL7			9
+#define HI3670_CLK_PPLL_PCIE			10
+#define HI3670_CLK_PCIEPLL_REV			11
+#define HI3670_CLK_SCPLL			12
+#define HI3670_PCLK				13
+#define HI3670_CLK_UART0_DBG			14
+#define HI3670_CLK_UART6			15
+#define HI3670_OSC32K				16
+#define HI3670_OSC19M				17
+#define HI3670_CLK_480M				18
+#define HI3670_CLK_INVALID			19
+#define HI3670_CLK_DIV_SYSBUS			20
+#define HI3670_CLK_FACTOR_MMC			21
+#define HI3670_CLK_SD_SYS			22
+#define HI3670_CLK_SDIO_SYS			23
+#define HI3670_CLK_DIV_A53HPM			24
+#define HI3670_CLK_DIV_320M			25
+#define HI3670_PCLK_GATE_UART0			26
+#define HI3670_CLK_FACTOR_UART0			27
+#define HI3670_CLK_FACTOR_USB3PHY_PLL		28
+#define HI3670_CLK_GATE_ABB_USB			29
+#define HI3670_CLK_GATE_UFSPHY_REF		30
+#define HI3670_ICS_VOLT_HIGH			31
+#define HI3670_ICS_VOLT_MIDDLE			32
+#define HI3670_VENC_VOLT_HOLD			33
+#define HI3670_VDEC_VOLT_HOLD			34
+#define HI3670_EDC_VOLT_HOLD			35
+#define HI3670_CLK_ISP_SNCLK_FAC		36
+#define HI3670_CLK_FACTOR_RXDPHY		37
+#define HI3670_AUTODIV_SYSBUS			38
+#define HI3670_AUTODIV_EMMC0BUS			39
+#define HI3670_PCLK_ANDGT_MMC1_PCIE		40
+#define HI3670_CLK_GATE_VCODECBUS_GT		41
+#define HI3670_CLK_ANDGT_SD			42
+#define HI3670_CLK_SD_SYS_GT			43
+#define HI3670_CLK_ANDGT_SDIO			44
+#define HI3670_CLK_SDIO_SYS_GT			45
+#define HI3670_CLK_A53HPM_ANDGT			46
+#define HI3670_CLK_320M_PLL_GT			47
+#define HI3670_CLK_ANDGT_UARTH			48
+#define HI3670_CLK_ANDGT_UARTL			49
+#define HI3670_CLK_ANDGT_UART0			50
+#define HI3670_CLK_ANDGT_SPI			51
+#define HI3670_CLK_ANDGT_PCIEAXI		52
+#define HI3670_CLK_DIV_AO_ASP_GT		53
+#define HI3670_CLK_GATE_CSI_TRANS		54
+#define HI3670_CLK_GATE_DSI_TRANS		55
+#define HI3670_CLK_ANDGT_PTP			56
+#define HI3670_CLK_ANDGT_OUT0			57
+#define HI3670_CLK_ANDGT_OUT1			58
+#define HI3670_CLKGT_DP_AUDIO_PLL_AO		59
+#define HI3670_CLK_ANDGT_VDEC			60
+#define HI3670_CLK_ANDGT_VENC			61
+#define HI3670_CLK_ISP_SNCLK_ANGT		62
+#define HI3670_CLK_ANDGT_RXDPHY			63
+#define HI3670_CLK_ANDGT_ICS			64
+#define HI3670_AUTODIV_DMABUS			65
+#define HI3670_CLK_MUX_SYSBUS			66
+#define HI3670_CLK_MUX_VCODECBUS		67
+#define HI3670_CLK_MUX_SD_SYS			68
+#define HI3670_CLK_MUX_SD_PLL			69
+#define HI3670_CLK_MUX_SDIO_SYS			70
+#define HI3670_CLK_MUX_SDIO_PLL			71
+#define HI3670_CLK_MUX_A53HPM			72
+#define HI3670_CLK_MUX_320M			73
+#define HI3670_CLK_MUX_UARTH			74
+#define HI3670_CLK_MUX_UARTL			75
+#define HI3670_CLK_MUX_UART0			76
+#define HI3670_CLK_MUX_I2C			77
+#define HI3670_CLK_MUX_SPI			78
+#define HI3670_CLK_MUX_PCIEAXI			79
+#define HI3670_CLK_MUX_AO_ASP			80
+#define HI3670_CLK_MUX_VDEC			81
+#define HI3670_CLK_MUX_VENC			82
+#define HI3670_CLK_ISP_SNCLK_MUX0		83
+#define HI3670_CLK_ISP_SNCLK_MUX1		84
+#define HI3670_CLK_ISP_SNCLK_MUX2		85
+#define HI3670_CLK_MUX_RXDPHY_CFG		86
+#define HI3670_CLK_MUX_ICS			87
+#define HI3670_CLK_DIV_CFGBUS			88
+#define HI3670_CLK_DIV_MMC0BUS			89
+#define HI3670_CLK_DIV_MMC1BUS			90
+#define HI3670_PCLK_DIV_MMC1_PCIE		91
+#define HI3670_CLK_DIV_VCODECBUS		92
+#define HI3670_CLK_DIV_SD			93
+#define HI3670_CLK_DIV_SDIO			94
+#define HI3670_CLK_DIV_UARTH			95
+#define HI3670_CLK_DIV_UARTL			96
+#define HI3670_CLK_DIV_UART0			97
+#define HI3670_CLK_DIV_I2C			98
+#define HI3670_CLK_DIV_SPI			99
+#define HI3670_CLK_DIV_PCIEAXI			100
+#define HI3670_CLK_DIV_AO_ASP			101
+#define HI3670_CLK_DIV_CSI_TRANS		102
+#define HI3670_CLK_DIV_DSI_TRANS		103
+#define HI3670_CLK_DIV_PTP			104
+#define HI3670_CLK_DIV_CLKOUT0_PLL		105
+#define HI3670_CLK_DIV_CLKOUT1_PLL		106
+#define HI3670_CLKDIV_DP_AUDIO_PLL_AO		107
+#define HI3670_CLK_DIV_VDEC			108
+#define HI3670_CLK_DIV_VENC			109
+#define HI3670_CLK_ISP_SNCLK_DIV0		110
+#define HI3670_CLK_ISP_SNCLK_DIV1		111
+#define HI3670_CLK_ISP_SNCLK_DIV2		112
+#define HI3670_CLK_DIV_ICS			113
+#define HI3670_PPLL1_EN_ACPU			114
+#define HI3670_PPLL2_EN_ACPU			115
+#define HI3670_PPLL3_EN_ACPU			116
+#define HI3670_PPLL1_GT_CPU			117
+#define HI3670_PPLL2_GT_CPU			118
+#define HI3670_PPLL3_GT_CPU			119
+#define HI3670_CLK_GATE_PPLL2_MEDIA		120
+#define HI3670_CLK_GATE_PPLL3_MEDIA		121
+#define HI3670_CLK_GATE_PPLL4_MEDIA		122
+#define HI3670_CLK_GATE_PPLL6_MEDIA		123
+#define HI3670_CLK_GATE_PPLL7_MEDIA		124
+#define HI3670_PCLK_GPIO0			125
+#define HI3670_PCLK_GPIO1			126
+#define HI3670_PCLK_GPIO2			127
+#define HI3670_PCLK_GPIO3			128
+#define HI3670_PCLK_GPIO4			129
+#define HI3670_PCLK_GPIO5			130
+#define HI3670_PCLK_GPIO6			131
+#define HI3670_PCLK_GPIO7			132
+#define HI3670_PCLK_GPIO8			133
+#define HI3670_PCLK_GPIO9			134
+#define HI3670_PCLK_GPIO10			135
+#define HI3670_PCLK_GPIO11			136
+#define HI3670_PCLK_GPIO12			137
+#define HI3670_PCLK_GPIO13			138
+#define HI3670_PCLK_GPIO14			139
+#define HI3670_PCLK_GPIO15			140
+#define HI3670_PCLK_GPIO16			141
+#define HI3670_PCLK_GPIO17			142
+#define HI3670_PCLK_GPIO20			143
+#define HI3670_PCLK_GPIO21			144
+#define HI3670_PCLK_GATE_DSI0			145
+#define HI3670_PCLK_GATE_DSI1			146
+#define HI3670_HCLK_GATE_USB3OTG		147
+#define HI3670_ACLK_GATE_USB3DVFS		148
+#define HI3670_HCLK_GATE_SDIO			149
+#define HI3670_PCLK_GATE_PCIE_SYS		150
+#define HI3670_PCLK_GATE_PCIE_PHY		151
+#define HI3670_PCLK_GATE_MMC1_PCIE		152
+#define HI3670_PCLK_GATE_MMC0_IOC		153
+#define HI3670_PCLK_GATE_MMC1_IOC		154
+#define HI3670_CLK_GATE_DMAC			155
+#define HI3670_CLK_GATE_VCODECBUS2DDR		156
+#define HI3670_CLK_CCI400_BYPASS		157
+#define HI3670_CLK_GATE_CCI400			158
+#define HI3670_CLK_GATE_SD			159
+#define HI3670_HCLK_GATE_SD			160
+#define HI3670_CLK_GATE_SDIO			161
+#define HI3670_CLK_GATE_A57HPM			162
+#define HI3670_CLK_GATE_A53HPM			163
+#define HI3670_CLK_GATE_PA_A53			164
+#define HI3670_CLK_GATE_PA_A57			165
+#define HI3670_CLK_GATE_PA_G3D			166
+#define HI3670_CLK_GATE_GPUHPM			167
+#define HI3670_CLK_GATE_PERIHPM			168
+#define HI3670_CLK_GATE_AOHPM			169
+#define HI3670_CLK_GATE_UART1			170
+#define HI3670_CLK_GATE_UART4			171
+#define HI3670_PCLK_GATE_UART1			172
+#define HI3670_PCLK_GATE_UART4			173
+#define HI3670_CLK_GATE_UART2			174
+#define HI3670_CLK_GATE_UART5			175
+#define HI3670_PCLK_GATE_UART2			176
+#define HI3670_PCLK_GATE_UART5			177
+#define HI3670_CLK_GATE_UART0			178
+#define HI3670_CLK_GATE_I2C3			179
+#define HI3670_CLK_GATE_I2C4			180
+#define HI3670_CLK_GATE_I2C7			181
+#define HI3670_PCLK_GATE_I2C3			182
+#define HI3670_PCLK_GATE_I2C4			183
+#define HI3670_PCLK_GATE_I2C7			184
+#define HI3670_CLK_GATE_SPI1			185
+#define HI3670_CLK_GATE_SPI4			186
+#define HI3670_PCLK_GATE_SPI1			187
+#define HI3670_PCLK_GATE_SPI4			188
+#define HI3670_CLK_GATE_USB3OTG_REF		189
+#define HI3670_CLK_GATE_USB2PHY_REF		190
+#define HI3670_CLK_GATE_PCIEAUX			191
+#define HI3670_ACLK_GATE_PCIE			192
+#define HI3670_CLK_GATE_MMC1_PCIEAXI		193
+#define HI3670_CLK_GATE_PCIEPHY_REF		194
+#define HI3670_CLK_GATE_PCIE_DEBOUNCE		195
+#define HI3670_CLK_GATE_PCIEIO			196
+#define HI3670_CLK_GATE_PCIE_HP			197
+#define HI3670_CLK_GATE_AO_ASP			198
+#define HI3670_PCLK_GATE_PCTRL			199
+#define HI3670_CLK_CSI_TRANS_GT			200
+#define HI3670_CLK_DSI_TRANS_GT			201
+#define HI3670_CLK_GATE_PWM			202
+#define HI3670_ABB_AUDIO_EN0			203
+#define HI3670_ABB_AUDIO_EN1			204
+#define HI3670_ABB_AUDIO_GT_EN0			205
+#define HI3670_ABB_AUDIO_GT_EN1			206
+#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO		207
+#define HI3670_PERI_VOLT_HOLD			208
+#define HI3670_PERI_VOLT_MIDDLE			209
+#define HI3670_CLK_GATE_ISP_SNCLK0		210
+#define HI3670_CLK_GATE_ISP_SNCLK1		211
+#define HI3670_CLK_GATE_ISP_SNCLK2		212
+#define HI3670_CLK_GATE_RXDPHY0_CFG		213
+#define HI3670_CLK_GATE_RXDPHY1_CFG		214
+#define HI3670_CLK_GATE_RXDPHY2_CFG		215
+#define HI3670_CLK_GATE_TXDPHY0_CFG		216
+#define HI3670_CLK_GATE_TXDPHY0_REF		217
+#define HI3670_CLK_GATE_TXDPHY1_CFG		218
+#define HI3670_CLK_GATE_TXDPHY1_REF		219
+#define HI3670_CLK_GATE_MEDIA_TCXO		220
+
+/* clk in sctrl */
+#define HI3670_CLK_ANDGT_IOPERI			0
+#define HI3670_CLKANDGT_ASP_SUBSYS_PERI		1
+#define HI3670_CLK_ANGT_ASP_SUBSYS		2
+#define HI3670_CLK_MUX_UFS_SUBSYS		3
+#define HI3670_CLK_MUX_CLKOUT0			4
+#define HI3670_CLK_MUX_CLKOUT1			5
+#define HI3670_CLK_MUX_ASP_SUBSYS_PERI		6
+#define HI3670_CLK_MUX_ASP_PLL			7
+#define HI3670_CLK_DIV_AOBUS			8
+#define HI3670_CLK_DIV_UFS_SUBSYS		9
+#define HI3670_CLK_DIV_IOPERI			10
+#define HI3670_CLK_DIV_CLKOUT0_TCXO		11
+#define HI3670_CLK_DIV_CLKOUT1_TCXO		12
+#define HI3670_CLK_ASP_SUBSYS_PERI_DIV		13
+#define HI3670_CLK_DIV_ASP_SUBSYS		14
+#define HI3670_PPLL0_EN_ACPU			15
+#define HI3670_PPLL0_GT_CPU			16
+#define HI3670_CLK_GATE_PPLL0_MEDIA		17
+#define HI3670_PCLK_GPIO18			18
+#define HI3670_PCLK_GPIO19			19
+#define HI3670_CLK_GATE_SPI			20
+#define HI3670_PCLK_GATE_SPI			21
+#define HI3670_CLK_GATE_UFS_SUBSYS		22
+#define HI3670_CLK_GATE_UFSIO_REF		23
+#define HI3670_PCLK_AO_GPIO0			24
+#define HI3670_PCLK_AO_GPIO1			25
+#define HI3670_PCLK_AO_GPIO2			26
+#define HI3670_PCLK_AO_GPIO3			27
+#define HI3670_PCLK_AO_GPIO4			28
+#define HI3670_PCLK_AO_GPIO5			29
+#define HI3670_PCLK_AO_GPIO6			30
+#define HI3670_CLK_GATE_OUT0			31
+#define HI3670_CLK_GATE_OUT1			32
+#define HI3670_PCLK_GATE_SYSCNT			33
+#define HI3670_CLK_GATE_SYSCNT			34
+#define HI3670_CLK_GATE_ASP_SUBSYS_PERI		35
+#define HI3670_CLK_GATE_ASP_SUBSYS		36
+#define HI3670_CLK_GATE_ASP_TCXO		37
+#define HI3670_CLK_GATE_DP_AUDIO_PLL		38
+
+/* clk in pmuctrl */
+#define HI3670_GATE_ABB_192			0
+
+/* clk in pctrl */
+#define HI3670_GATE_UFS_TCXO_EN			0
+#define HI3670_GATE_USB_TCXO_EN			1
+
+/* clk in iomcu */
+#define HI3670_CLK_GATE_I2C0			0
+#define HI3670_CLK_GATE_I2C1			1
+#define HI3670_CLK_GATE_I2C2			2
+#define HI3670_CLK_GATE_SPI0			3
+#define HI3670_CLK_GATE_SPI2			4
+#define HI3670_CLK_GATE_UART3			5
+#define HI3670_CLK_I2C0_GATE_IOMCU		6
+#define HI3670_CLK_I2C1_GATE_IOMCU		7
+#define HI3670_CLK_I2C2_GATE_IOMCU		8
+#define HI3670_CLK_SPI0_GATE_IOMCU		9
+#define HI3670_CLK_SPI2_GATE_IOMCU		10
+#define HI3670_CLK_UART3_GATE_IOMCU		11
+#define HI3670_CLK_GATE_PERI0_IOMCU		12
+
+/* clk in media1 */
+#define HI3670_CLK_GATE_VIVOBUS_ANDGT		0
+#define HI3670_CLK_ANDGT_EDC0			1
+#define HI3670_CLK_ANDGT_LDI0			2
+#define HI3670_CLK_ANDGT_LDI1			3
+#define HI3670_CLK_MMBUF_PLL_ANDGT		4
+#define HI3670_PCLK_MMBUF_ANDGT			5
+#define HI3670_CLK_MUX_VIVOBUS			6
+#define HI3670_CLK_MUX_EDC0			7
+#define HI3670_CLK_MUX_LDI0			8
+#define HI3670_CLK_MUX_LDI1			9
+#define HI3670_CLK_SW_MMBUF			10
+#define HI3670_CLK_DIV_VIVOBUS			11
+#define HI3670_CLK_DIV_EDC0			12
+#define HI3670_CLK_DIV_LDI0			13
+#define HI3670_CLK_DIV_LDI1			14
+#define HI3670_ACLK_DIV_MMBUF			15
+#define HI3670_PCLK_DIV_MMBUF			16
+#define HI3670_ACLK_GATE_NOC_DSS		17
+#define HI3670_PCLK_GATE_NOC_DSS_CFG		18
+#define HI3670_PCLK_GATE_MMBUF_CFG		19
+#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS	20
+#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS	21
+#define HI3670_PCLK_GATE_DSS			22
+#define HI3670_ACLK_GATE_DSS			23
+#define HI3670_CLK_GATE_VIVOBUSFREQ		24
+#define HI3670_CLK_GATE_EDC0			25
+#define HI3670_CLK_GATE_LDI0			26
+#define HI3670_CLK_GATE_LDI1FREQ		27
+#define HI3670_CLK_GATE_BRG			28
+#define HI3670_ACLK_GATE_ASC			29
+#define HI3670_CLK_GATE_DSS_AXI_MM		30
+#define HI3670_CLK_GATE_MMBUF			31
+#define HI3670_PCLK_GATE_MMBUF			32
+#define HI3670_CLK_GATE_ATDIV_VIVO		33
+
+/* clk in media2 */
+#define HI3670_CLK_GATE_VDECFREQ		0
+#define HI3670_CLK_GATE_VENCFREQ		1
+#define HI3670_CLK_GATE_ICSFREQ			2
+
+#endif /* __DT_BINDINGS_CLOCK_HI3670_H */

linux-7.2.3/include/dt-bindings/clock/hi6220-clock.h

@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK	0
+
+/* fixed rate clocks */
+#define HI6220_REF32K		1
+#define HI6220_CLK_TCXO		2
+#define HI6220_MMC1_PAD		3
+#define HI6220_MMC2_PAD		4
+#define HI6220_MMC0_PAD		5
+#define HI6220_PLL_BBP		6
+#define HI6220_PLL_GPU		7
+#define HI6220_PLL1_DDR		8
+#define HI6220_PLL_SYS		9
+#define HI6220_PLL_SYS_MEDIA	10
+#define HI6220_DDR_SRC		11
+#define HI6220_PLL_MEDIA	12
+#define HI6220_PLL_DDR		13
+
+/* fixed factor clocks */
+#define HI6220_300M		14
+#define HI6220_150M		15
+#define HI6220_PICOPHY_SRC	16
+#define HI6220_MMC0_SRC_SEL	17
+#define HI6220_MMC1_SRC_SEL	18
+#define HI6220_MMC2_SRC_SEL	19
+#define HI6220_VPU_CODEC	20
+#define HI6220_MMC0_SMP		21
+#define HI6220_MMC1_SMP		22
+#define HI6220_MMC2_SMP		23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK	24
+#define HI6220_WDT1_PCLK	25
+#define HI6220_WDT2_PCLK	26
+#define HI6220_TIMER0_PCLK	27
+#define HI6220_TIMER1_PCLK	28
+#define HI6220_TIMER2_PCLK	29
+#define HI6220_TIMER3_PCLK	30
+#define HI6220_TIMER4_PCLK	31
+#define HI6220_TIMER5_PCLK	32
+#define HI6220_TIMER6_PCLK	33
+#define HI6220_TIMER7_PCLK	34
+#define HI6220_TIMER8_PCLK	35
+#define HI6220_UART0_PCLK	36
+#define HI6220_RTC0_PCLK	37
+#define HI6220_RTC1_PCLK	38
+#define HI6220_AO_NR_CLKS	39
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK		1
+#define HI6220_MMC0_CIUCLK	2
+#define HI6220_MMC1_CLK		3
+#define HI6220_MMC1_CIUCLK	4
+#define HI6220_MMC2_CLK		5
+#define HI6220_MMC2_CIUCLK	6
+#define HI6220_USBOTG_HCLK	7
+#define HI6220_CLK_PICOPHY	8
+#define HI6220_HIFI		9
+#define HI6220_DACODEC_PCLK	10
+#define HI6220_EDMAC_ACLK	11
+#define HI6220_CS_ATB		12
+#define HI6220_I2C0_CLK		13
+#define HI6220_I2C1_CLK		14
+#define HI6220_I2C2_CLK		15
+#define HI6220_I2C3_CLK		16
+#define HI6220_UART1_PCLK	17
+#define HI6220_UART2_PCLK	18
+#define HI6220_UART3_PCLK	19
+#define HI6220_UART4_PCLK	20
+#define HI6220_SPI_CLK		21
+#define HI6220_TSENSOR_CLK	22
+#define HI6220_MMU_CLK		23
+#define HI6220_HIFI_SEL		24
+#define HI6220_MMC0_SYSPLL	25
+#define HI6220_MMC1_SYSPLL	26
+#define HI6220_MMC2_SYSPLL	27
+#define HI6220_MMC0_SEL		28
+#define HI6220_MMC1_SEL		29
+#define HI6220_BBPPLL_SEL	30
+#define HI6220_MEDIA_PLL_SRC	31
+#define HI6220_MMC2_SEL		32
+#define HI6220_CS_ATB_SYSPLL	33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC		34
+#define HI6220_MMC0_SMP_IN	35
+#define HI6220_MMC1_SRC		36
+#define HI6220_MMC1_SMP_IN	37
+#define HI6220_MMC2_SRC		38
+#define HI6220_MMC2_SMP_IN	39
+#define HI6220_HIFI_SRC		40
+#define HI6220_UART1_SRC	41
+#define HI6220_UART2_SRC	42
+#define HI6220_UART3_SRC	43
+#define HI6220_UART4_SRC	44
+#define HI6220_MMC0_MUX0	45
+#define HI6220_MMC1_MUX0	46
+#define HI6220_MMC2_MUX0	47
+#define HI6220_MMC0_MUX1	48
+#define HI6220_MMC1_MUX1	49
+#define HI6220_MMC2_MUX1	50
+
+/* divider clocks */
+#define HI6220_CLK_BUS		51
+#define HI6220_MMC0_DIV		52
+#define HI6220_MMC1_DIV		53
+#define HI6220_MMC2_DIV		54
+#define HI6220_HIFI_DIV		55
+#define HI6220_BBPPLL0_DIV	56
+#define HI6220_CS_DAPB		57
+#define HI6220_CS_ATB_DIV	58
+
+/* gate clock */
+#define HI6220_DAPB_CLK		59
+
+#define HI6220_SYS_NR_CLKS	60
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK		1
+#define HI6220_G3D_PCLK		2
+#define HI6220_ACLK_CODEC_VPU	3
+#define HI6220_ISP_SCLK		4
+#define HI6220_ADE_CORE		5
+#define HI6220_MED_MMU		6
+#define HI6220_CFG_CSI4PHY	7
+#define HI6220_CFG_CSI2PHY	8
+#define HI6220_ISP_SCLK_GATE	9
+#define HI6220_ISP_SCLK_GATE1	10
+#define HI6220_ADE_CORE_GATE	11
+#define HI6220_CODEC_VPU_GATE	12
+#define HI6220_MED_SYSPLL	13
+
+/* mux clocks */
+#define HI6220_1440_1200	14
+#define HI6220_1000_1200	15
+#define HI6220_1000_1440	16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG	17
+#define HI6220_ISP_SCLK_SRC	18
+#define HI6220_ISP_SCLK1	19
+#define HI6220_ADE_CORE_SRC	20
+#define HI6220_ADE_PIX_SRC	21
+#define HI6220_G3D_CLK		22
+#define HI6220_CODEC_VPU_SRC	23
+
+#define HI6220_MEDIA_NR_CLKS	24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE	1
+#define HI6220_PLL1_DDR_GATE	2
+#define HI6220_PLL_DDR_GATE	3
+#define HI6220_PLL_MEDIA_GATE	4
+#define HI6220_PLL0_BBP_GATE	5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC		6
+#define HI6220_DDRC_AXI1	7
+
+#define HI6220_POWER_NR_CLKS	8
+
+/* clk in Hi6220 acpu sctrl */
+#define HI6220_ACPU_SFT_AT_S		0
+
+#endif

linux-7.2.3/include/dt-bindings/clock/hip04-clock.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ */
+
+#ifndef __DTS_HIP04_CLOCK_H
+#define __DTS_HIP04_CLOCK_H
+
+#define HIP04_NONE_CLOCK	0
+
+/* fixed rate & fixed factor clocks */
+#define HIP04_OSC50M		1
+#define HIP04_CLK_50M		2
+#define HIP04_CLK_168M		3
+
+#define HIP04_NR_CLKS		64
+
+#endif	/* __DTS_HIP04_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/histb-clock.h

@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK			0
+#define HISTB_APB_CLK			1
+#define HISTB_AHB_CLK			2
+#define HISTB_UART1_CLK			3
+#define HISTB_UART2_CLK			4
+#define HISTB_UART3_CLK			5
+#define HISTB_I2C0_CLK			6
+#define HISTB_I2C1_CLK			7
+#define HISTB_I2C2_CLK			8
+#define HISTB_I2C3_CLK			9
+#define HISTB_I2C4_CLK			10
+#define HISTB_I2C5_CLK			11
+#define HISTB_SPI0_CLK			12
+#define HISTB_SPI1_CLK			13
+#define HISTB_SPI2_CLK			14
+#define HISTB_SCI_CLK			15
+#define HISTB_FMC_CLK			16
+#define HISTB_MMC_BIU_CLK		17
+#define HISTB_MMC_CIU_CLK		18
+#define HISTB_MMC_DRV_CLK		19
+#define HISTB_MMC_SAMPLE_CLK		20
+#define HISTB_SDIO0_BIU_CLK		21
+#define HISTB_SDIO0_CIU_CLK		22
+#define HISTB_SDIO0_DRV_CLK		23
+#define HISTB_SDIO0_SAMPLE_CLK		24
+#define HISTB_PCIE_AUX_CLK		25
+#define HISTB_PCIE_PIPE_CLK		26
+#define HISTB_PCIE_SYS_CLK		27
+#define HISTB_PCIE_BUS_CLK		28
+#define HISTB_ETH0_MAC_CLK		29
+#define HISTB_ETH0_MACIF_CLK		30
+#define HISTB_ETH1_MAC_CLK		31
+#define HISTB_ETH1_MACIF_CLK		32
+#define HISTB_COMBPHY1_CLK		33
+#define HISTB_USB2_BUS_CLK		34
+#define HISTB_USB2_PHY_CLK		35
+#define HISTB_USB2_UTMI_CLK		36
+#define HISTB_USB2_12M_CLK		37
+#define HISTB_USB2_48M_CLK		38
+#define HISTB_USB2_OTG_UTMI_CLK		39
+#define HISTB_USB2_PHY1_REF_CLK		40
+#define HISTB_USB2_PHY2_REF_CLK		41
+#define HISTB_COMBPHY0_CLK		42
+#define HISTB_USB3_BUS_CLK		43
+#define HISTB_USB3_UTMI_CLK		44
+#define HISTB_USB3_PIPE_CLK		45
+#define HISTB_USB3_SUSPEND_CLK		46
+#define HISTB_USB3_BUS_CLK1		47
+#define HISTB_USB3_UTMI_CLK1		48
+#define HISTB_USB3_PIPE_CLK1		49
+#define HISTB_USB3_SUSPEND_CLK1		50
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK			1
+#define HISTB_IR_CLK			2
+#define HISTB_TIMER01_CLK		3
+#define HISTB_LEDC_CLK			4
+#define HISTB_UART0_CLK			5
+#define HISTB_LSADC_CLK			6
+
+#endif	/* __DTS_HISTB_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/hix5hd2-clock.h

@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ */
+
+#ifndef __DTS_HIX5HD2_CLOCK_H
+#define __DTS_HIX5HD2_CLOCK_H
+
+/* fixed rate */
+#define HIX5HD2_FIXED_1200M		1
+#define HIX5HD2_FIXED_400M		2
+#define HIX5HD2_FIXED_48M		3
+#define HIX5HD2_FIXED_24M		4
+#define HIX5HD2_FIXED_600M		5
+#define HIX5HD2_FIXED_300M		6
+#define HIX5HD2_FIXED_75M		7
+#define HIX5HD2_FIXED_200M		8
+#define HIX5HD2_FIXED_100M		9
+#define HIX5HD2_FIXED_40M		10
+#define HIX5HD2_FIXED_150M		11
+#define HIX5HD2_FIXED_1728M		12
+#define HIX5HD2_FIXED_28P8M		13
+#define HIX5HD2_FIXED_432M		14
+#define HIX5HD2_FIXED_345P6M		15
+#define HIX5HD2_FIXED_288M		16
+#define HIX5HD2_FIXED_60M		17
+#define HIX5HD2_FIXED_750M		18
+#define HIX5HD2_FIXED_500M		19
+#define HIX5HD2_FIXED_54M		20
+#define HIX5HD2_FIXED_27M		21
+#define HIX5HD2_FIXED_1500M		22
+#define HIX5HD2_FIXED_375M		23
+#define HIX5HD2_FIXED_187M		24
+#define HIX5HD2_FIXED_250M		25
+#define HIX5HD2_FIXED_125M		26
+#define HIX5HD2_FIXED_2P02M		27
+#define HIX5HD2_FIXED_50M		28
+#define HIX5HD2_FIXED_25M		29
+#define HIX5HD2_FIXED_83M		30
+
+/* mux clocks */
+#define HIX5HD2_SFC_MUX			64
+#define HIX5HD2_MMC_MUX			65
+#define HIX5HD2_FEPHY_MUX		66
+#define HIX5HD2_SD_MUX			67
+
+/* gate clocks */
+#define HIX5HD2_SFC_RST			128
+#define HIX5HD2_SFC_CLK			129
+#define HIX5HD2_MMC_CIU_CLK		130
+#define HIX5HD2_MMC_BIU_CLK		131
+#define HIX5HD2_MMC_CIU_RST		132
+#define HIX5HD2_FWD_BUS_CLK		133
+#define HIX5HD2_FWD_SYS_CLK		134
+#define HIX5HD2_MAC0_PHY_CLK		135
+#define HIX5HD2_SD_CIU_CLK		136
+#define HIX5HD2_SD_BIU_CLK		137
+#define HIX5HD2_SD_CIU_RST		138
+#define HIX5HD2_WDG0_CLK		139
+#define HIX5HD2_WDG0_RST		140
+#define HIX5HD2_I2C0_CLK		141
+#define HIX5HD2_I2C0_RST		142
+#define HIX5HD2_I2C1_CLK		143
+#define HIX5HD2_I2C1_RST		144
+#define HIX5HD2_I2C2_CLK		145
+#define HIX5HD2_I2C2_RST		146
+#define HIX5HD2_I2C3_CLK		147
+#define HIX5HD2_I2C3_RST		148
+#define HIX5HD2_I2C4_CLK		149
+#define HIX5HD2_I2C4_RST		150
+#define HIX5HD2_I2C5_CLK		151
+#define HIX5HD2_I2C5_RST		152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK		192
+#define HIX5HD2_MAC1_CLK		193
+#define HIX5HD2_SATA_CLK		194
+#define HIX5HD2_USB_CLK			195
+
+#define HIX5HD2_NR_CLKS			256
+#endif	/* __DTS_HIX5HD2_CLOCK_H */

linux-7.2.3/include/dt-bindings/clock/imx1-clock.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX1_H
+#define __DT_BINDINGS_CLOCK_IMX1_H
+
+#define IMX1_CLK_DUMMY		0
+#define IMX1_CLK_CLK32		1
+#define IMX1_CLK_CLK16M_EXT	2
+#define IMX1_CLK_CLK16M		3
+#define IMX1_CLK_CLK32_PREMULT	4
+#define IMX1_CLK_PREM		5
+#define IMX1_CLK_MPLL		6
+#define IMX1_CLK_MPLL_GATE	7
+#define IMX1_CLK_SPLL		8
+#define IMX1_CLK_SPLL_GATE	9
+#define IMX1_CLK_MCU		10
+#define IMX1_CLK_FCLK		11
+#define IMX1_CLK_HCLK		12
+#define IMX1_CLK_CLK48M		13
+#define IMX1_CLK_PER1		14
+#define IMX1_CLK_PER2		15
+#define IMX1_CLK_PER3		16
+#define IMX1_CLK_CLKO		17
+#define IMX1_CLK_UART3_GATE	18
+#define IMX1_CLK_SSI2_GATE	19
+#define IMX1_CLK_BROM_GATE	20
+#define IMX1_CLK_DMA_GATE	21
+#define IMX1_CLK_CSI_GATE	22
+#define IMX1_CLK_MMA_GATE	23
+#define IMX1_CLK_USBD_GATE	24
+#define IMX1_CLK_MAX		25
+
+#endif

linux-7.2.3/include/dt-bindings/clock/imx21-clock.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX21_H
+#define __DT_BINDINGS_CLOCK_IMX21_H
+
+#define IMX21_CLK_DUMMY			0
+#define IMX21_CLK_CKIL			1
+#define IMX21_CLK_CKIH			2
+#define IMX21_CLK_FPM			3
+#define IMX21_CLK_CKIH_DIV1P5		4
+#define IMX21_CLK_MPLL_GATE		5
+#define IMX21_CLK_SPLL_GATE		6
+#define IMX21_CLK_FPM_GATE		7
+#define IMX21_CLK_CKIH_GATE		8
+#define IMX21_CLK_MPLL_OSC_SEL		9
+#define IMX21_CLK_IPG			10
+#define IMX21_CLK_HCLK			11
+#define IMX21_CLK_MPLL_SEL		12
+#define IMX21_CLK_SPLL_SEL		13
+#define IMX21_CLK_SSI1_SEL		14
+#define IMX21_CLK_SSI2_SEL		15
+#define IMX21_CLK_USB_DIV		16
+#define IMX21_CLK_FCLK			17
+#define IMX21_CLK_MPLL			18
+#define IMX21_CLK_SPLL			19
+#define IMX21_CLK_NFC_DIV		20
+#define IMX21_CLK_SSI1_DIV		21
+#define IMX21_CLK_SSI2_DIV		22
+#define IMX21_CLK_PER1			23
+#define IMX21_CLK_PER2			24
+#define IMX21_CLK_PER3			25
+#define IMX21_CLK_PER4			26
+#define IMX21_CLK_UART1_IPG_GATE	27
+#define IMX21_CLK_UART2_IPG_GATE	28
+#define IMX21_CLK_UART3_IPG_GATE	29
+#define IMX21_CLK_UART4_IPG_GATE	30
+#define IMX21_CLK_CSPI1_IPG_GATE	31
+#define IMX21_CLK_CSPI2_IPG_GATE	32
+#define IMX21_CLK_SSI1_GATE		33
+#define IMX21_CLK_SSI2_GATE		34
+#define IMX21_CLK_SDHC1_IPG_GATE	35
+#define IMX21_CLK_SDHC2_IPG_GATE	36
+#define IMX21_CLK_GPIO_GATE		37
+#define IMX21_CLK_I2C_GATE		38
+#define IMX21_CLK_DMA_GATE		39
+#define IMX21_CLK_USB_GATE		40
+#define IMX21_CLK_EMMA_GATE		41
+#define IMX21_CLK_SSI2_BAUD_GATE	42
+#define IMX21_CLK_SSI1_BAUD_GATE	43
+#define IMX21_CLK_LCDC_IPG_GATE		44
+#define IMX21_CLK_NFC_GATE		45
+#define IMX21_CLK_LCDC_HCLK_GATE	46
+#define IMX21_CLK_PER4_GATE		47
+#define IMX21_CLK_BMI_GATE		48
+#define IMX21_CLK_USB_HCLK_GATE		49
+#define IMX21_CLK_SLCDC_GATE		50
+#define IMX21_CLK_SLCDC_HCLK_GATE	51
+#define IMX21_CLK_EMMA_HCLK_GATE	52
+#define IMX21_CLK_BROM_GATE		53
+#define IMX21_CLK_DMA_HCLK_GATE		54
+#define IMX21_CLK_CSI_HCLK_GATE		55
+#define IMX21_CLK_CSPI3_IPG_GATE	56
+#define IMX21_CLK_WDOG_GATE		57
+#define IMX21_CLK_GPT1_IPG_GATE		58
+#define IMX21_CLK_GPT2_IPG_GATE		59
+#define IMX21_CLK_GPT3_IPG_GATE		60
+#define IMX21_CLK_PWM_IPG_GATE		61
+#define IMX21_CLK_RTC_GATE		62
+#define IMX21_CLK_KPP_GATE		63
+#define IMX21_CLK_OWIRE_GATE		64
+#define IMX21_CLK_MAX			65
+
+#endif

linux-7.2.3/include/dt-bindings/clock/imx27-clock.h

@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX27_H
+#define __DT_BINDINGS_CLOCK_IMX27_H
+
+#define IMX27_CLK_DUMMY			0
+#define IMX27_CLK_CKIH			1
+#define IMX27_CLK_CKIL			2
+#define IMX27_CLK_MPLL			3
+#define IMX27_CLK_SPLL			4
+#define IMX27_CLK_MPLL_MAIN2		5
+#define IMX27_CLK_AHB			6
+#define IMX27_CLK_IPG			7
+#define IMX27_CLK_NFC_DIV		8
+#define IMX27_CLK_PER1_DIV		9
+#define IMX27_CLK_PER2_DIV		10
+#define IMX27_CLK_PER3_DIV		11
+#define IMX27_CLK_PER4_DIV		12
+#define IMX27_CLK_VPU_SEL		13
+#define IMX27_CLK_VPU_DIV		14
+#define IMX27_CLK_USB_DIV		15
+#define IMX27_CLK_CPU_SEL		16
+#define IMX27_CLK_CLKO_SEL		17
+#define IMX27_CLK_CPU_DIV		18
+#define IMX27_CLK_CLKO_DIV		19
+#define IMX27_CLK_SSI1_SEL		20
+#define IMX27_CLK_SSI2_SEL		21
+#define IMX27_CLK_SSI1_DIV		22
+#define IMX27_CLK_SSI2_DIV		23
+#define IMX27_CLK_CLKO_EN		24
+#define IMX27_CLK_SSI2_IPG_GATE		25
+#define IMX27_CLK_SSI1_IPG_GATE		26
+#define IMX27_CLK_SLCDC_IPG_GATE	27
+#define IMX27_CLK_SDHC3_IPG_GATE	28
+#define IMX27_CLK_SDHC2_IPG_GATE	29
+#define IMX27_CLK_SDHC1_IPG_GATE	30
+#define IMX27_CLK_SCC_IPG_GATE		31
+#define IMX27_CLK_SAHARA_IPG_GATE	32
+#define IMX27_CLK_RTC_IPG_GATE		33
+#define IMX27_CLK_PWM_IPG_GATE		34
+#define IMX27_CLK_OWIRE_IPG_GATE	35
+#define IMX27_CLK_LCDC_IPG_GATE		36
+#define IMX27_CLK_KPP_IPG_GATE		37
+#define IMX27_CLK_IIM_IPG_GATE		38
+#define IMX27_CLK_I2C2_IPG_GATE		39
+#define IMX27_CLK_I2C1_IPG_GATE		40
+#define IMX27_CLK_GPT6_IPG_GATE		41
+#define IMX27_CLK_GPT5_IPG_GATE		42
+#define IMX27_CLK_GPT4_IPG_GATE		43
+#define IMX27_CLK_GPT3_IPG_GATE		44
+#define IMX27_CLK_GPT2_IPG_GATE		45
+#define IMX27_CLK_GPT1_IPG_GATE		46
+#define IMX27_CLK_GPIO_IPG_GATE		47
+#define IMX27_CLK_FEC_IPG_GATE		48
+#define IMX27_CLK_EMMA_IPG_GATE		49
+#define IMX27_CLK_DMA_IPG_GATE		50
+#define IMX27_CLK_CSPI3_IPG_GATE	51
+#define IMX27_CLK_CSPI2_IPG_GATE	52
+#define IMX27_CLK_CSPI1_IPG_GATE	53
+#define IMX27_CLK_NFC_BAUD_GATE		54
+#define IMX27_CLK_SSI2_BAUD_GATE	55
+#define IMX27_CLK_SSI1_BAUD_GATE	56
+#define IMX27_CLK_VPU_BAUD_GATE		57
+#define IMX27_CLK_PER4_GATE		58
+#define IMX27_CLK_PER3_GATE		59
+#define IMX27_CLK_PER2_GATE		60
+#define IMX27_CLK_PER1_GATE		61
+#define IMX27_CLK_USB_AHB_GATE		62
+#define IMX27_CLK_SLCDC_AHB_GATE	63
+#define IMX27_CLK_SAHARA_AHB_GATE	64
+#define IMX27_CLK_LCDC_AHB_GATE		65
+#define IMX27_CLK_VPU_AHB_GATE		66
+#define IMX27_CLK_FEC_AHB_GATE		67
+#define IMX27_CLK_EMMA_AHB_GATE		68
+#define IMX27_CLK_EMI_AHB_GATE		69
+#define IMX27_CLK_DMA_AHB_GATE		70
+#define IMX27_CLK_CSI_AHB_GATE		71
+#define IMX27_CLK_BROM_AHB_GATE		72
+#define IMX27_CLK_ATA_AHB_GATE		73
+#define IMX27_CLK_WDOG_IPG_GATE		74
+#define IMX27_CLK_USB_IPG_GATE		75
+#define IMX27_CLK_UART6_IPG_GATE	76
+#define IMX27_CLK_UART5_IPG_GATE	77
+#define IMX27_CLK_UART4_IPG_GATE	78
+#define IMX27_CLK_UART3_IPG_GATE	79
+#define IMX27_CLK_UART2_IPG_GATE	80
+#define IMX27_CLK_UART1_IPG_GATE	81
+#define IMX27_CLK_CKIH_DIV1P5		82
+#define IMX27_CLK_FPM			83
+#define IMX27_CLK_MPLL_OSC_SEL		84
+#define IMX27_CLK_MPLL_SEL		85
+#define IMX27_CLK_SPLL_GATE		86
+#define IMX27_CLK_MSHC_DIV		87
+#define IMX27_CLK_RTIC_IPG_GATE		88
+#define IMX27_CLK_MSHC_IPG_GATE		89
+#define IMX27_CLK_RTIC_AHB_GATE		90
+#define IMX27_CLK_MSHC_BAUD_GATE	91
+#define IMX27_CLK_CKIH_GATE		92
+#define IMX27_CLK_MAX			93
+
+#endif

linux-7.2.3/include/dt-bindings/clock/imx5-clock.h

@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY			0
+#define IMX5_CLK_CKIL			1
+#define IMX5_CLK_OSC			2
+#define IMX5_CLK_CKIH1			3
+#define IMX5_CLK_CKIH2			4
+#define IMX5_CLK_AHB			5
+#define IMX5_CLK_IPG			6
+#define IMX5_CLK_AXI_A			7
+#define IMX5_CLK_AXI_B			8
+#define IMX5_CLK_UART_PRED		9
+#define IMX5_CLK_UART_ROOT		10
+#define IMX5_CLK_ESDHC_A_PRED		11
+#define IMX5_CLK_ESDHC_B_PRED		12
+#define IMX5_CLK_ESDHC_C_SEL		13
+#define IMX5_CLK_ESDHC_D_SEL		14
+#define IMX5_CLK_EMI_SEL		15
+#define IMX5_CLK_EMI_SLOW_PODF		16
+#define IMX5_CLK_NFC_PODF		17
+#define IMX5_CLK_ECSPI_PRED		18
+#define IMX5_CLK_ECSPI_PODF		19
+#define IMX5_CLK_USBOH3_PRED		20
+#define IMX5_CLK_USBOH3_PODF		21
+#define IMX5_CLK_USB_PHY_PRED		22
+#define IMX5_CLK_USB_PHY_PODF		23
+#define IMX5_CLK_CPU_PODF		24
+#define IMX5_CLK_DI_PRED		25
+#define IMX5_CLK_TVE_SEL		27
+#define IMX5_CLK_UART1_IPG_GATE		28
+#define IMX5_CLK_UART1_PER_GATE		29
+#define IMX5_CLK_UART2_IPG_GATE		30
+#define IMX5_CLK_UART2_PER_GATE		31
+#define IMX5_CLK_UART3_IPG_GATE		32
+#define IMX5_CLK_UART3_PER_GATE		33
+#define IMX5_CLK_I2C1_GATE		34
+#define IMX5_CLK_I2C2_GATE		35
+#define IMX5_CLK_GPT_IPG_GATE		36
+#define IMX5_CLK_PWM1_IPG_GATE		37
+#define IMX5_CLK_PWM1_HF_GATE		38
+#define IMX5_CLK_PWM2_IPG_GATE		39
+#define IMX5_CLK_PWM2_HF_GATE		40
+#define IMX5_CLK_GPT_HF_GATE		41
+#define IMX5_CLK_FEC_GATE		42
+#define IMX5_CLK_USBOH3_PER_GATE	43
+#define IMX5_CLK_ESDHC1_IPG_GATE	44
+#define IMX5_CLK_ESDHC2_IPG_GATE	45
+#define IMX5_CLK_ESDHC3_IPG_GATE	46
+#define IMX5_CLK_ESDHC4_IPG_GATE	47
+#define IMX5_CLK_SSI1_IPG_GATE		48
+#define IMX5_CLK_SSI2_IPG_GATE		49
+#define IMX5_CLK_SSI3_IPG_GATE		50
+#define IMX5_CLK_ECSPI1_IPG_GATE	51
+#define IMX5_CLK_ECSPI1_PER_GATE	52
+#define IMX5_CLK_ECSPI2_IPG_GATE	53
+#define IMX5_CLK_ECSPI2_PER_GATE	54
+#define IMX5_CLK_CSPI_IPG_GATE		55
+#define IMX5_CLK_SDMA_GATE		56
+#define IMX5_CLK_EMI_SLOW_GATE		57
+#define IMX5_CLK_IPU_SEL		58
+#define IMX5_CLK_IPU_GATE		59
+#define IMX5_CLK_NFC_GATE		60
+#define IMX5_CLK_IPU_DI1_GATE		61
+#define IMX5_CLK_VPU_SEL		62
+#define IMX5_CLK_VPU_GATE		63
+#define IMX5_CLK_VPU_REFERENCE_GATE	64
+#define IMX5_CLK_UART4_IPG_GATE		65
+#define IMX5_CLK_UART4_PER_GATE		66
+#define IMX5_CLK_UART5_IPG_GATE		67
+#define IMX5_CLK_UART5_PER_GATE		68
+#define IMX5_CLK_TVE_GATE		69
+#define IMX5_CLK_TVE_PRED		70
+#define IMX5_CLK_ESDHC1_PER_GATE	71
+#define IMX5_CLK_ESDHC2_PER_GATE	72
+#define IMX5_CLK_ESDHC3_PER_GATE	73
+#define IMX5_CLK_ESDHC4_PER_GATE	74
+#define IMX5_CLK_USB_PHY_GATE		75
+#define IMX5_CLK_HSI2C_GATE		76
+#define IMX5_CLK_MIPI_HSC1_GATE		77
+#define IMX5_CLK_MIPI_HSC2_GATE		78
+#define IMX5_CLK_MIPI_ESC_GATE		79
+#define IMX5_CLK_MIPI_HSP_GATE		80
+#define IMX5_CLK_LDB_DI1_DIV_3_5	81
+#define IMX5_CLK_LDB_DI1_DIV		82
+#define IMX5_CLK_LDB_DI0_DIV_3_5	83
+#define IMX5_CLK_LDB_DI0_DIV		84
+#define IMX5_CLK_LDB_DI1_GATE		85
+#define IMX5_CLK_CAN2_SERIAL_GATE	86
+#define IMX5_CLK_CAN2_IPG_GATE		87
+#define IMX5_CLK_I2C3_GATE		88
+#define IMX5_CLK_LP_APM			89
+#define IMX5_CLK_PERIPH_APM		90
+#define IMX5_CLK_MAIN_BUS		91
+#define IMX5_CLK_AHB_MAX		92
+#define IMX5_CLK_AIPS_TZ1		93
+#define IMX5_CLK_AIPS_TZ2		94
+#define IMX5_CLK_TMAX1			95
+#define IMX5_CLK_TMAX2			96
+#define IMX5_CLK_TMAX3			97
+#define IMX5_CLK_SPBA			98
+#define IMX5_CLK_UART_SEL		99
+#define IMX5_CLK_ESDHC_A_SEL		100
+#define IMX5_CLK_ESDHC_B_SEL		101
+#define IMX5_CLK_ESDHC_A_PODF		102
+#define IMX5_CLK_ESDHC_B_PODF		103
+#define IMX5_CLK_ECSPI_SEL		104
+#define IMX5_CLK_USBOH3_SEL		105
+#define IMX5_CLK_USB_PHY_SEL		106
+#define IMX5_CLK_IIM_GATE		107
+#define IMX5_CLK_USBOH3_GATE		108
+#define IMX5_CLK_EMI_FAST_GATE		109
+#define IMX5_CLK_IPU_DI0_GATE		110
+#define IMX5_CLK_GPC_DVFS		111
+#define IMX5_CLK_PLL1_SW		112
+#define IMX5_CLK_PLL2_SW		113
+#define IMX5_CLK_PLL3_SW		114
+#define IMX5_CLK_IPU_DI0_SEL		115
+#define IMX5_CLK_IPU_DI1_SEL		116
+#define IMX5_CLK_TVE_EXT_SEL		117
+#define IMX5_CLK_MX51_MIPI		118
+#define IMX5_CLK_PLL4_SW		119
+#define IMX5_CLK_LDB_DI1_SEL		120
+#define IMX5_CLK_DI_PLL4_PODF		121
+#define IMX5_CLK_LDB_DI0_SEL		122
+#define IMX5_CLK_LDB_DI0_GATE		123
+#define IMX5_CLK_USB_PHY1_GATE		124
+#define IMX5_CLK_USB_PHY2_GATE		125
+#define IMX5_CLK_PER_LP_APM		126
+#define IMX5_CLK_PER_PRED1		127
+#define IMX5_CLK_PER_PRED2		128
+#define IMX5_CLK_PER_PODF		129
+#define IMX5_CLK_PER_ROOT		130
+#define IMX5_CLK_SSI_APM		131
+#define IMX5_CLK_SSI1_ROOT_SEL		132
+#define IMX5_CLK_SSI2_ROOT_SEL		133
+#define IMX5_CLK_SSI3_ROOT_SEL		134
+#define IMX5_CLK_SSI_EXT1_SEL		135
+#define IMX5_CLK_SSI_EXT2_SEL		136
+#define IMX5_CLK_SSI_EXT1_COM_SEL	137
+#define IMX5_CLK_SSI_EXT2_COM_SEL	138
+#define IMX5_CLK_SSI1_ROOT_PRED		139
+#define IMX5_CLK_SSI1_ROOT_PODF		140
+#define IMX5_CLK_SSI2_ROOT_PRED		141
+#define IMX5_CLK_SSI2_ROOT_PODF		142
+#define IMX5_CLK_SSI_EXT1_PRED		143
+#define IMX5_CLK_SSI_EXT1_PODF		144
+#define IMX5_CLK_SSI_EXT2_PRED		145
+#define IMX5_CLK_SSI_EXT2_PODF		146
+#define IMX5_CLK_SSI1_ROOT_GATE		147
+#define IMX5_CLK_SSI2_ROOT_GATE		148
+#define IMX5_CLK_SSI3_ROOT_GATE		149
+#define IMX5_CLK_SSI_EXT1_GATE		150
+#define IMX5_CLK_SSI_EXT2_GATE		151
+#define IMX5_CLK_EPIT1_IPG_GATE		152
+#define IMX5_CLK_EPIT1_HF_GATE		153
+#define IMX5_CLK_EPIT2_IPG_GATE		154
+#define IMX5_CLK_EPIT2_HF_GATE		155
+#define IMX5_CLK_CAN_SEL		156
+#define IMX5_CLK_CAN1_SERIAL_GATE	157
+#define IMX5_CLK_CAN1_IPG_GATE		158
+#define IMX5_CLK_OWIRE_GATE		159
+#define IMX5_CLK_GPU3D_SEL		160
+#define IMX5_CLK_GPU2D_SEL		161
+#define IMX5_CLK_GPU3D_GATE		162
+#define IMX5_CLK_GPU2D_GATE		163
+#define IMX5_CLK_GARB_GATE		164
+#define IMX5_CLK_CKO1_SEL		165
+#define IMX5_CLK_CKO1_PODF		166
+#define IMX5_CLK_CKO1			167
+#define IMX5_CLK_CKO2_SEL		168
+#define IMX5_CLK_CKO2_PODF		169
+#define IMX5_CLK_CKO2			170
+#define IMX5_CLK_SRTC_GATE		171
+#define IMX5_CLK_PATA_GATE		172
+#define IMX5_CLK_SATA_GATE		173
+#define IMX5_CLK_SPDIF_XTAL_SEL		174
+#define IMX5_CLK_SPDIF0_SEL		175
+#define IMX5_CLK_SPDIF1_SEL		176
+#define IMX5_CLK_SPDIF0_PRED		177
+#define IMX5_CLK_SPDIF0_PODF		178
+#define IMX5_CLK_SPDIF1_PRED		179
+#define IMX5_CLK_SPDIF1_PODF		180
+#define IMX5_CLK_SPDIF0_COM_SEL		181
+#define IMX5_CLK_SPDIF1_COM_SEL		182
+#define IMX5_CLK_SPDIF0_GATE		183
+#define IMX5_CLK_SPDIF1_GATE		184
+#define IMX5_CLK_SPDIF_IPG_GATE		185
+#define IMX5_CLK_OCRAM			186
+#define IMX5_CLK_SAHARA_IPG_GATE	187
+#define IMX5_CLK_SATA_REF		188
+#define IMX5_CLK_STEP_SEL		189
+#define IMX5_CLK_CPU_PODF_SEL		190
+#define IMX5_CLK_ARM			191
+#define IMX5_CLK_FIRI_PRED		192
+#define IMX5_CLK_FIRI_SEL		193
+#define IMX5_CLK_FIRI_PODF		194
+#define IMX5_CLK_FIRI_SERIAL_GATE	195
+#define IMX5_CLK_FIRI_IPG_GATE		196
+#define IMX5_CLK_CSI0_MCLK1_PRED	197
+#define IMX5_CLK_CSI0_MCLK1_SEL		198
+#define IMX5_CLK_CSI0_MCLK1_PODF	199
+#define IMX5_CLK_CSI0_MCLK1_GATE	200
+#define IMX5_CLK_IEEE1588_PRED		201
+#define IMX5_CLK_IEEE1588_SEL		202
+#define IMX5_CLK_IEEE1588_PODF		203
+#define IMX5_CLK_IEEE1588_GATE		204
+#define IMX5_CLK_SCC2_IPG_GATE		205
+#define IMX5_CLK_END			206
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */

linux-7.2.3/include/dt-bindings/clock/imx6qdl-clock.h

@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY			0
+#define IMX6QDL_CLK_CKIL			1
+#define IMX6QDL_CLK_CKIH			2
+#define IMX6QDL_CLK_OSC				3
+#define IMX6QDL_CLK_PLL2_PFD0_352M		4
+#define IMX6QDL_CLK_PLL2_PFD1_594M		5
+#define IMX6QDL_CLK_PLL2_PFD2_396M		6
+#define IMX6QDL_CLK_PLL3_PFD0_720M		7
+#define IMX6QDL_CLK_PLL3_PFD1_540M		8
+#define IMX6QDL_CLK_PLL3_PFD2_508M		9
+#define IMX6QDL_CLK_PLL3_PFD3_454M		10
+#define IMX6QDL_CLK_PLL2_198M			11
+#define IMX6QDL_CLK_PLL3_120M			12
+#define IMX6QDL_CLK_PLL3_80M			13
+#define IMX6QDL_CLK_PLL3_60M			14
+#define IMX6QDL_CLK_TWD				15
+#define IMX6QDL_CLK_STEP			16
+#define IMX6QDL_CLK_PLL1_SW			17
+#define IMX6QDL_CLK_PERIPH_PRE			18
+#define IMX6QDL_CLK_PERIPH2_PRE			19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
+#define IMX6QDL_CLK_AXI_SEL			22
+#define IMX6QDL_CLK_ESAI_SEL			23
+#define IMX6QDL_CLK_ASRC_SEL			24
+#define IMX6QDL_CLK_SPDIF_SEL			25
+#define IMX6QDL_CLK_GPU2D_AXI			26
+#define IMX6QDL_CLK_GPU3D_AXI			27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL		28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL		29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
+#define IMX6QDL_CLK_IPU1_SEL			31
+#define IMX6QDL_CLK_IPU2_SEL			32
+#define IMX6QDL_CLK_LDB_DI0_SEL			33
+#define IMX6QDL_CLK_LDB_DI1_SEL			34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
+#define IMX6QDL_CLK_IPU1_DI0_SEL		39
+#define IMX6QDL_CLK_IPU1_DI1_SEL		40
+#define IMX6QDL_CLK_IPU2_DI0_SEL		41
+#define IMX6QDL_CLK_IPU2_DI1_SEL		42
+#define IMX6QDL_CLK_HSI_TX_SEL			43
+#define IMX6QDL_CLK_PCIE_AXI_SEL		44
+#define IMX6QDL_CLK_SSI1_SEL			45
+#define IMX6QDL_CLK_SSI2_SEL			46
+#define IMX6QDL_CLK_SSI3_SEL			47
+#define IMX6QDL_CLK_USDHC1_SEL			48
+#define IMX6QDL_CLK_USDHC2_SEL			49
+#define IMX6QDL_CLK_USDHC3_SEL			50
+#define IMX6QDL_CLK_USDHC4_SEL			51
+#define IMX6QDL_CLK_ENFC_SEL			52
+#define IMX6QDL_CLK_EIM_SEL			53
+#define IMX6QDL_CLK_EIM_SLOW_SEL		54
+#define IMX6QDL_CLK_VDO_AXI_SEL			55
+#define IMX6QDL_CLK_VPU_AXI_SEL			56
+#define IMX6QDL_CLK_CKO1_SEL			57
+#define IMX6QDL_CLK_PERIPH			58
+#define IMX6QDL_CLK_PERIPH2			59
+#define IMX6QDL_CLK_PERIPH_CLK2			60
+#define IMX6QDL_CLK_PERIPH2_CLK2		61
+#define IMX6QDL_CLK_IPG				62
+#define IMX6QDL_CLK_IPG_PER			63
+#define IMX6QDL_CLK_ESAI_PRED			64
+#define IMX6QDL_CLK_ESAI_PODF			65
+#define IMX6QDL_CLK_ASRC_PRED			66
+#define IMX6QDL_CLK_ASRC_PODF			67
+#define IMX6QDL_CLK_SPDIF_PRED			68
+#define IMX6QDL_CLK_SPDIF_PODF			69
+#define IMX6QDL_CLK_CAN_ROOT			70
+#define IMX6QDL_CLK_ECSPI_ROOT			71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF		72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF		73
+#define IMX6QDL_CLK_GPU3D_SHADER		74
+#define IMX6QDL_CLK_IPU1_PODF			75
+#define IMX6QDL_CLK_IPU2_PODF			76
+#define IMX6QDL_CLK_LDB_DI0_PODF		77
+#define IMX6QDL_CLK_LDB_DI1_PODF		78
+#define IMX6QDL_CLK_IPU1_DI0_PRE		79
+#define IMX6QDL_CLK_IPU1_DI1_PRE		80
+#define IMX6QDL_CLK_IPU2_DI0_PRE		81
+#define IMX6QDL_CLK_IPU2_DI1_PRE		82
+#define IMX6QDL_CLK_HSI_TX_PODF			83
+#define IMX6QDL_CLK_SSI1_PRED			84
+#define IMX6QDL_CLK_SSI1_PODF			85
+#define IMX6QDL_CLK_SSI2_PRED			86
+#define IMX6QDL_CLK_SSI2_PODF			87
+#define IMX6QDL_CLK_SSI3_PRED			88
+#define IMX6QDL_CLK_SSI3_PODF			89
+#define IMX6QDL_CLK_UART_SERIAL_PODF		90
+#define IMX6QDL_CLK_USDHC1_PODF			91
+#define IMX6QDL_CLK_USDHC2_PODF			92
+#define IMX6QDL_CLK_USDHC3_PODF			93
+#define IMX6QDL_CLK_USDHC4_PODF			94
+#define IMX6QDL_CLK_ENFC_PRED			95
+#define IMX6QDL_CLK_ENFC_PODF			96
+#define IMX6QDL_CLK_EIM_PODF			97
+#define IMX6QDL_CLK_EIM_SLOW_PODF		98
+#define IMX6QDL_CLK_VPU_AXI_PODF		99
+#define IMX6QDL_CLK_CKO1_PODF			100
+#define IMX6QDL_CLK_AXI				101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
+#define IMX6QDL_CLK_ARM				104
+#define IMX6QDL_CLK_AHB				105
+#define IMX6QDL_CLK_APBH_DMA			106
+#define IMX6QDL_CLK_ASRC			107
+#define IMX6QDL_CLK_CAN1_IPG			108
+#define IMX6QDL_CLK_CAN1_SERIAL			109
+#define IMX6QDL_CLK_CAN2_IPG			110
+#define IMX6QDL_CLK_CAN2_SERIAL			111
+#define IMX6QDL_CLK_ECSPI1			112
+#define IMX6QDL_CLK_ECSPI2			113
+#define IMX6QDL_CLK_ECSPI3			114
+#define IMX6QDL_CLK_ECSPI4			115
+#define IMX6Q_CLK_ECSPI5			116
+#define IMX6DL_CLK_I2C4				116
+#define IMX6QDL_CLK_ENET			117
+#define IMX6QDL_CLK_ESAI_EXTAL			118
+#define IMX6QDL_CLK_GPT_IPG			119
+#define IMX6QDL_CLK_GPT_IPG_PER			120
+#define IMX6QDL_CLK_GPU2D_CORE			121
+#define IMX6QDL_CLK_GPU3D_CORE			122
+#define IMX6QDL_CLK_HDMI_IAHB			123
+#define IMX6QDL_CLK_HDMI_ISFR			124
+#define IMX6QDL_CLK_I2C1			125
+#define IMX6QDL_CLK_I2C2			126
+#define IMX6QDL_CLK_I2C3			127
+#define IMX6QDL_CLK_IIM				128
+#define IMX6QDL_CLK_ENFC			129
+#define IMX6QDL_CLK_IPU1			130
+#define IMX6QDL_CLK_IPU1_DI0			131
+#define IMX6QDL_CLK_IPU1_DI1			132
+#define IMX6QDL_CLK_IPU2			133
+#define IMX6QDL_CLK_IPU2_DI0			134
+#define IMX6QDL_CLK_LDB_DI0			135
+#define IMX6QDL_CLK_LDB_DI1			136
+#define IMX6QDL_CLK_IPU2_DI1			137
+#define IMX6QDL_CLK_HSI_TX			138
+#define IMX6QDL_CLK_MLB				139
+#define IMX6QDL_CLK_MMDC_CH0_AXI		140
+#define IMX6QDL_CLK_MMDC_CH1_AXI		141
+#define IMX6QDL_CLK_OCRAM			142
+#define IMX6QDL_CLK_OPENVG_AXI			143
+#define IMX6QDL_CLK_PCIE_AXI			144
+#define IMX6QDL_CLK_PWM1			145
+#define IMX6QDL_CLK_PWM2			146
+#define IMX6QDL_CLK_PWM3			147
+#define IMX6QDL_CLK_PWM4			148
+#define IMX6QDL_CLK_PER1_BCH			149
+#define IMX6QDL_CLK_GPMI_BCH_APB		150
+#define IMX6QDL_CLK_GPMI_BCH			151
+#define IMX6QDL_CLK_GPMI_IO			152
+#define IMX6QDL_CLK_GPMI_APB			153
+#define IMX6QDL_CLK_SATA			154
+#define IMX6QDL_CLK_SDMA			155
+#define IMX6QDL_CLK_SPBA			156
+#define IMX6QDL_CLK_SSI1			157
+#define IMX6QDL_CLK_SSI2			158
+#define IMX6QDL_CLK_SSI3			159
+#define IMX6QDL_CLK_UART_IPG			160
+#define IMX6QDL_CLK_UART_SERIAL			161
+#define IMX6QDL_CLK_USBOH3			162
+#define IMX6QDL_CLK_USDHC1			163
+#define IMX6QDL_CLK_USDHC2			164
+#define IMX6QDL_CLK_USDHC3			165
+#define IMX6QDL_CLK_USDHC4			166
+#define IMX6QDL_CLK_VDO_AXI			167
+#define IMX6QDL_CLK_VPU_AXI			168
+#define IMX6QDL_CLK_CKO1			169
+#define IMX6QDL_CLK_PLL1_SYS			170
+#define IMX6QDL_CLK_PLL2_BUS			171
+#define IMX6QDL_CLK_PLL3_USB_OTG		172
+#define IMX6QDL_CLK_PLL4_AUDIO			173
+#define IMX6QDL_CLK_PLL5_VIDEO			174
+#define IMX6QDL_CLK_PLL8_MLB			175
+#define IMX6QDL_CLK_PLL7_USB_HOST		176
+#define IMX6QDL_CLK_PLL6_ENET			177
+#define IMX6QDL_CLK_SSI1_IPG			178
+#define IMX6QDL_CLK_SSI2_IPG			179
+#define IMX6QDL_CLK_SSI3_IPG			180
+#define IMX6QDL_CLK_ROM				181
+#define IMX6QDL_CLK_USBPHY1			182
+#define IMX6QDL_CLK_USBPHY2			183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185
+#define IMX6QDL_CLK_SATA_REF			186
+#define IMX6QDL_CLK_SATA_REF_100M		187
+#define IMX6QDL_CLK_PCIE_REF			188
+#define IMX6QDL_CLK_PCIE_REF_125M		189
+#define IMX6QDL_CLK_ENET_REF			190
+#define IMX6QDL_CLK_USBPHY1_GATE		191
+#define IMX6QDL_CLK_USBPHY2_GATE		192
+#define IMX6QDL_CLK_PLL4_POST_DIV		193
+#define IMX6QDL_CLK_PLL5_POST_DIV		194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV		195
+#define IMX6QDL_CLK_EIM_SLOW			196
+#define IMX6QDL_CLK_SPDIF			197
+#define IMX6QDL_CLK_CKO2_SEL			198
+#define IMX6QDL_CLK_CKO2_PODF			199
+#define IMX6QDL_CLK_CKO2			200
+#define IMX6QDL_CLK_CKO				201
+#define IMX6QDL_CLK_VDOA			202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV		203
+#define IMX6QDL_CLK_LVDS1_SEL			204
+#define IMX6QDL_CLK_LVDS2_SEL			205
+#define IMX6QDL_CLK_LVDS1_GATE			206
+#define IMX6QDL_CLK_LVDS2_GATE			207
+#define IMX6QDL_CLK_ESAI_IPG			208
+#define IMX6QDL_CLK_ESAI_MEM			209
+#define IMX6QDL_CLK_ASRC_IPG			210
+#define IMX6QDL_CLK_ASRC_MEM			211
+#define IMX6QDL_CLK_LVDS1_IN			212
+#define IMX6QDL_CLK_LVDS2_IN			213
+#define IMX6QDL_CLK_ANACLK1			214
+#define IMX6QDL_CLK_ANACLK2			215
+#define IMX6QDL_PLL1_BYPASS_SRC			216
+#define IMX6QDL_PLL2_BYPASS_SRC			217
+#define IMX6QDL_PLL3_BYPASS_SRC			218
+#define IMX6QDL_PLL4_BYPASS_SRC			219
+#define IMX6QDL_PLL5_BYPASS_SRC			220
+#define IMX6QDL_PLL6_BYPASS_SRC			221
+#define IMX6QDL_PLL7_BYPASS_SRC			222
+#define IMX6QDL_CLK_PLL1			223
+#define IMX6QDL_CLK_PLL2			224
+#define IMX6QDL_CLK_PLL3			225
+#define IMX6QDL_CLK_PLL4			226
+#define IMX6QDL_CLK_PLL5			227
+#define IMX6QDL_CLK_PLL6			228
+#define IMX6QDL_CLK_PLL7			229
+#define IMX6QDL_PLL1_BYPASS			230
+#define IMX6QDL_PLL2_BYPASS			231
+#define IMX6QDL_PLL3_BYPASS			232
+#define IMX6QDL_PLL4_BYPASS			233
+#define IMX6QDL_PLL5_BYPASS			234
+#define IMX6QDL_PLL6_BYPASS			235
+#define IMX6QDL_PLL7_BYPASS			236
+#define IMX6QDL_CLK_GPT_3M			237
+#define IMX6QDL_CLK_VIDEO_27M			238
+#define IMX6QDL_CLK_MIPI_CORE_CFG		239
+#define IMX6QDL_CLK_MIPI_IPG			240
+#define IMX6QDL_CLK_CAAM_MEM			241
+#define IMX6QDL_CLK_CAAM_ACLK			242
+#define IMX6QDL_CLK_CAAM_IPG			243
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_MLB_SEL			259
+#define IMX6QDL_CLK_MLB_PODF			260
+#define IMX6QDL_CLK_EPIT1			261
+#define IMX6QDL_CLK_EPIT2			262
+#define IMX6QDL_CLK_MMDC_P0_IPG			263
+#define IMX6QDL_CLK_DCIC1			264
+#define IMX6QDL_CLK_DCIC2			265
+#define IMX6QDL_CLK_ENET_REF_SEL		266
+#define IMX6QDL_CLK_ENET_REF_PAD		267
+#define IMX6QDL_CLK_END				268
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */