Resguardo inicial

This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
* Author: Huqiang Qin <huqiang.qin@amlogic.com>
*/
#ifndef _DT_BINDINGS_AMLOGIC_T7_GPIO_H
#define _DT_BINDINGS_AMLOGIC_T7_GPIO_H
#define GPIOB_0 0
#define GPIOB_1 1
#define GPIOB_2 2
#define GPIOB_3 3
#define GPIOB_4 4
#define GPIOB_5 5
#define GPIOB_6 6
#define GPIOB_7 7
#define GPIOB_8 8
#define GPIOB_9 9
#define GPIOB_10 10
#define GPIOB_11 11
#define GPIOB_12 12
#define GPIOC_0 13
#define GPIOC_1 14
#define GPIOC_2 15
#define GPIOC_3 16
#define GPIOC_4 17
#define GPIOC_5 18
#define GPIOC_6 19
#define GPIOX_0 20
#define GPIOX_1 21
#define GPIOX_2 22
#define GPIOX_3 23
#define GPIOX_4 24
#define GPIOX_5 25
#define GPIOX_6 26
#define GPIOX_7 27
#define GPIOX_8 28
#define GPIOX_9 29
#define GPIOX_10 30
#define GPIOX_11 31
#define GPIOX_12 32
#define GPIOX_13 33
#define GPIOX_14 34
#define GPIOX_15 35
#define GPIOX_16 36
#define GPIOX_17 37
#define GPIOX_18 38
#define GPIOX_19 39
#define GPIOW_0 40
#define GPIOW_1 41
#define GPIOW_2 42
#define GPIOW_3 43
#define GPIOW_4 44
#define GPIOW_5 45
#define GPIOW_6 46
#define GPIOW_7 47
#define GPIOW_8 48
#define GPIOW_9 49
#define GPIOW_10 50
#define GPIOW_11 51
#define GPIOW_12 52
#define GPIOW_13 53
#define GPIOW_14 54
#define GPIOW_15 55
#define GPIOW_16 56
#define GPIOD_0 57
#define GPIOD_1 58
#define GPIOD_2 59
#define GPIOD_3 60
#define GPIOD_4 61
#define GPIOD_5 62
#define GPIOD_6 63
#define GPIOD_7 64
#define GPIOD_8 65
#define GPIOD_9 66
#define GPIOD_10 67
#define GPIOD_11 68
#define GPIOD_12 69
#define GPIOE_0 70
#define GPIOE_1 71
#define GPIOE_2 72
#define GPIOE_3 73
#define GPIOE_4 74
#define GPIOE_5 75
#define GPIOE_6 76
#define GPIOZ_0 77
#define GPIOZ_1 78
#define GPIOZ_2 79
#define GPIOZ_3 80
#define GPIOZ_4 81
#define GPIOZ_5 82
#define GPIOZ_6 83
#define GPIOZ_7 84
#define GPIOZ_8 85
#define GPIOZ_9 86
#define GPIOZ_10 87
#define GPIOZ_11 88
#define GPIOZ_12 89
#define GPIOZ_13 90
#define GPIOT_0 91
#define GPIOT_1 92
#define GPIOT_2 93
#define GPIOT_3 94
#define GPIOT_4 95
#define GPIOT_5 96
#define GPIOT_6 97
#define GPIOT_7 98
#define GPIOT_8 99
#define GPIOT_9 100
#define GPIOT_10 101
#define GPIOT_11 102
#define GPIOT_12 103
#define GPIOT_13 104
#define GPIOT_14 105
#define GPIOT_15 106
#define GPIOT_16 107
#define GPIOT_17 108
#define GPIOT_18 109
#define GPIOT_19 110
#define GPIOT_20 111
#define GPIOT_21 112
#define GPIOT_22 113
#define GPIOT_23 114
#define GPIOM_0 115
#define GPIOM_1 116
#define GPIOM_2 117
#define GPIOM_3 118
#define GPIOM_4 119
#define GPIOM_5 120
#define GPIOM_6 121
#define GPIOM_7 122
#define GPIOM_8 123
#define GPIOM_9 124
#define GPIOM_10 125
#define GPIOM_11 126
#define GPIOM_12 127
#define GPIOM_13 128
#define GPIOY_0 129
#define GPIOY_1 130
#define GPIOY_2 131
#define GPIOY_3 132
#define GPIOY_4 133
#define GPIOY_5 134
#define GPIOY_6 135
#define GPIOY_7 136
#define GPIOY_8 137
#define GPIOY_9 138
#define GPIOY_10 139
#define GPIOY_11 140
#define GPIOY_12 141
#define GPIOY_13 142
#define GPIOY_14 143
#define GPIOY_15 144
#define GPIOY_16 145
#define GPIOY_17 146
#define GPIOY_18 147
#define GPIOH_0 148
#define GPIOH_1 149
#define GPIOH_2 150
#define GPIOH_3 151
#define GPIOH_4 152
#define GPIOH_5 153
#define GPIOH_6 154
#define GPIOH_7 155
#define GPIO_TEST_N 156
#endif /* _DT_BINDINGS_AMLOGIC_T7_GPIO_H */
@@ -0,0 +1,72 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
* Author: Huqiang Qin <huqiang.qin@amlogic.com>
*/
#ifndef _DT_BINDINGS_AMLOGIC_C3_GPIO_H
#define _DT_BINDINGS_AMLOGIC_C3_GPIO_H
#define GPIOE_0 0
#define GPIOE_1 1
#define GPIOE_2 2
#define GPIOE_3 3
#define GPIOE_4 4
#define GPIOB_0 5
#define GPIOB_1 6
#define GPIOB_2 7
#define GPIOB_3 8
#define GPIOB_4 9
#define GPIOB_5 10
#define GPIOB_6 11
#define GPIOB_7 12
#define GPIOB_8 13
#define GPIOB_9 14
#define GPIOB_10 15
#define GPIOB_11 16
#define GPIOB_12 17
#define GPIOB_13 18
#define GPIOB_14 19
#define GPIOC_0 20
#define GPIOC_1 21
#define GPIOC_2 22
#define GPIOC_3 23
#define GPIOC_4 24
#define GPIOC_5 25
#define GPIOC_6 26
#define GPIOX_0 27
#define GPIOX_1 28
#define GPIOX_2 29
#define GPIOX_3 30
#define GPIOX_4 31
#define GPIOX_5 32
#define GPIOX_6 33
#define GPIOX_7 34
#define GPIOX_8 35
#define GPIOX_9 36
#define GPIOX_10 37
#define GPIOX_11 38
#define GPIOX_12 39
#define GPIOX_13 40
#define GPIOD_0 41
#define GPIOD_1 42
#define GPIOD_2 43
#define GPIOD_3 44
#define GPIOD_4 45
#define GPIOD_5 46
#define GPIOD_6 47
#define GPIOA_0 48
#define GPIOA_1 49
#define GPIOA_2 50
#define GPIOA_3 51
#define GPIOA_4 52
#define GPIOA_5 53
#define GPIO_TEST_N 54
#endif /* _DT_BINDINGS_AMLOGIC_C3_GPIO_H */
@@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* This header provides constants for binding aspeed,*-gpio.
*
* The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H
#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define ASPEED_GPIO_PORT_A 0
#define ASPEED_GPIO_PORT_B 1
#define ASPEED_GPIO_PORT_C 2
#define ASPEED_GPIO_PORT_D 3
#define ASPEED_GPIO_PORT_E 4
#define ASPEED_GPIO_PORT_F 5
#define ASPEED_GPIO_PORT_G 6
#define ASPEED_GPIO_PORT_H 7
#define ASPEED_GPIO_PORT_I 8
#define ASPEED_GPIO_PORT_J 9
#define ASPEED_GPIO_PORT_K 10
#define ASPEED_GPIO_PORT_L 11
#define ASPEED_GPIO_PORT_M 12
#define ASPEED_GPIO_PORT_N 13
#define ASPEED_GPIO_PORT_O 14
#define ASPEED_GPIO_PORT_P 15
#define ASPEED_GPIO_PORT_Q 16
#define ASPEED_GPIO_PORT_R 17
#define ASPEED_GPIO_PORT_S 18
#define ASPEED_GPIO_PORT_T 19
#define ASPEED_GPIO_PORT_U 20
#define ASPEED_GPIO_PORT_V 21
#define ASPEED_GPIO_PORT_W 22
#define ASPEED_GPIO_PORT_X 23
#define ASPEED_GPIO_PORT_Y 24
#define ASPEED_GPIO_PORT_Z 25
#define ASPEED_GPIO_PORT_AA 26
#define ASPEED_GPIO_PORT_AB 27
#define ASPEED_GPIO_PORT_AC 28
#define ASPEED_GPIO(port, offset) \
((ASPEED_GPIO_PORT_##port * 8) + offset)
#endif
@@ -0,0 +1,45 @@
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
/*
* This header provides constants for most GPIO bindings.
*
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
/* Bit 0 express polarity */
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
/* Bit 1 express single-endedness */
#define GPIO_PUSH_PULL 0
#define GPIO_SINGLE_ENDED 2
/* Bit 2 express Open drain or open source */
#define GPIO_LINE_OPEN_SOURCE 0
#define GPIO_LINE_OPEN_DRAIN 4
/*
* Open Drain/Collector is the combination of single-ended open drain interface.
* Open Source/Emitter is the combination of single-ended open source interface.
*/
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
/* Bit 3 express GPIO suspend/resume and reset persistence */
#define GPIO_PERSISTENT 0
#define GPIO_TRANSITORY 8
/* Bit 4 express pull up */
#define GPIO_PULL_UP 16
/* Bit 5 express pull down */
#define GPIO_PULL_DOWN 32
/* Bit 6 express pull disable */
#define GPIO_PULL_DISABLE 64
#endif
@@ -0,0 +1,73 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Qianggui Song <qianggui.song@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
#define _DT_BINDINGS_MESON_A1_GPIO_H
#define GPIOP_0 0
#define GPIOP_1 1
#define GPIOP_2 2
#define GPIOP_3 3
#define GPIOP_4 4
#define GPIOP_5 5
#define GPIOP_6 6
#define GPIOP_7 7
#define GPIOP_8 8
#define GPIOP_9 9
#define GPIOP_10 10
#define GPIOP_11 11
#define GPIOP_12 12
#define GPIOB_0 13
#define GPIOB_1 14
#define GPIOB_2 15
#define GPIOB_3 16
#define GPIOB_4 17
#define GPIOB_5 18
#define GPIOB_6 19
#define GPIOX_0 20
#define GPIOX_1 21
#define GPIOX_2 22
#define GPIOX_3 23
#define GPIOX_4 24
#define GPIOX_5 25
#define GPIOX_6 26
#define GPIOX_7 27
#define GPIOX_8 28
#define GPIOX_9 29
#define GPIOX_10 30
#define GPIOX_11 31
#define GPIOX_12 32
#define GPIOX_13 33
#define GPIOX_14 34
#define GPIOX_15 35
#define GPIOX_16 36
#define GPIOF_0 37
#define GPIOF_1 38
#define GPIOF_2 39
#define GPIOF_3 40
#define GPIOF_4 41
#define GPIOF_5 42
#define GPIOF_6 43
#define GPIOF_7 44
#define GPIOF_8 45
#define GPIOF_9 46
#define GPIOF_10 47
#define GPIOF_11 48
#define GPIOF_12 49
#define GPIOA_0 50
#define GPIOA_1 51
#define GPIOA_2 52
#define GPIOA_3 53
#define GPIOA_4 54
#define GPIOA_5 55
#define GPIOA_6 56
#define GPIOA_7 57
#define GPIOA_8 58
#define GPIOA_9 59
#define GPIOA_10 60
#define GPIOA_11 61
#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
@@ -0,0 +1,116 @@
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
#define _DT_BINDINGS_MESON_AXG_GPIO_H
/* First GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_TEST_N 14
/* Second GPIO chip */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define BOOT_0 11
#define BOOT_1 12
#define BOOT_2 13
#define BOOT_3 14
#define BOOT_4 15
#define BOOT_5 16
#define BOOT_6 17
#define BOOT_7 18
#define BOOT_8 19
#define BOOT_9 20
#define BOOT_10 21
#define BOOT_11 22
#define BOOT_12 23
#define BOOT_13 24
#define BOOT_14 25
#define GPIOA_0 26
#define GPIOA_1 27
#define GPIOA_2 28
#define GPIOA_3 29
#define GPIOA_4 30
#define GPIOA_5 31
#define GPIOA_6 32
#define GPIOA_7 33
#define GPIOA_8 34
#define GPIOA_9 35
#define GPIOA_10 36
#define GPIOA_11 37
#define GPIOA_12 38
#define GPIOA_13 39
#define GPIOA_14 40
#define GPIOA_15 41
#define GPIOA_16 42
#define GPIOA_17 43
#define GPIOA_18 44
#define GPIOA_19 45
#define GPIOA_20 46
#define GPIOX_0 47
#define GPIOX_1 48
#define GPIOX_2 49
#define GPIOX_3 50
#define GPIOX_4 51
#define GPIOX_5 52
#define GPIOX_6 53
#define GPIOX_7 54
#define GPIOX_8 55
#define GPIOX_9 56
#define GPIOX_10 57
#define GPIOX_11 58
#define GPIOX_12 59
#define GPIOX_13 60
#define GPIOX_14 61
#define GPIOX_15 62
#define GPIOX_16 63
#define GPIOX_17 64
#define GPIOX_18 65
#define GPIOX_19 66
#define GPIOX_20 67
#define GPIOX_21 68
#define GPIOX_22 69
#define GPIOY_0 70
#define GPIOY_1 71
#define GPIOY_2 72
#define GPIOY_3 73
#define GPIOY_4 74
#define GPIOY_5 75
#define GPIOY_6 76
#define GPIOY_7 77
#define GPIOY_8 78
#define GPIOY_9 79
#define GPIOY_10 80
#define GPIOY_11 81
#define GPIOY_12 82
#define GPIOY_13 83
#define GPIOY_14 84
#define GPIOY_15 85
#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
@@ -0,0 +1,114 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
#define _DT_BINDINGS_MESON_G12A_GPIO_H
/* First GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOE_0 12
#define GPIOE_1 13
#define GPIOE_2 14
/* Second GPIO chip */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOZ_11 11
#define GPIOZ_12 12
#define GPIOZ_13 13
#define GPIOZ_14 14
#define GPIOZ_15 15
#define GPIOH_0 16
#define GPIOH_1 17
#define GPIOH_2 18
#define GPIOH_3 19
#define GPIOH_4 20
#define GPIOH_5 21
#define GPIOH_6 22
#define GPIOH_7 23
#define GPIOH_8 24
#define BOOT_0 25
#define BOOT_1 26
#define BOOT_2 27
#define BOOT_3 28
#define BOOT_4 29
#define BOOT_5 30
#define BOOT_6 31
#define BOOT_7 32
#define BOOT_8 33
#define BOOT_9 34
#define BOOT_10 35
#define BOOT_11 36
#define BOOT_12 37
#define BOOT_13 38
#define BOOT_14 39
#define BOOT_15 40
#define GPIOC_0 41
#define GPIOC_1 42
#define GPIOC_2 43
#define GPIOC_3 44
#define GPIOC_4 45
#define GPIOC_5 46
#define GPIOC_6 47
#define GPIOC_7 48
#define GPIOA_0 49
#define GPIOA_1 50
#define GPIOA_2 51
#define GPIOA_3 52
#define GPIOA_4 53
#define GPIOA_5 54
#define GPIOA_6 55
#define GPIOA_7 56
#define GPIOA_8 57
#define GPIOA_9 58
#define GPIOA_10 59
#define GPIOA_11 60
#define GPIOA_12 61
#define GPIOA_13 62
#define GPIOA_14 63
#define GPIOA_15 64
#define GPIOX_0 65
#define GPIOX_1 66
#define GPIOX_2 67
#define GPIOX_3 68
#define GPIOX_4 69
#define GPIOX_5 70
#define GPIOX_6 71
#define GPIOX_7 72
#define GPIOX_8 73
#define GPIOX_9 74
#define GPIOX_10 75
#define GPIOX_11 76
#define GPIOX_12 77
#define GPIOX_13 78
#define GPIOX_14 79
#define GPIOX_15 80
#define GPIOX_16 81
#define GPIOX_17 82
#define GPIOX_18 83
#define GPIOX_19 84
#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
@@ -0,0 +1,148 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* GPIO definitions for Amlogic Meson GXBB SoCs
*
* Copyright (C) 2016 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*/
#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
#define _DT_BINDINGS_MESON_GXBB_GPIO_H
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_TEST_N 14
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOZ_11 11
#define GPIOZ_12 12
#define GPIOZ_13 13
#define GPIOZ_14 14
#define GPIOZ_15 15
#define GPIOH_0 16
#define GPIOH_1 17
#define GPIOH_2 18
#define GPIOH_3 19
#define BOOT_0 20
#define BOOT_1 21
#define BOOT_2 22
#define BOOT_3 23
#define BOOT_4 24
#define BOOT_5 25
#define BOOT_6 26
#define BOOT_7 27
#define BOOT_8 28
#define BOOT_9 29
#define BOOT_10 30
#define BOOT_11 31
#define BOOT_12 32
#define BOOT_13 33
#define BOOT_14 34
#define BOOT_15 35
#define BOOT_16 36
#define BOOT_17 37
#define CARD_0 38
#define CARD_1 39
#define CARD_2 40
#define CARD_3 41
#define CARD_4 42
#define CARD_5 43
#define CARD_6 44
#define GPIODV_0 45
#define GPIODV_1 46
#define GPIODV_2 47
#define GPIODV_3 48
#define GPIODV_4 49
#define GPIODV_5 50
#define GPIODV_6 51
#define GPIODV_7 52
#define GPIODV_8 53
#define GPIODV_9 54
#define GPIODV_10 55
#define GPIODV_11 56
#define GPIODV_12 57
#define GPIODV_13 58
#define GPIODV_14 59
#define GPIODV_15 60
#define GPIODV_16 61
#define GPIODV_17 62
#define GPIODV_18 63
#define GPIODV_19 64
#define GPIODV_20 65
#define GPIODV_21 66
#define GPIODV_22 67
#define GPIODV_23 68
#define GPIODV_24 69
#define GPIODV_25 70
#define GPIODV_26 71
#define GPIODV_27 72
#define GPIODV_28 73
#define GPIODV_29 74
#define GPIOY_0 75
#define GPIOY_1 76
#define GPIOY_2 77
#define GPIOY_3 78
#define GPIOY_4 79
#define GPIOY_5 80
#define GPIOY_6 81
#define GPIOY_7 82
#define GPIOY_8 83
#define GPIOY_9 84
#define GPIOY_10 85
#define GPIOY_11 86
#define GPIOY_12 87
#define GPIOY_13 88
#define GPIOY_14 89
#define GPIOY_15 90
#define GPIOY_16 91
#define GPIOX_0 92
#define GPIOX_1 93
#define GPIOX_2 94
#define GPIOX_3 95
#define GPIOX_4 96
#define GPIOX_5 97
#define GPIOX_6 98
#define GPIOX_7 99
#define GPIOX_8 100
#define GPIOX_9 101
#define GPIOX_10 102
#define GPIOX_11 103
#define GPIOX_12 104
#define GPIOX_13 105
#define GPIOX_14 106
#define GPIOX_15 107
#define GPIOX_16 108
#define GPIOX_17 109
#define GPIOX_18 110
#define GPIOX_19 111
#define GPIOX_20 112
#define GPIOX_21 113
#define GPIOX_22 114
#define GPIOCLK_0 115
#define GPIOCLK_1 116
#define GPIOCLK_2 117
#define GPIOCLK_3 118
#endif
@@ -0,0 +1,125 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* GPIO definitions for Amlogic Meson GXL SoCs
*
* Copyright (C) 2016 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*/
#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
#define _DT_BINDINGS_MESON_GXL_GPIO_H
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIO_TEST_N 10
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOZ_11 11
#define GPIOZ_12 12
#define GPIOZ_13 13
#define GPIOZ_14 14
#define GPIOZ_15 15
#define GPIOH_0 16
#define GPIOH_1 17
#define GPIOH_2 18
#define GPIOH_3 19
#define GPIOH_4 20
#define GPIOH_5 21
#define GPIOH_6 22
#define GPIOH_7 23
#define GPIOH_8 24
#define GPIOH_9 25
#define BOOT_0 26
#define BOOT_1 27
#define BOOT_2 28
#define BOOT_3 29
#define BOOT_4 30
#define BOOT_5 31
#define BOOT_6 32
#define BOOT_7 33
#define BOOT_8 34
#define BOOT_9 35
#define BOOT_10 36
#define BOOT_11 37
#define BOOT_12 38
#define BOOT_13 39
#define BOOT_14 40
#define BOOT_15 41
#define CARD_0 42
#define CARD_1 43
#define CARD_2 44
#define CARD_3 45
#define CARD_4 46
#define CARD_5 47
#define CARD_6 48
#define GPIODV_0 49
#define GPIODV_1 50
#define GPIODV_2 51
#define GPIODV_3 52
#define GPIODV_4 53
#define GPIODV_5 54
#define GPIODV_6 55
#define GPIODV_7 56
#define GPIODV_8 57
#define GPIODV_9 58
#define GPIODV_10 59
#define GPIODV_11 60
#define GPIODV_12 61
#define GPIODV_13 62
#define GPIODV_14 63
#define GPIODV_15 64
#define GPIODV_16 65
#define GPIODV_17 66
#define GPIODV_18 67
#define GPIODV_19 68
#define GPIODV_20 69
#define GPIODV_21 70
#define GPIODV_22 71
#define GPIODV_23 72
#define GPIODV_24 73
#define GPIODV_25 74
#define GPIODV_26 75
#define GPIODV_27 76
#define GPIODV_28 77
#define GPIODV_29 78
#define GPIOX_0 79
#define GPIOX_1 80
#define GPIOX_2 81
#define GPIOX_3 82
#define GPIOX_4 83
#define GPIOX_5 84
#define GPIOX_6 85
#define GPIOX_7 86
#define GPIOX_8 87
#define GPIOX_9 88
#define GPIOX_10 89
#define GPIOX_11 90
#define GPIOX_12 91
#define GPIOX_13 92
#define GPIOX_14 93
#define GPIOX_15 94
#define GPIOX_16 95
#define GPIOX_17 96
#define GPIOX_18 97
#define GPIOCLK_0 98
#define GPIOCLK_1 99
#endif
@@ -0,0 +1,99 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
* Author: Qianggui Song <qianggui.song@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_S4_GPIO_H
#define _DT_BINDINGS_MESON_S4_GPIO_H
#define GPIOB_0 0
#define GPIOB_1 1
#define GPIOB_2 2
#define GPIOB_3 3
#define GPIOB_4 4
#define GPIOB_5 5
#define GPIOB_6 6
#define GPIOB_7 7
#define GPIOB_8 8
#define GPIOB_9 9
#define GPIOB_10 10
#define GPIOB_11 11
#define GPIOB_12 12
#define GPIOB_13 13
#define GPIOC_0 14
#define GPIOC_1 15
#define GPIOC_2 16
#define GPIOC_3 17
#define GPIOC_4 18
#define GPIOC_5 19
#define GPIOC_6 20
#define GPIOC_7 21
#define GPIOE_0 22
#define GPIOE_1 23
#define GPIOD_0 24
#define GPIOD_1 25
#define GPIOD_2 26
#define GPIOD_3 27
#define GPIOD_4 28
#define GPIOD_5 29
#define GPIOD_6 30
#define GPIOD_7 31
#define GPIOD_8 32
#define GPIOD_9 33
#define GPIOD_10 34
#define GPIOD_11 35
#define GPIOH_0 36
#define GPIOH_1 37
#define GPIOH_2 38
#define GPIOH_3 39
#define GPIOH_4 40
#define GPIOH_5 41
#define GPIOH_6 42
#define GPIOH_7 43
#define GPIOH_8 44
#define GPIOH_9 45
#define GPIOH_10 46
#define GPIOH_11 47
#define GPIOX_0 48
#define GPIOX_1 49
#define GPIOX_2 50
#define GPIOX_3 51
#define GPIOX_4 52
#define GPIOX_5 53
#define GPIOX_6 54
#define GPIOX_7 55
#define GPIOX_8 56
#define GPIOX_9 57
#define GPIOX_10 58
#define GPIOX_11 59
#define GPIOX_12 60
#define GPIOX_13 61
#define GPIOX_14 62
#define GPIOX_15 63
#define GPIOX_16 64
#define GPIOX_17 65
#define GPIOX_18 66
#define GPIOX_19 67
#define GPIOZ_0 68
#define GPIOZ_1 69
#define GPIOZ_2 70
#define GPIOZ_3 71
#define GPIOZ_4 72
#define GPIOZ_5 73
#define GPIOZ_6 74
#define GPIOZ_7 75
#define GPIOZ_8 76
#define GPIOZ_9 77
#define GPIOZ_10 78
#define GPIOZ_11 79
#define GPIOZ_12 80
#define GPIO_TEST_N 81
#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */
@@ -0,0 +1,151 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* GPIO definitions for Amlogic Meson8 SoCs
*
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
*/
#ifndef _DT_BINDINGS_MESON8_GPIO_H
#define _DT_BINDINGS_MESON8_GPIO_H
/* First GPIO chip */
#define GPIOX_0 0
#define GPIOX_1 1
#define GPIOX_2 2
#define GPIOX_3 3
#define GPIOX_4 4
#define GPIOX_5 5
#define GPIOX_6 6
#define GPIOX_7 7
#define GPIOX_8 8
#define GPIOX_9 9
#define GPIOX_10 10
#define GPIOX_11 11
#define GPIOX_12 12
#define GPIOX_13 13
#define GPIOX_14 14
#define GPIOX_15 15
#define GPIOX_16 16
#define GPIOX_17 17
#define GPIOX_18 18
#define GPIOX_19 19
#define GPIOX_20 20
#define GPIOX_21 21
#define GPIOY_0 22
#define GPIOY_1 23
#define GPIOY_2 24
#define GPIOY_3 25
#define GPIOY_4 26
#define GPIOY_5 27
#define GPIOY_6 28
#define GPIOY_7 29
#define GPIOY_8 30
#define GPIOY_9 31
#define GPIOY_10 32
#define GPIOY_11 33
#define GPIOY_12 34
#define GPIOY_13 35
#define GPIOY_14 36
#define GPIOY_15 37
#define GPIOY_16 38
#define GPIODV_0 39
#define GPIODV_1 40
#define GPIODV_2 41
#define GPIODV_3 42
#define GPIODV_4 43
#define GPIODV_5 44
#define GPIODV_6 45
#define GPIODV_7 46
#define GPIODV_8 47
#define GPIODV_9 48
#define GPIODV_10 49
#define GPIODV_11 50
#define GPIODV_12 51
#define GPIODV_13 52
#define GPIODV_14 53
#define GPIODV_15 54
#define GPIODV_16 55
#define GPIODV_17 56
#define GPIODV_18 57
#define GPIODV_19 58
#define GPIODV_20 59
#define GPIODV_21 60
#define GPIODV_22 61
#define GPIODV_23 62
#define GPIODV_24 63
#define GPIODV_25 64
#define GPIODV_26 65
#define GPIODV_27 66
#define GPIODV_28 67
#define GPIODV_29 68
#define GPIOH_0 69
#define GPIOH_1 70
#define GPIOH_2 71
#define GPIOH_3 72
#define GPIOH_4 73
#define GPIOH_5 74
#define GPIOH_6 75
#define GPIOH_7 76
#define GPIOH_8 77
#define GPIOH_9 78
#define GPIOZ_0 79
#define GPIOZ_1 80
#define GPIOZ_2 81
#define GPIOZ_3 82
#define GPIOZ_4 83
#define GPIOZ_5 84
#define GPIOZ_6 85
#define GPIOZ_7 86
#define GPIOZ_8 87
#define GPIOZ_9 88
#define GPIOZ_10 89
#define GPIOZ_11 90
#define GPIOZ_12 91
#define GPIOZ_13 92
#define GPIOZ_14 93
#define CARD_0 94
#define CARD_1 95
#define CARD_2 96
#define CARD_3 97
#define CARD_4 98
#define CARD_5 99
#define CARD_6 100
#define BOOT_0 101
#define BOOT_1 102
#define BOOT_2 103
#define BOOT_3 104
#define BOOT_4 105
#define BOOT_5 106
#define BOOT_6 107
#define BOOT_7 108
#define BOOT_8 109
#define BOOT_9 110
#define BOOT_10 111
#define BOOT_11 112
#define BOOT_12 113
#define BOOT_13 114
#define BOOT_14 115
#define BOOT_15 116
#define BOOT_16 117
#define BOOT_17 118
#define BOOT_18 119
/* Second GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_BSD_EN 14
#define GPIO_TEST_N 15
#endif /* _DT_BINDINGS_MESON8_GPIO_H */
@@ -0,0 +1,121 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* GPIO definitions for Amlogic Meson8b SoCs
*
* Copyright (C) 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*/
#ifndef _DT_BINDINGS_MESON8B_GPIO_H
#define _DT_BINDINGS_MESON8B_GPIO_H
/* EE (CBUS) GPIO chip */
#define GPIOX_0 0
#define GPIOX_1 1
#define GPIOX_2 2
#define GPIOX_3 3
#define GPIOX_4 4
#define GPIOX_5 5
#define GPIOX_6 6
#define GPIOX_7 7
#define GPIOX_8 8
#define GPIOX_9 9
#define GPIOX_10 10
#define GPIOX_11 11
#define GPIOX_16 12
#define GPIOX_17 13
#define GPIOX_18 14
#define GPIOX_19 15
#define GPIOX_20 16
#define GPIOX_21 17
#define GPIOY_0 18
#define GPIOY_1 19
#define GPIOY_3 20
#define GPIOY_6 21
#define GPIOY_7 22
#define GPIOY_8 23
#define GPIOY_9 24
#define GPIOY_10 25
#define GPIOY_11 26
#define GPIOY_12 27
#define GPIOY_13 28
#define GPIOY_14 29
#define GPIODV_9 30
#define GPIODV_24 31
#define GPIODV_25 32
#define GPIODV_26 33
#define GPIODV_27 34
#define GPIODV_28 35
#define GPIODV_29 36
#define GPIOH_0 37
#define GPIOH_1 38
#define GPIOH_2 39
#define GPIOH_3 40
#define GPIOH_4 41
#define GPIOH_5 42
#define GPIOH_6 43
#define GPIOH_7 44
#define GPIOH_8 45
#define GPIOH_9 46
#define CARD_0 47
#define CARD_1 48
#define CARD_2 49
#define CARD_3 50
#define CARD_4 51
#define CARD_5 52
#define CARD_6 53
#define BOOT_0 54
#define BOOT_1 55
#define BOOT_2 56
#define BOOT_3 57
#define BOOT_4 58
#define BOOT_5 59
#define BOOT_6 60
#define BOOT_7 61
#define BOOT_8 62
#define BOOT_9 63
#define BOOT_10 64
#define BOOT_11 65
#define BOOT_12 66
#define BOOT_13 67
#define BOOT_14 68
#define BOOT_15 69
#define BOOT_16 70
#define BOOT_17 71
#define BOOT_18 72
#define DIF_0_P 73
#define DIF_0_N 74
#define DIF_1_P 75
#define DIF_1_N 76
#define DIF_2_P 77
#define DIF_2_N 78
#define DIF_3_P 79
#define DIF_3_N 80
#define DIF_4_P 81
#define DIF_4_N 82
/* AO GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_BSD_EN 14
#define GPIO_TEST_N 15
#endif /* _DT_BINDINGS_MESON8B_GPIO_H */
@@ -0,0 +1,124 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* GPIO definitions for MStar/SigmaStar MSC313 and later SoCs
*
* Copyright (C) 2020 Daniel Palmer <daniel@thingy.jp>
*/
#ifndef _DT_BINDINGS_MSC313_GPIO_H
#define _DT_BINDINGS_MSC313_GPIO_H
#define MSC313_GPIO_FUART 0
#define MSC313_GPIO_FUART_RX (MSC313_GPIO_FUART + 0)
#define MSC313_GPIO_FUART_TX (MSC313_GPIO_FUART + 1)
#define MSC313_GPIO_FUART_CTS (MSC313_GPIO_FUART + 2)
#define MSC313_GPIO_FUART_RTS (MSC313_GPIO_FUART + 3)
#define MSC313_GPIO_SR (MSC313_GPIO_FUART_RTS + 1)
#define MSC313_GPIO_SR_IO2 (MSC313_GPIO_SR + 0)
#define MSC313_GPIO_SR_IO3 (MSC313_GPIO_SR + 1)
#define MSC313_GPIO_SR_IO4 (MSC313_GPIO_SR + 2)
#define MSC313_GPIO_SR_IO5 (MSC313_GPIO_SR + 3)
#define MSC313_GPIO_SR_IO6 (MSC313_GPIO_SR + 4)
#define MSC313_GPIO_SR_IO7 (MSC313_GPIO_SR + 5)
#define MSC313_GPIO_SR_IO8 (MSC313_GPIO_SR + 6)
#define MSC313_GPIO_SR_IO9 (MSC313_GPIO_SR + 7)
#define MSC313_GPIO_SR_IO10 (MSC313_GPIO_SR + 8)
#define MSC313_GPIO_SR_IO11 (MSC313_GPIO_SR + 9)
#define MSC313_GPIO_SR_IO12 (MSC313_GPIO_SR + 10)
#define MSC313_GPIO_SR_IO13 (MSC313_GPIO_SR + 11)
#define MSC313_GPIO_SR_IO14 (MSC313_GPIO_SR + 12)
#define MSC313_GPIO_SR_IO15 (MSC313_GPIO_SR + 13)
#define MSC313_GPIO_SR_IO16 (MSC313_GPIO_SR + 14)
#define MSC313_GPIO_SR_IO17 (MSC313_GPIO_SR + 15)
#define MSC313_GPIO_SD (MSC313_GPIO_SR_IO17 + 1)
#define MSC313_GPIO_SD_CLK (MSC313_GPIO_SD + 0)
#define MSC313_GPIO_SD_CMD (MSC313_GPIO_SD + 1)
#define MSC313_GPIO_SD_D0 (MSC313_GPIO_SD + 2)
#define MSC313_GPIO_SD_D1 (MSC313_GPIO_SD + 3)
#define MSC313_GPIO_SD_D2 (MSC313_GPIO_SD + 4)
#define MSC313_GPIO_SD_D3 (MSC313_GPIO_SD + 5)
#define MSC313_GPIO_I2C1 (MSC313_GPIO_SD_D3 + 1)
#define MSC313_GPIO_I2C1_SCL (MSC313_GPIO_I2C1 + 0)
#define MSC313_GPIO_I2C1_SDA (MSC313_GPIO_I2C1 + 1)
#define MSC313_GPIO_SPI0 (MSC313_GPIO_I2C1_SDA + 1)
#define MSC313_GPIO_SPI0_CZ (MSC313_GPIO_SPI0 + 0)
#define MSC313_GPIO_SPI0_CK (MSC313_GPIO_SPI0 + 1)
#define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2)
#define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3)
/* SSD20x */
#define SSD20XD_GPIO_FUART 0
#define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0)
#define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1)
#define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2)
#define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3)
#define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1)
#define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0)
#define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1)
#define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2)
#define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3)
#define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4)
#define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5)
#define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1)
#define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0)
#define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1)
#define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1)
#define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0)
#define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1)
#define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1)
#define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0)
#define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1)
#define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2)
#define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3)
#define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4)
#define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5)
#define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6)
#define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7)
#define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8)
#define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9)
#define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10)
#define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11)
#define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12)
#define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13)
#define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14)
#define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15)
#define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16)
#define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17)
#define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18)
#define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19)
#define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20)
#define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21)
#define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22)
#define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23)
#define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24)
#define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25)
#define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26)
#define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27)
#define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1)
#define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0)
#define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1)
#define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2)
#define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3)
#define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4)
#define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5)
#define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6)
#define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7)
#define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8)
#define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9)
#define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10)
#define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11)
#define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12)
#define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13)
#define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14)
#define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15)
#endif /* _DT_BINDINGS_MSC313_GPIO_H */
@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for binding nvidia,tegra238-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA238_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA238_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA238_MAIN_GPIO_PORT_A 0
#define TEGRA238_MAIN_GPIO_PORT_B 1
#define TEGRA238_MAIN_GPIO_PORT_C 2
#define TEGRA238_MAIN_GPIO_PORT_D 3
#define TEGRA238_MAIN_GPIO_PORT_E 4
#define TEGRA238_MAIN_GPIO_PORT_F 5
#define TEGRA238_MAIN_GPIO_PORT_G 6
#define TEGRA238_MAIN_GPIO_PORT_H 7
#define TEGRA238_MAIN_GPIO_PORT_J 8
#define TEGRA238_MAIN_GPIO_PORT_K 9
#define TEGRA238_MAIN_GPIO_PORT_L 10
#define TEGRA238_MAIN_GPIO_PORT_M 11
#define TEGRA238_MAIN_GPIO_PORT_N 12
#define TEGRA238_MAIN_GPIO_PORT_P 13
#define TEGRA238_MAIN_GPIO_PORT_Q 14
#define TEGRA238_MAIN_GPIO_PORT_R 15
#define TEGRA238_MAIN_GPIO_PORT_S 16
#define TEGRA238_MAIN_GPIO_PORT_T 17
#define TEGRA238_MAIN_GPIO_PORT_U 18
#define TEGRA238_MAIN_GPIO_PORT_V 19
#define TEGRA238_MAIN_GPIO_PORT_W 20
#define TEGRA238_MAIN_GPIO_PORT_X 21
#define TEGRA238_MAIN_GPIO(port, offset) \
((TEGRA238_MAIN_GPIO_PORT_##port * 8) + (offset))
/* GPIOs implemented by AON GPIO controller */
#define TEGRA238_AON_GPIO_PORT_AA 0
#define TEGRA238_AON_GPIO_PORT_BB 1
#define TEGRA238_AON_GPIO_PORT_CC 2
#define TEGRA238_AON_GPIO_PORT_DD 3
#define TEGRA238_AON_GPIO_PORT_EE 4
#define TEGRA238_AON_GPIO_PORT_FF 5
#define TEGRA238_AON_GPIO_PORT_GG 6
#define TEGRA238_AON_GPIO_PORT_HH 7
#define TEGRA238_AON_GPIO(port, offset) \
((TEGRA238_AON_GPIO_PORT_##port * 8) + (offset))
#endif
@@ -0,0 +1,61 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for binding nvidia,tegra264-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA264_MAIN_GPIO_PORT_T 0
#define TEGRA264_MAIN_GPIO_PORT_U 1
#define TEGRA264_MAIN_GPIO_PORT_V 2
#define TEGRA264_MAIN_GPIO_PORT_W 3
#define TEGRA264_MAIN_GPIO_PORT_AL 4
#define TEGRA264_MAIN_GPIO_PORT_Y 5
#define TEGRA264_MAIN_GPIO_PORT_Z 6
#define TEGRA264_MAIN_GPIO_PORT_X 7
#define TEGRA264_MAIN_GPIO_PORT_H 8
#define TEGRA264_MAIN_GPIO_PORT_J 9
#define TEGRA264_MAIN_GPIO_PORT_K 10
#define TEGRA264_MAIN_GPIO_PORT_L 11
#define TEGRA264_MAIN_GPIO_PORT_M 12
#define TEGRA264_MAIN_GPIO_PORT_P 13
#define TEGRA264_MAIN_GPIO_PORT_Q 14
#define TEGRA264_MAIN_GPIO_PORT_R 15
#define TEGRA264_MAIN_GPIO_PORT_S 16
#define TEGRA264_MAIN_GPIO_PORT_F 17
#define TEGRA264_MAIN_GPIO_PORT_G 18
#define TEGRA264_MAIN_GPIO(port, offset) \
((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset))
/* GPIOs implemented by AON GPIO controller */
#define TEGRA264_AON_GPIO_PORT_AA 0
#define TEGRA264_AON_GPIO_PORT_BB 1
#define TEGRA264_AON_GPIO_PORT_CC 2
#define TEGRA264_AON_GPIO_PORT_DD 3
#define TEGRA264_AON_GPIO_PORT_EE 4
#define TEGRA264_AON_GPIO(port, offset) \
((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset))
#define TEGRA264_UPHY_GPIO_PORT_A 0
#define TEGRA264_UPHY_GPIO_PORT_B 1
#define TEGRA264_UPHY_GPIO_PORT_C 2
#define TEGRA264_UPHY_GPIO_PORT_D 3
#define TEGRA264_UPHY_GPIO_PORT_E 4
#define TEGRA264_UPHY_GPIO(port, offset) \
((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset))
#endif
@@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for binding nvidia,tegra*-gpio.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_PORT_A 0
#define TEGRA_GPIO_PORT_B 1
#define TEGRA_GPIO_PORT_C 2
#define TEGRA_GPIO_PORT_D 3
#define TEGRA_GPIO_PORT_E 4
#define TEGRA_GPIO_PORT_F 5
#define TEGRA_GPIO_PORT_G 6
#define TEGRA_GPIO_PORT_H 7
#define TEGRA_GPIO_PORT_I 8
#define TEGRA_GPIO_PORT_J 9
#define TEGRA_GPIO_PORT_K 10
#define TEGRA_GPIO_PORT_L 11
#define TEGRA_GPIO_PORT_M 12
#define TEGRA_GPIO_PORT_N 13
#define TEGRA_GPIO_PORT_O 14
#define TEGRA_GPIO_PORT_P 15
#define TEGRA_GPIO_PORT_Q 16
#define TEGRA_GPIO_PORT_R 17
#define TEGRA_GPIO_PORT_S 18
#define TEGRA_GPIO_PORT_T 19
#define TEGRA_GPIO_PORT_U 20
#define TEGRA_GPIO_PORT_V 21
#define TEGRA_GPIO_PORT_W 22
#define TEGRA_GPIO_PORT_X 23
#define TEGRA_GPIO_PORT_Y 24
#define TEGRA_GPIO_PORT_Z 25
#define TEGRA_GPIO_PORT_AA 26
#define TEGRA_GPIO_PORT_BB 27
#define TEGRA_GPIO_PORT_CC 28
#define TEGRA_GPIO_PORT_DD 29
#define TEGRA_GPIO_PORT_EE 30
#define TEGRA_GPIO_PORT_FF 31
#define TEGRA_GPIO(port, offset) \
((TEGRA_GPIO_PORT_##port * 8) + offset)
#endif
@@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for binding nvidia,tegra186-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA186_MAIN_GPIO_PORT_A 0
#define TEGRA186_MAIN_GPIO_PORT_B 1
#define TEGRA186_MAIN_GPIO_PORT_C 2
#define TEGRA186_MAIN_GPIO_PORT_D 3
#define TEGRA186_MAIN_GPIO_PORT_E 4
#define TEGRA186_MAIN_GPIO_PORT_F 5
#define TEGRA186_MAIN_GPIO_PORT_G 6
#define TEGRA186_MAIN_GPIO_PORT_H 7
#define TEGRA186_MAIN_GPIO_PORT_I 8
#define TEGRA186_MAIN_GPIO_PORT_J 9
#define TEGRA186_MAIN_GPIO_PORT_K 10
#define TEGRA186_MAIN_GPIO_PORT_L 11
#define TEGRA186_MAIN_GPIO_PORT_M 12
#define TEGRA186_MAIN_GPIO_PORT_N 13
#define TEGRA186_MAIN_GPIO_PORT_O 14
#define TEGRA186_MAIN_GPIO_PORT_P 15
#define TEGRA186_MAIN_GPIO_PORT_Q 16
#define TEGRA186_MAIN_GPIO_PORT_R 17
#define TEGRA186_MAIN_GPIO_PORT_T 18
#define TEGRA186_MAIN_GPIO_PORT_X 19
#define TEGRA186_MAIN_GPIO_PORT_Y 20
#define TEGRA186_MAIN_GPIO_PORT_BB 21
#define TEGRA186_MAIN_GPIO_PORT_CC 22
#define TEGRA186_MAIN_GPIO(port, offset) \
((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset)
/* GPIOs implemented by AON GPIO controller */
#define TEGRA186_AON_GPIO_PORT_S 0
#define TEGRA186_AON_GPIO_PORT_U 1
#define TEGRA186_AON_GPIO_PORT_V 2
#define TEGRA186_AON_GPIO_PORT_W 3
#define TEGRA186_AON_GPIO_PORT_Z 4
#define TEGRA186_AON_GPIO_PORT_AA 5
#define TEGRA186_AON_GPIO_PORT_EE 6
#define TEGRA186_AON_GPIO_PORT_FF 7
#define TEGRA186_AON_GPIO(port, offset) \
((TEGRA186_AON_GPIO_PORT_##port * 8) + offset)
#endif
@@ -0,0 +1,61 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for binding nvidia,tegra194-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA194_MAIN_GPIO_PORT_A 0
#define TEGRA194_MAIN_GPIO_PORT_B 1
#define TEGRA194_MAIN_GPIO_PORT_C 2
#define TEGRA194_MAIN_GPIO_PORT_D 3
#define TEGRA194_MAIN_GPIO_PORT_E 4
#define TEGRA194_MAIN_GPIO_PORT_F 5
#define TEGRA194_MAIN_GPIO_PORT_G 6
#define TEGRA194_MAIN_GPIO_PORT_H 7
#define TEGRA194_MAIN_GPIO_PORT_I 8
#define TEGRA194_MAIN_GPIO_PORT_J 9
#define TEGRA194_MAIN_GPIO_PORT_K 10
#define TEGRA194_MAIN_GPIO_PORT_L 11
#define TEGRA194_MAIN_GPIO_PORT_M 12
#define TEGRA194_MAIN_GPIO_PORT_N 13
#define TEGRA194_MAIN_GPIO_PORT_O 14
#define TEGRA194_MAIN_GPIO_PORT_P 15
#define TEGRA194_MAIN_GPIO_PORT_Q 16
#define TEGRA194_MAIN_GPIO_PORT_R 17
#define TEGRA194_MAIN_GPIO_PORT_S 18
#define TEGRA194_MAIN_GPIO_PORT_T 19
#define TEGRA194_MAIN_GPIO_PORT_U 20
#define TEGRA194_MAIN_GPIO_PORT_V 21
#define TEGRA194_MAIN_GPIO_PORT_W 22
#define TEGRA194_MAIN_GPIO_PORT_X 23
#define TEGRA194_MAIN_GPIO_PORT_Y 24
#define TEGRA194_MAIN_GPIO_PORT_Z 25
#define TEGRA194_MAIN_GPIO_PORT_FF 26
#define TEGRA194_MAIN_GPIO_PORT_GG 27
#define TEGRA194_MAIN_GPIO(port, offset) \
((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)
/* GPIOs implemented by AON GPIO controller */
#define TEGRA194_AON_GPIO_PORT_AA 0
#define TEGRA194_AON_GPIO_PORT_BB 1
#define TEGRA194_AON_GPIO_PORT_CC 2
#define TEGRA194_AON_GPIO_PORT_DD 3
#define TEGRA194_AON_GPIO_PORT_EE 4
#define TEGRA194_AON_GPIO(port, offset) \
((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)
#endif
@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for binding nvidia,tegra234-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA234_MAIN_GPIO_PORT_A 0
#define TEGRA234_MAIN_GPIO_PORT_B 1
#define TEGRA234_MAIN_GPIO_PORT_C 2
#define TEGRA234_MAIN_GPIO_PORT_D 3
#define TEGRA234_MAIN_GPIO_PORT_E 4
#define TEGRA234_MAIN_GPIO_PORT_F 5
#define TEGRA234_MAIN_GPIO_PORT_G 6
#define TEGRA234_MAIN_GPIO_PORT_H 7
#define TEGRA234_MAIN_GPIO_PORT_I 8
#define TEGRA234_MAIN_GPIO_PORT_J 9
#define TEGRA234_MAIN_GPIO_PORT_K 10
#define TEGRA234_MAIN_GPIO_PORT_L 11
#define TEGRA234_MAIN_GPIO_PORT_M 12
#define TEGRA234_MAIN_GPIO_PORT_N 13
#define TEGRA234_MAIN_GPIO_PORT_P 14
#define TEGRA234_MAIN_GPIO_PORT_Q 15
#define TEGRA234_MAIN_GPIO_PORT_R 16
#define TEGRA234_MAIN_GPIO_PORT_X 17
#define TEGRA234_MAIN_GPIO_PORT_Y 18
#define TEGRA234_MAIN_GPIO_PORT_Z 19
#define TEGRA234_MAIN_GPIO_PORT_AC 20
#define TEGRA234_MAIN_GPIO_PORT_AD 21
#define TEGRA234_MAIN_GPIO_PORT_AE 22
#define TEGRA234_MAIN_GPIO_PORT_AF 23
#define TEGRA234_MAIN_GPIO_PORT_AG 24
#define TEGRA234_MAIN_GPIO(port, offset) \
((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
/* GPIOs implemented by AON GPIO controller */
#define TEGRA234_AON_GPIO_PORT_AA 0
#define TEGRA234_AON_GPIO_PORT_BB 1
#define TEGRA234_AON_GPIO_PORT_CC 2
#define TEGRA234_AON_GPIO_PORT_DD 3
#define TEGRA234_AON_GPIO_PORT_EE 4
#define TEGRA234_AON_GPIO_PORT_GG 5
#define TEGRA234_AON_GPIO(port, offset) \
((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
#endif
@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for the nvidia,tegra241-gpio DT binding.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA241_MAIN_GPIO_PORT_A 0
#define TEGRA241_MAIN_GPIO_PORT_B 1
#define TEGRA241_MAIN_GPIO_PORT_C 2
#define TEGRA241_MAIN_GPIO_PORT_D 3
#define TEGRA241_MAIN_GPIO_PORT_E 4
#define TEGRA241_MAIN_GPIO_PORT_F 5
#define TEGRA241_MAIN_GPIO_PORT_G 6
#define TEGRA241_MAIN_GPIO_PORT_H 7
#define TEGRA241_MAIN_GPIO_PORT_I 8
#define TEGRA241_MAIN_GPIO_PORT_J 9
#define TEGRA241_MAIN_GPIO_PORT_K 10
#define TEGRA241_MAIN_GPIO_PORT_L 11
#define TEGRA241_MAIN_GPIO(port, offset) \
((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset))
/* GPIOs implemented by AON GPIO controller */
#define TEGRA241_AON_GPIO_PORT_AA 0
#define TEGRA241_AON_GPIO_PORT_BB 1
#define TEGRA241_AON_GPIO(port, offset) \
((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset))
#endif
@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for the nvidia,tegra256-gpio DT binding.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID.
* The macros below provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA256_MAIN_GPIO_PORT_A 0
#define TEGRA256_MAIN_GPIO_PORT_B 1
#define TEGRA256_MAIN_GPIO_PORT_C 2
#define TEGRA256_MAIN_GPIO_PORT_D 3
#define TEGRA256_MAIN_GPIO(port, offset) \
((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset))
#endif
@@ -0,0 +1,18 @@
/*
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H
#define _DT_BINDINGS_GPIO_UNIPHIER_H
#define UNIPHIER_GPIO_LINES_PER_BANK 8
#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)
#define UNIPHIER_GPIO_PORT(bank, line) \
((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))
#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */