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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/include/dt-bindings/iio/adc/adi,ad4695.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_ADI_AD4695_H
#define _DT_BINDINGS_ADI_AD4695_H
#define AD4695_COMMON_MODE_REFGND 0xFF
#define AD4695_COMMON_MODE_COM 0xFE
#define AD4695_TRIGGER_EVENT_BUSY 0
#define AD4695_TRIGGER_EVENT_ALERT 1
#define AD4695_TRIGGER_PIN_GP0 0
#define AD4695_TRIGGER_PIN_GP2 2
#define AD4695_TRIGGER_PIN_GP3 3
#endif /* _DT_BINDINGS_ADI_AD4695_H */
linux-7.2.3/include/dt-bindings/iio/adc/adi,ad7606.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_ADI_AD7606_H
#define _DT_BINDINGS_ADI_AD7606_H
#define AD7606_TRIGGER_EVENT_BUSY 0
#define AD7606_TRIGGER_EVENT_FRSTDATA 1
#endif /* _DT_BINDINGS_ADI_AD7606_H */
linux-7.2.3/include/dt-bindings/iio/adc/adi,ad7768-1.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_ADI_AD7768_1_H
#define _DT_BINDINGS_ADI_AD7768_1_H
#define AD7768_TRIGGER_SOURCE_SYNC_OUT 0
#define AD7768_TRIGGER_SOURCE_GPIO3 1
#define AD7768_TRIGGER_SOURCE_DRDY 2
#endif /* _DT_BINDINGS_ADI_AD7768_1_H */
linux-7.2.3/include/dt-bindings/iio/adc/at91-sama5d2_adc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for configuring the AT91 SAMA5D2 ADC
*/
#ifndef _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H
#define _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H
/* X relative position channel index */
#define AT91_SAMA5D2_ADC_X_CHANNEL 24
/* Y relative position channel index */
#define AT91_SAMA5D2_ADC_Y_CHANNEL 25
/* pressure channel index */
#define AT91_SAMA5D2_ADC_P_CHANNEL 26
/* SAMA7G5 Temperature sensor channel index. */
#define AT91_SAMA7G5_ADC_TEMP_CHANNEL 31
#endif
linux-7.2.3/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for configuring the I.MX25 ADC
*/
#ifndef _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
#define _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
#define MX25_ADC_REFP_YP 0 /* YP voltage reference */
#define MX25_ADC_REFP_XP 1 /* XP voltage reference */
#define MX25_ADC_REFP_EXT 2 /* External voltage reference */
#define MX25_ADC_REFP_INT 3 /* Internal voltage reference */
#define MX25_ADC_REFN_XN 0 /* XN ground reference */
#define MX25_ADC_REFN_YN 1 /* YN ground reference */
#define MX25_ADC_REFN_NGND 2 /* Internal ground reference */
#define MX25_ADC_REFN_NGND2 3 /* External ground reference */
#endif
linux-7.2.3/include/dt-bindings/iio/adc/gehc,pmc-adc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_IIO_ADC_GEHC_PMC_ADC_H
#define _DT_BINDINGS_IIO_ADC_GEHC_PMC_ADC_H
/* ADC channel type */
#define GEHC_PMC_ADC_VOLTAGE 0
#define GEHC_PMC_ADC_CURRENT 1
#endif
linux-7.2.3/include/dt-bindings/iio/adc/ingenic,adc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_IIO_ADC_INGENIC_ADC_H
#define _DT_BINDINGS_IIO_ADC_INGENIC_ADC_H
/* ADC channel idx. */
#define INGENIC_ADC_AUX 0
#define INGENIC_ADC_BATTERY 1
#define INGENIC_ADC_AUX2 2
#define INGENIC_ADC_TOUCH_XP 3
#define INGENIC_ADC_TOUCH_YP 4
#define INGENIC_ADC_TOUCH_XN 5
#define INGENIC_ADC_TOUCH_YN 6
#define INGENIC_ADC_TOUCH_XD 7
#define INGENIC_ADC_TOUCH_YD 8
#define INGENIC_ADC_AUX0 9
#endif
linux-7.2.3/include/dt-bindings/iio/adc/mediatek,mt6357-auxadc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H
/* ADC Channel Index */
#define MT6357_AUXADC_BATADC 0
#define MT6357_AUXADC_ISENSE 1
#define MT6357_AUXADC_VCDT 2
#define MT6357_AUXADC_BAT_TEMP 3
#define MT6357_AUXADC_CHIP_TEMP 4
#define MT6357_AUXADC_ACCDET 5
#define MT6357_AUXADC_VDCXO 6
#define MT6357_AUXADC_TSX_TEMP 7
#define MT6357_AUXADC_HPOFS_CAL 8
#define MT6357_AUXADC_DCXO_TEMP 9
#define MT6357_AUXADC_VCORE_TEMP 10
#define MT6357_AUXADC_VPROC_TEMP 11
#define MT6357_AUXADC_VBAT 12
#endif
linux-7.2.3/include/dt-bindings/iio/adc/mediatek,mt6358-auxadc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H
/* ADC Channel Index */
#define MT6358_AUXADC_BATADC 0
#define MT6358_AUXADC_VCDT 1
#define MT6358_AUXADC_BAT_TEMP 2
#define MT6358_AUXADC_CHIP_TEMP 3
#define MT6358_AUXADC_ACCDET 4
#define MT6358_AUXADC_VDCXO 5
#define MT6358_AUXADC_TSX_TEMP 6
#define MT6358_AUXADC_HPOFS_CAL 7
#define MT6358_AUXADC_DCXO_TEMP 8
#define MT6358_AUXADC_VBIF 9
#define MT6358_AUXADC_VCORE_TEMP 10
#define MT6358_AUXADC_VPROC_TEMP 11
#define MT6358_AUXADC_VGPU_TEMP 12
#define MT6358_AUXADC_VBAT 13
#endif
linux-7.2.3/include/dt-bindings/iio/adc/mediatek,mt6359-auxadc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H
/* ADC Channel Index */
#define MT6359_AUXADC_BATADC 0
#define MT6359_AUXADC_BAT_TEMP 1
#define MT6359_AUXADC_CHIP_TEMP 2
#define MT6359_AUXADC_ACCDET 3
#define MT6359_AUXADC_VDCXO 4
#define MT6359_AUXADC_TSX_TEMP 5
#define MT6359_AUXADC_HPOFS_CAL 6
#define MT6359_AUXADC_DCXO_TEMP 7
#define MT6359_AUXADC_VBIF 8
#define MT6359_AUXADC_VCORE_TEMP 9
#define MT6359_AUXADC_VPROC_TEMP 10
#define MT6359_AUXADC_VGPU_TEMP 11
#define MT6359_AUXADC_VBAT 12
#define MT6359_AUXADC_IBAT 13
#endif
linux-7.2.3/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H
/* ADC Channel Index */
#define MT6363_AUXADC_BATADC 0
#define MT6363_AUXADC_VCDT 1
#define MT6363_AUXADC_BAT_TEMP 2
#define MT6363_AUXADC_CHIP_TEMP 3
#define MT6363_AUXADC_VSYSSNS 4
#define MT6363_AUXADC_VTREF 5
#define MT6363_AUXADC_VCORE_TEMP 6
#define MT6363_AUXADC_VPROC_TEMP 7
#define MT6363_AUXADC_VGPU_TEMP 8
#define MT6363_AUXADC_VIN1 9
#define MT6363_AUXADC_VIN2 10
#define MT6363_AUXADC_VIN3 11
#define MT6363_AUXADC_VIN4 12
#define MT6363_AUXADC_VIN5 13
#define MT6363_AUXADC_VIN6 14
#define MT6363_AUXADC_VIN7 15
#endif
linux-7.2.3/include/dt-bindings/iio/adc/mediatek,mt6370_adc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef __DT_BINDINGS_MEDIATEK_MT6370_ADC_H__
#define __DT_BINDINGS_MEDIATEK_MT6370_ADC_H__
/* ADC Channel Index */
#define MT6370_CHAN_VBUSDIV5 0
#define MT6370_CHAN_VBUSDIV2 1
#define MT6370_CHAN_VSYS 2
#define MT6370_CHAN_VBAT 3
#define MT6370_CHAN_TS_BAT 4
#define MT6370_CHAN_IBUS 5
#define MT6370_CHAN_IBAT 6
#define MT6370_CHAN_CHG_VDDP 7
#define MT6370_CHAN_TEMP_JC 8
#define MT6370_CHAN_MAX 9
#endif
linux-7.2.3/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H
/* ADC Channel Index */
#define MT6373_AUXADC_CHIP_TEMP 0
#define MT6373_AUXADC_VCORE_TEMP 1
#define MT6373_AUXADC_VPROC_TEMP 2
#define MT6373_AUXADC_VGPU_TEMP 3
#define MT6373_AUXADC_VIN1 4
#define MT6373_AUXADC_VIN2 5
#define MT6373_AUXADC_VIN3 6
#define MT6373_AUXADC_VIN4 7
#define MT6373_AUXADC_VIN5 8
#define MT6373_AUXADC_VIN6 9
#define MT6373_AUXADC_VIN7 10
#endif
linux-7.2.3/include/dt-bindings/iio/addac/adi,ad74413r.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_ADI_AD74413R_H
#define _DT_BINDINGS_ADI_AD74413R_H
#define CH_FUNC_HIGH_IMPEDANCE 0x0
#define CH_FUNC_VOLTAGE_OUTPUT 0x1
#define CH_FUNC_CURRENT_OUTPUT 0x2
#define CH_FUNC_VOLTAGE_INPUT 0x3
#define CH_FUNC_CURRENT_INPUT_EXT_POWER 0x4
#define CH_FUNC_CURRENT_INPUT_LOOP_POWER 0x5
#define CH_FUNC_RESISTANCE_INPUT 0x6
#define CH_FUNC_DIGITAL_INPUT_LOGIC 0x7
#define CH_FUNC_DIGITAL_INPUT_LOOP_POWER 0x8
#define CH_FUNC_CURRENT_INPUT_EXT_POWER_HART 0x9
#define CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART 0xA
#define CH_FUNC_MIN CH_FUNC_HIGH_IMPEDANCE
#define CH_FUNC_MAX CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART
#endif /* _DT_BINDINGS_ADI_AD74413R_H */
linux-7.2.3/include/dt-bindings/iio/adi,ad5592r.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_ADI_AD5592R_H
#define _DT_BINDINGS_ADI_AD5592R_H
#define CH_MODE_UNUSED 0
#define CH_MODE_ADC 1
#define CH_MODE_DAC 2
#define CH_MODE_DAC_AND_ADC 3
#define CH_MODE_GPIO 8
#define CH_OFFSTATE_PULLDOWN 0
#define CH_OFFSTATE_OUT_LOW 1
#define CH_OFFSTATE_OUT_HIGH 2
#define CH_OFFSTATE_OUT_TRISTATE 3
#endif /* _DT_BINDINGS_ADI_AD5592R_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H
#ifndef PM7325_SID
#define PM7325_SID 1
#endif
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PM7325_ADC for PMIC7 */
#define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND)
#define PM7325_ADC7_1P25VREF (PM7325_SID << 8 | ADC7_1P25VREF)
#define PM7325_ADC7_VREF_VADC (PM7325_SID << 8 | ADC7_VREF_VADC)
#define PM7325_ADC7_DIE_TEMP (PM7325_SID << 8 | ADC7_DIE_TEMP)
#define PM7325_ADC7_AMUX_THM1 (PM7325_SID << 8 | ADC7_AMUX_THM1)
#define PM7325_ADC7_AMUX_THM2 (PM7325_SID << 8 | ADC7_AMUX_THM2)
#define PM7325_ADC7_AMUX_THM3 (PM7325_SID << 8 | ADC7_AMUX_THM3)
#define PM7325_ADC7_AMUX_THM4 (PM7325_SID << 8 | ADC7_AMUX_THM4)
#define PM7325_ADC7_AMUX_THM5 (PM7325_SID << 8 | ADC7_AMUX_THM5)
#define PM7325_ADC7_GPIO1 (PM7325_SID << 8 | ADC7_GPIO1)
#define PM7325_ADC7_GPIO2 (PM7325_SID << 8 | ADC7_GPIO2)
#define PM7325_ADC7_GPIO3 (PM7325_SID << 8 | ADC7_GPIO3)
#define PM7325_ADC7_GPIO4 (PM7325_SID << 8 | ADC7_GPIO4)
/* 30k pull-up1 */
#define PM7325_ADC7_AMUX_THM1_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_30K_PU)
#define PM7325_ADC7_AMUX_THM2_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_30K_PU)
#define PM7325_ADC7_AMUX_THM3_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_30K_PU)
#define PM7325_ADC7_AMUX_THM4_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_30K_PU)
#define PM7325_ADC7_AMUX_THM5_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_30K_PU)
#define PM7325_ADC7_GPIO1_30K_PU (PM7325_SID << 8 | ADC7_GPIO1_30K_PU)
#define PM7325_ADC7_GPIO2_30K_PU (PM7325_SID << 8 | ADC7_GPIO2_30K_PU)
#define PM7325_ADC7_GPIO3_30K_PU (PM7325_SID << 8 | ADC7_GPIO3_30K_PU)
#define PM7325_ADC7_GPIO4_30K_PU (PM7325_SID << 8 | ADC7_GPIO4_30K_PU)
/* 100k pull-up2 */
#define PM7325_ADC7_AMUX_THM1_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_100K_PU)
#define PM7325_ADC7_AMUX_THM2_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_100K_PU)
#define PM7325_ADC7_AMUX_THM3_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_100K_PU)
#define PM7325_ADC7_AMUX_THM4_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_100K_PU)
#define PM7325_ADC7_AMUX_THM5_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_100K_PU)
#define PM7325_ADC7_GPIO1_100K_PU (PM7325_SID << 8 | ADC7_GPIO1_100K_PU)
#define PM7325_ADC7_GPIO2_100K_PU (PM7325_SID << 8 | ADC7_GPIO2_100K_PU)
#define PM7325_ADC7_GPIO3_100K_PU (PM7325_SID << 8 | ADC7_GPIO3_100K_PU)
#define PM7325_ADC7_GPIO4_100K_PU (PM7325_SID << 8 | ADC7_GPIO4_100K_PU)
/* 400k pull-up3 */
#define PM7325_ADC7_AMUX_THM1_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_400K_PU)
#define PM7325_ADC7_AMUX_THM2_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_400K_PU)
#define PM7325_ADC7_AMUX_THM3_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_400K_PU)
#define PM7325_ADC7_AMUX_THM4_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_400K_PU)
#define PM7325_ADC7_AMUX_THM5_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_400K_PU)
#define PM7325_ADC7_GPIO1_400K_PU (PM7325_SID << 8 | ADC7_GPIO1_400K_PU)
#define PM7325_ADC7_GPIO2_400K_PU (PM7325_SID << 8 | ADC7_GPIO2_400K_PU)
#define PM7325_ADC7_GPIO3_400K_PU (PM7325_SID << 8 | ADC7_GPIO3_400K_PU)
#define PM7325_ADC7_GPIO4_400K_PU (PM7325_SID << 8 | ADC7_GPIO4_400K_PU)
/* 1/3 Divider */
#define PM7325_ADC7_GPIO4_DIV3 (PM7325_SID << 8 | ADC7_GPIO4_DIV3)
#define PM7325_ADC7_VPH_PWR (PM7325_SID << 8 | ADC7_VPH_PWR)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PM8350_ADC for PMIC7 */
#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | ADC7_REF_GND)
#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | ADC7_1P25VREF)
#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | ADC7_VREF_VADC)
#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | ADC7_DIE_TEMP)
#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | ADC7_AMUX_THM1)
#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | ADC7_AMUX_THM2)
#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | ADC7_AMUX_THM3)
#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | ADC7_AMUX_THM4)
#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | ADC7_AMUX_THM5)
#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | ADC7_GPIO1)
#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | ADC7_GPIO2)
#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | ADC7_GPIO3)
#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | ADC7_GPIO4)
/* 30k pull-up1 */
#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM1_30K_PU)
#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM2_30K_PU)
#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM3_30K_PU)
#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM4_30K_PU)
#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM5_30K_PU)
#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | ADC7_GPIO1_30K_PU)
#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | ADC7_GPIO2_30K_PU)
#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | ADC7_GPIO3_30K_PU)
#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | ADC7_GPIO4_30K_PU)
/* 100k pull-up2 */
#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM1_100K_PU)
#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM2_100K_PU)
#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM3_100K_PU)
#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM4_100K_PU)
#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM5_100K_PU)
#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | ADC7_GPIO1_100K_PU)
#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | ADC7_GPIO2_100K_PU)
#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | ADC7_GPIO3_100K_PU)
#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | ADC7_GPIO4_100K_PU)
/* 400k pull-up3 */
#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM1_400K_PU)
#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM2_400K_PU)
#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM3_400K_PU)
#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM4_400K_PU)
#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM5_400K_PU)
#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | ADC7_GPIO1_400K_PU)
#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | ADC7_GPIO2_400K_PU)
#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | ADC7_GPIO3_400K_PU)
#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | ADC7_GPIO4_400K_PU)
/* 1/3 Divider */
#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | ADC7_GPIO4_DIV3)
#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | ADC7_VPH_PWR)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
#ifndef PM8350B_SID
#define PM8350B_SID 3
#endif
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PM8350B_ADC for PMIC7 */
#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | ADC7_REF_GND)
#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | ADC7_1P25VREF)
#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | ADC7_VREF_VADC)
#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | ADC7_DIE_TEMP)
#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | ADC7_AMUX_THM1)
#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | ADC7_AMUX_THM2)
#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | ADC7_AMUX_THM3)
#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | ADC7_AMUX_THM4)
#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | ADC7_AMUX_THM5)
#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | ADC7_AMUX_THM6)
#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | ADC7_GPIO1)
#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | ADC7_GPIO2)
#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | ADC7_GPIO3)
#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | ADC7_GPIO4)
#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | ADC7_CHG_TEMP)
#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | ADC7_USB_IN_V_16)
#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | ADC7_VDC_16)
#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | ADC7_CC1_ID)
#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | ADC7_VREF_BAT_THERM)
#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | ADC7_IIN_FB)
/* 30k pull-up1 */
#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM1_30K_PU)
#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM2_30K_PU)
#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM3_30K_PU)
#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM4_30K_PU)
#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM5_30K_PU)
#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM6_30K_PU)
#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | ADC7_GPIO1_30K_PU)
#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | ADC7_GPIO2_30K_PU)
#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | ADC7_GPIO3_30K_PU)
#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | ADC7_GPIO4_30K_PU)
#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | ADC7_CC1_ID_30K_PU)
/* 100k pull-up2 */
#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM1_100K_PU)
#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM2_100K_PU)
#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM3_100K_PU)
#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM4_100K_PU)
#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM5_100K_PU)
#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM6_100K_PU)
#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | ADC7_GPIO1_100K_PU)
#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | ADC7_GPIO2_100K_PU)
#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | ADC7_GPIO3_100K_PU)
#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | ADC7_GPIO4_100K_PU)
#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | ADC7_CC1_ID_100K_PU)
/* 400k pull-up3 */
#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM1_400K_PU)
#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM2_400K_PU)
#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM3_400K_PU)
#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM4_400K_PU)
#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM5_400K_PU)
#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM6_400K_PU)
#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | ADC7_GPIO1_400K_PU)
#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | ADC7_GPIO2_400K_PU)
#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | ADC7_GPIO3_400K_PU)
#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | ADC7_GPIO4_400K_PU)
#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | ADC7_CC1_ID_400K_PU)
/* 1/3 Divider */
#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | ADC7_GPIO1_DIV3)
#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | ADC7_GPIO2_DIV3)
#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | ADC7_GPIO3_DIV3)
#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | ADC7_GPIO4_DIV3)
#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | ADC7_VPH_PWR)
#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | ADC7_VBAT_SNS)
#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | ADC7_SBU)
#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | ADC7_VBAT_2S_MID)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
#ifndef PMK8350_SID
#define PMK8350_SID 0
#endif
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PMK8350_ADC for PMIC7 */
#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | ADC7_REF_GND)
#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | ADC7_1P25VREF)
#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | ADC7_VREF_VADC)
#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | ADC7_DIE_TEMP)
#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | ADC7_AMUX_THM1)
#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | ADC7_AMUX_THM2)
#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | ADC7_AMUX_THM3)
#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | ADC7_AMUX_THM4)
#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | ADC7_AMUX_THM5)
/* 30k pull-up1 */
#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM1_30K_PU)
#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM2_30K_PU)
#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM3_30K_PU)
#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM4_30K_PU)
#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM5_30K_PU)
/* 100k pull-up2 */
#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM1_100K_PU)
#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM2_100K_PU)
#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM3_100K_PU)
#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM4_100K_PU)
#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM5_100K_PU)
/* 400k pull-up3 */
#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM1_400K_PU)
#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM2_400K_PU)
#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM3_400K_PU)
#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM4_400K_PU)
#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM5_400K_PU)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
#ifndef PMR735A_SID
#define PMR735A_SID 4
#endif
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PMR735A_ADC for PMIC7 */
#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | ADC7_REF_GND)
#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | ADC7_1P25VREF)
#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | ADC7_VREF_VADC)
#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | ADC7_DIE_TEMP)
#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | ADC7_GPIO1)
#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | ADC7_GPIO2)
#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | ADC7_GPIO3)
/* 100k pull-up2 */
#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | ADC7_GPIO1_100K_PU)
#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | ADC7_GPIO2_100K_PU)
#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | ADC7_GPIO3_100K_PU)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
#ifndef PMR735B_SID
#define PMR735B_SID 5
#endif
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PMR735B_ADC for PMIC7 */
#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND)
#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | ADC7_1P25VREF)
#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | ADC7_VREF_VADC)
#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | ADC7_DIE_TEMP)
#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | ADC7_GPIO1)
#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | ADC7_GPIO2)
#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | ADC7_GPIO3)
/* 100k pull-up2 */
#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | ADC7_GPIO1_100K_PU)
#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | ADC7_GPIO2_100K_PU)
#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | ADC7_GPIO3_100K_PU)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
#define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
#define SMB139x_1_ADC7_IIN_SMB (SMB139x_1_SID << 8 | ADC7_IIN_SMB)
#define SMB139x_2_ADC7_SMB_TEMP (SMB139x_2_SID << 8 | ADC7_SMB_TEMP)
#define SMB139x_2_ADC7_ICHG_SMB (SMB139x_2_SID << 8 | ADC7_ICHG_SMB)
#define SMB139x_2_ADC7_IIN_SMB (SMB139x_2_SID << 8 | ADC7_IIN_SMB)
#endif
linux-7.2.3/include/dt-bindings/iio/qcom,spmi-vadc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_H
/* Voltage ADC channels */
#define VADC_USBIN 0x00
#define VADC_DCIN 0x01
#define VADC_VCHG_SNS 0x02
#define VADC_SPARE1_03 0x03
#define VADC_USB_ID_MV 0x04
#define VADC_VCOIN 0x05
#define VADC_VBAT_SNS 0x06
#define VADC_VSYS 0x07
#define VADC_DIE_TEMP 0x08
#define VADC_REF_625MV 0x09
#define VADC_REF_1250MV 0x0a
#define VADC_CHG_TEMP 0x0b
#define VADC_SPARE1 0x0c
#define VADC_SPARE2 0x0d
#define VADC_GND_REF 0x0e
#define VADC_VDD_VADC 0x0f
#define VADC_P_MUX1_1_1 0x10
#define VADC_P_MUX2_1_1 0x11
#define VADC_P_MUX3_1_1 0x12
#define VADC_P_MUX4_1_1 0x13
#define VADC_P_MUX5_1_1 0x14
#define VADC_P_MUX6_1_1 0x15
#define VADC_P_MUX7_1_1 0x16
#define VADC_P_MUX8_1_1 0x17
#define VADC_P_MUX9_1_1 0x18
#define VADC_P_MUX10_1_1 0x19
#define VADC_P_MUX11_1_1 0x1a
#define VADC_P_MUX12_1_1 0x1b
#define VADC_P_MUX13_1_1 0x1c
#define VADC_P_MUX14_1_1 0x1d
#define VADC_P_MUX15_1_1 0x1e
#define VADC_P_MUX16_1_1 0x1f
#define VADC_P_MUX1_1_3 0x20
#define VADC_P_MUX2_1_3 0x21
#define VADC_P_MUX3_1_3 0x22
#define VADC_P_MUX4_1_3 0x23
#define VADC_P_MUX5_1_3 0x24
#define VADC_P_MUX6_1_3 0x25
#define VADC_P_MUX7_1_3 0x26
#define VADC_P_MUX8_1_3 0x27
#define VADC_P_MUX9_1_3 0x28
#define VADC_P_MUX10_1_3 0x29
#define VADC_P_MUX11_1_3 0x2a
#define VADC_P_MUX12_1_3 0x2b
#define VADC_P_MUX13_1_3 0x2c
#define VADC_P_MUX14_1_3 0x2d
#define VADC_P_MUX15_1_3 0x2e
#define VADC_P_MUX16_1_3 0x2f
#define VADC_LR_MUX1_BAT_THERM 0x30
#define VADC_LR_MUX2_BAT_ID 0x31
#define VADC_LR_MUX3_XO_THERM 0x32
#define VADC_LR_MUX4_AMUX_THM1 0x33
#define VADC_LR_MUX5_AMUX_THM2 0x34
#define VADC_LR_MUX6_AMUX_THM3 0x35
#define VADC_LR_MUX7_HW_ID 0x36
#define VADC_LR_MUX8_AMUX_THM4 0x37
#define VADC_LR_MUX9_AMUX_THM5 0x38
#define VADC_LR_MUX10_USB_ID 0x39
#define VADC_AMUX_PU1 0x3a
#define VADC_AMUX_PU2 0x3b
#define VADC_LR_MUX3_BUF_XO_THERM 0x3c
#define VADC_LR_MUX1_PU1_BAT_THERM 0x70
#define VADC_LR_MUX2_PU1_BAT_ID 0x71
#define VADC_LR_MUX3_PU1_XO_THERM 0x72
#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73
#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74
#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75
#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76
#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77
#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78
#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79
#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c
#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0
#define VADC_LR_MUX2_PU2_BAT_ID 0xb1
#define VADC_LR_MUX3_PU2_XO_THERM 0xb2
#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3
#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4
#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5
#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6
#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7
#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8
#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9
#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc
#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0
#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1
#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2
#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3
#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4
#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5
#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6
#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7
#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8
#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
/* ADC channels for SPMI PMIC5 */
#define ADC5_REF_GND 0x00
#define ADC5_1P25VREF 0x01
#define ADC5_VREF_VADC 0x02
#define ADC5_VREF_VADC5_DIV_3 0x82
#define ADC5_VPH_PWR 0x83
#define ADC5_VBAT_SNS 0x84
#define ADC5_VCOIN 0x85
#define ADC5_DIE_TEMP 0x06
#define ADC5_USB_IN_I 0x07
#define ADC5_USB_IN_V_16 0x08
#define ADC5_CHG_TEMP 0x09
#define ADC5_BAT_THERM 0x0a
#define ADC5_BAT_ID 0x0b
#define ADC5_XO_THERM 0x0c
#define ADC5_AMUX_THM1 0x0d
#define ADC5_AMUX_THM2 0x0e
#define ADC5_AMUX_THM3 0x0f
#define ADC5_AMUX_THM4 0x10
#define ADC5_AMUX_THM5 0x11
#define ADC5_GPIO1 0x12
#define ADC5_GPIO2 0x13
#define ADC5_GPIO3 0x14
#define ADC5_GPIO4 0x15
#define ADC5_GPIO5 0x16
#define ADC5_GPIO6 0x17
#define ADC5_GPIO7 0x18
#define ADC5_SBUx 0x99
#define ADC5_MID_CHG_DIV6 0x1e
#define ADC5_OFF 0xff
/* 30k pull-up1 */
#define ADC5_BAT_THERM_30K_PU 0x2a
#define ADC5_BAT_ID_30K_PU 0x2b
#define ADC5_XO_THERM_30K_PU 0x2c
#define ADC5_AMUX_THM1_30K_PU 0x2d
#define ADC5_AMUX_THM2_30K_PU 0x2e
#define ADC5_AMUX_THM3_30K_PU 0x2f
#define ADC5_AMUX_THM4_30K_PU 0x30
#define ADC5_AMUX_THM5_30K_PU 0x31
#define ADC5_GPIO1_30K_PU 0x32
#define ADC5_GPIO2_30K_PU 0x33
#define ADC5_GPIO3_30K_PU 0x34
#define ADC5_GPIO4_30K_PU 0x35
#define ADC5_GPIO5_30K_PU 0x36
#define ADC5_GPIO6_30K_PU 0x37
#define ADC5_GPIO7_30K_PU 0x38
#define ADC5_SBUx_30K_PU 0x39
/* 100k pull-up2 */
#define ADC5_BAT_THERM_100K_PU 0x4a
#define ADC5_BAT_ID_100K_PU 0x4b
#define ADC5_XO_THERM_100K_PU 0x4c
#define ADC5_AMUX_THM1_100K_PU 0x4d
#define ADC5_AMUX_THM2_100K_PU 0x4e
#define ADC5_AMUX_THM3_100K_PU 0x4f
#define ADC5_AMUX_THM4_100K_PU 0x50
#define ADC5_AMUX_THM5_100K_PU 0x51
#define ADC5_GPIO1_100K_PU 0x52
#define ADC5_GPIO2_100K_PU 0x53
#define ADC5_GPIO3_100K_PU 0x54
#define ADC5_GPIO4_100K_PU 0x55
#define ADC5_GPIO5_100K_PU 0x56
#define ADC5_GPIO6_100K_PU 0x57
#define ADC5_GPIO7_100K_PU 0x58
#define ADC5_SBUx_100K_PU 0x59
/* 400k pull-up3 */
#define ADC5_BAT_THERM_400K_PU 0x6a
#define ADC5_BAT_ID_400K_PU 0x6b
#define ADC5_XO_THERM_400K_PU 0x6c
#define ADC5_AMUX_THM1_400K_PU 0x6d
#define ADC5_AMUX_THM2_400K_PU 0x6e
#define ADC5_AMUX_THM3_400K_PU 0x6f
#define ADC5_AMUX_THM4_400K_PU 0x70
#define ADC5_AMUX_THM5_400K_PU 0x71
#define ADC5_GPIO1_400K_PU 0x72
#define ADC5_GPIO2_400K_PU 0x73
#define ADC5_GPIO3_400K_PU 0x74
#define ADC5_GPIO4_400K_PU 0x75
#define ADC5_GPIO5_400K_PU 0x76
#define ADC5_GPIO6_400K_PU 0x77
#define ADC5_GPIO7_400K_PU 0x78
#define ADC5_SBUx_400K_PU 0x79
/* 1/3 Divider */
#define ADC5_GPIO1_DIV3 0x92
#define ADC5_GPIO2_DIV3 0x93
#define ADC5_GPIO3_DIV3 0x94
#define ADC5_GPIO4_DIV3 0x95
#define ADC5_GPIO5_DIV3 0x96
#define ADC5_GPIO6_DIV3 0x97
#define ADC5_GPIO7_DIV3 0x98
#define ADC5_SBUx_DIV3 0x99
/* Current and combined current/voltage channels */
#define ADC5_INT_EXT_ISENSE 0xa1
#define ADC5_PARALLEL_ISENSE 0xa5
#define ADC5_CUR_REPLICA_VDS 0xa7
#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
#define ADC5_EXT_SENS_OFFSET 0xad
#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
#define ADC5_MAX_CHANNEL 0xc0
/* ADC channels for ADC for PMIC7 */
#define ADC7_REF_GND 0x00
#define ADC7_1P25VREF 0x01
#define ADC7_VREF_VADC 0x02
#define ADC7_DIE_TEMP 0x03
#define ADC7_AMUX_THM1 0x04
#define ADC7_AMUX_THM2 0x05
#define ADC7_AMUX_THM3 0x06
#define ADC7_AMUX_THM4 0x07
#define ADC7_AMUX_THM5 0x08
#define ADC7_AMUX_THM6 0x09
#define ADC7_GPIO1 0x0a
#define ADC7_GPIO2 0x0b
#define ADC7_GPIO3 0x0c
#define ADC7_GPIO4 0x0d
#define ADC7_SMB_TEMP 0x06
#define ADC7_CHG_TEMP 0x10
#define ADC7_USB_IN_V_16 0x11
#define ADC7_VDC_16 0x12
#define ADC7_CC1_ID 0x13
#define ADC7_VREF_BAT_THERM 0x15
#define ADC7_IIN_FB 0x17
#define ADC7_ICHG_SMB 0x18
#define ADC7_IIN_SMB 0x19
/* 30k pull-up1 */
#define ADC7_AMUX_THM1_30K_PU 0x24
#define ADC7_AMUX_THM2_30K_PU 0x25
#define ADC7_AMUX_THM3_30K_PU 0x26
#define ADC7_AMUX_THM4_30K_PU 0x27
#define ADC7_AMUX_THM5_30K_PU 0x28
#define ADC7_AMUX_THM6_30K_PU 0x29
#define ADC7_GPIO1_30K_PU 0x2a
#define ADC7_GPIO2_30K_PU 0x2b
#define ADC7_GPIO3_30K_PU 0x2c
#define ADC7_GPIO4_30K_PU 0x2d
#define ADC7_CC1_ID_30K_PU 0x33
/* 100k pull-up2 */
#define ADC7_AMUX_THM1_100K_PU 0x44
#define ADC7_AMUX_THM2_100K_PU 0x45
#define ADC7_AMUX_THM3_100K_PU 0x46
#define ADC7_AMUX_THM4_100K_PU 0x47
#define ADC7_AMUX_THM5_100K_PU 0x48
#define ADC7_AMUX_THM6_100K_PU 0x49
#define ADC7_GPIO1_100K_PU 0x4a
#define ADC7_GPIO2_100K_PU 0x4b
#define ADC7_GPIO3_100K_PU 0x4c
#define ADC7_GPIO4_100K_PU 0x4d
#define ADC7_CC1_ID_100K_PU 0x53
/* 400k pull-up3 */
#define ADC7_AMUX_THM1_400K_PU 0x64
#define ADC7_AMUX_THM2_400K_PU 0x65
#define ADC7_AMUX_THM3_400K_PU 0x66
#define ADC7_AMUX_THM4_400K_PU 0x67
#define ADC7_AMUX_THM5_400K_PU 0x68
#define ADC7_AMUX_THM6_400K_PU 0x69
#define ADC7_GPIO1_400K_PU 0x6a
#define ADC7_GPIO2_400K_PU 0x6b
#define ADC7_GPIO3_400K_PU 0x6c
#define ADC7_GPIO4_400K_PU 0x6d
#define ADC7_CC1_ID_400K_PU 0x73
/* 1/3 Divider */
#define ADC7_GPIO1_DIV3 0x8a
#define ADC7_GPIO2_DIV3 0x8b
#define ADC7_GPIO3_DIV3 0x8c
#define ADC7_GPIO4_DIV3 0x8d
#define ADC7_VPH_PWR 0x8e
#define ADC7_VBAT_SNS 0x8f
#define ADC7_SBUx 0x94
#define ADC7_VBAT_2S_MID 0x96
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
linux-7.2.3/include/dt-bindings/iio/temperature/thermocouple.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H
#define _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H
#define THERMOCOUPLE_TYPE_B 0x00
#define THERMOCOUPLE_TYPE_E 0x01
#define THERMOCOUPLE_TYPE_J 0x02
#define THERMOCOUPLE_TYPE_K 0x03
#define THERMOCOUPLE_TYPE_N 0x04
#define THERMOCOUPLE_TYPE_R 0x05
#define THERMOCOUPLE_TYPE_S 0x06
#define THERMOCOUPLE_TYPE_T 0x07
#endif /* _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H */