Resguardo inicial

This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* include/dt-bindings/media/omap3-isp.h
*
* Copyright (C) 2015 Sakari Ailus
*/
#ifndef __DT_BINDINGS_OMAP3_ISP_H__
#define __DT_BINDINGS_OMAP3_ISP_H__
#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0
#define OMAP3ISP_PHY_TYPE_CSIPHY 1
#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */
@@ -0,0 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 Gateworks Corporation
*/
#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H
#define _DT_BINDINGS_MEDIA_TDA1997X_H
/* TDA19973 36bit Video Port control registers */
#define TDA1997X_VP36_35_32 0
#define TDA1997X_VP36_31_28 1
#define TDA1997X_VP36_27_24 2
#define TDA1997X_VP36_23_20 3
#define TDA1997X_VP36_19_16 4
#define TDA1997X_VP36_15_12 5
#define TDA1997X_VP36_11_08 6
#define TDA1997X_VP36_07_04 7
#define TDA1997X_VP36_03_00 8
/* TDA19971 24bit Video Port control registers */
#define TDA1997X_VP24_V23_20 0
#define TDA1997X_VP24_V19_16 1
#define TDA1997X_VP24_V15_12 3
#define TDA1997X_VP24_V11_08 4
#define TDA1997X_VP24_V07_04 6
#define TDA1997X_VP24_V03_00 7
/* Pin groups */
#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */
#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */
#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */
#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
/* pinswapped groups */
#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP)
#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP)
#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP)
#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP)
#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP)
#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP)
#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP)
#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP)
#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP)
/* Audio bus DAI format */
#define TDA1997X_I2S16 1 /* I2S 16bit */
#define TDA1997X_I2S32 2 /* I2S 32bit */
#define TDA1997X_SPDIF 3 /* SPDIF */
#define TDA1997X_OBA 4 /* One Bit Audio */
#define TDA1997X_DST 5 /* Direct Stream Transfer */
#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */
#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */
#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */
#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */
/* Audio bus channel layout */
#define TDA1997X_LAYOUT0 0 /* 2-channel */
#define TDA1997X_LAYOUT1 1 /* 8-channel */
/* Audio bus clock */
#define TDA1997X_ACLK_16FS 0
#define TDA1997X_ACLK_32FS 1
#define TDA1997X_ACLK_64FS 2
#define TDA1997X_ACLK_128FS 3
#define TDA1997X_ACLK_256FS 4
#define TDA1997X_ACLK_512FS 5
#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */
@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
tvp5150.h - definition for tvp5150 inputs
Copyright (C) 2006 Hans Verkuil (hverkuil@kernel.org)
*/
#ifndef _DT_BINDINGS_MEDIA_TVP5150_H
#define _DT_BINDINGS_MEDIA_TVP5150_H
/* TVP5150 HW inputs */
#define TVP5150_COMPOSITE0 0
#define TVP5150_COMPOSITE1 1
#define TVP5150_SVIDEO 2
/* TVP5150 HW outputs */
#define TVP5150_NORMAL 0
#define TVP5150_BLACK_SCREEN 1
#endif /* _DT_BINDINGS_MEDIA_TVP5150_H */
@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
#define MEDIA_BUS_TYPE_CSI2_CPHY 1
#define MEDIA_BUS_TYPE_CSI1 2
#define MEDIA_BUS_TYPE_CCP2 3
#define MEDIA_BUS_TYPE_CSI2_DPHY 4
#define MEDIA_BUS_TYPE_PARALLEL 5
#define MEDIA_BUS_TYPE_BT656 6
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC 0
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB 1
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC 2
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA 3
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5
#define MEDIA_PCLK_SAMPLE_FALLING_EDGE 0
#define MEDIA_PCLK_SAMPLE_RISING_EDGE 1
#define MEDIA_PCLK_SAMPLE_DUAL_EDGE 2
#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
@@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Video IP Core
*
* Copyright (C) 2013-2015 Ideas on Board
* Copyright (C) 2013-2015 Xilinx, Inc.
*
* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__
#define __DT_BINDINGS_MEDIA_XILINX_VIP_H__
/*
* Video format codes as defined in "AXI4-Stream Video IP and System Design
* Guide".
*/
#define XVIP_VF_YUV_422 0
#define XVIP_VF_YUV_444 1
#define XVIP_VF_RBG 2
#define XVIP_VF_YUV_420 3
#define XVIP_VF_YUVA_422 4
#define XVIP_VF_YUVA_444 5
#define XVIP_VF_RGBA 6
#define XVIP_VF_YUVA_420 7
#define XVIP_VF_YUVD_422 8
#define XVIP_VF_YUVD_444 9
#define XVIP_VF_RGBD 10
#define XVIP_VF_YUVD_420 11
#define XVIP_VF_MONO_SENSOR 12
#define XVIP_VF_CUSTOM2 13
#define XVIP_VF_CUSTOM3 14
#define XVIP_VF_CUSTOM4 15
#endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */