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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/include/dt-bindings/net/microchip-lan78xx.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H
#define _DT_BINDINGS_MICROCHIP_LAN78XX_H
/* LED modes for LAN7800/LAN7850 embedded PHY */
#define LAN78XX_LINK_ACTIVITY 0
#define LAN78XX_LINK_1000_ACTIVITY 1
#define LAN78XX_LINK_100_ACTIVITY 2
#define LAN78XX_LINK_10_ACTIVITY 3
#define LAN78XX_LINK_100_1000_ACTIVITY 4
#define LAN78XX_LINK_10_1000_ACTIVITY 5
#define LAN78XX_LINK_10_100_ACTIVITY 6
#define LAN78XX_DUPLEX_COLLISION 8
#define LAN78XX_COLLISION 9
#define LAN78XX_ACTIVITY 10
#define LAN78XX_AUTONEG_FAULT 12
#define LAN78XX_FORCE_LED_OFF 14
#define LAN78XX_FORCE_LED_ON 15
#endif
linux-7.2.3/include/dt-bindings/net/mscc-phy-vsc8531.h
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/*
* Device Tree constants for Microsemi VSC8531 PHY
*
* Author: Nagaraju Lakkaraju
*
* License: Dual MIT/GPL
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _DT_BINDINGS_MSCC_VSC8531_H
#define _DT_BINDINGS_MSCC_VSC8531_H
/* PHY LED Modes */
#define VSC8531_LINK_ACTIVITY 0
#define VSC8531_LINK_1000_ACTIVITY 1
#define VSC8531_LINK_100_ACTIVITY 2
#define VSC8531_LINK_10_ACTIVITY 3
#define VSC8531_LINK_100_1000_ACTIVITY 4
#define VSC8531_LINK_10_1000_ACTIVITY 5
#define VSC8531_LINK_10_100_ACTIVITY 6
#define VSC8584_LINK_100FX_1000X_ACTIVITY 7
#define VSC8531_DUPLEX_COLLISION 8
#define VSC8531_COLLISION 9
#define VSC8531_ACTIVITY 10
#define VSC8584_100FX_1000X_ACTIVITY 11
#define VSC8531_AUTONEG_FAULT 12
#define VSC8531_SERIAL_MODE 13
#define VSC8531_FORCE_LED_OFF 14
#define VSC8531_FORCE_LED_ON 15
#endif
linux-7.2.3/include/dt-bindings/net/pcs-rzn1-miic.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Schneider-Electric
*
* Clément Léger <clement.leger@bootlin.com>
*/
#ifndef _DT_BINDINGS_PCS_RZN1_MIIC
#define _DT_BINDINGS_PCS_RZN1_MIIC
/*
* Reefer to the datasheet [1] section 8.2.1, Internal Connection of Ethernet
* Ports to check the available combination
*
* [1] REN_r01uh0750ej0140-rzn1-introduction_MAT_20210228.pdf
*/
#define MIIC_GMAC1_PORT 0
#define MIIC_GMAC2_PORT 1
#define MIIC_RTOS_PORT 2
#define MIIC_SERCOS_PORTA 3
#define MIIC_SERCOS_PORTB 4
#define MIIC_ETHERCAT_PORTA 5
#define MIIC_ETHERCAT_PORTB 6
#define MIIC_ETHERCAT_PORTC 7
#define MIIC_SWITCH_PORTA 8
#define MIIC_SWITCH_PORTB 9
#define MIIC_SWITCH_PORTC 10
#define MIIC_SWITCH_PORTD 11
#define MIIC_HSR_PORTA 12
#define MIIC_HSR_PORTB 13
#endif
linux-7.2.3/include/dt-bindings/net/qca-ar803x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Device Tree constants for the Qualcomm Atheros AR803x PHYs
*/
#ifndef _DT_BINDINGS_QCA_AR803X_H
#define _DT_BINDINGS_QCA_AR803X_H
#define AR803X_STRENGTH_FULL 0
#define AR803X_STRENGTH_HALF 1
#define AR803X_STRENGTH_QUARTER 2
#endif
linux-7.2.3/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2025 Renesas Electronics Corporation.
*/
#ifndef _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
#define _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
/*
* Media Interface Connection Matrix
* ===========================================================
*
* Selects the function of the Media interface of the MAC to be used
*
* SW_MODE[2:0] | Port 0 | Port 1 | Port 2 | Port 3
* -------------|-------------|-------------|-------------|-------------
* 000b | ETHSW Port0 | ETHSW Port1 | ETHSW Port2 | GMAC1
* 001b | ESC Port0 | ESC Port1 | GMAC2 | GMAC1
* 010b | ESC Port0 | ESC Port1 | ETHSW Port2 | GMAC1
* 011b | ESC Port0 | ESC Port1 | ESC Port2 | GMAC1
* 100b | ETHSW Port0 | ESC Port1 | ESC Port2 | GMAC1
* 101b | ETHSW Port0 | ESC Port1 | ETHSW Port2 | GMAC1
* 110b | ETHSW Port0 | ETHSW Port1 | GMAC2 | GMAC1
* 111b | GMAC0 | GMAC1 | GMAC2 | -
*/
#define ETHSS_GMAC0_PORT 0
#define ETHSS_GMAC1_PORT 1
#define ETHSS_GMAC2_PORT 2
#define ETHSS_ESC_PORT0 3
#define ETHSS_ESC_PORT1 4
#define ETHSS_ESC_PORT2 5
#define ETHSS_ETHSW_PORT0 6
#define ETHSS_ETHSW_PORT1 7
#define ETHSS_ETHSW_PORT2 8
#endif
linux-7.2.3/include/dt-bindings/net/ti-dp83867.h
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* Device Tree constants for the Texas Instruments DP83867 PHY
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _DT_BINDINGS_TI_DP83867_H
#define _DT_BINDINGS_TI_DP83867_H
/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
/* RGMIIDCTL internal delay for rx and tx */
#define DP83867_RGMIIDCTL_250_PS 0x0
#define DP83867_RGMIIDCTL_500_PS 0x1
#define DP83867_RGMIIDCTL_750_PS 0x2
#define DP83867_RGMIIDCTL_1_NS 0x3
#define DP83867_RGMIIDCTL_1_25_NS 0x4
#define DP83867_RGMIIDCTL_1_50_NS 0x5
#define DP83867_RGMIIDCTL_1_75_NS 0x6
#define DP83867_RGMIIDCTL_2_00_NS 0x7
#define DP83867_RGMIIDCTL_2_25_NS 0x8
#define DP83867_RGMIIDCTL_2_50_NS 0x9
#define DP83867_RGMIIDCTL_2_75_NS 0xa
#define DP83867_RGMIIDCTL_3_00_NS 0xb
#define DP83867_RGMIIDCTL_3_25_NS 0xc
#define DP83867_RGMIIDCTL_3_50_NS 0xd
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
#define DP83867_CLK_O_SEL_REF_CLK 0xC
/* Special flag to indicate clock should be off */
#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
#endif
linux-7.2.3/include/dt-bindings/net/ti-dp83869.h
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* Device Tree constants for the Texas Instruments DP83869 PHY
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _DT_BINDINGS_TI_DP83869_H
#define _DT_BINDINGS_TI_DP83869_H
/* PHY CTRL bits */
#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
/* IO_MUX_CFG - Clock output selection */
#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1
#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2
#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3
#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8
#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9
#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa
#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb
#define DP83869_CLK_O_SEL_REF_CLK 0xc
#define DP83869_RGMII_COPPER_ETHERNET 0x00
#define DP83869_RGMII_1000_BASE 0x01
#define DP83869_RGMII_100_BASE 0x02
#define DP83869_RGMII_SGMII_BRIDGE 0x03
#define DP83869_1000M_MEDIA_CONVERT 0x04
#define DP83869_100M_MEDIA_CONVERT 0x05
#define DP83869_SGMII_COPPER_ETHERNET 0x06
#endif