Resguardo inicial

This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for the LM90 thermal bindings.
*/
#ifndef _DT_BINDINGS_THERMAL_LM90_H_
#define _DT_BINDINGS_THERMAL_LM90_H_
#define LM90_LOCAL_TEMPERATURE 0
#define LM90_REMOTE_TEMPERATURE 1
#define LM90_REMOTE2_TEMPERATURE 2
#endif
@@ -0,0 +1,112 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Balsam CHIHI <bchihi@baylibre.com>
*/
#ifndef __MEDIATEK_LVTS_DT_H
#define __MEDIATEK_LVTS_DT_H
#define MT7987_CPU 0
#define MT7987_ETH2P5G 1
#define MT7988_CPU_0 0
#define MT7988_CPU_1 1
#define MT7988_ETH2P5G_0 2
#define MT7988_ETH2P5G_1 3
#define MT7988_TOPS_0 4
#define MT7988_TOPS_1 5
#define MT7988_ETHWARP_0 6
#define MT7988_ETHWARP_1 7
#define MT8186_LITTLE_CPU0 0
#define MT8186_LITTLE_CPU1 1
#define MT8186_LITTLE_CPU2 2
#define MT8186_CAM 3
#define MT8186_BIG_CPU0 4
#define MT8186_BIG_CPU1 5
#define MT8186_NNA 6
#define MT8186_ADSP 7
#define MT8186_GPU 8
#define MT8188_MCU_LITTLE_CPU0 0
#define MT8188_MCU_LITTLE_CPU1 1
#define MT8188_MCU_LITTLE_CPU2 2
#define MT8188_MCU_LITTLE_CPU3 3
#define MT8188_MCU_BIG_CPU0 4
#define MT8188_MCU_BIG_CPU1 5
#define MT8188_AP_APU 0
#define MT8188_AP_GPU0 1
#define MT8188_AP_GPU1 2
#define MT8188_AP_ADSP 3
#define MT8188_AP_VDO 4
#define MT8188_AP_INFRA 5
#define MT8188_AP_CAM1 6
#define MT8188_AP_CAM2 7
#define MT8195_MCU_BIG_CPU0 0
#define MT8195_MCU_BIG_CPU1 1
#define MT8195_MCU_BIG_CPU2 2
#define MT8195_MCU_BIG_CPU3 3
#define MT8195_MCU_LITTLE_CPU0 4
#define MT8195_MCU_LITTLE_CPU1 5
#define MT8195_MCU_LITTLE_CPU2 6
#define MT8195_MCU_LITTLE_CPU3 7
#define MT8195_AP_VPU0 8
#define MT8195_AP_VPU1 9
#define MT8195_AP_GPU0 10
#define MT8195_AP_GPU1 11
#define MT8195_AP_VDEC 12
#define MT8195_AP_IMG 13
#define MT8195_AP_INFRA 14
#define MT8195_AP_CAM0 15
#define MT8195_AP_CAM1 16
#define MT8192_MCU_BIG_CPU0 0
#define MT8192_MCU_BIG_CPU1 1
#define MT8192_MCU_BIG_CPU2 2
#define MT8192_MCU_BIG_CPU3 3
#define MT8192_MCU_LITTLE_CPU0 4
#define MT8192_MCU_LITTLE_CPU1 5
#define MT8192_MCU_LITTLE_CPU2 6
#define MT8192_MCU_LITTLE_CPU3 7
#define MT8192_AP_VPU0 8
#define MT8192_AP_VPU1 9
#define MT8192_AP_GPU0 10
#define MT8192_AP_GPU1 11
#define MT8192_AP_INFRA 12
#define MT8192_AP_CAM 13
#define MT8192_AP_MD0 14
#define MT8192_AP_MD1 15
#define MT8192_AP_MD2 16
#define MT8196_MCU_MEDIUM_CPU6_0 0
#define MT8196_MCU_MEDIUM_CPU6_1 1
#define MT8196_MCU_DSU2 2
#define MT8196_MCU_DSU3 3
#define MT8196_MCU_LITTLE_CPU3 4
#define MT8196_MCU_LITTLE_CPU0 5
#define MT8196_MCU_LITTLE_CPU1 6
#define MT8196_MCU_LITTLE_CPU2 7
#define MT8196_MCU_MEDIUM_CPU4_0 8
#define MT8196_MCU_MEDIUM_CPU4_1 9
#define MT8196_MCU_MEDIUM_CPU5_0 10
#define MT8196_MCU_MEDIUM_CPU5_1 11
#define MT8196_MCU_DSU0 12
#define MT8196_MCU_DSU1 13
#define MT8196_MCU_BIG_CPU7_0 14
#define MT8196_MCU_BIG_CPU7_1 15
#define MT8196_AP_TOP0 0
#define MT8196_AP_TOP1 1
#define MT8196_AP_TOP2 2
#define MT8196_AP_TOP3 3
#define MT8196_AP_BOT0 4
#define MT8196_AP_BOT1 5
#define MT8196_AP_BOT2 6
#define MT8196_AP_BOT3 7
#endif /* __MEDIATEK_LVTS_DT_H */
@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for binding nvidia,tegra114-soctherm.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA114_SOCTHERM_H
#define _DT_BINDINGS_THERMAL_TEGRA114_SOCTHERM_H
#define TEGRA114_SOCTHERM_SENSOR_CPU 0
#define TEGRA114_SOCTHERM_SENSOR_MEM 1
#define TEGRA114_SOCTHERM_SENSOR_GPU 2
#define TEGRA114_SOCTHERM_SENSOR_PLLX 3
#define TEGRA114_SOCTHERM_THROT_LEVEL_NONE 0
#define TEGRA114_SOCTHERM_THROT_LEVEL_LOW 1
#define TEGRA114_SOCTHERM_THROT_LEVEL_MED 2
#define TEGRA114_SOCTHERM_THROT_LEVEL_HIGH 3
#endif
@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for binding nvidia,tegra124-soctherm.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
#define TEGRA124_SOCTHERM_SENSOR_CPU 0
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0
#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1
#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2
#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3
#endif
@@ -0,0 +1,14 @@
/*
* This header provides constants for binding nvidia,tegra186-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H
#define TEGRA186_BPMP_THERMAL_ZONE_CPU 2
#define TEGRA186_BPMP_THERMAL_ZONE_GPU 3
#define TEGRA186_BPMP_THERMAL_ZONE_AUX 4
#define TEGRA186_BPMP_THERMAL_ZONE_PLLX 5
#define TEGRA186_BPMP_THERMAL_ZONE_AO 6
#endif
@@ -0,0 +1,15 @@
/*
* This header provides constants for binding nvidia,tegra194-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2
#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3
#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4
#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5
#define TEGRA194_BPMP_THERMAL_ZONE_AO 6
#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7
#endif
@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for binding nvidia,tegra234-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
#define TEGRA234_BPMP_THERMAL_ZONE_CPU 0
#define TEGRA234_BPMP_THERMAL_ZONE_GPU 1
#define TEGRA234_BPMP_THERMAL_ZONE_CV0 2
#define TEGRA234_BPMP_THERMAL_ZONE_CV1 3
#define TEGRA234_BPMP_THERMAL_ZONE_CV2 4
#define TEGRA234_BPMP_THERMAL_ZONE_SOC0 5
#define TEGRA234_BPMP_THERMAL_ZONE_SOC1 6
#define TEGRA234_BPMP_THERMAL_ZONE_SOC2 7
#define TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX 8
#endif
@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides constants for most thermal bindings.
*
* Copyright (C) 2013 Texas Instruments
* Eduardo Valentin <eduardo.valentin@ti.com>
*/
#ifndef _DT_BINDINGS_THERMAL_THERMAL_H
#define _DT_BINDINGS_THERMAL_THERMAL_H
/* On cooling devices upper and lower limits */
#define THERMAL_NO_LIMIT (~0)
#endif
@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* thermal_exynos.h - Samsung Exynos TMU device tree definitions
*
* Copyright (C) 2014 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*/
#ifndef _EXYNOS_THERMAL_TMU_DT_H
#define _EXYNOS_THERMAL_TMU_DT_H
#define TYPE_ONE_POINT_TRIMMING 0
#define TYPE_ONE_POINT_TRIMMING_25 1
#define TYPE_ONE_POINT_TRIMMING_85 2
#define TYPE_TWO_POINT_TRIMMING 3
#define TYPE_NONE 4
#endif /* _EXYNOS_THERMAL_TMU_DT_H */