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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/include/linux/mfd/samsung/core.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_SEC_CORE_H
#define __LINUX_MFD_SEC_CORE_H
/* Macros to represent minimum voltages for LDO/BUCK */
#define MIN_3000_MV 3000000
#define MIN_2500_MV 2500000
#define MIN_2000_MV 2000000
#define MIN_1800_MV 1800000
#define MIN_1500_MV 1500000
#define MIN_1400_MV 1400000
#define MIN_1000_MV 1000000
#define MIN_900_MV 900000
#define MIN_850_MV 850000
#define MIN_800_MV 800000
#define MIN_750_MV 750000
#define MIN_650_MV 650000
#define MIN_600_MV 600000
#define MIN_500_MV 500000
/* Ramp delay in uV/us */
#define RAMP_DELAY_12_MVUS 12000
/* Macros to represent steps for LDO/BUCK */
#define STEP_50_MV 50000
#define STEP_25_MV 25000
#define STEP_12_5_MV 12500
#define STEP_6_25_MV 6250
struct gpio_desc;
enum sec_device_type {
S5M8767X,
S2DOS05,
S2MPA01,
S2MPG10,
S2MPG11,
S2MPS11X,
S2MPS13X,
S2MPS14X,
S2MPS15X,
S2MPU02,
S2MPU05,
S2MU005,
};
/**
* struct sec_pmic_dev - s2m/s5m master device for sub-drivers
* @dev: Master device of the chip
* @pdata: Platform data populated with data from DTS
* or board files
* @regmap_pmic: Regmap associated with PMIC's I2C address
* @i2c: I2C client of the main driver
* @device_type: Type of device, matches enum sec_device_type
* @irq_base: Base IRQ number for device, required for IRQs
* @irq: Generic IRQ number for device
* @irq_data: Runtime data structure for IRQ controller
* @wakeup: Whether or not this is a wakeup device
*/
struct sec_pmic_dev {
struct device *dev;
struct sec_platform_data *pdata;
struct regmap *regmap_pmic;
struct i2c_client *i2c;
int device_type;
int irq;
};
struct sec_platform_data {
struct sec_regulator_data *regulators;
struct sec_opmode_data *opmode;
int num_regulators;
int buck_gpios[3];
int buck_ds[3];
unsigned int buck2_voltage[8];
bool buck2_gpiodvs;
unsigned int buck3_voltage[8];
bool buck3_gpiodvs;
unsigned int buck4_voltage[8];
bool buck4_gpiodvs;
int buck_default_idx;
int buck_ramp_delay;
bool buck2_ramp_enable;
bool buck3_ramp_enable;
bool buck4_ramp_enable;
int buck2_init;
int buck3_init;
int buck4_init;
/* Whether or not manually set PWRHOLD to low during shutdown. */
bool manual_poweroff;
/* Disable the WRSTBI (buck voltage warm reset) when probing? */
bool disable_wrstbi;
};
/**
* sec_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct sec_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
struct gpio_desc *ext_control_gpiod;
};
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
struct sec_opmode_data {
int id;
unsigned int mode;
};
/*
* samsung regulator operation mode
* SEC_OPMODE_OFF Regulator always OFF
* SEC_OPMODE_ON Regulator always ON
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
* If PWREN is high, regulator is on
* If PWREN is low, regulator is off
*/
enum sec_opmode {
SEC_OPMODE_OFF,
SEC_OPMODE_ON,
SEC_OPMODE_LOWPOWER,
SEC_OPMODE_SUSPEND,
};
#endif /* __LINUX_MFD_SEC_CORE_H */
linux-7.2.3/include/linux/mfd/samsung/irq.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_SEC_IRQ_H
#define __LINUX_MFD_SEC_IRQ_H
enum s2mpa01_irq {
S2MPA01_IRQ_PWRONF,
S2MPA01_IRQ_PWRONR,
S2MPA01_IRQ_JIGONBF,
S2MPA01_IRQ_JIGONBR,
S2MPA01_IRQ_ACOKBF,
S2MPA01_IRQ_ACOKBR,
S2MPA01_IRQ_PWRON1S,
S2MPA01_IRQ_MRB,
S2MPA01_IRQ_RTC60S,
S2MPA01_IRQ_RTCA1,
S2MPA01_IRQ_RTCA0,
S2MPA01_IRQ_SMPL,
S2MPA01_IRQ_RTC1S,
S2MPA01_IRQ_WTSR,
S2MPA01_IRQ_INT120C,
S2MPA01_IRQ_INT140C,
S2MPA01_IRQ_LDO3_TSD,
S2MPA01_IRQ_B16_TSD,
S2MPA01_IRQ_B24_TSD,
S2MPA01_IRQ_B35_TSD,
S2MPA01_IRQ_NR,
};
#define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
#define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPA01_IRQ_MRB_MASK (1 << 7)
#define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
#define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
#define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
#define S2MPA01_IRQ_SMPL_MASK (1 << 3)
#define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
#define S2MPA01_IRQ_WTSR_MASK (1 << 5)
#define S2MPA01_IRQ_INT120C_MASK (1 << 0)
#define S2MPA01_IRQ_INT140C_MASK (1 << 1)
#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
enum s2mpg10_common_irq {
/* Top-level (common) block */
S2MPG10_COMMON_IRQ_PMIC,
S2MPG10_COMMON_IRQ_UNUSED,
};
enum s2mpg10_irq {
/* PMIC */
S2MPG10_IRQ_PWRONF,
S2MPG10_IRQ_PWRONR,
S2MPG10_IRQ_JIGONBF,
S2MPG10_IRQ_JIGONBR,
S2MPG10_IRQ_ACOKBF,
S2MPG10_IRQ_ACOKBR,
S2MPG10_IRQ_PWRON1S,
S2MPG10_IRQ_MRB,
#define S2MPG10_IRQ_PWRONF_MASK BIT(0)
#define S2MPG10_IRQ_PWRONR_MASK BIT(1)
#define S2MPG10_IRQ_JIGONBF_MASK BIT(2)
#define S2MPG10_IRQ_JIGONBR_MASK BIT(3)
#define S2MPG10_IRQ_ACOKBF_MASK BIT(4)
#define S2MPG10_IRQ_ACOKBR_MASK BIT(5)
#define S2MPG10_IRQ_PWRON1S_MASK BIT(6)
#define S2MPG10_IRQ_MRB_MASK BIT(7)
S2MPG10_IRQ_RTC60S,
S2MPG10_IRQ_RTCA1,
S2MPG10_IRQ_RTCA0,
S2MPG10_IRQ_RTC1S,
S2MPG10_IRQ_WTSR_COLDRST,
S2MPG10_IRQ_WTSR,
S2MPG10_IRQ_WRST,
S2MPG10_IRQ_SMPL,
#define S2MPG10_IRQ_RTC60S_MASK BIT(0)
#define S2MPG10_IRQ_RTCA1_MASK BIT(1)
#define S2MPG10_IRQ_RTCA0_MASK BIT(2)
#define S2MPG10_IRQ_RTC1S_MASK BIT(3)
#define S2MPG10_IRQ_WTSR_COLDRST_MASK BIT(4)
#define S2MPG10_IRQ_WTSR_MASK BIT(5)
#define S2MPG10_IRQ_WRST_MASK BIT(6)
#define S2MPG10_IRQ_SMPL_MASK BIT(7)
S2MPG10_IRQ_120C,
S2MPG10_IRQ_140C,
S2MPG10_IRQ_TSD,
S2MPG10_IRQ_PIF_TIMEOUT1,
S2MPG10_IRQ_PIF_TIMEOUT2,
S2MPG10_IRQ_SPD_PARITY_ERR,
S2MPG10_IRQ_SPD_ABNORMAL_STOP,
S2MPG10_IRQ_PMETER_OVERF,
#define S2MPG10_IRQ_INT120C_MASK BIT(0)
#define S2MPG10_IRQ_INT140C_MASK BIT(1)
#define S2MPG10_IRQ_TSD_MASK BIT(2)
#define S2MPG10_IRQ_PIF_TIMEOUT1_MASK BIT(3)
#define S2MPG10_IRQ_PIF_TIMEOUT2_MASK BIT(4)
#define S2MPG10_IRQ_SPD_PARITY_ERR_MASK BIT(5)
#define S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
#define S2MPG10_IRQ_PMETER_OVERF_MASK BIT(7)
S2MPG10_IRQ_OCP_B1M,
S2MPG10_IRQ_OCP_B2M,
S2MPG10_IRQ_OCP_B3M,
S2MPG10_IRQ_OCP_B4M,
S2MPG10_IRQ_OCP_B5M,
S2MPG10_IRQ_OCP_B6M,
S2MPG10_IRQ_OCP_B7M,
S2MPG10_IRQ_OCP_B8M,
#define S2MPG10_IRQ_OCP_B1M_MASK BIT(0)
#define S2MPG10_IRQ_OCP_B2M_MASK BIT(1)
#define S2MPG10_IRQ_OCP_B3M_MASK BIT(2)
#define S2MPG10_IRQ_OCP_B4M_MASK BIT(3)
#define S2MPG10_IRQ_OCP_B5M_MASK BIT(4)
#define S2MPG10_IRQ_OCP_B6M_MASK BIT(5)
#define S2MPG10_IRQ_OCP_B7M_MASK BIT(6)
#define S2MPG10_IRQ_OCP_B8M_MASK BIT(7)
S2MPG10_IRQ_OCP_B9M,
S2MPG10_IRQ_OCP_B10M,
S2MPG10_IRQ_WLWP_ACC,
S2MPG10_IRQ_SMPL_TIMEOUT,
S2MPG10_IRQ_WTSR_TIMEOUT,
S2MPG10_IRQ_SPD_SRP_PKT_RST,
#define S2MPG10_IRQ_OCP_B9M_MASK BIT(0)
#define S2MPG10_IRQ_OCP_B10M_MASK BIT(1)
#define S2MPG10_IRQ_WLWP_ACC_MASK BIT(2)
#define S2MPG10_IRQ_SMPL_TIMEOUT_MASK BIT(5)
#define S2MPG10_IRQ_WTSR_TIMEOUT_MASK BIT(6)
#define S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
S2MPG10_IRQ_PWR_WARN_CH0,
S2MPG10_IRQ_PWR_WARN_CH1,
S2MPG10_IRQ_PWR_WARN_CH2,
S2MPG10_IRQ_PWR_WARN_CH3,
S2MPG10_IRQ_PWR_WARN_CH4,
S2MPG10_IRQ_PWR_WARN_CH5,
S2MPG10_IRQ_PWR_WARN_CH6,
S2MPG10_IRQ_PWR_WARN_CH7,
#define S2MPG10_IRQ_PWR_WARN_CH0_MASK BIT(0)
#define S2MPG10_IRQ_PWR_WARN_CH1_MASK BIT(1)
#define S2MPG10_IRQ_PWR_WARN_CH2_MASK BIT(2)
#define S2MPG10_IRQ_PWR_WARN_CH3_MASK BIT(3)
#define S2MPG10_IRQ_PWR_WARN_CH4_MASK BIT(4)
#define S2MPG10_IRQ_PWR_WARN_CH5_MASK BIT(5)
#define S2MPG10_IRQ_PWR_WARN_CH6_MASK BIT(6)
#define S2MPG10_IRQ_PWR_WARN_CH7_MASK BIT(7)
S2MPG10_IRQ_NR,
};
enum s2mpg11_common_irq {
/* Top-level (common) block */
S2MPG11_COMMON_IRQ_PMIC,
S2MPG11_COMMON_IRQ_UNUSED,
};
enum s2mpg11_irq {
/* PMIC */
S2MPG11_IRQ_PWRONF,
S2MPG11_IRQ_PWRONR,
S2MPG11_IRQ_PIF_TIMEOUT_MIF,
S2MPG11_IRQ_PIF_TIMEOUTS,
S2MPG11_IRQ_WTSR,
S2MPG11_IRQ_SPD_ABNORMAL_STOP,
S2MPG11_IRQ_SPD_PARITY_ERR,
#define S2MPG11_IRQ_PWRONF_MASK BIT(0)
#define S2MPG11_IRQ_PWRONR_MASK BIT(1)
#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3)
#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4)
#define S2MPG11_IRQ_WTSR_MASK BIT(5)
#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7)
S2MPG11_IRQ_140C,
S2MPG11_IRQ_120C,
S2MPG11_IRQ_TSD,
S2MPG11_IRQ_WRST,
S2MPG11_IRQ_NTC_CYCLE_DONE,
S2MPG11_IRQ_PMETER_OVERF,
#define S2MPG11_IRQ_INT140C_MASK BIT(0)
#define S2MPG11_IRQ_INT120C_MASK BIT(1)
#define S2MPG11_IRQ_TSD_MASK BIT(2)
#define S2MPG11_IRQ_WRST_MASK BIT(5)
#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6)
#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7)
S2MPG11_IRQ_OCP_B1S,
S2MPG11_IRQ_OCP_B2S,
S2MPG11_IRQ_OCP_B3S,
S2MPG11_IRQ_OCP_B4S,
S2MPG11_IRQ_OCP_B5S,
S2MPG11_IRQ_OCP_B6S,
S2MPG11_IRQ_OCP_B7S,
S2MPG11_IRQ_OCP_B8S,
#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0)
#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1)
#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2)
#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3)
#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4)
#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5)
#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6)
#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7)
S2MPG11_IRQ_OCP_B9S,
S2MPG11_IRQ_OCP_B10S,
S2MPG11_IRQ_OCP_BDS,
S2MPG11_IRQ_OCP_BAS,
S2MPG11_IRQ_OCP_BBS,
S2MPG11_IRQ_WLWP_ACC,
S2MPG11_IRQ_SPD_SRP_PKT_RST,
#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0)
#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1)
#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2)
#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3)
#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4)
#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5)
#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
S2MPG11_IRQ_PWR_WARN_CH0,
S2MPG11_IRQ_PWR_WARN_CH1,
S2MPG11_IRQ_PWR_WARN_CH2,
S2MPG11_IRQ_PWR_WARN_CH3,
S2MPG11_IRQ_PWR_WARN_CH4,
S2MPG11_IRQ_PWR_WARN_CH5,
S2MPG11_IRQ_PWR_WARN_CH6,
S2MPG11_IRQ_PWR_WARN_CH7,
#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0)
#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1)
#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2)
#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3)
#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4)
#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5)
#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6)
#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7)
S2MPG11_IRQ_NTC_WARN_CH0,
S2MPG11_IRQ_NTC_WARN_CH1,
S2MPG11_IRQ_NTC_WARN_CH2,
S2MPG11_IRQ_NTC_WARN_CH3,
S2MPG11_IRQ_NTC_WARN_CH4,
S2MPG11_IRQ_NTC_WARN_CH5,
S2MPG11_IRQ_NTC_WARN_CH6,
S2MPG11_IRQ_NTC_WARN_CH7,
#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0)
#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1)
#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2)
#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3)
#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4)
#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5)
#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6)
#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7)
S2MPG11_IRQ_NR,
};
enum s2mps11_irq {
S2MPS11_IRQ_PWRONF,
S2MPS11_IRQ_PWRONR,
S2MPS11_IRQ_JIGONBF,
S2MPS11_IRQ_JIGONBR,
S2MPS11_IRQ_ACOKBF,
S2MPS11_IRQ_ACOKBR,
S2MPS11_IRQ_PWRON1S,
S2MPS11_IRQ_MRB,
S2MPS11_IRQ_RTC60S,
S2MPS11_IRQ_RTCA1,
S2MPS11_IRQ_RTCA0,
S2MPS11_IRQ_SMPL,
S2MPS11_IRQ_RTC1S,
S2MPS11_IRQ_WTSR,
S2MPS11_IRQ_INT120C,
S2MPS11_IRQ_INT140C,
S2MPS11_IRQ_NR,
};
#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPS11_IRQ_MRB_MASK (1 << 7)
#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
enum s2mps14_irq {
S2MPS14_IRQ_PWRONF,
S2MPS14_IRQ_PWRONR,
S2MPS14_IRQ_JIGONBF,
S2MPS14_IRQ_JIGONBR,
S2MPS14_IRQ_ACOKBF,
S2MPS14_IRQ_ACOKBR,
S2MPS14_IRQ_PWRON1S,
S2MPS14_IRQ_MRB,
S2MPS14_IRQ_RTC60S,
S2MPS14_IRQ_RTCA1,
S2MPS14_IRQ_RTCA0,
S2MPS14_IRQ_SMPL,
S2MPS14_IRQ_RTC1S,
S2MPS14_IRQ_WTSR,
S2MPS14_IRQ_INT120C,
S2MPS14_IRQ_INT140C,
S2MPS14_IRQ_TSD,
S2MPS14_IRQ_NR,
};
enum s2mpu02_irq {
S2MPU02_IRQ_PWRONF,
S2MPU02_IRQ_PWRONR,
S2MPU02_IRQ_JIGONBF,
S2MPU02_IRQ_JIGONBR,
S2MPU02_IRQ_ACOKBF,
S2MPU02_IRQ_ACOKBR,
S2MPU02_IRQ_PWRON1S,
S2MPU02_IRQ_MRB,
S2MPU02_IRQ_RTC60S,
S2MPU02_IRQ_RTCA1,
S2MPU02_IRQ_RTCA0,
S2MPU02_IRQ_SMPL,
S2MPU02_IRQ_RTC1S,
S2MPU02_IRQ_WTSR,
S2MPU02_IRQ_INT120C,
S2MPU02_IRQ_INT140C,
S2MPU02_IRQ_TSD,
S2MPU02_IRQ_NR,
};
/* Masks for interrupts are the same as in s2mps11 */
#define S2MPS14_IRQ_TSD_MASK (1 << 2)
enum s2mpu05_irq {
S2MPU05_IRQ_PWRONF,
S2MPU05_IRQ_PWRONR,
S2MPU05_IRQ_JIGONBF,
S2MPU05_IRQ_JIGONBR,
S2MPU05_IRQ_ACOKF,
S2MPU05_IRQ_ACOKR,
S2MPU05_IRQ_PWRON1S,
S2MPU05_IRQ_MRB,
S2MPU05_IRQ_RTC60S,
S2MPU05_IRQ_RTCA1,
S2MPU05_IRQ_RTCA0,
S2MPU05_IRQ_SMPL,
S2MPU05_IRQ_RTC1S,
S2MPU05_IRQ_WTSR,
S2MPU05_IRQ_INT120C,
S2MPU05_IRQ_INT140C,
S2MPU05_IRQ_TSD,
S2MPU05_IRQ_NR,
};
#define S2MPU05_IRQ_PWRONF_MASK BIT(0)
#define S2MPU05_IRQ_PWRONR_MASK BIT(1)
#define S2MPU05_IRQ_JIGONBF_MASK BIT(2)
#define S2MPU05_IRQ_JIGONBR_MASK BIT(3)
#define S2MPU05_IRQ_ACOKF_MASK BIT(4)
#define S2MPU05_IRQ_ACOKR_MASK BIT(5)
#define S2MPU05_IRQ_PWRON1S_MASK BIT(6)
#define S2MPU05_IRQ_MRB_MASK BIT(7)
#define S2MPU05_IRQ_RTC60S_MASK BIT(0)
#define S2MPU05_IRQ_RTCA1_MASK BIT(1)
#define S2MPU05_IRQ_RTCA0_MASK BIT(2)
#define S2MPU05_IRQ_SMPL_MASK BIT(3)
#define S2MPU05_IRQ_RTC1S_MASK BIT(4)
#define S2MPU05_IRQ_WTSR_MASK BIT(5)
#define S2MPU05_IRQ_INT120C_MASK BIT(0)
#define S2MPU05_IRQ_INT140C_MASK BIT(1)
#define S2MPU05_IRQ_TSD_MASK BIT(2)
enum s2mu005_irq {
S2MU005_IRQ_CHGR_DETBAT,
S2MU005_IRQ_CHGR_BAT,
S2MU005_IRQ_CHGR_IVR,
S2MU005_IRQ_CHGR_EVENT,
S2MU005_IRQ_CHGR_CHG,
S2MU005_IRQ_CHGR_VMID,
S2MU005_IRQ_CHGR_WCIN,
S2MU005_IRQ_CHGR_VBUS,
S2MU005_IRQ_FLED_LBPROT,
S2MU005_IRQ_FLED_OPENCH2,
S2MU005_IRQ_FLED_OPENCH1,
S2MU005_IRQ_FLED_SHORTCH2,
S2MU005_IRQ_FLED_SHORTCH1,
S2MU005_IRQ_MUIC_ATTACH,
S2MU005_IRQ_MUIC_DETACH,
S2MU005_IRQ_MUIC_KP,
S2MU005_IRQ_MUIC_LKP,
S2MU005_IRQ_MUIC_LKR,
S2MU005_IRQ_MUIC_RIDCHG,
S2MU005_IRQ_MUIC_VBUSON,
S2MU005_IRQ_MUIC_RSVD,
S2MU005_IRQ_MUIC_ADC,
S2MU005_IRQ_MUIC_STUCK,
S2MU005_IRQ_MUIC_STUCKRCV,
S2MU005_IRQ_MUIC_MHDL,
S2MU005_IRQ_MUIC_AVCHG,
S2MU005_IRQ_MUIC_VBUSOFF,
S2MU005_IRQ_NR,
};
#define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0)
#define S2MU005_IRQ_CHGR_BAT_MASK BIT(1)
#define S2MU005_IRQ_CHGR_IVR_MASK BIT(2)
#define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3)
#define S2MU005_IRQ_CHGR_CHG_MASK BIT(4)
#define S2MU005_IRQ_CHGR_VMID_MASK BIT(5)
#define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6)
#define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7)
#define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2)
#define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4)
#define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5)
#define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6)
#define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7)
#define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0)
#define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1)
#define S2MU005_IRQ_MUIC_KP_MASK BIT(2)
#define S2MU005_IRQ_MUIC_LKP_MASK BIT(3)
#define S2MU005_IRQ_MUIC_LKR_MASK BIT(4)
#define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5)
#define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0)
#define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1)
#define S2MU005_IRQ_MUIC_ADC_MASK BIT(2)
#define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3)
#define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4)
#define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5)
#define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6)
#define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7)
enum s5m8767_irq {
S5M8767_IRQ_PWRR,
S5M8767_IRQ_PWRF,
S5M8767_IRQ_PWR1S,
S5M8767_IRQ_JIGR,
S5M8767_IRQ_JIGF,
S5M8767_IRQ_LOWBAT2,
S5M8767_IRQ_LOWBAT1,
S5M8767_IRQ_MRB,
S5M8767_IRQ_DVSOK2,
S5M8767_IRQ_DVSOK3,
S5M8767_IRQ_DVSOK4,
S5M8767_IRQ_RTC60S,
S5M8767_IRQ_RTCA1,
S5M8767_IRQ_RTCA2,
S5M8767_IRQ_SMPL,
S5M8767_IRQ_RTC1S,
S5M8767_IRQ_WTSR,
S5M8767_IRQ_NR,
};
#define S5M8767_IRQ_PWRR_MASK (1 << 0)
#define S5M8767_IRQ_PWRF_MASK (1 << 1)
#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
#define S5M8767_IRQ_JIGR_MASK (1 << 4)
#define S5M8767_IRQ_JIGF_MASK (1 << 5)
#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
#define S5M8767_IRQ_MRB_MASK (1 << 2)
#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
#define S5M8767_IRQ_SMPL_MASK (1 << 3)
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
#endif /* __LINUX_MFD_SEC_IRQ_H */
linux-7.2.3/include/linux/mfd/samsung/rtc.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_SEC_RTC_H
#define __LINUX_MFD_SEC_RTC_H
enum s5m_rtc_reg {
S5M_RTC_SEC,
S5M_RTC_MIN,
S5M_RTC_HOUR,
S5M_RTC_WEEKDAY,
S5M_RTC_DATE,
S5M_RTC_MONTH,
S5M_RTC_YEAR1,
S5M_RTC_YEAR2,
S5M_ALARM0_SEC,
S5M_ALARM0_MIN,
S5M_ALARM0_HOUR,
S5M_ALARM0_WEEKDAY,
S5M_ALARM0_DATE,
S5M_ALARM0_MONTH,
S5M_ALARM0_YEAR1,
S5M_ALARM0_YEAR2,
S5M_ALARM1_SEC,
S5M_ALARM1_MIN,
S5M_ALARM1_HOUR,
S5M_ALARM1_WEEKDAY,
S5M_ALARM1_DATE,
S5M_ALARM1_MONTH,
S5M_ALARM1_YEAR1,
S5M_ALARM1_YEAR2,
S5M_ALARM0_CONF,
S5M_ALARM1_CONF,
S5M_RTC_STATUS,
S5M_WTSR_SMPL_CNTL,
S5M_RTC_UDR_CON,
S5M_RTC_REG_MAX,
};
enum s2mps_rtc_reg {
S2MPS_RTC_CTRL,
S2MPS_WTSR_SMPL_CNTL,
S2MPS_RTC_UDR_CON,
S2MPS_RSVD,
S2MPS_RTC_SEC,
S2MPS_RTC_MIN,
S2MPS_RTC_HOUR,
S2MPS_RTC_WEEKDAY,
S2MPS_RTC_DATE,
S2MPS_RTC_MONTH,
S2MPS_RTC_YEAR,
S2MPS_ALARM0_SEC,
S2MPS_ALARM0_MIN,
S2MPS_ALARM0_HOUR,
S2MPS_ALARM0_WEEKDAY,
S2MPS_ALARM0_DATE,
S2MPS_ALARM0_MONTH,
S2MPS_ALARM0_YEAR,
S2MPS_ALARM1_SEC,
S2MPS_ALARM1_MIN,
S2MPS_ALARM1_HOUR,
S2MPS_ALARM1_WEEKDAY,
S2MPS_ALARM1_DATE,
S2MPS_ALARM1_MONTH,
S2MPS_ALARM1_YEAR,
S2MPS_OFFSRC,
S2MPS_RTC_REG_MAX,
};
enum s2mpg10_rtc_reg {
S2MPG10_RTC_CTRL,
S2MPG10_RTC_UPDATE,
S2MPG10_RTC_SMPL,
S2MPG10_RTC_WTSR,
S2MPG10_RTC_CAP_SEL,
S2MPG10_RTC_MSEC,
S2MPG10_RTC_SEC,
S2MPG10_RTC_MIN,
S2MPG10_RTC_HOUR,
S2MPG10_RTC_WEEK,
S2MPG10_RTC_DAY,
S2MPG10_RTC_MON,
S2MPG10_RTC_YEAR,
S2MPG10_RTC_A0SEC,
S2MPG10_RTC_A0MIN,
S2MPG10_RTC_A0HOUR,
S2MPG10_RTC_A0WEEK,
S2MPG10_RTC_A0DAY,
S2MPG10_RTC_A0MON,
S2MPG10_RTC_A0YEAR,
S2MPG10_RTC_A1SEC,
S2MPG10_RTC_A1MIN,
S2MPG10_RTC_A1HOUR,
S2MPG10_RTC_A1WEEK,
S2MPG10_RTC_A1DAY,
S2MPG10_RTC_A1MON,
S2MPG10_RTC_A1YEAR,
S2MPG10_RTC_OSC_CTRL,
};
#define RTC_I2C_ADDR (0x0C >> 1)
#define HOUR_12 (1 << 7)
#define HOUR_AMPM (1 << 6)
#define HOUR_PM (1 << 5)
#define S5M_ALARM0_STATUS (1 << 1)
#define S5M_ALARM1_STATUS (1 << 2)
#define S5M_UPDATE_AD (1 << 0)
#define S2MPS_ALARM0_STATUS (1 << 2)
#define S2MPS_ALARM1_STATUS (1 << 1)
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK (1 << MODEL24_SHIFT)
/* RTC Update Register1 */
#define S5M_RTC_UDR_SHIFT 0
#define S5M_RTC_UDR_MASK (1 << S5M_RTC_UDR_SHIFT)
#define S2MPS_RTC_WUDR_SHIFT 4
#define S2MPS_RTC_WUDR_MASK (1 << S2MPS_RTC_WUDR_SHIFT)
#define S2MPS15_RTC_AUDR_SHIFT 4
#define S2MPS15_RTC_AUDR_MASK (1 << S2MPS15_RTC_AUDR_SHIFT)
#define S2MPS13_RTC_AUDR_SHIFT 1
#define S2MPS13_RTC_AUDR_MASK (1 << S2MPS13_RTC_AUDR_SHIFT)
#define S2MPS15_RTC_WUDR_SHIFT 1
#define S2MPS15_RTC_WUDR_MASK (1 << S2MPS15_RTC_WUDR_SHIFT)
#define S2MPS_RTC_RUDR_SHIFT 0
#define S2MPS_RTC_RUDR_MASK (1 << S2MPS_RTC_RUDR_SHIFT)
#define RTC_TCON_SHIFT 1
#define RTC_TCON_MASK (1 << RTC_TCON_SHIFT)
#define S5M_RTC_TIME_EN_SHIFT 3
#define S5M_RTC_TIME_EN_MASK (1 << S5M_RTC_TIME_EN_SHIFT)
/*
* UDR_T field in S5M_RTC_UDR_CON register determines the time needed
* for updating alarm and time registers. Default is 7.32 ms.
*/
#define S5M_RTC_UDR_T_SHIFT 6
#define S5M_RTC_UDR_T_MASK (0x3 << S5M_RTC_UDR_T_SHIFT)
#define S5M_RTC_UDR_T_7320_US (0x0 << S5M_RTC_UDR_T_SHIFT)
#define S5M_RTC_UDR_T_1830_US (0x1 << S5M_RTC_UDR_T_SHIFT)
#define S5M_RTC_UDR_T_3660_US (0x2 << S5M_RTC_UDR_T_SHIFT)
#define S5M_RTC_UDR_T_450_US (0x3 << S5M_RTC_UDR_T_SHIFT)
/* RTC Hour register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
/* WTSR & SMPL registers */
#define SMPL_ENABLE_SHIFT 7
#define SMPL_ENABLE_MASK (1 << SMPL_ENABLE_SHIFT)
#define WTSR_ENABLE_SHIFT 6
#define WTSR_ENABLE_MASK (1 << WTSR_ENABLE_SHIFT)
#define S2MPG10_WTSR_COLDTIMER GENMASK(6, 5)
#define S2MPG10_WTSR_COLDRST BIT(4)
#define S2MPG10_WTSR_WTSRT GENMASK(3, 1)
#define S2MPG10_WTSR_WTSR_EN BIT(0)
#endif /* __LINUX_MFD_SEC_RTC_H */
linux-7.2.3/include/linux/mfd/samsung/s2mpa01.h
+175
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S2MPA01_H
#define __LINUX_MFD_S2MPA01_H
/* S2MPA01 registers */
enum s2mpa01_reg {
S2MPA01_REG_ID,
S2MPA01_REG_INT1,
S2MPA01_REG_INT2,
S2MPA01_REG_INT3,
S2MPA01_REG_INT1M,
S2MPA01_REG_INT2M,
S2MPA01_REG_INT3M,
S2MPA01_REG_ST1,
S2MPA01_REG_ST2,
S2MPA01_REG_PWRONSRC,
S2MPA01_REG_OFFSRC,
S2MPA01_REG_RTC_BUF,
S2MPA01_REG_CTRL1,
S2MPA01_REG_ETC_TEST,
S2MPA01_REG_RSVD1,
S2MPA01_REG_BU_CHG,
S2MPA01_REG_RAMP1,
S2MPA01_REG_RAMP2,
S2MPA01_REG_LDO_DSCH1,
S2MPA01_REG_LDO_DSCH2,
S2MPA01_REG_LDO_DSCH3,
S2MPA01_REG_LDO_DSCH4,
S2MPA01_REG_OTP_ADRL,
S2MPA01_REG_OTP_ADRH,
S2MPA01_REG_OTP_DATA,
S2MPA01_REG_MON1SEL,
S2MPA01_REG_MON2SEL,
S2MPA01_REG_LEE,
S2MPA01_REG_RSVD2,
S2MPA01_REG_RSVD3,
S2MPA01_REG_RSVD4,
S2MPA01_REG_RSVD5,
S2MPA01_REG_RSVD6,
S2MPA01_REG_TOP_RSVD,
S2MPA01_REG_DVS_SEL,
S2MPA01_REG_DVS_PTR,
S2MPA01_REG_DVS_DATA,
S2MPA01_REG_RSVD_NO,
S2MPA01_REG_UVLO,
S2MPA01_REG_LEE_NO,
S2MPA01_REG_B1CTRL1,
S2MPA01_REG_B1CTRL2,
S2MPA01_REG_B2CTRL1,
S2MPA01_REG_B2CTRL2,
S2MPA01_REG_B3CTRL1,
S2MPA01_REG_B3CTRL2,
S2MPA01_REG_B4CTRL1,
S2MPA01_REG_B4CTRL2,
S2MPA01_REG_B5CTRL1,
S2MPA01_REG_B5CTRL2,
S2MPA01_REG_B5CTRL3,
S2MPA01_REG_B5CTRL4,
S2MPA01_REG_B5CTRL5,
S2MPA01_REG_B5CTRL6,
S2MPA01_REG_B6CTRL1,
S2MPA01_REG_B6CTRL2,
S2MPA01_REG_B7CTRL1,
S2MPA01_REG_B7CTRL2,
S2MPA01_REG_B8CTRL1,
S2MPA01_REG_B8CTRL2,
S2MPA01_REG_B9CTRL1,
S2MPA01_REG_B9CTRL2,
S2MPA01_REG_B10CTRL1,
S2MPA01_REG_B10CTRL2,
S2MPA01_REG_L1CTRL,
S2MPA01_REG_L2CTRL,
S2MPA01_REG_L3CTRL,
S2MPA01_REG_L4CTRL,
S2MPA01_REG_L5CTRL,
S2MPA01_REG_L6CTRL,
S2MPA01_REG_L7CTRL,
S2MPA01_REG_L8CTRL,
S2MPA01_REG_L9CTRL,
S2MPA01_REG_L10CTRL,
S2MPA01_REG_L11CTRL,
S2MPA01_REG_L12CTRL,
S2MPA01_REG_L13CTRL,
S2MPA01_REG_L14CTRL,
S2MPA01_REG_L15CTRL,
S2MPA01_REG_L16CTRL,
S2MPA01_REG_L17CTRL,
S2MPA01_REG_L18CTRL,
S2MPA01_REG_L19CTRL,
S2MPA01_REG_L20CTRL,
S2MPA01_REG_L21CTRL,
S2MPA01_REG_L22CTRL,
S2MPA01_REG_L23CTRL,
S2MPA01_REG_L24CTRL,
S2MPA01_REG_L25CTRL,
S2MPA01_REG_L26CTRL,
S2MPA01_REG_LDO_OVCB1,
S2MPA01_REG_LDO_OVCB2,
S2MPA01_REG_LDO_OVCB3,
S2MPA01_REG_LDO_OVCB4,
};
/* S2MPA01 regulator ids */
enum s2mpa01_regulators {
S2MPA01_LDO1,
S2MPA01_LDO2,
S2MPA01_LDO3,
S2MPA01_LDO4,
S2MPA01_LDO5,
S2MPA01_LDO6,
S2MPA01_LDO7,
S2MPA01_LDO8,
S2MPA01_LDO9,
S2MPA01_LDO10,
S2MPA01_LDO11,
S2MPA01_LDO12,
S2MPA01_LDO13,
S2MPA01_LDO14,
S2MPA01_LDO15,
S2MPA01_LDO16,
S2MPA01_LDO17,
S2MPA01_LDO18,
S2MPA01_LDO19,
S2MPA01_LDO20,
S2MPA01_LDO21,
S2MPA01_LDO22,
S2MPA01_LDO23,
S2MPA01_LDO24,
S2MPA01_LDO25,
S2MPA01_LDO26,
S2MPA01_BUCK1,
S2MPA01_BUCK2,
S2MPA01_BUCK3,
S2MPA01_BUCK4,
S2MPA01_BUCK5,
S2MPA01_BUCK6,
S2MPA01_BUCK7,
S2MPA01_BUCK8,
S2MPA01_BUCK9,
S2MPA01_BUCK10,
S2MPA01_REGULATOR_MAX,
};
#define S2MPA01_LDO_VSEL_MASK 0x3F
#define S2MPA01_BUCK_VSEL_MASK 0xFF
#define S2MPA01_ENABLE_MASK (0x03 << S2MPA01_ENABLE_SHIFT)
#define S2MPA01_ENABLE_SHIFT 0x06
#define S2MPA01_LDO_N_VOLTAGES (S2MPA01_LDO_VSEL_MASK + 1)
#define S2MPA01_BUCK_N_VOLTAGES (S2MPA01_BUCK_VSEL_MASK + 1)
#define S2MPA01_RAMP_DELAY 12500 /* uV/us */
#define S2MPA01_BUCK16_RAMP_SHIFT 4
#define S2MPA01_BUCK24_RAMP_SHIFT 6
#define S2MPA01_BUCK3_RAMP_SHIFT 4
#define S2MPA01_BUCK5_RAMP_SHIFT 6
#define S2MPA01_BUCK7_RAMP_SHIFT 2
#define S2MPA01_BUCK8910_RAMP_SHIFT 0
#define S2MPA01_BUCK1_RAMP_EN_SHIFT 3
#define S2MPA01_BUCK2_RAMP_EN_SHIFT 2
#define S2MPA01_BUCK3_RAMP_EN_SHIFT 1
#define S2MPA01_BUCK4_RAMP_EN_SHIFT 0
#define S2MPA01_PMIC_EN_SHIFT 6
#endif /*__LINUX_MFD_S2MPA01_H */
linux-7.2.3/include/linux/mfd/samsung/s2mpg10.h
+478
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Samsung Electronics
* Copyright 2020 Google Inc
* Copyright 2025 Linaro Ltd.
*/
#ifndef __LINUX_MFD_S2MPG10_H
#define __LINUX_MFD_S2MPG10_H
/* Common registers (type 0x000) */
enum s2mpg10_common_reg {
S2MPG10_COMMON_CHIPID,
S2MPG10_COMMON_INT,
S2MPG10_COMMON_INT_MASK,
S2MPG10_COMMON_SPD_CTRL1 = 0x0a,
S2MPG10_COMMON_SPD_CTRL2,
S2MPG10_COMMON_SPD_CTRL3,
S2MPG10_COMMON_MON1SEL = 0x1a,
S2MPG10_COMMON_MON2SEL,
S2MPG10_COMMON_MONR,
S2MPG10_COMMON_DEBUG_CTRL1,
S2MPG10_COMMON_DEBUG_CTRL2,
S2MPG10_COMMON_DEBUG_CTRL3,
S2MPG10_COMMON_DEBUG_CTRL4,
S2MPG10_COMMON_DEBUG_CTRL5,
S2MPG10_COMMON_DEBUG_CTRL6,
S2MPG10_COMMON_DEBUG_CTRL7,
S2MPG10_COMMON_DEBUG_CTRL8,
S2MPG10_COMMON_TEST_MODE1,
S2MPG10_COMMON_TEST_MODE2,
S2MPG10_COMMON_SPD_DEBUG1,
S2MPG10_COMMON_SPD_DEBUG2,
S2MPG10_COMMON_SPD_DEBUG3,
S2MPG10_COMMON_SPD_DEBUG4,
};
/* For S2MPG10_COMMON_INT and S2MPG10_COMMON_INT_MASK */
#define S2MPG10_COMMON_INT_SRC GENMASK(7, 0)
#define S2MPG10_COMMON_INT_SRC_PMIC BIT(0)
/* PMIC registers (type 0x100) */
enum s2mpg10_pmic_reg {
S2MPG10_PMIC_INT1,
S2MPG10_PMIC_INT2,
S2MPG10_PMIC_INT3,
S2MPG10_PMIC_INT4,
S2MPG10_PMIC_INT5,
S2MPG10_PMIC_INT6,
S2MPG10_PMIC_INT1M,
S2MPG10_PMIC_INT2M,
S2MPG10_PMIC_INT3M,
S2MPG10_PMIC_INT4M,
S2MPG10_PMIC_INT5M,
S2MPG10_PMIC_INT6M,
S2MPG10_PMIC_STATUS1,
S2MPG10_PMIC_STATUS2,
S2MPG10_PMIC_PWRONSRC,
S2MPG10_PMIC_OFFSRC,
S2MPG10_PMIC_BU_CHG,
S2MPG10_PMIC_RTCBUF,
S2MPG10_PMIC_COMMON_CTRL1,
S2MPG10_PMIC_COMMON_CTRL2,
S2MPG10_PMIC_COMMON_CTRL3,
S2MPG10_PMIC_COMMON_CTRL4,
S2MPG10_PMIC_SMPL_WARN_CTRL,
S2MPG10_PMIC_MIMICKING_CTRL,
S2MPG10_PMIC_B1M_CTRL,
S2MPG10_PMIC_B1M_OUT1,
S2MPG10_PMIC_B1M_OUT2,
S2MPG10_PMIC_B2M_CTRL,
S2MPG10_PMIC_B2M_OUT1,
S2MPG10_PMIC_B2M_OUT2,
S2MPG10_PMIC_B3M_CTRL,
S2MPG10_PMIC_B3M_OUT1,
S2MPG10_PMIC_B3M_OUT2,
S2MPG10_PMIC_B4M_CTRL,
S2MPG10_PMIC_B4M_OUT1,
S2MPG10_PMIC_B4M_OUT2,
S2MPG10_PMIC_B5M_CTRL,
S2MPG10_PMIC_B5M_OUT1,
S2MPG10_PMIC_B5M_OUT2,
S2MPG10_PMIC_B6M_CTRL,
S2MPG10_PMIC_B6M_OUT1,
S2MPG10_PMIC_B6M_OUT2,
S2MPG10_PMIC_B7M_CTRL,
S2MPG10_PMIC_B7M_OUT1,
S2MPG10_PMIC_B7M_OUT2,
S2MPG10_PMIC_B8M_CTRL,
S2MPG10_PMIC_B8M_OUT1,
S2MPG10_PMIC_B8M_OUT2,
S2MPG10_PMIC_B9M_CTRL,
S2MPG10_PMIC_B9M_OUT1,
S2MPG10_PMIC_B9M_OUT2,
S2MPG10_PMIC_B10M_CTRL,
S2MPG10_PMIC_B10M_OUT1,
S2MPG10_PMIC_B10M_OUT2,
S2MPG10_PMIC_BUCK1M_USONIC,
S2MPG10_PMIC_BUCK2M_USONIC,
S2MPG10_PMIC_BUCK3M_USONIC,
S2MPG10_PMIC_BUCK4M_USONIC,
S2MPG10_PMIC_BUCK5M_USONIC,
S2MPG10_PMIC_BUCK6M_USONIC,
S2MPG10_PMIC_BUCK7M_USONIC,
S2MPG10_PMIC_BUCK8M_USONIC,
S2MPG10_PMIC_BUCK9M_USONIC,
S2MPG10_PMIC_BUCK10M_USONIC,
S2MPG10_PMIC_L1M_CTRL,
S2MPG10_PMIC_L2M_CTRL,
S2MPG10_PMIC_L3M_CTRL,
S2MPG10_PMIC_L4M_CTRL,
S2MPG10_PMIC_L5M_CTRL,
S2MPG10_PMIC_L6M_CTRL,
S2MPG10_PMIC_L7M_CTRL,
S2MPG10_PMIC_L8M_CTRL,
S2MPG10_PMIC_L9M_CTRL,
S2MPG10_PMIC_L10M_CTRL,
S2MPG10_PMIC_L11M_CTRL1,
S2MPG10_PMIC_L11M_CTRL2,
S2MPG10_PMIC_L12M_CTRL1,
S2MPG10_PMIC_L12M_CTRL2,
S2MPG10_PMIC_L13M_CTRL1,
S2MPG10_PMIC_L13M_CTRL2,
S2MPG10_PMIC_L14M_CTRL,
S2MPG10_PMIC_L15M_CTRL1,
S2MPG10_PMIC_L15M_CTRL2,
S2MPG10_PMIC_L16M_CTRL,
S2MPG10_PMIC_L17M_CTRL,
S2MPG10_PMIC_L18M_CTRL,
S2MPG10_PMIC_L19M_CTRL,
S2MPG10_PMIC_L20M_CTRL,
S2MPG10_PMIC_L21M_CTRL,
S2MPG10_PMIC_L22M_CTRL,
S2MPG10_PMIC_L23M_CTRL,
S2MPG10_PMIC_L24M_CTRL,
S2MPG10_PMIC_L25M_CTRL,
S2MPG10_PMIC_L26M_CTRL,
S2MPG10_PMIC_L27M_CTRL,
S2MPG10_PMIC_L28M_CTRL,
S2MPG10_PMIC_L29M_CTRL,
S2MPG10_PMIC_L30M_CTRL,
S2MPG10_PMIC_L31M_CTRL,
S2MPG10_PMIC_LDO_CTRL1,
S2MPG10_PMIC_LDO_CTRL2,
S2MPG10_PMIC_LDO_DSCH1,
S2MPG10_PMIC_LDO_DSCH2,
S2MPG10_PMIC_LDO_DSCH3,
S2MPG10_PMIC_LDO_DSCH4,
S2MPG10_PMIC_LDO_BUCK7M_HLIMIT,
S2MPG10_PMIC_LDO_BUCK7M_LLIMIT,
S2MPG10_PMIC_LDO_LDO21M_HLIMIT,
S2MPG10_PMIC_LDO_LDO21M_LLIMIT,
S2MPG10_PMIC_LDO_LDO11M_HLIMIT,
S2MPG10_PMIC_DVS_RAMP1,
S2MPG10_PMIC_DVS_RAMP2,
S2MPG10_PMIC_DVS_RAMP3,
S2MPG10_PMIC_DVS_RAMP4,
S2MPG10_PMIC_DVS_RAMP5,
S2MPG10_PMIC_DVS_RAMP6,
S2MPG10_PMIC_DVS_SYNC_CTRL1,
S2MPG10_PMIC_DVS_SYNC_CTRL2,
S2MPG10_PMIC_DVS_SYNC_CTRL3,
S2MPG10_PMIC_DVS_SYNC_CTRL4,
S2MPG10_PMIC_DVS_SYNC_CTRL5,
S2MPG10_PMIC_DVS_SYNC_CTRL6,
S2MPG10_PMIC_OFF_CTRL1,
S2MPG10_PMIC_OFF_CTRL2,
S2MPG10_PMIC_OFF_CTRL3,
S2MPG10_PMIC_OFF_CTRL4,
S2MPG10_PMIC_SEQ_CTRL1,
S2MPG10_PMIC_SEQ_CTRL2,
S2MPG10_PMIC_SEQ_CTRL3,
S2MPG10_PMIC_SEQ_CTRL4,
S2MPG10_PMIC_SEQ_CTRL5,
S2MPG10_PMIC_SEQ_CTRL6,
S2MPG10_PMIC_SEQ_CTRL7,
S2MPG10_PMIC_SEQ_CTRL8,
S2MPG10_PMIC_SEQ_CTRL9,
S2MPG10_PMIC_SEQ_CTRL10,
S2MPG10_PMIC_SEQ_CTRL11,
S2MPG10_PMIC_SEQ_CTRL12,
S2MPG10_PMIC_SEQ_CTRL13,
S2MPG10_PMIC_SEQ_CTRL14,
S2MPG10_PMIC_SEQ_CTRL15,
S2MPG10_PMIC_SEQ_CTRL16,
S2MPG10_PMIC_SEQ_CTRL17,
S2MPG10_PMIC_SEQ_CTRL18,
S2MPG10_PMIC_SEQ_CTRL19,
S2MPG10_PMIC_SEQ_CTRL20,
S2MPG10_PMIC_SEQ_CTRL21,
S2MPG10_PMIC_SEQ_CTRL22,
S2MPG10_PMIC_SEQ_CTRL23,
S2MPG10_PMIC_SEQ_CTRL24,
S2MPG10_PMIC_SEQ_CTRL25,
S2MPG10_PMIC_SEQ_CTRL26,
S2MPG10_PMIC_SEQ_CTRL27,
S2MPG10_PMIC_SEQ_CTRL28,
S2MPG10_PMIC_SEQ_CTRL29,
S2MPG10_PMIC_SEQ_CTRL30,
S2MPG10_PMIC_SEQ_CTRL31,
S2MPG10_PMIC_SEQ_CTRL32,
S2MPG10_PMIC_SEQ_CTRL33,
S2MPG10_PMIC_SEQ_CTRL34,
S2MPG10_PMIC_SEQ_CTRL35,
S2MPG10_PMIC_OFF_SEQ_CTRL1,
S2MPG10_PMIC_OFF_SEQ_CTRL2,
S2MPG10_PMIC_OFF_SEQ_CTRL3,
S2MPG10_PMIC_OFF_SEQ_CTRL4,
S2MPG10_PMIC_OFF_SEQ_CTRL5,
S2MPG10_PMIC_OFF_SEQ_CTRL6,
S2MPG10_PMIC_OFF_SEQ_CTRL7,
S2MPG10_PMIC_OFF_SEQ_CTRL8,
S2MPG10_PMIC_OFF_SEQ_CTRL9,
S2MPG10_PMIC_OFF_SEQ_CTRL10,
S2MPG10_PMIC_OFF_SEQ_CTRL11,
S2MPG10_PMIC_OFF_SEQ_CTRL12,
S2MPG10_PMIC_OFF_SEQ_CTRL13,
S2MPG10_PMIC_OFF_SEQ_CTRL14,
S2MPG10_PMIC_OFF_SEQ_CTRL15,
S2MPG10_PMIC_OFF_SEQ_CTRL16,
S2MPG10_PMIC_OFF_SEQ_CTRL17,
S2MPG10_PMIC_OFF_SEQ_CTRL18,
S2MPG10_PMIC_PCTRLSEL1,
S2MPG10_PMIC_PCTRLSEL2,
S2MPG10_PMIC_PCTRLSEL3,
S2MPG10_PMIC_PCTRLSEL4,
S2MPG10_PMIC_PCTRLSEL5,
S2MPG10_PMIC_PCTRLSEL6,
S2MPG10_PMIC_PCTRLSEL7,
S2MPG10_PMIC_PCTRLSEL8,
S2MPG10_PMIC_PCTRLSEL9,
S2MPG10_PMIC_PCTRLSEL10,
S2MPG10_PMIC_PCTRLSEL11,
S2MPG10_PMIC_PCTRLSEL12,
S2MPG10_PMIC_PCTRLSEL13,
S2MPG10_PMIC_DCTRLSEL1,
S2MPG10_PMIC_DCTRLSEL2,
S2MPG10_PMIC_DCTRLSEL3,
S2MPG10_PMIC_DCTRLSEL4,
S2MPG10_PMIC_DCTRLSEL5,
S2MPG10_PMIC_DCTRLSEL6,
S2MPG10_PMIC_DCTRLSEL7,
S2MPG10_PMIC_GPIO_CTRL1,
S2MPG10_PMIC_GPIO_CTRL2,
S2MPG10_PMIC_GPIO_CTRL3,
S2MPG10_PMIC_GPIO_CTRL4,
S2MPG10_PMIC_GPIO_CTRL5,
S2MPG10_PMIC_GPIO_CTRL6,
S2MPG10_PMIC_GPIO_CTRL7,
S2MPG10_PMIC_B2M_OCP_WARN,
S2MPG10_PMIC_B2M_OCP_WARN_X,
S2MPG10_PMIC_B2M_OCP_WARN_Y,
S2MPG10_PMIC_B2M_OCP_WARN_Z,
S2MPG10_PMIC_B3M_OCP_WARN,
S2MPG10_PMIC_B3M_OCP_WARN_X,
S2MPG10_PMIC_B3M_OCP_WARN_Y,
S2MPG10_PMIC_B3M_OCP_WARN_Z,
S2MPG10_PMIC_B10M_OCP_WARN,
S2MPG10_PMIC_B10M_OCP_WARN_X,
S2MPG10_PMIC_B10M_OCP_WARN_Y,
S2MPG10_PMIC_B10M_OCP_WARN_Z,
S2MPG10_PMIC_B2M_SOFT_OCP_WARN,
S2MPG10_PMIC_B2M_SOFT_OCP_WARN_X,
S2MPG10_PMIC_B2M_SOFT_OCP_WARN_Y,
S2MPG10_PMIC_B2M_SOFT_OCP_WARN_Z,
S2MPG10_PMIC_B3M_SOFT_OCP_WARN,
S2MPG10_PMIC_B3M_SOFT_OCP_WARN_X,
S2MPG10_PMIC_B3M_SOFT_OCP_WARN_Y,
S2MPG10_PMIC_B3M_SOFT_OCP_WARN_Z,
S2MPG10_PMIC_B10M_SOFT_OCP_WARN,
S2MPG10_PMIC_B10M_SOFT_OCP_WARN_X,
S2MPG10_PMIC_B10M_SOFT_OCP_WARN_Y,
S2MPG10_PMIC_B10M_SOFT_OCP_WARN_Z,
S2MPG10_PMIC_BUCK_OCP_EN1,
S2MPG10_PMIC_BUCK_OCP_EN2,
S2MPG10_PMIC_BUCK_OCP_PD_EN1,
S2MPG10_PMIC_BUCK_OCP_PD_EN2,
S2MPG10_PMIC_BUCK_OCP_CTRL1,
S2MPG10_PMIC_BUCK_OCP_CTRL2,
S2MPG10_PMIC_BUCK_OCP_CTRL3,
S2MPG10_PMIC_BUCK_OCP_CTRL4,
S2MPG10_PMIC_BUCK_OCP_CTRL5,
S2MPG10_PMIC_PIF_CTRL,
S2MPG10_PMIC_BUCK_HR_MODE1,
S2MPG10_PMIC_BUCK_HR_MODE2,
S2MPG10_PMIC_FAULTOUT_CTRL,
S2MPG10_PMIC_LDO_SENSE1,
S2MPG10_PMIC_LDO_SENSE2,
S2MPG10_PMIC_LDO_SENSE3,
S2MPG10_PMIC_LDO_SENSE4,
};
/* Rail controlled externally, based on PCTRLSELx */
#define S2MPG10_PMIC_CTRL_ENABLE_EXT BIT(0)
/* For S2MPG10_PMIC_PCTRLSELx */
#define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */
#define S2MPG10_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */
#define S2MPG10_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */
#define S2MPG10_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */
#define S2MPG10_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */
#define S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */
#define S2MPG10_PCTRLSEL_CPUCL1_EN 0x7 /* CPUCL1_EN pin */
#define S2MPG10_PCTRLSEL_CPUCL1_EN2 0x8 /* CPUCL1_EN & PWREN pins */
#define S2MPG10_PCTRLSEL_CPUCL2_EN 0x9 /* CPUCL2_EN pin */
#define S2MPG10_PCTRLSEL_CPUCL2_EN2 0xa /* CPUCL2_E2 & PWREN pins */
#define S2MPG10_PCTRLSEL_TPU_EN 0xb /* TPU_EN pin */
#define S2MPG10_PCTRLSEL_TPU_EN2 0xc /* TPU_EN & ~AP_ACTIVE_N pins */
#define S2MPG10_PCTRLSEL_TCXO_ON 0xd /* TCXO_ON pin */
#define S2MPG10_PCTRLSEL_TCXO_ON2 0xe /* TCXO_ON & ~AP_ACTIVE_N pins */
/* For S2MPG10_PMIC_PCTRLSELx of LDO20M */
#define S2MPG10_PCTRLSEL_LDO20M_EN2 0x1 /* VLDO20M_EN & LDO20M_SFR */
#define S2MPG10_PCTRLSEL_LDO20M_EN 0x2 /* VLDO20M_EN pin */
#define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTRL1 register */
/* Meter registers (type 0xa00) */
enum s2mpg10_meter_reg {
S2MPG10_METER_CTRL1,
S2MPG10_METER_CTRL2,
S2MPG10_METER_CTRL3,
S2MPG10_METER_CTRL4,
S2MPG10_METER_BUCKEN1,
S2MPG10_METER_BUCKEN2,
S2MPG10_METER_MUXSEL0,
S2MPG10_METER_MUXSEL1,
S2MPG10_METER_MUXSEL2,
S2MPG10_METER_MUXSEL3,
S2MPG10_METER_MUXSEL4,
S2MPG10_METER_MUXSEL5,
S2MPG10_METER_MUXSEL6,
S2MPG10_METER_MUXSEL7,
S2MPG10_METER_LPF_C0_0,
S2MPG10_METER_LPF_C0_1,
S2MPG10_METER_LPF_C0_2,
S2MPG10_METER_LPF_C0_3,
S2MPG10_METER_LPF_C0_4,
S2MPG10_METER_LPF_C0_5,
S2MPG10_METER_LPF_C0_6,
S2MPG10_METER_LPF_C0_7,
S2MPG10_METER_PWR_WARN0,
S2MPG10_METER_PWR_WARN1,
S2MPG10_METER_PWR_WARN2,
S2MPG10_METER_PWR_WARN3,
S2MPG10_METER_PWR_WARN4,
S2MPG10_METER_PWR_WARN5,
S2MPG10_METER_PWR_WARN6,
S2MPG10_METER_PWR_WARN7,
S2MPG10_METER_PWR_HYS1,
S2MPG10_METER_PWR_HYS2,
S2MPG10_METER_PWR_HYS3,
S2MPG10_METER_PWR_HYS4,
S2MPG10_METER_ACC_DATA_CH0_1 = 0x40,
S2MPG10_METER_ACC_DATA_CH0_2,
S2MPG10_METER_ACC_DATA_CH0_3,
S2MPG10_METER_ACC_DATA_CH0_4,
S2MPG10_METER_ACC_DATA_CH0_5,
S2MPG10_METER_ACC_DATA_CH0_6,
S2MPG10_METER_ACC_DATA_CH1_1,
S2MPG10_METER_ACC_DATA_CH1_2,
S2MPG10_METER_ACC_DATA_CH1_3,
S2MPG10_METER_ACC_DATA_CH1_4,
S2MPG10_METER_ACC_DATA_CH1_5,
S2MPG10_METER_ACC_DATA_CH1_6,
S2MPG10_METER_ACC_DATA_CH2_1,
S2MPG10_METER_ACC_DATA_CH2_2,
S2MPG10_METER_ACC_DATA_CH2_3,
S2MPG10_METER_ACC_DATA_CH2_4,
S2MPG10_METER_ACC_DATA_CH2_5,
S2MPG10_METER_ACC_DATA_CH2_6,
S2MPG10_METER_ACC_DATA_CH3_1,
S2MPG10_METER_ACC_DATA_CH3_2,
S2MPG10_METER_ACC_DATA_CH3_3,
S2MPG10_METER_ACC_DATA_CH3_4,
S2MPG10_METER_ACC_DATA_CH3_5,
S2MPG10_METER_ACC_DATA_CH3_6,
S2MPG10_METER_ACC_DATA_CH4_1,
S2MPG10_METER_ACC_DATA_CH4_2,
S2MPG10_METER_ACC_DATA_CH4_3,
S2MPG10_METER_ACC_DATA_CH4_4,
S2MPG10_METER_ACC_DATA_CH4_5,
S2MPG10_METER_ACC_DATA_CH4_6,
S2MPG10_METER_ACC_DATA_CH5_1,
S2MPG10_METER_ACC_DATA_CH5_2,
S2MPG10_METER_ACC_DATA_CH5_3,
S2MPG10_METER_ACC_DATA_CH5_4,
S2MPG10_METER_ACC_DATA_CH5_5,
S2MPG10_METER_ACC_DATA_CH5_6,
S2MPG10_METER_ACC_DATA_CH6_1,
S2MPG10_METER_ACC_DATA_CH6_2,
S2MPG10_METER_ACC_DATA_CH6_3,
S2MPG10_METER_ACC_DATA_CH6_4,
S2MPG10_METER_ACC_DATA_CH6_5,
S2MPG10_METER_ACC_DATA_CH6_6,
S2MPG10_METER_ACC_DATA_CH7_1,
S2MPG10_METER_ACC_DATA_CH7_2,
S2MPG10_METER_ACC_DATA_CH7_3,
S2MPG10_METER_ACC_DATA_CH7_4,
S2MPG10_METER_ACC_DATA_CH7_5,
S2MPG10_METER_ACC_DATA_CH7_6,
S2MPG10_METER_ACC_COUNT_1,
S2MPG10_METER_ACC_COUNT_2,
S2MPG10_METER_ACC_COUNT_3,
S2MPG10_METER_LPF_DATA_CH0_1,
S2MPG10_METER_LPF_DATA_CH0_2,
S2MPG10_METER_LPF_DATA_CH0_3,
S2MPG10_METER_LPF_DATA_CH1_1,
S2MPG10_METER_LPF_DATA_CH1_2,
S2MPG10_METER_LPF_DATA_CH1_3,
S2MPG10_METER_LPF_DATA_CH2_1,
S2MPG10_METER_LPF_DATA_CH2_2,
S2MPG10_METER_LPF_DATA_CH2_3,
S2MPG10_METER_LPF_DATA_CH3_1,
S2MPG10_METER_LPF_DATA_CH3_2,
S2MPG10_METER_LPF_DATA_CH3_3,
S2MPG10_METER_LPF_DATA_CH4_1,
S2MPG10_METER_LPF_DATA_CH4_2,
S2MPG10_METER_LPF_DATA_CH4_3,
S2MPG10_METER_LPF_DATA_CH5_1,
S2MPG10_METER_LPF_DATA_CH5_2,
S2MPG10_METER_LPF_DATA_CH5_3,
S2MPG10_METER_LPF_DATA_CH6_1,
S2MPG10_METER_LPF_DATA_CH6_2,
S2MPG10_METER_LPF_DATA_CH6_3,
S2MPG10_METER_LPF_DATA_CH7_1,
S2MPG10_METER_LPF_DATA_CH7_2,
S2MPG10_METER_LPF_DATA_CH7_3,
S2MPG10_METER_DSM_TRIM_OFFSET = 0xee,
S2MPG10_METER_BUCK_METER_TRIM3 = 0xf1,
};
/* S2MPG10 regulator IDs */
enum s2mpg10_regulators {
S2MPG10_BUCK1,
S2MPG10_BUCK2,
S2MPG10_BUCK3,
S2MPG10_BUCK4,
S2MPG10_BUCK5,
S2MPG10_BUCK6,
S2MPG10_BUCK7,
S2MPG10_BUCK8,
S2MPG10_BUCK9,
S2MPG10_BUCK10,
S2MPG10_LDO1,
S2MPG10_LDO2,
S2MPG10_LDO3,
S2MPG10_LDO4,
S2MPG10_LDO5,
S2MPG10_LDO6,
S2MPG10_LDO7,
S2MPG10_LDO8,
S2MPG10_LDO9,
S2MPG10_LDO10,
S2MPG10_LDO11,
S2MPG10_LDO12,
S2MPG10_LDO13,
S2MPG10_LDO14,
S2MPG10_LDO15,
S2MPG10_LDO16,
S2MPG10_LDO17,
S2MPG10_LDO18,
S2MPG10_LDO19,
S2MPG10_LDO20,
S2MPG10_LDO21,
S2MPG10_LDO22,
S2MPG10_LDO23,
S2MPG10_LDO24,
S2MPG10_LDO25,
S2MPG10_LDO26,
S2MPG10_LDO27,
S2MPG10_LDO28,
S2MPG10_LDO29,
S2MPG10_LDO30,
S2MPG10_LDO31,
S2MPG10_REGULATOR_MAX,
};
#endif /* __LINUX_MFD_S2MPG10_H */
linux-7.2.3/include/linux/mfd/samsung/s2mpg11.h
+434
View File
@@ -0,0 +1,434 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Samsung Electronics
* Copyright 2020 Google Inc
* Copyright 2025 Linaro Ltd.
*/
#ifndef __LINUX_MFD_S2MPG11_H
#define __LINUX_MFD_S2MPG11_H
/* Common registers (type 0x000) */
enum s2mpg11_common_reg {
S2MPG11_COMMON_CHIPID,
S2MPG11_COMMON_INT,
S2MPG11_COMMON_INT_MASK,
S2MPG11_COMMON_SPD_CTRL1 = 0x0a,
S2MPG11_COMMON_SPD_CTRL2,
S2MPG11_COMMON_SPD_CTRL3,
S2MPG11_COMMON_MON1SEL = 0x1a,
S2MPG11_COMMON_MON2SEL,
S2MPG11_COMMON_MONR,
S2MPG11_COMMON_DEBUG_CTRL1,
S2MPG11_COMMON_DEBUG_CTRL2,
S2MPG11_COMMON_DEBUG_CTRL3,
S2MPG11_COMMON_DEBUG_CTRL4,
S2MPG11_COMMON_DEBUG_CTRL5,
S2MPG11_COMMON_DEBUG_CTRL6,
S2MPG11_COMMON_TEST_MODE1,
S2MPG11_COMMON_SPD_DEBUG1,
S2MPG11_COMMON_SPD_DEBUG2,
S2MPG11_COMMON_SPD_DEBUG3,
S2MPG11_COMMON_SPD_DEBUG4,
};
/* For S2MPG11_COMMON_INT and S2MPG11_COMMON_INT_MASK */
#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0)
#define S2MPG11_COMMON_INT_SRC_PMIC BIT(0)
/* PMIC registers (type 0x100) */
enum s2mpg11_pmic_reg {
S2MPG11_PMIC_INT1,
S2MPG11_PMIC_INT2,
S2MPG11_PMIC_INT3,
S2MPG11_PMIC_INT4,
S2MPG11_PMIC_INT5,
S2MPG11_PMIC_INT6,
S2MPG11_PMIC_INT1M,
S2MPG11_PMIC_INT2M,
S2MPG11_PMIC_INT3M,
S2MPG11_PMIC_INT4M,
S2MPG11_PMIC_INT5M,
S2MPG11_PMIC_INT6M,
S2MPG11_PMIC_STATUS1,
S2MPG11_PMIC_OFFSRC,
S2MPG11_PMIC_COMMON_CTRL1,
S2MPG11_PMIC_COMMON_CTRL2,
S2MPG11_PMIC_COMMON_CTRL3,
S2MPG11_PMIC_MIMICKING_CTRL,
S2MPG11_PMIC_B1S_CTRL,
S2MPG11_PMIC_B1S_OUT1,
S2MPG11_PMIC_B1S_OUT2,
S2MPG11_PMIC_B2S_CTRL,
S2MPG11_PMIC_B2S_OUT1,
S2MPG11_PMIC_B2S_OUT2,
S2MPG11_PMIC_B3S_CTRL,
S2MPG11_PMIC_B3S_OUT1,
S2MPG11_PMIC_B3S_OUT2,
S2MPG11_PMIC_B4S_CTRL,
S2MPG11_PMIC_B4S_OUT,
S2MPG11_PMIC_B5S_CTRL,
S2MPG11_PMIC_B5S_OUT,
S2MPG11_PMIC_B6S_CTRL,
S2MPG11_PMIC_B6S_OUT1,
S2MPG11_PMIC_B6S_OUT2,
S2MPG11_PMIC_B7S_CTRL,
S2MPG11_PMIC_B7S_OUT1,
S2MPG11_PMIC_B7S_OUT2,
S2MPG11_PMIC_B8S_CTRL,
S2MPG11_PMIC_B8S_OUT1,
S2MPG11_PMIC_B8S_OUT2,
S2MPG11_PMIC_B9S_CTRL,
S2MPG11_PMIC_B9S_OUT1,
S2MPG11_PMIC_B9S_OUT2,
S2MPG11_PMIC_B10S_CTRL,
S2MPG11_PMIC_B10S_OUT,
S2MPG11_PMIC_BUCKD_CTRL,
S2MPG11_PMIC_BUCKD_OUT,
S2MPG11_PMIC_BUCKA_CTRL,
S2MPG11_PMIC_BUCKA_OUT,
S2MPG11_PMIC_BB_CTRL,
S2MPG11_PMIC_BB_OUT1,
S2MPG11_PMIC_BB_OUT2,
S2MPG11_PMIC_BUCK1S_USONIC,
S2MPG11_PMIC_BUCK2S_USONIC,
S2MPG11_PMIC_BUCK3S_USONIC,
S2MPG11_PMIC_BUCK4S_USONIC,
S2MPG11_PMIC_BUCK5S_USONIC,
S2MPG11_PMIC_BUCK6S_USONIC,
S2MPG11_PMIC_BUCK7S_USONIC,
S2MPG11_PMIC_BUCK8S_USONIC,
S2MPG11_PMIC_BUCK9S_USONIC,
S2MPG11_PMIC_BUCK10S_USONIC,
S2MPG11_PMIC_BUCKD_USONIC,
S2MPG11_PMIC_BUCKA_USONIC,
S2MPG11_PMIC_BB_USONIC,
S2MPG11_PMIC_L1S_CTRL1,
S2MPG11_PMIC_L1S_CTRL2,
S2MPG11_PMIC_L2S_CTRL1,
S2MPG11_PMIC_L2S_CTRL2,
S2MPG11_PMIC_L3S_CTRL,
S2MPG11_PMIC_L4S_CTRL,
S2MPG11_PMIC_L5S_CTRL,
S2MPG11_PMIC_L6S_CTRL,
S2MPG11_PMIC_L7S_CTRL,
S2MPG11_PMIC_L8S_CTRL,
S2MPG11_PMIC_L9S_CTRL,
S2MPG11_PMIC_L10S_CTRL,
S2MPG11_PMIC_L11S_CTRL,
S2MPG11_PMIC_L12S_CTRL,
S2MPG11_PMIC_L13S_CTRL,
S2MPG11_PMIC_L14S_CTRL,
S2MPG11_PMIC_L15S_CTRL,
S2MPG11_PMIC_LDO_CTRL1,
S2MPG11_PMIC_LDO_DSCH1,
S2MPG11_PMIC_LDO_DSCH2,
S2MPG11_PMIC_DVS_RAMP1,
S2MPG11_PMIC_DVS_RAMP2,
S2MPG11_PMIC_DVS_RAMP3,
S2MPG11_PMIC_DVS_RAMP4,
S2MPG11_PMIC_DVS_RAMP5,
S2MPG11_PMIC_DVS_RAMP6,
/* Nothing @ 0x5a */
S2MPG11_PMIC_DVS_SYNC_CTRL1 = 0x5c,
S2MPG11_PMIC_DVS_SYNC_CTRL2,
S2MPG11_PMIC_OFF_CTRL1,
S2MPG11_PMIC_OFF_CTRL2,
S2MPG11_PMIC_OFF_CTRL3,
S2MPG11_PMIC_SEQ_CTRL1,
S2MPG11_PMIC_SEQ_CTRL2,
S2MPG11_PMIC_SEQ_CTRL3,
S2MPG11_PMIC_SEQ_CTRL4,
S2MPG11_PMIC_SEQ_CTRL5,
S2MPG11_PMIC_SEQ_CTRL6,
S2MPG11_PMIC_SEQ_CTRL7,
S2MPG11_PMIC_SEQ_CTRL8,
S2MPG11_PMIC_SEQ_CTRL9,
S2MPG11_PMIC_SEQ_CTRL10,
S2MPG11_PMIC_SEQ_CTRL11,
S2MPG11_PMIC_SEQ_CTRL12,
S2MPG11_PMIC_SEQ_CTRL13,
S2MPG11_PMIC_SEQ_CTRL14,
S2MPG11_PMIC_SEQ_CTRL15,
S2MPG11_PMIC_SEQ_CTRL16,
S2MPG11_PMIC_SEQ_CTRL17,
S2MPG11_PMIC_SEQ_CTRL18,
S2MPG11_PMIC_SEQ_CTRL19,
S2MPG11_PMIC_SEQ_CTRL20,
S2MPG11_PMIC_SEQ_CTRL21,
S2MPG11_PMIC_SEQ_CTRL22,
S2MPG11_PMIC_SEQ_CTRL23,
S2MPG11_PMIC_SEQ_CTRL24,
S2MPG11_PMIC_SEQ_CTRL25,
S2MPG11_PMIC_SEQ_CTRL26,
S2MPG11_PMIC_SEQ_CTRL27,
S2MPG11_PMIC_OFF_SEQ_CTRL1,
S2MPG11_PMIC_OFF_SEQ_CTRL2,
S2MPG11_PMIC_OFF_SEQ_CTRL3,
S2MPG11_PMIC_OFF_SEQ_CTRL4,
S2MPG11_PMIC_OFF_SEQ_CTRL5,
S2MPG11_PMIC_OFF_SEQ_CTRL6,
S2MPG11_PMIC_OFF_SEQ_CTRL7,
S2MPG11_PMIC_OFF_SEQ_CTRL8,
S2MPG11_PMIC_OFF_SEQ_CTRL9,
S2MPG11_PMIC_OFF_SEQ_CTRL10,
S2MPG11_PMIC_OFF_SEQ_CTRL11,
S2MPG11_PMIC_OFF_SEQ_CTRL12,
S2MPG11_PMIC_OFF_SEQ_CTRL13,
S2MPG11_PMIC_OFF_SEQ_CTRL14,
S2MPG11_PMIC_OFF_SEQ_CTRL15,
S2MPG11_PMIC_OFF_SEQ_CTRL16,
S2MPG11_PMIC_OFF_SEQ_CTRL17,
S2MPG11_PMIC_PCTRLSEL1,
S2MPG11_PMIC_PCTRLSEL2,
S2MPG11_PMIC_PCTRLSEL3,
S2MPG11_PMIC_PCTRLSEL4,
S2MPG11_PMIC_PCTRLSEL5,
S2MPG11_PMIC_PCTRLSEL6,
S2MPG11_PMIC_DCTRLSEL1,
S2MPG11_PMIC_DCTRLSEL2,
S2MPG11_PMIC_DCTRLSEL3,
S2MPG11_PMIC_DCTRLSEL4,
S2MPG11_PMIC_DCTRLSEL5,
S2MPG11_PMIC_GPIO_CTRL1,
S2MPG11_PMIC_GPIO_CTRL2,
S2MPG11_PMIC_GPIO_CTRL3,
S2MPG11_PMIC_GPIO_CTRL4,
S2MPG11_PMIC_GPIO_CTRL5,
S2MPG11_PMIC_GPIO_CTRL6,
S2MPG11_PMIC_GPIO_CTRL7,
S2MPG11_PMIC_B2S_OCP_WARN,
S2MPG11_PMIC_B2S_OCP_WARN_X,
S2MPG11_PMIC_B2S_OCP_WARN_Y,
S2MPG11_PMIC_B2S_OCP_WARN_Z,
S2MPG11_PMIC_B2S_SOFT_OCP_WARN,
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_X,
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y,
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z,
S2MPG11_PMIC_BUCK_OCP_EN1,
S2MPG11_PMIC_BUCK_OCP_EN2,
S2MPG11_PMIC_BUCK_OCP_PD_EN1,
S2MPG11_PMIC_BUCK_OCP_PD_EN2,
S2MPG11_PMIC_BUCK_OCP_CTRL1,
S2MPG11_PMIC_BUCK_OCP_CTRL2,
S2MPG11_PMIC_BUCK_OCP_CTRL3,
S2MPG11_PMIC_BUCK_OCP_CTRL4,
S2MPG11_PMIC_BUCK_OCP_CTRL5,
S2MPG11_PMIC_BUCK_OCP_CTRL6,
S2MPG11_PMIC_BUCK_OCP_CTRL7,
S2MPG11_PMIC_PIF_CTRL,
S2MPG11_PMIC_BUCK_HR_MODE1,
S2MPG11_PMIC_BUCK_HR_MODE2,
S2MPG11_PMIC_FAULTOUT_CTRL,
S2MPG11_PMIC_LDO_SENSE1,
S2MPG11_PMIC_LDO_SENSE2,
};
/* For S2MPG11_PMIC_PCTRLSELx */
#define S2MPG11_PCTRLSEL_PWREN 0x1 /* PWREN pin */
#define S2MPG11_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */
#define S2MPG11_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */
#define S2MPG11_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */
#define S2MPG11_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */
#define S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */
#define S2MPG11_PCTRLSEL_G3D_EN 0x7 /* G3D_EN pin */
#define S2MPG11_PCTRLSEL_G3D_EN2 0x8 /* G3D_EN & ~AP_ACTIVE_N pins */
#define S2MPG11_PCTRLSEL_AOC_VDD 0x9 /* AOC_VDD pin */
#define S2MPG11_PCTRLSEL_AOC_RET 0xa /* AOC_RET pin */
#define S2MPG11_PCTRLSEL_UFS_EN 0xb /* UFS_EN pin */
#define S2MPG11_PCTRLSEL_LDO13S_EN 0xc /* VLDO13S_EN pin */
/* Meter registers (type 0xa00) */
enum s2mpg11_meter_reg {
S2MPG11_METER_CTRL1,
S2MPG11_METER_CTRL2,
S2MPG11_METER_CTRL3,
S2MPG11_METER_CTRL4,
S2MPG11_METER_CTRL5,
S2MPG11_METER_BUCKEN1,
S2MPG11_METER_BUCKEN2,
S2MPG11_METER_MUXSEL0,
S2MPG11_METER_MUXSEL1,
S2MPG11_METER_MUXSEL2,
S2MPG11_METER_MUXSEL3,
S2MPG11_METER_MUXSEL4,
S2MPG11_METER_MUXSEL5,
S2MPG11_METER_MUXSEL6,
S2MPG11_METER_MUXSEL7,
S2MPG11_METER_LPF_C0_0,
S2MPG11_METER_LPF_C0_1,
S2MPG11_METER_LPF_C0_2,
S2MPG11_METER_LPF_C0_3,
S2MPG11_METER_LPF_C0_4,
S2MPG11_METER_LPF_C0_5,
S2MPG11_METER_LPF_C0_6,
S2MPG11_METER_LPF_C0_7,
S2MPG11_METER_NTC_LPF_C0_0,
S2MPG11_METER_NTC_LPF_C0_1,
S2MPG11_METER_NTC_LPF_C0_2,
S2MPG11_METER_NTC_LPF_C0_3,
S2MPG11_METER_NTC_LPF_C0_4,
S2MPG11_METER_NTC_LPF_C0_5,
S2MPG11_METER_NTC_LPF_C0_6,
S2MPG11_METER_NTC_LPF_C0_7,
S2MPG11_METER_PWR_WARN0,
S2MPG11_METER_PWR_WARN1,
S2MPG11_METER_PWR_WARN2,
S2MPG11_METER_PWR_WARN3,
S2MPG11_METER_PWR_WARN4,
S2MPG11_METER_PWR_WARN5,
S2MPG11_METER_PWR_WARN6,
S2MPG11_METER_PWR_WARN7,
S2MPG11_METER_NTC_L_WARN0,
S2MPG11_METER_NTC_L_WARN1,
S2MPG11_METER_NTC_L_WARN2,
S2MPG11_METER_NTC_L_WARN3,
S2MPG11_METER_NTC_L_WARN4,
S2MPG11_METER_NTC_L_WARN5,
S2MPG11_METER_NTC_L_WARN6,
S2MPG11_METER_NTC_L_WARN7,
S2MPG11_METER_NTC_H_WARN0,
S2MPG11_METER_NTC_H_WARN1,
S2MPG11_METER_NTC_H_WARN2,
S2MPG11_METER_NTC_H_WARN3,
S2MPG11_METER_NTC_H_WARN4,
S2MPG11_METER_NTC_H_WARN5,
S2MPG11_METER_NTC_H_WARN6,
S2MPG11_METER_NTC_H_WARN7,
S2MPG11_METER_PWR_HYS1,
S2MPG11_METER_PWR_HYS2,
S2MPG11_METER_PWR_HYS3,
S2MPG11_METER_PWR_HYS4,
S2MPG11_METER_NTC_HYS1,
S2MPG11_METER_NTC_HYS2,
S2MPG11_METER_NTC_HYS3,
S2MPG11_METER_NTC_HYS4,
/* Nothing @ 0x3f */
S2MPG11_METER_ACC_DATA_CH0_1 = 0x40,
S2MPG11_METER_ACC_DATA_CH0_2,
S2MPG11_METER_ACC_DATA_CH0_3,
S2MPG11_METER_ACC_DATA_CH0_4,
S2MPG11_METER_ACC_DATA_CH0_5,
S2MPG11_METER_ACC_DATA_CH0_6,
S2MPG11_METER_ACC_DATA_CH1_1,
S2MPG11_METER_ACC_DATA_CH1_2,
S2MPG11_METER_ACC_DATA_CH1_3,
S2MPG11_METER_ACC_DATA_CH1_4,
S2MPG11_METER_ACC_DATA_CH1_5,
S2MPG11_METER_ACC_DATA_CH1_6,
S2MPG11_METER_ACC_DATA_CH2_1,
S2MPG11_METER_ACC_DATA_CH2_2,
S2MPG11_METER_ACC_DATA_CH2_3,
S2MPG11_METER_ACC_DATA_CH2_4,
S2MPG11_METER_ACC_DATA_CH2_5,
S2MPG11_METER_ACC_DATA_CH2_6,
S2MPG11_METER_ACC_DATA_CH3_1,
S2MPG11_METER_ACC_DATA_CH3_2,
S2MPG11_METER_ACC_DATA_CH3_3,
S2MPG11_METER_ACC_DATA_CH3_4,
S2MPG11_METER_ACC_DATA_CH3_5,
S2MPG11_METER_ACC_DATA_CH3_6,
S2MPG11_METER_ACC_DATA_CH4_1,
S2MPG11_METER_ACC_DATA_CH4_2,
S2MPG11_METER_ACC_DATA_CH4_3,
S2MPG11_METER_ACC_DATA_CH4_4,
S2MPG11_METER_ACC_DATA_CH4_5,
S2MPG11_METER_ACC_DATA_CH4_6,
S2MPG11_METER_ACC_DATA_CH5_1,
S2MPG11_METER_ACC_DATA_CH5_2,
S2MPG11_METER_ACC_DATA_CH5_3,
S2MPG11_METER_ACC_DATA_CH5_4,
S2MPG11_METER_ACC_DATA_CH5_5,
S2MPG11_METER_ACC_DATA_CH5_6,
S2MPG11_METER_ACC_DATA_CH6_1,
S2MPG11_METER_ACC_DATA_CH6_2,
S2MPG11_METER_ACC_DATA_CH6_3,
S2MPG11_METER_ACC_DATA_CH6_4,
S2MPG11_METER_ACC_DATA_CH6_5,
S2MPG11_METER_ACC_DATA_CH6_6,
S2MPG11_METER_ACC_DATA_CH7_1,
S2MPG11_METER_ACC_DATA_CH7_2,
S2MPG11_METER_ACC_DATA_CH7_3,
S2MPG11_METER_ACC_DATA_CH7_4,
S2MPG11_METER_ACC_DATA_CH7_5,
S2MPG11_METER_ACC_DATA_CH7_6,
S2MPG11_METER_ACC_COUNT_1,
S2MPG11_METER_ACC_COUNT_2,
S2MPG11_METER_ACC_COUNT_3,
S2MPG11_METER_LPF_DATA_CH0_1,
S2MPG11_METER_LPF_DATA_CH0_2,
S2MPG11_METER_LPF_DATA_CH0_3,
S2MPG11_METER_LPF_DATA_CH1_1,
S2MPG11_METER_LPF_DATA_CH1_2,
S2MPG11_METER_LPF_DATA_CH1_3,
S2MPG11_METER_LPF_DATA_CH2_1,
S2MPG11_METER_LPF_DATA_CH2_2,
S2MPG11_METER_LPF_DATA_CH2_3,
S2MPG11_METER_LPF_DATA_CH3_1,
S2MPG11_METER_LPF_DATA_CH3_2,
S2MPG11_METER_LPF_DATA_CH3_3,
S2MPG11_METER_LPF_DATA_CH4_1,
S2MPG11_METER_LPF_DATA_CH4_2,
S2MPG11_METER_LPF_DATA_CH4_3,
S2MPG11_METER_LPF_DATA_CH5_1,
S2MPG11_METER_LPF_DATA_CH5_2,
S2MPG11_METER_LPF_DATA_CH5_3,
S2MPG11_METER_LPF_DATA_CH6_1,
S2MPG11_METER_LPF_DATA_CH6_2,
S2MPG11_METER_LPF_DATA_CH6_3,
S2MPG11_METER_LPF_DATA_CH7_1,
S2MPG11_METER_LPF_DATA_CH7_2,
S2MPG11_METER_LPF_DATA_CH7_3,
/* Nothing @ 0x8b 0x8c */
S2MPG11_METER_LPF_DATA_NTC0_1 = 0x8d,
S2MPG11_METER_LPF_DATA_NTC0_2,
S2MPG11_METER_LPF_DATA_NTC1_1,
S2MPG11_METER_LPF_DATA_NTC1_2,
S2MPG11_METER_LPF_DATA_NTC2_1,
S2MPG11_METER_LPF_DATA_NTC2_2,
S2MPG11_METER_LPF_DATA_NTC3_1,
S2MPG11_METER_LPF_DATA_NTC3_2,
S2MPG11_METER_LPF_DATA_NTC4_1,
S2MPG11_METER_LPF_DATA_NTC4_2,
S2MPG11_METER_LPF_DATA_NTC5_1,
S2MPG11_METER_LPF_DATA_NTC5_2,
S2MPG11_METER_LPF_DATA_NTC6_1,
S2MPG11_METER_LPF_DATA_NTC6_2,
S2MPG11_METER_LPF_DATA_NTC7_1,
S2MPG11_METER_LPF_DATA_NTC7_2,
};
/* S2MPG11 regulator IDs */
enum s2mpg11_regulators {
S2MPG11_BUCKBOOST,
S2MPG11_BUCK1,
S2MPG11_BUCK2,
S2MPG11_BUCK3,
S2MPG11_BUCK4,
S2MPG11_BUCK5,
S2MPG11_BUCK6,
S2MPG11_BUCK7,
S2MPG11_BUCK8,
S2MPG11_BUCK9,
S2MPG11_BUCK10,
S2MPG11_BUCKD,
S2MPG11_BUCKA,
S2MPG11_LDO1,
S2MPG11_LDO2,
S2MPG11_LDO3,
S2MPG11_LDO4,
S2MPG11_LDO5,
S2MPG11_LDO6,
S2MPG11_LDO7,
S2MPG11_LDO8,
S2MPG11_LDO9,
S2MPG11_LDO10,
S2MPG11_LDO11,
S2MPG11_LDO12,
S2MPG11_LDO13,
S2MPG11_LDO14,
S2MPG11_LDO15,
S2MPG11_REGULATOR_MAX,
};
#endif /* __LINUX_MFD_S2MPG11_H */
linux-7.2.3/include/linux/mfd/samsung/s2mps11.h
+198
View File
@@ -0,0 +1,198 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S2MPS11_H
#define __LINUX_MFD_S2MPS11_H
/* S2MPS11 registers */
enum s2mps11_reg {
S2MPS11_REG_ID,
S2MPS11_REG_INT1,
S2MPS11_REG_INT2,
S2MPS11_REG_INT3,
S2MPS11_REG_INT1M,
S2MPS11_REG_INT2M,
S2MPS11_REG_INT3M,
S2MPS11_REG_ST1,
S2MPS11_REG_ST2,
S2MPS11_REG_OFFSRC,
S2MPS11_REG_PWRONSRC,
S2MPS11_REG_RTC_CTRL,
S2MPS11_REG_CTRL1,
S2MPS11_REG_ETC_TEST,
S2MPS11_REG_RSVD3,
S2MPS11_REG_BU_CHG,
S2MPS11_REG_RAMP,
S2MPS11_REG_RAMP_BUCK,
S2MPS11_REG_LDO1_8,
S2MPS11_REG_LDO9_16,
S2MPS11_REG_LDO17_24,
S2MPS11_REG_LDO25_32,
S2MPS11_REG_LDO33_38,
S2MPS11_REG_LDO1_8_1,
S2MPS11_REG_LDO9_16_1,
S2MPS11_REG_LDO17_24_1,
S2MPS11_REG_LDO25_32_1,
S2MPS11_REG_LDO33_38_1,
S2MPS11_REG_OTP_ADRL,
S2MPS11_REG_OTP_ADRH,
S2MPS11_REG_OTP_DATA,
S2MPS11_REG_MON1SEL,
S2MPS11_REG_MON2SEL,
S2MPS11_REG_LEE,
S2MPS11_REG_RSVD_NO,
S2MPS11_REG_UVLO,
S2MPS11_REG_LEE_NO,
S2MPS11_REG_B1CTRL1,
S2MPS11_REG_B1CTRL2,
S2MPS11_REG_B2CTRL1,
S2MPS11_REG_B2CTRL2,
S2MPS11_REG_B3CTRL1,
S2MPS11_REG_B3CTRL2,
S2MPS11_REG_B4CTRL1,
S2MPS11_REG_B4CTRL2,
S2MPS11_REG_B5CTRL1,
S2MPS11_REG_BUCK5_SW,
S2MPS11_REG_B5CTRL2,
S2MPS11_REG_B5CTRL3,
S2MPS11_REG_B5CTRL4,
S2MPS11_REG_B5CTRL5,
S2MPS11_REG_B6CTRL1,
S2MPS11_REG_B6CTRL2,
S2MPS11_REG_B7CTRL1,
S2MPS11_REG_B7CTRL2,
S2MPS11_REG_B8CTRL1,
S2MPS11_REG_B8CTRL2,
S2MPS11_REG_B9CTRL1,
S2MPS11_REG_B9CTRL2,
S2MPS11_REG_B10CTRL1,
S2MPS11_REG_B10CTRL2,
S2MPS11_REG_L1CTRL,
S2MPS11_REG_L2CTRL,
S2MPS11_REG_L3CTRL,
S2MPS11_REG_L4CTRL,
S2MPS11_REG_L5CTRL,
S2MPS11_REG_L6CTRL,
S2MPS11_REG_L7CTRL,
S2MPS11_REG_L8CTRL,
S2MPS11_REG_L9CTRL,
S2MPS11_REG_L10CTRL,
S2MPS11_REG_L11CTRL,
S2MPS11_REG_L12CTRL,
S2MPS11_REG_L13CTRL,
S2MPS11_REG_L14CTRL,
S2MPS11_REG_L15CTRL,
S2MPS11_REG_L16CTRL,
S2MPS11_REG_L17CTRL,
S2MPS11_REG_L18CTRL,
S2MPS11_REG_L19CTRL,
S2MPS11_REG_L20CTRL,
S2MPS11_REG_L21CTRL,
S2MPS11_REG_L22CTRL,
S2MPS11_REG_L23CTRL,
S2MPS11_REG_L24CTRL,
S2MPS11_REG_L25CTRL,
S2MPS11_REG_L26CTRL,
S2MPS11_REG_L27CTRL,
S2MPS11_REG_L28CTRL,
S2MPS11_REG_L29CTRL,
S2MPS11_REG_L30CTRL,
S2MPS11_REG_L31CTRL,
S2MPS11_REG_L32CTRL,
S2MPS11_REG_L33CTRL,
S2MPS11_REG_L34CTRL,
S2MPS11_REG_L35CTRL,
S2MPS11_REG_L36CTRL,
S2MPS11_REG_L37CTRL,
S2MPS11_REG_L38CTRL,
};
/* S2MPS11 regulator ids */
enum s2mps11_regulators {
S2MPS11_LDO1,
S2MPS11_LDO2,
S2MPS11_LDO3,
S2MPS11_LDO4,
S2MPS11_LDO5,
S2MPS11_LDO6,
S2MPS11_LDO7,
S2MPS11_LDO8,
S2MPS11_LDO9,
S2MPS11_LDO10,
S2MPS11_LDO11,
S2MPS11_LDO12,
S2MPS11_LDO13,
S2MPS11_LDO14,
S2MPS11_LDO15,
S2MPS11_LDO16,
S2MPS11_LDO17,
S2MPS11_LDO18,
S2MPS11_LDO19,
S2MPS11_LDO20,
S2MPS11_LDO21,
S2MPS11_LDO22,
S2MPS11_LDO23,
S2MPS11_LDO24,
S2MPS11_LDO25,
S2MPS11_LDO26,
S2MPS11_LDO27,
S2MPS11_LDO28,
S2MPS11_LDO29,
S2MPS11_LDO30,
S2MPS11_LDO31,
S2MPS11_LDO32,
S2MPS11_LDO33,
S2MPS11_LDO34,
S2MPS11_LDO35,
S2MPS11_LDO36,
S2MPS11_LDO37,
S2MPS11_LDO38,
S2MPS11_BUCK1,
S2MPS11_BUCK2,
S2MPS11_BUCK3,
S2MPS11_BUCK4,
S2MPS11_BUCK5,
S2MPS11_BUCK6,
S2MPS11_BUCK7,
S2MPS11_BUCK8,
S2MPS11_BUCK9,
S2MPS11_BUCK10,
S2MPS11_REGULATOR_MAX,
};
#define S2MPS11_LDO_VSEL_MASK 0x3F
#define S2MPS11_BUCK_VSEL_MASK 0xFF
#define S2MPS11_BUCK9_VSEL_MASK 0x1F
#define S2MPS11_ENABLE_MASK (0x03 << S2MPS11_ENABLE_SHIFT)
#define S2MPS11_ENABLE_SHIFT 0x06
#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
#define S2MPS11_BUCK12346_N_VOLTAGES 153
#define S2MPS11_BUCK5_N_VOLTAGES 216
#define S2MPS11_BUCK7810_N_VOLTAGES 225
#define S2MPS11_BUCK9_N_VOLTAGES (S2MPS11_BUCK9_VSEL_MASK + 1)
#define S2MPS11_RAMP_DELAY 25000 /* uV/us */
#define S2MPS11_CTRL1_PWRHOLD_MASK BIT(4)
#define S2MPS11_BUCK2_RAMP_SHIFT 6
#define S2MPS11_BUCK34_RAMP_SHIFT 4
#define S2MPS11_BUCK5_RAMP_SHIFT 6
#define S2MPS11_BUCK16_RAMP_SHIFT 4
#define S2MPS11_BUCK7810_RAMP_SHIFT 2
#define S2MPS11_BUCK9_RAMP_SHIFT 0
#define S2MPS11_BUCK2_RAMP_EN_SHIFT 3
#define S2MPS11_BUCK3_RAMP_EN_SHIFT 2
#define S2MPS11_BUCK4_RAMP_EN_SHIFT 1
#define S2MPS11_BUCK6_RAMP_EN_SHIFT 0
#define S2MPS11_PMIC_EN_SHIFT 6
/*
* Bits for "enable suspend" (On/Off controlled by PWREN)
* are the same as in S2MPS14: S2MPS14_ENABLE_SUSPEND
*/
#endif /* __LINUX_MFD_S2MPS11_H */
linux-7.2.3/include/linux/mfd/samsung/s2mps13.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S2MPS13_H
#define __LINUX_MFD_S2MPS13_H
/* S2MPS13 registers */
enum s2mps13_reg {
S2MPS13_REG_ID,
S2MPS13_REG_INT1,
S2MPS13_REG_INT2,
S2MPS13_REG_INT3,
S2MPS13_REG_INT1M,
S2MPS13_REG_INT2M,
S2MPS13_REG_INT3M,
S2MPS13_REG_ST1,
S2MPS13_REG_ST2,
S2MPS13_REG_PWRONSRC,
S2MPS13_REG_OFFSRC,
S2MPS13_REG_BU_CHG,
S2MPS13_REG_RTCCTRL,
S2MPS13_REG_CTRL1,
S2MPS13_REG_CTRL2,
S2MPS13_REG_RSVD1,
S2MPS13_REG_RSVD2,
S2MPS13_REG_RSVD3,
S2MPS13_REG_RSVD4,
S2MPS13_REG_RSVD5,
S2MPS13_REG_RSVD6,
S2MPS13_REG_CTRL3,
S2MPS13_REG_RSVD7,
S2MPS13_REG_RSVD8,
S2MPS13_REG_WRSTBI,
S2MPS13_REG_B1CTRL,
S2MPS13_REG_B1OUT,
S2MPS13_REG_B2CTRL,
S2MPS13_REG_B2OUT,
S2MPS13_REG_B3CTRL,
S2MPS13_REG_B3OUT,
S2MPS13_REG_B4CTRL,
S2MPS13_REG_B4OUT,
S2MPS13_REG_B5CTRL,
S2MPS13_REG_B5OUT,
S2MPS13_REG_B6CTRL,
S2MPS13_REG_B6OUT,
S2MPS13_REG_B7CTRL,
S2MPS13_REG_B7SW,
S2MPS13_REG_B7OUT,
S2MPS13_REG_B8CTRL,
S2MPS13_REG_B8OUT,
S2MPS13_REG_B9CTRL,
S2MPS13_REG_B9OUT,
S2MPS13_REG_B10CTRL,
S2MPS13_REG_B10OUT,
S2MPS13_REG_BB1CTRL,
S2MPS13_REG_BB1OUT,
S2MPS13_REG_BUCK_RAMP1,
S2MPS13_REG_BUCK_RAMP2,
S2MPS13_REG_LDO_DVS1,
S2MPS13_REG_LDO_DVS2,
S2MPS13_REG_LDO_DVS3,
S2MPS13_REG_B6OUT2,
S2MPS13_REG_L1CTRL,
S2MPS13_REG_L2CTRL,
S2MPS13_REG_L3CTRL,
S2MPS13_REG_L4CTRL,
S2MPS13_REG_L5CTRL,
S2MPS13_REG_L6CTRL,
S2MPS13_REG_L7CTRL,
S2MPS13_REG_L8CTRL,
S2MPS13_REG_L9CTRL,
S2MPS13_REG_L10CTRL,
S2MPS13_REG_L11CTRL,
S2MPS13_REG_L12CTRL,
S2MPS13_REG_L13CTRL,
S2MPS13_REG_L14CTRL,
S2MPS13_REG_L15CTRL,
S2MPS13_REG_L16CTRL,
S2MPS13_REG_L17CTRL,
S2MPS13_REG_L18CTRL,
S2MPS13_REG_L19CTRL,
S2MPS13_REG_L20CTRL,
S2MPS13_REG_L21CTRL,
S2MPS13_REG_L22CTRL,
S2MPS13_REG_L23CTRL,
S2MPS13_REG_L24CTRL,
S2MPS13_REG_L25CTRL,
S2MPS13_REG_L26CTRL,
S2MPS13_REG_L27CTRL,
S2MPS13_REG_L28CTRL,
S2MPS13_REG_L29CTRL,
S2MPS13_REG_L30CTRL,
S2MPS13_REG_L31CTRL,
S2MPS13_REG_L32CTRL,
S2MPS13_REG_L33CTRL,
S2MPS13_REG_L34CTRL,
S2MPS13_REG_L35CTRL,
S2MPS13_REG_L36CTRL,
S2MPS13_REG_L37CTRL,
S2MPS13_REG_L38CTRL,
S2MPS13_REG_L39CTRL,
S2MPS13_REG_L40CTRL,
S2MPS13_REG_LDODSCH1,
S2MPS13_REG_LDODSCH2,
S2MPS13_REG_LDODSCH3,
S2MPS13_REG_LDODSCH4,
S2MPS13_REG_LDODSCH5,
};
/* regulator ids */
enum s2mps13_regulators {
S2MPS13_LDO1,
S2MPS13_LDO2,
S2MPS13_LDO3,
S2MPS13_LDO4,
S2MPS13_LDO5,
S2MPS13_LDO6,
S2MPS13_LDO7,
S2MPS13_LDO8,
S2MPS13_LDO9,
S2MPS13_LDO10,
S2MPS13_LDO11,
S2MPS13_LDO12,
S2MPS13_LDO13,
S2MPS13_LDO14,
S2MPS13_LDO15,
S2MPS13_LDO16,
S2MPS13_LDO17,
S2MPS13_LDO18,
S2MPS13_LDO19,
S2MPS13_LDO20,
S2MPS13_LDO21,
S2MPS13_LDO22,
S2MPS13_LDO23,
S2MPS13_LDO24,
S2MPS13_LDO25,
S2MPS13_LDO26,
S2MPS13_LDO27,
S2MPS13_LDO28,
S2MPS13_LDO29,
S2MPS13_LDO30,
S2MPS13_LDO31,
S2MPS13_LDO32,
S2MPS13_LDO33,
S2MPS13_LDO34,
S2MPS13_LDO35,
S2MPS13_LDO36,
S2MPS13_LDO37,
S2MPS13_LDO38,
S2MPS13_LDO39,
S2MPS13_LDO40,
S2MPS13_BUCK1,
S2MPS13_BUCK2,
S2MPS13_BUCK3,
S2MPS13_BUCK4,
S2MPS13_BUCK5,
S2MPS13_BUCK6,
S2MPS13_BUCK7,
S2MPS13_BUCK8,
S2MPS13_BUCK9,
S2MPS13_BUCK10,
S2MPS13_REGULATOR_MAX,
};
/*
* Default ramp delay in uv/us. Datasheet says that ramp delay can be
* controlled however it does not specify which register is used for that.
* Let's assume that default value will be set.
*/
#define S2MPS13_BUCK_RAMP_DELAY 12500
#define S2MPS13_REG_WRSTBI_MASK BIT(5)
#endif /* __LINUX_MFD_S2MPS13_H */
linux-7.2.3/include/linux/mfd/samsung/s2mps14.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S2MPS14_H
#define __LINUX_MFD_S2MPS14_H
/* S2MPS14 registers */
enum s2mps14_reg {
S2MPS14_REG_ID,
S2MPS14_REG_INT1,
S2MPS14_REG_INT2,
S2MPS14_REG_INT3,
S2MPS14_REG_INT1M,
S2MPS14_REG_INT2M,
S2MPS14_REG_INT3M,
S2MPS14_REG_ST1,
S2MPS14_REG_ST2,
S2MPS14_REG_PWRONSRC,
S2MPS14_REG_OFFSRC,
S2MPS14_REG_BU_CHG,
S2MPS14_REG_RTCCTRL,
S2MPS14_REG_CTRL1,
S2MPS14_REG_CTRL2,
S2MPS14_REG_RSVD1,
S2MPS14_REG_RSVD2,
S2MPS14_REG_RSVD3,
S2MPS14_REG_RSVD4,
S2MPS14_REG_RSVD5,
S2MPS14_REG_RSVD6,
S2MPS14_REG_CTRL3,
S2MPS14_REG_RSVD7,
S2MPS14_REG_RSVD8,
S2MPS14_REG_WRSTBI,
S2MPS14_REG_B1CTRL1,
S2MPS14_REG_B1CTRL2,
S2MPS14_REG_B2CTRL1,
S2MPS14_REG_B2CTRL2,
S2MPS14_REG_B3CTRL1,
S2MPS14_REG_B3CTRL2,
S2MPS14_REG_B4CTRL1,
S2MPS14_REG_B4CTRL2,
S2MPS14_REG_B5CTRL1,
S2MPS14_REG_B5CTRL2,
S2MPS14_REG_L1CTRL,
S2MPS14_REG_L2CTRL,
S2MPS14_REG_L3CTRL,
S2MPS14_REG_L4CTRL,
S2MPS14_REG_L5CTRL,
S2MPS14_REG_L6CTRL,
S2MPS14_REG_L7CTRL,
S2MPS14_REG_L8CTRL,
S2MPS14_REG_L9CTRL,
S2MPS14_REG_L10CTRL,
S2MPS14_REG_L11CTRL,
S2MPS14_REG_L12CTRL,
S2MPS14_REG_L13CTRL,
S2MPS14_REG_L14CTRL,
S2MPS14_REG_L15CTRL,
S2MPS14_REG_L16CTRL,
S2MPS14_REG_L17CTRL,
S2MPS14_REG_L18CTRL,
S2MPS14_REG_L19CTRL,
S2MPS14_REG_L20CTRL,
S2MPS14_REG_L21CTRL,
S2MPS14_REG_L22CTRL,
S2MPS14_REG_L23CTRL,
S2MPS14_REG_L24CTRL,
S2MPS14_REG_L25CTRL,
S2MPS14_REG_LDODSCH1,
S2MPS14_REG_LDODSCH2,
S2MPS14_REG_LDODSCH3,
};
/* S2MPS14 regulator ids */
enum s2mps14_regulators {
S2MPS14_LDO1,
S2MPS14_LDO2,
S2MPS14_LDO3,
S2MPS14_LDO4,
S2MPS14_LDO5,
S2MPS14_LDO6,
S2MPS14_LDO7,
S2MPS14_LDO8,
S2MPS14_LDO9,
S2MPS14_LDO10,
S2MPS14_LDO11,
S2MPS14_LDO12,
S2MPS14_LDO13,
S2MPS14_LDO14,
S2MPS14_LDO15,
S2MPS14_LDO16,
S2MPS14_LDO17,
S2MPS14_LDO18,
S2MPS14_LDO19,
S2MPS14_LDO20,
S2MPS14_LDO21,
S2MPS14_LDO22,
S2MPS14_LDO23,
S2MPS14_LDO24,
S2MPS14_LDO25,
S2MPS14_BUCK1,
S2MPS14_BUCK2,
S2MPS14_BUCK3,
S2MPS14_BUCK4,
S2MPS14_BUCK5,
S2MPS14_REGULATOR_MAX,
};
/* Regulator constraints for BUCKx */
#define S2MPS14_BUCK1235_START_SEL 0x20
#define S2MPS14_BUCK4_START_SEL 0x40
/*
* Default ramp delay in uv/us. Datasheet says that ramp delay can be
* controlled however it does not specify which register is used for that.
* Let's assume that default value will be set.
*/
#define S2MPS14_BUCK_RAMP_DELAY 12500
#define S2MPS14_LDO_VSEL_MASK 0x3F
#define S2MPS14_BUCK_VSEL_MASK 0xFF
#define S2MPS14_ENABLE_MASK (0x03 << S2MPS14_ENABLE_SHIFT)
#define S2MPS14_ENABLE_SHIFT 6
/* On/Off controlled by PWREN */
#define S2MPS14_ENABLE_SUSPEND (0x01 << S2MPS14_ENABLE_SHIFT)
/* On/Off controlled by LDO10EN or EMMCEN */
#define S2MPS14_ENABLE_EXT_CONTROL (0x00 << S2MPS14_ENABLE_SHIFT)
#define S2MPS14_LDO_N_VOLTAGES (S2MPS14_LDO_VSEL_MASK + 1)
#define S2MPS14_BUCK_N_VOLTAGES (S2MPS14_BUCK_VSEL_MASK + 1)
#endif /* __LINUX_MFD_S2MPS14_H */
linux-7.2.3/include/linux/mfd/samsung/s2mps15.h
+149
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S2MPS15_H
#define __LINUX_MFD_S2MPS15_H
/* S2MPS15 registers */
enum s2mps15_reg {
S2MPS15_REG_ID,
S2MPS15_REG_INT1,
S2MPS15_REG_INT2,
S2MPS15_REG_INT3,
S2MPS15_REG_INT1M,
S2MPS15_REG_INT2M,
S2MPS15_REG_INT3M,
S2MPS15_REG_ST1,
S2MPS15_REG_ST2,
S2MPS15_REG_PWRONSRC,
S2MPS15_REG_OFFSRC,
S2MPS15_REG_BU_CHG,
S2MPS15_REG_RTC_BUF,
S2MPS15_REG_CTRL1,
S2MPS15_REG_CTRL2,
S2MPS15_REG_RSVD1,
S2MPS15_REG_RSVD2,
S2MPS15_REG_RSVD3,
S2MPS15_REG_RSVD4,
S2MPS15_REG_RSVD5,
S2MPS15_REG_RSVD6,
S2MPS15_REG_CTRL3,
S2MPS15_REG_RSVD7,
S2MPS15_REG_RSVD8,
S2MPS15_REG_RSVD9,
S2MPS15_REG_B1CTRL1,
S2MPS15_REG_B1CTRL2,
S2MPS15_REG_B2CTRL1,
S2MPS15_REG_B2CTRL2,
S2MPS15_REG_B3CTRL1,
S2MPS15_REG_B3CTRL2,
S2MPS15_REG_B4CTRL1,
S2MPS15_REG_B4CTRL2,
S2MPS15_REG_B5CTRL1,
S2MPS15_REG_B5CTRL2,
S2MPS15_REG_B6CTRL1,
S2MPS15_REG_B6CTRL2,
S2MPS15_REG_B7CTRL1,
S2MPS15_REG_B7CTRL2,
S2MPS15_REG_B8CTRL1,
S2MPS15_REG_B8CTRL2,
S2MPS15_REG_B9CTRL1,
S2MPS15_REG_B9CTRL2,
S2MPS15_REG_B10CTRL1,
S2MPS15_REG_B10CTRL2,
S2MPS15_REG_BBCTRL1,
S2MPS15_REG_BBCTRL2,
S2MPS15_REG_BRAMP,
S2MPS15_REG_LDODVS1,
S2MPS15_REG_LDODVS2,
S2MPS15_REG_LDODVS3,
S2MPS15_REG_LDODVS4,
S2MPS15_REG_L1CTRL,
S2MPS15_REG_L2CTRL,
S2MPS15_REG_L3CTRL,
S2MPS15_REG_L4CTRL,
S2MPS15_REG_L5CTRL,
S2MPS15_REG_L6CTRL,
S2MPS15_REG_L7CTRL,
S2MPS15_REG_L8CTRL,
S2MPS15_REG_L9CTRL,
S2MPS15_REG_L10CTRL,
S2MPS15_REG_L11CTRL,
S2MPS15_REG_L12CTRL,
S2MPS15_REG_L13CTRL,
S2MPS15_REG_L14CTRL,
S2MPS15_REG_L15CTRL,
S2MPS15_REG_L16CTRL,
S2MPS15_REG_L17CTRL,
S2MPS15_REG_L18CTRL,
S2MPS15_REG_L19CTRL,
S2MPS15_REG_L20CTRL,
S2MPS15_REG_L21CTRL,
S2MPS15_REG_L22CTRL,
S2MPS15_REG_L23CTRL,
S2MPS15_REG_L24CTRL,
S2MPS15_REG_L25CTRL,
S2MPS15_REG_L26CTRL,
S2MPS15_REG_L27CTRL,
S2MPS15_REG_LDODSCH1,
S2MPS15_REG_LDODSCH2,
S2MPS15_REG_LDODSCH3,
S2MPS15_REG_LDODSCH4,
};
/* S2MPS15 regulator ids */
enum s2mps15_regulators {
S2MPS15_LDO1,
S2MPS15_LDO2,
S2MPS15_LDO3,
S2MPS15_LDO4,
S2MPS15_LDO5,
S2MPS15_LDO6,
S2MPS15_LDO7,
S2MPS15_LDO8,
S2MPS15_LDO9,
S2MPS15_LDO10,
S2MPS15_LDO11,
S2MPS15_LDO12,
S2MPS15_LDO13,
S2MPS15_LDO14,
S2MPS15_LDO15,
S2MPS15_LDO16,
S2MPS15_LDO17,
S2MPS15_LDO18,
S2MPS15_LDO19,
S2MPS15_LDO20,
S2MPS15_LDO21,
S2MPS15_LDO22,
S2MPS15_LDO23,
S2MPS15_LDO24,
S2MPS15_LDO25,
S2MPS15_LDO26,
S2MPS15_LDO27,
S2MPS15_BUCK1,
S2MPS15_BUCK2,
S2MPS15_BUCK3,
S2MPS15_BUCK4,
S2MPS15_BUCK5,
S2MPS15_BUCK6,
S2MPS15_BUCK7,
S2MPS15_BUCK8,
S2MPS15_BUCK9,
S2MPS15_BUCK10,
S2MPS15_BUCK11,
S2MPS15_REGULATOR_MAX,
};
#define S2MPS15_LDO_VSEL_MASK (0x3F)
#define S2MPS15_BUCK_VSEL_MASK (0xFF)
#define S2MPS15_ENABLE_SHIFT (0x06)
#define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
#define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
#define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
#endif /* __LINUX_MFD_S2MPS15_H */
linux-7.2.3/include/linux/mfd/samsung/s2mpu02.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S2MPU02_H
#define __LINUX_MFD_S2MPU02_H
/* S2MPU02 registers */
enum S2MPU02_reg {
S2MPU02_REG_ID,
S2MPU02_REG_INT1,
S2MPU02_REG_INT2,
S2MPU02_REG_INT3,
S2MPU02_REG_INT1M,
S2MPU02_REG_INT2M,
S2MPU02_REG_INT3M,
S2MPU02_REG_ST1,
S2MPU02_REG_ST2,
S2MPU02_REG_PWRONSRC,
S2MPU02_REG_OFFSRC,
S2MPU02_REG_BU_CHG,
S2MPU02_REG_RTCCTRL,
S2MPU02_REG_PMCTRL1,
S2MPU02_REG_RSVD1,
S2MPU02_REG_RSVD2,
S2MPU02_REG_RSVD3,
S2MPU02_REG_RSVD4,
S2MPU02_REG_RSVD5,
S2MPU02_REG_RSVD6,
S2MPU02_REG_RSVD7,
S2MPU02_REG_WRSTEN,
S2MPU02_REG_RSVD8,
S2MPU02_REG_RSVD9,
S2MPU02_REG_RSVD10,
S2MPU02_REG_B1CTRL1,
S2MPU02_REG_B1CTRL2,
S2MPU02_REG_B2CTRL1,
S2MPU02_REG_B2CTRL2,
S2MPU02_REG_B3CTRL1,
S2MPU02_REG_B3CTRL2,
S2MPU02_REG_B4CTRL1,
S2MPU02_REG_B4CTRL2,
S2MPU02_REG_B5CTRL1,
S2MPU02_REG_B5CTRL2,
S2MPU02_REG_B5CTRL3,
S2MPU02_REG_B5CTRL4,
S2MPU02_REG_B5CTRL5,
S2MPU02_REG_B6CTRL1,
S2MPU02_REG_B6CTRL2,
S2MPU02_REG_B7CTRL1,
S2MPU02_REG_B7CTRL2,
S2MPU02_REG_RAMP1,
S2MPU02_REG_RAMP2,
S2MPU02_REG_L1CTRL,
S2MPU02_REG_L2CTRL1,
S2MPU02_REG_L2CTRL2,
S2MPU02_REG_L2CTRL3,
S2MPU02_REG_L2CTRL4,
S2MPU02_REG_L3CTRL,
S2MPU02_REG_L4CTRL,
S2MPU02_REG_L5CTRL,
S2MPU02_REG_L6CTRL,
S2MPU02_REG_L7CTRL,
S2MPU02_REG_L8CTRL,
S2MPU02_REG_L9CTRL,
S2MPU02_REG_L10CTRL,
S2MPU02_REG_L11CTRL,
S2MPU02_REG_L12CTRL,
S2MPU02_REG_L13CTRL,
S2MPU02_REG_L14CTRL,
S2MPU02_REG_L15CTRL,
S2MPU02_REG_L16CTRL,
S2MPU02_REG_L17CTRL,
S2MPU02_REG_L18CTRL,
S2MPU02_REG_L19CTRL,
S2MPU02_REG_L20CTRL,
S2MPU02_REG_L21CTRL,
S2MPU02_REG_L22CTRL,
S2MPU02_REG_L23CTRL,
S2MPU02_REG_L24CTRL,
S2MPU02_REG_L25CTRL,
S2MPU02_REG_L26CTRL,
S2MPU02_REG_L27CTRL,
S2MPU02_REG_L28CTRL,
S2MPU02_REG_LDODSCH1,
S2MPU02_REG_LDODSCH2,
S2MPU02_REG_LDODSCH3,
S2MPU02_REG_LDODSCH4,
S2MPU02_REG_SELMIF,
S2MPU02_REG_RSVD11,
S2MPU02_REG_RSVD12,
S2MPU02_REG_RSVD13,
S2MPU02_REG_DVSSEL,
S2MPU02_REG_DVSPTR,
S2MPU02_REG_DVSDATA,
};
/* S2MPU02 regulator ids */
enum S2MPU02_regulators {
S2MPU02_LDO1,
S2MPU02_LDO2,
S2MPU02_LDO3,
S2MPU02_LDO4,
S2MPU02_LDO5,
S2MPU02_LDO6,
S2MPU02_LDO7,
S2MPU02_LDO8,
S2MPU02_LDO9,
S2MPU02_LDO10,
S2MPU02_LDO11,
S2MPU02_LDO12,
S2MPU02_LDO13,
S2MPU02_LDO14,
S2MPU02_LDO15,
S2MPU02_LDO16,
S2MPU02_LDO17,
S2MPU02_LDO18,
S2MPU02_LDO19,
S2MPU02_LDO20,
S2MPU02_LDO21,
S2MPU02_LDO22,
S2MPU02_LDO23,
S2MPU02_LDO24,
S2MPU02_LDO25,
S2MPU02_LDO26,
S2MPU02_LDO27,
S2MPU02_LDO28,
S2MPU02_BUCK1,
S2MPU02_BUCK2,
S2MPU02_BUCK3,
S2MPU02_BUCK4,
S2MPU02_BUCK5,
S2MPU02_BUCK6,
S2MPU02_BUCK7,
S2MPU02_REGULATOR_MAX,
};
/* Regulator constraints for BUCKx */
#define S2MPU02_BUCK1234_MIN_600MV 600000
#define S2MPU02_BUCK5_MIN_1081_25MV 1081250
#define S2MPU02_BUCK6_MIN_1700MV 1700000
#define S2MPU02_BUCK7_MIN_900MV 900000
#define S2MPU02_BUCK1234_STEP_6_25MV 6250
#define S2MPU02_BUCK5_STEP_6_25MV 6250
#define S2MPU02_BUCK6_STEP_2_50MV 2500
#define S2MPU02_BUCK7_STEP_6_25MV 6250
#define S2MPU02_BUCK1234_START_SEL 0x00
#define S2MPU02_BUCK5_START_SEL 0x4D
#define S2MPU02_BUCK6_START_SEL 0x28
#define S2MPU02_BUCK7_START_SEL 0x30
#define S2MPU02_BUCK_RAMP_DELAY 12500
/* Regulator constraints for different types of LDOx */
#define S2MPU02_LDO_MIN_900MV 900000
#define S2MPU02_LDO_MIN_1050MV 1050000
#define S2MPU02_LDO_MIN_1600MV 1600000
#define S2MPU02_LDO_STEP_12_5MV 12500
#define S2MPU02_LDO_STEP_25MV 25000
#define S2MPU02_LDO_STEP_50MV 50000
#define S2MPU02_LDO_GROUP1_START_SEL 0x8
#define S2MPU02_LDO_GROUP2_START_SEL 0xA
#define S2MPU02_LDO_GROUP3_START_SEL 0x10
#define S2MPU02_LDO_VSEL_MASK 0x3F
#define S2MPU02_BUCK_VSEL_MASK 0xFF
#define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT)
#define S2MPU02_ENABLE_SHIFT 6
/* On/Off controlled by PWREN */
#define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT)
#define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT)
#define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1)
#define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1)
/* RAMP delay for BUCK1234*/
#define S2MPU02_BUCK1_RAMP_SHIFT 6
#define S2MPU02_BUCK2_RAMP_SHIFT 4
#define S2MPU02_BUCK3_RAMP_SHIFT 2
#define S2MPU02_BUCK4_RAMP_SHIFT 0
#define S2MPU02_BUCK1234_RAMP_MASK 0x3
#endif /* __LINUX_MFD_S2MPU02_H */
linux-7.2.3/include/linux/mfd/samsung/s2mpu05.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd
* Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
*/
#ifndef __LINUX_MFD_S2MPU05_H
#define __LINUX_MFD_S2MPU05_H
/* S2MPU05 registers */
enum S2MPU05_reg {
S2MPU05_REG_ID,
S2MPU05_REG_INT1,
S2MPU05_REG_INT2,
S2MPU05_REG_INT3,
S2MPU05_REG_INT1M,
S2MPU05_REG_INT2M,
S2MPU05_REG_INT3M,
S2MPU05_REG_ST1,
S2MPU05_REG_ST2,
S2MPU05_REG_PWRONSRC,
S2MPU05_REG_OFFSRC,
S2MPU05_REG_BU_CHG,
S2MPU05_REG_RTC_BUF,
S2MPU05_REG_CTRL1,
S2MPU05_REG_CTRL2,
S2MPU05_REG_ETC_TEST,
S2MPU05_REG_OTP_ADRL,
S2MPU05_REG_OTP_ADRH,
S2MPU05_REG_OTP_DATA,
S2MPU05_REG_MON1SEL,
S2MPU05_REG_MON2SEL,
S2MPU05_REG_CTRL3,
S2MPU05_REG_ETC_OTP,
S2MPU05_REG_UVLO,
S2MPU05_REG_TIME_CTRL1,
S2MPU05_REG_TIME_CTRL2,
S2MPU05_REG_B1CTRL1,
S2MPU05_REG_B1CTRL2,
S2MPU05_REG_B2CTRL1,
S2MPU05_REG_B2CTRL2,
S2MPU05_REG_B2CTRL3,
S2MPU05_REG_B2CTRL4,
S2MPU05_REG_B3CTRL1,
S2MPU05_REG_B3CTRL2,
S2MPU05_REG_B3CTRL3,
S2MPU05_REG_B4CTRL1,
S2MPU05_REG_B4CTRL2,
S2MPU05_REG_B5CTRL1,
S2MPU05_REG_B5CTRL2,
S2MPU05_REG_BUCK_RAMP,
S2MPU05_REG_LDO_DVS1,
S2MPU05_REG_LDO_DVS9,
S2MPU05_REG_LDO_DVS10,
S2MPU05_REG_L1CTRL,
S2MPU05_REG_L2CTRL,
S2MPU05_REG_L3CTRL,
S2MPU05_REG_L4CTRL,
S2MPU05_REG_L5CTRL,
S2MPU05_REG_L6CTRL,
S2MPU05_REG_L7CTRL,
S2MPU05_REG_L8CTRL,
S2MPU05_REG_L9CTRL1,
S2MPU05_REG_L9CTRL2,
S2MPU05_REG_L10CTRL,
S2MPU05_REG_L11CTRL1,
S2MPU05_REG_L11CTRL2,
S2MPU05_REG_L12CTRL,
S2MPU05_REG_L13CTRL,
S2MPU05_REG_L14CTRL,
S2MPU05_REG_L15CTRL,
S2MPU05_REG_L16CTRL,
S2MPU05_REG_L17CTRL1,
S2MPU05_REG_L17CTRL2,
S2MPU05_REG_L18CTRL1,
S2MPU05_REG_L18CTRL2,
S2MPU05_REG_L19CTRL,
S2MPU05_REG_L20CTRL,
S2MPU05_REG_L21CTRL,
S2MPU05_REG_L22CTRL,
S2MPU05_REG_L23CTRL,
S2MPU05_REG_L24CTRL,
S2MPU05_REG_L25CTRL,
S2MPU05_REG_L26CTRL,
S2MPU05_REG_L27CTRL,
S2MPU05_REG_L28CTRL,
S2MPU05_REG_L29CTRL,
S2MPU05_REG_L30CTRL,
S2MPU05_REG_L31CTRL,
S2MPU05_REG_L32CTRL,
S2MPU05_REG_L33CTRL,
S2MPU05_REG_L34CTRL,
S2MPU05_REG_L35CTRL,
S2MPU05_REG_LDO_DSCH1,
S2MPU05_REG_LDO_DSCH2,
S2MPU05_REG_LDO_DSCH3,
S2MPU05_REG_LDO_DSCH4,
S2MPU05_REG_LDO_DSCH5,
S2MPU05_REG_LDO_CTRL1,
S2MPU05_REG_LDO_CTRL2,
S2MPU05_REG_TCXO_CTRL,
S2MPU05_REG_SELMIF,
};
/* S2MPU05 regulator ids */
enum S2MPU05_regulators {
S2MPU05_LDO1,
S2MPU05_LDO2,
S2MPU05_LDO3,
S2MPU05_LDO4,
S2MPU05_LDO5,
S2MPU05_LDO6,
S2MPU05_LDO7,
S2MPU05_LDO8,
S2MPU05_LDO9,
S2MPU05_LDO10,
S2MPU05_LDO11,
S2MPU05_LDO12,
S2MPU05_LDO13,
S2MPU05_LDO14,
S2MPU05_LDO15,
S2MPU05_LDO16,
S2MPU05_LDO17,
S2MPU05_LDO18,
S2MPU05_LDO19,
S2MPU05_LDO20,
S2MPU05_LDO21,
S2MPU05_LDO22,
S2MPU05_LDO23,
S2MPU05_LDO24,
S2MPU05_LDO25,
S2MPU05_LDO26,
S2MPU05_LDO27,
S2MPU05_LDO28,
S2MPU05_LDO29,
S2MPU05_LDO30,
S2MPU05_LDO31,
S2MPU05_LDO32,
S2MPU05_LDO33,
S2MPU05_LDO34,
S2MPU05_LDO35,
S2MPU05_BUCK1,
S2MPU05_BUCK2,
S2MPU05_BUCK3,
S2MPU05_BUCK4,
S2MPU05_BUCK5,
S2MPU05_REGULATOR_MAX,
};
#define S2MPU05_SW_ENABLE_MASK 0x03
#define S2MPU05_ENABLE_TIME_LDO 128
#define S2MPU05_ENABLE_TIME_BUCK1 110
#define S2MPU05_ENABLE_TIME_BUCK2 110
#define S2MPU05_ENABLE_TIME_BUCK3 110
#define S2MPU05_ENABLE_TIME_BUCK4 150
#define S2MPU05_ENABLE_TIME_BUCK5 150
#define S2MPU05_LDO_MIN1 800000
#define S2MPU05_LDO_MIN2 1800000
#define S2MPU05_LDO_MIN3 400000
#define S2MPU05_LDO_STEP1 12500
#define S2MPU05_LDO_STEP2 25000
#define S2MPU05_BUCK_MIN1 400000
#define S2MPU05_BUCK_MIN2 600000
#define S2MPU05_BUCK_STEP1 6250
#define S2MPU05_BUCK_STEP2 12500
#define S2MPU05_RAMP_DELAY 12000 /* uV/uS */
#define S2MPU05_ENABLE_SHIFT 6
#define S2MPU05_ENABLE_MASK (0x03 << S2MPU05_ENABLE_SHIFT)
#define S2MPU05_LDO_VSEL_MASK 0x3F
#define S2MPU05_BUCK_VSEL_MASK 0xFF
#define S2MPU05_LDO_N_VOLTAGES (S2MPU05_LDO_VSEL_MASK + 1)
#define S2MPU05_BUCK_N_VOLTAGES (S2MPU05_BUCK_VSEL_MASK + 1)
#define S2MPU05_PMIC_EN_SHIFT 6
#endif /* __LINUX_MFD_S2MPU05_H */
linux-7.2.3/include/linux/mfd/samsung/s2mu005.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd
* Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
* Copyright (c) 2026 Łukasz Lebiedziński <kernel@lvkasz.us>
*/
#ifndef __LINUX_MFD_S2MU005_H
#define __LINUX_MFD_S2MU005_H
#include <linux/bitfield.h>
#include <linux/bits.h>
/* S2MU005 registers */
enum s2mu005_reg {
S2MU005_REG_CHGR_INT1,
S2MU005_REG_CHGR_INT1M,
S2MU005_REG_FLED_INT1,
S2MU005_REG_FLED_INT1M,
S2MU005_REG_MUIC_INT1,
S2MU005_REG_MUIC_INT2,
S2MU005_REG_MUIC_INT1M,
S2MU005_REG_MUIC_INT2M,
S2MU005_REG_CHGR_STATUS0,
S2MU005_REG_CHGR_STATUS1,
S2MU005_REG_CHGR_STATUS2,
S2MU005_REG_CHGR_STATUS3,
S2MU005_REG_CHGR_STATUS4,
S2MU005_REG_CHGR_STATUS5,
S2MU005_REG_CHGR_CTRL0,
S2MU005_REG_CHGR_CTRL1,
S2MU005_REG_CHGR_CTRL2,
S2MU005_REG_CHGR_CTRL3,
S2MU005_REG_CHGR_CTRL4,
S2MU005_REG_CHGR_CTRL5,
S2MU005_REG_CHGR_CTRL6,
S2MU005_REG_CHGR_CTRL7,
S2MU005_REG_CHGR_CTRL8,
S2MU005_REG_CHGR_CTRL9,
S2MU005_REG_CHGR_CTRL10,
S2MU005_REG_CHGR_CTRL11,
S2MU005_REG_CHGR_CTRL12,
S2MU005_REG_CHGR_CTRL13,
S2MU005_REG_CHGR_CTRL14,
S2MU005_REG_CHGR_CTRL15,
S2MU005_REG_CHGR_CTRL16,
S2MU005_REG_CHGR_CTRL17,
S2MU005_REG_CHGR_CTRL18,
S2MU005_REG_CHGR_CTRL19,
S2MU005_REG_CHGR_TEST0,
S2MU005_REG_CHGR_TEST1,
S2MU005_REG_CHGR_TEST2,
S2MU005_REG_CHGR_TEST3,
S2MU005_REG_CHGR_TEST4,
S2MU005_REG_CHGR_TEST5,
S2MU005_REG_CHGR_TEST6,
S2MU005_REG_CHGR_TEST7,
S2MU005_REG_CHGR_TEST8,
S2MU005_REG_CHGR_TEST9,
S2MU005_REG_CHGR_TEST10,
S2MU005_REG_FLED_STATUS,
S2MU005_REG_FLED_CH0_CTRL0,
S2MU005_REG_FLED_CH0_CTRL1,
S2MU005_REG_FLED_CH0_CTRL2,
S2MU005_REG_FLED_CH0_CTRL3,
S2MU005_REG_FLED_CH1_CTRL0,
S2MU005_REG_FLED_CH1_CTRL1,
S2MU005_REG_FLED_CH1_CTRL2,
S2MU005_REG_FLED_CH1_CTRL3,
S2MU005_REG_FLED_CTRL0,
S2MU005_REG_FLED_CTRL1,
S2MU005_REG_FLED_CTRL2,
S2MU005_REG_FLED_CTRL3,
S2MU005_REG_FLED_CTRL4,
S2MU005_REG_FLED_CTRL5,
S2MU005_REG_FLED_CTRL6,
S2MU005_REG_RGB_EN,
S2MU005_REG_RGB_CH0_CTRL,
S2MU005_REG_RGB_CH1_CTRL,
S2MU005_REG_RGB_CH2_CTRL,
S2MU005_REG_RGB_CH0_RAMP,
S2MU005_REG_RGB_CH0_STAY,
S2MU005_REG_RGB_CH1_RAMP,
S2MU005_REG_RGB_CH1_STAY,
S2MU005_REG_RGB_CH2_RAMP,
S2MU005_REG_RGB_CH2_STAY,
S2MU005_REG_RGB_TEST0,
S2MU005_REG_RGB_CTRL0,
S2MU005_REG_MUIC_ADC,
S2MU005_REG_MUIC_DEV1,
S2MU005_REG_MUIC_DEV2,
S2MU005_REG_MUIC_DEV3,
S2MU005_REG_MUIC_BUTTON1,
S2MU005_REG_MUIC_BUTTON2,
S2MU005_REG_MUIC_RESET,
S2MU005_REG_MUIC_CHGTYPE,
S2MU005_REG_MUIC_DEVAPPLE,
S2MU005_REG_MUIC_BCDRESCAN,
S2MU005_REG_MUIC_TEST1,
S2MU005_REG_MUIC_TEST2,
S2MU005_REG_MUIC_TEST3,
S2MU005_REG_ID = 0x73,
S2MU005_REG_MUIC_CTRL1 = 0xb2,
S2MU005_REG_MUIC_TIMERSET1,
S2MU005_REG_MUIC_TIMERSET2,
S2MU005_REG_MUIC_SWCTRL,
S2MU005_REG_MUIC_TIMERSET3,
S2MU005_REG_MUIC_CTRL2,
S2MU005_REG_MUIC_CTRL3,
S2MU005_REG_MUIC_LDOADC_L = 0xbf,
S2MU005_REG_MUIC_LDOADC_H,
};
#define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x))
#define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x))
#define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x))
#define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x))
#define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x))
#define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x))
#define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x))
/* S2MU005_REG_CHGR_STATUS0 */
#define S2MU005_CHGR_VBUS BIT(7)
#define S2MU005_CHGR_WCIN BIT(6)
#define S2MU005_CHGR_VMID BIT(5)
#define S2MU005_CHGR_CHG BIT(4)
#define S2MU005_CHGR_STAT GENMASK(3, 0)
#define S2MU005_CHGR_STAT_DONE 8
#define S2MU005_CHGR_STAT_TOPOFF 7
#define S2MU005_CHGR_STAT_DONE_FLAG 6
#define S2MU005_CHGR_STAT_CV 5
#define S2MU005_CHGR_STAT_CC 4
#define S2MU005_CHGR_STAT_COOL_CHG 3
#define S2MU005_CHGR_STAT_PRE_CHG 2
/* S2MU005_REG_CHGR_STATUS1 */
#define S2MU005_CHGR_DETBAT BIT(7)
#define S2MU005_CHGR_VBUS_OVP GENMASK(6, 4)
#define S2MU005_CHGR_VBUS_OVP_OVERVOLT 2
/* S2MU005_REG_CHGR_STATUS2 */
#define S2MU005_CHGR_BAT GENMASK(6, 4)
#define S2MU005_CHGR_BAT_VOLT_DET 7
#define S2MU005_CHGR_BAT_FAST_CHG_DET 6
#define S2MU005_CHGR_BAT_COOL_CHG_DET 5
#define S2MU005_CHGR_BAT_LOW_CHG 2
#define S2MU005_CHGR_BAT_SELF_DISCHG 1
#define S2MU005_CHGR_BAT_OVP_DET 0
/* S2MU005_REG_CHGR_STATUS3 */
#define S2MU005_CHGR_EVT GENMASK(3, 0)
#define S2MU005_CHGR_EVT_WDT_RST 6
#define S2MU005_CHGR_EVT_WDT_SUSP 5
#define S2MU005_CHGR_EVT_VSYS_VUVLO 4
#define S2MU005_CHGR_EVT_VSYS_VOVP 3
#define S2MU005_CHGR_EVT_THERM_FOLDBACK 2
#define S2MU005_CHGR_EVT_THERM_SHUTDOWN 1
/* S2MU005_REG_CHGR_CTRL0 */
#define S2MU005_CHGR_CHG_EN BIT(4)
#define S2MU005_CHGR_OP_MODE GENMASK(2, 0)
#define S2MU005_CHGR_OP_MODE_OTG BIT(2)
#define S2MU005_CHGR_OP_MODE_CHG BIT(1)
/* S2MU005_REG_CHGR_CTRL1 */
#define S2MU005_CHGR_VIN_DROP GENMASK(6, 4)
/* S2MU005_REG_CHGR_CTRL2 */
#define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0)
/* S2MU005_REG_CHGR_CTRL4 */
#define S2MU005_CHGR_OTG_OCP_ON BIT(5)
#define S2MU005_CHGR_OTG_OCP_OFF BIT(4)
#define S2MU005_CHGR_OTG_OCP GENMASK(3, 2)
#define S2MU005_CHGR_OTG_OCP_1P5A 0x3
/* S2MU005_REG_CHGR_CTRL5 */
#define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0)
#define S2MU005_CHGR_VMID_BOOST_5P1V 0x16
/* S2MU005_REG_CHGR_CTRL6 */
#define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0)
/* S2MU005_REG_CHGR_CTRL7 */
#define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0)
/* S2MU005_REG_CHGR_CTRL8 */
#define S2MU005_CHGR_VF_VBAT GENMASK(6, 1)
/* S2MU005_REG_CHGR_CTRL10 */
#define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x))
/* S2MU005_REG_CHGR_CTRL11 */
#define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5)
#define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3)
#define S2MU005_CHGR_OSC_BOOST_2MHZ 0x3
/* S2MU005_REG_CHGR_CTRL12 */
#define S2MU005_CHGR_WDT GENMASK(2, 0)
#define S2MU005_CHGR_WDT_ON BIT(2)
#define S2MU005_CHGR_WDT_OFF BIT(1)
/* S2MU005_REG_CHGR_CTRL15 */
#define S2MU005_CHGR_OTG_EN GENMASK(3, 2)
#define S2MU005_CHGR_OTG_EN_ON 0x3
/* S2MU005_REG_FLED_STATUS */
#define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x))
#define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x))
/* S2MU005_REG_FLED_CHx_CTRL0 */
#define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0)
/* S2MU005_REG_FLED_CHx_CTRL1 */
#define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0)
/* S2MU005_REG_FLED_CHx_CTRL2 */
#define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0)
/* S2MU005_REG_FLED_CHx_CTRL3 */
#define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0)
/* S2MU005_REG_FLED_CTRL1 */
#define S2MU005_FLED_CH_EN BIT(7)
/*
* S2MU005_REG_FLED_CTRL4 - Rev. EVT0
* S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later
*/
#define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x))
#define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x))
/* S2MU005_REG_RGB_EN */
#define S2MU005_RGB_RESET BIT(6)
#define S2MU005_RGB_SLOPE GENMASK(5, 0)
#define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0))
#define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1))
/* S2MU005_REG_RGB_CHx_RAMP */
#define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4)
#define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0)
/* S2MU005_REG_RGB_CHx_STAY */
#define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4)
#define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0)
/* S2MU005_REG_MUIC_DEV1 */
#define S2MU005_MUIC_OTG BIT(7)
#define S2MU005_MUIC_DCP BIT(6)
#define S2MU005_MUIC_CDP BIT(5)
#define S2MU005_MUIC_T1_T2_CHG BIT(4)
#define S2MU005_MUIC_UART BIT(3)
#define S2MU005_MUIC_SDP BIT(2)
#define S2MU005_MUIC_LANHUB BIT(1)
#define S2MU005_MUIC_AUDIO BIT(0)
/* S2MU005_REG_MUIC_DEV2 */
#define S2MU005_MUIC_SDP_1P8S BIT(7)
#define S2MU005_MUIC_AV BIT(6)
#define S2MU005_MUIC_TTY BIT(5)
#define S2MU005_MUIC_PPD BIT(4)
#define S2MU005_MUIC_JIG_UART_OFF BIT(3)
#define S2MU005_MUIC_JIG_UART_ON BIT(2)
#define S2MU005_MUIC_JIG_USB_OFF BIT(1)
#define S2MU005_MUIC_JIG_USB_ON BIT(0)
/* S2MU005_REG_MUIC_DEV3 */
#define S2MU005_MUIC_U200_CHG BIT(7)
#define S2MU005_MUIC_VBUS_AV BIT(4)
#define S2MU005_MUIC_VBUS_R255 BIT(1)
#define S2MU005_MUIC_MHL BIT(0)
/* S2MU005_REG_MUIC_DEVAPPLE */
#define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7)
#define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6)
#define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5)
#define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4)
#define S2MU005_MUIC_SDP_DCD_OUT BIT(3)
#define S2MU005_MUIC_RID_WAKEUP BIT(2)
#define S2MU005_MUIC_VBUS_WAKEUP BIT(1)
#define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0)
/* S2MU005_REG_ID */
#define S2MU005_ID_MASK GENMASK(3, 0)
/* S2MU005_REG_MUIC_SWCTRL */
#define S2MU005_MUIC_DM_DP GENMASK(7, 2)
#define S2MU005_MUIC_JIG BIT(0)
#define S2MU005_MUIC_DM_DP_UART 0x12
#define S2MU005_MUIC_DM_DP_USB 0x09
/* S2MU005_REG_MUIC_CTRL1 */
#define S2MU005_MUIC_OPEN BIT(4)
#define S2MU005_MUIC_RAW_DATA BIT(3)
#define S2MU005_MUIC_MAN_SW BIT(2)
#define S2MU005_MUIC_WAIT BIT(1)
#define S2MU005_MUIC_IRQ BIT(0)
/* S2MU005_REG_MUIC_CTRL3 */
#define S2MU005_MUIC_ONESHOT_ADC BIT(2)
/* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */
#define S2MU005_MUIC_VSET GENMASK(4, 0)
#define S2MU005_MUIC_VSET_3P0V 0x1f
#define S2MU005_MUIC_VSET_2P6V 0x0e
#define S2MU005_MUIC_VSET_2P4V 0x0c
#define S2MU005_MUIC_VSET_2P2V 0x0a
#define S2MU005_MUIC_VSET_2P0V 0x08
#define S2MU005_MUIC_VSET_1P5V 0x03
#define S2MU005_MUIC_VSET_1P4V 0x02
#define S2MU005_MUIC_VSET_1P2V 0x00
#endif /* __LINUX_MFD_S2MU005_H */
linux-7.2.3/include/linux/mfd/samsung/s5m8767.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*/
#ifndef __LINUX_MFD_S5M8767_H
#define __LINUX_MFD_S5M8767_H
/* S5M8767 registers */
enum s5m8767_reg {
S5M8767_REG_ID,
S5M8767_REG_INT1,
S5M8767_REG_INT2,
S5M8767_REG_INT3,
S5M8767_REG_INT1M,
S5M8767_REG_INT2M,
S5M8767_REG_INT3M,
S5M8767_REG_STATUS1,
S5M8767_REG_STATUS2,
S5M8767_REG_STATUS3,
S5M8767_REG_CTRL1,
S5M8767_REG_CTRL2,
S5M8767_REG_LOWBAT1,
S5M8767_REG_LOWBAT2,
S5M8767_REG_BUCHG,
S5M8767_REG_DVSRAMP,
S5M8767_REG_DVSTIMER2 = 0x10,
S5M8767_REG_DVSTIMER3,
S5M8767_REG_DVSTIMER4,
S5M8767_REG_LDO1,
S5M8767_REG_LDO2,
S5M8767_REG_LDO3,
S5M8767_REG_LDO4,
S5M8767_REG_LDO5,
S5M8767_REG_LDO6,
S5M8767_REG_LDO7,
S5M8767_REG_LDO8,
S5M8767_REG_LDO9,
S5M8767_REG_LDO10,
S5M8767_REG_LDO11,
S5M8767_REG_LDO12,
S5M8767_REG_LDO13,
S5M8767_REG_LDO14 = 0x20,
S5M8767_REG_LDO15,
S5M8767_REG_LDO16,
S5M8767_REG_LDO17,
S5M8767_REG_LDO18,
S5M8767_REG_LDO19,
S5M8767_REG_LDO20,
S5M8767_REG_LDO21,
S5M8767_REG_LDO22,
S5M8767_REG_LDO23,
S5M8767_REG_LDO24,
S5M8767_REG_LDO25,
S5M8767_REG_LDO26,
S5M8767_REG_LDO27,
S5M8767_REG_LDO28,
S5M8767_REG_UVLO = 0x31,
S5M8767_REG_BUCK1CTRL1,
S5M8767_REG_BUCK1CTRL2,
S5M8767_REG_BUCK2CTRL,
S5M8767_REG_BUCK2DVS1,
S5M8767_REG_BUCK2DVS2,
S5M8767_REG_BUCK2DVS3,
S5M8767_REG_BUCK2DVS4,
S5M8767_REG_BUCK2DVS5,
S5M8767_REG_BUCK2DVS6,
S5M8767_REG_BUCK2DVS7,
S5M8767_REG_BUCK2DVS8,
S5M8767_REG_BUCK3CTRL,
S5M8767_REG_BUCK3DVS1,
S5M8767_REG_BUCK3DVS2,
S5M8767_REG_BUCK3DVS3,
S5M8767_REG_BUCK3DVS4,
S5M8767_REG_BUCK3DVS5,
S5M8767_REG_BUCK3DVS6,
S5M8767_REG_BUCK3DVS7,
S5M8767_REG_BUCK3DVS8,
S5M8767_REG_BUCK4CTRL,
S5M8767_REG_BUCK4DVS1,
S5M8767_REG_BUCK4DVS2,
S5M8767_REG_BUCK4DVS3,
S5M8767_REG_BUCK4DVS4,
S5M8767_REG_BUCK4DVS5,
S5M8767_REG_BUCK4DVS6,
S5M8767_REG_BUCK4DVS7,
S5M8767_REG_BUCK4DVS8,
S5M8767_REG_BUCK5CTRL1,
S5M8767_REG_BUCK5CTRL2,
S5M8767_REG_BUCK5CTRL3,
S5M8767_REG_BUCK5CTRL4,
S5M8767_REG_BUCK5CTRL5,
S5M8767_REG_BUCK6CTRL1,
S5M8767_REG_BUCK6CTRL2,
S5M8767_REG_BUCK7CTRL1,
S5M8767_REG_BUCK7CTRL2,
S5M8767_REG_BUCK8CTRL1,
S5M8767_REG_BUCK8CTRL2,
S5M8767_REG_BUCK9CTRL1,
S5M8767_REG_BUCK9CTRL2,
S5M8767_REG_LDO1CTRL,
S5M8767_REG_LDO2_1CTRL,
S5M8767_REG_LDO2_2CTRL,
S5M8767_REG_LDO2_3CTRL,
S5M8767_REG_LDO2_4CTRL,
S5M8767_REG_LDO3CTRL,
S5M8767_REG_LDO4CTRL,
S5M8767_REG_LDO5CTRL,
S5M8767_REG_LDO6CTRL,
S5M8767_REG_LDO7CTRL,
S5M8767_REG_LDO8CTRL,
S5M8767_REG_LDO9CTRL,
S5M8767_REG_LDO10CTRL,
S5M8767_REG_LDO11CTRL,
S5M8767_REG_LDO12CTRL,
S5M8767_REG_LDO13CTRL,
S5M8767_REG_LDO14CTRL,
S5M8767_REG_LDO15CTRL,
S5M8767_REG_LDO16CTRL,
S5M8767_REG_LDO17CTRL,
S5M8767_REG_LDO18CTRL,
S5M8767_REG_LDO19CTRL,
S5M8767_REG_LDO20CTRL,
S5M8767_REG_LDO21CTRL,
S5M8767_REG_LDO22CTRL,
S5M8767_REG_LDO23CTRL,
S5M8767_REG_LDO24CTRL,
S5M8767_REG_LDO25CTRL,
S5M8767_REG_LDO26CTRL,
S5M8767_REG_LDO27CTRL,
S5M8767_REG_LDO28CTRL,
};
/* S5M8767 regulator ids */
enum s5m8767_regulators {
S5M8767_LDO1,
S5M8767_LDO2,
S5M8767_LDO3,
S5M8767_LDO4,
S5M8767_LDO5,
S5M8767_LDO6,
S5M8767_LDO7,
S5M8767_LDO8,
S5M8767_LDO9,
S5M8767_LDO10,
S5M8767_LDO11,
S5M8767_LDO12,
S5M8767_LDO13,
S5M8767_LDO14,
S5M8767_LDO15,
S5M8767_LDO16,
S5M8767_LDO17,
S5M8767_LDO18,
S5M8767_LDO19,
S5M8767_LDO20,
S5M8767_LDO21,
S5M8767_LDO22,
S5M8767_LDO23,
S5M8767_LDO24,
S5M8767_LDO25,
S5M8767_LDO26,
S5M8767_LDO27,
S5M8767_LDO28,
S5M8767_BUCK1,
S5M8767_BUCK2,
S5M8767_BUCK3,
S5M8767_BUCK4,
S5M8767_BUCK5,
S5M8767_BUCK6,
S5M8767_BUCK7,
S5M8767_BUCK8,
S5M8767_BUCK9,
S5M8767_AP_EN32KHZ,
S5M8767_CP_EN32KHZ,
S5M8767_REG_MAX,
};
/* LDO_EN/BUCK_EN field in registers */
#define S5M8767_ENCTRL_SHIFT 6
#define S5M8767_ENCTRL_MASK (0x3 << S5M8767_ENCTRL_SHIFT)
/*
* LDO_EN/BUCK_EN register value for controlling this Buck or LDO
* by GPIO (PWREN, BUCKEN).
*/
#define S5M8767_ENCTRL_USE_GPIO 0x1
/*
* Values for BUCK_RAMP field in DVS_RAMP register, matching raw values
* in mV/us.
*/
enum s5m8767_dvs_buck_ramp_values {
S5M8767_DVS_BUCK_RAMP_5 = 0x4,
S5M8767_DVS_BUCK_RAMP_10 = 0x9,
S5M8767_DVS_BUCK_RAMP_12_5 = 0xb,
S5M8767_DVS_BUCK_RAMP_25 = 0xd,
S5M8767_DVS_BUCK_RAMP_50 = 0xe,
S5M8767_DVS_BUCK_RAMP_100 = 0xf,
};
#define S5M8767_DVS_BUCK_RAMP_SHIFT 4
#define S5M8767_DVS_BUCK_RAMP_MASK (0xf << S5M8767_DVS_BUCK_RAMP_SHIFT)
#endif /* __LINUX_MFD_S5M8767_H */