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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/include/linux/platform_data/x86/amd-fch.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_AMD_FCH_H_
#define _ASM_X86_AMD_FCH_H_
#define FCH_PM_BASE 0xFED80300
/* Register offsets from PM base: */
#define FCH_PM_DECODEEN 0x00
#define FCH_PM_DECODEEN_SMBUS0SEL GENMASK(20, 19)
#define FCH_PM_SCRATCH 0x80
#define FCH_PM_S5_RESET_STATUS 0xC0
#endif /* _ASM_X86_AMD_FCH_H_ */
linux-7.2.3/include/linux/platform_data/x86/apple.h
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#ifndef PLATFORM_DATA_X86_APPLE_H
#define PLATFORM_DATA_X86_APPLE_H
#ifdef CONFIG_X86
/**
* x86_apple_machine - whether the machine is an x86 Apple Macintosh
*/
extern bool x86_apple_machine;
#else
#define x86_apple_machine false
#endif
#endif
linux-7.2.3/include/linux/platform_data/x86/asus-wmi.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PLATFORM_DATA_X86_ASUS_WMI_H
#define __PLATFORM_DATA_X86_ASUS_WMI_H
#include <linux/errno.h>
#include <linux/types.h>
#define ASUS_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66"
#define ASUS_ACPI_UID_ASUSWMI "ASUSWMI"
/* WMI Methods */
#define ASUS_WMI_METHODID_SPEC 0x43455053 /* BIOS SPECification */
#define ASUS_WMI_METHODID_SFBD 0x44424653 /* Set First Boot Device */
#define ASUS_WMI_METHODID_GLCD 0x44434C47 /* Get LCD status */
#define ASUS_WMI_METHODID_GPID 0x44495047 /* Get Panel ID?? (Resol) */
#define ASUS_WMI_METHODID_QMOD 0x444F4D51 /* Quiet MODe */
#define ASUS_WMI_METHODID_SPLV 0x4C425053 /* Set Panel Light Value */
#define ASUS_WMI_METHODID_AGFN 0x4E464741 /* Atk Generic FuNction */
#define ASUS_WMI_METHODID_SFUN 0x4E554653 /* FUNCtionalities */
#define ASUS_WMI_METHODID_SDSP 0x50534453 /* Set DiSPlay output */
#define ASUS_WMI_METHODID_GDSP 0x50534447 /* Get DiSPlay output */
#define ASUS_WMI_METHODID_DEVP 0x50564544 /* DEVice Policy */
#define ASUS_WMI_METHODID_OSVR 0x5256534F /* OS VeRsion */
#define ASUS_WMI_METHODID_DCTS 0x53544344 /* Device status (DCTS) */
#define ASUS_WMI_METHODID_DSTS 0x53545344 /* Device status (DSTS) */
#define ASUS_WMI_METHODID_BSTS 0x53545342 /* Bios STatuS ? */
#define ASUS_WMI_METHODID_DEVS 0x53564544 /* DEVice Set */
#define ASUS_WMI_METHODID_CFVS 0x53564643 /* CPU Frequency Volt Set */
#define ASUS_WMI_METHODID_KBFT 0x5446424B /* KeyBoard FilTer */
#define ASUS_WMI_METHODID_INIT 0x54494E49 /* INITialize */
#define ASUS_WMI_METHODID_HKEY 0x59454B48 /* Hot KEY ?? */
#define ASUS_WMI_METHODID_NOTIF 0x00100021 /* Notify method */
#define ASUS_WMI_UNSUPPORTED_METHOD 0xFFFFFFFE
/* Wireless */
#define ASUS_WMI_DEVID_HW_SWITCH 0x00010001
#define ASUS_WMI_DEVID_WIRELESS_LED 0x00010002
#define ASUS_WMI_DEVID_CWAP 0x00010003
#define ASUS_WMI_DEVID_WLAN 0x00010011
#define ASUS_WMI_DEVID_WLAN_LED 0x00010012
#define ASUS_WMI_DEVID_BLUETOOTH 0x00010013
#define ASUS_WMI_DEVID_GPS 0x00010015
#define ASUS_WMI_DEVID_WIMAX 0x00010017
#define ASUS_WMI_DEVID_WWAN3G 0x00010019
#define ASUS_WMI_DEVID_UWB 0x00010021
/* Leds */
/* 0x000200XX and 0x000400XX */
#define ASUS_WMI_DEVID_LED1 0x00020011
#define ASUS_WMI_DEVID_LED2 0x00020012
#define ASUS_WMI_DEVID_LED3 0x00020013
#define ASUS_WMI_DEVID_LED4 0x00020014
#define ASUS_WMI_DEVID_LED5 0x00020015
#define ASUS_WMI_DEVID_LED6 0x00020016
#define ASUS_WMI_DEVID_MICMUTE_LED 0x00040017
/* Disable Camera LED */
#define ASUS_WMI_DEVID_CAMERA_LED_NEG 0x00060078 /* 0 = on (unused) */
#define ASUS_WMI_DEVID_CAMERA_LED 0x00060079 /* 1 = on */
/* Backlight and Brightness */
#define ASUS_WMI_DEVID_ALS_ENABLE 0x00050001 /* Ambient Light Sensor */
#define ASUS_WMI_DEVID_BACKLIGHT 0x00050011
#define ASUS_WMI_DEVID_BRIGHTNESS 0x00050012
#define ASUS_WMI_DEVID_KBD_BACKLIGHT 0x00050021
#define ASUS_WMI_DEVID_LIGHT_SENSOR 0x00050022 /* ?? */
#define ASUS_WMI_DEVID_LIGHTBAR 0x00050025
#define ASUS_WMI_DEVID_OOBE 0x0005002F
/* This can only be used to disable the screen, not re-enable */
#define ASUS_WMI_DEVID_SCREENPAD_POWER 0x00050031
/* Writing a brightness re-enables the screen if disabled */
#define ASUS_WMI_DEVID_SCREENPAD_LIGHT 0x00050032
#define ASUS_WMI_DEVID_FAN_BOOST_MODE 0x00110018
#define ASUS_WMI_DEVID_THROTTLE_THERMAL_POLICY 0x00120075
#define ASUS_WMI_DEVID_THROTTLE_THERMAL_POLICY_VIVO 0x00110019
/* Misc */
#define ASUS_WMI_DEVID_PANEL_HD 0x0005001C
#define ASUS_WMI_DEVID_PANEL_OD 0x00050019
#define ASUS_WMI_DEVID_CAMERA 0x00060013
#define ASUS_WMI_DEVID_LID_FLIP 0x00060062
#define ASUS_WMI_DEVID_LID_FLIP_ROG 0x00060077
#define ASUS_WMI_DEVID_MINI_LED_MODE 0x0005001E
#define ASUS_WMI_DEVID_MINI_LED_MODE2 0x0005002E
#define ASUS_WMI_DEVID_SCREEN_AUTO_BRIGHTNESS 0x0005002A
/* Storage */
#define ASUS_WMI_DEVID_CARDREADER 0x00080013
/* Input */
#define ASUS_WMI_DEVID_TOUCHPAD 0x00100011
#define ASUS_WMI_DEVID_TOUCHPAD_LED 0x00100012
#define ASUS_WMI_DEVID_FNLOCK 0x00100023
/* Fan, Thermal */
#define ASUS_WMI_DEVID_THERMAL_CTRL 0x00110011
#define ASUS_WMI_DEVID_FAN_CTRL 0x00110012 /* deprecated */
#define ASUS_WMI_DEVID_CPU_FAN_CTRL 0x00110013
#define ASUS_WMI_DEVID_GPU_FAN_CTRL 0x00110014
#define ASUS_WMI_DEVID_MID_FAN_CTRL 0x00110031
#define ASUS_WMI_DEVID_CPU_FAN_CURVE 0x00110024
#define ASUS_WMI_DEVID_GPU_FAN_CURVE 0x00110025
#define ASUS_WMI_DEVID_MID_FAN_CURVE 0x00110032
/* Tunables for AUS ROG laptops */
#define ASUS_WMI_DEVID_PPT_PL2_SPPT 0x001200A0
#define ASUS_WMI_DEVID_PPT_PL1_SPL 0x001200A3
#define ASUS_WMI_DEVID_PPT_APU_SPPT 0x001200B0
#define ASUS_WMI_DEVID_PPT_PLAT_SPPT 0x001200B1
#define ASUS_WMI_DEVID_PPT_PL3_FPPT 0x001200C1
#define ASUS_WMI_DEVID_NV_DYN_BOOST 0x001200C0
#define ASUS_WMI_DEVID_NV_THERM_TARGET 0x001200C2
/* Power */
#define ASUS_WMI_DEVID_PROCESSOR_STATE 0x00120012
/* Deep S3 / Resume on LID open */
#define ASUS_WMI_DEVID_LID_RESUME 0x00120031
/* Maximum charging percentage */
#define ASUS_WMI_DEVID_RSOC 0x00120057
/* Keyboard dock */
#define ASUS_WMI_DEVID_KBD_DOCK 0x00120063
/* Charging mode - 1=Barrel, 2=USB */
#define ASUS_WMI_DEVID_CHARGE_MODE 0x0012006C
/* MCU powersave mode */
#define ASUS_WMI_DEVID_MCU_POWERSAVE 0x001200E2
/* epu is connected? 1 == true */
#define ASUS_WMI_DEVID_EGPU_CONNECTED 0x00090018
/* egpu on/off */
#define ASUS_WMI_DEVID_EGPU 0x00090019
/* dgpu on/off */
#define ASUS_WMI_DEVID_DGPU 0x00090020
#define ASUS_WMI_DEVID_APU_MEM 0x000600C1
#define ASUS_WMI_DEVID_DGPU_BASE_TGP 0x00120099
#define ASUS_WMI_DEVID_DGPU_SET_TGP 0x00120098
/* gpu mux switch, 0 = dGPU, 1 = Optimus */
#define ASUS_WMI_DEVID_GPU_MUX 0x00090016
#define ASUS_WMI_DEVID_GPU_MUX_VIVO 0x00090026
/* Keystone dongle insert/remove state.
* PRESENCE_BIT (0x00010000) encodes insert state:
* 0x00010000 = inserted, 0x00000000 = absent. STATUS_BIT is never set.
* 0xFFFFFFFE means no keystone slot on this machine.
*/
#define ASUS_WMI_DEVID_KEYSTONE 0x00120091
/* TUF laptop RGB modes/colours */
#define ASUS_WMI_DEVID_TUF_RGB_MODE 0x00100056
#define ASUS_WMI_DEVID_TUF_RGB_MODE2 0x0010005A
/* TUF laptop RGB power/state */
#define ASUS_WMI_DEVID_TUF_RGB_STATE 0x00100057
/* Bootup sound control */
#define ASUS_WMI_DEVID_BOOT_SOUND 0x00130022
/* DSTS masks */
#define ASUS_WMI_DSTS_STATUS_BIT 0x00000001
#define ASUS_WMI_DSTS_UNKNOWN_BIT 0x00000002
#define ASUS_WMI_DSTS_PRESENCE_BIT 0x00010000
#define ASUS_WMI_DSTS_USER_BIT 0x00020000
#define ASUS_WMI_DSTS_BIOS_BIT 0x00040000
#define ASUS_WMI_DSTS_BRIGHTNESS_MASK 0x000000FF
#define ASUS_WMI_DSTS_MAX_BRIGTH_MASK 0x0000FF00
#define ASUS_WMI_DSTS_LIGHTBAR_MASK 0x0000000F
enum asus_ally_mcu_hack {
ASUS_WMI_ALLY_MCU_HACK_INIT,
ASUS_WMI_ALLY_MCU_HACK_ENABLED,
ASUS_WMI_ALLY_MCU_HACK_DISABLED,
};
/* Used to notify hid-asus when asus-wmi changes keyboard backlight */
struct asus_hid_listener {
struct list_head list;
void (*brightness_set)(struct asus_hid_listener *listener, int brightness);
};
enum asus_hid_event {
ASUS_EV_BRTUP,
ASUS_EV_BRTDOWN,
ASUS_EV_BRTTOGGLE,
};
#define ASUS_EV_MAX_BRIGHTNESS 3
#if IS_REACHABLE(CONFIG_ASUS_WMI)
void set_ally_mcu_hack(enum asus_ally_mcu_hack status);
void set_ally_mcu_powersave(bool enabled);
int asus_wmi_get_devstate_dsts(u32 dev_id, u32 *retval);
int asus_wmi_set_devstate(u32 dev_id, u32 ctrl_param, u32 *retval);
int asus_wmi_evaluate_method(u32 method_id, u32 arg0, u32 arg1, u32 *retval);
int asus_hid_register_listener(struct asus_hid_listener *cdev);
void asus_hid_unregister_listener(struct asus_hid_listener *cdev);
int asus_hid_event(enum asus_hid_event event);
#else
static inline void set_ally_mcu_hack(enum asus_ally_mcu_hack status)
{
}
static inline void set_ally_mcu_powersave(bool enabled)
{
}
static inline int asus_wmi_set_devstate(u32 dev_id, u32 ctrl_param, u32 *retval)
{
return -ENODEV;
}
static inline int asus_wmi_get_devstate_dsts(u32 dev_id, u32 *retval)
{
return -ENODEV;
}
static inline int asus_wmi_evaluate_method(u32 method_id, u32 arg0, u32 arg1,
u32 *retval)
{
return -ENODEV;
}
static inline int asus_hid_register_listener(struct asus_hid_listener *bdev)
{
return -ENODEV;
}
static inline void asus_hid_unregister_listener(struct asus_hid_listener *bdev)
{
}
static inline int asus_hid_event(enum asus_hid_event event)
{
return -ENODEV;
}
#endif
#endif /* __PLATFORM_DATA_X86_ASUS_WMI_H */
linux-7.2.3/include/linux/platform_data/x86/clk-lpss.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Intel Low Power Subsystem clocks.
*
* Copyright (C) 2013, Intel Corporation
* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
* Rafael J. Wysocki <rafael.j.wysocki@intel.com>
*/
#ifndef __CLK_LPSS_H
#define __CLK_LPSS_H
struct lpss_clk_data {
const char *name;
struct clk *clk;
};
int lpss_atom_clk_init(void);
#endif /* __CLK_LPSS_H */
linux-7.2.3/include/linux/platform_data/x86/clk-pmc-atom.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Intel Atom platform clocks for BayTrail and CherryTrail SoC.
*
* Copyright (C) 2016, Intel Corporation
* Author: Irina Tirdea <irina.tirdea@intel.com>
*/
#ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
#define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
/**
* struct pmc_clk - PMC platform clock configuration
*
* @name: identified, typically pmc_plt_clk_<x>, x=[0..5]
* @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported
* @parent_name: one of 'xtal' or 'osc'
*/
struct pmc_clk {
const char *name;
unsigned long freq;
const char *parent_name;
};
/**
* struct pmc_clk_data - common PMC clock configuration
*
* @base: PMC clock register base offset
* @clks: pointer to set of registered clocks, typically 0..5
* @critical: flag to indicate if firmware enabled pmc_plt_clks
* should be marked as critial or not
*/
struct pmc_clk_data {
void __iomem *base;
const struct pmc_clk *clks;
bool critical;
};
#endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */
linux-7.2.3/include/linux/platform_data/x86/int3472.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel INT3472 ACPI camera sensor power-management support
*
* Author: Dan Scally <djrscally@gmail.com>
*/
#ifndef __PLATFORM_DATA_X86_INT3472_H
#define __PLATFORM_DATA_X86_INT3472_H
#include <linux/clk-provider.h>
#include <linux/gpio/machine.h>
#include <linux/leds.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/device-id/dmi.h>
#include <linux/types.h>
/* FIXME drop this once the I2C_DEV_NAME_FORMAT macro has been added to include/linux/i2c.h */
#ifndef I2C_DEV_NAME_FORMAT
#define I2C_DEV_NAME_FORMAT "i2c-%s"
#endif
/* PMIC GPIO Types */
#define INT3472_GPIO_TYPE_RESET 0x00
#define INT3472_GPIO_TYPE_POWERDOWN 0x01
#define INT3472_GPIO_TYPE_STROBE 0x02
#define INT3472_GPIO_TYPE_POWER_ENABLE 0x0b
#define INT3472_GPIO_TYPE_CLK_ENABLE 0x0c
#define INT3472_GPIO_TYPE_PRIVACY_LED 0x0d
#define INT3472_GPIO_TYPE_DOVDD 0x10
#define INT3472_GPIO_TYPE_HANDSHAKE 0x12
#define INT3472_GPIO_TYPE_HOTPLUG_DETECT 0x13
#define INT3472_PDEV_MAX_NAME_LEN 23
#define INT3472_MAX_SENSOR_GPIOS 3
#define INT3472_MAX_LEDS 2
#define INT3472_MAX_REGULATORS 3
/* E.g. "dovdd\0" */
#define GPIO_SUPPLY_NAME_LENGTH 6
/* 12 chars for acpi_dev_name() + "-", e.g. "ABCD1234:00-" */
#define GPIO_REGULATOR_NAME_LENGTH (12 + GPIO_SUPPLY_NAME_LENGTH)
/* lower- and upper-case mapping */
#define GPIO_REGULATOR_SUPPLY_MAP_COUNT 2
/*
* Ensure the GPIO is driven low/high for at least 2 ms before changing.
*
* 2 ms has been chosen because it is the minimum time ovXXXX sensors need to
* have their reset line driven logical high to properly register a reset.
*/
#define GPIO_REGULATOR_ENABLE_TIME (2 * USEC_PER_MSEC)
#define GPIO_REGULATOR_OFF_ON_DELAY (2 * USEC_PER_MSEC)
#define INT3472_LED_MAX_NAME_LEN 32
#define CIO2_SENSOR_SSDB_MCLKSPEED_OFFSET 86
#define INT3472_REGULATOR(_name, _ops, _enable_time, _off_on_delay) \
(const struct regulator_desc) { \
.name = _name, \
.type = REGULATOR_VOLTAGE, \
.ops = _ops, \
.owner = THIS_MODULE, \
.enable_time = _enable_time, \
.off_on_delay = _off_on_delay, \
}
#define to_int3472_clk(hw) \
container_of(hw, struct int3472_clock, clk_hw)
#define to_int3472_device(clk) \
container_of(clk, struct int3472_discrete_device, clock)
struct acpi_device;
struct i2c_client;
struct platform_device;
struct int3472_cldb {
u8 version;
/*
* control logic type
* 0: UNKNOWN
* 1: DISCRETE(CRD-D)
* 2: PMIC TPS68470
* 3: PMIC uP6641
*/
u8 control_logic_type;
u8 control_logic_id;
u8 sensor_card_sku;
u8 reserved[10];
u8 clock_source;
u8 reserved2[17];
};
struct int3472_discrete_quirks {
/* For models where AVDD GPIO is shared between sensors */
const char *avdd_second_sensor;
};
struct int3472_gpio_regulator {
/* SUPPLY_MAP_COUNT * 2 to make room for second sensor mappings */
struct regulator_consumer_supply supply_map[GPIO_REGULATOR_SUPPLY_MAP_COUNT * 2];
char supply_name_upper[GPIO_SUPPLY_NAME_LENGTH];
char regulator_name[GPIO_REGULATOR_NAME_LENGTH];
struct regulator_dev *rdev;
struct regulator_desc rdesc;
};
struct int3472_discrete_device {
struct acpi_device *adev;
struct device *dev;
struct acpi_device *sensor;
const char *sensor_name;
struct int3472_gpio_regulator regulators[INT3472_MAX_REGULATORS];
struct int3472_clock {
struct clk *clk;
struct clk_hw clk_hw;
struct clk_lookup *cl;
struct gpio_desc *ena_gpio;
u32 frequency;
u8 imgclk_index;
} clock;
struct int3472_led {
struct led_classdev classdev;
struct led_lookup_data lookup;
char name[INT3472_LED_MAX_NAME_LEN];
struct gpio_desc *gpio;
} leds[INT3472_MAX_LEDS];
struct int3472_discrete_quirks quirks;
unsigned int ngpios; /* how many GPIOs have we seen */
unsigned int n_leds; /* how many LEDs have we registered */
unsigned int n_sensor_gpios; /* how many have we mapped to sensor */
unsigned int n_regulator_gpios; /* how many have we mapped to a regulator */
struct gpiod_lookup_table gpios;
};
extern const struct dmi_system_id skl_int3472_discrete_quirks[];
union acpi_object *skl_int3472_get_acpi_buffer(struct acpi_device *adev,
char *id);
int skl_int3472_fill_cldb(struct acpi_device *adev, struct int3472_cldb *cldb);
int skl_int3472_get_sensor_adev_and_name(struct device *dev,
struct acpi_device **sensor_adev_ret,
const char **name_ret);
int int3472_discrete_parse_crs(struct int3472_discrete_device *int3472);
void int3472_discrete_cleanup(struct int3472_discrete_device *int3472);
int skl_int3472_register_gpio_clock(struct int3472_discrete_device *int3472,
struct gpio_desc *gpio);
int skl_int3472_register_dsm_clock(struct int3472_discrete_device *int3472);
void skl_int3472_unregister_clock(struct int3472_discrete_device *int3472);
int skl_int3472_register_regulator(struct int3472_discrete_device *int3472,
struct gpio_desc *gpio,
unsigned int enable_time,
const char *supply_name,
const char *second_sensor);
void skl_int3472_unregister_regulator(struct int3472_discrete_device *int3472);
int skl_int3472_register_led(struct int3472_discrete_device *int3472, struct gpio_desc *gpio,
const char *con_id);
void skl_int3472_unregister_leds(struct int3472_discrete_device *int3472);
#endif
linux-7.2.3/include/linux/platform_data/x86/intel-mid_wdt.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* intel-mid_wdt: generic Intel MID SCU watchdog driver
*
* Copyright (C) 2014 Intel Corporation. All rights reserved.
* Contact: David Cohen <david.a.cohen@linux.intel.com>
*/
#ifndef __PLATFORM_X86_INTEL_MID_WDT_H_
#define __PLATFORM_X86_INTEL_MID_WDT_H_
#include <linux/platform_device.h>
struct intel_mid_wdt_pdata {
int irq;
int (*probe)(struct platform_device *pdev);
};
#endif /* __PLATFORM_X86_INTEL_MID_WDT_H_ */
linux-7.2.3/include/linux/platform_data/x86/intel_pmc_ipc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel Core SoC Power Management Controller Header File
*
* Copyright (c) 2025, Intel Corporation.
* All Rights Reserved.
*
*/
#ifndef INTEL_PMC_IPC_H
#define INTEL_PMC_IPC_H
#include <linux/acpi.h>
#include <linux/cleanup.h>
#define IPC_SOC_REGISTER_ACCESS 0xAA
#define IPC_SOC_SUB_CMD_READ 0x00
#define IPC_SOC_SUB_CMD_WRITE 0x01
#define PMC_IPCS_PARAM_COUNT 7
#define VALID_IPC_RESPONSE 5
struct pmc_ipc_cmd {
u32 cmd;
u32 sub_cmd;
u32 size;
u32 wbuf[4];
};
struct pmc_ipc_rbuf {
u32 buf[4];
};
/**
* intel_pmc_ipc() - PMC IPC Mailbox accessor
* @ipc_cmd: Prepared input command to send
* @rbuf: Allocated array for returned IPC data
*
* Return: 0 on success. Non-zero on mailbox error
*/
static inline int intel_pmc_ipc(struct pmc_ipc_cmd *ipc_cmd, struct pmc_ipc_rbuf *rbuf)
{
#ifdef CONFIG_ACPI
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object params[PMC_IPCS_PARAM_COUNT] = {
{.type = ACPI_TYPE_INTEGER,},
{.type = ACPI_TYPE_INTEGER,},
{.type = ACPI_TYPE_INTEGER,},
{.type = ACPI_TYPE_INTEGER,},
{.type = ACPI_TYPE_INTEGER,},
{.type = ACPI_TYPE_INTEGER,},
{.type = ACPI_TYPE_INTEGER,},
};
struct acpi_object_list arg_list = { PMC_IPCS_PARAM_COUNT, params };
int status;
if (!ipc_cmd || !rbuf)
return -EINVAL;
/*
* 0: IPC Command
* 1: IPC Sub Command
* 2: Size
* 3-6: Write Buffer for offset
*/
params[0].integer.value = ipc_cmd->cmd;
params[1].integer.value = ipc_cmd->sub_cmd;
params[2].integer.value = ipc_cmd->size;
params[3].integer.value = ipc_cmd->wbuf[0];
params[4].integer.value = ipc_cmd->wbuf[1];
params[5].integer.value = ipc_cmd->wbuf[2];
params[6].integer.value = ipc_cmd->wbuf[3];
status = acpi_evaluate_object(NULL, "\\IPCS", &arg_list, &buffer);
if (ACPI_FAILURE(status))
return -ENODEV;
union acpi_object *obj __free(kfree) = buffer.pointer;
if (obj && obj->type == ACPI_TYPE_PACKAGE &&
obj->package.count == VALID_IPC_RESPONSE) {
const union acpi_object *objs = obj->package.elements;
if ((u8)objs[0].integer.value != 0)
return -EINVAL;
rbuf->buf[0] = objs[1].integer.value;
rbuf->buf[1] = objs[2].integer.value;
rbuf->buf[2] = objs[3].integer.value;
rbuf->buf[3] = objs[4].integer.value;
} else {
return -EINVAL;
}
return 0;
#else
return -ENODEV;
#endif /* CONFIG_ACPI */
}
#endif /* INTEL_PMC_IPC_H */
linux-7.2.3/include/linux/platform_data/x86/intel_scu_ipc.h
+72
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PLATFORM_X86_INTEL_SCU_IPC_H_
#define __PLATFORM_X86_INTEL_SCU_IPC_H_
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/types.h>
struct device;
struct module;
struct intel_scu_ipc_dev;
/**
* struct intel_scu_ipc_data - Data used to configure SCU IPC
* @mem: Base address of SCU IPC MMIO registers
* @irq: The IRQ number used for SCU (optional)
*/
struct intel_scu_ipc_data {
struct resource mem;
int irq;
};
struct intel_scu_ipc_dev *
__intel_scu_ipc_register(struct device *parent,
const struct intel_scu_ipc_data *scu_data,
struct module *owner);
#define intel_scu_ipc_register(parent, scu_data) \
__intel_scu_ipc_register(parent, scu_data, THIS_MODULE)
void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu);
struct intel_scu_ipc_dev *
__devm_intel_scu_ipc_register(struct device *parent,
const struct intel_scu_ipc_data *scu_data,
struct module *owner);
#define devm_intel_scu_ipc_register(parent, scu_data) \
__devm_intel_scu_ipc_register(parent, scu_data, THIS_MODULE)
struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void);
void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu);
struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev);
int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr,
u8 *data);
int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr,
u8 data);
int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr,
u8 *data, size_t len);
int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr,
u8 *data, size_t len);
int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr,
u8 data, u8 mask);
int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
int sub);
int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
int sub, const void *in, size_t inlen,
size_t size, void *out, size_t outlen);
static inline int intel_scu_ipc_dev_command(struct intel_scu_ipc_dev *scu, int cmd,
int sub, const void *in, size_t inlen,
void *out, size_t outlen)
{
return intel_scu_ipc_dev_command_with_size(scu, cmd, sub, in, inlen,
inlen, out, outlen);
}
#endif
linux-7.2.3/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
+76
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __PLATFORM_DATA_X86_NVIDIA_WMI_EC_BACKLIGHT_H
#define __PLATFORM_DATA_X86_NVIDIA_WMI_EC_BACKLIGHT_H
#define WMI_BRIGHTNESS_GUID "603E9613-EF25-4338-A3D0-C46177516DB7"
/**
* enum wmi_brightness_method - WMI method IDs
* @WMI_BRIGHTNESS_METHOD_LEVEL: Get/Set EC brightness level status
* @WMI_BRIGHTNESS_METHOD_SOURCE: Get/Set EC Brightness Source
*/
enum wmi_brightness_method {
WMI_BRIGHTNESS_METHOD_LEVEL = 1,
WMI_BRIGHTNESS_METHOD_SOURCE = 2,
WMI_BRIGHTNESS_METHOD_MAX
};
/**
* enum wmi_brightness_mode - Operation mode for WMI-wrapped method
* @WMI_BRIGHTNESS_MODE_GET: Get the current brightness level/source.
* @WMI_BRIGHTNESS_MODE_SET: Set the brightness level.
* @WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL: Get the maximum brightness level. This
* is only valid when the WMI method is
* %WMI_BRIGHTNESS_METHOD_LEVEL.
*/
enum wmi_brightness_mode {
WMI_BRIGHTNESS_MODE_GET = 0,
WMI_BRIGHTNESS_MODE_SET = 1,
WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL = 2,
WMI_BRIGHTNESS_MODE_MAX
};
/**
* enum wmi_brightness_source - Backlight brightness control source selection
* @WMI_BRIGHTNESS_SOURCE_GPU: Backlight brightness is controlled by the GPU.
* @WMI_BRIGHTNESS_SOURCE_EC: Backlight brightness is controlled by the
* system's Embedded Controller (EC).
* @WMI_BRIGHTNESS_SOURCE_AUX: Backlight brightness is controlled over the
* DisplayPort AUX channel.
*/
enum wmi_brightness_source {
WMI_BRIGHTNESS_SOURCE_GPU = 1,
WMI_BRIGHTNESS_SOURCE_EC = 2,
WMI_BRIGHTNESS_SOURCE_AUX = 3,
WMI_BRIGHTNESS_SOURCE_MAX
};
/**
* struct wmi_brightness_args - arguments for the WMI-wrapped ACPI method
* @mode: Pass in an &enum wmi_brightness_mode value to select between
* getting or setting a value.
* @val: In parameter for value to set when using %WMI_BRIGHTNESS_MODE_SET
* mode. Not used in conjunction with %WMI_BRIGHTNESS_MODE_GET or
* %WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL mode.
* @ret: Out parameter returning retrieved value when operating in
* %WMI_BRIGHTNESS_MODE_GET or %WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL
* mode. Not used in %WMI_BRIGHTNESS_MODE_SET mode.
* @ignored: Padding; not used. The ACPI method expects a 24 byte params struct.
*
* This is the parameters structure for the WmiBrightnessNotify ACPI method as
* wrapped by WMI. The value passed in to @val or returned by @ret will be a
* brightness value when the WMI method ID is %WMI_BRIGHTNESS_METHOD_LEVEL, or
* an &enum wmi_brightness_source value with %WMI_BRIGHTNESS_METHOD_SOURCE.
*/
struct wmi_brightness_args {
u32 mode;
u32 val;
u32 ret;
u32 ignored[3];
};
#endif
linux-7.2.3/include/linux/platform_data/x86/p2sb.h
+28
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Primary to Sideband (P2SB) bridge access support
*/
#ifndef _PLATFORM_DATA_X86_P2SB_H
#define _PLATFORM_DATA_X86_P2SB_H
#include <linux/errno.h>
#include <linux/kconfig.h>
struct pci_bus;
struct resource;
#if IS_BUILTIN(CONFIG_P2SB)
int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem);
#else /* CONFIG_P2SB */
static inline int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem)
{
return -ENODEV;
}
#endif /* CONFIG_P2SB is not set */
#endif /* _PLATFORM_DATA_X86_P2SB_H */
linux-7.2.3/include/linux/platform_data/x86/pmc_atom.h
+163
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Intel Atom SoC Power Management Controller Header File
* Copyright (c) 2014-2015,2022 Intel Corporation.
*/
#ifndef PMC_ATOM_H
#define PMC_ATOM_H
#include <linux/bits.h>
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
/* CherryTrail Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_CHT_PMC 0x229C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
#define PMC_BASE_ADDR_MASK 0xFFFFFE00
#define PMC_MMIO_REG_LEN 0x100
#define PMC_REG_BIT_WIDTH 32
/* BIOS uses FUNC_DIS to disable specific function */
#define PMC_FUNC_DIS 0x34
#define PMC_FUNC_DIS_2 0x38
/* CHT specific bits in FUNC_DIS2 register */
#define BIT_FD_GMM BIT(3)
#define BIT_FD_ISH BIT(4)
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
#define BIT_LPC_CLOCK_RUN BIT(4)
#define BIT_SHARED_IRQ_GPSC BIT(5)
#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
#define BIT_SHARED_IRQ_GPSS BIT(20)
#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
BIT_SHARED_IRQ_GPSC | \
BIT_ORED_DEDICATED_IRQ_GPSS | \
BIT_ORED_DEDICATED_IRQ_GPSC | \
BIT_SHARED_IRQ_GPSS)
/* External clk generator settings */
#define PMC_CLK_CTL_OFFSET 0x60
#define PMC_CLK_CTL_SIZE 4
#define PMC_CLK_NUM 6
#define PMC_CLK_CTL_GATED_ON_D3 0x0
#define PMC_CLK_CTL_FORCE_ON 0x1
#define PMC_CLK_CTL_FORCE_OFF 0x2
#define PMC_CLK_CTL_RESERVED 0x3
#define PMC_MASK_CLK_CTL GENMASK(1, 0)
#define PMC_MASK_CLK_FREQ BIT(2)
#define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
#define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
/* The timers accumulate time spent in sleep state */
#define PMC_S0IR_TMR 0x80
#define PMC_S0I1_TMR 0x84
#define PMC_S0I2_TMR 0x88
#define PMC_S0I3_TMR 0x8C
#define PMC_S0_TMR 0x90
/* Sleep state counter is in units of 32us */
#define PMC_TMR_SHIFT 5
/* Power status of power islands */
#define PMC_PSS 0x98
#define PMC_PSS_BIT_GBE BIT(0)
#define PMC_PSS_BIT_SATA BIT(1)
#define PMC_PSS_BIT_HDA BIT(2)
#define PMC_PSS_BIT_SEC BIT(3)
#define PMC_PSS_BIT_PCIE BIT(4)
#define PMC_PSS_BIT_LPSS BIT(5)
#define PMC_PSS_BIT_LPE BIT(6)
#define PMC_PSS_BIT_DFX BIT(7)
#define PMC_PSS_BIT_USH_CTRL BIT(8)
#define PMC_PSS_BIT_USH_SUS BIT(9)
#define PMC_PSS_BIT_USH_VCCS BIT(10)
#define PMC_PSS_BIT_USH_VCCA BIT(11)
#define PMC_PSS_BIT_OTG_CTRL BIT(12)
#define PMC_PSS_BIT_OTG_VCCS BIT(13)
#define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14)
#define PMC_PSS_BIT_OTG_VCCA BIT(15)
#define PMC_PSS_BIT_USB BIT(16)
#define PMC_PSS_BIT_USB_SUS BIT(17)
/* CHT specific bits in PSS register */
#define PMC_PSS_BIT_CHT_UFS BIT(7)
#define PMC_PSS_BIT_CHT_UXD BIT(11)
#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
#define PMC_PSS_BIT_CHT_GMM BIT(17)
#define PMC_PSS_BIT_CHT_ISH BIT(18)
#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0
#define BIT_LPSS1_F0_DMA BIT(0)
#define BIT_LPSS1_F1_PWM1 BIT(1)
#define BIT_LPSS1_F2_PWM2 BIT(2)
#define BIT_LPSS1_F3_HSUART1 BIT(3)
#define BIT_LPSS1_F4_HSUART2 BIT(4)
#define BIT_LPSS1_F5_SPI BIT(5)
#define BIT_LPSS1_F6_XXX BIT(6)
#define BIT_LPSS1_F7_XXX BIT(7)
#define BIT_SCC_EMMC BIT(8)
#define BIT_SCC_SDIO BIT(9)
#define BIT_SCC_SDCARD BIT(10)
#define BIT_SCC_MIPI BIT(11)
#define BIT_HDA BIT(12) /* CHT datasheet: reserved */
#define BIT_LPE BIT(13)
#define BIT_OTG BIT(14)
#define BIT_USH BIT(15) /* CHT datasheet: reserved */
#define BIT_GBE BIT(16) /* CHT datasheet: reserved */
#define BIT_SATA BIT(17) /* CHT datasheet: reserved */
#define BIT_USB_EHCI BIT(18) /* CHT datasheet: XHCI! */
#define BIT_SEC BIT(19) /* BYT datasheet: reserved */
#define BIT_PCIE_PORT0 BIT(20)
#define BIT_PCIE_PORT1 BIT(21)
#define BIT_PCIE_PORT2 BIT(22)
#define BIT_PCIE_PORT3 BIT(23)
#define BIT_LPSS2_F0_DMA BIT(24)
#define BIT_LPSS2_F1_I2C1 BIT(25)
#define BIT_LPSS2_F2_I2C2 BIT(26)
#define BIT_LPSS2_F3_I2C3 BIT(27)
#define BIT_LPSS2_F4_I2C4 BIT(28)
#define BIT_LPSS2_F5_I2C5 BIT(29)
#define BIT_LPSS2_F6_I2C6 BIT(30)
#define BIT_LPSS2_F7_I2C7 BIT(31)
#define PMC_D3_STS_1 0xA4
#define BIT_SMB BIT(0)
#define BIT_OTG_SS_PHY BIT(1)
#define BIT_USH_SS_PHY BIT(2)
#define BIT_DFX BIT(3)
/* CHT specific bits in PMC_D3_STS_1 register */
#define BIT_STS_GMM BIT(1)
#define BIT_STS_ISH BIT(2)
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
#define ACPI_MMIO_REG_LEN 0x100
#define PM1_CNT 0x4
#define SLEEP_TYPE_MASK GENMASK(12, 10)
#define SLEEP_TYPE_S5 0x1C00
#define SLEEP_ENABLE BIT(13)
extern int pmc_atom_read(int offset, u32 *value);
#endif /* PMC_ATOM_H */
linux-7.2.3/include/linux/platform_data/x86/pwm-lpss.h
+60
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Intel Low Power Subsystem PWM controller driver */
#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H
#define __PLATFORM_DATA_X86_PWM_LPSS_H
#include <linux/types.h>
struct device;
struct pwm_lpss_chip;
struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
unsigned long base_unit_bits;
/*
* NOTE:
* Intel Broxton, Apollo Lake, and Gemini Lake have different programming flow.
*
* Initial Enable or First Activation
* 1. Program the base unit and on time divisor values.
* 2. Set the software update bit.
* 3. Poll in a loop on the PWMCTRL bit until software update bit is cleared.+
* 4. Enable the PWM output by setting PWM Enable.
* 5. Repeat the above steps for the next PWM Module.
*
* Dynamic update while PWM is Enabled
* 1. Program the base unit and on-time divisor values.
* 2. Set the software update bit.
* 3. Repeat the above steps for the next PWM module.
*
* + After setting PWMCTRL register's SW update bit, hardware automatically
* deasserts the SW update bit after a brief delay. It was observed that
* setting of PWM enable is typically done via read-modify-write of the PWMCTRL
* register. If there is no/little delay between setting software update bit
* and setting enable bit via read-modify-write, it is possible that the read
* could return with software enable as 1. In that case, the last write to set
* enable to 1 could also set sw_update to 1. If this happens, sw_update gets
* stuck and the driver code can hang as it explicitly waits for sw_update bit
* to be 0 after setting the enable bit to 1. To avoid this race condition,
* SW should poll on the software update bit to make sure that it is 0 before
* doing the read-modify-write to set the enable bit to 1.
*
* Also, we noted that if sw_update bit was set in step #1 above then when it
* is set again in step #2, sw_update bit never gets cleared and the flow hangs.
* As such, we need to make sure that sw_update bit is 0 when doing step #1.
*/
bool bypass;
/*
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
* messes with the PWM0 controllers state,
*/
bool other_devices_aml_touches_pwm_regs;
};
struct pwm_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info);
#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */
linux-7.2.3/include/linux/platform_data/x86/simatic-ipc-base.h
+31
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Siemens SIMATIC IPC drivers
*
* Copyright (c) Siemens AG, 2018-2023
*
* Authors:
* Henning Schild <henning.schild@siemens.com>
* Gerd Haeussler <gerd.haeussler.ext@siemens.com>
*/
#ifndef __PLATFORM_DATA_X86_SIMATIC_IPC_BASE_H
#define __PLATFORM_DATA_X86_SIMATIC_IPC_BASE_H
#include <linux/types.h>
#define SIMATIC_IPC_DEVICE_NONE 0
#define SIMATIC_IPC_DEVICE_227D 1
#define SIMATIC_IPC_DEVICE_427E 2
#define SIMATIC_IPC_DEVICE_127E 3
#define SIMATIC_IPC_DEVICE_227E 4
#define SIMATIC_IPC_DEVICE_227G 5
#define SIMATIC_IPC_DEVICE_BX_21A 6
#define SIMATIC_IPC_DEVICE_BX_39A 7
#define SIMATIC_IPC_DEVICE_BX_59A 8
struct simatic_ipc_platform {
u8 devmode;
};
#endif /* __PLATFORM_DATA_X86_SIMATIC_IPC_BASE_H */
linux-7.2.3/include/linux/platform_data/x86/simatic-ipc.h
+79
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Siemens SIMATIC IPC drivers
*
* Copyright (c) Siemens AG, 2018-2023
*
* Authors:
* Henning Schild <henning.schild@siemens.com>
* Gerd Haeussler <gerd.haeussler.ext@siemens.com>
*/
#ifndef __PLATFORM_DATA_X86_SIMATIC_IPC_H
#define __PLATFORM_DATA_X86_SIMATIC_IPC_H
#include <linux/dmi.h>
#include <linux/platform_data/x86/simatic-ipc-base.h>
#define SIMATIC_IPC_DMI_ENTRY_OEM 129
/* binary type */
#define SIMATIC_IPC_DMI_TYPE 0xff
#define SIMATIC_IPC_DMI_GROUP 0x05
#define SIMATIC_IPC_DMI_ENTRY 0x02
#define SIMATIC_IPC_DMI_TID 0x02
enum simatic_ipc_station_ids {
SIMATIC_IPC_INVALID_STATION_ID = 0,
SIMATIC_IPC_IPC227D = 0x00000501,
SIMATIC_IPC_IPC427D = 0x00000701,
SIMATIC_IPC_IPC227E = 0x00000901,
SIMATIC_IPC_IPC277E = 0x00000902,
SIMATIC_IPC_IPC427E = 0x00000A01,
SIMATIC_IPC_IPC477E = 0x00000A02,
SIMATIC_IPC_IPC127E = 0x00000D01,
SIMATIC_IPC_IPC227G = 0x00000F01,
SIMATIC_IPC_IPC277G = 0x00000F02,
SIMATIC_IPC_IPCBX_39A = 0x00001001,
SIMATIC_IPC_IPCPX_39A = 0x00001002,
SIMATIC_IPC_IPCBX_21A = 0x00001101,
SIMATIC_IPC_IPCBX_56A = 0x00001201,
SIMATIC_IPC_IPCBX_59A = 0x00001202,
};
static inline u32 simatic_ipc_get_station_id(u8 *data, int max_len)
{
struct {
u8 type; /* type (0xff = binary) */
u8 len; /* len of data entry */
u8 group;
u8 entry;
u8 tid;
__le32 station_id; /* station id (LE) */
} __packed * data_entry = (void *)data + sizeof(struct dmi_header);
while ((u8 *)data_entry < data + max_len) {
if (data_entry->type == SIMATIC_IPC_DMI_TYPE &&
data_entry->len == sizeof(*data_entry) &&
data_entry->group == SIMATIC_IPC_DMI_GROUP &&
data_entry->entry == SIMATIC_IPC_DMI_ENTRY &&
data_entry->tid == SIMATIC_IPC_DMI_TID) {
return le32_to_cpu(data_entry->station_id);
}
data_entry = (void *)((u8 *)(data_entry) + data_entry->len);
}
return SIMATIC_IPC_INVALID_STATION_ID;
}
static inline void
simatic_ipc_find_dmi_entry_helper(const struct dmi_header *dh, void *_data)
{
u32 *id = _data;
if (dh->type != SIMATIC_IPC_DMI_ENTRY_OEM)
return;
*id = simatic_ipc_get_station_id((u8 *)dh, dh->length);
}
#endif /* __PLATFORM_DATA_X86_SIMATIC_IPC_H */
linux-7.2.3/include/linux/platform_data/x86/soc.h
+70
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Helpers for Intel SoC model detection
*
* Copyright (c) 2019, Intel Corporation.
*/
#ifndef __PLATFORM_DATA_X86_SOC_H
#define __PLATFORM_DATA_X86_SOC_H
#include <linux/types.h>
#if IS_ENABLED(CONFIG_X86)
#include <linux/device-id/x86_cpu.h>
#include <asm/cpu_device_id.h>
#define SOC_INTEL_IS_CPU(soc, type) \
static inline bool soc_intel_is_##soc(void) \
{ \
static const struct x86_cpu_id soc##_cpu_ids[] = { \
X86_MATCH_VFM(type, NULL), \
{} \
}; \
const struct x86_cpu_id *id; \
\
id = x86_match_cpu(soc##_cpu_ids); \
if (id) \
return true; \
return false; \
}
SOC_INTEL_IS_CPU(byt, INTEL_ATOM_SILVERMONT);
SOC_INTEL_IS_CPU(cht, INTEL_ATOM_AIRMONT);
SOC_INTEL_IS_CPU(apl, INTEL_ATOM_GOLDMONT);
SOC_INTEL_IS_CPU(glk, INTEL_ATOM_GOLDMONT_PLUS);
SOC_INTEL_IS_CPU(cml, INTEL_KABYLAKE_L);
#undef SOC_INTEL_IS_CPU
#else /* IS_ENABLED(CONFIG_X86) */
static inline bool soc_intel_is_byt(void)
{
return false;
}
static inline bool soc_intel_is_cht(void)
{
return false;
}
static inline bool soc_intel_is_apl(void)
{
return false;
}
static inline bool soc_intel_is_glk(void)
{
return false;
}
static inline bool soc_intel_is_cml(void)
{
return false;
}
#endif /* IS_ENABLED(CONFIG_X86) */
#endif /* __PLATFORM_DATA_X86_SOC_H */
linux-7.2.3/include/linux/platform_data/x86/spi-intel.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Intel PCH/PCU SPI flash driver.
*
* Copyright (C) 2016, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#ifndef SPI_INTEL_PDATA_H
#define SPI_INTEL_PDATA_H
enum intel_spi_type {
INTEL_SPI_BYT = 1,
INTEL_SPI_LPT,
INTEL_SPI_BXT,
INTEL_SPI_CNL,
};
/**
* struct intel_spi_boardinfo - Board specific data for Intel SPI driver
* @type: Type which this controller is compatible with
* @set_writeable: Try to make the chip writeable (optional)
* @data: Data to be passed to @set_writeable can be %NULL
*/
struct intel_spi_boardinfo {
enum intel_spi_type type;
bool (*set_writeable)(void __iomem *base, void *data);
void *data;
};
#endif /* SPI_INTEL_PDATA_H */