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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/include/linux/soc/ti/k3-ringacc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* K3 Ring Accelerator (RA) subsystem interface
*
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __SOC_TI_K3_RINGACC_API_H_
#define __SOC_TI_K3_RINGACC_API_H_
#include <linux/types.h>
struct device_node;
/**
* enum k3_ring_mode - &struct k3_ring_cfg mode
*
* RA ring operational modes
*
* @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
* @K3_RINGACC_RING_MODE_MESSAGE: Messaging mode. Messaging mode requires
* that all accesses to the queue must go through this IP so that all
* accesses to the memory are controlled and ordered. This IP then
* controls the entire state of the queue, and SW has no directly control,
* such as through doorbells and cannot access the storage memory directly.
* This is particularly useful when more than one SW or HW entity can be
* the producer and/or consumer at the same time
* @K3_RINGACC_RING_MODE_CREDENTIALS: Credentials mode is message mode plus
* stores credentials with each message, requiring the element size to be
* doubled to fit the credentials. Any exposed memory should be protected
* by a firewall from unwanted access
*/
enum k3_ring_mode {
K3_RINGACC_RING_MODE_RING = 0,
K3_RINGACC_RING_MODE_MESSAGE,
K3_RINGACC_RING_MODE_CREDENTIALS,
K3_RINGACC_RING_MODE_INVALID
};
/**
* enum k3_ring_size - &struct k3_ring_cfg elm_size
*
* RA ring element's sizes in bytes.
*/
enum k3_ring_size {
K3_RINGACC_RING_ELSIZE_4 = 0,
K3_RINGACC_RING_ELSIZE_8,
K3_RINGACC_RING_ELSIZE_16,
K3_RINGACC_RING_ELSIZE_32,
K3_RINGACC_RING_ELSIZE_64,
K3_RINGACC_RING_ELSIZE_128,
K3_RINGACC_RING_ELSIZE_256,
K3_RINGACC_RING_ELSIZE_INVALID
};
struct k3_ringacc;
struct k3_ring;
/**
* enum k3_ring_cfg - RA ring configuration structure
*
* @size: Ring size, number of elements
* @elm_size: Ring element size
* @mode: Ring operational mode
* @flags: Ring configuration flags. Possible values:
* @K3_RINGACC_RING_SHARED: when set allows to request the same ring
* few times. It's usable when the same ring is used as Free Host PD ring
* for different flows, for example.
* Note: Locking should be done by consumer if required
* @dma_dev: Master device which is using and accessing to the ring
* memory when the mode is K3_RINGACC_RING_MODE_RING. Memory allocations
* should be done using this device.
* @asel: Address Space Select value for physical addresses
*/
struct k3_ring_cfg {
u32 size;
enum k3_ring_size elm_size;
enum k3_ring_mode mode;
#define K3_RINGACC_RING_SHARED BIT(1)
u32 flags;
struct device *dma_dev;
u32 asel;
};
#define K3_RINGACC_RING_ID_ANY (-1)
/**
* of_k3_ringacc_get_by_phandle - find a RA by phandle property
* @np: device node
* @propname: property name containing phandle on RA node
*
* Returns pointer on the RA - struct k3_ringacc
* or -ENODEV if not found,
* or -EPROBE_DEFER if not yet registered
*/
struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np,
const char *property);
#define K3_RINGACC_RING_USE_PROXY BIT(1)
/**
* k3_ringacc_request_ring - request ring from ringacc
* @ringacc: pointer on ringacc
* @id: ring id or K3_RINGACC_RING_ID_ANY for any general purpose ring
* @flags:
* @K3_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
* used to access ring memory. Sopported only for rings in
* Message/Credentials/Queue mode.
*
* Returns pointer on the Ring - struct k3_ring
* or NULL in case of failure.
*/
struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc,
int id, u32 flags);
int k3_ringacc_request_rings_pair(struct k3_ringacc *ringacc,
int fwd_id, int compl_id,
struct k3_ring **fwd_ring,
struct k3_ring **compl_ring);
/**
* k3_ringacc_ring_reset - ring reset
* @ring: pointer on Ring
*
* Resets ring internal state ((hw)occ, (hw)idx).
*/
void k3_ringacc_ring_reset(struct k3_ring *ring);
/**
* k3_ringacc_ring_reset - ring reset for DMA rings
* @ring: pointer on Ring
*
* Resets ring internal state ((hw)occ, (hw)idx). Should be used for rings
* which are read by K3 UDMA, like TX or Free Host PD rings.
*/
void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ);
/**
* k3_ringacc_ring_free - ring free
* @ring: pointer on Ring
*
* Resets ring and free all alocated resources.
*/
int k3_ringacc_ring_free(struct k3_ring *ring);
/**
* k3_ringacc_get_ring_id - Get the Ring ID
* @ring: pointer on ring
*
* Returns the Ring ID
*/
u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
/**
* k3_ringacc_get_ring_irq_num - Get the irq number for the ring
* @ring: pointer on ring
*
* Returns the interrupt number which can be used to request the interrupt
*/
int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
/**
* k3_ringacc_ring_cfg - ring configure
* @ring: pointer on ring
* @cfg: Ring configuration parameters (see &struct k3_ring_cfg)
*
* Configures ring, including ring memory allocation.
* Returns 0 on success, errno otherwise.
*/
int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg);
/**
* k3_ringacc_ring_get_size - get ring size
* @ring: pointer on ring
*
* Returns ring size in number of elements.
*/
u32 k3_ringacc_ring_get_size(struct k3_ring *ring);
/**
* k3_ringacc_ring_get_free - get free elements
* @ring: pointer on ring
*
* Returns number of free elements in the ring.
*/
u32 k3_ringacc_ring_get_free(struct k3_ring *ring);
/**
* k3_ringacc_ring_get_occ - get ring occupancy
* @ring: pointer on ring
*
* Returns total number of valid entries on the ring
*/
u32 k3_ringacc_ring_get_occ(struct k3_ring *ring);
/**
* k3_ringacc_ring_is_full - checks if ring is full
* @ring: pointer on ring
*
* Returns true if the ring is full
*/
u32 k3_ringacc_ring_is_full(struct k3_ring *ring);
/**
* k3_ringacc_ring_push - push element to the ring tail
* @ring: pointer on ring
* @elem: pointer on ring element buffer
*
* Push one ring element to the ring tail. Size of the ring element is
* determined by ring configuration &struct k3_ring_cfg elm_size.
*
* Returns 0 on success, errno otherwise.
*/
int k3_ringacc_ring_push(struct k3_ring *ring, void *elem);
/**
* k3_ringacc_ring_pop - pop element from the ring head
* @ring: pointer on ring
* @elem: pointer on ring element buffer
*
* Push one ring element from the ring head. Size of the ring element is
* determined by ring configuration &struct k3_ring_cfg elm_size..
*
* Returns 0 on success, errno otherwise.
*/
int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem);
/**
* k3_ringacc_ring_push_head - push element to the ring head
* @ring: pointer on ring
* @elem: pointer on ring element buffer
*
* Push one ring element to the ring head. Size of the ring element is
* determined by ring configuration &struct k3_ring_cfg elm_size.
*
* Returns 0 on success, errno otherwise.
* Not Supported by ring modes: K3_RINGACC_RING_MODE_RING
*/
int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem);
/**
* k3_ringacc_ring_pop_tail - pop element from the ring tail
* @ring: pointer on ring
* @elem: pointer on ring element buffer
*
* Push one ring element from the ring tail. Size of the ring element is
* determined by ring configuration &struct k3_ring_cfg elm_size.
*
* Returns 0 on success, errno otherwise.
* Not Supported by ring modes: K3_RINGACC_RING_MODE_RING
*/
int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem);
u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring);
/* DMA ring support */
struct ti_sci_handle;
/**
* struct struct k3_ringacc_init_data - Initialization data for DMA rings
*/
struct k3_ringacc_init_data {
const struct ti_sci_handle *tisci;
u32 tisci_dev_id;
u32 num_rings;
};
struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
struct k3_ringacc_init_data *data);
#endif /* __SOC_TI_K3_RINGACC_API_H_ */
linux-7.2.3/include/linux/soc/ti/knav_dma.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 Texas Instruments Incorporated
* Authors: Sandeep Nair <sandeep_n@ti.com
* Cyril Chemparathy <cyril@ti.com
Santosh Shilimkar <santosh.shilimkar@ti.com>
*/
#ifndef __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__
#define __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__
#include <linux/dmaengine.h>
/*
* PKTDMA descriptor manipulation macros for host packet descriptor
*/
#define MASK(x) (BIT(x) - 1)
#define KNAV_DMA_DESC_PKT_LEN_MASK MASK(22)
#define KNAV_DMA_DESC_PKT_LEN_SHIFT 0
#define KNAV_DMA_DESC_PS_INFO_IN_SOP BIT(22)
#define KNAV_DMA_DESC_PS_INFO_IN_DESC 0
#define KNAV_DMA_DESC_TAG_MASK MASK(8)
#define KNAV_DMA_DESC_SAG_HI_SHIFT 24
#define KNAV_DMA_DESC_STAG_LO_SHIFT 16
#define KNAV_DMA_DESC_DTAG_HI_SHIFT 8
#define KNAV_DMA_DESC_DTAG_LO_SHIFT 0
#define KNAV_DMA_DESC_HAS_EPIB BIT(31)
#define KNAV_DMA_DESC_NO_EPIB 0
#define KNAV_DMA_DESC_PSLEN_SHIFT 24
#define KNAV_DMA_DESC_PSLEN_MASK MASK(6)
#define KNAV_DMA_DESC_ERR_FLAG_SHIFT 20
#define KNAV_DMA_DESC_ERR_FLAG_MASK MASK(4)
#define KNAV_DMA_DESC_PSFLAG_SHIFT 16
#define KNAV_DMA_DESC_PSFLAG_MASK MASK(4)
#define KNAV_DMA_DESC_RETQ_SHIFT 0
#define KNAV_DMA_DESC_RETQ_MASK MASK(14)
#define KNAV_DMA_DESC_BUF_LEN_MASK MASK(22)
#define KNAV_DMA_DESC_EFLAGS_MASK MASK(4)
#define KNAV_DMA_DESC_EFLAGS_SHIFT 20
#define KNAV_DMA_NUM_EPIB_WORDS 4
#define KNAV_DMA_NUM_PS_WORDS 16
#define KNAV_DMA_NUM_SW_DATA_WORDS 4
#define KNAV_DMA_FDQ_PER_CHAN 4
/* Tx channel scheduling priority */
enum knav_dma_tx_priority {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MED_H,
DMA_PRIO_MED_L,
DMA_PRIO_LOW
};
/* Rx channel error handling mode during buffer starvation */
enum knav_dma_rx_err_mode {
DMA_DROP = 0,
DMA_RETRY
};
/* Rx flow size threshold configuration */
enum knav_dma_rx_thresholds {
DMA_THRESH_NONE = 0,
DMA_THRESH_0 = 1,
DMA_THRESH_0_1 = 3,
DMA_THRESH_0_1_2 = 7
};
/* Descriptor type */
enum knav_dma_desc_type {
DMA_DESC_HOST = 0,
DMA_DESC_MONOLITHIC = 2
};
/**
* struct knav_dma_tx_cfg: Tx channel configuration
* @filt_einfo: Filter extended packet info
* @filt_pswords: Filter PS words present
* @priority: Tx channel scheduling priority
*/
struct knav_dma_tx_cfg {
bool filt_einfo;
bool filt_pswords;
enum knav_dma_tx_priority priority;
};
/**
* struct knav_dma_rx_cfg: Rx flow configuration
* @einfo_present: Extended packet info present
* @psinfo_present: PS words present
* @err_mode: Error during buffer starvation
* @desc_type: Host or Monolithic desc
* @psinfo_at_sop: PS word located at start of packet
* @sop_offset: Start of packet offset
* @dst_q: Destination queue for a given flow
* @thresh: Rx flow size threshold
* @fdq: Free desc Queue array
* @sz_thresh0: RX packet size threshold 0
* @sz_thresh1: RX packet size threshold 1
* @sz_thresh2: RX packet size threshold 2
*/
struct knav_dma_rx_cfg {
bool einfo_present;
bool psinfo_present;
enum knav_dma_rx_err_mode err_mode;
enum knav_dma_desc_type desc_type;
bool psinfo_at_sop;
unsigned int sop_offset;
unsigned int dst_q;
enum knav_dma_rx_thresholds thresh;
unsigned int fdq[KNAV_DMA_FDQ_PER_CHAN];
unsigned int sz_thresh0;
unsigned int sz_thresh1;
unsigned int sz_thresh2;
};
/**
* struct knav_dma_cfg: Pktdma channel configuration
* @direction: DMA transfer mode and direction
* @u: union containing @tx or @rx
* @tx: Tx channel configuration
* @rx: Rx flow configuration
*/
struct knav_dma_cfg {
enum dma_transfer_direction direction;
union {
struct knav_dma_tx_cfg tx;
struct knav_dma_rx_cfg rx;
} u;
};
/**
* struct knav_dma_desc: Host packet descriptor layout
* @desc_info: Descriptor information like id, type, length
* @tag_info: Flow tag info written in during RX
* @packet_info: Queue Manager, policy, flags etc
* @buff_len: Buffer length in bytes
* @buff: Buffer pointer
* @next_desc: For chaining the descriptors
* @orig_len: length since 'buff_len' can be overwritten
* @orig_buff: buff pointer since 'buff' can be overwritten
* @epib: Extended packet info block
* @psdata: Protocol specific
* @sw_data: Software private data not touched by h/w
*/
struct knav_dma_desc {
__le32 desc_info;
__le32 tag_info;
__le32 packet_info;
__le32 buff_len;
__le32 buff;
__le32 next_desc;
__le32 orig_len;
__le32 orig_buff;
__le32 epib[KNAV_DMA_NUM_EPIB_WORDS];
__le32 psdata[KNAV_DMA_NUM_PS_WORDS];
u32 sw_data[KNAV_DMA_NUM_SW_DATA_WORDS];
} ____cacheline_aligned;
#if IS_ENABLED(CONFIG_KEYSTONE_NAVIGATOR_DMA)
void *knav_dma_open_channel(struct device *dev, const char *name,
struct knav_dma_cfg *config);
void knav_dma_close_channel(void *channel);
int knav_dma_get_flow(void *channel);
bool knav_dma_device_ready(void);
#else
static inline void *knav_dma_open_channel(struct device *dev, const char *name,
struct knav_dma_cfg *config)
{
return (void *) NULL;
}
static inline void knav_dma_close_channel(void *channel)
{}
static inline int knav_dma_get_flow(void *channel)
{
return -EINVAL;
}
static inline bool knav_dma_device_ready(void)
{
return false;
}
#endif
#endif /* __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__ */
linux-7.2.3/include/linux/soc/ti/knav_qmss.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Keystone Navigator Queue Management Sub-System header
*
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
* Author: Sandeep Nair <sandeep_n@ti.com>
* Cyril Chemparathy <cyril@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com>
*/
#ifndef __SOC_TI_KNAV_QMSS_H__
#define __SOC_TI_KNAV_QMSS_H__
#include <linux/err.h>
#include <linux/time.h>
#include <linux/atomic.h>
#include <linux/device.h>
#include <linux/fcntl.h>
#include <linux/dma-mapping.h>
/* queue types */
#define KNAV_QUEUE_QPEND ((unsigned)-2) /* interruptible qpend queue */
#define KNAV_QUEUE_ACC ((unsigned)-3) /* Accumulated queue */
#define KNAV_QUEUE_GP ((unsigned)-4) /* General purpose queue */
/* queue flags */
#define KNAV_QUEUE_SHARED 0x0001 /* Queue can be shared */
/**
* enum knav_queue_ctrl_cmd - queue operations.
* @KNAV_QUEUE_GET_ID: Get the ID number for an open queue
* @KNAV_QUEUE_FLUSH: forcibly empty a queue if possible
* @KNAV_QUEUE_SET_NOTIFIER: Set a notifier callback to a queue handle.
* @KNAV_QUEUE_ENABLE_NOTIFY: Enable notifier callback for a queue handle.
* @KNAV_QUEUE_DISABLE_NOTIFY: Disable notifier callback for a queue handle.
* @KNAV_QUEUE_GET_COUNT: Get number of queues.
*/
enum knav_queue_ctrl_cmd {
KNAV_QUEUE_GET_ID,
KNAV_QUEUE_FLUSH,
KNAV_QUEUE_SET_NOTIFIER,
KNAV_QUEUE_ENABLE_NOTIFY,
KNAV_QUEUE_DISABLE_NOTIFY,
KNAV_QUEUE_GET_COUNT
};
/* Queue notifier callback prototype */
typedef void (*knav_queue_notify_fn)(void *arg);
/**
* struct knav_queue_notify_config: Notifier configuration
* @fn: Notifier function
* @fn_arg: Notifier function arguments
*/
struct knav_queue_notify_config {
knav_queue_notify_fn fn;
void *fn_arg;
};
void *knav_queue_open(const char *name, unsigned id,
unsigned flags);
void knav_queue_close(void *qhandle);
int knav_queue_device_control(void *qhandle,
enum knav_queue_ctrl_cmd cmd,
unsigned long arg);
dma_addr_t knav_queue_pop(void *qhandle, unsigned *size);
int knav_queue_push(void *qhandle, dma_addr_t dma,
unsigned size, unsigned flags);
void *knav_pool_create(const char *name,
int num_desc, int region_id);
void knav_pool_destroy(void *ph);
int knav_pool_count(void *ph);
void *knav_pool_desc_get(void *ph);
void knav_pool_desc_put(void *ph, void *desc);
int knav_pool_desc_map(void *ph, void *desc, unsigned size,
dma_addr_t *dma, unsigned *dma_sz);
void *knav_pool_desc_unmap(void *ph, dma_addr_t dma, unsigned dma_sz);
dma_addr_t knav_pool_desc_virt_to_dma(void *ph, void *virt);
void *knav_pool_desc_dma_to_virt(void *ph, dma_addr_t dma);
bool knav_qmss_device_ready(void);
#endif /* __SOC_TI_KNAV_QMSS_H__ */
linux-7.2.3/include/linux/soc/ti/omap1-io.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ASM_ARCH_OMAP_IO_H
#define __ASM_ARCH_OMAP_IO_H
#ifndef __ASSEMBLER__
#include <linux/types.h>
#ifdef CONFIG_ARCH_OMAP1
/*
* NOTE: Please use ioremap + __raw_read/write where possible instead of these
*/
extern u8 omap_readb(u32 pa);
extern u16 omap_readw(u32 pa);
extern u32 omap_readl(u32 pa);
extern void omap_writeb(u8 v, u32 pa);
extern void omap_writew(u16 v, u32 pa);
extern void omap_writel(u32 v, u32 pa);
#elif defined(CONFIG_COMPILE_TEST)
static inline u8 omap_readb(u32 pa) { return 0; }
static inline u16 omap_readw(u32 pa) { return 0; }
static inline u32 omap_readl(u32 pa) { return 0; }
static inline void omap_writeb(u8 v, u32 pa) { }
static inline void omap_writew(u16 v, u32 pa) { }
static inline void omap_writel(u32 v, u32 pa) { }
#endif
#endif
/*
* ----------------------------------------------------------------------------
* System control registers
* ----------------------------------------------------------------------------
*/
#define MOD_CONF_CTRL_0 0xfffe1080
#define MOD_CONF_CTRL_1 0xfffe1110
/*
* ---------------------------------------------------------------------------
* UPLD
* ---------------------------------------------------------------------------
*/
#define ULPD_REG_BASE (0xfffe0800)
#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
# define SOFT_UDC_REQ (1 << 4)
# define SOFT_USB_CLK_REQ (1 << 3)
# define SOFT_DPLL_REQ (1 << 0)
#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
# define DIS_MMC2_DPLL_REQ (1 << 11)
# define DIS_MMC1_DPLL_REQ (1 << 10)
# define DIS_UART3_DPLL_REQ (1 << 9)
# define DIS_UART2_DPLL_REQ (1 << 8)
# define DIS_UART1_DPLL_REQ (1 << 7)
# define DIS_USB_HOST_DPLL_REQ (1 << 6)
#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
/*
* ----------------------------------------------------------------------------
* Clocks
* ----------------------------------------------------------------------------
*/
#define CLKGEN_REG_BASE (0xfffece00)
#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
#define CK_RATEF 1
#define CK_IDLEF 2
#define CK_ENABLEF 4
#define CK_SELECTF 8
#define SETARM_IDLE_SHIFT
/* DPLL control registers */
#define DPLL_CTL (0xfffecf00)
/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
/*
* ----------------------------------------------------------------------------
* Pulse-Width Light
* ----------------------------------------------------------------------------
*/
#define OMAP_PWL_BASE 0xfffb5800
#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
/*
* ----------------------------------------------------------------------------
* Pin multiplexing registers
* ----------------------------------------------------------------------------
*/
#define FUNC_MUX_CTRL_0 0xfffe1000
#define FUNC_MUX_CTRL_1 0xfffe1004
#define FUNC_MUX_CTRL_2 0xfffe1008
#define COMP_MODE_CTRL_0 0xfffe100c
#define FUNC_MUX_CTRL_3 0xfffe1010
#define FUNC_MUX_CTRL_4 0xfffe1014
#define FUNC_MUX_CTRL_5 0xfffe1018
#define FUNC_MUX_CTRL_6 0xfffe101C
#define FUNC_MUX_CTRL_7 0xfffe1020
#define FUNC_MUX_CTRL_8 0xfffe1024
#define FUNC_MUX_CTRL_9 0xfffe1028
#define FUNC_MUX_CTRL_A 0xfffe102C
#define FUNC_MUX_CTRL_B 0xfffe1030
#define FUNC_MUX_CTRL_C 0xfffe1034
#define FUNC_MUX_CTRL_D 0xfffe1038
#define PULL_DWN_CTRL_0 0xfffe1040
#define PULL_DWN_CTRL_1 0xfffe1044
#define PULL_DWN_CTRL_2 0xfffe1048
#define PULL_DWN_CTRL_3 0xfffe104c
#define PULL_DWN_CTRL_4 0xfffe10ac
/* OMAP-1610 specific multiplexing registers */
#define FUNC_MUX_CTRL_E 0xfffe1090
#define FUNC_MUX_CTRL_F 0xfffe1094
#define FUNC_MUX_CTRL_10 0xfffe1098
#define FUNC_MUX_CTRL_11 0xfffe109c
#define FUNC_MUX_CTRL_12 0xfffe10a0
#define PU_PD_SEL_0 0xfffe10b4
#define PU_PD_SEL_1 0xfffe10b8
#define PU_PD_SEL_2 0xfffe10bc
#define PU_PD_SEL_3 0xfffe10c0
#define PU_PD_SEL_4 0xfffe10c4
#endif
linux-7.2.3/include/linux/soc/ti/omap1-mux.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOC_TI_OMAP1_MUX_H
#define __SOC_TI_OMAP1_MUX_H
/*
* This should not really be a global header, it reflects the
* traditional way that omap1 does pin muxing without the
* pinctrl subsystem.
*/
enum omap7xx_index {
/* OMAP 730 keyboard */
E2_7XX_KBR0,
J7_7XX_KBR1,
E1_7XX_KBR2,
F3_7XX_KBR3,
D2_7XX_KBR4,
C2_7XX_KBC0,
D3_7XX_KBC1,
E4_7XX_KBC2,
F4_7XX_KBC3,
E3_7XX_KBC4,
/* USB */
AA17_7XX_USB_DM,
W16_7XX_USB_PU_EN,
W17_7XX_USB_VBUSI,
W18_7XX_USB_DMCK_OUT,
W19_7XX_USB_DCRST,
/* MMC */
MMC_7XX_CMD,
MMC_7XX_CLK,
MMC_7XX_DAT0,
/* I2C */
I2C_7XX_SCL,
I2C_7XX_SDA,
/* SPI */
SPI_7XX_1,
SPI_7XX_2,
SPI_7XX_3,
SPI_7XX_4,
SPI_7XX_5,
SPI_7XX_6,
/* UART */
UART_7XX_1,
UART_7XX_2,
};
enum omap1xxx_index {
/* UART1 (BT_UART_GATING)*/
UART1_TX = 0,
UART1_RTS,
/* UART2 (COM_UART_GATING)*/
UART2_TX,
UART2_RX,
UART2_CTS,
UART2_RTS,
/* UART3 (GIGA_UART_GATING) */
UART3_TX,
UART3_RX,
UART3_CTS,
UART3_RTS,
UART3_CLKREQ,
UART3_BCLK, /* 12MHz clock out */
Y15_1610_UART3_RTS,
/* PWT & PWL */
PWT,
PWL,
/* USB master generic */
R18_USB_VBUS,
R18_1510_USB_GPIO0,
W4_USB_PUEN,
W4_USB_CLKO,
W4_USB_HIGHZ,
W4_GPIO58,
/* USB1 master */
USB1_SUSP,
USB1_SEO,
W13_1610_USB1_SE0,
USB1_TXEN,
USB1_TXD,
USB1_VP,
USB1_VM,
USB1_RCV,
USB1_SPEED,
R13_1610_USB1_SPEED,
R13_1710_USB1_SE0,
/* USB2 master */
USB2_SUSP,
USB2_VP,
USB2_TXEN,
USB2_VM,
USB2_RCV,
USB2_SEO,
USB2_TXD,
/* OMAP-1510 GPIO */
R18_1510_GPIO0,
R19_1510_GPIO1,
M14_1510_GPIO2,
/* OMAP1610 GPIO */
P18_1610_GPIO3,
Y15_1610_GPIO17,
/* OMAP-1710 GPIO */
R18_1710_GPIO0,
V2_1710_GPIO10,
N21_1710_GPIO14,
W15_1710_GPIO40,
/* MPUIO */
MPUIO2,
N15_1610_MPUIO2,
MPUIO4,
MPUIO5,
T20_1610_MPUIO5,
W11_1610_MPUIO6,
V10_1610_MPUIO7,
W11_1610_MPUIO9,
V10_1610_MPUIO10,
W10_1610_MPUIO11,
E20_1610_MPUIO13,
U20_1610_MPUIO14,
E19_1610_MPUIO15,
/* MCBSP2 */
MCBSP2_CLKR,
MCBSP2_CLKX,
MCBSP2_DR,
MCBSP2_DX,
MCBSP2_FSR,
MCBSP2_FSX,
/* MCBSP3 */
MCBSP3_CLKX,
/* Misc ballouts */
BALLOUT_V8_ARMIO3,
N20_HDQ,
/* OMAP-1610 MMC2 */
W8_1610_MMC2_DAT0,
V8_1610_MMC2_DAT1,
W15_1610_MMC2_DAT2,
R10_1610_MMC2_DAT3,
Y10_1610_MMC2_CLK,
Y8_1610_MMC2_CMD,
V9_1610_MMC2_CMDDIR,
V5_1610_MMC2_DATDIR0,
W19_1610_MMC2_DATDIR1,
R18_1610_MMC2_CLKIN,
/* OMAP-1610 External Trace Interface */
M19_1610_ETM_PSTAT0,
L15_1610_ETM_PSTAT1,
L18_1610_ETM_PSTAT2,
L19_1610_ETM_D0,
J19_1610_ETM_D6,
J18_1610_ETM_D7,
/* OMAP16XX GPIO */
P20_1610_GPIO4,
V9_1610_GPIO7,
W8_1610_GPIO9,
N20_1610_GPIO11,
N19_1610_GPIO13,
P10_1610_GPIO22,
V5_1610_GPIO24,
AA20_1610_GPIO_41,
W19_1610_GPIO48,
M7_1610_GPIO62,
V14_16XX_GPIO37,
R9_16XX_GPIO18,
L14_16XX_GPIO49,
/* OMAP-1610 uWire */
V19_1610_UWIRE_SCLK,
U18_1610_UWIRE_SDI,
W21_1610_UWIRE_SDO,
N14_1610_UWIRE_CS0,
P15_1610_UWIRE_CS3,
N15_1610_UWIRE_CS1,
/* OMAP-1610 SPI */
U19_1610_SPIF_SCK,
U18_1610_SPIF_DIN,
P20_1610_SPIF_DIN,
W21_1610_SPIF_DOUT,
R18_1610_SPIF_DOUT,
N14_1610_SPIF_CS0,
N15_1610_SPIF_CS1,
T19_1610_SPIF_CS2,
P15_1610_SPIF_CS3,
/* OMAP-1610 Flash */
L3_1610_FLASH_CS2B_OE,
M8_1610_FLASH_CS2B_WE,
/* First MMC */
MMC_CMD,
MMC_DAT1,
MMC_DAT2,
MMC_DAT0,
MMC_CLK,
MMC_DAT3,
/* OMAP-1710 MMC CMDDIR and DATDIR0 */
M15_1710_MMC_CLKI,
P19_1710_MMC_CMDDIR,
P20_1710_MMC_DATDIR0,
/* OMAP-1610 USB0 alternate pin configuration */
W9_USB0_TXEN,
AA9_USB0_VP,
Y5_USB0_RCV,
R9_USB0_VM,
V6_USB0_TXD,
W5_USB0_SE0,
V9_USB0_SPEED,
V9_USB0_SUSP,
/* USB2 */
W9_USB2_TXEN,
AA9_USB2_VP,
Y5_USB2_RCV,
R9_USB2_VM,
V6_USB2_TXD,
W5_USB2_SE0,
/* 16XX UART */
R13_1610_UART1_TX,
V14_16XX_UART1_RX,
R14_1610_UART1_CTS,
AA15_1610_UART1_RTS,
R9_16XX_UART2_RX,
L14_16XX_UART3_RX,
/* I2C OMAP-1610 */
I2C_SCL,
I2C_SDA,
/* Keypad */
F18_1610_KBC0,
D20_1610_KBC1,
D19_1610_KBC2,
E18_1610_KBC3,
C21_1610_KBC4,
G18_1610_KBR0,
F19_1610_KBR1,
H14_1610_KBR2,
E20_1610_KBR3,
E19_1610_KBR4,
N19_1610_KBR5,
/* Power management */
T20_1610_LOW_PWR,
/* MCLK Settings */
V5_1710_MCLK_ON,
V5_1710_MCLK_OFF,
R10_1610_MCLK_ON,
R10_1610_MCLK_OFF,
/* CompactFlash controller */
P11_1610_CF_CD2,
R11_1610_CF_IOIS16,
V10_1610_CF_IREQ,
W10_1610_CF_RESET,
W11_1610_CF_CD1,
/* parallel camera */
J15_1610_CAM_LCLK,
J18_1610_CAM_D7,
J19_1610_CAM_D6,
J14_1610_CAM_D5,
K18_1610_CAM_D4,
K19_1610_CAM_D3,
K15_1610_CAM_D2,
K14_1610_CAM_D1,
L19_1610_CAM_D0,
L18_1610_CAM_VS,
L15_1610_CAM_HS,
M19_1610_CAM_RSTZ,
Y15_1610_CAM_OUTCLK,
/* serial camera */
H19_1610_CAM_EXCLK,
Y12_1610_CCP_CLKP,
W13_1610_CCP_CLKM,
W14_1610_CCP_DATAP,
Y14_1610_CCP_DATAM,
};
#ifdef CONFIG_OMAP_MUX
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif
#endif
linux-7.2.3/include/linux/soc/ti/omap1-soc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* OMAP cpu type detection
*
* Copyright (C) 2004, 2008 Nokia Corporation
*
* Copyright (C) 2009-11 Texas Instruments.
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
*/
#ifndef __ASM_ARCH_OMAP_CPU_H
#define __ASM_ARCH_OMAP_CPU_H
/*
* Test if multicore OMAP support is needed
*/
#undef MULTI_OMAP1
#undef OMAP_NAME
#ifdef CONFIG_ARCH_OMAP15XX
# ifdef OMAP_NAME
# undef MULTI_OMAP1
# define MULTI_OMAP1
# else
# define OMAP_NAME omap1510
# endif
#endif
#ifdef CONFIG_ARCH_OMAP16XX
# ifdef OMAP_NAME
# undef MULTI_OMAP1
# define MULTI_OMAP1
# else
# define OMAP_NAME omap16xx
# endif
#endif
/*
* omap_rev bits:
* CPU id bits (0730, 1510, 1710, 2422...) [31:16]
* CPU revision (See _REV_ defined in cpu.h) [15:08]
* CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
*/
unsigned int omap_rev(void);
/*
* Get the CPU revision for OMAP devices
*/
#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
/*
* Macros to group OMAP into cpu classes.
* These can be used in most places.
* cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
* cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
#define IS_OMAP_CLASS(class, id) \
static inline int is_omap ##class (void) \
{ \
return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
}
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
static inline int is_omap ##subclass (void) \
{ \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
IS_OMAP_CLASS(15xx, 0x15)
IS_OMAP_CLASS(16xx, 0x16)
#define cpu_is_omap15xx() 0
#define cpu_is_omap16xx() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP15XX)
# undef cpu_is_omap15xx
# define cpu_is_omap15xx() is_omap15xx()
# endif
# if defined(CONFIG_ARCH_OMAP16XX)
# undef cpu_is_omap16xx
# define cpu_is_omap16xx() is_omap16xx()
# endif
#else
# if defined(CONFIG_ARCH_OMAP15XX)
# undef cpu_is_omap15xx
# define cpu_is_omap15xx() 1
# endif
# if defined(CONFIG_ARCH_OMAP16XX)
# undef cpu_is_omap16xx
# define cpu_is_omap16xx() 1
# endif
#endif
/*
* Macros to detect individual cpu types.
* These are only rarely needed.
* cpu_is_omap310(): True for OMAP310
* cpu_is_omap1510(): True for OMAP1510
* cpu_is_omap1610(): True for OMAP1610
* cpu_is_omap1611(): True for OMAP1611
* cpu_is_omap5912(): True for OMAP5912
* cpu_is_omap1621(): True for OMAP1621
* cpu_is_omap1710(): True for OMAP1710
*/
#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
#define IS_OMAP_TYPE(type, id) \
static inline int is_omap ##type (void) \
{ \
return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
}
IS_OMAP_TYPE(310, 0x0310)
IS_OMAP_TYPE(1510, 0x1510)
IS_OMAP_TYPE(1610, 0x1610)
IS_OMAP_TYPE(1611, 0x1611)
IS_OMAP_TYPE(5912, 0x1611)
IS_OMAP_TYPE(1621, 0x1621)
IS_OMAP_TYPE(1710, 0x1710)
#define cpu_is_omap310() 0
#define cpu_is_omap1510() 0
#define cpu_is_omap1610() 0
#define cpu_is_omap5912() 0
#define cpu_is_omap1611() 0
#define cpu_is_omap1621() 0
#define cpu_is_omap1710() 0
#define cpu_class_is_omap1() 1
/*
* Whether we have MULTI_OMAP1 or not, we still need to distinguish
* between 310 vs. 1510 and 1611B/5912 vs. 1710.
*/
#if defined(CONFIG_ARCH_OMAP15XX)
# undef cpu_is_omap310
# undef cpu_is_omap1510
# define cpu_is_omap310() is_omap310()
# define cpu_is_omap1510() is_omap1510()
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
# undef cpu_is_omap1610
# undef cpu_is_omap1611
# undef cpu_is_omap5912
# undef cpu_is_omap1621
# undef cpu_is_omap1710
# define cpu_is_omap1610() is_omap1610()
# define cpu_is_omap1611() is_omap1611()
# define cpu_is_omap5912() is_omap5912()
# define cpu_is_omap1621() is_omap1621()
# define cpu_is_omap1710() is_omap1710()
#endif
#endif
linux-7.2.3/include/linux/soc/ti/omap1-usb.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SOC_TI_OMAP1_USB
#define __SOC_TI_OMAP1_USB
/*
* Constants in this file are used all over the place, in platform
* code, as well as the udc, phy and ohci drivers.
* This is not a great design, but unlikely to get fixed after
* such a long time. Don't do this elsewhere.
*/
#define OMAP1_OTG_BASE 0xfffb0400
#define OMAP1_UDC_BASE 0xfffb4000
#define OMAP2_UDC_BASE 0x4805e200
#define OMAP2_OTG_BASE 0x4805e300
#define OTG_BASE OMAP1_OTG_BASE
#define UDC_BASE OMAP1_UDC_BASE
/*
* OTG and transceiver registers, for OMAPs starting with ARM926
*/
#define OTG_REV (OTG_BASE + 0x00)
#define OTG_SYSCON_1 (OTG_BASE + 0x04)
# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
# define OTG_IDLE_EN (1 << 15)
# define HST_IDLE_EN (1 << 14)
# define DEV_IDLE_EN (1 << 13)
# define OTG_RESET_DONE (1 << 2)
# define OTG_SOFT_RESET (1 << 1)
#define OTG_SYSCON_2 (OTG_BASE + 0x08)
# define OTG_EN (1 << 31)
# define USBX_SYNCHRO (1 << 30)
# define OTG_MST16 (1 << 29)
# define SRP_GPDATA (1 << 28)
# define SRP_GPDVBUS (1 << 27)
# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
# define B_ASE_BRST(w) (((w)>>16)&0x07)
# define SRP_DPW (1 << 14)
# define SRP_DATA (1 << 13)
# define SRP_VBUS (1 << 12)
# define OTG_PADEN (1 << 10)
# define HMC_PADEN (1 << 9)
# define UHOST_EN (1 << 8)
# define HMC_TLLSPEED (1 << 7)
# define HMC_TLLATTACH (1 << 6)
# define OTG_HMC(w) (((w)>>0)&0x3f)
#define OTG_CTRL (OTG_BASE + 0x0c)
# define OTG_USB2_EN (1 << 29)
# define OTG_USB2_DP (1 << 28)
# define OTG_USB2_DM (1 << 27)
# define OTG_USB1_EN (1 << 26)
# define OTG_USB1_DP (1 << 25)
# define OTG_USB1_DM (1 << 24)
# define OTG_USB0_EN (1 << 23)
# define OTG_USB0_DP (1 << 22)
# define OTG_USB0_DM (1 << 21)
# define OTG_ASESSVLD (1 << 20)
# define OTG_BSESSEND (1 << 19)
# define OTG_BSESSVLD (1 << 18)
# define OTG_VBUSVLD (1 << 17)
# define OTG_ID (1 << 16)
# define OTG_DRIVER_SEL (1 << 15)
# define OTG_A_SETB_HNPEN (1 << 12)
# define OTG_A_BUSREQ (1 << 11)
# define OTG_B_HNPEN (1 << 9)
# define OTG_B_BUSREQ (1 << 8)
# define OTG_BUSDROP (1 << 7)
# define OTG_PULLDOWN (1 << 5)
# define OTG_PULLUP (1 << 4)
# define OTG_DRV_VBUS (1 << 3)
# define OTG_PD_VBUS (1 << 2)
# define OTG_PU_VBUS (1 << 1)
# define OTG_PU_ID (1 << 0)
#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
# define DRIVER_SWITCH (1 << 15)
# define A_VBUS_ERR (1 << 13)
# define A_REQ_TMROUT (1 << 12)
# define A_SRP_DETECT (1 << 11)
# define B_HNP_FAIL (1 << 10)
# define B_SRP_TMROUT (1 << 9)
# define B_SRP_DONE (1 << 8)
# define B_SRP_STARTED (1 << 7)
# define OPRT_CHG (1 << 0)
#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
// same bits as in IRQ_EN
#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
# define OTGVPD (1 << 14)
# define OTGVPU (1 << 13)
# define OTGPUID (1 << 12)
# define USB2VDR (1 << 10)
# define USB2PDEN (1 << 9)
# define USB2PUEN (1 << 8)
# define USB1VDR (1 << 6)
# define USB1PDEN (1 << 5)
# define USB1PUEN (1 << 4)
# define USB0VDR (1 << 2)
# define USB0PDEN (1 << 1)
# define USB0PUEN (1 << 0)
#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
/*-------------------------------------------------------------------------*/
/* OMAP1 */
#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
# define CONF_USB2_UNI_R (1 << 8)
# define CONF_USB1_UNI_R (1 << 7)
# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
# define CONF_USB0_ISOLATE_R (1 << 3)
# define CONF_USB_PWRDN_DM_R (1 << 2)
# define CONF_USB_PWRDN_DP_R (1 << 1)
#endif
linux-7.2.3/include/linux/soc/ti/ti-msgmgr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Texas Instruments' Message Manager
*
* Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
*/
#ifndef TI_MSGMGR_H
#define TI_MSGMGR_H
struct mbox_chan;
/**
* struct ti_msgmgr_message - Message Manager structure
* @len: Length of data in the Buffer
* @buf: Buffer pointer
* @chan_rx: Expected channel for response, must be provided to use polled rx
* @timeout_rx_ms: Timeout value to use if polling for response
*
* This is the structure for data used in mbox_send_message
* the length of data buffer used depends on the SoC integration
* parameters - each message may be 64, 128 bytes long depending
* on SoC. Client is supposed to be aware of this.
*/
struct ti_msgmgr_message {
size_t len;
u8 *buf;
struct mbox_chan *chan_rx;
int timeout_rx_ms;
};
#endif /* TI_MSGMGR_H */
linux-7.2.3/include/linux/soc/ti/ti_sci_inta_msi.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Texas Instruments' K3 TI SCI INTA MSI helper
*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
#define __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
#include <linux/msi.h>
#include <linux/soc/ti/ti_sci_protocol.h>
struct irq_domain
*ti_sci_inta_msi_create_irq_domain(struct fwnode_handle *fwnode,
struct msi_domain_info *info,
struct irq_domain *parent);
int ti_sci_inta_msi_domain_alloc_irqs(struct device *dev,
struct ti_sci_resource *res);
#endif /* __INCLUDE_LINUX_IRQCHIP_TI_SCI_INTA_H */
linux-7.2.3/include/linux/soc/ti/ti_sci_protocol.h
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// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments System Control Interface Protocol
*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
*/
#ifndef __TISCI_PROTOCOL_H
#define __TISCI_PROTOCOL_H
/**
* struct ti_sci_version_info - version information structure
* @abi_major: Major ABI version. Change here implies risk of backward
* compatibility break.
* @abi_minor: Minor ABI version. Change here implies new feature addition,
* or compatible change in ABI.
* @firmware_revision: Firmware revision (not usually used).
* @firmware_description: Firmware description (not usually used).
*/
struct ti_sci_version_info {
u8 abi_major;
u8 abi_minor;
u16 firmware_revision;
char firmware_description[32];
};
struct ti_sci_handle;
/**
* struct ti_sci_core_ops - SoC Core Operations
* @reboot_device: Reboot the SoC
* Returns 0 for successful request(ideally should never return),
* else returns corresponding error value.
*/
struct ti_sci_core_ops {
int (*reboot_device)(const struct ti_sci_handle *handle);
};
/**
* struct ti_sci_dev_ops - Device control operations
* @get_device: Command to request for device managed by TISCI
* Returns 0 for successful exclusive request, else returns
* corresponding error message.
* @idle_device: Command to idle a device managed by TISCI
* Returns 0 for successful exclusive request, else returns
* corresponding error message.
* @put_device: Command to release a device managed by TISCI
* Returns 0 for successful release, else returns corresponding
* error message.
* @is_valid: Check if the device ID is a valid ID.
* Returns 0 if the ID is valid, else returns corresponding error.
* @get_context_loss_count: Command to retrieve context loss counter - this
* increments every time the device looses context. Overflow
* is possible.
* - count: pointer to u32 which will retrieve counter
* Returns 0 for successful information request and count has
* proper data, else returns corresponding error message.
* @is_idle: Reports back about device idle state
* - req_state: Returns requested idle state
* Returns 0 for successful information request and req_state and
* current_state has proper data, else returns corresponding error
* message.
* @is_stop: Reports back about device stop state
* - req_state: Returns requested stop state
* - current_state: Returns current stop state
* Returns 0 for successful information request and req_state and
* current_state has proper data, else returns corresponding error
* message.
* @is_on: Reports back about device ON(or active) state
* - req_state: Returns requested ON state
* - current_state: Returns current ON state
* Returns 0 for successful information request and req_state and
* current_state has proper data, else returns corresponding error
* message.
* @is_transitioning: Reports back if the device is in the middle of transition
* of state.
* -current_state: Returns 'true' if currently transitioning.
* @set_device_resets: Command to configure resets for device managed by TISCI.
* -reset_state: Device specific reset bit field
* Returns 0 for successful request, else returns
* corresponding error message.
* @get_device_resets: Command to read state of resets for device managed
* by TISCI.
* -reset_state: pointer to u32 which will retrieve resets
* Returns 0 for successful request, else returns
* corresponding error message.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* -id: Device Identifier
*
* Request for the device - NOTE: the client MUST maintain integrity of
* usage count by balancing get_device with put_device. No refcounting is
* managed by driver for that purpose.
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
u32 id, u32 *count);
int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
bool *requested_state);
int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
bool *req_state, bool *current_state);
int (*is_on)(const struct ti_sci_handle *handle, u32 id,
bool *req_state, bool *current_state);
int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
bool *current_state);
int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 reset_state);
int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 *reset_state);
};
/**
* struct ti_sci_clk_ops - Clock control operations
* @get_clock: Request for activation of clock and manage by processor
* - needs_ssc: 'true' if Spread Spectrum clock is desired.
* - can_change_freq: 'true' if frequency change is desired.
* - enable_input_term: 'true' if input termination is desired.
* @idle_clock: Request for Idling a clock managed by processor
* @put_clock: Release the clock to be auto managed by TISCI
* @is_auto: Is the clock being auto managed
* - req_state: state indicating if the clock is auto managed
* @is_on: Is the clock ON
* - req_state: if the clock is requested to be forced ON
* - current_state: if the clock is currently ON
* @is_off: Is the clock OFF
* - req_state: if the clock is requested to be forced OFF
* - current_state: if the clock is currently Gated
* @set_parent: Set the clock source of a specific device clock
* - parent_id: Parent clock identifier to set.
* @get_parent: Get the current clock source of a specific device clock
* - parent_id: Parent clock identifier which is the parent.
* @get_num_parents: Get the number of parents of the current clock source
* - num_parents: returns the number of parent clocks.
* @get_best_match_freq: Find a best matching frequency for a frequency
* range.
* - match_freq: Best matching frequency in Hz.
* @set_freq: Set the Clock frequency
* @get_freq: Get the Clock frequency
* - current_freq: Frequency in Hz that the clock is at.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* -did: Device identifier this request is for
* -cid: Clock identifier for the device for this request.
* Each device has it's own set of clock inputs. This indexes
* which clock input to modify.
* -min_freq: The minimum allowable frequency in Hz. This is the minimum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
* -target_freq: The target clock frequency in Hz. A frequency will be
* processed as close to this target frequency as possible.
* -max_freq: The maximum allowable frequency in Hz. This is the maximum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
*
* Request for the clock - NOTE: the client MUST maintain integrity of
* usage count by balancing get_clock with put_clock. No refcounting is
* managed by driver for that purpose.
*/
struct ti_sci_clk_ops {
int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
bool needs_ssc, bool can_change_freq,
bool enable_input_term);
int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
bool *req_state);
int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
bool *req_state, bool *current_state);
int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
bool *req_state, bool *current_state);
int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
u32 parent_id);
int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
u32 *parent_id);
int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
u32 cid, u32 *num_parents);
int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
u32 cid, u64 min_freq, u64 target_freq,
u64 max_freq, u64 *match_freq);
int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
u64 min_freq, u64 target_freq, u64 max_freq);
int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
u64 *current_freq);
};
/* TISCI LPM IO isolation control values */
#define TISCI_MSG_VALUE_IO_ENABLE 1
#define TISCI_MSG_VALUE_IO_DISABLE 0
/* TISCI LPM constraint state values */
#define TISCI_MSG_CONSTRAINT_SET 1
#define TISCI_MSG_CONSTRAINT_CLR 0
/**
* struct ti_sci_pm_ops - Low Power Mode (LPM) control operations
* @lpm_wake_reason: Get the wake up source that woke the SoC from LPM
* - source: The wake up source that woke soc from LPM.
* - timestamp: Timestamp at which soc woke.
* @set_device_constraint: Set LPM constraint on behalf of a device
* - id: Device Identifier
* - state: The desired state of device constraint: set or clear.
* @set_latency_constraint: Set LPM resume latency constraint
* - latency: maximum acceptable latency to wake up from low power mode
* - state: The desired state of latency constraint: set or clear.
*/
struct ti_sci_pm_ops {
int (*lpm_wake_reason)(const struct ti_sci_handle *handle,
u32 *source, u64 *timestamp, u8 *pin, u8 *mode);
int (*set_device_constraint)(const struct ti_sci_handle *handle,
u32 id, u8 state);
int (*set_latency_constraint)(const struct ti_sci_handle *handle,
u16 latency, u8 state);
};
/**
* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
* @start: Start index of the first resource range.
* @num: Number of resources in the first range.
* @start_sec: Start index of the second resource range.
* @num_sec: Number of resources in the second range.
* @res_map: Bitmap to manage the allocation of these resources.
*/
struct ti_sci_resource_desc {
u16 start;
u16 num;
u16 start_sec;
u16 num_sec;
unsigned long *res_map;
};
/**
* struct ti_sci_rm_core_ops - Resource management core operations
* @get_range: Get a range of resources belonging to ti sci host.
* @get_rage_from_shost: Get a range of resources belonging to
* specified host id.
* - s_host: Host processing entity to which the
* resources are allocated
*
* NOTE: for these functions, all the parameters are consolidated and defined
* as below:
* - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* - dev_id: TISCI device ID.
* - subtype: Resource assignment subtype that is being requested
* from the given device.
* - desc: Pointer to ti_sci_resource_desc to be updated with the resource
* range start index and number of resources
*/
struct ti_sci_rm_core_ops {
int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
u8 subtype, struct ti_sci_resource_desc *desc);
int (*get_range_from_shost)(const struct ti_sci_handle *handle,
u32 dev_id, u8 subtype, u8 s_host,
struct ti_sci_resource_desc *desc);
};
#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
#define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
#define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
/**
* struct ti_sci_rm_irq_ops: IRQ management operations
* @set_irq: Set an IRQ route between the requested source
* and destination
* @set_event_map: Set an Event based peripheral irq to Interrupt
* Aggregator.
* @free_irq: Free an IRQ route between the requested source
* and destination.
* @free_event_map: Free an event based peripheral irq to Interrupt
* Aggregator.
*/
struct ti_sci_rm_irq_ops {
int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
u16 src_index, u16 dst_id, u16 dst_host_irq);
int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
u16 src_index, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit);
int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
u16 src_index, u16 dst_id, u16 dst_host_irq);
int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
u16 src_index, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit);
};
/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
/* RA config.count parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
/* RA config.size parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
/* RA config.order_id parameter is valid for RM ring configure TISCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
/* RA config.virtid parameter is valid for RM ring configure TISCI message */
#define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID BIT(6)
/* RA config.asel parameter is valid for RM ring configure TISCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
/**
* struct ti_sci_msg_rm_ring_cfg - Ring configuration
*
* Parameters for Navigator Subsystem ring configuration
* See @ti_sci_msg_rm_ring_cfg_req
*/
struct ti_sci_msg_rm_ring_cfg {
u32 valid_params;
u16 nav_id;
u16 index;
u32 addr_lo;
u32 addr_hi;
u32 count;
u8 mode;
u8 size;
u8 order_id;
u16 virtid;
u8 asel;
};
/**
* struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
* @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
*/
struct ti_sci_rm_ringacc_ops {
int (*set_cfg)(const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_ring_cfg *params);
};
/**
* struct ti_sci_rm_psil_ops - PSI-L thread operations
* @pair: pair PSI-L source thread to a destination thread.
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
* TCHAN_THRD_ID register is updated.
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
* RCHAN_THRD_ID register is updated.
* @unpair: unpair PSI-L source thread from a destination thread.
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
* TCHAN_THRD_ID register is cleared.
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
* RCHAN_THRD_ID register is cleared.
*/
struct ti_sci_rm_psil_ops {
int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
u32 src_thread, u32 dst_thread);
int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
u32 src_thread, u32 dst_thread);
};
/* UDMAP channel types */
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
/* UDMAP TX/RX channel valid_params common declarations */
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
/**
* Configures a Navigator Subsystem UDMAP transmit channel
*
* Configures a Navigator Subsystem UDMAP transmit channel registers.
* See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg {
u32 valid_params;
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
u16 nav_id;
u16 index;
u8 tx_pause_on_err;
u8 tx_filt_einfo;
u8 tx_filt_pswords;
u8 tx_atype;
u8 tx_chan_type;
u8 tx_supr_tdpkt;
u16 tx_fetch_size;
u8 tx_credit_count;
u16 txcq_qnum;
u8 tx_priority;
u8 tx_qos;
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
u8 tx_burst_size;
u8 tx_tdtype;
u8 extended_ch_type;
};
/**
* Configures a Navigator Subsystem UDMAP receive channel
*
* Configures a Navigator Subsystem UDMAP receive channel registers.
* See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
*/
struct ti_sci_msg_rm_udmap_rx_ch_cfg {
u32 valid_params;
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
u16 nav_id;
u16 index;
u16 rx_fetch_size;
u16 rxcq_qnum;
u8 rx_priority;
u8 rx_qos;
u8 rx_orderid;
u8 rx_sched_priority;
u16 flowid_start;
u16 flowid_cnt;
u8 rx_pause_on_err;
u8 rx_atype;
u8 rx_chan_type;
u8 rx_ignore_short;
u8 rx_ignore_long;
u8 rx_burst_size;
};
/**
* Configures a Navigator Subsystem UDMAP receive flow
*
* Configures a Navigator Subsystem UDMAP receive flow's registers.
* See @tis_ci_msg_rm_udmap_flow_cfg_req
*/
struct ti_sci_msg_rm_udmap_flow_cfg {
u32 valid_params;
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
u16 nav_id;
u16 flow_index;
u8 rx_einfo_present;
u8 rx_psinfo_present;
u8 rx_error_handling;
u8 rx_desc_type;
u16 rx_sop_offset;
u16 rx_dest_qnum;
u8 rx_src_tag_hi;
u8 rx_src_tag_lo;
u8 rx_dest_tag_hi;
u8 rx_dest_tag_lo;
u8 rx_src_tag_hi_sel;
u8 rx_src_tag_lo_sel;
u8 rx_dest_tag_hi_sel;
u8 rx_dest_tag_lo_sel;
u16 rx_fdq0_sz0_qnum;
u16 rx_fdq1_qnum;
u16 rx_fdq2_qnum;
u16 rx_fdq3_qnum;
u8 rx_ps_location;
};
/**
* struct ti_sci_rm_udmap_ops - UDMA Management operations
* @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
* @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
* @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
*/
struct ti_sci_rm_udmap_ops {
int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_flow_cfg *params);
};
/**
* struct ti_sci_proc_ops - Processor Control operations
* @request: Request to control a physical processor. The requesting host
* should be in the processor access list
* @release: Relinquish a physical processor control
* @handover: Handover a physical processor control to another host
* in the permitted list
* @set_config: Set base configuration of a processor
* @set_control: Setup limited control flags in specific cases
* @get_status: Get the state of physical processor
*
* NOTE: The following paramteres are generic in nature for all these ops,
* -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
* -pid: Processor ID
* -hid: Host ID
*/
struct ti_sci_proc_ops {
int (*request)(const struct ti_sci_handle *handle, u8 pid);
int (*release)(const struct ti_sci_handle *handle, u8 pid);
int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
u64 boot_vector, u32 cfg_set, u32 cfg_clr);
int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
u32 ctrl_set, u32 ctrl_clr);
int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
u32 *status_flags);
};
/**
* struct ti_sci_ops - Function support for TI SCI
* @dev_ops: Device specific operations
* @clk_ops: Clock specific operations
* @rm_core_ops: Resource management core operations.
* @rm_irq_ops: IRQ management specific operations
* @proc_ops: Processor Control specific operations
*/
struct ti_sci_ops {
struct ti_sci_core_ops core_ops;
struct ti_sci_dev_ops dev_ops;
struct ti_sci_clk_ops clk_ops;
struct ti_sci_pm_ops pm_ops;
struct ti_sci_rm_core_ops rm_core_ops;
struct ti_sci_rm_irq_ops rm_irq_ops;
struct ti_sci_rm_ringacc_ops rm_ring_ops;
struct ti_sci_rm_psil_ops rm_psil_ops;
struct ti_sci_rm_udmap_ops rm_udmap_ops;
struct ti_sci_proc_ops proc_ops;
};
/**
* struct ti_sci_handle - Handle returned to TI SCI clients for usage.
* @version: structure containing version information
* @ops: operations that are made available to TI SCI clients
*/
struct ti_sci_handle {
struct ti_sci_version_info version;
struct ti_sci_ops ops;
};
#define TI_SCI_RESOURCE_NULL 0xffff
/**
* struct ti_sci_resource - Structure representing a resource assigned
* to a device.
* @sets: Number of sets available from this resource type
* @lock: Lock to guard the res map in each set.
* @desc: Array of resource descriptors.
*/
struct ti_sci_resource {
u16 sets;
raw_spinlock_t lock;
struct ti_sci_resource_desc *desc;
};
#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
int ti_sci_put_handle(const struct ti_sci_handle *handle);
const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
const char *property);
const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
const char *property);
u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
struct device *dev, u32 dev_id, char *of_prop);
struct ti_sci_resource *
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
u32 dev_id, u32 sub_type);
#else /* CONFIG_TI_SCI_PROTOCOL */
static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
{
return ERR_PTR(-EINVAL);
}
static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
{
return -EINVAL;
}
static inline
const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
{
return ERR_PTR(-EINVAL);
}
static inline
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
const char *property)
{
return ERR_PTR(-EINVAL);
}
static inline
const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
const char *property)
{
return ERR_PTR(-EINVAL);
}
static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
{
return TI_SCI_RESOURCE_NULL;
}
static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
{
}
static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
{
return 0;
}
static inline struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
struct device *dev, u32 dev_id, char *of_prop)
{
return ERR_PTR(-EINVAL);
}
static inline struct ti_sci_resource *
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
u32 dev_id, u32 sub_type)
{
return ERR_PTR(-EINVAL);
}
#endif /* CONFIG_TI_SCI_PROTOCOL */
#endif /* __TISCI_PROTOCOL_H */