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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/include/soc/amlogic/meson_ddr_pmu.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022 Amlogic, Inc. All rights reserved.
*/
#ifndef __MESON_DDR_PMU_H__
#define __MESON_DDR_PMU_H__
#define MAX_CHANNEL_NUM 8
enum {
ALL_CHAN_COUNTER_ID,
CHAN1_COUNTER_ID,
CHAN2_COUNTER_ID,
CHAN3_COUNTER_ID,
CHAN4_COUNTER_ID,
CHAN5_COUNTER_ID,
CHAN6_COUNTER_ID,
CHAN7_COUNTER_ID,
CHAN8_COUNTER_ID,
COUNTER_MAX_ID,
};
struct dmc_info;
struct dmc_counter {
u64 all_cnt; /* The count of all requests come in/out ddr controller */
union {
u64 all_req;
struct {
u64 all_idle_cnt;
u64 all_16bit_cnt;
};
};
u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
};
struct dmc_hw_info {
void (*enable)(struct dmc_info *info);
void (*disable)(struct dmc_info *info);
/* Bind an axi line to a bandwidth-monitor channel */
void (*set_axi_filter)(struct dmc_info *info, int axi_id, int chann);
int (*irq_handler)(struct dmc_info *info,
struct dmc_counter *counter);
void (*get_counters)(struct dmc_info *info,
struct dmc_counter *counter);
int dmc_nr; /* The number of dmc controller */
int chann_nr; /* The number of dmc bandwidth monitor channels */
struct attribute **fmt_attr;
const u64 capability[2];
};
struct dmc_info {
const struct dmc_hw_info *hw_info;
void __iomem *ddr_reg[4];
unsigned long timer_value; /* Timer value in TIMER register */
void __iomem *pll_reg;
int irq_num; /* irq vector number */
};
int meson_ddr_pmu_create(struct platform_device *pdev);
int meson_ddr_pmu_remove(struct platform_device *pdev);
#endif /* __MESON_DDR_PMU_H__ */
linux-7.2.3/include/soc/arc/arc_aux.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2016-2017 Synopsys, Inc. (www.synopsys.com)
*/
#ifndef __SOC_ARC_AUX_H__
#define __SOC_ARC_AUX_H__
#ifdef CONFIG_ARC
#define read_aux_reg(r) __builtin_arc_lr(r)
/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r)
#else /* !CONFIG_ARC */
static inline int read_aux_reg(u32 r)
{
return 0;
}
/*
* function helps elide unused variable warning
* see: https://lists.infradead.org/pipermail/linux-snps-arc/2016-November/001748.html
*/
static inline void write_aux_reg(u32 r, u32 v)
{
;
}
#endif
#define READ_BCR(reg, into) \
{ \
unsigned int tmp; \
tmp = read_aux_reg(reg); \
if (sizeof(tmp) == sizeof(into)) { \
into = *((typeof(into) *)&tmp); \
} else { \
extern void bogus_undefined(void); \
bogus_undefined(); \
} \
}
#define WRITE_AUX(reg, into) \
{ \
unsigned int tmp; \
if (sizeof(tmp) == sizeof(into)) { \
tmp = (*(unsigned int *)&(into)); \
write_aux_reg(reg, tmp); \
} else { \
extern void bogus_undefined(void); \
bogus_undefined(); \
} \
}
#endif
linux-7.2.3/include/soc/arc/mcip.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
#ifndef __SOC_ARC_MCIP_H
#define __SOC_ARC_MCIP_H
#include <soc/arc/arc_aux.h>
#define ARC_REG_MCIP_BCR 0x0d0
#define ARC_REG_MCIP_IDU_BCR 0x0D5
#define ARC_REG_GFRC_BUILD 0x0D6
#define ARC_REG_MCIP_CMD 0x600
#define ARC_REG_MCIP_WDATA 0x601
#define ARC_REG_MCIP_READBACK 0x602
struct mcip_cmd {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:8, param:16, cmd:8;
#else
unsigned int cmd:8, param:16, pad:8;
#endif
#define CMD_INTRPT_GENERATE_IRQ 0x01
#define CMD_INTRPT_GENERATE_ACK 0x02
#define CMD_INTRPT_READ_STATUS 0x03
#define CMD_INTRPT_CHECK_SOURCE 0x04
/* Semaphore Commands */
#define CMD_SEMA_CLAIM_AND_READ 0x11
#define CMD_SEMA_RELEASE 0x12
#define CMD_DEBUG_SET_MASK 0x34
#define CMD_DEBUG_READ_MASK 0x35
#define CMD_DEBUG_SET_SELECT 0x36
#define CMD_DEBUG_READ_SELECT 0x37
#define CMD_GFRC_READ_LO 0x42
#define CMD_GFRC_READ_HI 0x43
#define CMD_GFRC_SET_CORE 0x47
#define CMD_GFRC_READ_CORE 0x48
#define CMD_IDU_ENABLE 0x71
#define CMD_IDU_DISABLE 0x72
#define CMD_IDU_SET_MODE 0x74
#define CMD_IDU_READ_MODE 0x75
#define CMD_IDU_SET_DEST 0x76
#define CMD_IDU_ACK_CIRQ 0x79
#define CMD_IDU_SET_MASK 0x7C
#define IDU_M_TRIG_LEVEL 0x0
#define IDU_M_TRIG_EDGE 0x1
#define IDU_M_DISTRI_RR 0x0
#define IDU_M_DISTRI_DEST 0x2
};
struct mcip_bcr {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad4:6, pw_dom:1, pad3:1,
idu:1, pad2:1, num_cores:6,
pad:1, gfrc:1, dbg:1, pw:1,
msg:1, sem:1, ipi:1, slv:1,
ver:8;
#else
unsigned int ver:8,
slv:1, ipi:1, sem:1, msg:1,
pw:1, dbg:1, gfrc:1, pad:1,
num_cores:6, pad2:1, idu:1,
pad3:1, pw_dom:1, pad4:6;
#endif
};
struct mcip_idu_bcr {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:21, cirqnum:3, ver:8;
#else
unsigned int ver:8, cirqnum:3, pad:21;
#endif
};
/*
* Build register for IDU contains not an actual number of supported common
* interrupts but an exponent of 2 which must be multiplied by 4 to
* get a number of supported common interrupts.
*/
#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
/*
* MCIP programming model
*
* - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
* (param could be irq, common_irq, core_id ...)
* - More involved commands setup MCIP_WDATA with cmd specific data
* before invoking the simple command
*/
static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
{
struct mcip_cmd buf;
buf.pad = 0;
buf.cmd = cmd;
buf.param = param;
WRITE_AUX(ARC_REG_MCIP_CMD, buf);
}
/*
* Setup additional data for a cmd
* Callers need to lock to ensure atomicity
*/
static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
unsigned int data)
{
write_aux_reg(ARC_REG_MCIP_WDATA, data);
__mcip_cmd(cmd, param);
}
/*
* Read MCIP register
*/
static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
{
__mcip_cmd(cmd, param);
return read_aux_reg(ARC_REG_MCIP_READBACK);
}
#endif
linux-7.2.3/include/soc/arc/timers.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
*/
#ifndef __SOC_ARC_TIMERS_H
#define __SOC_ARC_TIMERS_H
#include <soc/arc/arc_aux.h>
/* Timer related Aux registers */
#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
/* CTRL reg bits */
#define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
#define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
#define ARC_TIMERN_MAX 0xFFFFFFFF
#define ARC_REG_TIMERS_BCR 0x75
struct bcr_timer {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
#else
unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
#endif
};
#endif
linux-7.2.3/include/soc/at91/at91sam9_ddrsdr.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Header file for the Atmel DDR/SDR SDRAM Controller
*
* Copyright (C) 2010 Atmel Corporation
* Nicolas Ferre <nicolas.ferre@atmel.com>
*/
#ifndef AT91SAM9_DDRSDR_H
#define AT91SAM9_DDRSDR_H
#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
#define AT91_DDRSDRC_MODE_NORMAL 0
#define AT91_DDRSDRC_MODE_NOP 1
#define AT91_DDRSDRC_MODE_PRECHARGE 2
#define AT91_DDRSDRC_MODE_LMR 3
#define AT91_DDRSDRC_MODE_REFRESH 4
#define AT91_DDRSDRC_MODE_EXT_LMR 5
#define AT91_DDRSDRC_MODE_DEEP 6
#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
#define AT91_DDRSDRC_NR_11 (0 << 2)
#define AT91_DDRSDRC_NR_12 (1 << 2)
#define AT91_DDRSDRC_NR_13 (2 << 2)
#define AT91_DDRSDRC_NR_14 (3 << 2)
#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
#define AT91_DDRSDRC_CAS_2 (2 << 4)
#define AT91_DDRSDRC_CAS_3 (3 << 4)
#define AT91_DDRSDRC_CAS_25 (6 << 4)
#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_DDRSDRC_LPCB_DISABLE 0
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
#define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
#define AT91_DDRSDRC_MD_LPDDR3 5
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
#define AT91_DDRSDRC_MD_LPDDR2 7
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
#endif
linux-7.2.3/include/soc/at91/at91sam9_sdramc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* SDRAM Controllers (SDRAMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*/
#ifndef AT91SAM9_SDRAMC_H
#define AT91SAM9_SDRAMC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
#define AT91_SDRAMC_MODE_PRECHARGE 2
#define AT91_SDRAMC_MODE_LMR 3
#define AT91_SDRAMC_MODE_REFRESH 4
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_1 (1 << 5)
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_CAS_3 (3 << 5)
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
#define AT91_SDRAMC_LPCB_POWER_DOWN 2
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
#endif
linux-7.2.3/include/soc/at91/atmel-secumod.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atmel Security Module register offsets and bit definitions.
*
* Copyright (C) 2016 Atmel
*
* Author: Alexandre Belloni <alexandre.belloni@free-electrons.com>
*/
#ifndef _LINUX_SOC_AT91_ATMEL_SECUMOD_H
#define _LINUX_SOC_AT91_ATMEL_SECUMOD_H
#define AT91_SECUMOD_RAMRDY 0x14
#define AT91_SECUMOD_RAMRDY_READY BIT(0)
#endif /* _LINUX_SOC_AT91_ATMEL_SECUMOD_H */
linux-7.2.3/include/soc/at91/atmel-sfr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atmel SFR (Special Function Registers) register offsets and bit definitions.
*
* Copyright (C) 2016 Atmel
*
* Author: Ludovic Desroches <ludovic.desroches@atmel.com>
*/
#ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H
#define _LINUX_MFD_SYSCON_ATMEL_SFR_H
#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */
#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */
/* 0x08 ~ 0x0c: Reserved */
#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */
#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */
#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */
#define AT91_SFR_LS 0x7c /* Light Sleep Register */
#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */
#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */
/* Field definitions */
#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))
#define AT91_SFR_CCFG_EBI_DBPUC BIT(8)
#define AT91_SFR_CCFG_EBI_DBPDC BIT(9)
#define AT91_SFR_CCFG_EBI_DRIVE BIT(17)
#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)
#define AT91_SFR_CCFG_DDR_MP_EN BIT(25)
#define AT91_SFR_OHCIICR_RES(x) BIT(x)
#define AT91_SFR_OHCIICR_ARIE BIT(4)
#define AT91_SFR_OHCIICR_APPSTART BIT(5)
#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)
#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)
#define AT91_SFR_OHCIISR_RIS(x) BIT(x)
#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
#define AT91_SFR_UTMISWAP_PORT(x) BIT(x)
#define AT91_SFR_LS_VALUE(x) BIT(x)
#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)
#define AT91_SFR_WPMR_WPEN BIT(0)
#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
#endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */
linux-7.2.3/include/soc/at91/atmel_tcb.h
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/*
* Timer/Counter Unit (TC) registers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __SOC_ATMEL_TCB_H
#define __SOC_ATMEL_TCB_H
#include <linux/compiler.h>
#include <linux/list.h>
/*
* Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
* three general-purpose 16-bit timers. These timers share one register bank.
* Depending on the SOC, each timer may have its own clock and IRQ, or those
* may be shared by the whole TC block.
*
* These TC blocks may have up to nine external pins: TCLK0..2 signals for
* clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
* or triggering. Those pins need to be set up for use with the TC block,
* else they will be used as GPIOs or for a different controller.
*
* Although we expect each TC block to have a platform_device node, those
* nodes are not what drivers bind to. Instead, they ask for a specific
* TC block, by number ... which is a common approach on systems with many
* timers. Then they use clk_get() and platform_get_irq() to get clock and
* IRQ resources.
*/
struct clk;
/**
* struct atmel_tcb_config - SoC data for a Timer/Counter Block
* @counter_width: size in bits of a timer counter register
* @has_gclk: boolean indicating if a timer counter has a generic clock
* @has_qdec: boolean indicating if a timer counter has a quadrature
* decoder.
*/
struct atmel_tcb_config {
size_t counter_width;
bool has_gclk;
bool has_qdec;
};
/**
* struct atmel_tc - information about a Timer/Counter Block
* @pdev: physical device
* @regs: mapping through which the I/O registers can be accessed
* @id: block id
* @tcb_config: configuration data from SoC
* @irq: irq for each of the three channels
* @clk: internal clock source for each of the three channels
* @node: list node, for tclib internal use
* @allocated: if already used, for tclib internal use
*
* On some platforms, each TC channel has its own clocks and IRQs,
* while on others, all TC channels share the same clock and IRQ.
* Drivers should clk_enable() all the clocks they need even though
* all the entries in @clk may point to the same physical clock.
* Likewise, drivers should request irqs independently for each
* channel, but they must use IRQF_SHARED in case some of the entries
* in @irq are actually the same IRQ.
*/
struct atmel_tc {
struct platform_device *pdev;
void __iomem *regs;
int id;
const struct atmel_tcb_config *tcb_config;
int irq[3];
struct clk *clk[3];
struct clk *slow_clk;
struct list_head node;
bool allocated;
};
/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
extern const u8 atmel_tc_divisors[5];
/*
* Two registers have block-wide controls. These are: configuring the three
* "external" clocks (or event sources) used by the timer channels; and
* synchronizing the timers by resetting them all at once.
*
* "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
* signals. Or, it can mean "external to timer", using the TIOA output from
* one of the other two timers that's being run in waveform mode.
*/
#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
/*
* Each TC block has three "channels", each with one counter and controls.
*
* Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
* when it's not "external") is silicon-specific. AT91 platforms use one
* set of definitions; AVR32 platforms use a different set. Don't hard-wire
* such knowledge into your code, use the global "atmel_tc_divisors" ...
* where index N is the divisor for clock N+1, else zero to indicate it uses
* the 32 KiHz clock.
*
* The timers can be chained in various ways, and operated in "waveform"
* generation mode (including PWM) or "capture" mode (to time events). In
* both modes, behavior can be configured in many ways.
*
* Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
* PWM output, and TIOB as either another PWM or as a trigger. Capture mode
* uses them only as inputs.
*/
#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
/* Both modes share some CMR bits */
#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
#define ATMEL_TC_XC0 (5 << 0)
#define ATMEL_TC_XC1 (6 << 0)
#define ATMEL_TC_XC2 (7 << 0)
#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
#define ATMEL_TC_BURST (3 << 4) /* clock gating */
#define ATMEL_TC_GATE_NONE (0 << 4)
#define ATMEL_TC_GATE_XC0 (1 << 4)
#define ATMEL_TC_GATE_XC1 (2 << 4)
#define ATMEL_TC_GATE_XC2 (3 << 4)
#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
/* CAPTURE mode CMR bits */
#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
#define ATMEL_TC_LDRA_NONE (0 << 16)
#define ATMEL_TC_LDRA_RISING (1 << 16)
#define ATMEL_TC_LDRA_FALLING (2 << 16)
#define ATMEL_TC_LDRA_BOTH (3 << 16)
#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
#define ATMEL_TC_LDRB_NONE (0 << 18)
#define ATMEL_TC_LDRB_RISING (1 << 18)
#define ATMEL_TC_LDRB_FALLING (2 << 18)
#define ATMEL_TC_LDRB_BOTH (3 << 18)
/* WAVEFORM mode CMR bits */
#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
#define ATMEL_TC_EEVT (3 << 10) /* external event source */
#define ATMEL_TC_EEVT_TIOB (0 << 10)
#define ATMEL_TC_EEVT_XC0 (1 << 10)
#define ATMEL_TC_EEVT_XC1 (2 << 10)
#define ATMEL_TC_EEVT_XC2 (3 << 10)
#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
#define ATMEL_TC_WAVESEL_UP (0 << 13)
#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
#define ATMEL_TC_ACPA_NONE (0 << 16)
#define ATMEL_TC_ACPA_SET (1 << 16)
#define ATMEL_TC_ACPA_CLEAR (2 << 16)
#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
#define ATMEL_TC_ACPC_NONE (0 << 18)
#define ATMEL_TC_ACPC_SET (1 << 18)
#define ATMEL_TC_ACPC_CLEAR (2 << 18)
#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
#define ATMEL_TC_AEEVT_NONE (0 << 20)
#define ATMEL_TC_AEEVT_SET (1 << 20)
#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
#define ATMEL_TC_ASWTRG_NONE (0 << 22)
#define ATMEL_TC_ASWTRG_SET (1 << 22)
#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
#define ATMEL_TC_BCPB_NONE (0 << 24)
#define ATMEL_TC_BCPB_SET (1 << 24)
#define ATMEL_TC_BCPB_CLEAR (2 << 24)
#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
#define ATMEL_TC_BCPC_NONE (0 << 26)
#define ATMEL_TC_BCPC_SET (1 << 26)
#define ATMEL_TC_BCPC_CLEAR (2 << 26)
#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
#define ATMEL_TC_BEEVT_NONE (0 << 28)
#define ATMEL_TC_BEEVT_SET (1 << 28)
#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
#define ATMEL_TC_BSWTRG_NONE (0 << 30)
#define ATMEL_TC_BSWTRG_SET (1 << 30)
#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
#define ATMEL_TC_CV 0x10 /* counter Value */
#define ATMEL_TC_RA 0x14 /* register A */
#define ATMEL_TC_RB 0x18 /* register B */
#define ATMEL_TC_RC 0x1c /* register C */
#define ATMEL_TC_SR 0x20 /* status (read-only) */
/* Status-only flags */
#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
/* Status and IRQ flags */
#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
#define ATMEL_TC_ALL_IRQ (ATMEL_TC_COVFS | ATMEL_TC_LOVRS | \
ATMEL_TC_CPAS | ATMEL_TC_CPBS | \
ATMEL_TC_CPCS | ATMEL_TC_LDRAS | \
ATMEL_TC_LDRBS | ATMEL_TC_ETRGS) \
/* all IRQs */
#endif
linux-7.2.3/include/soc/at91/sama7-ddr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets
* and bit definitions.
*
* Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
*
* Author: Claudu Beznea <claudiu.beznea@microchip.com>
*/
#ifndef __SAMA7_DDR_H__
#define __SAMA7_DDR_H__
/* DDR3PHY */
#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
#define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */
#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
#define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
#define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
#define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */
#define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
#define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */
#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */
#define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
#define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
#define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
#define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
#define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */
#define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */
#define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */
/* UDDRC */
#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */
#define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
#define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */
#define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */
#define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */
#define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
#define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */
#define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */
#define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */
#define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */
#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */
#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */
#define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */
#define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */
#define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */
#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */
#define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */
#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */
#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */
#endif /* __SAMA7_DDR_H__ */
linux-7.2.3/include/soc/at91/sama7-sfrbu.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Microchip SAMA7 SFRBU registers offsets and bit definitions.
*
* Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
*
* Author: Claudu Beznea <claudiu.beznea@microchip.com>
*/
#ifndef __SAMA7_SFRBU_H__
#define __SAMA7_SFRBU_H__
#ifdef CONFIG_SOC_SAMA7
#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */
#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */
#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */
#endif /* CONFIG_SOC_SAMA7 */
#endif /* __SAMA7_SFRBU_H__ */
linux-7.2.3/include/soc/bcm2835/raspberrypi-firmware.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright © 2015 Broadcom
*/
#ifndef __SOC_RASPBERRY_FIRMWARE_H__
#define __SOC_RASPBERRY_FIRMWARE_H__
#include <linux/types.h>
#include <linux/of_device.h>
struct rpi_firmware;
enum rpi_firmware_property_status {
RPI_FIRMWARE_STATUS_REQUEST = 0,
RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
};
/**
* struct rpi_firmware_property_tag_header - Firmware property tag header
* @tag: One of enum_mbox_property_tag.
* @buf_size: The number of bytes in the value buffer following this
* struct.
* @req_resp_size: On submit, the length of the request (though it doesn't
* appear to be currently used by the firmware). On return,
* the length of the response (always 4 byte aligned), with
* the low bit set.
*/
struct rpi_firmware_property_tag_header {
u32 tag;
u32 buf_size;
u32 req_resp_size;
};
enum rpi_firmware_property_tag {
RPI_FIRMWARE_PROPERTY_END = 0,
RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
RPI_FIRMWARE_GET_BOARD_SERIAL = 0x00010004,
RPI_FIRMWARE_GET_ARM_MEMORY = 0x00010005,
RPI_FIRMWARE_GET_VC_MEMORY = 0x00010006,
RPI_FIRMWARE_GET_CLOCKS = 0x00010007,
RPI_FIRMWARE_GET_POWER_STATE = 0x00020001,
RPI_FIRMWARE_GET_TIMING = 0x00020002,
RPI_FIRMWARE_SET_POWER_STATE = 0x00028001,
RPI_FIRMWARE_GET_CLOCK_STATE = 0x00030001,
RPI_FIRMWARE_GET_CLOCK_RATE = 0x00030002,
RPI_FIRMWARE_GET_VOLTAGE = 0x00030003,
RPI_FIRMWARE_GET_MAX_CLOCK_RATE = 0x00030004,
RPI_FIRMWARE_GET_MAX_VOLTAGE = 0x00030005,
RPI_FIRMWARE_GET_TEMPERATURE = 0x00030006,
RPI_FIRMWARE_GET_MIN_CLOCK_RATE = 0x00030007,
RPI_FIRMWARE_GET_MIN_VOLTAGE = 0x00030008,
RPI_FIRMWARE_GET_TURBO = 0x00030009,
RPI_FIRMWARE_GET_MAX_TEMPERATURE = 0x0003000a,
RPI_FIRMWARE_GET_STC = 0x0003000b,
RPI_FIRMWARE_ALLOCATE_MEMORY = 0x0003000c,
RPI_FIRMWARE_LOCK_MEMORY = 0x0003000d,
RPI_FIRMWARE_UNLOCK_MEMORY = 0x0003000e,
RPI_FIRMWARE_RELEASE_MEMORY = 0x0003000f,
RPI_FIRMWARE_EXECUTE_CODE = 0x00030010,
RPI_FIRMWARE_EXECUTE_QPU = 0x00030011,
RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012,
RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014,
RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020,
RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021,
RPI_FIRMWARE_GET_DOMAIN_STATE = 0x00030030,
RPI_FIRMWARE_GET_THROTTLED = 0x00030046,
RPI_FIRMWARE_GET_CLOCK_MEASURED = 0x00030047,
RPI_FIRMWARE_NOTIFY_REBOOT = 0x00030048,
RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001,
RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002,
RPI_FIRMWARE_SET_VOLTAGE = 0x00038003,
RPI_FIRMWARE_SET_TURBO = 0x00038009,
RPI_FIRMWARE_SET_CUSTOMER_OTP = 0x00038021,
RPI_FIRMWARE_SET_DOMAIN_STATE = 0x00038030,
RPI_FIRMWARE_GET_GPIO_STATE = 0x00030041,
RPI_FIRMWARE_SET_GPIO_STATE = 0x00038041,
RPI_FIRMWARE_SET_SDHOST_CLOCK = 0x00038042,
RPI_FIRMWARE_GET_GPIO_CONFIG = 0x00030043,
RPI_FIRMWARE_SET_GPIO_CONFIG = 0x00038043,
RPI_FIRMWARE_GET_PERIPH_REG = 0x00030045,
RPI_FIRMWARE_SET_PERIPH_REG = 0x00038045,
RPI_FIRMWARE_GET_POE_HAT_VAL = 0x00030049,
RPI_FIRMWARE_SET_POE_HAT_VAL = 0x00030050,
RPI_FIRMWARE_NOTIFY_XHCI_RESET = 0x00030058,
RPI_FIRMWARE_NOTIFY_DISPLAY_DONE = 0x00030066,
/* Dispmanx TAGS */
RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001,
RPI_FIRMWARE_FRAMEBUFFER_BLANK = 0x00040002,
RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
RPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 0x00040005,
RPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006,
RPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007,
RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 0x00040008,
RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009,
RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a,
RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 0x0004000b,
RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f,
RPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF = 0x00040010,
RPI_FIRMWARE_FRAMEBUFFER_RELEASE = 0x00048001,
RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
RPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 0x00044005,
RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006,
RPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007,
RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009,
RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a,
RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 0x0004400b,
RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 0x0004400e,
RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 0x00048005,
RPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006,
RPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007,
RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009,
RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a,
RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b,
RPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF = 0x0004801f,
RPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF = 0x00048020,
RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 0x0004800e,
RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT = 0x0004800f,
RPI_FIRMWARE_VCHIQ_INIT = 0x00048010,
RPI_FIRMWARE_GET_COMMAND_LINE = 0x00050001,
RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001,
};
enum rpi_firmware_clk_id {
RPI_FIRMWARE_EMMC_CLK_ID = 1,
RPI_FIRMWARE_UART_CLK_ID,
RPI_FIRMWARE_ARM_CLK_ID,
RPI_FIRMWARE_CORE_CLK_ID,
RPI_FIRMWARE_V3D_CLK_ID,
RPI_FIRMWARE_H264_CLK_ID,
RPI_FIRMWARE_ISP_CLK_ID,
RPI_FIRMWARE_SDRAM_CLK_ID,
RPI_FIRMWARE_PIXEL_CLK_ID,
RPI_FIRMWARE_PWM_CLK_ID,
RPI_FIRMWARE_HEVC_CLK_ID,
RPI_FIRMWARE_EMMC2_CLK_ID,
RPI_FIRMWARE_M2MC_CLK_ID,
RPI_FIRMWARE_PIXEL_BVB_CLK_ID,
RPI_FIRMWARE_VEC_CLK_ID,
RPI_FIRMWARE_DISP_CLK_ID,
RPI_FIRMWARE_NUM_CLK_ID,
};
enum rpi_firmware_volt_id {
RPI_FIRMWARE_VOLT_ID_CORE = 1,
RPI_FIRMWARE_VOLT_ID_SDRAM_C = 2,
RPI_FIRMWARE_VOLT_ID_SDRAM_P = 3,
RPI_FIRMWARE_VOLT_ID_SDRAM_I = 4,
RPI_FIRMWARE_NUM_VOLT_ID,
};
/**
* struct rpi_firmware_get_voltage_request - Firmware request for a voltage
* @id: ID of the voltage being queried
* @value: Voltage in microvolts. Set by the firmware.
*
* Used by @RPI_FIRMWARE_GET_VOLTAGE.
*/
struct rpi_firmware_get_voltage_request {
__le32 id;
__le32 value;
} __packed;
#define RPI_FIRMWARE_GET_VOLTAGE_REQUEST(_id) \
{ \
.id = cpu_to_le32(_id), \
}
/**
* struct rpi_firmware_clk_rate_request - Firmware Request for a rate
* @id: ID of the clock being queried
* @rate: Rate in Hertz. Set by the firmware.
*
* Used by @RPI_FIRMWARE_GET_CLOCK_RATE, @RPI_FIRMWARE_GET_CLOCK_MEASURED,
* @RPI_FIRMWARE_GET_MAX_CLOCK_RATE and @RPI_FIRMWARE_GET_MIN_CLOCK_RATE.
*/
struct rpi_firmware_clk_rate_request {
__le32 id;
__le32 rate;
} __packed;
#define RPI_FIRMWARE_CLK_RATE_REQUEST(_id) \
{ \
.id = cpu_to_le32(_id), \
}
#if IS_ENABLED(CONFIG_RASPBERRYPI_FIRMWARE)
int rpi_firmware_property(struct rpi_firmware *fw,
u32 tag, void *data, size_t len);
int rpi_firmware_property_list(struct rpi_firmware *fw,
void *data, size_t tag_size);
void rpi_firmware_put(struct rpi_firmware *fw);
unsigned int rpi_firmware_clk_get_max_rate(struct rpi_firmware *fw,
unsigned int id);
struct device_node *rpi_firmware_find_node(void);
struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node);
struct rpi_firmware *devm_rpi_firmware_get(struct device *dev,
struct device_node *firmware_node);
#else
static inline int rpi_firmware_property(struct rpi_firmware *fw, u32 tag,
void *data, size_t len)
{
return -ENOSYS;
}
static inline int rpi_firmware_property_list(struct rpi_firmware *fw,
void *data, size_t tag_size)
{
return -ENOSYS;
}
static inline void rpi_firmware_put(struct rpi_firmware *fw) { }
static inline unsigned int rpi_firmware_clk_get_max_rate(struct rpi_firmware *fw,
unsigned int id)
{
return UINT_MAX;
}
static inline struct device_node *rpi_firmware_find_node(void)
{
return NULL;
}
static inline struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)
{
return NULL;
}
static inline struct rpi_firmware *devm_rpi_firmware_get(struct device *dev,
struct device_node *firmware_node)
{
return NULL;
}
#endif
#endif /* __SOC_RASPBERRY_FIRMWARE_H__ */
linux-7.2.3/include/soc/canaan/k210-sysctl.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*/
#ifndef K210_SYSCTL_H
#define K210_SYSCTL_H
/*
* Kendryte K210 SoC system controller registers offsets.
* Taken from Kendryte SDK (kendryte-standalone-sdk).
*/
#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */
#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */
#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */
#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */
#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */
#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */
#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */
#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */
#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */
#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */
#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */
#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */
#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */
#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */
#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */
#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */
#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */
#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */
#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */
#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */
#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */
void k210_clk_early_init(void __iomem *regs);
#endif
linux-7.2.3/include/soc/fsl/bman.h
+145
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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_BMAN_H
#define __FSL_BMAN_H
/* wrapper for 48-bit buffers */
struct bm_buffer {
union {
struct {
__be16 bpid; /* hi 8-bits reserved */
__be16 hi; /* High 16-bits of 48-bit address */
__be32 lo; /* Low 32-bits of 48-bit address */
};
__be64 data;
};
} __aligned(8);
/*
* Restore the 48 bit address previously stored in BMan
* hardware pools as a dma_addr_t
*/
static inline dma_addr_t bm_buf_addr(const struct bm_buffer *buf)
{
return be64_to_cpu(buf->data) & 0xffffffffffffLLU;
}
static inline u64 bm_buffer_get64(const struct bm_buffer *buf)
{
return be64_to_cpu(buf->data) & 0xffffffffffffLLU;
}
static inline void bm_buffer_set64(struct bm_buffer *buf, u64 addr)
{
buf->hi = cpu_to_be16(upper_32_bits(addr));
buf->lo = cpu_to_be32(lower_32_bits(addr));
}
static inline u8 bm_buffer_get_bpid(const struct bm_buffer *buf)
{
return be16_to_cpu(buf->bpid) & 0xff;
}
static inline void bm_buffer_set_bpid(struct bm_buffer *buf, int bpid)
{
buf->bpid = cpu_to_be16(bpid & 0xff);
}
/* Managed portal, high-level i/face */
/* Portal and Buffer Pools */
struct bman_portal;
struct bman_pool;
#define BM_POOL_MAX 64 /* max # of buffer pools */
/**
* bman_new_pool - Allocates a Buffer Pool object
*
* Creates a pool object, and returns a reference to it or NULL on error.
*/
struct bman_pool *bman_new_pool(void);
/**
* bman_free_pool - Deallocates a Buffer Pool object
* @pool: the pool object to release
*/
void bman_free_pool(struct bman_pool *pool);
/**
* bman_get_bpid - Returns a pool object's BPID.
* @pool: the pool object
*
* The returned value is the index of the encapsulated buffer pool,
* in the range of [0, @BM_POOL_MAX-1].
*/
int bman_get_bpid(const struct bman_pool *pool);
/**
* bman_release - Release buffer(s) to the buffer pool
* @pool: the buffer pool object to release to
* @bufs: an array of buffers to release
* @num: the number of buffers in @bufs (1-8)
*
* Adds the given buffers to RCR entries. If the RCR ring is unresponsive,
* the function will return -ETIMEDOUT. Otherwise, it returns zero.
*/
int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num);
/**
* bman_acquire - Acquire buffer(s) from a buffer pool
* @pool: the buffer pool object to acquire from
* @bufs: array for storing the acquired buffers
* @num: the number of buffers desired (@bufs is at least this big)
*
* Issues an "Acquire" command via the portal's management command interface.
* The return value will be the number of buffers obtained from the pool, or a
* negative error code if a h/w error or pool starvation was encountered. In
* the latter case, the content of @bufs is undefined.
*/
int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num);
/**
* bman_is_probed - Check if bman is probed
*
* Returns 1 if the bman driver successfully probed, -1 if the bman driver
* failed to probe or 0 if the bman driver did not probed yet.
*/
int bman_is_probed(void);
/**
* bman_portals_probed - Check if all cpu bound bman portals are probed
*
* Returns 1 if all the required cpu bound bman portals successfully probed,
* -1 if probe errors appeared or 0 if the bman portals did not yet finished
* probing.
*/
int bman_portals_probed(void);
#endif /* __FSL_BMAN_H */
linux-7.2.3/include/soc/fsl/caam-blob.h
+129
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020 Pengutronix, Ahmad Fatoum <kernel@pengutronix.de>
* Copyright 2024-2025 NXP
*/
#ifndef __CAAM_BLOB_GEN
#define __CAAM_BLOB_GEN
#include <linux/types.h>
#include <linux/errno.h>
#define CAAM_BLOB_KEYMOD_LENGTH 16
#define CAAM_BLOB_OVERHEAD (32 + 16)
#define CAAM_BLOB_MAX_LEN 4096
#define CAAM_ENC_ALGO_CCM 0x1
#define CAAM_ENC_ALGO_ECB 0x2
#define CAAM_NONCE_SIZE 6
#define CAAM_ICV_SIZE 6
#define CAAM_CCM_OVERHEAD (CAAM_NONCE_SIZE + CAAM_ICV_SIZE)
struct caam_blob_priv;
/**
* struct caam_pkey_info - information for CAAM protected key
* @is_pkey: flag to identify, if the key is protected.
* @key_enc_algo: identifies the algorithm, ccm or ecb
* @plain_key_sz: size of plain key.
* @key_buf: contains key data
*/
struct caam_pkey_info {
u8 is_pkey;
u8 key_enc_algo;
u16 plain_key_sz;
u8 key_buf[];
} __packed;
/* sizeof struct caam_pkey_info */
#define CAAM_PKEY_HEADER 4
/**
* struct caam_blob_info - information for CAAM blobbing
* @pkey_info: pointer to keep protected key information
* @input: pointer to input buffer (must be DMAable)
* @input_len: length of @input buffer in bytes.
* @output: pointer to output buffer (must be DMAable)
* @output_len: length of @output buffer in bytes.
* @key_mod: key modifier
* @key_mod_len: length of @key_mod in bytes.
* May not exceed %CAAM_BLOB_KEYMOD_LENGTH
*/
struct caam_blob_info {
struct caam_pkey_info pkey_info;
void *input;
size_t input_len;
void *output;
size_t output_len;
const void *key_mod;
size_t key_mod_len;
};
/**
* caam_blob_gen_init - initialize blob generation
* Return: pointer to new &struct caam_blob_priv instance on success
* and ``ERR_PTR(-ENODEV)`` if CAAM has no hardware blobbing support
* or no job ring could be allocated.
*/
struct caam_blob_priv *caam_blob_gen_init(void);
/**
* caam_blob_gen_exit - free blob generation resources
* @priv: instance returned by caam_blob_gen_init()
*/
void caam_blob_gen_exit(struct caam_blob_priv *priv);
/**
* caam_process_blob - encapsulate or decapsulate blob
* @priv: instance returned by caam_blob_gen_init()
* @info: pointer to blobbing info describing key, blob and
* key modifier buffers.
* @encap: true for encapsulation, false for decapsulation
*
* Return: %0 and sets ``info->output_len`` on success and a negative
* error code otherwise.
*/
int caam_process_blob(struct caam_blob_priv *priv,
struct caam_blob_info *info, bool encap);
/**
* caam_encap_blob - encapsulate blob
* @priv: instance returned by caam_blob_gen_init()
* @info: pointer to blobbing info describing input key,
* output blob and key modifier buffers.
*
* Return: %0 and sets ``info->output_len`` on success and
* a negative error code otherwise.
*/
static inline int caam_encap_blob(struct caam_blob_priv *priv,
struct caam_blob_info *info)
{
if (info->output_len < info->input_len + CAAM_BLOB_OVERHEAD)
return -EINVAL;
return caam_process_blob(priv, info, true);
}
/**
* caam_decap_blob - decapsulate blob
* @priv: instance returned by caam_blob_gen_init()
* @info: pointer to blobbing info describing output key,
* input blob and key modifier buffers.
*
* Return: %0 and sets ``info->output_len`` on success and
* a negative error code otherwise.
*/
static inline int caam_decap_blob(struct caam_blob_priv *priv,
struct caam_blob_info *info)
{
if (info->input_len < CAAM_BLOB_OVERHEAD ||
info->output_len < info->input_len - CAAM_BLOB_OVERHEAD)
return -EINVAL;
return caam_process_blob(priv, info, false);
}
#endif
linux-7.2.3/include/soc/fsl/cpm.h
+171
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __CPM_H
#define __CPM_H
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/of.h>
#include <soc/fsl/qe/qe.h>
/*
* SPI Parameter RAM common to QE and CPM.
*/
struct spi_pram {
__be16 rbase; /* Rx Buffer descriptor base address */
__be16 tbase; /* Tx Buffer descriptor base address */
u8 rfcr; /* Rx function code */
u8 tfcr; /* Tx function code */
__be16 mrblr; /* Max receive buffer length */
__be32 rstate; /* Internal */
__be32 rdp; /* Internal */
__be16 rbptr; /* Internal */
__be16 rbc; /* Internal */
__be32 rxtmp; /* Internal */
__be32 tstate; /* Internal */
__be32 tdp; /* Internal */
__be16 tbptr; /* Internal */
__be16 tbc; /* Internal */
__be32 txtmp; /* Internal */
__be32 res; /* Tx temp. */
__be16 rpbase; /* Relocation pointer (CPM1 only) */
__be16 res1; /* Reserved */
};
/*
* USB Controller pram common to QE and CPM.
*/
struct usb_ctlr {
u8 usb_usmod;
u8 usb_usadr;
u8 usb_uscom;
u8 res1[1];
__be16 usb_usep[4];
u8 res2[4];
__be16 usb_usber;
u8 res3[2];
__be16 usb_usbmr;
u8 res4[1];
u8 usb_usbs;
/* Fields down below are QE-only */
__be16 usb_ussft;
u8 res5[2];
__be16 usb_usfrn;
u8 res6[0x22];
} __attribute__ ((packed));
/*
* Function code bits, usually generic to devices.
*/
#ifdef CONFIG_CPM1
#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
#else
#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
#endif
#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
/* Opcodes common to CPM1 and CPM2
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_SET_TIMER ((ushort)0x0008)
#define CPM_CR_STOP_IDMA ((ushort)0x000b)
/* Buffer descriptors used by many of the CPM protocols. */
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
/* Buffer descriptor control/status used by serial
*/
#define BD_SC_EMPTY (0x8000) /* Receive is empty */
#define BD_SC_READY (0x8000) /* Transmit is ready */
#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
#define BD_SC_LAST (0x0800) /* Last buffer in frame */
#define BD_SC_TC (0x0400) /* Transmit CRC */
#define BD_SC_CM (0x0200) /* Continuous mode */
#define BD_SC_ID (0x0100) /* Rec'd too many idles */
#define BD_SC_P (0x0100) /* xmt preamble */
#define BD_SC_BR (0x0020) /* Break received */
#define BD_SC_FR (0x0010) /* Framing error */
#define BD_SC_PR (0x0008) /* Parity error */
#define BD_SC_NAK (0x0004) /* NAK - did not respond */
#define BD_SC_OV (0x0002) /* Overrun */
#define BD_SC_UN (0x0002) /* Underrun */
#define BD_SC_CD (0x0001) /* */
#define BD_SC_CL (0x0001) /* Collision */
/* Buffer descriptor control/status used by Ethernet receive.
* Common to SCC and FCC.
*/
#define BD_ENET_RX_EMPTY (0x8000)
#define BD_ENET_RX_WRAP (0x2000)
#define BD_ENET_RX_INTR (0x1000)
#define BD_ENET_RX_LAST (0x0800)
#define BD_ENET_RX_FIRST (0x0400)
#define BD_ENET_RX_MISS (0x0100)
#define BD_ENET_RX_BC (0x0080) /* FCC Only */
#define BD_ENET_RX_MC (0x0040) /* FCC Only */
#define BD_ENET_RX_LG (0x0020)
#define BD_ENET_RX_NO (0x0010)
#define BD_ENET_RX_SH (0x0008)
#define BD_ENET_RX_CR (0x0004)
#define BD_ENET_RX_OV (0x0002)
#define BD_ENET_RX_CL (0x0001)
#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
* Common to SCC and FCC.
*/
#define BD_ENET_TX_READY (0x8000)
#define BD_ENET_TX_PAD (0x4000)
#define BD_ENET_TX_WRAP (0x2000)
#define BD_ENET_TX_INTR (0x1000)
#define BD_ENET_TX_LAST (0x0800)
#define BD_ENET_TX_TC (0x0400)
#define BD_ENET_TX_DEF (0x0200)
#define BD_ENET_TX_HB (0x0100)
#define BD_ENET_TX_LC (0x0080)
#define BD_ENET_TX_RL (0x0040)
#define BD_ENET_TX_RCMASK (0x003c)
#define BD_ENET_TX_UN (0x0002)
#define BD_ENET_TX_CSL (0x0001)
#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
/* Buffer descriptor control/status used by Transparent mode SCC.
*/
#define BD_SCC_TX_LAST (0x0800)
/* Buffer descriptor control/status used by I2C.
*/
#define BD_I2C_START (0x0400)
#ifdef CONFIG_CPM
int cpm_command(u32 command, u8 opcode);
#else
static inline int cpm_command(u32 command, u8 opcode)
{
return -ENOSYS;
}
#endif /* CONFIG_CPM */
int cpm2_gpiochip_add32(struct device *dev);
#endif
linux-7.2.3/include/soc/fsl/dcp.h
+20
View File
@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2021 sigma star gmbh
*
* Specifies paes key slot handles for NXP's DCP (Data Co-Processor) to be used
* with the crypto_skcipher_setkey().
*/
#ifndef MXS_DCP_H
#define MXS_DCP_H
#define DCP_PAES_KEYSIZE 1
#define DCP_PAES_KEY_SLOT0 0x00
#define DCP_PAES_KEY_SLOT1 0x01
#define DCP_PAES_KEY_SLOT2 0x02
#define DCP_PAES_KEY_SLOT3 0x03
#define DCP_PAES_KEY_UNIQUE 0xfe
#define DCP_PAES_KEY_OTP 0xff
#endif /* MXS_DCP_H */
linux-7.2.3/include/soc/fsl/dpaa2-fd.h
+681
View File
@@ -0,0 +1,681 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
*
*/
#ifndef __FSL_DPAA2_FD_H
#define __FSL_DPAA2_FD_H
#include <linux/byteorder/generic.h>
#include <linux/types.h>
/**
* DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
*
* Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
* Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
* by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
*
* There are three types of frames: single, scatter gather, and frame lists.
*
* The set of APIs in this file must be used to create, manipulate and
* query Frame Descriptors.
*/
/**
* struct dpaa2_fd - Struct describing FDs
* @words: for easier/faster copying the whole FD structure
* @addr: address in the FD
* @len: length in the FD
* @bpid: buffer pool ID
* @format_offset: format, offset, and short-length fields
* @frc: frame context
* @ctrl: control bits...including dd, sc, va, err, etc
* @flc: flow context address
*
* This structure represents the basic Frame Descriptor used in the system.
*/
struct dpaa2_fd {
union {
u32 words[8];
struct dpaa2_fd_simple {
__le64 addr;
__le32 len;
__le16 bpid;
__le16 format_offset;
__le32 frc;
__le32 ctrl;
__le64 flc;
} simple;
};
};
#define FD_SHORT_LEN_FLAG_MASK 0x1
#define FD_SHORT_LEN_FLAG_SHIFT 14
#define FD_SHORT_LEN_MASK 0x3FFFF
#define FD_OFFSET_MASK 0x0FFF
#define FD_FORMAT_MASK 0x3
#define FD_FORMAT_SHIFT 12
#define FD_BPID_MASK 0x3FFF
#define SG_SHORT_LEN_FLAG_MASK 0x1
#define SG_SHORT_LEN_FLAG_SHIFT 14
#define SG_SHORT_LEN_MASK 0x1FFFF
#define SG_OFFSET_MASK 0x0FFF
#define SG_FORMAT_MASK 0x3
#define SG_FORMAT_SHIFT 12
#define SG_BPID_MASK 0x3FFF
#define SG_FINAL_FLAG_MASK 0x1
#define SG_FINAL_FLAG_SHIFT 15
#define FL_SHORT_LEN_FLAG_MASK 0x1
#define FL_SHORT_LEN_FLAG_SHIFT 14
#define FL_SHORT_LEN_MASK 0x3FFFF
#define FL_OFFSET_MASK 0x0FFF
#define FL_FORMAT_MASK 0x3
#define FL_FORMAT_SHIFT 12
#define FL_BPID_MASK 0x3FFF
#define FL_FINAL_FLAG_MASK 0x1
#define FL_FINAL_FLAG_SHIFT 15
/* Error bits in FD CTRL */
#define FD_CTRL_ERR_MASK 0x000000FF
#define FD_CTRL_UFD 0x00000004
#define FD_CTRL_SBE 0x00000008
#define FD_CTRL_FLC 0x00000010
#define FD_CTRL_FSE 0x00000020
#define FD_CTRL_FAERR 0x00000040
/* Annotation bits in FD CTRL */
#define FD_CTRL_PTA 0x00800000
#define FD_CTRL_PTV1 0x00400000
enum dpaa2_fd_format {
dpaa2_fd_single = 0,
dpaa2_fd_list,
dpaa2_fd_sg
};
/**
* dpaa2_fd_get_addr() - get the addr field of frame descriptor
* @fd: the given frame descriptor
*
* Return the address in the frame descriptor.
*/
static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
{
return (dma_addr_t)le64_to_cpu(fd->simple.addr);
}
/**
* dpaa2_fd_set_addr() - Set the addr field of frame descriptor
* @fd: the given frame descriptor
* @addr: the address needs to be set in frame descriptor
*/
static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
{
fd->simple.addr = cpu_to_le64(addr);
}
/**
* dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
* @fd: the given frame descriptor
*
* Return the frame context field in the frame descriptor.
*/
static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
{
return le32_to_cpu(fd->simple.frc);
}
/**
* dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
* @fd: the given frame descriptor
* @frc: the frame context needs to be set in frame descriptor
*/
static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
{
fd->simple.frc = cpu_to_le32(frc);
}
/**
* dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
* @fd: the given frame descriptor
*
* Return the control bits field in the frame descriptor.
*/
static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
{
return le32_to_cpu(fd->simple.ctrl);
}
/**
* dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
* @fd: the given frame descriptor
* @ctrl: the control bits to be set in the frame descriptor
*/
static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
{
fd->simple.ctrl = cpu_to_le32(ctrl);
}
/**
* dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
* @fd: the given frame descriptor
*
* Return the flow context in the frame descriptor.
*/
static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
{
return (dma_addr_t)le64_to_cpu(fd->simple.flc);
}
/**
* dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
* @fd: the given frame descriptor
* @flc_addr: the flow context needs to be set in frame descriptor
*/
static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr)
{
fd->simple.flc = cpu_to_le64(flc_addr);
}
static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
{
return !!((le16_to_cpu(fd->simple.format_offset) >>
FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
}
/**
* dpaa2_fd_get_len() - Get the length in the frame descriptor
* @fd: the given frame descriptor
*
* Return the length field in the frame descriptor.
*/
static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
{
if (dpaa2_fd_short_len(fd))
return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
return le32_to_cpu(fd->simple.len);
}
/**
* dpaa2_fd_set_len() - Set the length field of frame descriptor
* @fd: the given frame descriptor
* @len: the length needs to be set in frame descriptor
*/
static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
{
fd->simple.len = cpu_to_le32(len);
}
/**
* dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
* @fd: the given frame descriptor
*
* Return the offset.
*/
static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
{
return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
}
/**
* dpaa2_fd_set_offset() - Set the offset field of frame descriptor
* @fd: the given frame descriptor
* @offset: the offset needs to be set in frame descriptor
*/
static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
{
fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
fd->simple.format_offset |= cpu_to_le16(offset);
}
/**
* dpaa2_fd_get_format() - Get the format field in the frame descriptor
* @fd: the given frame descriptor
*
* Return the format.
*/
static inline enum dpaa2_fd_format dpaa2_fd_get_format(
const struct dpaa2_fd *fd)
{
return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
>> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
}
/**
* dpaa2_fd_set_format() - Set the format field of frame descriptor
* @fd: the given frame descriptor
* @format: the format needs to be set in frame descriptor
*/
static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
enum dpaa2_fd_format format)
{
fd->simple.format_offset &=
cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
}
/**
* dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
* @fd: the given frame descriptor
*
* Return the buffer pool id.
*/
static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
{
return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
}
/**
* dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
* @fd: the given frame descriptor
* @bpid: buffer pool id to be set
*/
static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
{
fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
fd->simple.bpid |= cpu_to_le16(bpid);
}
/**
* struct dpaa2_sg_entry - the scatter-gathering structure
* @addr: address of the sg entry
* @len: length in this sg entry
* @bpid: buffer pool id
* @format_offset: format and offset fields
*/
struct dpaa2_sg_entry {
__le64 addr;
__le32 len;
__le16 bpid;
__le16 format_offset;
};
enum dpaa2_sg_format {
dpaa2_sg_single = 0,
dpaa2_sg_frame_data,
dpaa2_sg_sgt_ext
};
/* Accessors for SG entry fields */
/**
* dpaa2_sg_get_addr() - Get the address from SG entry
* @sg: the given scatter-gathering object
*
* Return the address.
*/
static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
{
return (dma_addr_t)le64_to_cpu(sg->addr);
}
/**
* dpaa2_sg_set_addr() - Set the address in SG entry
* @sg: the given scatter-gathering object
* @addr: the address to be set
*/
static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
{
sg->addr = cpu_to_le64(addr);
}
static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
{
return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
& SG_SHORT_LEN_FLAG_MASK);
}
/**
* dpaa2_sg_get_len() - Get the length in SG entry
* @sg: the given scatter-gathering object
*
* Return the length.
*/
static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
{
if (dpaa2_sg_short_len(sg))
return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
return le32_to_cpu(sg->len);
}
/**
* dpaa2_sg_set_len() - Set the length in SG entry
* @sg: the given scatter-gathering object
* @len: the length to be set
*/
static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
{
sg->len = cpu_to_le32(len);
}
/**
* dpaa2_sg_get_offset() - Get the offset in SG entry
* @sg: the given scatter-gathering object
*
* Return the offset.
*/
static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
{
return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
}
/**
* dpaa2_sg_set_offset() - Set the offset in SG entry
* @sg: the given scatter-gathering object
* @offset: the offset to be set
*/
static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
u16 offset)
{
sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
sg->format_offset |= cpu_to_le16(offset);
}
/**
* dpaa2_sg_get_format() - Get the SG format in SG entry
* @sg: the given scatter-gathering object
*
* Return the format.
*/
static inline enum dpaa2_sg_format
dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
{
return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
>> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
}
/**
* dpaa2_sg_set_format() - Set the SG format in SG entry
* @sg: the given scatter-gathering object
* @format: the format to be set
*/
static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
enum dpaa2_sg_format format)
{
sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
}
/**
* dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
* @sg: the given scatter-gathering object
*
* Return the bpid.
*/
static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
{
return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
}
/**
* dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
* @sg: the given scatter-gathering object
* @bpid: the bpid to be set
*/
static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
{
sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
sg->bpid |= cpu_to_le16(bpid);
}
/**
* dpaa2_sg_is_final() - Check final bit in SG entry
* @sg: the given scatter-gathering object
*
* Return bool.
*/
static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
{
return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
}
/**
* dpaa2_sg_set_final() - Set the final bit in SG entry
* @sg: the given scatter-gathering object
* @final: the final boolean to be set
*/
static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
{
sg->format_offset &= cpu_to_le16((~(SG_FINAL_FLAG_MASK
<< SG_FINAL_FLAG_SHIFT)) & 0xFFFF);
sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
}
/**
* struct dpaa2_fl_entry - structure for frame list entry.
* @addr: address in the FLE
* @len: length in the FLE
* @bpid: buffer pool ID
* @format_offset: format, offset, and short-length fields
* @frc: frame context
* @ctrl: control bits...including pta, pvt1, pvt2, err, etc
* @flc: flow context address
*/
struct dpaa2_fl_entry {
__le64 addr;
__le32 len;
__le16 bpid;
__le16 format_offset;
__le32 frc;
__le32 ctrl;
__le64 flc;
};
enum dpaa2_fl_format {
dpaa2_fl_single = 0,
dpaa2_fl_res,
dpaa2_fl_sg
};
/**
* dpaa2_fl_get_addr() - get the addr field of FLE
* @fle: the given frame list entry
*
* Return the address in the frame list entry.
*/
static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
{
return (dma_addr_t)le64_to_cpu(fle->addr);
}
/**
* dpaa2_fl_set_addr() - Set the addr field of FLE
* @fle: the given frame list entry
* @addr: the address needs to be set in frame list entry
*/
static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
dma_addr_t addr)
{
fle->addr = cpu_to_le64(addr);
}
/**
* dpaa2_fl_get_frc() - Get the frame context in the FLE
* @fle: the given frame list entry
*
* Return the frame context field in the frame lsit entry.
*/
static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
{
return le32_to_cpu(fle->frc);
}
/**
* dpaa2_fl_set_frc() - Set the frame context in the FLE
* @fle: the given frame list entry
* @frc: the frame context needs to be set in frame list entry
*/
static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
{
fle->frc = cpu_to_le32(frc);
}
/**
* dpaa2_fl_get_ctrl() - Get the control bits in the FLE
* @fle: the given frame list entry
*
* Return the control bits field in the frame list entry.
*/
static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
{
return le32_to_cpu(fle->ctrl);
}
/**
* dpaa2_fl_set_ctrl() - Set the control bits in the FLE
* @fle: the given frame list entry
* @ctrl: the control bits to be set in the frame list entry
*/
static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
{
fle->ctrl = cpu_to_le32(ctrl);
}
/**
* dpaa2_fl_get_flc() - Get the flow context in the FLE
* @fle: the given frame list entry
*
* Return the flow context in the frame list entry.
*/
static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
{
return (dma_addr_t)le64_to_cpu(fle->flc);
}
/**
* dpaa2_fl_set_flc() - Set the flow context field of FLE
* @fle: the given frame list entry
* @flc_addr: the flow context needs to be set in frame list entry
*/
static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
dma_addr_t flc_addr)
{
fle->flc = cpu_to_le64(flc_addr);
}
static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
{
return !!((le16_to_cpu(fle->format_offset) >>
FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
}
/**
* dpaa2_fl_get_len() - Get the length in the FLE
* @fle: the given frame list entry
*
* Return the length field in the frame list entry.
*/
static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
{
if (dpaa2_fl_short_len(fle))
return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
return le32_to_cpu(fle->len);
}
/**
* dpaa2_fl_set_len() - Set the length field of FLE
* @fle: the given frame list entry
* @len: the length needs to be set in frame list entry
*/
static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
{
fle->len = cpu_to_le32(len);
}
/**
* dpaa2_fl_get_offset() - Get the offset field in the frame list entry
* @fle: the given frame list entry
*
* Return the offset.
*/
static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
{
return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
}
/**
* dpaa2_fl_set_offset() - Set the offset field of FLE
* @fle: the given frame list entry
* @offset: the offset needs to be set in frame list entry
*/
static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
{
fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
fle->format_offset |= cpu_to_le16(offset);
}
/**
* dpaa2_fl_get_format() - Get the format field in the FLE
* @fle: the given frame list entry
*
* Return the format.
*/
static inline enum dpaa2_fl_format dpaa2_fl_get_format(const struct dpaa2_fl_entry *fle)
{
return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
}
/**
* dpaa2_fl_set_format() - Set the format field of FLE
* @fle: the given frame list entry
* @format: the format needs to be set in frame list entry
*/
static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
enum dpaa2_fl_format format)
{
fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
}
/**
* dpaa2_fl_get_bpid() - Get the bpid field in the FLE
* @fle: the given frame list entry
*
* Return the buffer pool id.
*/
static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
{
return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
}
/**
* dpaa2_fl_set_bpid() - Set the bpid field of FLE
* @fle: the given frame list entry
* @bpid: buffer pool id to be set
*/
static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
{
fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
fle->bpid |= cpu_to_le16(bpid);
}
/**
* dpaa2_fl_is_final() - Check final bit in FLE
* @fle: the given frame list entry
*
* Return bool.
*/
static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
{
return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
}
/**
* dpaa2_fl_set_final() - Set the final bit in FLE
* @fle: the given frame list entry
* @final: the final boolean to be set
*/
static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
{
fle->format_offset &= cpu_to_le16((~(FL_FINAL_FLAG_MASK <<
FL_FINAL_FLAG_SHIFT)) & 0xFFFF);
fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
}
#endif /* __FSL_DPAA2_FD_H */
linux-7.2.3/include/soc/fsl/dpaa2-global.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
*
*/
#ifndef __FSL_DPAA2_GLOBAL_H
#define __FSL_DPAA2_GLOBAL_H
#include <linux/types.h>
#include <linux/cpumask.h>
#include "dpaa2-fd.h"
struct dpaa2_dq {
union {
struct common {
u8 verb;
u8 reserved[63];
} common;
struct dq {
u8 verb;
u8 stat;
__le16 seqnum;
__le16 oprid;
u8 reserved;
u8 tok;
__le32 fqid;
u32 reserved2;
__le32 fq_byte_cnt;
__le32 fq_frm_cnt;
__le64 fqd_ctx;
u8 fd[32];
} dq;
struct scn {
u8 verb;
u8 stat;
u8 state;
u8 reserved;
__le32 rid_tok;
__le64 ctx;
} scn;
};
};
/* Parsing frame dequeue results */
/* FQ empty */
#define DPAA2_DQ_STAT_FQEMPTY 0x80
/* FQ held active */
#define DPAA2_DQ_STAT_HELDACTIVE 0x40
/* FQ force eligible */
#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
/* valid frame */
#define DPAA2_DQ_STAT_VALIDFRAME 0x10
/* FQ ODP enable */
#define DPAA2_DQ_STAT_ODPVALID 0x04
/* volatile dequeue */
#define DPAA2_DQ_STAT_VOLATILE 0x02
/* volatile dequeue command is expired */
#define DPAA2_DQ_STAT_EXPIRED 0x01
#define DQ_FQID_MASK 0x00FFFFFF
#define DQ_FRAME_COUNT_MASK 0x00FFFFFF
/**
* dpaa2_dq_flags() - Get the stat field of dequeue response
* @dq: the dequeue result.
*/
static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
{
return dq->dq.stat;
}
/**
* dpaa2_dq_is_pull() - Check whether the dq response is from a pull
* command.
* @dq: the dequeue result
*
* Return 1 for volatile(pull) dequeue, 0 for static dequeue.
*/
static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
{
return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
}
/**
* dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
* @dq: the dequeue result
*
* Return boolean.
*/
static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
{
return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
}
/**
* dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
* @dq: the dequeue result
*
* seqnum is valid only if VALIDFRAME flag is TRUE
*
* Return seqnum.
*/
static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
{
return le16_to_cpu(dq->dq.seqnum);
}
/**
* dpaa2_dq_odpid() - Get the odpid field in dequeue response
* @dq: the dequeue result
*
* odpid is valid only if ODPVALID flag is TRUE.
*
* Return odpid.
*/
static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
{
return le16_to_cpu(dq->dq.oprid);
}
/**
* dpaa2_dq_fqid() - Get the fqid in dequeue response
* @dq: the dequeue result
*
* Return fqid.
*/
static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
{
return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
}
/**
* dpaa2_dq_byte_count() - Get the byte count in dequeue response
* @dq: the dequeue result
*
* Return the byte count remaining in the FQ.
*/
static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
{
return le32_to_cpu(dq->dq.fq_byte_cnt);
}
/**
* dpaa2_dq_frame_count() - Get the frame count in dequeue response
* @dq: the dequeue result
*
* Return the frame count remaining in the FQ.
*/
static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
{
return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
}
/**
* dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
* @dq: the dequeue result
*
* Return the frame queue context.
*/
static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
{
return le64_to_cpu(dq->dq.fqd_ctx);
}
/**
* dpaa2_dq_fd() - Get the frame descriptor in dequeue response
* @dq: the dequeue result
*
* Return the frame descriptor.
*/
static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
{
return (const struct dpaa2_fd *)&dq->dq.fd[0];
}
#define DPAA2_CSCN_SIZE sizeof(struct dpaa2_dq)
#define DPAA2_CSCN_ALIGN 16
#define DPAA2_CSCN_STATE_CG BIT(0)
/**
* dpaa2_cscn_state_congested() - Check congestion state
* @cscn: congestion SCN (delivered to WQ or memory)
*
i * Return true is congested.
*/
static inline bool dpaa2_cscn_state_congested(struct dpaa2_dq *cscn)
{
return !!(cscn->scn.state & DPAA2_CSCN_STATE_CG);
}
#endif /* __FSL_DPAA2_GLOBAL_H */
linux-7.2.3/include/soc/fsl/dpaa2-io.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2017-2019 NXP
*
*/
#ifndef __FSL_DPAA2_IO_H
#define __FSL_DPAA2_IO_H
#include <linux/types.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>
#include "dpaa2-fd.h"
#include "dpaa2-global.h"
struct dpaa2_io;
struct dpaa2_io_store;
struct device;
/**
* DOC: DPIO Service
*
* The DPIO service provides APIs for users to interact with the datapath
* by enqueueing and dequeing frame descriptors.
*
* The following set of APIs can be used to enqueue and dequeue frames
* as well as producing notification callbacks when data is available
* for dequeue.
*/
#define DPAA2_IO_ANY_CPU -1
/**
* struct dpaa2_io_desc - The DPIO descriptor
* @receives_notifications: Use notificaton mode. Non-zero if the DPIO
* has a channel.
* @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
* unless receives_notification is TRUE.
* @cpu: The cpu index that at least interrupt handlers will
* execute on.
* @stash_affinity: The stash affinity for this portal favour 'cpu'
* @regs_cena: The cache enabled regs.
* @regs_cinh: The cache inhibited regs
* @dpio_id: The dpio index
* @qman_version: The qman version
* @qman_clk: The qman clock frequency in Hz
*
* Describes the attributes and features of the DPIO object.
*/
struct dpaa2_io_desc {
int receives_notifications;
int has_8prio;
int cpu;
void *regs_cena;
void __iomem *regs_cinh;
int dpio_id;
u32 qman_version;
u32 qman_clk;
};
struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc,
struct device *dev);
void dpaa2_io_down(struct dpaa2_io *d);
irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
struct dpaa2_io *dpaa2_io_service_select(int cpu);
/**
* struct dpaa2_io_notification_ctx - The DPIO notification context structure
* @cb: The callback to be invoked when the notification arrives
* @is_cdan: Zero for FQDAN, non-zero for CDAN
* @id: FQID or channel ID, needed for rearm
* @desired_cpu: The cpu on which the notifications will show up. Use
* DPAA2_IO_ANY_CPU if don't care
* @dpio_id: The dpio index
* @qman64: The 64-bit context value shows up in the FQDAN/CDAN.
* @node: The list node
* @dpio_private: The dpio object internal to dpio_service
*
* Used when a FQDAN/CDAN registration is made by drivers.
*/
struct dpaa2_io_notification_ctx {
void (*cb)(struct dpaa2_io_notification_ctx *ctx);
int is_cdan;
u32 id;
int desired_cpu;
int dpio_id;
u64 qman64;
struct list_head node;
void *dpio_private;
};
int dpaa2_io_get_cpu(struct dpaa2_io *d);
int dpaa2_io_service_register(struct dpaa2_io *service,
struct dpaa2_io_notification_ctx *ctx,
struct device *dev);
void dpaa2_io_service_deregister(struct dpaa2_io *service,
struct dpaa2_io_notification_ctx *ctx,
struct device *dev);
int dpaa2_io_service_rearm(struct dpaa2_io *service,
struct dpaa2_io_notification_ctx *ctx);
int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
struct dpaa2_io_store *s);
int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
struct dpaa2_io_store *s);
int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
const struct dpaa2_fd *fd);
int dpaa2_io_service_enqueue_multiple_fq(struct dpaa2_io *d, u32 fqid,
const struct dpaa2_fd *fd, int number_of_frame);
int dpaa2_io_service_enqueue_multiple_desc_fq(struct dpaa2_io *d, u32 *fqid,
const struct dpaa2_fd *fd, int number_of_frame);
int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
u16 qdbin, const struct dpaa2_fd *fd);
int dpaa2_io_service_release(struct dpaa2_io *d, u16 bpid,
const u64 *buffers, unsigned int num_buffers);
int dpaa2_io_service_acquire(struct dpaa2_io *d, u16 bpid,
u64 *buffers, unsigned int num_buffers);
struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
struct device *dev);
void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
u32 *fcnt, u32 *bcnt);
int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid,
u32 *num);
int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff);
void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff);
void dpaa2_io_set_adaptive_coalescing(struct dpaa2_io *d,
int use_adaptive_rx_coalesce);
int dpaa2_io_get_adaptive_coalescing(struct dpaa2_io *d);
void dpaa2_io_update_net_dim(struct dpaa2_io *d, __u64 frames, __u64 bytes);
#endif /* __FSL_DPAA2_IO_H */
linux-7.2.3/include/soc/fsl/phy-fsl-lynx.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright 2023-2026 NXP */
#ifndef __PHY_FSL_LYNX_H_
#define __PHY_FSL_LYNX_H_
enum lynx_lane_mode {
LANE_MODE_UNKNOWN,
LANE_MODE_1000BASEX_SGMII,
LANE_MODE_2500BASEX,
LANE_MODE_QSGMII,
LANE_MODE_10G_QXGMII,
LANE_MODE_10GBASER,
LANE_MODE_USXGMII,
LANE_MODE_25GBASER,
LANE_MODE_MAX,
};
static inline bool lynx_lane_mode_uses_gmii_mac(enum lynx_lane_mode mode)
{
switch (mode) {
case LANE_MODE_1000BASEX_SGMII:
case LANE_MODE_2500BASEX:
case LANE_MODE_QSGMII:
case LANE_MODE_10G_QXGMII:
return true;
default:
return false;
}
}
static inline bool lynx_lane_mode_uses_xgmii_mac(enum lynx_lane_mode mode)
{
switch (mode) {
case LANE_MODE_10GBASER:
case LANE_MODE_USXGMII:
return true;
default:
return false;
}
}
#endif /* __PHY_FSL_LYNX_H_ */
linux-7.2.3/include/soc/fsl/qe/immap_qe.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QUICC Engine (QE) Internal Memory Map.
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
* Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com>
*/
#ifndef _ASM_POWERPC_IMMAP_QE_H
#define _ASM_POWERPC_IMMAP_QE_H
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/io.h>
#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
/* QE I-RAM */
struct qe_iram {
__be32 iadd; /* I-RAM Address Register */
__be32 idata; /* I-RAM Data Register */
u8 res0[0x04];
__be32 iready; /* I-RAM Ready Register */
u8 res1[0x70];
} __attribute__ ((packed));
/* QE Interrupt Controller */
struct qe_ic_regs {
__be32 qicr;
__be32 qivec;
__be32 qripnr;
__be32 qipnr;
__be32 qipxcc;
__be32 qipycc;
__be32 qipwcc;
__be32 qipzcc;
__be32 qimr;
__be32 qrimr;
__be32 qicnr;
u8 res0[0x4];
__be32 qiprta;
__be32 qiprtb;
u8 res1[0x4];
__be32 qricr;
u8 res2[0x20];
__be32 qhivec;
u8 res3[0x1C];
} __attribute__ ((packed));
/* Communications Processor */
struct cp_qe {
__be32 cecr; /* QE command register */
__be32 ceccr; /* QE controller configuration register */
__be32 cecdr; /* QE command data register */
u8 res0[0xA];
__be16 ceter; /* QE timer event register */
u8 res1[0x2];
__be16 cetmr; /* QE timers mask register */
__be32 cetscr; /* QE time-stamp timer control register */
__be32 cetsr1; /* QE time-stamp register 1 */
__be32 cetsr2; /* QE time-stamp register 2 */
u8 res2[0x8];
__be32 cevter; /* QE virtual tasks event register */
__be32 cevtmr; /* QE virtual tasks mask register */
__be16 cercr; /* QE RAM control register */
u8 res3[0x2];
u8 res4[0x24];
__be16 ceexe1; /* QE external request 1 event register */
u8 res5[0x2];
__be16 ceexm1; /* QE external request 1 mask register */
u8 res6[0x2];
__be16 ceexe2; /* QE external request 2 event register */
u8 res7[0x2];
__be16 ceexm2; /* QE external request 2 mask register */
u8 res8[0x2];
__be16 ceexe3; /* QE external request 3 event register */
u8 res9[0x2];
__be16 ceexm3; /* QE external request 3 mask register */
u8 res10[0x2];
__be16 ceexe4; /* QE external request 4 event register */
u8 res11[0x2];
__be16 ceexm4; /* QE external request 4 mask register */
u8 res12[0x3A];
__be32 ceurnr; /* QE microcode revision number register */
u8 res13[0x244];
} __attribute__ ((packed));
/* QE Multiplexer */
struct qe_mux {
__be32 cmxgcr; /* CMX general clock route register */
__be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
__be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
__be32 cmxsi1syr; /* CMX SI1 SYNC route register */
__be32 cmxucr[4]; /* CMX UCCx clock route registers */
__be32 cmxupcr; /* CMX UPC clock route register */
u8 res0[0x1C];
} __attribute__ ((packed));
/* QE Timers */
struct qe_timers {
u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
u8 res0[0x3];
u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
u8 res1[0xB];
__be16 gtmdr1; /* Timer 1 mode register */
__be16 gtmdr2; /* Timer 2 mode register */
__be16 gtrfr1; /* Timer 1 reference register */
__be16 gtrfr2; /* Timer 2 reference register */
__be16 gtcpr1; /* Timer 1 capture register */
__be16 gtcpr2; /* Timer 2 capture register */
__be16 gtcnr1; /* Timer 1 counter */
__be16 gtcnr2; /* Timer 2 counter */
__be16 gtmdr3; /* Timer 3 mode register */
__be16 gtmdr4; /* Timer 4 mode register */
__be16 gtrfr3; /* Timer 3 reference register */
__be16 gtrfr4; /* Timer 4 reference register */
__be16 gtcpr3; /* Timer 3 capture register */
__be16 gtcpr4; /* Timer 4 capture register */
__be16 gtcnr3; /* Timer 3 counter */
__be16 gtcnr4; /* Timer 4 counter */
__be16 gtevr1; /* Timer 1 event register */
__be16 gtevr2; /* Timer 2 event register */
__be16 gtevr3; /* Timer 3 event register */
__be16 gtevr4; /* Timer 4 event register */
__be16 gtps; /* Timer 1 prescale register */
u8 res2[0x46];
} __attribute__ ((packed));
/* BRG */
struct qe_brg {
__be32 brgc[16]; /* BRG configuration registers */
u8 res0[0x40];
} __attribute__ ((packed));
/* SPI */
struct spi {
u8 res0[0x20];
__be32 spmode; /* SPI mode register */
u8 res1[0x2];
u8 spie; /* SPI event register */
u8 res2[0x1];
u8 res3[0x2];
u8 spim; /* SPI mask register */
u8 res4[0x1];
u8 res5[0x1];
u8 spcom; /* SPI command register */
u8 res6[0x2];
__be32 spitd; /* SPI transmit data register (cpu mode) */
__be32 spird; /* SPI receive data register (cpu mode) */
u8 res7[0x8];
} __attribute__ ((packed));
/* SI */
struct si1 {
__be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */
u8 siglmr1_h; /* SI1 global mode register high */
u8 res0[0x1];
u8 sicmdr1_h; /* SI1 command register high */
u8 res2[0x1];
u8 sistr1_h; /* SI1 status register high */
u8 res3[0x1];
__be16 sirsr1_h; /* SI1 RAM shadow address register high */
u8 sitarc1; /* SI1 RAM counter Tx TDMA */
u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
u8 sirarc1; /* SI1 RAM counter Rx TDMA */
u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
u8 sircrc1; /* SI1 RAM counter Rx TDMC */
u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
u8 res4[0x8];
__be16 siemr1; /* SI1 TDME mode register 16 bits */
__be16 sifmr1; /* SI1 TDMF mode register 16 bits */
__be16 sigmr1; /* SI1 TDMG mode register 16 bits */
__be16 sihmr1; /* SI1 TDMH mode register 16 bits */
u8 siglmg1_l; /* SI1 global mode register low 8 bits */
u8 res5[0x1];
u8 sicmdr1_l; /* SI1 command register low 8 bits */
u8 res6[0x1];
u8 sistr1_l; /* SI1 status register low 8 bits */
u8 res7[0x1];
__be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
u8 res8[0x8];
__be32 siml1; /* SI1 multiframe limit register */
u8 siedm1; /* SI1 extended diagnostic mode register */
u8 res9[0xBB];
} __attribute__ ((packed));
/* SI Routing Tables */
struct sir {
u8 tx[0x400];
u8 rx[0x400];
u8 res0[0x800];
} __attribute__ ((packed));
/* USB Controller */
struct qe_usb_ctlr {
u8 usb_usmod;
u8 usb_usadr;
u8 usb_uscom;
u8 res1[1];
__be16 usb_usep[4];
u8 res2[4];
__be16 usb_usber;
u8 res3[2];
__be16 usb_usbmr;
u8 res4[1];
u8 usb_usbs;
__be16 usb_ussft;
u8 res5[2];
__be16 usb_usfrn;
u8 res6[0x22];
} __attribute__ ((packed));
/* MCC */
struct qe_mcc {
__be32 mcce; /* MCC event register */
__be32 mccm; /* MCC mask register */
__be32 mccf; /* MCC configuration register */
__be32 merl; /* MCC emergency request level register */
u8 res0[0xF0];
} __attribute__ ((packed));
/* QE UCC Slow */
struct ucc_slow {
__be32 gumr_l; /* UCCx general mode register (low) */
__be32 gumr_h; /* UCCx general mode register (high) */
__be16 upsmr; /* UCCx protocol-specific mode register */
u8 res0[0x2];
__be16 utodr; /* UCCx transmit on demand register */
__be16 udsr; /* UCCx data synchronization register */
__be16 ucce; /* UCCx event register */
u8 res1[0x2];
__be16 uccm; /* UCCx mask register */
u8 res2[0x1];
u8 uccs; /* UCCx status register */
u8 res3[0x24];
__be16 utpt;
u8 res4[0x52];
u8 guemr; /* UCC general extended mode register */
} __attribute__ ((packed));
/* QE UCC Fast */
struct ucc_fast {
__be32 gumr; /* UCCx general mode register */
__be32 upsmr; /* UCCx protocol-specific mode register */
__be16 utodr; /* UCCx transmit on demand register */
u8 res0[0x2];
__be16 udsr; /* UCCx data synchronization register */
u8 res1[0x2];
__be32 ucce; /* UCCx event register */
__be32 uccm; /* UCCx mask register */
u8 uccs; /* UCCx status register */
u8 res2[0x7];
__be32 urfb; /* UCC receive FIFO base */
__be16 urfs; /* UCC receive FIFO size */
u8 res3[0x2];
__be16 urfet; /* UCC receive FIFO emergency threshold */
__be16 urfset; /* UCC receive FIFO special emergency
threshold */
__be32 utfb; /* UCC transmit FIFO base */
__be16 utfs; /* UCC transmit FIFO size */
u8 res4[0x2];
__be16 utfet; /* UCC transmit FIFO emergency threshold */
u8 res5[0x2];
__be16 utftt; /* UCC transmit FIFO transmit threshold */
u8 res6[0x2];
__be16 utpt; /* UCC transmit polling timer */
u8 res7[0x2];
__be32 urtry; /* UCC retry counter register */
u8 res8[0x4C];
u8 guemr; /* UCC general extended mode register */
} __attribute__ ((packed));
struct ucc {
union {
struct ucc_slow slow;
struct ucc_fast fast;
u8 res[0x200]; /* UCC blocks are 512 bytes each */
};
} __attribute__ ((packed));
/* MultiPHY UTOPIA POS Controllers (UPC) */
struct upc {
__be32 upgcr; /* UTOPIA/POS general configuration register */
__be32 uplpa; /* UTOPIA/POS last PHY address */
__be32 uphec; /* ATM HEC register */
__be32 upuc; /* UTOPIA/POS UCC configuration */
__be32 updc1; /* UTOPIA/POS device 1 configuration */
__be32 updc2; /* UTOPIA/POS device 2 configuration */
__be32 updc3; /* UTOPIA/POS device 3 configuration */
__be32 updc4; /* UTOPIA/POS device 4 configuration */
__be32 upstpa; /* UTOPIA/POS STPA threshold */
u8 res0[0xC];
__be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
__be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
__be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
__be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
__be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
__be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
__be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
__be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
__be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
__be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
__be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
__be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
__be32 upde1; /* UTOPIA/POS device 1 event */
__be32 upde2; /* UTOPIA/POS device 2 event */
__be32 upde3; /* UTOPIA/POS device 3 event */
__be32 upde4; /* UTOPIA/POS device 4 event */
__be16 uprp1;
__be16 uprp2;
__be16 uprp3;
__be16 uprp4;
u8 res1[0x8];
__be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
__be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
__be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
__be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
__be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
__be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
__be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
__be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
__be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
__be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
__be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
__be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
__be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
__be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
__be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
__be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
__be32 uper1; /* Device 1 port enable register */
__be32 uper2; /* Device 2 port enable register */
__be32 uper3; /* Device 3 port enable register */
__be32 uper4; /* Device 4 port enable register */
u8 res2[0x150];
} __attribute__ ((packed));
/* SDMA */
struct sdma {
__be32 sdsr; /* Serial DMA status register */
__be32 sdmr; /* Serial DMA mode register */
__be32 sdtr1; /* SDMA system bus threshold register */
__be32 sdtr2; /* SDMA secondary bus threshold register */
__be32 sdhy1; /* SDMA system bus hysteresis register */
__be32 sdhy2; /* SDMA secondary bus hysteresis register */
__be32 sdta1; /* SDMA system bus address register */
__be32 sdta2; /* SDMA secondary bus address register */
__be32 sdtm1; /* SDMA system bus MSNUM register */
__be32 sdtm2; /* SDMA secondary bus MSNUM register */
u8 res0[0x10];
__be32 sdaqr; /* SDMA address bus qualify register */
__be32 sdaqmr; /* SDMA address bus qualify mask register */
u8 res1[0x4];
__be32 sdebcr; /* SDMA CAM entries base register */
u8 res2[0x38];
} __attribute__ ((packed));
/* Debug Space */
struct dbg {
__be32 bpdcr; /* Breakpoint debug command register */
__be32 bpdsr; /* Breakpoint debug status register */
__be32 bpdmr; /* Breakpoint debug mask register */
__be32 bprmrr0; /* Breakpoint request mode risc register 0 */
__be32 bprmrr1; /* Breakpoint request mode risc register 1 */
u8 res0[0x8];
__be32 bprmtr0; /* Breakpoint request mode trb register 0 */
__be32 bprmtr1; /* Breakpoint request mode trb register 1 */
u8 res1[0x8];
__be32 bprmir; /* Breakpoint request mode immediate register */
__be32 bprmsr; /* Breakpoint request mode serial register */
__be32 bpemr; /* Breakpoint exit mode register */
u8 res2[0x48];
} __attribute__ ((packed));
/*
* RISC Special Registers (Trap and Breakpoint). These are described in
* the QE Developer's Handbook.
*/
struct rsp {
__be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
u8 res0[64];
__be32 ibcr0;
__be32 ibs0;
__be32 ibcnr0;
u8 res1[4];
__be32 ibcr1;
__be32 ibs1;
__be32 ibcnr1;
__be32 npcr;
__be32 dbcr;
__be32 dbar;
__be32 dbamr;
__be32 dbsr;
__be32 dbcnr;
u8 res2[12];
__be32 dbdr_h;
__be32 dbdr_l;
__be32 dbdmr_h;
__be32 dbdmr_l;
__be32 bsr;
__be32 bor;
__be32 bior;
u8 res3[4];
__be32 iatr[4];
__be32 eccr; /* Exception control configuration register */
__be32 eicr;
u8 res4[0x100-0xf8];
} __attribute__ ((packed));
struct qe_immap {
struct qe_iram iram; /* I-RAM */
struct qe_ic_regs ic; /* Interrupt Controller */
struct cp_qe cp; /* Communications Processor */
struct qe_mux qmx; /* QE Multiplexer */
struct qe_timers qet; /* QE Timers */
struct spi spi[0x2]; /* spi */
struct qe_mcc mcc; /* mcc */
struct qe_brg brg; /* brg */
struct qe_usb_ctlr usb; /* USB */
struct si1 si1; /* SI */
u8 res11[0x800];
struct sir sir; /* SI Routing Tables */
struct ucc ucc1; /* ucc1 */
struct ucc ucc3; /* ucc3 */
struct ucc ucc5; /* ucc5 */
struct ucc ucc7; /* ucc7 */
u8 res12[0x600];
struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
struct ucc ucc2; /* ucc2 */
struct ucc ucc4; /* ucc4 */
struct ucc ucc6; /* ucc6 */
struct ucc ucc8; /* ucc8 */
u8 res13[0x600];
struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
struct sdma sdma; /* SDMA */
struct dbg dbg; /* 0x104080 - 0x1040FF
Debug Space */
struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
RISC Special Registers
(Trap and Breakpoint) */
u8 res14[0x300]; /* 0x104300 - 0x1045FF */
u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
u8 muram[0xC000]; /* 0x110000 - 0x11C000
Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
} __attribute__ ((packed));
extern struct qe_immap __iomem *qe_immr;
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_IMMAP_QE_H */
linux-7.2.3/include/soc/fsl/qe/qe.h
+833
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@@ -0,0 +1,833 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com>
*
* Description:
* QUICC Engine (QE) external definitions and structure.
*/
#ifndef _ASM_POWERPC_QE_H
#define _ASM_POWERPC_QE_H
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <linux/genalloc.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <soc/fsl/cpm.h>
#include <soc/fsl/qe/immap_qe.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/types.h>
struct device;
#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
#define QE_NUM_OF_BRGS 16
#define QE_NUM_OF_PORTS 1024
/* Clocks and BRGs */
enum qe_clock {
QE_CLK_NONE = 0,
QE_BRG1, /* Baud Rate Generator 1 */
QE_BRG2, /* Baud Rate Generator 2 */
QE_BRG3, /* Baud Rate Generator 3 */
QE_BRG4, /* Baud Rate Generator 4 */
QE_BRG5, /* Baud Rate Generator 5 */
QE_BRG6, /* Baud Rate Generator 6 */
QE_BRG7, /* Baud Rate Generator 7 */
QE_BRG8, /* Baud Rate Generator 8 */
QE_BRG9, /* Baud Rate Generator 9 */
QE_BRG10, /* Baud Rate Generator 10 */
QE_BRG11, /* Baud Rate Generator 11 */
QE_BRG12, /* Baud Rate Generator 12 */
QE_BRG13, /* Baud Rate Generator 13 */
QE_BRG14, /* Baud Rate Generator 14 */
QE_BRG15, /* Baud Rate Generator 15 */
QE_BRG16, /* Baud Rate Generator 16 */
QE_CLK1, /* Clock 1 */
QE_CLK2, /* Clock 2 */
QE_CLK3, /* Clock 3 */
QE_CLK4, /* Clock 4 */
QE_CLK5, /* Clock 5 */
QE_CLK6, /* Clock 6 */
QE_CLK7, /* Clock 7 */
QE_CLK8, /* Clock 8 */
QE_CLK9, /* Clock 9 */
QE_CLK10, /* Clock 10 */
QE_CLK11, /* Clock 11 */
QE_CLK12, /* Clock 12 */
QE_CLK13, /* Clock 13 */
QE_CLK14, /* Clock 14 */
QE_CLK15, /* Clock 15 */
QE_CLK16, /* Clock 16 */
QE_CLK17, /* Clock 17 */
QE_CLK18, /* Clock 18 */
QE_CLK19, /* Clock 19 */
QE_CLK20, /* Clock 20 */
QE_CLK21, /* Clock 21 */
QE_CLK22, /* Clock 22 */
QE_CLK23, /* Clock 23 */
QE_CLK24, /* Clock 24 */
QE_RSYNC_PIN, /* RSYNC from pin */
QE_TSYNC_PIN, /* TSYNC from pin */
QE_CLK_DUMMY
};
static inline bool qe_clock_is_brg(enum qe_clock clk)
{
return clk >= QE_BRG1 && clk <= QE_BRG16;
}
extern spinlock_t cmxgcr_lock;
/* Export QE common operations */
#ifdef CONFIG_QUICC_ENGINE
extern void qe_reset(void);
#else
static inline void qe_reset(void) {}
#endif
int cpm_muram_init(void);
#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
s32 cpm_muram_alloc(unsigned long size, unsigned long align);
s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size,
unsigned long align);
void cpm_muram_free(s32 offset);
s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
s32 devm_cpm_muram_alloc_fixed(struct device *dev, unsigned long offset,
unsigned long size);
void __iomem *cpm_muram_addr(unsigned long offset);
unsigned long cpm_muram_offset(const void __iomem *addr);
dma_addr_t cpm_muram_dma(void __iomem *addr);
void cpm_muram_free_addr(const void __iomem *addr);
#else
static inline s32 cpm_muram_alloc(unsigned long size,
unsigned long align)
{
return -ENOSYS;
}
static inline s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size,
unsigned long align)
{
return -ENOSYS;
}
static inline void cpm_muram_free(s32 offset)
{
}
static inline s32 cpm_muram_alloc_fixed(unsigned long offset,
unsigned long size)
{
return -ENOSYS;
}
static inline s32 devm_cpm_muram_alloc_fixed(struct device *dev,
unsigned long offset,
unsigned long size)
{
return -ENOSYS;
}
static inline void __iomem *cpm_muram_addr(unsigned long offset)
{
return NULL;
}
static inline unsigned long cpm_muram_offset(const void __iomem *addr)
{
return -ENOSYS;
}
static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
{
return 0;
}
static inline void cpm_muram_free_addr(const void __iomem *addr)
{
}
#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
/* QE PIO */
#define QE_PIO_PINS 32
struct qe_pio_regs {
__be32 cpodr; /* Open drain register */
__be32 cpdata; /* Data register */
__be32 cpdir1; /* Direction register */
__be32 cpdir2; /* Direction register */
__be32 cppar1; /* Pin assignment register */
__be32 cppar2; /* Pin assignment register */
#ifdef CONFIG_PPC_85xx
u8 pad[8];
#endif
};
#define QE_PIO_DIR_IN 2
#define QE_PIO_DIR_OUT 1
extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
int dir, int open_drain, int assignment,
int has_irq);
#ifdef CONFIG_QUICC_ENGINE
extern int par_io_init(struct device_node *np);
extern int par_io_of_config(struct device_node *np);
extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
int assignment, int has_irq);
extern int par_io_data_set(u8 port, u8 pin, u8 val);
#else
static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
int assignment, int has_irq) { return -ENOSYS; }
static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
#endif /* CONFIG_QUICC_ENGINE */
/*
* Pin multiplexing functions.
*/
struct qe_pin;
#ifdef CONFIG_QE_GPIO
extern struct qe_pin *qe_pin_request(struct device *dev, int index);
extern void qe_pin_free(struct qe_pin *qe_pin);
extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
extern void qe_pin_set_dedicated(struct qe_pin *pin);
#else
static inline struct qe_pin *qe_pin_request(struct device *dev, int index)
{
return ERR_PTR(-ENOSYS);
}
static inline void qe_pin_free(struct qe_pin *qe_pin) {}
static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
#endif /* CONFIG_QE_GPIO */
#ifdef CONFIG_QUICC_ENGINE
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
#else
static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
u32 cmd_input)
{
return -ENOSYS;
}
#endif /* CONFIG_QUICC_ENGINE */
/* QE internal API */
enum qe_clock qe_clock_source(const char *source);
unsigned int qe_get_brg_clk(void);
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
unsigned int qe_get_num_of_risc(void);
unsigned int qe_get_num_of_snums(void);
static inline int qe_alive_during_sleep(void)
{
/*
* MPC8568E reference manual says:
*
* "...power down sequence waits for all I/O interfaces to become idle.
* In some applications this may happen eventually without actively
* shutting down interfaces, but most likely, software will have to
* take steps to shut down the eTSEC, QUICC Engine Block, and PCI
* interfaces before issuing the command (either the write to the core
* MSR[WE] as described above or writing to POWMGTCSR) to put the
* device into sleep state."
*
* MPC8569E reference manual has a similar paragraph.
*/
#ifdef CONFIG_PPC_85xx
return 0;
#else
return 1;
#endif
}
/* we actually use cpm_muram implementation, define this for convenience */
#define qe_muram_init cpm_muram_init
#define qe_muram_alloc cpm_muram_alloc
#define devm_qe_muram_alloc devm_cpm_muram_alloc
#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
#define devm_qe_muram_alloc_fixed devm_cpm_muram_alloc_fixed
#define qe_muram_free cpm_muram_free
#define qe_muram_addr cpm_muram_addr
#define qe_muram_offset cpm_muram_offset
#define qe_muram_dma cpm_muram_dma
#define qe_muram_free_addr cpm_muram_free_addr
#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
#define qe_clrsetbits_be32(addr, clear, set) \
iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_be16(addr, clear, set) \
iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_8(addr, clear, set) \
iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
/* Structure that defines QE firmware binary files.
*
* See Documentation/arch/powerpc/qe_firmware.rst for a description of these
* fields.
*/
struct qe_firmware {
struct qe_header {
__be32 length; /* Length of the entire structure, in bytes */
u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
u8 version; /* Version of this layout. First ver is '1' */
} header;
u8 id[62]; /* Null-terminated identifier string */
u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
u8 count; /* Number of microcode[] structures */
struct {
__be16 model; /* The SOC model */
u8 major; /* The SOC revision major */
u8 minor; /* The SOC revision minor */
} __attribute__ ((packed)) soc;
u8 padding[4]; /* Reserved, for alignment */
__be64 extended_modes; /* Extended modes */
__be32 vtraps[8]; /* Virtual trap addresses */
u8 reserved[4]; /* Reserved, for future expansion */
struct qe_microcode {
u8 id[32]; /* Null-terminated identifier */
__be32 traps[16]; /* Trap addresses, 0 == ignore */
__be32 eccr; /* The value for the ECCR register */
__be32 iram_offset; /* Offset into I-RAM for the code */
__be32 count; /* Number of 32-bit words of the code */
__be32 code_offset; /* Offset of the actual microcode */
u8 major; /* The microcode version major */
u8 minor; /* The microcode version minor */
u8 revision; /* The microcode version revision */
u8 padding; /* Reserved, for alignment */
u8 reserved[4]; /* Reserved, for future expansion */
} __packed microcode[];
/* All microcode binaries should be located here */
/* CRC32 should be located here, after the microcode binaries */
} __attribute__ ((packed));
struct qe_firmware_info {
char id[64]; /* Firmware name */
u32 vtraps[8]; /* Virtual trap addresses */
u64 extended_modes; /* Extended modes */
};
#ifdef CONFIG_QUICC_ENGINE
/* Upload a firmware to the QE */
int qe_upload_firmware(const struct qe_firmware *firmware);
#else
static inline int qe_upload_firmware(const struct qe_firmware *firmware)
{
return -ENOSYS;
}
#endif /* CONFIG_QUICC_ENGINE */
/* Obtain information on the uploaded firmware */
struct qe_firmware_info *qe_get_firmware_info(void);
/* QE USB */
int qe_usb_clock_set(enum qe_clock clk, int rate);
/* Buffer descriptors */
struct qe_bd {
__be16 status;
__be16 length;
__be32 buf;
} __attribute__ ((packed));
#define BD_STATUS_MASK 0xffff0000
#define BD_LENGTH_MASK 0x0000ffff
/* Alignment */
#define QE_INTR_TABLE_ALIGN 16 /* ??? */
#define QE_ALIGNMENT_OF_BD 8
#define QE_ALIGNMENT_OF_PRAM 64
/* RISC allocation */
#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
QE_RISC_ALLOCATION_RISC2)
#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
QE_RISC_ALLOCATION_RISC2 | \
QE_RISC_ALLOCATION_RISC3 | \
QE_RISC_ALLOCATION_RISC4)
/* QE extended filtering Table Lookup Key Size */
enum qe_fltr_tbl_lookup_key_size {
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
= 0x3f, /* LookupKey parsed by the Generate LookupKey
CMD is truncated to 8 bytes */
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
= 0x5f, /* LookupKey parsed by the Generate LookupKey
CMD is truncated to 16 bytes */
};
/* QE FLTR extended filtering Largest External Table Lookup Key Size */
enum qe_fltr_largest_external_tbl_lookup_key_size {
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
= 0x0,/* not used */
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
};
/* structure representing QE parameter RAM */
struct qe_timer_tables {
u16 tm_base; /* QE timer table base adr */
u16 tm_ptr; /* QE timer table pointer */
u16 r_tmr; /* QE timer mode register */
u16 r_tmv; /* QE timer valid register */
u32 tm_cmd; /* QE timer cmd register */
u32 tm_cnt; /* QE timer internal cnt */
} __attribute__ ((packed));
#define QE_FLTR_TAD_SIZE 8
/* QE extended filtering Termination Action Descriptor (TAD) */
struct qe_fltr_tad {
u8 serialized[QE_FLTR_TAD_SIZE];
} __attribute__ ((packed));
/* Communication Direction */
enum comm_dir {
COMM_DIR_NONE = 0,
COMM_DIR_RX = 1,
COMM_DIR_TX = 2,
COMM_DIR_RX_AND_TX = 3
};
/* QE CMXUCR Registers.
* There are two UCCs represented in each of the four CMXUCR registers.
* These values are for the UCC in the LSBs
*/
#define QE_CMXUCR_MII_ENET_MNG 0x00007000
#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
#define QE_CMXUCR_GRANT 0x00008000
#define QE_CMXUCR_TSA 0x00004000
#define QE_CMXUCR_BKPT 0x00000100
#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
/* QE CMXGCR Registers.
*/
#define QE_CMXGCR_MII_ENET_MNG 0x00007000
#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
#define QE_CMXGCR_USBCS 0x0000000f
#define QE_CMXGCR_USBCS_CLK3 0x1
#define QE_CMXGCR_USBCS_CLK5 0x2
#define QE_CMXGCR_USBCS_CLK7 0x3
#define QE_CMXGCR_USBCS_CLK9 0x4
#define QE_CMXGCR_USBCS_CLK13 0x5
#define QE_CMXGCR_USBCS_CLK17 0x6
#define QE_CMXGCR_USBCS_CLK19 0x7
#define QE_CMXGCR_USBCS_CLK21 0x8
#define QE_CMXGCR_USBCS_BRG9 0x9
#define QE_CMXGCR_USBCS_BRG10 0xa
/* QE CECR Commands.
*/
#define QE_CR_FLG 0x00010000
#define QE_RESET 0x80000000
#define QE_INIT_TX_RX 0x00000000
#define QE_INIT_RX 0x00000001
#define QE_INIT_TX 0x00000002
#define QE_ENTER_HUNT_MODE 0x00000003
#define QE_STOP_TX 0x00000004
#define QE_GRACEFUL_STOP_TX 0x00000005
#define QE_RESTART_TX 0x00000006
#define QE_CLOSE_RX_BD 0x00000007
#define QE_SWITCH_COMMAND 0x00000007
#define QE_SET_GROUP_ADDRESS 0x00000008
#define QE_START_IDMA 0x00000009
#define QE_MCC_STOP_RX 0x00000009
#define QE_ATM_TRANSMIT 0x0000000a
#define QE_HPAC_CLEAR_ALL 0x0000000b
#define QE_GRACEFUL_STOP_RX 0x0000001a
#define QE_RESTART_RX 0x0000001b
#define QE_HPAC_SET_PRIORITY 0x0000010b
#define QE_HPAC_STOP_TX 0x0000020b
#define QE_HPAC_STOP_RX 0x0000030b
#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
#define QE_HPAC_START_TX 0x0000060b
#define QE_HPAC_START_RX 0x0000070b
#define QE_USB_STOP_TX 0x0000000a
#define QE_USB_RESTART_TX 0x0000000c
#define QE_QMC_STOP_TX 0x0000000c
#define QE_QMC_STOP_RX 0x0000000d
#define QE_SS7_SU_FIL_RESET 0x0000000e
#define QE_PUSHSCHED 0x0000000f
/* jonathbr added from here down for 83xx */
#define QE_RESET_BCS 0x0000000a
#define QE_MCC_INIT_TX_RX_16 0x00000003
#define QE_MCC_STOP_TX 0x00000004
#define QE_MCC_INIT_TX_1 0x00000005
#define QE_MCC_INIT_RX_1 0x00000006
#define QE_MCC_RESET 0x00000007
#define QE_SET_TIMER 0x00000008
#define QE_RANDOM_NUMBER 0x0000000c
#define QE_ATM_MULTI_THREAD_INIT 0x00000011
#define QE_ASSIGN_PAGE 0x00000012
#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
#define QE_START_FLOW_CONTROL 0x00000014
#define QE_STOP_FLOW_CONTROL 0x00000015
#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
#define QE_ASSIGN_RISC 0x00000010
#define QE_CR_MCN_NORMAL_SHIFT 6
#define QE_CR_MCN_USB_SHIFT 4
#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
#define QE_CR_SNUM_SHIFT 17
/* QE CECR Sub Block - sub block of QE command.
*/
#define QE_CR_SUBBLOCK_INVALID 0x00000000
#define QE_CR_SUBBLOCK_USB 0x03200000
#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
#define QE_CR_SUBBLOCK_MCC1 0x03800000
#define QE_CR_SUBBLOCK_MCC2 0x03a00000
#define QE_CR_SUBBLOCK_MCC3 0x03000000
#define QE_CR_SUBBLOCK_IDMA1 0x02800000
#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
#define QE_CR_SUBBLOCK_HPAC 0x01e00000
#define QE_CR_SUBBLOCK_SPI1 0x01400000
#define QE_CR_SUBBLOCK_SPI2 0x01600000
#define QE_CR_SUBBLOCK_RAND 0x01c00000
#define QE_CR_SUBBLOCK_TIMER 0x01e00000
#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
#define QE_CR_PROTOCOL_QMC 0x02
#define QE_CR_PROTOCOL_UART 0x04
#define QE_CR_PROTOCOL_ATM_POS 0x0A
#define QE_CR_PROTOCOL_ETHERNET 0x0C
#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
/* BRG configuration register */
#define QE_BRGC_ENABLE 0x00010000
#define QE_BRGC_DIVISOR_SHIFT 1
#define QE_BRGC_DIVISOR_MAX 0xFFF
#define QE_BRGC_DIV16 1
/* QE Timers registers */
#define QE_GTCFR1_PCAS 0x80
#define QE_GTCFR1_STP2 0x20
#define QE_GTCFR1_RST2 0x10
#define QE_GTCFR1_GM2 0x08
#define QE_GTCFR1_GM1 0x04
#define QE_GTCFR1_STP1 0x02
#define QE_GTCFR1_RST1 0x01
/* SDMA registers */
#define QE_SDSR_BER1 0x02000000
#define QE_SDSR_BER2 0x01000000
#define QE_SDMR_GLB_1_MSK 0x80000000
#define QE_SDMR_ADR_SEL 0x20000000
#define QE_SDMR_BER1_MSK 0x02000000
#define QE_SDMR_BER2_MSK 0x01000000
#define QE_SDMR_EB1_MSK 0x00800000
#define QE_SDMR_ER1_MSK 0x00080000
#define QE_SDMR_ER2_MSK 0x00040000
#define QE_SDMR_CEN_MASK 0x0000E000
#define QE_SDMR_SBER_1 0x00000200
#define QE_SDMR_SBER_2 0x00000200
#define QE_SDMR_EB1_PR_MASK 0x000000C0
#define QE_SDMR_ER1_PR 0x00000008
#define QE_SDMR_CEN_SHIFT 13
#define QE_SDMR_EB1_PR_SHIFT 6
#define QE_SDTM_MSNUM_SHIFT 24
#define QE_SDEBCR_BA_MASK 0x01FFFFFF
/* Communication Processor */
#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
/* I-RAM */
#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
#define QE_IRAM_READY 0x80000000 /* Ready */
/* UPC */
#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
/* UCC GUEMR register */
#define UCC_GUEMR_MODE_MASK_RX 0x02
#define UCC_GUEMR_MODE_FAST_RX 0x02
#define UCC_GUEMR_MODE_SLOW_RX 0x00
#define UCC_GUEMR_MODE_MASK_TX 0x01
#define UCC_GUEMR_MODE_FAST_TX 0x01
#define UCC_GUEMR_MODE_SLOW_TX 0x00
#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
must be set 1 */
/* structure representing UCC SLOW parameter RAM */
struct ucc_slow_pram {
__be16 rbase; /* RX BD base address */
__be16 tbase; /* TX BD base address */
u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
__be16 mrblr; /* Rx buffer length */
__be32 rstate; /* Rx internal state */
__be32 rptr; /* Rx internal data pointer */
__be16 rbptr; /* rb BD Pointer */
__be16 rcount; /* Rx internal byte count */
__be32 rtemp; /* Rx temp */
__be32 tstate; /* Tx internal state */
__be32 tptr; /* Tx internal data pointer */
__be16 tbptr; /* Tx BD pointer */
__be16 tcount; /* Tx byte count */
__be32 ttemp; /* Tx temp */
__be32 rcrc; /* temp receive CRC */
__be32 tcrc; /* temp transmit CRC */
} __attribute__ ((packed));
/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
#define UCC_SLOW_GUMR_H_REVD 0x00002000
#define UCC_SLOW_GUMR_H_TRX 0x00001000
#define UCC_SLOW_GUMR_H_TTX 0x00000800
#define UCC_SLOW_GUMR_H_CDP 0x00000400
#define UCC_SLOW_GUMR_H_CTSP 0x00000200
#define UCC_SLOW_GUMR_H_CDS 0x00000100
#define UCC_SLOW_GUMR_H_CTSS 0x00000080
#define UCC_SLOW_GUMR_H_TFL 0x00000040
#define UCC_SLOW_GUMR_H_RFW 0x00000020
#define UCC_SLOW_GUMR_H_TXSY 0x00000010
#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
#define UCC_SLOW_GUMR_H_RTSM 0x00000002
#define UCC_SLOW_GUMR_H_RSYN 0x00000001
#define UCC_SLOW_GUMR_L_TCI 0x10000000
#define UCC_SLOW_GUMR_L_RINV 0x02000000
#define UCC_SLOW_GUMR_L_TINV 0x01000000
#define UCC_SLOW_GUMR_L_TEND 0x00040000
#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
#define UCC_SLOW_GUMR_L_ENR 0x00000020
#define UCC_SLOW_GUMR_L_ENT 0x00000010
#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
/* General UCC FAST Mode Register */
#define UCC_FAST_GUMR_LOOPBACK 0x40000000
#define UCC_FAST_GUMR_TCI 0x20000000
#define UCC_FAST_GUMR_TRX 0x10000000
#define UCC_FAST_GUMR_TTX 0x08000000
#define UCC_FAST_GUMR_CDP 0x04000000
#define UCC_FAST_GUMR_CTSP 0x02000000
#define UCC_FAST_GUMR_CDS 0x01000000
#define UCC_FAST_GUMR_CTSS 0x00800000
#define UCC_FAST_GUMR_TXSY 0x00020000
#define UCC_FAST_GUMR_RSYN 0x00010000
#define UCC_FAST_GUMR_SYNL_MASK 0x0000C000
#define UCC_FAST_GUMR_SYNL_16 0x0000C000
#define UCC_FAST_GUMR_SYNL_8 0x00008000
#define UCC_FAST_GUMR_SYNL_AUTO 0x00004000
#define UCC_FAST_GUMR_RTSM 0x00002000
#define UCC_FAST_GUMR_REVD 0x00000400
#define UCC_FAST_GUMR_ENR 0x00000020
#define UCC_FAST_GUMR_ENT 0x00000010
/* UART Slow UCC Event Register (UCCE) */
#define UCC_UART_UCCE_AB 0x0200
#define UCC_UART_UCCE_IDLE 0x0100
#define UCC_UART_UCCE_GRA 0x0080
#define UCC_UART_UCCE_BRKE 0x0040
#define UCC_UART_UCCE_BRKS 0x0020
#define UCC_UART_UCCE_CCR 0x0008
#define UCC_UART_UCCE_BSY 0x0004
#define UCC_UART_UCCE_TX 0x0002
#define UCC_UART_UCCE_RX 0x0001
/* HDLC Slow UCC Event Register (UCCE) */
#define UCC_HDLC_UCCE_GLR 0x1000
#define UCC_HDLC_UCCE_GLT 0x0800
#define UCC_HDLC_UCCE_IDLE 0x0100
#define UCC_HDLC_UCCE_BRKE 0x0040
#define UCC_HDLC_UCCE_BRKS 0x0020
#define UCC_HDLC_UCCE_TXE 0x0010
#define UCC_HDLC_UCCE_RXF 0x0008
#define UCC_HDLC_UCCE_BSY 0x0004
#define UCC_HDLC_UCCE_TXB 0x0002
#define UCC_HDLC_UCCE_RXB 0x0001
/* BISYNC Slow UCC Event Register (UCCE) */
#define UCC_BISYNC_UCCE_GRA 0x0080
#define UCC_BISYNC_UCCE_TXE 0x0010
#define UCC_BISYNC_UCCE_RCH 0x0008
#define UCC_BISYNC_UCCE_BSY 0x0004
#define UCC_BISYNC_UCCE_TXB 0x0002
#define UCC_BISYNC_UCCE_RXB 0x0001
/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
#define UCC_GETH_UCCE_MPD 0x80000000
#define UCC_GETH_UCCE_SCAR 0x40000000
#define UCC_GETH_UCCE_GRA 0x20000000
#define UCC_GETH_UCCE_CBPR 0x10000000
#define UCC_GETH_UCCE_BSY 0x08000000
#define UCC_GETH_UCCE_RXC 0x04000000
#define UCC_GETH_UCCE_TXC 0x02000000
#define UCC_GETH_UCCE_TXE 0x01000000
#define UCC_GETH_UCCE_TXB7 0x00800000
#define UCC_GETH_UCCE_TXB6 0x00400000
#define UCC_GETH_UCCE_TXB5 0x00200000
#define UCC_GETH_UCCE_TXB4 0x00100000
#define UCC_GETH_UCCE_TXB3 0x00080000
#define UCC_GETH_UCCE_TXB2 0x00040000
#define UCC_GETH_UCCE_TXB1 0x00020000
#define UCC_GETH_UCCE_TXB0 0x00010000
#define UCC_GETH_UCCE_RXB7 0x00008000
#define UCC_GETH_UCCE_RXB6 0x00004000
#define UCC_GETH_UCCE_RXB5 0x00002000
#define UCC_GETH_UCCE_RXB4 0x00001000
#define UCC_GETH_UCCE_RXB3 0x00000800
#define UCC_GETH_UCCE_RXB2 0x00000400
#define UCC_GETH_UCCE_RXB1 0x00000200
#define UCC_GETH_UCCE_RXB0 0x00000100
#define UCC_GETH_UCCE_RXF7 0x00000080
#define UCC_GETH_UCCE_RXF6 0x00000040
#define UCC_GETH_UCCE_RXF5 0x00000020
#define UCC_GETH_UCCE_RXF4 0x00000010
#define UCC_GETH_UCCE_RXF3 0x00000008
#define UCC_GETH_UCCE_RXF2 0x00000004
#define UCC_GETH_UCCE_RXF1 0x00000002
#define UCC_GETH_UCCE_RXF0 0x00000001
/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
#define UCC_UART_UPSMR_FLC 0x8000
#define UCC_UART_UPSMR_SL 0x4000
#define UCC_UART_UPSMR_CL_MASK 0x3000
#define UCC_UART_UPSMR_CL_8 0x3000
#define UCC_UART_UPSMR_CL_7 0x2000
#define UCC_UART_UPSMR_CL_6 0x1000
#define UCC_UART_UPSMR_CL_5 0x0000
#define UCC_UART_UPSMR_UM_MASK 0x0c00
#define UCC_UART_UPSMR_UM_NORMAL 0x0000
#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
#define UCC_UART_UPSMR_FRZ 0x0200
#define UCC_UART_UPSMR_RZS 0x0100
#define UCC_UART_UPSMR_SYN 0x0080
#define UCC_UART_UPSMR_DRT 0x0040
#define UCC_UART_UPSMR_PEN 0x0010
#define UCC_UART_UPSMR_RPM_MASK 0x000c
#define UCC_UART_UPSMR_RPM_ODD 0x0000
#define UCC_UART_UPSMR_RPM_LOW 0x0004
#define UCC_UART_UPSMR_RPM_EVEN 0x0008
#define UCC_UART_UPSMR_RPM_HIGH 0x000C
#define UCC_UART_UPSMR_TPM_MASK 0x0003
#define UCC_UART_UPSMR_TPM_ODD 0x0000
#define UCC_UART_UPSMR_TPM_LOW 0x0001
#define UCC_UART_UPSMR_TPM_EVEN 0x0002
#define UCC_UART_UPSMR_TPM_HIGH 0x0003
/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
#define UCC_GETH_UPSMR_FTFE 0x80000000
#define UCC_GETH_UPSMR_PTPE 0x40000000
#define UCC_GETH_UPSMR_ECM 0x04000000
#define UCC_GETH_UPSMR_HSE 0x02000000
#define UCC_GETH_UPSMR_PRO 0x00400000
#define UCC_GETH_UPSMR_CAP 0x00200000
#define UCC_GETH_UPSMR_RSH 0x00100000
#define UCC_GETH_UPSMR_RPM 0x00080000
#define UCC_GETH_UPSMR_R10M 0x00040000
#define UCC_GETH_UPSMR_RLPB 0x00020000
#define UCC_GETH_UPSMR_TBIM 0x00010000
#define UCC_GETH_UPSMR_RES1 0x00002000
#define UCC_GETH_UPSMR_RMM 0x00001000
#define UCC_GETH_UPSMR_CAM 0x00000400
#define UCC_GETH_UPSMR_BRO 0x00000200
#define UCC_GETH_UPSMR_SMM 0x00000080
#define UCC_GETH_UPSMR_SGMM 0x00000020
/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
#define UCC_HDLC_UPSMR_RTE 0x02000000
#define UCC_HDLC_UPSMR_BUS 0x00200000
#define UCC_HDLC_UPSMR_CW8 0x00007000
/* UCC Transmit On Demand Register (UTODR) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000
/* UCC Bus Mode Register masks */
/* Not to be confused with the Bundle Mode Register */
#define UCC_BMR_GBL 0x20
#define UCC_BMR_BO_BE 0x10
#define UCC_BMR_CETM 0x04
#define UCC_BMR_DTB 0x02
#define UCC_BMR_BDB 0x01
/* Function code masks */
#define FC_GBL 0x20
#define FC_DTB_LCL 0x02
#define UCC_FAST_FUNCTION_CODE_GBL 0x20
#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_QE_H */
linux-7.2.3/include/soc/fsl/qe/qe_tdm.h
+92
View File
@@ -0,0 +1,92 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Internal header file for QE TDM mode routines.
*
* Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
*
* Authors: Zhao Qiang <qiang.zhao@nxp.com>
*/
#ifndef _QE_TDM_H_
#define _QE_TDM_H_
#include <linux/list.h>
#include <linux/types.h>
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>
#include <soc/fsl/qe/ucc.h>
#include <soc/fsl/qe/ucc_fast.h>
struct device_node;
/* SI RAM entries */
#define SIR_LAST 0x0001
#define SIR_BYTE 0x0002
#define SIR_CNT(x) ((x) << 2)
#define SIR_CSEL(x) ((x) << 5)
#define SIR_SGS 0x0200
#define SIR_SWTR 0x4000
#define SIR_MCC 0x8000
#define SIR_IDLE 0
/* SIxMR fields */
#define SIMR_SAD(x) ((x) << 12)
#define SIMR_SDM_NORMAL 0x0000
#define SIMR_SDM_INTERNAL_LOOPBACK 0x0800
#define SIMR_SDM_MASK 0x0c00
#define SIMR_CRT 0x0040
#define SIMR_SL 0x0020
#define SIMR_CE 0x0010
#define SIMR_FE 0x0008
#define SIMR_GM 0x0004
#define SIMR_TFSD(n) (n)
#define SIMR_RFSD(n) ((n) << 8)
enum tdm_ts_t {
TDM_TX_TS,
TDM_RX_TS
};
enum tdm_framer_t {
TDM_FRAMER_T1,
TDM_FRAMER_E1
};
enum tdm_mode_t {
TDM_INTERNAL_LOOPBACK,
TDM_NORMAL
};
struct si_mode_info {
u8 simr_rfsd;
u8 simr_tfsd;
u8 simr_crt;
u8 simr_sl;
u8 simr_ce;
u8 simr_fe;
u8 simr_gm;
};
struct ucc_tdm_info {
struct ucc_fast_info uf_info;
struct si_mode_info si_info;
};
struct ucc_tdm {
u16 tdm_port; /* port for this tdm:TDMA,TDMB */
u32 siram_entry_id;
u16 __iomem *siram;
struct si1 __iomem *si_regs;
enum tdm_framer_t tdm_framer_type;
enum tdm_mode_t tdm_mode;
u8 num_of_ts; /* the number of timeslots in this tdm frame */
u32 tx_ts_mask; /* tx time slot mask */
u32 rx_ts_mask; /* rx time slot mask */
};
int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
struct ucc_tdm_info *ut_info);
void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info);
#endif
linux-7.2.3/include/soc/fsl/qe/qmc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QMC management
*
* Copyright 2022 CS GROUP France
*
* Author: Herve Codina <herve.codina@bootlin.com>
*/
#ifndef __SOC_FSL_QMC_H__
#define __SOC_FSL_QMC_H__
#include <linux/bits.h>
#include <linux/types.h>
struct device_node;
struct device;
struct qmc_chan;
int qmc_chan_count_phandles(struct device_node *np, const char *phandles_name);
struct qmc_chan *qmc_chan_get_byphandles_index(struct device_node *np,
const char *phandles_name,
int index);
struct qmc_chan *devm_qmc_chan_get_byphandles_index(struct device *dev,
struct device_node *np,
const char *phandles_name,
int index);
static inline struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np,
const char *phandle_name)
{
return qmc_chan_get_byphandles_index(np, phandle_name, 0);
}
static inline struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev,
struct device_node *np,
const char *phandle_name)
{
return devm_qmc_chan_get_byphandles_index(dev, np, phandle_name, 0);
}
struct qmc_chan *qmc_chan_get_bychild(struct device_node *np);
void qmc_chan_put(struct qmc_chan *chan);
struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, struct device_node *np);
enum qmc_mode {
QMC_TRANSPARENT,
QMC_HDLC,
};
struct qmc_chan_info {
enum qmc_mode mode;
unsigned long rx_fs_rate;
unsigned long rx_bit_rate;
u8 nb_rx_ts;
unsigned long tx_fs_rate;
unsigned long tx_bit_rate;
u8 nb_tx_ts;
};
int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);
struct qmc_chan_ts_info {
u64 rx_ts_mask_avail;
u64 tx_ts_mask_avail;
u64 rx_ts_mask;
u64 tx_ts_mask;
};
int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info);
int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info);
struct qmc_chan_param {
enum qmc_mode mode;
union {
struct {
u16 max_rx_buf_size;
u16 max_rx_frame_size;
bool is_crc32;
} hdlc;
struct {
u16 max_rx_buf_size;
} transp;
};
};
int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param);
int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
void (*complete)(void *context), void *context);
/* Flags available (ORed) for read complete() flags parameter in HDLC mode.
* No flags are available in transparent mode and the read complete() flags
* parameter has no meaning in transparent mode.
*/
#define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */
#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */
#define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */
#define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */
#define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */
#define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */
int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
void (*complete)(void *context, size_t length,
unsigned int flags),
void *context);
#define QMC_CHAN_READ (1<<0)
#define QMC_CHAN_WRITE (1<<1)
#define QMC_CHAN_ALL (QMC_CHAN_READ | QMC_CHAN_WRITE)
int qmc_chan_start(struct qmc_chan *chan, int direction);
int qmc_chan_stop(struct qmc_chan *chan, int direction);
int qmc_chan_reset(struct qmc_chan *chan, int direction);
#endif /* __SOC_FSL_QMC_H__ */
linux-7.2.3/include/soc/fsl/qe/ucc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com>
*
* Description:
* Internal header file for UCC unit routines.
*/
#ifndef __UCC_H__
#define __UCC_H__
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>
#define STATISTICS
#define UCC_MAX_NUM 8
/* Slow or fast type for UCCs.
*/
enum ucc_speed_type {
UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
};
/* ucc_set_type
* Sets UCC to slow or fast mode.
*
* ucc_num - (In) number of UCC (0-7).
* speed - (In) slow or fast mode for UCC.
*/
int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
enum comm_dir mode);
int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock,
enum comm_dir mode);
int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock,
enum comm_dir mode);
int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
/* QE MUX clock routing for UCC
*/
static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
{
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
}
static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
{
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
}
static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
{
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
}
#endif /* __UCC_H__ */
linux-7.2.3/include/soc/fsl/qe/ucc_fast.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Internal header file for UCC FAST unit routines.
*
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com>
*/
#ifndef __UCC_FAST_H__
#define __UCC_FAST_H__
#include <linux/types.h>
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>
#include <soc/fsl/qe/ucc.h>
/* Receive BD's status and length*/
#define R_E 0x80000000 /* buffer empty */
#define R_W 0x20000000 /* wrap bit */
#define R_I 0x10000000 /* interrupt on reception */
#define R_L 0x08000000 /* last */
#define R_F 0x04000000 /* first */
/* transmit BD's status and length*/
#define T_R 0x80000000 /* ready bit */
#define T_W 0x20000000 /* wrap bit */
#define T_I 0x10000000 /* interrupt on completion */
#define T_L 0x08000000 /* last */
/* Receive BD's status */
#define R_E_S 0x8000 /* buffer empty */
#define R_W_S 0x2000 /* wrap bit */
#define R_I_S 0x1000 /* interrupt on reception */
#define R_L_S 0x0800 /* last */
#define R_F_S 0x0400 /* first */
#define R_CM_S 0x0200 /* continuous mode */
#define R_LG_S 0x0020 /* frame length */
#define R_NO_S 0x0010 /* nonoctet */
#define R_AB_S 0x0008 /* abort */
#define R_CR_S 0x0004 /* crc */
#define R_OV_S 0x0002 /* overrun */
#define R_CD_S 0x0001 /* carrier detect */
/* transmit BD's status */
#define T_R_S 0x8000 /* ready bit */
#define T_W_S 0x2000 /* wrap bit */
#define T_I_S 0x1000 /* interrupt on completion */
#define T_L_S 0x0800 /* last */
#define T_TC_S 0x0400 /* crc */
#define T_TM_S 0x0200 /* continuous mode */
#define T_UN_S 0x0002 /* hdlc underrun */
#define T_CT_S 0x0001 /* hdlc carrier lost */
/* Rx Data buffer must be 4 bytes aligned in most cases */
#define UCC_FAST_RX_ALIGN 4
#define UCC_FAST_MRBLR_ALIGNMENT 4
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
/* Sizes */
#define UCC_FAST_URFS_MIN_VAL 0x88
#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
/* ucc_fast_channel_protocol_mode - UCC FAST mode */
enum ucc_fast_channel_protocol_mode {
UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
};
/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
enum ucc_fast_transparent_txrx {
UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
};
/* UCC fast diagnostic mode */
enum ucc_fast_diag_mode {
UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
};
/* UCC fast Sync length (transparent mode only) */
enum ucc_fast_sync_len {
UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
};
/* UCC fast RTS mode */
enum ucc_fast_ready_to_send {
UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
};
/* UCC fast receiver decoding mode */
enum ucc_fast_rx_decoding_method {
UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
};
/* UCC fast transmitter encoding mode */
enum ucc_fast_tx_encoding_method {
UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
};
/* UCC fast CRC length */
enum ucc_fast_transparent_tcrc {
UCC_FAST_16_BIT_CRC = 0x00000000,
UCC_FAST_CRC_RESERVED0 = 0x00000040,
UCC_FAST_32_BIT_CRC = 0x00000080,
UCC_FAST_CRC_RESERVED1 = 0x000000C0
};
/* Fast UCC initialization structure */
struct ucc_fast_info {
int ucc_num;
int tdm_num;
enum qe_clock rx_clock;
enum qe_clock tx_clock;
enum qe_clock rx_sync;
enum qe_clock tx_sync;
resource_size_t regs;
int irq;
u32 uccm_mask;
int brkpt_support;
int grant_support;
int tsa;
int cdp;
int cds;
int ctsp;
int ctss;
int tci;
int txsy;
int rtsm;
int revd;
int rsyn;
u16 max_rx_buf_length;
u16 urfs;
u16 urfet;
u16 urfset;
u16 utfs;
u16 utfet;
u16 utftt;
u16 ufpt;
enum ucc_fast_channel_protocol_mode mode;
enum ucc_fast_transparent_txrx ttx_trx;
enum ucc_fast_tx_encoding_method tenc;
enum ucc_fast_rx_decoding_method renc;
enum ucc_fast_transparent_tcrc tcrc;
enum ucc_fast_sync_len synl;
};
struct ucc_fast_private {
struct ucc_fast_info *uf_info;
struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
__be32 __iomem *p_ucce; /* a pointer to the event register in memory. */
__be32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
#ifdef CONFIG_UGETH_TX_ON_DEMAND
__be16 __iomem *p_utodr;/* pointer to the transmit on demand register */
#endif
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
int stopped_tx; /* Whether channel has been stopped for Tx
(STOP_TX, etc.) */
int stopped_rx; /* Whether channel has been stopped for Rx */
s32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
virtual fifo */
s32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
virtual fifo */
#ifdef STATISTICS
u32 tx_frames; /* Transmitted frames counter. */
u32 rx_frames; /* Received frames counter (only frames
passed to application). */
u32 tx_discarded; /* Discarded tx frames counter (frames that
were discarded by the driver due to errors).
*/
u32 rx_discarded; /* Discarded rx frames counter (frames that
were discarded by the driver due to errors).
*/
#endif /* STATISTICS */
u16 mrblr; /* maximum receive buffer length */
};
/* ucc_fast_init
* Initializes Fast UCC according to user provided parameters.
*
* uf_info - (In) pointer to the fast UCC info structure.
* uccf_ret - (Out) pointer to the fast UCC structure.
*/
int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
/* ucc_fast_free
* Frees all resources for fast UCC.
*
* uccf - (In) pointer to the fast UCC structure.
*/
void ucc_fast_free(struct ucc_fast_private * uccf);
/* ucc_fast_enable
* Enables a fast UCC port.
* This routine enables Tx and/or Rx through the General UCC Mode Register.
*
* uccf - (In) pointer to the fast UCC structure.
* mode - (In) TX, RX, or both.
*/
void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
/* ucc_fast_disable
* Disables a fast UCC port.
* This routine disables Tx and/or Rx through the General UCC Mode Register.
*
* uccf - (In) pointer to the fast UCC structure.
* mode - (In) TX, RX, or both.
*/
void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
/* ucc_fast_irq
* Handles interrupts on fast UCC.
* Called from the general interrupt routine to handle interrupts on fast UCC.
*
* uccf - (In) pointer to the fast UCC structure.
*/
void ucc_fast_irq(struct ucc_fast_private * uccf);
/* ucc_fast_transmit_on_demand
* Immediately forces a poll of the transmitter for data to be sent.
* Typically, the hardware performs a periodic poll for data that the
* transmit routine has set up to be transmitted. In cases where
* this polling cycle is not soon enough, this optional routine can
* be invoked to force a poll right away, instead. Proper use for
* each transmission for which this functionality is desired is to
* call the transmit routine and then this routine right after.
*
* uccf - (In) pointer to the fast UCC structure.
*/
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
#endif /* __UCC_FAST_H__ */
linux-7.2.3/include/soc/fsl/qe/ucc_slow.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com>
*
* Description:
* Internal header file for UCC SLOW unit routines.
*/
#ifndef __UCC_SLOW_H__
#define __UCC_SLOW_H__
#include <linux/types.h>
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>
#include <soc/fsl/qe/ucc.h>
/* transmit BD's status */
#define T_R 0x80000000 /* ready bit */
#define T_PAD 0x40000000 /* add pads to short frames */
#define T_W 0x20000000 /* wrap bit */
#define T_I 0x10000000 /* interrupt on completion */
#define T_L 0x08000000 /* last */
#define T_A 0x04000000 /* Address - the data transmitted as address
chars */
#define T_TC 0x04000000 /* transmit CRC */
#define T_CM 0x02000000 /* continuous mode */
#define T_DEF 0x02000000 /* collision on previous attempt to transmit */
#define T_P 0x01000000 /* Preamble - send Preamble sequence before
data */
#define T_HB 0x01000000 /* heartbeat */
#define T_NS 0x00800000 /* No Stop */
#define T_LC 0x00800000 /* late collision */
#define T_RL 0x00400000 /* retransmission limit */
#define T_UN 0x00020000 /* underrun */
#define T_CT 0x00010000 /* CTS lost */
#define T_CSL 0x00010000 /* carrier sense lost */
#define T_RC 0x003c0000 /* retry count */
/* Receive BD's status */
#define R_E 0x80000000 /* buffer empty */
#define R_W 0x20000000 /* wrap bit */
#define R_I 0x10000000 /* interrupt on reception */
#define R_L 0x08000000 /* last */
#define R_C 0x08000000 /* the last byte in this buffer is a cntl
char */
#define R_F 0x04000000 /* first */
#define R_A 0x04000000 /* the first byte in this buffer is address
byte */
#define R_CM 0x02000000 /* continuous mode */
#define R_ID 0x01000000 /* buffer close on reception of idles */
#define R_M 0x01000000 /* Frame received because of promiscuous
mode */
#define R_AM 0x00800000 /* Address match */
#define R_DE 0x00800000 /* Address match */
#define R_LG 0x00200000 /* Break received */
#define R_BR 0x00200000 /* Frame length violation */
#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
#define R_FR 0x00100000 /* Framing Error (no stop bit) character
received */
#define R_PR 0x00080000 /* Parity Error character received */
#define R_AB 0x00080000 /* Frame Aborted */
#define R_SH 0x00080000 /* frame is too short */
#define R_CR 0x00040000 /* CRC Error */
#define R_OV 0x00020000 /* Overrun */
#define R_CD 0x00010000 /* CD lost */
#define R_CL 0x00010000 /* this frame is closed because of a
collision */
/* Rx Data buffer must be 4 bytes aligned in most cases.*/
#define UCC_SLOW_RX_ALIGN 4
#define UCC_SLOW_MRBLR_ALIGNMENT 4
#define UCC_SLOW_PRAM_SIZE 0x100
#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
/* UCC Slow Channel Protocol Mode */
enum ucc_slow_channel_protocol_mode {
UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
};
/* UCC Slow Transparent Transmit CRC (TCRC) */
enum ucc_slow_transparent_tcrc {
/* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
/* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */
UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
/* 32-bit CCITT CRC (Ethernet and HDLC) */
UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
};
/* UCC Slow oversampling rate for transmitter (TDCR) */
enum ucc_slow_tx_oversampling_rate {
/* 1x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
/* 8x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
/* 16x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
/* 32x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
};
/* UCC Slow Oversampling rate for receiver (RDCR)
*/
enum ucc_slow_rx_oversampling_rate {
/* 1x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
/* 8x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
/* 16x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
/* 32x clock mode */
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
};
/* UCC Slow Transmitter encoding method (TENC)
*/
enum ucc_slow_tx_encoding_method {
UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
};
/* UCC Slow Receiver decoding method (RENC)
*/
enum ucc_slow_rx_decoding_method {
UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
};
/* UCC Slow Diagnostic mode (DIAG)
*/
enum ucc_slow_diag_mode {
UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
};
struct ucc_slow_info {
int ucc_num;
int protocol; /* QE_CR_PROTOCOL_xxx */
enum qe_clock rx_clock;
enum qe_clock tx_clock;
phys_addr_t regs;
int irq;
u16 uccm_mask;
int data_mem_part;
int init_tx;
int init_rx;
u32 tx_bd_ring_len;
u32 rx_bd_ring_len;
int rx_interrupts;
int brkpt_support;
int grant_support;
int tsa;
int cdp;
int cds;
int ctsp;
int ctss;
int rinv;
int tinv;
int rtsm;
int rfw;
int tci;
int tend;
int tfl;
int txsy;
u16 max_rx_buf_length;
enum ucc_slow_transparent_tcrc tcrc;
enum ucc_slow_channel_protocol_mode mode;
enum ucc_slow_diag_mode diag;
enum ucc_slow_tx_oversampling_rate tdcr;
enum ucc_slow_rx_oversampling_rate rdcr;
enum ucc_slow_tx_encoding_method tenc;
enum ucc_slow_rx_decoding_method renc;
};
struct ucc_slow_private {
struct ucc_slow_info *us_info;
struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
struct ucc_slow_pram __iomem *us_pram; /* a pointer to the parameter RAM */
s32 us_pram_offset;
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
int stopped_tx; /* Whether channel has been stopped for Tx
(STOP_TX, etc.) */
int stopped_rx; /* Whether channel has been stopped for Rx */
struct list_head confQ; /* frames passed to chip waiting for tx */
u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
and length for first BD in a frame */
s32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
s32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
struct qe_bd __iomem *confBd; /* next BD for confirm after Tx */
struct qe_bd __iomem *tx_bd; /* next BD for new Tx request */
struct qe_bd __iomem *rx_bd; /* next BD to collect after Rx */
void *p_rx_frame; /* accumulating receive frame */
__be16 __iomem *p_ucce; /* a pointer to the event register in memory */
__be16 __iomem *p_uccm; /* a pointer to the mask register in memory */
u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
#ifdef STATISTICS
u32 tx_frames; /* Transmitted frames counters */
u32 rx_frames; /* Received frames counters (only frames
passed to application) */
u32 rx_discarded; /* Discarded frames counters (frames that
were discarded by the driver due to
errors) */
#endif /* STATISTICS */
};
/* ucc_slow_init
* Initializes Slow UCC according to provided parameters.
*
* us_info - (In) pointer to the slow UCC info structure.
* uccs_ret - (Out) pointer to the slow UCC structure.
*/
int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
/* ucc_slow_free
* Frees all resources for slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
void ucc_slow_free(struct ucc_slow_private * uccs);
/* ucc_slow_enable
* Enables a fast UCC port.
* This routine enables Tx and/or Rx through the General UCC Mode Register.
*
* uccs - (In) pointer to the slow UCC structure.
* mode - (In) TX, RX, or both.
*/
void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
/* ucc_slow_disable
* Disables a fast UCC port.
* This routine disables Tx and/or Rx through the General UCC Mode Register.
*
* uccs - (In) pointer to the slow UCC structure.
* mode - (In) TX, RX, or both.
*/
void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
/* ucc_slow_graceful_stop_tx
* Smoothly stops transmission on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
/* ucc_slow_stop_tx
* Stops transmission on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
/* ucc_slow_restart_tx
* Restarts transmitting on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
#endif /* __UCC_SLOW_H__ */
linux-7.2.3/include/soc/fsl/qman.h
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linux-7.2.3/include/soc/imx/cpu.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __IMX_CPU_H__
#define __IMX_CPU_H__
#define MXC_CPU_MX1 1
#define MXC_CPU_MX21 21
#define MXC_CPU_MX25 25
#define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35
#define MXC_CPU_MX50 50
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
#define MXC_CPU_IMX6SL 0x60
#define MXC_CPU_IMX6DL 0x61
#define MXC_CPU_IMX6SX 0x62
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
/* virtual cpu id for i.mx6ulz */
#define MXC_CPU_IMX6ULZ 0x6b
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define MXC_CPU_IMX7ULP 0xff
#define MXC_CPU_VFx10 0x010
#define MXC_CPU_VF500 0x500
#define MXC_CPU_VF510 (MXC_CPU_VF500 | MXC_CPU_VFx10)
#define MXC_CPU_VF600 0x600
#define MXC_CPU_VF610 (MXC_CPU_VF600 | MXC_CPU_VFx10)
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#endif
#endif
linux-7.2.3/include/soc/imx/cpuidle.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2016 Pengutronix, <kernel@pengutronix.de>
*/
#ifndef __SOC_IMX_CPUIDLE_H__
#define __SOC_IMX_CPUIDLE_H__
#if defined(CONFIG_CPU_IDLE) && defined(CONFIG_SOC_IMX6Q)
void imx6q_cpuidle_fec_irqs_used(void);
void imx6q_cpuidle_fec_irqs_unused(void);
#else
static inline void imx6q_cpuidle_fec_irqs_used(void) { }
static inline void imx6q_cpuidle_fec_irqs_unused(void) { }
#endif
#endif /* __SOC_IMX_CPUIDLE_H__ */
linux-7.2.3/include/soc/imx/revision.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2015 Linaro Ltd.
*/
#ifndef __SOC_IMX_REVISION_H__
#define __SOC_IMX_REVISION_H__
#define IMX_CHIP_REVISION_1_0 0x10
#define IMX_CHIP_REVISION_1_1 0x11
#define IMX_CHIP_REVISION_1_2 0x12
#define IMX_CHIP_REVISION_1_3 0x13
#define IMX_CHIP_REVISION_1_4 0x14
#define IMX_CHIP_REVISION_1_5 0x15
#define IMX_CHIP_REVISION_2_0 0x20
#define IMX_CHIP_REVISION_2_1 0x21
#define IMX_CHIP_REVISION_2_2 0x22
#define IMX_CHIP_REVISION_2_3 0x23
#define IMX_CHIP_REVISION_3_0 0x30
#define IMX_CHIP_REVISION_3_1 0x31
#define IMX_CHIP_REVISION_3_2 0x32
#define IMX_CHIP_REVISION_3_3 0x33
#define IMX_CHIP_REVISION_UNKNOWN 0xff
int mx25_revision(void);
int mx27_revision(void);
int mx31_revision(void);
int mx35_revision(void);
int mx51_revision(void);
int mx53_revision(void);
unsigned int imx_get_soc_revision(void);
void imx_print_silicon_rev(const char *cpu, int srev);
#endif /* __SOC_IMX_REVISION_H__ */
linux-7.2.3/include/soc/mediatek/smi.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#ifndef MTK_IOMMU_SMI_H
#define MTK_IOMMU_SMI_H
#include <linux/bitops.h>
#include <linux/device.h>
#if IS_ENABLED(CONFIG_MTK_SMI)
enum iommu_atf_cmd {
IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */
IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */
IOMMU_ATF_CMD_MAX,
};
#define MTK_SMI_MMU_EN(port) BIT(port)
struct mtk_smi_larb_iommu {
struct device *dev;
unsigned int mmu;
unsigned char bank[32];
};
#endif
#endif
linux-7.2.3/include/soc/microchip/mpfs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
*
* Microchip PolarFire SoC (MPFS)
*
* Copyright (c) 2020 Microchip Corporation. All rights reserved.
*
* Author: Conor Dooley <conor.dooley@microchip.com>
*
*/
#ifndef __SOC_MPFS_H__
#define __SOC_MPFS_H__
#include <linux/types.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
struct mpfs_sys_controller;
struct mpfs_mss_msg {
u8 cmd_opcode;
u16 cmd_data_size;
struct mpfs_mss_response *response;
u8 *cmd_data;
u16 mbox_offset;
u16 resp_offset;
};
struct mpfs_mss_response {
u32 resp_status;
u32 *resp_msg;
u16 resp_size;
};
#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL)
int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg);
struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client);
#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
#if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC)
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map);
#else
static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; }
#endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */
#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
#endif /* __SOC_MPFS_H__ */
linux-7.2.3/include/soc/mscc/ocelot.h
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linux-7.2.3/include/soc/mscc/ocelot_ana.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_ANA_H_
#define _MSCC_OCELOT_ANA_H_
#define ANA_ANAGEFIL_B_DOM_EN BIT(22)
#define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
#define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
#define ANA_ANAGEFIL_PID_EN BIT(19)
#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
#define ANA_ANAGEFIL_VID_EN BIT(13)
#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
#define ANA_STORMLIMIT_CFG_RSZ 0x4
#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
#define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
#define ANA_AUTOAGE_AGE_FAST BIT(21)
#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)
#define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
#define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
#define ANA_MACTOPTIONS_SHADOW BIT(0)
#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))
#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)
#define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
#define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
#define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
#define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
#define ANA_AGENCTRL_MIRROR_CPU BIT(7)
#define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
#define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
#define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
#define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
#define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
#define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
#define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
#define ANA_FLOODING_RSZ 0x4
#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))
#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)
#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)
#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))
#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))
#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))
#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
#define ANA_SFLOW_CFG_RSZ 0x4
#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))
#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)
#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)
#define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
#define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
#define ANA_PORT_MODE_RSZ 0x4
#define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))
#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)
#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)
#define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
#define ANA_CUT_THRU_CFG_RSZ 0x4
#define ANA_PGID_PGID_RSZ 0x4
#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
#define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))
#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)
#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)
#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))
#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)
#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)
#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))
#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)
#define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))
#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)
#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)
#define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))
#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)
#define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
#define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
#define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
#define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
#define ANA_TABLES_MACACCESS_VALID BIT(11)
#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))
#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)
#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)
#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))
#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)
#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)
#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))
#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
#define MACACCESS_CMD_IDLE 0
#define MACACCESS_CMD_LEARN 1
#define MACACCESS_CMD_FORGET 2
#define MACACCESS_CMD_AGE 3
#define MACACCESS_CMD_GET_NEXT 4
#define MACACCESS_CMD_INIT 5
#define MACACCESS_CMD_READ 6
#define MACACCESS_CMD_WRITE 7
#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))
#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)
#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)
#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))
#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)
#define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0
#define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2
#define ANA_TABLES_VLANACCESS_CMD_INIT 0x3
#define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
#define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
#define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
#define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
#define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
#define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))
#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)
#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)
#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))
#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)
#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))
#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)
#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)
#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))
#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)
#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)
#define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
#define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))
#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)
#define ANA_TABLES_ENTRYLIM_RSZ 0x4
#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))
#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)
#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)
#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))
#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)
#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))
#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)
#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)
#define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
#define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))
#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)
#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))
#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)
#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)
#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))
#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)
#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)
#define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))
#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)
#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)
#define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
#define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
#define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))
#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)
#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))
#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)
#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)
#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))
#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)
#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)
#define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
#define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))
#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)
#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)
#define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))
#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)
#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)
#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))
#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)
#define SFIDACCESS_CMD_IDLE 0
#define SFIDACCESS_CMD_READ 1
#define SFIDACCESS_CMD_WRITE 2
#define SFIDACCESS_CMD_INIT 3
#define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))
#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)
#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)
#define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))
#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)
#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)
#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))
#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)
#define ANA_MSTI_STATE_RSZ 0x4
#define ANA_OAM_UPM_LM_CNT_RSZ 0x4
#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))
#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)
#define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
#define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24)
#define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24))
#define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21))
#define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21)
#define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21)
#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))
#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)
#define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
#define ANA_SG_GCL_TI_CONFIG_RSZ 0x4
#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
#define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))
#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)
#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)
#define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
#define ANA_PORT_VLAN_CFG_GSZ 0x100
#define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
#define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))
#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)
#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)
#define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
#define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
#define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))
#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)
#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
#define ANA_PORT_DROP_CFG_GSZ 0x100
#define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
#define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
#define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
#define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
#define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
#define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
#define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
#define ANA_PORT_QOS_CFG_GSZ 0x100
#define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))
#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)
#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)
#define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
#define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
#define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))
#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)
#define ANA_PORT_VCAP_CFG_GSZ 0x100
#define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))
#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)
#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)
#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))
#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)
#define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100
#define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))
#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)
#define ANA_PORT_VCAP_S2_CFG_GSZ 0x100
#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))
#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)
#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)
#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))
#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)
#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)
#define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))
#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)
#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)
#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))
#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)
#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)
#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))
#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)
#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)
#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))
#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)
#define ANA_PORT_PCP_DEI_MAP_GSZ 0x100
#define ANA_PORT_PCP_DEI_MAP_RSZ 0x4
#define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))
#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)
#define ANA_PORT_CPU_FWD_CFG_GSZ 0x100
#define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
#define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
#define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
#define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
#define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
#define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
#define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100
#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)
#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))
#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)
#define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100
#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)
#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))
#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)
#define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100
#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)
#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))
#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)
#define ANA_PORT_PORT_CFG_GSZ 0x100
#define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
#define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
#define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
#define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
#define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
#define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
#define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))
#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)
#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)
#define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
#define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
#define ANA_PORT_POL_CFG_GSZ 0x100
#define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
#define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
#define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))
#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)
#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)
#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))
#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)
#define ANA_PORT_PTP_CFG_GSZ 0x100
#define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
#define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100
#define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100
#define ANA_PORT_SFID_CFG_GSZ 0x100
#define ANA_PORT_SFID_CFG_RSZ 0x4
#define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))
#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)
#define ANA_PFC_PFC_CFG_GSZ 0x40
#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))
#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)
#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)
#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))
#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)
#define ANA_PFC_PFC_TIMER_GSZ 0x40
#define ANA_PFC_PFC_TIMER_RSZ 0x4
#define ANA_IPT_OAM_MEP_CFG_GSZ 0x8
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)
#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
#define ANA_IPT_IPT_GSZ 0x8
#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))
#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)
#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)
#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))
#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)
#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)
#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
#define ANA_PPT_PPT_RSZ 0x4
#define ANA_FID_MAP_FID_MAP_RSZ 0x4
#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))
#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)
#define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
#define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
#define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
#define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))
#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)
#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)
#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))
#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)
#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)
#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))
#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)
#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)
#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))
#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)
#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)
#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))
#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)
#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)
#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))
#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)
#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)
#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))
#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)
#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)
#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))
#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)
#define ANA_CPUQ_8021_CFG_RSZ 0x4
#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))
#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)
#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)
#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))
#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)
#define ANA_DSCP_CFG_RSZ 0x4
#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))
#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)
#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)
#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))
#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)
#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)
#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
#define ANA_DSCP_REWR_CFG_RSZ 0x4
#define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4
#define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4
#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))
#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)
#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))
#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)
#define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
#define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
#define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
#define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
#define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
#define ANA_FID_CFG_VID_MC_ENA BIT(0)
#define ANA_POL_PIR_CFG_GSZ 0x20
#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))
#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)
#define ANA_POL_CIR_CFG_GSZ 0x20
#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
#define ANA_POL_MODE_CFG_GSZ 0x20
#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))
#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)
#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)
#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))
#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)
#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)
#define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
#define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
#define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
#define ANA_POL_PIR_STATE_GSZ 0x20
#define ANA_POL_CIR_STATE_GSZ 0x20
#define ANA_POL_STATE_GSZ 0x20
#define ANA_POL_FLOWC_RSZ 0x4
#define ANA_POL_FLOWC_POL_FLOWC BIT(0)
#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))
#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)
#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)
#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))
#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)
#define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
#define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)
#endif
linux-7.2.3/include/soc/mscc/ocelot_dev.h
+220
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@@ -0,0 +1,220 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_DEV_H_
#define _MSCC_OCELOT_DEV_H_
#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
#define DEV_CLOCK_CFG_PORT_RST BIT(3)
#define DEV_CLOCK_CFG_PHY_RST BIT(2)
#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
#define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
#define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
#define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
#define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
#define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
#define DEV_EEE_CFG_EEE_ENA BIT(22)
#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
#define DEV_EEE_CFG_PORT_LPI BIT(0)
#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))
#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
#define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
#define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1)
#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
#define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
#define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
#define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
#define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
#define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
#define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
#define DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA BIT(0)
#define DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA BIT(4)
#define DEV_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D BIT(8)
#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS BIT(0)
#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) (((x) << 4) & GENMASK(11, 4))
#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M GENMASK(11, 4)
#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) (((x) & GENMASK(11, 4)) >> 4)
#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) (((x) << 12) & GENMASK(13, 12))
#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M GENMASK(13, 12)
#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12)
#define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS BIT(0)
#define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY BIT(4)
#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8))
#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8)
#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8)
#define DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY BIT(12)
#define DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY BIT(16)
#define DEV_MM_STAT_MM_STATUS_MM_RX_FRAME_STATUS BIT(20)
#define DEV_MM_STAT_MM_STATUS_MM_TX_FRAME_STATUS BIT(24)
#define DEV_MM_STAT_MM_STATUS_MM_TX_PRMPT_STATUS BIT(28)
#define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
#define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
#define PCS1G_CFG_PCS_ENA BIT(0)
#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
#define PCS1G_SD_CFG_SD_SEL BIT(8)
#define PCS1G_SD_CFG_SD_POL BIT(4)
#define PCS1G_SD_CFG_SD_ENA BIT(0)
#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)
#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
#define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))
#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)
#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
#define PCS1G_LB_CFG_RA_ENA BIT(4)
#define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
#define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
#define PCS1G_DBG_CFG_UDLT BIT(0)
#define PCS1G_CDET_CFG_CDET_ENA BIT(0)
#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)
#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define PCS1G_ANEG_STATUS_PR BIT(4)
#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
#define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))
#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)
#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)
#define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
#define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
#define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
#define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
#define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
#define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
#define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))
#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)
#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
#define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
#define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
#define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
#define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
#define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
#define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
#define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
#define DEV_PCS_FX100_CFG_SD_POL BIT(25)
#define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
#define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
#define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))
#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)
#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)
#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))
#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)
#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)
#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))
#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
#define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
#define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
#define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
#define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
#define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
#endif
linux-7.2.3/include/soc/mscc/ocelot_hsio.h
+859
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@@ -0,0 +1,859 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_HSIO_H_
#define _MSCC_OCELOT_HSIO_H_
#define HSIO_PLL5G_CFG0 0x0000
#define HSIO_PLL5G_CFG1 0x0004
#define HSIO_PLL5G_CFG2 0x0008
#define HSIO_PLL5G_CFG3 0x000c
#define HSIO_PLL5G_CFG4 0x0010
#define HSIO_PLL5G_CFG5 0x0014
#define HSIO_PLL5G_CFG6 0x0018
#define HSIO_PLL5G_STATUS0 0x001c
#define HSIO_PLL5G_STATUS1 0x0020
#define HSIO_PLL5G_BIST_CFG0 0x0024
#define HSIO_PLL5G_BIST_CFG1 0x0028
#define HSIO_PLL5G_BIST_CFG2 0x002c
#define HSIO_PLL5G_BIST_STAT0 0x0030
#define HSIO_PLL5G_BIST_STAT1 0x0034
#define HSIO_RCOMP_CFG0 0x0038
#define HSIO_RCOMP_STATUS 0x003c
#define HSIO_SYNC_ETH_CFG 0x0040
#define HSIO_SYNC_ETH_PLL_CFG 0x0048
#define HSIO_S1G_DES_CFG 0x004c
#define HSIO_S1G_IB_CFG 0x0050
#define HSIO_S1G_OB_CFG 0x0054
#define HSIO_S1G_SER_CFG 0x0058
#define HSIO_S1G_COMMON_CFG 0x005c
#define HSIO_S1G_PLL_CFG 0x0060
#define HSIO_S1G_PLL_STATUS 0x0064
#define HSIO_S1G_DFT_CFG0 0x0068
#define HSIO_S1G_DFT_CFG1 0x006c
#define HSIO_S1G_DFT_CFG2 0x0070
#define HSIO_S1G_TP_CFG 0x0074
#define HSIO_S1G_RC_PLL_BIST_CFG 0x0078
#define HSIO_S1G_MISC_CFG 0x007c
#define HSIO_S1G_DFT_STATUS 0x0080
#define HSIO_S1G_MISC_STATUS 0x0084
#define HSIO_MCB_S1G_ADDR_CFG 0x0088
#define HSIO_S6G_DIG_CFG 0x008c
#define HSIO_S6G_DFT_CFG0 0x0090
#define HSIO_S6G_DFT_CFG1 0x0094
#define HSIO_S6G_DFT_CFG2 0x0098
#define HSIO_S6G_TP_CFG0 0x009c
#define HSIO_S6G_TP_CFG1 0x00a0
#define HSIO_S6G_RC_PLL_BIST_CFG 0x00a4
#define HSIO_S6G_MISC_CFG 0x00a8
#define HSIO_S6G_OB_ANEG_CFG 0x00ac
#define HSIO_S6G_DFT_STATUS 0x00b0
#define HSIO_S6G_ERR_CNT 0x00b4
#define HSIO_S6G_MISC_STATUS 0x00b8
#define HSIO_S6G_DES_CFG 0x00bc
#define HSIO_S6G_IB_CFG 0x00c0
#define HSIO_S6G_IB_CFG1 0x00c4
#define HSIO_S6G_IB_CFG2 0x00c8
#define HSIO_S6G_IB_CFG3 0x00cc
#define HSIO_S6G_IB_CFG4 0x00d0
#define HSIO_S6G_IB_CFG5 0x00d4
#define HSIO_S6G_OB_CFG 0x00d8
#define HSIO_S6G_OB_CFG1 0x00dc
#define HSIO_S6G_SER_CFG 0x00e0
#define HSIO_S6G_COMMON_CFG 0x00e4
#define HSIO_S6G_PLL_CFG 0x00e8
#define HSIO_S6G_ACJTAG_CFG 0x00ec
#define HSIO_S6G_GP_CFG 0x00f0
#define HSIO_S6G_IB_STATUS0 0x00f4
#define HSIO_S6G_IB_STATUS1 0x00f8
#define HSIO_S6G_ACJTAG_STATUS 0x00fc
#define HSIO_S6G_PLL_STATUS 0x0100
#define HSIO_S6G_REVID 0x0104
#define HSIO_MCB_S6G_ADDR_CFG 0x0108
#define HSIO_HW_CFG 0x010c
#define HSIO_HW_QSGMII_CFG 0x0110
#define HSIO_HW_QSGMII_STAT 0x0114
#define HSIO_CLK_CFG 0x0118
#define HSIO_TEMP_SENSOR_CTRL 0x011c
#define HSIO_TEMP_SENSOR_CFG 0x0120
#define HSIO_TEMP_SENSOR_STAT 0x0124
#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
#define HSIO_PLL5G_CFG0_DIV4 BIT(28)
#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))
#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
#define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
#define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))
#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)
#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19))
#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19)
#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19)
#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))
#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)
#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20))
#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20)
#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20)
#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16)
#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16)
#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))
#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)
#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))
#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))
#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)
#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21))
#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21)
#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21)
#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16))
#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16)
#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16)
#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4))
#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4)
#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4)
#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1))
#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1)
#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16))
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16)
#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4)
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16))
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)
#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10))
#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10)
#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10)
#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))
#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)
#define HSIO_RCOMP_STATUS_BUSY BIT(12)
#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))
#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
#define HSIO_SYNC_ETH_CFG_RSZ 0x4
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1))
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11))
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11)
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11)
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)
#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5))
#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5)
#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5)
#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1))
#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1)
#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24))
#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24)
#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24)
#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19))
#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19)
#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19)
#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4))
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4)
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4)
#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)
#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))
#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)
#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13))
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13)
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10))
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10)
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4)
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13))
#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13)
#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13)
#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
#define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16))
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))
#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)
#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3))
#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3)
#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3)
#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))
#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)
#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16))
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13))
#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13)
#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13)
#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13))
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)
#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10))
#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10)
#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5))
#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5)
#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5)
#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1))
#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1)
#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29))
#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29)
#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29)
#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24))
#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24)
#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24)
#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))
#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)
#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)
#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15))
#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15)
#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13))
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11))
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)
#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17))
#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17)
#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17)
#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12))
#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12)
#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12)
#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))
#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)
#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)
#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27))
#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27)
#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27)
#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22))
#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22)
#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22)
#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19))
#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19)
#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19)
#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))
#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)
#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10))
#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10)
#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10)
#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))
#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)
#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)
#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3))
#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3)
#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3)
#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))
#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)
#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12))
#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12)
#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6))
#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6)
#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))
#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)
#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12))
#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12)
#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6))
#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6)
#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))
#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)
#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12))
#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12)
#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6))
#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6)
#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))
#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)
#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
#define HSIO_S6G_OB_CFG_OB_POL BIT(29)
#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))
#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)
#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)
#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11))
#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11)
#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11)
#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4))
#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4)
#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)
#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))
#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)
#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))
#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)
#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)
#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
#define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
#define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))
#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)
#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16))
#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16)
#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16)
#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6)
#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16))
#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16)
#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))
#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)
#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)
#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12))
#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12)
#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12)
#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6))
#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6)
#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6)
#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))
#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)
#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26))
#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26)
#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26)
#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21))
#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21)
#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21)
#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16))
#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16)
#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16)
#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10))
#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10)
#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10)
#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))
#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)
#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)
#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))
#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)
#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
#define HSIO_HW_CFG_PCIE_ENA BIT(1)
#define HSIO_HW_CFG_QSGMII_ENA BIT(0)
#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1))
#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1)
#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1)
#define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))
#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)
#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)
#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))
#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)
#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))
#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)
#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)
#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))
#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)
#endif
linux-7.2.3/include/soc/mscc/ocelot_ptp.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* License: Dual MIT/GPL
* Copyright (c) 2017 Microsemi Corporation
* Copyright 2020 NXP
*/
#ifndef _MSCC_OCELOT_PTP_H_
#define _MSCC_OCELOT_PTP_H_
#include <linux/ptp_clock_kernel.h>
#include <soc/mscc/ocelot.h>
#define OCELOT_MAX_PTP_ID 63
#define OCELOT_PTP_FIFO_SIZE 128
#define PTP_PIN_CFG_RSZ 0x20
#define PTP_PIN_TOD_SEC_MSB_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_TOD_SEC_LSB_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_TOD_NSEC_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_WF_HIGH_PERIOD_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_WF_LOW_PERIOD_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_CFG_DOM BIT(0)
#define PTP_PIN_CFG_SYNC BIT(2)
#define PTP_PIN_CFG_ACTION(x) ((x) << 3)
#define PTP_PIN_CFG_ACTION_MASK PTP_PIN_CFG_ACTION(0x7)
enum {
PTP_PIN_ACTION_IDLE = 0,
PTP_PIN_ACTION_LOAD,
PTP_PIN_ACTION_SAVE,
PTP_PIN_ACTION_CLOCK,
PTP_PIN_ACTION_DELTA,
PTP_PIN_ACTION_NOSYNC,
PTP_PIN_ACTION_SYNC,
};
#define PTP_CFG_MISC_PTP_EN BIT(2)
#define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0)
#define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1)
#define PTP_CFG_CLK_ADJ_FREQ_NS BIT(30)
int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
const struct timespec64 *ts);
int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta);
int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm);
int ocelot_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
enum ptp_pin_function func, unsigned int chan);
int ocelot_ptp_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on);
int ocelot_init_timestamp(struct ocelot *ocelot,
const struct ptp_clock_info *info);
int ocelot_deinit_timestamp(struct ocelot *ocelot);
#endif
linux-7.2.3/include/soc/mscc/ocelot_qsys.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_QSYS_H_
#define _MSCC_OCELOT_QSYS_H_
#define QSYS_PORT_MODE_RSZ 0x4
#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
#define QSYS_EEE_CFG_RSZ 0x4
#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
#define QSYS_SW_STATUS_RSZ 0x4
#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
#define QSYS_QMAP_GSZ 0x4
#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))
#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)
#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))
#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)
#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))
#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
#define QSYS_ISDX_SGRP_GSZ 0x4
#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4
#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)
#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))
#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
#define QSYS_RED_PROFILE_RSZ 0x4
#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))
#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
#define QSYS_RES_CFG_GSZ 0x8
#define QSYS_RES_STAT_GSZ 0x8
#define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x) ((x) & GENMASK(15, 0))
#define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT_M GENMASK(15, 0)
#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))
#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)
#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)
#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))
#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)
#define QSYS_QMAXSDU_CFG_0_RSZ 0x4
#define QSYS_QMAXSDU_CFG_1_RSZ 0x4
#define QSYS_QMAXSDU_CFG_2_RSZ 0x4
#define QSYS_QMAXSDU_CFG_3_RSZ 0x4
#define QSYS_QMAXSDU_CFG_4_RSZ 0x4
#define QSYS_QMAXSDU_CFG_5_RSZ 0x4
#define QSYS_QMAXSDU_CFG_6_RSZ 0x4
#define QSYS_QMAXSDU_CFG_7_RSZ 0x4
#define QSYS_PREEMPTION_CFG_RSZ 0x4
#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))
#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)
#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))
#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)
#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)
#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))
#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)
#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define QSYS_CIR_CFG_GSZ 0x80
#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
#define QSYS_EIR_CFG_GSZ 0x80
#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))
#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)
#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)
#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))
#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)
#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)
#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
#define QSYS_SE_CFG_GSZ 0x80
#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))
#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)
#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)
#define QSYS_SE_CFG_SE_RR_ENA BIT(5)
#define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))
#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)
#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
#define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
#define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
#define QSYS_SE_DWRR_CFG_GSZ 0x80
#define QSYS_SE_DWRR_CFG_RSZ 0x4
#define QSYS_SE_CONNECT_GSZ 0x80
#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))
#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)
#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)
#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))
#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)
#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)
#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))
#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)
#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)
#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
#define QSYS_SE_DLB_SENSE_GSZ 0x80
#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))
#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)
#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)
#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))
#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)
#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)
#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))
#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)
#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)
#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
#define QSYS_CIR_STATE_GSZ 0x80
#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))
#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)
#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)
#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))
#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)
#define QSYS_EIR_STATE_GSZ 0x80
#define QSYS_SE_STATE_GSZ 0x80
#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))
#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)
#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)
#define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))
#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)
#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)
#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
#define QSYS_TAG_CONFIG_RSZ 0x4
#define QSYS_TAG_CONFIG_ENABLE BIT(0)
#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))
#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)
#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)
#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))
#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)
#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)
#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))
#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)
#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
#define QSYS_PORT_MAX_SDU_RSZ 0x4
#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)
#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)
#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))
#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)
#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)
#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
#endif
linux-7.2.3/include/soc/mscc/ocelot_sys.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_SYS_H_
#define _MSCC_OCELOT_SYS_H_
#define SYS_COUNT_RX_OCTETS_RSZ 0x4
#define SYS_COUNT_TX_OCTETS_RSZ 0x4
#define SYS_FRONT_PORT_MODE_RSZ 0x4
#define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0)
#define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
#define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
#define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
#define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
#define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
#define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
#define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
#define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
#define SYS_SW_STATUS_RSZ 0x4
#define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0)
#define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1)
#define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0)
#define SYS_REW_MAC_HIGH_CFG_RSZ 0x4
#define SYS_REW_MAC_LOW_CFG_RSZ 0x4
#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0))
#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9))
#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9)
#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0))
#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
#define SYS_ATOP_RSZ 0x4
#define SYS_MAC_FC_CFG_RSZ 0x4
#define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26))
#define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26)
#define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20))
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20)
#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
#define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
#define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0))
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0)
#define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16))
#define SYS_MMGT_RELCNT_M GENMASK(31, 16)
#define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0))
#define SYS_MMGT_FREECNT_M GENMASK(15, 0)
#define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4))
#define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
#define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4)
#define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0))
#define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
#define SYS_EVENTS_DIF_RSZ 0x4
#define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6))
#define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
#define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6)
#define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0))
#define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0)
#define SYS_EVENTS_CORE_EV_FWR BIT(2)
#define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0))
#define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0)
#define SYS_CNT_GSZ 0x4
#define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29)
#define SYS_PTP_STATUS_PTP_OVFL BIT(28)
#define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27)
#define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21))
#define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21)
#define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21)
#define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16))
#define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16)
#define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16)
#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0))
#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0)
#define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0))
#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0)
#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31)
#define SYS_PTP_NXT_PTP_NXT BIT(0)
#define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2))
#define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2)
#define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2)
#define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0))
#define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0)
#define SYS_RAM_INIT_RAM_INIT BIT(1)
#define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0)
#endif
linux-7.2.3/include/soc/mscc/ocelot_vcap.h
+733
View File
@@ -0,0 +1,733 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
* Microsemi Ocelot Switch driver
* Copyright (c) 2019 Microsemi Corporation
*/
#ifndef _OCELOT_VCAP_H_
#define _OCELOT_VCAP_H_
#include <soc/mscc/ocelot.h>
/* Cookie definitions for private VCAP filters installed by the driver.
* Must be unique per VCAP block.
*/
#define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream) ((upstream) << 16 | (port))
#define OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port) (port)
#define OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port) ((ocelot)->num_phys_ports + (port))
#define OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port) (port)
#define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port))
#define OCELOT_VCAP_IS2_MRP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2)
#define OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 1)
#define OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 2)
#define OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 3)
#define OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 4)
#define OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 5)
/* =================================================================
* VCAP Common
* =================================================================
*/
enum {
VCAP_ES0,
VCAP_IS1,
VCAP_IS2,
__VCAP_COUNT,
};
#define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT
struct vcap_props {
u16 tg_width; /* Type-group width (in bits) */
u16 sw_count; /* Sub word count */
u16 entry_count; /* Entry count */
u16 entry_words; /* Number of entry words */
u16 entry_width; /* Entry width (in bits) */
u16 action_count; /* Action count */
u16 action_words; /* Number of action words */
u16 action_width; /* Action width (in bits) */
u16 action_type_width; /* Action type width (in bits) */
struct {
u16 width; /* Action type width (in bits) */
u16 count; /* Action type sub word count */
} action_table[2];
u16 counter_words; /* Number of counter words */
u16 counter_width; /* Counter width (in bits) */
enum ocelot_target target;
const struct vcap_field *keys;
const struct vcap_field *actions;
};
/* VCAP Type-Group values */
#define VCAP_TG_NONE 0 /* Entry is invalid */
#define VCAP_TG_FULL 1 /* Full entry */
#define VCAP_TG_HALF 2 /* Half entry */
#define VCAP_TG_QUARTER 3 /* Quarter entry */
#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))
#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))
#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)
#define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
#define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
#define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
#define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))
#define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)
#define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))
#define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)
#define VCAP_CACHE_ENTRY_DAT_RSZ 0x4
#define VCAP_CACHE_MASK_DAT_RSZ 0x4
#define VCAP_CACHE_ACTION_DAT_RSZ 0x4
#define VCAP_CACHE_CNT_DAT_RSZ 0x4
#define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
#define TCAM_BIST_CTRL_TCAM_BIST BIT(1)
#define TCAM_BIST_CTRL_TCAM_INIT BIT(0)
#define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
#define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7)
#define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6)
#define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))
#define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)
#define TCAM_BIST_STAT_BIST_RT_ERR BIT(15)
#define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14)
#define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13)
#define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12)
#define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11)
#define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10)
#define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9)
#define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8)
#define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7)
#define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6)
#define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5)
#define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4)
#define TCAM_BIST_STAT_BIST_RUN BIT(3)
#define TCAM_BIST_STAT_BIST_ERR BIT(2)
#define TCAM_BIST_STAT_BIST_BUSY BIT(1)
#define TCAM_BIST_STAT_TCAM_RDY BIT(0)
/* =================================================================
* VCAP IS2
* =================================================================
*/
/* IS2 half key types */
#define IS2_TYPE_ETYPE 0
#define IS2_TYPE_LLC 1
#define IS2_TYPE_SNAP 2
#define IS2_TYPE_ARP 3
#define IS2_TYPE_IP_UDP_TCP 4
#define IS2_TYPE_IP_OTHER 5
#define IS2_TYPE_IPV6 6
#define IS2_TYPE_OAM 7
#define IS2_TYPE_SMAC_SIP6 8
#define IS2_TYPE_ANY 100 /* Pseudo type */
/* IS2 half key type mask for matching any IP */
#define IS2_TYPE_MASK_IP_ANY 0xe
enum {
IS2_ACTION_TYPE_NORMAL,
IS2_ACTION_TYPE_SMAC_SIP,
IS2_ACTION_TYPE_MAX,
};
/* IS2 MASK_MODE values */
#define IS2_ACT_MASK_MODE_NONE 0
#define IS2_ACT_MASK_MODE_FILTER 1
#define IS2_ACT_MASK_MODE_POLICY 2
#define IS2_ACT_MASK_MODE_REDIR 3
/* IS2 REW_OP values */
#define IS2_ACT_REW_OP_NONE 0
#define IS2_ACT_REW_OP_PTP_ONE 2
#define IS2_ACT_REW_OP_PTP_TWO 3
#define IS2_ACT_REW_OP_SPECIAL 8
#define IS2_ACT_REW_OP_PTP_ORG 9
#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
#define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
#define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
#define VCAP_PORT_WIDTH 4
/* IS2 quarter key - SMAC_SIP4 */
#define IS2_QKO_IGR_PORT 0
#define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
#define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
#define IS2_QKL_L2_SMAC 48
#define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
#define IS2_QKL_L3_IP4_SIP 32
enum vcap_is2_half_key_field {
/* Common */
VCAP_IS2_TYPE,
VCAP_IS2_HK_FIRST,
VCAP_IS2_HK_PAG,
VCAP_IS2_HK_RSV1,
VCAP_IS2_HK_IGR_PORT_MASK,
VCAP_IS2_HK_RSV2,
VCAP_IS2_HK_HOST_MATCH,
VCAP_IS2_HK_L2_MC,
VCAP_IS2_HK_L2_BC,
VCAP_IS2_HK_VLAN_TAGGED,
VCAP_IS2_HK_VID,
VCAP_IS2_HK_DEI,
VCAP_IS2_HK_PCP,
/* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
VCAP_IS2_HK_L2_DMAC,
VCAP_IS2_HK_L2_SMAC,
/* MAC_ETYPE (TYPE=000) */
VCAP_IS2_HK_MAC_ETYPE_ETYPE,
VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,
VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,
/* MAC_LLC (TYPE=001) */
VCAP_IS2_HK_MAC_LLC_DMAC,
VCAP_IS2_HK_MAC_LLC_SMAC,
VCAP_IS2_HK_MAC_LLC_L2_LLC,
/* MAC_SNAP (TYPE=010) */
VCAP_IS2_HK_MAC_SNAP_SMAC,
VCAP_IS2_HK_MAC_SNAP_DMAC,
VCAP_IS2_HK_MAC_SNAP_L2_SNAP,
/* MAC_ARP (TYPE=011) */
VCAP_IS2_HK_MAC_ARP_SMAC,
VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,
VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,
VCAP_IS2_HK_MAC_ARP_LEN_OK,
VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,
VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,
VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,
VCAP_IS2_HK_MAC_ARP_OPCODE,
VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,
VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,
VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,
/* IP4_TCP_UDP / IP4_OTHER common */
VCAP_IS2_HK_IP4,
VCAP_IS2_HK_L3_FRAGMENT,
VCAP_IS2_HK_L3_FRAG_OFS_GT0,
VCAP_IS2_HK_L3_OPTIONS,
VCAP_IS2_HK_IP4_L3_TTL_GT0,
VCAP_IS2_HK_L3_TOS,
VCAP_IS2_HK_L3_IP4_DIP,
VCAP_IS2_HK_L3_IP4_SIP,
VCAP_IS2_HK_DIP_EQ_SIP,
/* IP4_TCP_UDP (TYPE=100) */
VCAP_IS2_HK_TCP,
VCAP_IS2_HK_L4_SPORT,
VCAP_IS2_HK_L4_DPORT,
VCAP_IS2_HK_L4_RNG,
VCAP_IS2_HK_L4_SPORT_EQ_DPORT,
VCAP_IS2_HK_L4_SEQUENCE_EQ0,
VCAP_IS2_HK_L4_URG,
VCAP_IS2_HK_L4_ACK,
VCAP_IS2_HK_L4_PSH,
VCAP_IS2_HK_L4_RST,
VCAP_IS2_HK_L4_SYN,
VCAP_IS2_HK_L4_FIN,
VCAP_IS2_HK_L4_1588_DOM,
VCAP_IS2_HK_L4_1588_VER,
/* IP4_OTHER (TYPE=101) */
VCAP_IS2_HK_IP4_L3_PROTO,
VCAP_IS2_HK_L3_PAYLOAD,
/* IP6_STD (TYPE=110) */
VCAP_IS2_HK_IP6_L3_TTL_GT0,
VCAP_IS2_HK_IP6_L3_PROTO,
VCAP_IS2_HK_L3_IP6_SIP,
/* OAM (TYPE=111) */
VCAP_IS2_HK_OAM_MEL_FLAGS,
VCAP_IS2_HK_OAM_VER,
VCAP_IS2_HK_OAM_OPCODE,
VCAP_IS2_HK_OAM_FLAGS,
VCAP_IS2_HK_OAM_MEPID,
VCAP_IS2_HK_OAM_CCM_CNTS_EQ0,
VCAP_IS2_HK_OAM_IS_Y1731,
};
struct vcap_field {
int offset;
int length;
};
enum vcap_is2_action_field {
VCAP_IS2_ACT_HIT_ME_ONCE,
VCAP_IS2_ACT_CPU_COPY_ENA,
VCAP_IS2_ACT_CPU_QU_NUM,
VCAP_IS2_ACT_MASK_MODE,
VCAP_IS2_ACT_MIRROR_ENA,
VCAP_IS2_ACT_LRN_DIS,
VCAP_IS2_ACT_POLICE_ENA,
VCAP_IS2_ACT_POLICE_IDX,
VCAP_IS2_ACT_POLICE_VCAP_ONLY,
VCAP_IS2_ACT_PORT_MASK,
VCAP_IS2_ACT_REW_OP,
VCAP_IS2_ACT_SMAC_REPLACE_ENA,
VCAP_IS2_ACT_RSV,
VCAP_IS2_ACT_ACL_ID,
VCAP_IS2_ACT_HIT_CNT,
};
/* =================================================================
* VCAP IS1
* =================================================================
*/
/* IS1 half key types */
#define IS1_TYPE_S1_NORMAL 0
#define IS1_TYPE_S1_5TUPLE_IP4 1
/* IS1 full key types */
#define IS1_TYPE_S1_NORMAL_IP6 0
#define IS1_TYPE_S1_7TUPLE 1
#define IS2_TYPE_S1_5TUPLE_IP6 2
enum {
IS1_ACTION_TYPE_NORMAL,
IS1_ACTION_TYPE_MAX,
};
enum vcap_is1_half_key_field {
VCAP_IS1_HK_TYPE,
VCAP_IS1_HK_LOOKUP,
VCAP_IS1_HK_IGR_PORT_MASK,
VCAP_IS1_HK_RSV,
VCAP_IS1_HK_OAM_Y1731,
VCAP_IS1_HK_L2_MC,
VCAP_IS1_HK_L2_BC,
VCAP_IS1_HK_IP_MC,
VCAP_IS1_HK_VLAN_TAGGED,
VCAP_IS1_HK_VLAN_DBL_TAGGED,
VCAP_IS1_HK_TPID,
VCAP_IS1_HK_VID,
VCAP_IS1_HK_DEI,
VCAP_IS1_HK_PCP,
/* Specific Fields for IS1 Half Key S1_NORMAL */
VCAP_IS1_HK_L2_SMAC,
VCAP_IS1_HK_ETYPE_LEN,
VCAP_IS1_HK_ETYPE,
VCAP_IS1_HK_IP_SNAP,
VCAP_IS1_HK_IP4,
VCAP_IS1_HK_L3_FRAGMENT,
VCAP_IS1_HK_L3_FRAG_OFS_GT0,
VCAP_IS1_HK_L3_OPTIONS,
VCAP_IS1_HK_L3_DSCP,
VCAP_IS1_HK_L3_IP4_SIP,
VCAP_IS1_HK_TCP_UDP,
VCAP_IS1_HK_TCP,
VCAP_IS1_HK_L4_SPORT,
VCAP_IS1_HK_L4_RNG,
/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
VCAP_IS1_HK_IP4_INNER_TPID,
VCAP_IS1_HK_IP4_INNER_VID,
VCAP_IS1_HK_IP4_INNER_DEI,
VCAP_IS1_HK_IP4_INNER_PCP,
VCAP_IS1_HK_IP4_IP4,
VCAP_IS1_HK_IP4_L3_FRAGMENT,
VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0,
VCAP_IS1_HK_IP4_L3_OPTIONS,
VCAP_IS1_HK_IP4_L3_DSCP,
VCAP_IS1_HK_IP4_L3_IP4_DIP,
VCAP_IS1_HK_IP4_L3_IP4_SIP,
VCAP_IS1_HK_IP4_L3_PROTO,
VCAP_IS1_HK_IP4_TCP_UDP,
VCAP_IS1_HK_IP4_TCP,
VCAP_IS1_HK_IP4_L4_RNG,
VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE,
};
enum vcap_is1_action_field {
VCAP_IS1_ACT_DSCP_ENA,
VCAP_IS1_ACT_DSCP_VAL,
VCAP_IS1_ACT_QOS_ENA,
VCAP_IS1_ACT_QOS_VAL,
VCAP_IS1_ACT_DP_ENA,
VCAP_IS1_ACT_DP_VAL,
VCAP_IS1_ACT_PAG_OVERRIDE_MASK,
VCAP_IS1_ACT_PAG_VAL,
VCAP_IS1_ACT_RSV,
VCAP_IS1_ACT_VID_REPLACE_ENA,
VCAP_IS1_ACT_VID_ADD_VAL,
VCAP_IS1_ACT_FID_SEL,
VCAP_IS1_ACT_FID_VAL,
VCAP_IS1_ACT_PCP_DEI_ENA,
VCAP_IS1_ACT_PCP_VAL,
VCAP_IS1_ACT_DEI_VAL,
VCAP_IS1_ACT_VLAN_POP_CNT_ENA,
VCAP_IS1_ACT_VLAN_POP_CNT,
VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA,
VCAP_IS1_ACT_HIT_STICKY,
};
/* =================================================================
* VCAP ES0
* =================================================================
*/
enum {
ES0_ACTION_TYPE_NORMAL,
ES0_ACTION_TYPE_MAX,
};
enum vcap_es0_key_field {
VCAP_ES0_EGR_PORT,
VCAP_ES0_IGR_PORT,
VCAP_ES0_RSV,
VCAP_ES0_L2_MC,
VCAP_ES0_L2_BC,
VCAP_ES0_VID,
VCAP_ES0_DP,
VCAP_ES0_PCP,
};
enum vcap_es0_action_field {
VCAP_ES0_ACT_PUSH_OUTER_TAG,
VCAP_ES0_ACT_PUSH_INNER_TAG,
VCAP_ES0_ACT_TAG_A_TPID_SEL,
VCAP_ES0_ACT_TAG_A_VID_SEL,
VCAP_ES0_ACT_TAG_A_PCP_SEL,
VCAP_ES0_ACT_TAG_A_DEI_SEL,
VCAP_ES0_ACT_TAG_B_TPID_SEL,
VCAP_ES0_ACT_TAG_B_VID_SEL,
VCAP_ES0_ACT_TAG_B_PCP_SEL,
VCAP_ES0_ACT_TAG_B_DEI_SEL,
VCAP_ES0_ACT_VID_A_VAL,
VCAP_ES0_ACT_PCP_A_VAL,
VCAP_ES0_ACT_DEI_A_VAL,
VCAP_ES0_ACT_VID_B_VAL,
VCAP_ES0_ACT_PCP_B_VAL,
VCAP_ES0_ACT_DEI_B_VAL,
VCAP_ES0_ACT_RSV,
VCAP_ES0_ACT_HIT_STICKY,
};
struct ocelot_ipv4 {
u8 addr[4];
};
enum ocelot_vcap_bit {
OCELOT_VCAP_BIT_ANY,
OCELOT_VCAP_BIT_0,
OCELOT_VCAP_BIT_1
};
struct ocelot_vcap_u8 {
u8 value[1];
u8 mask[1];
};
struct ocelot_vcap_u16 {
u8 value[2];
u8 mask[2];
};
struct ocelot_vcap_u24 {
u8 value[3];
u8 mask[3];
};
struct ocelot_vcap_u32 {
u8 value[4];
u8 mask[4];
};
struct ocelot_vcap_u40 {
u8 value[5];
u8 mask[5];
};
struct ocelot_vcap_u48 {
u8 value[6];
u8 mask[6];
};
struct ocelot_vcap_u64 {
u8 value[8];
u8 mask[8];
};
struct ocelot_vcap_u128 {
u8 value[16];
u8 mask[16];
};
struct ocelot_vcap_vid {
u16 value;
u16 mask;
};
struct ocelot_vcap_ipv4 {
struct ocelot_ipv4 value;
struct ocelot_ipv4 mask;
};
struct ocelot_vcap_udp_tcp {
u16 value;
u16 mask;
};
struct ocelot_vcap_port {
u8 value;
u8 mask;
};
enum ocelot_vcap_key_type {
OCELOT_VCAP_KEY_ANY,
OCELOT_VCAP_KEY_ETYPE,
OCELOT_VCAP_KEY_LLC,
OCELOT_VCAP_KEY_SNAP,
OCELOT_VCAP_KEY_ARP,
OCELOT_VCAP_KEY_IPV4,
OCELOT_VCAP_KEY_IPV6
};
struct ocelot_vcap_key_vlan {
struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */
struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */
enum ocelot_vcap_bit dei; /* DEI */
enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */
enum ocelot_vcap_bit tpid;
};
struct ocelot_vcap_key_etype {
struct ocelot_vcap_u48 dmac;
struct ocelot_vcap_u48 smac;
struct ocelot_vcap_u16 etype;
struct ocelot_vcap_u16 data; /* MAC data */
};
struct ocelot_vcap_key_llc {
struct ocelot_vcap_u48 dmac;
struct ocelot_vcap_u48 smac;
/* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */
struct ocelot_vcap_u32 llc;
};
struct ocelot_vcap_key_snap {
struct ocelot_vcap_u48 dmac;
struct ocelot_vcap_u48 smac;
/* SNAP header: Organization Code at byte 0, Type at byte 3 */
struct ocelot_vcap_u40 snap;
};
struct ocelot_vcap_key_arp {
struct ocelot_vcap_u48 smac;
enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */
enum ocelot_vcap_bit req; /* Opcode request/reply */
enum ocelot_vcap_bit unknown; /* Opcode unknown */
enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */
enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */
/**< Protocol addr. length 4, hardware length 6 */
enum ocelot_vcap_bit length;
enum ocelot_vcap_bit ip; /* Protocol address type IP */
enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */
struct ocelot_vcap_ipv4 sip; /* Sender IP address */
struct ocelot_vcap_ipv4 dip; /* Target IP address */
};
struct ocelot_vcap_key_ipv4 {
enum ocelot_vcap_bit ttl; /* TTL zero */
enum ocelot_vcap_bit fragment; /* Fragment */
enum ocelot_vcap_bit options; /* Header options */
struct ocelot_vcap_u8 ds;
struct ocelot_vcap_u8 proto; /* Protocol */
struct ocelot_vcap_ipv4 sip; /* Source IP address */
struct ocelot_vcap_ipv4 dip; /* Destination IP address */
struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */
struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */
enum ocelot_vcap_bit tcp_fin;
enum ocelot_vcap_bit tcp_syn;
enum ocelot_vcap_bit tcp_rst;
enum ocelot_vcap_bit tcp_psh;
enum ocelot_vcap_bit tcp_ack;
enum ocelot_vcap_bit tcp_urg;
enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
};
struct ocelot_vcap_key_ipv6 {
struct ocelot_vcap_u8 proto; /* IPv6 protocol */
struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */
struct ocelot_vcap_u128 dip; /* IPv6 destination (byte 0-7 ignored) */
enum ocelot_vcap_bit ttl; /* TTL zero */
struct ocelot_vcap_u8 ds;
struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
struct ocelot_vcap_udp_tcp sport;
struct ocelot_vcap_udp_tcp dport;
enum ocelot_vcap_bit tcp_fin;
enum ocelot_vcap_bit tcp_syn;
enum ocelot_vcap_bit tcp_rst;
enum ocelot_vcap_bit tcp_psh;
enum ocelot_vcap_bit tcp_ack;
enum ocelot_vcap_bit tcp_urg;
enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
};
enum ocelot_mask_mode {
OCELOT_MASK_MODE_NONE,
OCELOT_MASK_MODE_PERMIT_DENY,
OCELOT_MASK_MODE_POLICY,
OCELOT_MASK_MODE_REDIRECT,
};
enum ocelot_es0_vid_sel {
OCELOT_ES0_VID_PLUS_CLASSIFIED_VID = 0,
OCELOT_ES0_VID = 1,
};
enum ocelot_es0_pcp_sel {
OCELOT_CLASSIFIED_PCP = 0,
OCELOT_ES0_PCP = 1,
};
enum ocelot_es0_tag {
OCELOT_NO_ES0_TAG,
OCELOT_ES0_TAG,
OCELOT_FORCE_PORT_TAG,
OCELOT_FORCE_UNTAG,
};
enum ocelot_tag_tpid_sel {
OCELOT_TAG_TPID_SEL_8021Q,
OCELOT_TAG_TPID_SEL_8021AD,
};
struct ocelot_vcap_action {
union {
/* VCAP ES0 */
struct {
enum ocelot_es0_tag push_outer_tag;
enum ocelot_es0_tag push_inner_tag;
enum ocelot_tag_tpid_sel tag_a_tpid_sel;
int tag_a_vid_sel;
int tag_a_pcp_sel;
u16 vid_a_val;
u8 pcp_a_val;
u8 dei_a_val;
enum ocelot_tag_tpid_sel tag_b_tpid_sel;
int tag_b_vid_sel;
int tag_b_pcp_sel;
u16 vid_b_val;
u8 pcp_b_val;
u8 dei_b_val;
};
/* VCAP IS1 */
struct {
bool vid_replace_ena;
u16 vid;
bool vlan_pop_cnt_ena;
int vlan_pop_cnt;
bool pcp_dei_ena;
u8 pcp;
u8 dei;
bool qos_ena;
u8 qos_val;
u8 pag_override_mask;
u8 pag_val;
};
/* VCAP IS2 */
struct {
bool cpu_copy_ena;
u8 cpu_qu_num;
enum ocelot_mask_mode mask_mode;
unsigned long port_mask;
bool police_ena;
bool mirror_ena;
struct ocelot_policer pol;
u32 pol_ix;
};
};
};
struct ocelot_vcap_stats {
u64 bytes;
u64 pkts;
u64 used;
};
enum ocelot_vcap_filter_type {
OCELOT_VCAP_FILTER_DUMMY,
OCELOT_VCAP_FILTER_PAG,
OCELOT_VCAP_FILTER_OFFLOAD,
OCELOT_PSFP_FILTER_OFFLOAD,
};
struct ocelot_vcap_id {
unsigned long cookie;
bool tc_offload;
};
struct ocelot_vcap_filter {
struct list_head list;
enum ocelot_vcap_filter_type type;
int block_id;
int goto_target;
int lookup;
u8 pag;
u16 prio;
struct ocelot_vcap_id id;
struct ocelot_vcap_action action;
struct ocelot_vcap_stats stats;
/* For VCAP IS1 and IS2 */
bool take_ts;
bool is_trap;
unsigned long ingress_port_mask;
/* For VCAP ES0 */
struct ocelot_vcap_port ingress_port;
/* For VCAP IS2 mirrors and ES0 */
struct ocelot_vcap_port egress_port;
enum ocelot_vcap_bit dmac_mc;
enum ocelot_vcap_bit dmac_bc;
struct ocelot_vcap_key_vlan vlan;
enum ocelot_vcap_key_type key_type;
union {
/* OCELOT_VCAP_KEY_ANY: No specific fields */
struct ocelot_vcap_key_etype etype;
struct ocelot_vcap_key_llc llc;
struct ocelot_vcap_key_snap snap;
struct ocelot_vcap_key_arp arp;
struct ocelot_vcap_key_ipv4 ipv4;
struct ocelot_vcap_key_ipv6 ipv6;
} key;
};
int ocelot_vcap_filter_add(struct ocelot *ocelot,
struct ocelot_vcap_filter *rule,
struct netlink_ext_ack *extack);
int ocelot_vcap_filter_del(struct ocelot *ocelot,
struct ocelot_vcap_filter *rule);
int ocelot_vcap_filter_replace(struct ocelot *ocelot,
struct ocelot_vcap_filter *filter);
struct ocelot_vcap_filter *
ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block,
unsigned long cookie, bool tc_offload);
#endif /* _OCELOT_VCAP_H_ */
linux-7.2.3/include/soc/mscc/vsc7514_regs.h
+19
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* Copyright (c) 2021 Innovative Advantage Inc.
*/
#ifndef VSC7514_REGS_H
#define VSC7514_REGS_H
#include <soc/mscc/ocelot_vcap.h>
extern struct vcap_props vsc7514_vcap_props[];
extern const struct reg_field vsc7514_regfields[REGFIELD_MAX];
extern const u32 *vsc7514_regmap[TARGET_MAX];
#endif
linux-7.2.3/include/soc/nuvoton/clock-npcm8xx.h
+18
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SOC_NPCM8XX_CLOCK_H
#define __SOC_NPCM8XX_CLOCK_H
#include <linux/auxiliary_bus.h>
#include <linux/container_of.h>
struct npcm_clock_adev {
void __iomem *base;
struct auxiliary_device adev;
};
static inline struct npcm_clock_adev *to_npcm_clock_adev(struct auxiliary_device *_adev)
{
return container_of(_adev, struct npcm_clock_adev, adev);
}
#endif
linux-7.2.3/include/soc/qcom/cmd-db.h
+48
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __QCOM_COMMAND_DB_H__
#define __QCOM_COMMAND_DB_H__
#include <linux/err.h>
enum cmd_db_hw_type {
CMD_DB_HW_INVALID = 0,
CMD_DB_HW_MIN = 3,
CMD_DB_HW_ARC = CMD_DB_HW_MIN,
CMD_DB_HW_VRM = 4,
CMD_DB_HW_BCM = 5,
CMD_DB_HW_MAX = CMD_DB_HW_BCM,
CMD_DB_HW_ALL = 0xff,
};
#if IS_ENABLED(CONFIG_QCOM_COMMAND_DB)
u32 cmd_db_read_addr(const char *resource_id);
const void *cmd_db_read_aux_data(const char *resource_id, size_t *len);
bool cmd_db_match_resource_addr(u32 addr1, u32 addr2);
enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id);
int cmd_db_ready(void);
#else
static inline u32 cmd_db_read_addr(const char *resource_id)
{ return 0; }
static inline const void *cmd_db_read_aux_data(const char *resource_id, size_t *len)
{ return ERR_PTR(-ENODEV); }
static inline bool cmd_db_match_resource_addr(u32 addr1, u32 addr2)
{ return false; }
static inline enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id)
{ return -ENODEV; }
static inline int cmd_db_ready(void)
{ return -ENODEV; }
#endif /* CONFIG_QCOM_COMMAND_DB */
#endif /* __QCOM_COMMAND_DB_H__ */
linux-7.2.3/include/soc/qcom/ice.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __QCOM_ICE_H__
#define __QCOM_ICE_H__
#include <linux/blk-crypto.h>
#include <linux/types.h>
struct qcom_ice;
int qcom_ice_enable(struct qcom_ice *ice);
int qcom_ice_resume(struct qcom_ice *ice);
int qcom_ice_suspend(struct qcom_ice *ice);
int qcom_ice_program_key(struct qcom_ice *ice, unsigned int slot,
const struct blk_crypto_key *blk_key);
int qcom_ice_evict_key(struct qcom_ice *ice, int slot);
enum blk_crypto_key_type qcom_ice_get_supported_key_type(struct qcom_ice *ice);
int qcom_ice_derive_sw_secret(struct qcom_ice *ice,
const u8 *eph_key, size_t eph_key_size,
u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]);
int qcom_ice_generate_key(struct qcom_ice *ice,
u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
int qcom_ice_prepare_key(struct qcom_ice *ice,
const u8 *lt_key, size_t lt_key_size,
u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
int qcom_ice_import_key(struct qcom_ice *ice,
const u8 *raw_key, size_t raw_key_size,
u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
struct qcom_ice *devm_of_qcom_ice_get(struct device *dev);
#endif /* __QCOM_ICE_H__ */
linux-7.2.3/include/soc/qcom/kryo-l2-accessors.h
+12
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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
#define __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
void kryo_l2_set_indirect_reg(u64 reg, u64 val);
u64 kryo_l2_get_indirect_reg(u64 reg);
#endif
linux-7.2.3/include/soc/qcom/ocmem.h
+65
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* The On Chip Memory (OCMEM) allocator allows various clients to allocate
* memory from OCMEM based on performance, latency and power requirements.
* This is typically used by the GPU, camera/video, and audio components on
* some Snapdragon SoCs.
*
* Copyright (C) 2019 Brian Masney <masneyb@onstation.org>
* Copyright (C) 2015 Red Hat. Author: Rob Clark <robdclark@gmail.com>
*/
#include <linux/device.h>
#include <linux/err.h>
#ifndef __OCMEM_H__
#define __OCMEM_H__
enum ocmem_client {
/* GMEM clients */
OCMEM_GRAPHICS = 0x0,
/*
* TODO add more once ocmem_allocate() is clever enough to
* deal with multiple clients.
*/
OCMEM_CLIENT_MAX,
};
struct ocmem;
struct ocmem_buf {
unsigned long offset;
unsigned long addr;
unsigned long len;
};
#if IS_ENABLED(CONFIG_QCOM_OCMEM)
struct ocmem *of_get_ocmem(struct device *dev);
struct ocmem_buf *ocmem_allocate(struct ocmem *ocmem, enum ocmem_client client,
unsigned long size);
void ocmem_free(struct ocmem *ocmem, enum ocmem_client client,
struct ocmem_buf *buf);
#else /* IS_ENABLED(CONFIG_QCOM_OCMEM) */
static inline struct ocmem *of_get_ocmem(struct device *dev)
{
return ERR_PTR(-ENODEV);
}
static inline struct ocmem_buf *ocmem_allocate(struct ocmem *ocmem,
enum ocmem_client client,
unsigned long size)
{
return ERR_PTR(-ENODEV);
}
static inline void ocmem_free(struct ocmem *ocmem, enum ocmem_client client,
struct ocmem_buf *buf)
{
}
#endif /* IS_ENABLED(CONFIG_QCOM_OCMEM) */
#endif /* __OCMEM_H__ */
linux-7.2.3/include/soc/qcom/qcom-spmi-pmic.h
+88
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2022 Linaro. All rights reserved.
* Author: Casey Connolly <casey.connolly@linaro.org>
*/
#ifndef __QCOM_SPMI_PMIC_H__
#define __QCOM_SPMI_PMIC_H__
#include <linux/device.h>
#define COMMON_SUBTYPE 0x00
#define PM8941_SUBTYPE 0x01
#define PM8841_SUBTYPE 0x02
#define PM8019_SUBTYPE 0x03
#define PM8226_SUBTYPE 0x04
#define PM8110_SUBTYPE 0x05
#define PMA8084_SUBTYPE 0x06
#define PMI8962_SUBTYPE 0x07
#define PMD9635_SUBTYPE 0x08
#define PM8994_SUBTYPE 0x09
#define PMI8994_SUBTYPE 0x0a
#define PM8916_SUBTYPE 0x0b
#define PM8004_SUBTYPE 0x0c
#define PM8909_SUBTYPE 0x0d
#define PM8028_SUBTYPE 0x0e
#define PM8901_SUBTYPE 0x0f
#define PM8950_SUBTYPE 0x10
#define PMI8950_SUBTYPE 0x11
#define PMK8001_SUBTYPE 0x12
#define PMI8996_SUBTYPE 0x13
#define PM8998_SUBTYPE 0x14
#define PMI8998_SUBTYPE 0x15
#define PM8005_SUBTYPE 0x18
#define PM8937_SUBTYPE 0x19
#define PM660L_SUBTYPE 0x1a
#define PM660_SUBTYPE 0x1b
#define PM8150_SUBTYPE 0x1e
#define PM8150L_SUBTYPE 0x1f
#define PM8150B_SUBTYPE 0x20
#define PMK8002_SUBTYPE 0x21
#define PM8009_SUBTYPE 0x24
#define PMI632_SUBTYPE 0x25
#define PM8150C_SUBTYPE 0x26
#define PM6150_SUBTYPE 0x28
#define SMB2351_SUBTYPE 0x29
#define PM8008_SUBTYPE 0x2c
#define PM6125_SUBTYPE 0x2d
#define PM7250B_SUBTYPE 0x2e
#define PMK8350_SUBTYPE 0x2f
#define PMR735B_SUBTYPE 0x34
#define PM6350_SUBTYPE 0x36
#define PM4125_SUBTYPE 0x37
#define PM8010_SUBTYPE 0x41
#define PM8550VS_SUBTYPE 0x45
#define PM8550VE_SUBTYPE 0x46
#define PMR735D_SUBTYPE 0x48
#define PM8550_SUBTYPE 0x49
#define PMK8550_SUBTYPE 0x4a
#define PMM8650AU_SUBTYPE 0x4e
#define PMM8650AU_PSAIL_SUBTYPE 0x4f
#define PM8750B_SUBTYPE 0x56
#define PMD8028_SUBTYPE 0x57
#define PMK8850_SUBTYPE 0x5c
#define PMH0101_SUBTYPE 0x5d
#define SMB2370_SUBTYPE 0x5f
#define PMH0104_SUBTYPE 0x60
#define PMH0110_SUBTYPE 0x61
#define PMCX0102_SUBTYPE 0x62
#define PMI8998_FAB_ID_SMIC 0x11
#define PMI8998_FAB_ID_GF 0x30
#define PM660_FAB_ID_GF 0x0
#define PM660_FAB_ID_TSMC 0x2
#define PM660_FAB_ID_MX 0x3
struct qcom_spmi_pmic {
unsigned int type;
unsigned int subtype;
unsigned int major;
unsigned int minor;
unsigned int rev2;
unsigned int fab_id;
const char *name;
};
const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev);
#endif /* __QCOM_SPMI_PMIC_H__ */
linux-7.2.3/include/soc/qcom/rpmh.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __SOC_QCOM_RPMH_H__
#define __SOC_QCOM_RPMH_H__
#include <soc/qcom/tcs.h>
#include <linux/platform_device.h>
#if IS_ENABLED(CONFIG_QCOM_RPMH)
int rpmh_write(const struct device *dev, enum rpmh_state state,
const struct tcs_cmd *cmd, u32 n);
int rpmh_write_async(const struct device *dev, enum rpmh_state state,
const struct tcs_cmd *cmd, u32 n);
int rpmh_write_batch(const struct device *dev, enum rpmh_state state,
const struct tcs_cmd *cmd, u32 *n);
void rpmh_invalidate(const struct device *dev);
#else
static inline int rpmh_write(const struct device *dev, enum rpmh_state state,
const struct tcs_cmd *cmd, u32 n)
{ return -ENODEV; }
static inline int rpmh_write_async(const struct device *dev,
enum rpmh_state state,
const struct tcs_cmd *cmd, u32 n)
{ return -ENODEV; }
static inline int rpmh_write_batch(const struct device *dev,
enum rpmh_state state,
const struct tcs_cmd *cmd, u32 *n)
{ return -ENODEV; }
static inline void rpmh_invalidate(const struct device *dev)
{
}
#endif /* CONFIG_QCOM_RPMH */
#endif /* __SOC_QCOM_RPMH_H__ */
linux-7.2.3/include/soc/qcom/spm.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
* Copyright (c) 2014,2015, Linaro Ltd.
*/
#ifndef __SPM_H__
#define __SPM_H__
enum pm_sleep_mode {
PM_SLEEP_MODE_STBY,
PM_SLEEP_MODE_RET,
PM_SLEEP_MODE_SPC,
PM_SLEEP_MODE_PC,
PM_SLEEP_MODE_NR,
};
struct spm_driver_data;
void spm_set_low_power_mode(struct spm_driver_data *drv,
enum pm_sleep_mode mode);
#endif /* __SPM_H__ */
linux-7.2.3/include/soc/qcom/tcs.h
+79
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __SOC_QCOM_TCS_H__
#define __SOC_QCOM_TCS_H__
#include <linux/bitfield.h>
#include <linux/bits.h>
#define MAX_RPMH_PAYLOAD 16
/**
* rpmh_state: state for the request
*
* RPMH_SLEEP_STATE: State of the resource when the processor subsystem
* is powered down. There is no client using the
* resource actively.
* RPMH_WAKE_ONLY_STATE: Resume resource state to the value previously
* requested before the processor was powered down.
* RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state
* is aggregated immediately.
*/
enum rpmh_state {
RPMH_SLEEP_STATE,
RPMH_WAKE_ONLY_STATE,
RPMH_ACTIVE_ONLY_STATE,
};
/**
* struct tcs_cmd: an individual request to RPMH.
*
* @addr: the address of the resource slv_id:18:16 | offset:0:15
* @data: the resource state request
* @wait: ensure that this command is complete before returning.
* Setting "wait" here only makes sense during rpmh_write_batch() for
* active-only transfers, this is because:
* rpmh_write() - Always waits.
* (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl)
* rpmh_write_async() - Never waits.
* (There's no request completion callback)
*/
struct tcs_cmd {
u32 addr;
u32 data;
u32 wait;
};
/**
* struct tcs_request: A set of tcs_cmds sent together in a TCS
*
* @state: state for the request.
* @wait_for_compl: wait until we get a response from the h/w accelerator
* (same as setting cmd->wait for all commands in the request)
* @num_cmds: the number of @cmds in this request
* @cmds: an array of tcs_cmds
*/
struct tcs_request {
enum rpmh_state state;
u32 wait_for_compl;
u32 num_cmds;
struct tcs_cmd *cmds;
};
#define BCM_TCS_CMD_COMMIT_MASK BIT(30)
#define BCM_TCS_CMD_VALID_MASK BIT(29)
#define BCM_TCS_CMD_VOTE_MASK GENMASK(13, 0)
#define BCM_TCS_CMD_VOTE_Y_MASK GENMASK(13, 0)
#define BCM_TCS_CMD_VOTE_X_MASK GENMASK(27, 14)
/* Construct a Bus Clock Manager (BCM) specific TCS command */
#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
(u32_encode_bits(commit, BCM_TCS_CMD_COMMIT_MASK) | \
u32_encode_bits(valid, BCM_TCS_CMD_VALID_MASK) | \
u32_encode_bits(vote_x, BCM_TCS_CMD_VOTE_X_MASK) | \
u32_encode_bits(vote_y, BCM_TCS_CMD_VOTE_Y_MASK))
#endif /* __SOC_QCOM_TCS_H__ */
linux-7.2.3/include/soc/rockchip/pm_domains.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2022, The Chromium OS Authors. All rights reserved.
*/
#ifndef __SOC_ROCKCHIP_PM_DOMAINS_H__
#define __SOC_ROCKCHIP_PM_DOMAINS_H__
#ifdef CONFIG_ROCKCHIP_PM_DOMAINS
int rockchip_pmu_block(void);
void rockchip_pmu_unblock(void);
#else /* CONFIG_ROCKCHIP_PM_DOMAINS */
static inline int rockchip_pmu_block(void)
{
return 0;
}
static inline void rockchip_pmu_unblock(void) { }
#endif /* CONFIG_ROCKCHIP_PM_DOMAINS */
#endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */
linux-7.2.3/include/soc/rockchip/rk3399_grf.h
+18
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Rockchip General Register Files definitions
*
* Copyright (c) 2018, Collabora Ltd.
* Author: Enric Balletbo i Serra <enric.balletbo@collabora.com>
*/
#ifndef __SOC_RK3399_GRF_H
#define __SOC_RK3399_GRF_H
/* PMU GRF Registers */
#define RK3399_PMUGRF_OS_REG2 0x308
#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
#define RK3399_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
#define RK3399_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
#endif
linux-7.2.3/include/soc/rockchip/rk3568_grf.h
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __SOC_RK3568_GRF_H
#define __SOC_RK3568_GRF_H
#define RK3568_PMUGRF_OS_REG2 0x208
#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
#define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
#define RK3568_PMUGRF_OS_REG3 0x20c
#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
#endif /* __SOC_RK3568_GRF_H */
linux-7.2.3/include/soc/rockchip/rk3588_grf.h
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __SOC_RK3588_GRF_H
#define __SOC_RK3588_GRF_H
#define RK3588_PMUGRF_OS_REG2 0x208
#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
#define RK3588_PMUGRF_OS_REG3 0x20c
#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
#define RK3588_PMUGRF_OS_REG4 0x210
#define RK3588_PMUGRF_OS_REG5 0x214
#define RK3588_PMUGRF_OS_REG6 0x218
#define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE GENMASK(2, 1)
/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
#define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0)
#define RK3588_SYSGRF_SOC_CON6 0x0318
#endif /* __SOC_RK3588_GRF_H */
linux-7.2.3/include/soc/rockchip/rockchip_grf.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Rockchip General Register Files definitions
*/
#ifndef __SOC_ROCKCHIP_GRF_H
#define __SOC_ROCKCHIP_GRF_H
/* Rockchip DDRTYPE defines */
enum {
ROCKCHIP_DDRTYPE_DDR3 = 3,
ROCKCHIP_DDRTYPE_LPDDR2 = 5,
ROCKCHIP_DDRTYPE_LPDDR3 = 6,
ROCKCHIP_DDRTYPE_LPDDR4 = 7,
ROCKCHIP_DDRTYPE_LPDDR4X = 8,
ROCKCHIP_DDRTYPE_LPDDR5 = 9,
};
#endif /* __SOC_ROCKCHIP_GRF_H */
linux-7.2.3/include/soc/rockchip/rockchip_sip.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
* Author: Lin Huang <hl@rock-chips.com>
*/
#ifndef __SOC_ROCKCHIP_SIP_H
#define __SOC_ROCKCHIP_SIP_H
#define ROCKCHIP_SIP_SUSPEND_MODE 0x82000003
#define ROCKCHIP_SLEEP_PD_CONFIG 0xff
#define ROCKCHIP_SIP_DRAM_FREQ 0x82000008
#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
#define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
#endif
linux-7.2.3/include/soc/sa1100/pwer.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_SA1100_PWER_H
#define SOC_SA1100_PWER_H
/*
* Copyright (C) 2015, Dmitry Eremin-Solenikov
*/
int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on);
int sa11x0_sc_set_wake(unsigned int irq, unsigned int on);
#endif
linux-7.2.3/include/soc/sifive/sifive_ccache.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* SiFive Composable Cache Controller header file
*
*/
#ifndef __SOC_SIFIVE_CCACHE_H
#define __SOC_SIFIVE_CCACHE_H
extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
#define SIFIVE_CCACHE_ERR_TYPE_CE 0
#define SIFIVE_CCACHE_ERR_TYPE_UE 1
#endif /* __SOC_SIFIVE_CCACHE_H */
linux-7.2.3/include/soc/spacemit/ccu.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_SPACEMIT_CCU_H__
#define __SOC_SPACEMIT_CCU_H__
#include <linux/auxiliary_bus.h>
#include <linux/regmap.h>
/* Auxiliary device used to represent a CCU reset controller */
struct spacemit_ccu_adev {
struct auxiliary_device adev;
struct regmap *regmap;
};
static inline struct spacemit_ccu_adev *
to_spacemit_ccu_adev(struct auxiliary_device *adev)
{
return container_of(adev, struct spacemit_ccu_adev, adev);
}
#endif /* __SOC_SPACEMIT_CCU_H__ */
linux-7.2.3/include/soc/spacemit/k1-syscon.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/* SpacemiT clock and reset driver definitions for the K1 SoC */
#ifndef __SOC_K1_SYSCON_H__
#define __SOC_K1_SYSCON_H__
#include "ccu.h"
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
/* MPMU register offset */
#define MPMU_POSR 0x0010
#define MPMU_FCCR 0x0008
#define POSR_PLL1_LOCK BIT(27)
#define POSR_PLL2_LOCK BIT(28)
#define POSR_PLL3_LOCK BIT(29)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
/* APBC register offset */
#define APBC_UART1_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS1_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS2_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR_CLK_RST 0x5c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TWSI7_CLK_RST 0x68
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
/* APMU register offset */
#define APMU_JPG_CLK_RES_CTRL 0x020
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
/* RCPU register offsets */
#define RCPU_SSP0_CLK_RST 0x0028
#define RCPU_I2C0_CLK_RST 0x0030
#define RCPU_UART1_CLK_RST 0x003c
#define RCPU_CAN_CLK_RST 0x0048
#define RCPU_IR_CLK_RST 0x004c
#define RCPU_UART0_CLK_RST 0x00d8
#define AUDIO_HDMI_CLK_CTRL 0x2044
/* RCPU2 register offsets */
#define RCPU2_PWM0_CLK_RST 0x0000
#define RCPU2_PWM1_CLK_RST 0x0004
#define RCPU2_PWM2_CLK_RST 0x0008
#define RCPU2_PWM3_CLK_RST 0x000c
#define RCPU2_PWM4_CLK_RST 0x0010
#define RCPU2_PWM5_CLK_RST 0x0014
#define RCPU2_PWM6_CLK_RST 0x0018
#define RCPU2_PWM7_CLK_RST 0x001c
#define RCPU2_PWM8_CLK_RST 0x0020
#define RCPU2_PWM9_CLK_RST 0x0024
/* APBC2 register offsets */
#define APBC2_UART1_CLK_RST 0x0000
#define APBC2_SSP2_CLK_RST 0x0004
#define APBC2_TWSI3_CLK_RST 0x0008
#define APBC2_RTC_CLK_RST 0x000c
#define APBC2_TIMERS0_CLK_RST 0x0010
#define APBC2_KPC_CLK_RST 0x0014
#define APBC2_GPIO_CLK_RST 0x001c
#endif /* __SOC_K1_SYSCON_H__ */
linux-7.2.3/include/soc/spacemit/k3-syscon.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/* SpacemiT clock and reset driver definitions for the K3 SoC */
#ifndef __SOC_K3_SYSCON_H__
#define __SOC_K3_SYSCON_H__
#include "ccu.h"
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
#define APBS_PLL4_SWCR1 0x130
#define APBS_PLL4_SWCR2 0x134
#define APBS_PLL4_SWCR3 0x138
#define APBS_PLL5_SWCR1 0x13c
#define APBS_PLL5_SWCR2 0x140
#define APBS_PLL5_SWCR3 0x144
#define APBS_PLL6_SWCR1 0x148
#define APBS_PLL6_SWCR2 0x14c
#define APBS_PLL6_SWCR3 0x150
#define APBS_PLL7_SWCR1 0x158
#define APBS_PLL7_SWCR2 0x15c
#define APBS_PLL7_SWCR3 0x160
#define APBS_PLL8_SWCR1 0x180
#define APBS_PLL8_SWCR2 0x184
#define APBS_PLL8_SWCR3 0x188
/* MPMU register offset */
#define MPMU_FCCR 0x0008
#define MPMU_POSR 0x0010
#define POSR_PLL1_LOCK BIT(24)
#define POSR_PLL2_LOCK BIT(25)
#define POSR_PLL3_LOCK BIT(26)
#define POSR_PLL4_LOCK BIT(27)
#define POSR_PLL5_LOCK BIT(28)
#define POSR_PLL6_LOCK BIT(29)
#define POSR_PLL7_LOCK BIT(30)
#define POSR_PLL8_LOCK BIT(31)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
#define MPMU_I2S0_SYSCLK 0x1100
#define MPMU_I2S2_SYSCLK 0x1104
#define MPMU_I2S3_SYSCLK 0x1108
#define MPMU_I2S4_SYSCLK 0x110c
#define MPMU_I2S5_SYSCLK 0x1110
#define MPMU_I2S_SYSCLK_CTRL 0x1114
/* APBC register offset */
#define APBC_UART0_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS0_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS1_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR0_CLK_RST 0x5c
#define APBC_IR1_CLK_RST 0x1c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_SSPA2_CLK_RST 0x88
#define APBC_SSPA3_CLK_RST 0x8c
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_CAN1_CLK_RST 0xa4
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
#define APBC_TIMERS2_CLK_RST 0x11c
#define APBC_TIMERS3_CLK_RST 0x120
#define APBC_TIMERS4_CLK_RST 0x124
#define APBC_TIMERS5_CLK_RST 0x128
#define APBC_TIMERS6_CLK_RST 0x12c
#define APBC_TIMERS7_CLK_RST 0x130
#define APBC_CAN2_CLK_RST 0x148
#define APBC_CAN3_CLK_RST 0x14c
#define APBC_CAN4_CLK_RST 0x150
#define APBC_UART10_CLK_RST 0x154
#define APBC_SSP0_CLK_RST 0x158
#define APBC_SSP1_CLK_RST 0x15c
#define APBC_SSPA4_CLK_RST 0x160
#define APBC_SSPA5_CLK_RST 0x164
/* APMU register offset */
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_PMU_CLK_GATE_CTRL 0x040
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_MCB_CLK_RES_CTRL 0x06c
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_DTC_CLK_RES_CTRL 0x0ac
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_UCIE_CTRL 0x11c
#define APMU_RCPU_CLK_RES_CTRL 0x14c
#define APMU_TOP_DCLK_CTRL 0x158
#define APMU_LCD_EDP_CTRL 0x23c
#define APMU_UFS_CLK_RES_CTRL 0x268
#define APMU_LCD_CLK_RES_CTRL3 0x26c
#define APMU_LCD_CLK_RES_CTRL4 0x270
#define APMU_LCD_CLK_RES_CTRL5 0x274
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_CPU_C2_CLK_CTRL 0x394
#define APMU_CPU_C3_CLK_CTRL 0x208
#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0
#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0
#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8
#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0
#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
#define APMU_EMAC2_CLK_RES_CTRL 0x248
#define APMU_ESPI_CLK_RES_CTRL 0x240
#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8
/* DCIU register offsets */
#define DCIU_DMASYS_CLK_EN 0x234
#define DCIU_DMASYS_SDMA_CLK_EN 0x238
#define DCIU_C2_TCM_PIPE_CLK 0x244
#define DCIU_C3_TCM_PIPE_CLK 0x248
#define DCIU_DMASYS_S0_RSTN 0x204
#define DCIU_DMASYS_S1_RSTN 0x208
#define DCIU_DMASYS_A0_RSTN 0x20C
#define DCIU_DMASYS_A1_RSTN 0x210
#define DCIU_DMASYS_A2_RSTN 0x214
#define DCIU_DMASYS_A3_RSTN 0x218
#define DCIU_DMASYS_A4_RSTN 0x21C
#define DCIU_DMASYS_A5_RSTN 0x220
#define DCIU_DMASYS_A6_RSTN 0x224
#define DCIU_DMASYS_A7_RSTN 0x228
#define DCIU_DMASYS_RSTN 0x22C
#define DCIU_DMASYS_SDMA_RSTN 0x230
/* RCPU SYSCTRL register offsets */
#define RCPU_CAN_CLK_RST 0x4c
#define RCPU_CAN1_CLK_RST 0xF0
#define RCPU_CAN2_CLK_RST 0xF4
#define RCPU_CAN3_CLK_RST 0xF8
#define RCPU_CAN4_CLK_RST 0xFC
#define RCPU_IRC_CLK_RST 0x48
#define RCPU_IRC1_CLK_RST 0xEC
#define RCPU_GMAC_CLK_RST 0xE4
#define RCPU_ESPI_CLK_RST 0xDC
#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70
#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44
/* RCPU UARTCTRL register offsets */
#define RCPU1_UART0_CLK_RST 0x00
#define RCPU1_UART1_CLK_RST 0x04
#define RCPU1_UART2_CLK_RST 0x08
#define RCPU1_UART3_CLK_RST 0x0c
#define RCPU1_UART4_CLK_RST 0x10
#define RCPU1_UART5_CLK_RST 0x14
/* RCPU I2SCTRL register offsets */
#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60
#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64
#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68
#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C
#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44
#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54
/* RCPU SPICTRL register offsets */
#define RCPU3_SSP0_CLK_RST 0x00
#define RCPU3_SSP1_CLK_RST 0x04
#define RCPU3_PWR_SSP_CLK_RST 0x08
/* RCPU I2CCTRL register offsets */
#define RCPU4_I2C0_CLK_RST 0x00
#define RCPU4_I2C1_CLK_RST 0x04
#define RCPU4_PWR_I2C_CLK_RST 0x08
/* RPMU register offsets */
#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C
#define RCPU5_TIMER1_CLK_RST 0x4C
#define RCPU5_TIMER2_CLK_RST 0x70
#define RCPU5_TIMER3_CLK_RST 0x78
#define RCPU5_TIMER4_CLK_RST 0x7C
#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74
#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0
#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4
#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8
#define RCPU5_RT24_CORE0_SW_RESET 0xCC
#define RCPU5_RT24_CORE1_SW_RESET 0xD0
/* RCPU PWMCTRL register offsets */
#define RCPU6_PWM0_CLK_RST 0x00
#define RCPU6_PWM1_CLK_RST 0x04
#define RCPU6_PWM2_CLK_RST 0x08
#define RCPU6_PWM3_CLK_RST 0x0c
#define RCPU6_PWM4_CLK_RST 0x10
#define RCPU6_PWM5_CLK_RST 0x14
#define RCPU6_PWM6_CLK_RST 0x18
#define RCPU6_PWM7_CLK_RST 0x1c
#define RCPU6_PWM8_CLK_RST 0x20
#define RCPU6_PWM9_CLK_RST 0x24
/* APBC2 SEC register offsets */
#define APBC2_UART1_CLK_RST 0x00
#define APBC2_SSP2_CLK_RST 0x04
#define APBC2_TWSI3_CLK_RST 0x08
#define APBC2_RTC_CLK_RST 0x0c
#define APBC2_TIMERS_CLK_RST 0x10
#define APBC2_GPIO_CLK_RST 0x1c
#endif /* __SOC_K3_SYSCON_H__ */
linux-7.2.3/include/soc/starfive/reset-starfive-jh71x0.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SOC_STARFIVE_RESET_JH71X0_H
#define __SOC_STARFIVE_RESET_JH71X0_H
#include <linux/auxiliary_bus.h>
#include <linux/compiler_types.h>
#include <linux/container_of.h>
struct jh71x0_reset_adev {
void __iomem *base;
struct auxiliary_device adev;
};
#define to_jh71x0_reset_adev(_adev) \
container_of((_adev), struct jh71x0_reset_adev, adev)
#endif
linux-7.2.3/include/soc/tegra/ahb.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __SOC_TEGRA_AHB_H__
#define __SOC_TEGRA_AHB_H__
extern int tegra_ahb_enable_smmu(struct device_node *ahb);
#endif /* __SOC_TEGRA_AHB_H__ */
linux-7.2.3/include/soc/tegra/bpmp-abi.h
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linux-7.2.3/include/soc/tegra/bpmp.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __SOC_TEGRA_BPMP_H
#define __SOC_TEGRA_BPMP_H
#include <linux/iosys-map.h>
#include <linux/mailbox_client.h>
#include <linux/pm_domain.h>
#include <linux/reset-controller.h>
#include <linux/semaphore.h>
#include <linux/types.h>
#include <soc/tegra/bpmp-abi.h>
struct tegra_bpmp_clk;
struct tegra_bpmp_ops;
struct tegra_bpmp_soc {
struct {
struct {
unsigned int offset;
unsigned int count;
unsigned int timeout;
} cpu_tx, thread, cpu_rx;
} channels;
const struct tegra_bpmp_ops *ops;
unsigned int num_resets;
};
struct tegra_bpmp_mb_data {
u32 code;
u32 flags;
u8 data[MSG_DATA_MIN_SZ];
} __packed;
#define tegra_bpmp_mb_read(dst, mb, size) \
iosys_map_memcpy_from(dst, mb, offsetof(struct tegra_bpmp_mb_data, data), size)
#define tegra_bpmp_mb_write(mb, src, size) \
iosys_map_memcpy_to(mb, offsetof(struct tegra_bpmp_mb_data, data), src, size)
#define tegra_bpmp_mb_read_field(mb, field) \
iosys_map_rd_field(mb, 0, struct tegra_bpmp_mb_data, field)
#define tegra_bpmp_mb_write_field(mb, field, value) \
iosys_map_wr_field(mb, 0, struct tegra_bpmp_mb_data, field, value)
struct tegra_bpmp_channel {
struct tegra_bpmp *bpmp;
struct iosys_map ib;
struct iosys_map ob;
struct completion completion;
struct tegra_ivc *ivc;
unsigned int index;
};
typedef void (*tegra_bpmp_mrq_handler_t)(unsigned int mrq,
struct tegra_bpmp_channel *channel,
void *data);
struct tegra_bpmp_mrq {
struct list_head list;
unsigned int mrq;
tegra_bpmp_mrq_handler_t handler;
void *data;
};
struct tegra_bpmp {
const struct tegra_bpmp_soc *soc;
struct device *dev;
void *priv;
struct {
struct mbox_client client;
struct mbox_chan *channel;
} mbox;
spinlock_t atomic_tx_lock;
struct tegra_bpmp_channel *tx_channel, *rx_channel, *threaded_channels;
struct {
unsigned long *allocated;
unsigned long *busy;
unsigned int count;
struct semaphore lock;
} threaded;
struct list_head mrqs;
spinlock_t lock;
struct tegra_bpmp_clk **clocks;
unsigned int num_clocks;
struct reset_controller_dev rstc;
struct genpd_onecell_data genpd;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_mirror;
#endif
bool suspended;
};
#define TEGRA_BPMP_MESSAGE_RESET BIT(0)
struct tegra_bpmp_message {
unsigned int mrq;
struct {
const void *data;
size_t size;
} tx;
struct {
void *data;
size_t size;
int ret;
} rx;
unsigned long flags;
};
#if IS_ENABLED(CONFIG_TEGRA_BPMP)
struct tegra_bpmp *tegra_bpmp_get(struct device *dev);
struct tegra_bpmp *tegra_bpmp_get_with_id(struct device *dev, unsigned int *id);
void tegra_bpmp_put(struct tegra_bpmp *bpmp);
int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg);
int tegra_bpmp_transfer(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg);
void tegra_bpmp_mrq_return(struct tegra_bpmp_channel *channel, int code,
const void *data, size_t size);
int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp, unsigned int mrq,
tegra_bpmp_mrq_handler_t handler, void *data);
void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq,
void *data);
bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, unsigned int mrq);
#else
static inline struct tegra_bpmp *tegra_bpmp_get(struct device *dev)
{
return ERR_PTR(-ENODEV);
}
static inline struct tegra_bpmp *tegra_bpmp_get_with_id(struct device *dev,
unsigned int *id)
{
return ERR_PTR(-ENODEV);
}
static inline void tegra_bpmp_put(struct tegra_bpmp *bpmp)
{
}
static inline int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
{
return -ENODEV;
}
static inline int tegra_bpmp_transfer(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
{
return -ENODEV;
}
static inline void tegra_bpmp_mrq_return(struct tegra_bpmp_channel *channel,
int code, const void *data,
size_t size)
{
}
static inline int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp,
unsigned int mrq,
tegra_bpmp_mrq_handler_t handler,
void *data)
{
return -ENODEV;
}
static inline void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp,
unsigned int mrq, void *data)
{
}
static inline bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp,
unsigned int mrq)
{
return false;
}
#endif
void tegra_bpmp_handle_rx(struct tegra_bpmp *bpmp);
#if IS_ENABLED(CONFIG_CLK_TEGRA_BPMP)
int tegra_bpmp_init_clocks(struct tegra_bpmp *bpmp);
#else
static inline int tegra_bpmp_init_clocks(struct tegra_bpmp *bpmp)
{
return 0;
}
#endif
#if IS_ENABLED(CONFIG_RESET_TEGRA_BPMP)
int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp);
#else
static inline int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp)
{
return 0;
}
#endif
#if IS_ENABLED(CONFIG_SOC_TEGRA_POWERGATE_BPMP)
int tegra_bpmp_init_powergates(struct tegra_bpmp *bpmp);
#else
static inline int tegra_bpmp_init_powergates(struct tegra_bpmp *bpmp)
{
return 0;
}
#endif
#if IS_ENABLED(CONFIG_DEBUG_FS)
int tegra_bpmp_init_debugfs(struct tegra_bpmp *bpmp);
#else
static inline int tegra_bpmp_init_debugfs(struct tegra_bpmp *bpmp)
{
return 0;
}
#endif
#endif /* __SOC_TEGRA_BPMP_H */
linux-7.2.3/include/soc/tegra/common.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 NVIDIA Corporation
*/
#ifndef __SOC_TEGRA_COMMON_H__
#define __SOC_TEGRA_COMMON_H__
#include <linux/errno.h>
#include <linux/types.h>
struct device;
/**
* Tegra SoC core device OPP table configuration
*
* @init_state: pre-initialize OPP state of a device
*/
struct tegra_core_opp_params {
bool init_state;
};
#ifdef CONFIG_ARCH_TEGRA
bool soc_is_tegra(void);
int devm_tegra_core_dev_init_opp_table(struct device *dev,
struct tegra_core_opp_params *params);
#else
static inline bool soc_is_tegra(void)
{
return false;
}
static inline int
devm_tegra_core_dev_init_opp_table(struct device *dev,
struct tegra_core_opp_params *params)
{
return -ENODEV;
}
#endif
static inline int
devm_tegra_core_dev_init_opp_table_common(struct device *dev)
{
struct tegra_core_opp_params opp_params = {};
int err;
opp_params.init_state = true;
err = devm_tegra_core_dev_init_opp_table(dev, &opp_params);
if (err != -ENODEV)
return err;
return 0;
}
#endif /* __SOC_TEGRA_COMMON_H__ */
linux-7.2.3/include/soc/tegra/cpuidle.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __SOC_TEGRA_CPUIDLE_H__
#define __SOC_TEGRA_CPUIDLE_H__
#ifdef CONFIG_ARM_TEGRA_CPUIDLE
void tegra_cpuidle_pcie_irqs_in_use(void);
#else
static inline void tegra_cpuidle_pcie_irqs_in_use(void)
{
}
#endif
#endif /* __SOC_TEGRA_CPUIDLE_H__ */
linux-7.2.3/include/soc/tegra/flowctrl.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Functions and macros to control the flowcontroller
*
* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
*/
#ifndef __SOC_TEGRA_FLOWCTRL_H__
#define __SOC_TEGRA_FLOWCTRL_H__
#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
#define FLOW_CTRL_WAITEVENT (2 << 29)
#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
#define FLOW_CTRL_JTAG_RESUME (1 << 28)
#define FLOW_CTRL_SCLK_RESUME (1 << 27)
#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
#define FLOW_CTRL_CPU0_CSR 0x8
#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
#define FLOW_CTRL_CSR_ENABLE (1 << 0)
#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
#define FLOW_CTRL_CPU1_CSR 0x18
#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
#ifndef __ASSEMBLY__
#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
u32 flowctrl_read_cpu_csr(unsigned int cpuid);
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
void flowctrl_cpu_suspend_enter(unsigned int cpuid);
void flowctrl_cpu_suspend_exit(unsigned int cpuid);
#else
static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
{
return 0;
}
static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
}
static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
{
}
static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
{
}
#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
#endif /* __ASSEMBLY */
#endif /* __SOC_TEGRA_FLOWCTRL_H__ */
linux-7.2.3/include/soc/tegra/fuse.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __SOC_TEGRA_FUSE_H__
#define __SOC_TEGRA_FUSE_H__
#include <linux/types.h>
#define TEGRA20 0x20
#define TEGRA30 0x30
#define TEGRA114 0x35
#define TEGRA124 0x40
#define TEGRA132 0x13
#define TEGRA210 0x21
#define TEGRA186 0x18
#define TEGRA194 0x19
#define TEGRA234 0x23
#define TEGRA241 0x24
#define TEGRA264 0x26
#define TEGRA_FUSE_SKU_CALIB_0 0xf0
#define TEGRA30_FUSE_SATA_CALIB 0x124
#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
#ifndef __ASSEMBLY__
enum tegra_revision {
TEGRA_REVISION_UNKNOWN = 0,
TEGRA_REVISION_A01,
TEGRA_REVISION_A02,
TEGRA_REVISION_A03,
TEGRA_REVISION_A03p,
TEGRA_REVISION_A04,
TEGRA_REVISION_MAX,
};
enum tegra_platform {
TEGRA_PLATFORM_SILICON = 0,
TEGRA_PLATFORM_QT,
TEGRA_PLATFORM_SYSTEM_FPGA,
TEGRA_PLATFORM_UNIT_FPGA,
TEGRA_PLATFORM_ASIM_QT,
TEGRA_PLATFORM_ASIM_LINSIM,
TEGRA_PLATFORM_DSIM_ASIM_LINSIM,
TEGRA_PLATFORM_VERIFICATION_SIMULATION,
TEGRA_PLATFORM_VDK,
TEGRA_PLATFORM_VSP,
TEGRA_PLATFORM_MAX,
};
struct tegra_sku_info {
int sku_id;
int cpu_process_id;
int cpu_speedo_id;
int cpu_speedo_value;
int cpu_iddq_value;
int soc_process_id;
int soc_speedo_id;
int soc_speedo_value;
int gpu_process_id;
int gpu_speedo_id;
int gpu_speedo_value;
enum tegra_revision revision;
enum tegra_platform platform;
};
#ifdef CONFIG_ARCH_TEGRA
extern struct tegra_sku_info tegra_sku_info;
u32 tegra_read_straps(void);
u32 tegra_read_ram_code(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);
u32 tegra_read_chipid(void);
u8 tegra_get_chip_id(void);
u8 tegra_get_platform(void);
bool tegra_is_silicon(void);
int tegra194_miscreg_mask_serror(void);
#else
static struct tegra_sku_info tegra_sku_info __maybe_unused;
static inline u32 tegra_read_straps(void)
{
return 0;
}
static inline u32 tegra_read_ram_code(void)
{
return 0;
}
static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
{
return -ENODEV;
}
static inline u32 tegra_read_chipid(void)
{
return 0;
}
static inline u8 tegra_get_chip_id(void)
{
return 0;
}
static inline u8 tegra_get_platform(void)
{
return 0;
}
static inline bool tegra_is_silicon(void)
{
return false;
}
static inline int tegra194_miscreg_mask_serror(void)
{
return false;
}
#endif
struct device *tegra_soc_device_register(void);
#endif /* __ASSEMBLY__ */
#endif /* __SOC_TEGRA_FUSE_H__ */
linux-7.2.3/include/soc/tegra/irq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
*/
#ifndef __SOC_TEGRA_IRQ_H
#define __SOC_TEGRA_IRQ_H
#include <linux/types.h>
#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_TEGRA)
bool tegra_pending_sgi(void);
#else
static inline bool tegra_pending_sgi(void)
{
return false;
}
#endif
#endif /* __SOC_TEGRA_IRQ_H */
linux-7.2.3/include/soc/tegra/ivc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __TEGRA_IVC_H
#define __TEGRA_IVC_H
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/iosys-map.h>
#include <linux/types.h>
struct tegra_ivc_header;
struct tegra_ivc {
struct device *peer;
struct {
struct iosys_map map;
unsigned int position;
dma_addr_t phys;
} rx, tx;
void (*notify)(struct tegra_ivc *ivc, void *data);
void *notify_data;
unsigned int num_frames;
size_t frame_size;
};
/**
* tegra_ivc_read_get_next_frame - Peek at the next frame to receive
* @ivc pointer of the IVC channel
*
* Peek at the next frame to be received, without removing it from
* the queue.
*
* Returns a pointer to the frame, or an error encoded pointer.
*/
int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map);
/**
* tegra_ivc_read_advance - Advance the read queue
* @ivc pointer of the IVC channel
*
* Advance the read queue
*
* Returns 0, or a negative error value if failed.
*/
int tegra_ivc_read_advance(struct tegra_ivc *ivc);
/**
* tegra_ivc_write_get_next_frame - Poke at the next frame to transmit
* @ivc pointer of the IVC channel
*
* Get access to the next frame.
*
* Returns a pointer to the frame, or an error encoded pointer.
*/
int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map);
/**
* tegra_ivc_write_advance - Advance the write queue
* @ivc pointer of the IVC channel
*
* Advance the write queue
*
* Returns 0, or a negative error value if failed.
*/
int tegra_ivc_write_advance(struct tegra_ivc *ivc);
/**
* tegra_ivc_notified - handle internal messages
* @ivc pointer of the IVC channel
*
* This function must be called following every notification.
*
* Returns 0 if the channel is ready for communication, or -EAGAIN if a channel
* reset is in progress.
*/
int tegra_ivc_notified(struct tegra_ivc *ivc);
/**
* tegra_ivc_reset - initiates a reset of the shared memory state
* @ivc pointer of the IVC channel
*
* This function must be called after a channel is reserved before it is used
* for communication. The channel will be ready for use when a subsequent call
* to notify the remote of the channel reset.
*/
void tegra_ivc_reset(struct tegra_ivc *ivc);
size_t tegra_ivc_align(size_t size);
unsigned tegra_ivc_total_queue_size(unsigned queue_size);
int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, const struct iosys_map *rx,
dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys,
unsigned int num_frames, size_t frame_size,
void (*notify)(struct tegra_ivc *ivc, void *data),
void *data);
void tegra_ivc_cleanup(struct tegra_ivc *ivc);
#endif /* __TEGRA_IVC_H */
linux-7.2.3/include/soc/tegra/mc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014-2026 NVIDIA Corporation
*/
#ifndef __SOC_TEGRA_MC_H__
#define __SOC_TEGRA_MC_H__
#include <linux/bits.h>
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/reset-controller.h>
#include <linux/tegra-icc.h>
#include <linux/types.h>
struct clk;
struct device;
struct page;
struct tegra_mc_timing {
unsigned long rate;
u32 *emem_data;
};
struct tegra_mc_client {
unsigned int id;
unsigned int bpmp_id;
enum tegra_icc_client_type type;
const char *name;
/*
* For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the
* Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
* stream ID used for IOVA translations for the given memory client.
*/
union {
unsigned int swgroup;
unsigned int sid;
};
unsigned int fifo_size;
struct {
/* Tegra SMMU enable (Tegra210 and earlier) */
struct {
unsigned int reg;
unsigned int bit;
} smmu;
/* latency allowance */
struct {
unsigned int reg;
unsigned int shift;
unsigned int mask;
unsigned int def;
} la;
/* stream ID overrides (Tegra186 and later) */
struct {
unsigned int override;
unsigned int security;
} sid;
} regs;
};
struct tegra_smmu_swgroup {
const char *name;
unsigned int swgroup;
unsigned int reg;
};
struct tegra_smmu_group_soc {
const char *name;
const unsigned int *swgroups;
unsigned int num_swgroups;
};
struct tegra_smmu_soc {
const struct tegra_mc_client *clients;
unsigned int num_clients;
const struct tegra_smmu_swgroup *swgroups;
unsigned int num_swgroups;
const struct tegra_smmu_group_soc *groups;
unsigned int num_groups;
bool supports_round_robin_arbitration;
bool supports_request_limit;
unsigned int num_tlb_lines;
unsigned int num_asids;
};
struct tegra_mc;
struct tegra_smmu;
#ifdef CONFIG_TEGRA_IOMMU_SMMU
struct tegra_smmu *tegra_smmu_probe(struct device *dev,
const struct tegra_smmu_soc *soc,
struct tegra_mc *mc);
void tegra_smmu_remove(struct tegra_smmu *smmu);
#else
static inline struct tegra_smmu *
tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
struct tegra_mc *mc)
{
return NULL;
}
static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
{
}
#endif
struct tegra_mc_reset {
const char *name;
unsigned long id;
unsigned int control;
unsigned int status;
unsigned int reset;
unsigned int bit;
};
struct tegra_mc_reset_ops {
int (*hotreset_assert)(struct tegra_mc *mc,
const struct tegra_mc_reset *rst);
int (*hotreset_deassert)(struct tegra_mc *mc,
const struct tegra_mc_reset *rst);
int (*block_dma)(struct tegra_mc *mc,
const struct tegra_mc_reset *rst);
bool (*dma_idling)(struct tegra_mc *mc,
const struct tegra_mc_reset *rst);
int (*unblock_dma)(struct tegra_mc *mc,
const struct tegra_mc_reset *rst);
int (*reset_status)(struct tegra_mc *mc,
const struct tegra_mc_reset *rst);
};
#define TEGRA_MC_ICC_TAG_DEFAULT 0
#define TEGRA_MC_ICC_TAG_ISO BIT(0)
struct tegra_mc_icc_ops {
int (*set)(struct icc_node *src, struct icc_node *dst);
int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
struct icc_node_data *(*xlate_extended)(const struct of_phandle_args *spec,
void *data);
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
};
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec,
void *data);
extern const struct tegra_mc_icc_ops tegra_mc_icc_ops;
struct tegra_mc_ops {
/*
* @probe: Callback to set up SoC-specific bits of the memory controller. This is called
* after basic, common set up that is done by the SoC-agnostic bits.
*/
int (*probe)(struct tegra_mc *mc);
void (*remove)(struct tegra_mc *mc);
void (*resume)(struct tegra_mc *mc);
int (*probe_device)(struct tegra_mc *mc, struct device *dev);
};
struct tegra_mc_regs {
unsigned int cfg_channel_enable;
unsigned int err_status;
unsigned int err_add;
unsigned int err_add_hi;
unsigned int err_vpr_status;
unsigned int err_vpr_add;
unsigned int err_sec_status;
unsigned int err_sec_add;
unsigned int err_mts_status;
unsigned int err_mts_add;
unsigned int err_gen_co_status;
unsigned int err_gen_co_add;
unsigned int err_route_status;
unsigned int err_route_add;
};
struct tegra_mc_intmask {
u32 reg;
u32 mask;
};
struct tegra_mc_soc {
const struct tegra_mc_client *clients;
unsigned int num_clients;
const unsigned long *emem_regs;
unsigned int num_emem_regs;
unsigned int num_address_bits;
unsigned int atom_size;
unsigned int num_carveouts;
u16 client_id_mask;
u8 num_channels;
const struct tegra_smmu_soc *smmu;
u32 ch_intmask;
u32 global_intstatus_channel_shift;
bool has_addr_hi_reg;
const struct tegra_mc_reset_ops *reset_ops;
const struct tegra_mc_reset *resets;
unsigned int num_resets;
const struct tegra_mc_icc_ops *icc_ops;
const struct tegra_mc_ops *ops;
const struct tegra_mc_regs *regs;
const irq_handler_t *handle_irq;
unsigned int num_interrupts;
unsigned int mc_addr_hi_mask;
unsigned int mc_err_status_type_mask;
const struct tegra_mc_intmask *intmasks;
unsigned int num_intmasks;
};
struct tegra_mc {
struct tegra_bpmp *bpmp;
struct device *dev;
struct tegra_smmu *smmu;
void __iomem *regs;
void __iomem *bcast_ch_regs;
void __iomem **ch_regs;
struct clk *clk;
const struct tegra_mc_soc *soc;
unsigned long tick;
struct tegra_mc_timing *timings;
unsigned int num_timings;
unsigned int num_channels;
bool bwmgr_mrq_supported;
struct reset_controller_dev reset;
struct icc_provider provider;
spinlock_t lock;
struct {
struct dentry *root;
} debugfs;
};
int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
#ifdef CONFIG_TEGRA_MC
struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
phys_addr_t *base, u64 *size);
#else
static inline struct tegra_mc *
devm_tegra_memory_controller_get(struct device *dev)
{
return ERR_PTR(-ENODEV);
}
static inline int
tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
{
return -ENODEV;
}
static inline int
tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
phys_addr_t *base, u64 *size)
{
return -ENODEV;
}
#endif
extern const struct tegra_mc_regs tegra20_mc_regs;
#endif /* __SOC_TEGRA_MC_H__ */
linux-7.2.3/include/soc/tegra/pm.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 NVIDIA Corporation
*/
#ifndef __SOC_TEGRA_PM_H__
#define __SOC_TEGRA_PM_H__
#include <linux/errno.h>
enum tegra_suspend_mode {
TEGRA_SUSPEND_NONE = 0,
TEGRA_SUSPEND_LP2, /* CPU voltage off */
TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
TEGRA_MAX_SUSPEND_MODE,
TEGRA_SUSPEND_NOT_READY,
};
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) && defined(CONFIG_ARCH_TEGRA)
enum tegra_suspend_mode
tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
/* low-level resume entry point */
void tegra_resume(void);
int tegra30_pm_secondary_cpu_suspend(unsigned long arg);
void tegra_pm_clear_cpu_in_lp2(void);
void tegra_pm_set_cpu_in_lp2(void);
int tegra_pm_enter_lp2(void);
int tegra_pm_park_secondary_cpu(unsigned long cpu);
void tegra_pm_init_suspend(void);
#else
static inline enum tegra_suspend_mode
tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
{
return TEGRA_SUSPEND_NONE;
}
static inline void tegra_resume(void)
{
}
static inline int tegra30_pm_secondary_cpu_suspend(unsigned long arg)
{
return -ENOTSUPP;
}
static inline void tegra_pm_clear_cpu_in_lp2(void)
{
}
static inline void tegra_pm_set_cpu_in_lp2(void)
{
}
static inline int tegra_pm_enter_lp2(void)
{
return -ENOTSUPP;
}
static inline int tegra_pm_park_secondary_cpu(unsigned long cpu)
{
return -ENOTSUPP;
}
static inline void tegra_pm_init_suspend(void)
{
}
#endif /* CONFIG_PM_SLEEP */
#endif /* __SOC_TEGRA_PM_H__ */
linux-7.2.3/include/soc/tegra/pmc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2010 Google, Inc
* Copyright (c) 2014 NVIDIA Corporation
*
* Author:
* Colin Cross <ccross@google.com>
*/
#ifndef __SOC_TEGRA_PMC_H__
#define __SOC_TEGRA_PMC_H__
#include <linux/reboot.h>
#include <soc/tegra/pm.h>
struct clk;
struct reset_control;
struct tegra_pmc;
/*
* powergate and I/O rail APIs
*/
#define TEGRA_POWERGATE_CPU 0
#define TEGRA_POWERGATE_3D 1
#define TEGRA_POWERGATE_VENC 2
#define TEGRA_POWERGATE_PCIE 3
#define TEGRA_POWERGATE_VDEC 4
#define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6
#define TEGRA_POWERGATE_HEG 7
#define TEGRA_POWERGATE_SATA 8
#define TEGRA_POWERGATE_CPU1 9
#define TEGRA_POWERGATE_CPU2 10
#define TEGRA_POWERGATE_CPU3 11
#define TEGRA_POWERGATE_CELP 12
#define TEGRA_POWERGATE_3D1 13
#define TEGRA_POWERGATE_CPU0 14
#define TEGRA_POWERGATE_C0NC 15
#define TEGRA_POWERGATE_C1NC 16
#define TEGRA_POWERGATE_SOR 17
#define TEGRA_POWERGATE_DIS 18
#define TEGRA_POWERGATE_DISB 19
#define TEGRA_POWERGATE_XUSBA 20
#define TEGRA_POWERGATE_XUSBB 21
#define TEGRA_POWERGATE_XUSBC 22
#define TEGRA_POWERGATE_VIC 23
#define TEGRA_POWERGATE_IRAM 24
#define TEGRA_POWERGATE_NVDEC 25
#define TEGRA_POWERGATE_NVJPG 26
#define TEGRA_POWERGATE_AUD 27
#define TEGRA_POWERGATE_DFD 28
#define TEGRA_POWERGATE_VE2 29
#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
/**
* enum tegra_io_pad - I/O pad group identifier
*
* I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
* can be used to control the common voltage signal level and power state of
* the pins of the given pad.
*/
enum tegra_io_pad {
TEGRA_IO_PAD_AUDIO,
TEGRA_IO_PAD_AUDIO_HV,
TEGRA_IO_PAD_BB,
TEGRA_IO_PAD_CAM,
TEGRA_IO_PAD_COMP,
TEGRA_IO_PAD_CONN,
TEGRA_IO_PAD_CSIA,
TEGRA_IO_PAD_CSIB,
TEGRA_IO_PAD_CSIC,
TEGRA_IO_PAD_CSID,
TEGRA_IO_PAD_CSIE,
TEGRA_IO_PAD_CSIF,
TEGRA_IO_PAD_CSIG,
TEGRA_IO_PAD_CSIH,
TEGRA_IO_PAD_DAP3,
TEGRA_IO_PAD_DAP5,
TEGRA_IO_PAD_DBG,
TEGRA_IO_PAD_DEBUG_NONAO,
TEGRA_IO_PAD_DMIC,
TEGRA_IO_PAD_DMIC_HV,
TEGRA_IO_PAD_DP,
TEGRA_IO_PAD_DSI,
TEGRA_IO_PAD_DSIB,
TEGRA_IO_PAD_DSIC,
TEGRA_IO_PAD_DSID,
TEGRA_IO_PAD_EDP,
TEGRA_IO_PAD_EMMC,
TEGRA_IO_PAD_EMMC2,
TEGRA_IO_PAD_EQOS,
TEGRA_IO_PAD_GPIO,
TEGRA_IO_PAD_GP_PWM2,
TEGRA_IO_PAD_GP_PWM3,
TEGRA_IO_PAD_HDMI,
TEGRA_IO_PAD_HDMI_DP0,
TEGRA_IO_PAD_HDMI_DP1,
TEGRA_IO_PAD_HDMI_DP2,
TEGRA_IO_PAD_HDMI_DP3,
TEGRA_IO_PAD_HSIC,
TEGRA_IO_PAD_HV,
TEGRA_IO_PAD_LVDS,
TEGRA_IO_PAD_MIPI_BIAS,
TEGRA_IO_PAD_NAND,
TEGRA_IO_PAD_PEX_BIAS,
TEGRA_IO_PAD_PEX_CLK_BIAS,
TEGRA_IO_PAD_PEX_CLK1,
TEGRA_IO_PAD_PEX_CLK2,
TEGRA_IO_PAD_PEX_CLK3,
TEGRA_IO_PAD_PEX_CLK_2_BIAS,
TEGRA_IO_PAD_PEX_CLK_2,
TEGRA_IO_PAD_PEX_CNTRL,
TEGRA_IO_PAD_PEX_CTL2,
TEGRA_IO_PAD_PEX_L0_RST,
TEGRA_IO_PAD_PEX_L1_RST,
TEGRA_IO_PAD_PEX_L5_RST,
TEGRA_IO_PAD_PWR_CTL,
TEGRA_IO_PAD_SDMMC1,
TEGRA_IO_PAD_SDMMC1_HV,
TEGRA_IO_PAD_SDMMC2,
TEGRA_IO_PAD_SDMMC2_HV,
TEGRA_IO_PAD_SDMMC3,
TEGRA_IO_PAD_SDMMC3_HV,
TEGRA_IO_PAD_SDMMC4,
TEGRA_IO_PAD_SOC_GPIO10,
TEGRA_IO_PAD_SOC_GPIO12,
TEGRA_IO_PAD_SOC_GPIO13,
TEGRA_IO_PAD_SOC_GPIO53,
TEGRA_IO_PAD_SPI,
TEGRA_IO_PAD_SPI_HV,
TEGRA_IO_PAD_SYS_DDC,
TEGRA_IO_PAD_UART,
TEGRA_IO_PAD_UART4,
TEGRA_IO_PAD_UART5,
TEGRA_IO_PAD_UFS,
TEGRA_IO_PAD_USB0,
TEGRA_IO_PAD_USB1,
TEGRA_IO_PAD_USB2,
TEGRA_IO_PAD_USB3,
TEGRA_IO_PAD_USB_BIAS,
TEGRA_IO_PAD_AO_HV,
};
#ifdef CONFIG_SOC_TEGRA_PMC
struct tegra_pmc *devm_tegra_pmc_get(struct device *dev);
int tegra_pmc_powergate_power_on(struct tegra_pmc *pmc, unsigned int id);
int tegra_pmc_powergate_power_off(struct tegra_pmc *pmc, unsigned int id);
int tegra_pmc_powergate_remove_clamping(struct tegra_pmc *pmc, unsigned int id);
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_pmc_powergate_sequence_power_up(struct tegra_pmc *pmc,
unsigned int id, struct clk *clk,
struct reset_control *rst);
int tegra_pmc_io_pad_power_enable(struct tegra_pmc *pmc, enum tegra_io_pad id);
int tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id);
#else
static inline struct tegra_pmc *devm_tegra_pmc_get(struct device *dev)
{
return ERR_PTR(-ENOSYS);
}
static inline int
tegra_pmc_powergate_power_on(struct tegra_pmc *pmc, unsigned int id)
{
return -ENOSYS;
}
static inline int
tegra_pmc_powergate_power_off(struct tegra_pmc *pmc, unsigned int id)
{
return -ENOSYS;
}
static inline int
tegra_pmc_powergate_remove_clamping(struct tegra_pmc *pmc, unsigned int id)
{
return -ENOSYS;
}
/* Must be called with clk disabled, and returns with clk enabled */
static inline int
tegra_pmc_powergate_sequence_power_up(struct tegra_pmc *pmc, unsigned int id,
struct clk *clk,
struct reset_control *rst)
{
return -ENOSYS;
}
static inline int
tegra_pmc_io_pad_power_enable(struct tegra_pmc *pmc, enum tegra_io_pad id)
{
return -ENOSYS;
}
static inline int
tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id)
{
return -ENOSYS;
}
#endif /* CONFIG_SOC_TEGRA_PMC */
/* 32-bit ARM platforms only */
#if defined(CONFIG_ARM)
bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
int tegra_pmc_cpu_power_on(unsigned int cpuid);
int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
#if defined(CONFIG_SOC_TEGRA_PMC) && defined(CONFIG_PM_SLEEP)
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
#else
static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
{
return TEGRA_SUSPEND_NONE;
}
static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
{
}
static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
{
}
#endif
#endif
#if defined(CONFIG_ARM) && defined(CONFIG_SOC_TEGRA_PMC)
bool tegra_pmc_core_domain_state_synced(void);
#else
/* needed for COMPILE_TEST */
static inline bool tegra_pmc_core_domain_state_synced(void)
{
return false;
}
#endif
#endif /* __SOC_TEGRA_PMC_H__ */
linux-7.2.3/include/soc/tegra/tegra-cbb.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
*/
#ifndef TEGRA_CBB_H
#define TEGRA_CBB_H
#include <linux/list.h>
struct tegra_cbb_error {
const char *code;
const char *source;
const char *desc;
};
struct tegra_cbb {
struct device *dev;
const struct tegra_cbb_ops *ops;
struct list_head node;
};
struct tegra_cbb_ops {
int (*debugfs_show)(struct tegra_cbb *cbb, struct seq_file *s, void *v);
int (*interrupt_enable)(struct tegra_cbb *cbb);
void (*error_enable)(struct tegra_cbb *cbb);
void (*fault_enable)(struct tegra_cbb *cbb);
void (*stall_enable)(struct tegra_cbb *cbb);
void (*error_clear)(struct tegra_cbb *cbb);
u32 (*get_status)(struct tegra_cbb *cbb);
};
int tegra_cbb_get_irq(struct platform_device *pdev, unsigned int *nonsec_irq,
unsigned int *sec_irq);
__printf(2, 3)
void tegra_cbb_print_err(struct seq_file *file, const char *fmt, ...);
void tegra_cbb_print_cache(struct seq_file *file, u32 cache);
void tegra_cbb_print_prot(struct seq_file *file, u32 prot);
int tegra_cbb_register(struct tegra_cbb *cbb);
void tegra_cbb_fault_enable(struct tegra_cbb *cbb);
void tegra_cbb_stall_enable(struct tegra_cbb *cbb);
void tegra_cbb_error_clear(struct tegra_cbb *cbb);
u32 tegra_cbb_get_status(struct tegra_cbb *cbb);
#endif /* TEGRA_CBB_H */