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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/include/sound/sof/channel_map.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2019 Intel Corporation
*/
#ifndef __IPC_CHANNEL_MAP_H__
#define __IPC_CHANNEL_MAP_H__
#include <uapi/sound/sof/header.h>
#include <sound/sof/header.h>
/**
* \brief Channel map, specifies transformation of one-to-many or many-to-one.
*
* In case of one-to-many specifies how the output channels are computed out of
* a single source channel,
* in case of many-to-one specifies how a single target channel is computed
* from a multichannel input stream.
*
* Channel index specifies position of the channel in the stream on the 'one'
* side.
*
* Ext ID is the identifier of external part of the transformation. Depending
* on the context, it may be pipeline ID, dai ID, ...
*
* Channel mask describes which channels are taken into account on the "many"
* side. Bit[i] set to 1 means that i-th channel is used for computation
* (either as source or as a target).
*
* Channel mask is followed by array of coefficients in Q2.30 format,
* one per each channel set in the mask (left to right, LS bit set in the
* mask corresponds to ch_coeffs[0]).
*/
struct sof_ipc_channel_map {
uint32_t ch_index;
uint32_t ext_id;
uint32_t ch_mask;
uint32_t reserved;
int32_t ch_coeffs[];
} __packed;
/**
* \brief Complete map for each channel of a multichannel stream.
*
* num_ch_map Specifies number of items in the ch_map.
* More than one transformation per a single channel is allowed (in case
* multiple external entities are transformed).
* A channel may be skipped in the transformation list, then it is filled
* with 0's by the transformation function.
*/
struct sof_ipc_stream_map {
struct sof_ipc_cmd_hdr hdr;
uint32_t num_ch_map;
uint32_t reserved[3];
struct sof_ipc_channel_map ch_map[];
} __packed;
#endif /* __IPC_CHANNEL_MAP_H__ */
linux-7.2.3/include/sound/sof/control.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_CONTROL_H__
#define __INCLUDE_SOUND_SOF_CONTROL_H__
#include <uapi/sound/sof/header.h>
#include <sound/sof/header.h>
/*
* Component Mixers and Controls
*/
/* channel positions - uses same values as ALSA */
enum sof_ipc_chmap {
SOF_CHMAP_UNKNOWN = 0,
SOF_CHMAP_NA, /**< N/A, silent */
SOF_CHMAP_MONO, /**< mono stream */
SOF_CHMAP_FL, /**< front left */
SOF_CHMAP_FR, /**< front right */
SOF_CHMAP_RL, /**< rear left */
SOF_CHMAP_RR, /**< rear right */
SOF_CHMAP_FC, /**< front centre */
SOF_CHMAP_LFE, /**< LFE */
SOF_CHMAP_SL, /**< side left */
SOF_CHMAP_SR, /**< side right */
SOF_CHMAP_RC, /**< rear centre */
SOF_CHMAP_FLC, /**< front left centre */
SOF_CHMAP_FRC, /**< front right centre */
SOF_CHMAP_RLC, /**< rear left centre */
SOF_CHMAP_RRC, /**< rear right centre */
SOF_CHMAP_FLW, /**< front left wide */
SOF_CHMAP_FRW, /**< front right wide */
SOF_CHMAP_FLH, /**< front left high */
SOF_CHMAP_FCH, /**< front centre high */
SOF_CHMAP_FRH, /**< front right high */
SOF_CHMAP_TC, /**< top centre */
SOF_CHMAP_TFL, /**< top front left */
SOF_CHMAP_TFR, /**< top front right */
SOF_CHMAP_TFC, /**< top front centre */
SOF_CHMAP_TRL, /**< top rear left */
SOF_CHMAP_TRR, /**< top rear right */
SOF_CHMAP_TRC, /**< top rear centre */
SOF_CHMAP_TFLC, /**< top front left centre */
SOF_CHMAP_TFRC, /**< top front right centre */
SOF_CHMAP_TSL, /**< top side left */
SOF_CHMAP_TSR, /**< top side right */
SOF_CHMAP_LLFE, /**< left LFE */
SOF_CHMAP_RLFE, /**< right LFE */
SOF_CHMAP_BC, /**< bottom centre */
SOF_CHMAP_BLC, /**< bottom left centre */
SOF_CHMAP_BRC, /**< bottom right centre */
SOF_CHMAP_LAST = SOF_CHMAP_BRC,
};
/* control data type and direction */
enum sof_ipc_ctrl_type {
/* per channel data - uses struct sof_ipc_ctrl_value_chan */
SOF_CTRL_TYPE_VALUE_CHAN_GET = 0,
SOF_CTRL_TYPE_VALUE_CHAN_SET,
/* component data - uses struct sof_ipc_ctrl_value_comp */
SOF_CTRL_TYPE_VALUE_COMP_GET,
SOF_CTRL_TYPE_VALUE_COMP_SET,
/* bespoke data - uses struct sof_abi_hdr */
SOF_CTRL_TYPE_DATA_GET,
SOF_CTRL_TYPE_DATA_SET,
};
/* control command type */
enum sof_ipc_ctrl_cmd {
SOF_CTRL_CMD_VOLUME = 0, /**< maps to ALSA volume style controls */
SOF_CTRL_CMD_ENUM, /**< maps to ALSA enum style controls */
SOF_CTRL_CMD_SWITCH, /**< maps to ALSA switch style controls */
SOF_CTRL_CMD_BINARY, /**< maps to ALSA binary style controls */
};
/* generic channel mapped value data */
struct sof_ipc_ctrl_value_chan {
uint32_t channel; /**< channel map - enum sof_ipc_chmap */
uint32_t value;
} __packed;
/* generic component mapped value data */
struct sof_ipc_ctrl_value_comp {
uint32_t index; /**< component source/sink/control index in control */
union {
uint32_t uvalue;
int32_t svalue;
};
} __packed;
/* generic control data */
struct sof_ipc_ctrl_data {
struct sof_ipc_reply rhdr;
uint32_t comp_id;
/* control access and data type */
uint32_t type; /**< enum sof_ipc_ctrl_type */
uint32_t cmd; /**< enum sof_ipc_ctrl_cmd */
uint32_t index; /**< control index for comps > 1 control */
/* control data - can either be appended or DMAed from host */
struct sof_ipc_host_buffer buffer;
uint32_t num_elems; /**< in array elems or bytes for data type */
uint32_t elems_remaining; /**< elems remaining if sent in parts */
uint32_t msg_index; /**< for large messages sent in parts */
/* reserved for future use */
uint32_t reserved[6];
/* control data - add new types if needed */
union {
/* channel values can be used by volume type controls */
DECLARE_FLEX_ARRAY(struct sof_ipc_ctrl_value_chan, chanv);
/* component values used by routing controls like mux, mixer */
DECLARE_FLEX_ARRAY(struct sof_ipc_ctrl_value_comp, compv);
/* data can be used by binary controls */
DECLARE_FLEX_ARRAY(struct sof_abi_hdr, data);
};
} __packed;
/** Event type */
enum sof_ipc_ctrl_event_type {
SOF_CTRL_EVENT_GENERIC = 0, /**< generic event */
SOF_CTRL_EVENT_GENERIC_METADATA, /**< generic event with metadata */
SOF_CTRL_EVENT_KD, /**< keyword detection event */
SOF_CTRL_EVENT_VAD, /**< voice activity detection event */
};
/**
* Generic notification data.
*/
struct sof_ipc_comp_event {
struct sof_ipc_reply rhdr;
uint16_t src_comp_type; /**< COMP_TYPE_ */
uint32_t src_comp_id; /**< source component id */
uint32_t event_type; /**< event type - SOF_CTRL_EVENT_* */
uint32_t num_elems; /**< in array elems or bytes for data type */
/* reserved for future use */
uint32_t reserved[8];
/* control data - add new types if needed */
union {
/* data can be used by binary controls */
struct sof_abi_hdr data[0];
/* event specific values */
uint32_t event_value;
};
} __packed;
#endif
linux-7.2.3/include/sound/sof/dai-amd.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2021 Advanced Micro Devices, Inc.. All rights reserved.
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_AMD_H__
#define __INCLUDE_SOUND_SOF_DAI_AMD_H__
#include <sound/sof/header.h>
/* ACP Configuration Request - SOF_IPC_DAI_AMD_CONFIG */
struct sof_ipc_dai_acp_params {
struct sof_ipc_hdr hdr;
uint32_t fsync_rate; /* FSYNC frequency in Hz */
uint32_t tdm_slots;
uint32_t tdm_mode;
} __packed;
/* ACPDMIC Configuration Request - SOF_IPC_DAI_AMD_CONFIG */
struct sof_ipc_dai_acpdmic_params {
uint32_t pdm_rate;
uint32_t pdm_ch;
} __packed;
/* ACP_SDW Configuration Request - SOF_IPC_DAI_AMD_SDW_CONFIG */
struct sof_ipc_dai_acp_sdw_params {
struct sof_ipc_hdr hdr;
u32 rate;
u32 channels;
} __packed;
#endif
linux-7.2.3/include/sound/sof/dai-imx.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Copyright 2019 NXP
*
* Author: Daniel Baluta <daniel.baluta@nxp.com>
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_IMX_H__
#define __INCLUDE_SOUND_SOF_DAI_IMX_H__
#include <sound/sof/header.h>
/* ESAI Configuration Request - SOF_IPC_DAI_ESAI_CONFIG */
struct sof_ipc_dai_esai_params {
struct sof_ipc_hdr hdr;
/* MCLK */
uint16_t reserved1;
uint16_t mclk_id;
uint32_t mclk_direction;
uint32_t mclk_rate; /* MCLK frequency in Hz */
uint32_t fsync_rate; /* FSYNC frequency in Hz */
uint32_t bclk_rate; /* BCLK frequency in Hz */
/* TDM */
uint32_t tdm_slots;
uint32_t rx_slots;
uint32_t tx_slots;
uint16_t tdm_slot_width;
uint16_t reserved2; /* alignment */
} __packed;
/* SAI Configuration Request - SOF_IPC_DAI_SAI_CONFIG */
struct sof_ipc_dai_sai_params {
struct sof_ipc_hdr hdr;
/* MCLK */
uint16_t reserved1;
uint16_t mclk_id;
uint32_t mclk_direction;
uint32_t mclk_rate; /* MCLK frequency in Hz */
uint32_t fsync_rate; /* FSYNC frequency in Hz */
uint32_t bclk_rate; /* BCLK frequency in Hz */
/* TDM */
uint32_t tdm_slots;
uint32_t rx_slots;
uint32_t tx_slots;
uint16_t tdm_slot_width;
uint16_t reserved2; /* alignment */
} __packed;
/* MICFIL Configuration Request - SOF_IPC_DAI_MICFIL_CONFIG */
struct sof_ipc_dai_micfil_params {
uint32_t pdm_rate;
uint32_t pdm_ch;
} __packed;
#endif
linux-7.2.3/include/sound/sof/dai-intel.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__
#define __INCLUDE_SOUND_SOF_DAI_INTEL_H__
#include <sound/sof/header.h>
/* ssc1: TINTE */
#define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0)
/* ssc1: PINTE */
#define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1)
/* ssc2: SMTATF */
#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2)
/* ssc2: MMRATF */
#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3)
/* ssc2: PSPSTWFDFD */
#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4)
/* ssc2: PSPSRWFDFD */
#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5)
/* ssc1: LBM */
#define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6)
/* here is the possibility to define others aux macros */
#define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38
#define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31
/* SSP clocks control settings
*
* Macros for clks_control field in sof_ipc_dai_ssp_params struct.
*/
/* mclk 0 disable */
#define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0)
/* mclk 1 disable */
#define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1)
/* mclk keep active */
#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2)
/* bclk keep active */
#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3)
/* fs keep active */
#define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4)
/* bclk idle */
#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
/* mclk early start */
#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6)
/* bclk early start */
#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7)
/* mclk always on */
#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON BIT(8)
/* DMIC max. four controllers for eight microphone channels */
#define SOF_DAI_INTEL_DMIC_NUM_CTRL 4
/* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
struct sof_ipc_dai_ssp_params {
struct sof_ipc_hdr hdr;
uint16_t reserved1;
uint16_t mclk_id;
uint32_t mclk_rate; /* mclk frequency in Hz */
uint32_t fsync_rate; /* fsync frequency in Hz */
uint32_t bclk_rate; /* bclk frequency in Hz */
/* TDM */
uint32_t tdm_slots;
uint32_t rx_slots;
uint32_t tx_slots;
/* data */
uint32_t sample_valid_bits;
uint16_t tdm_slot_width;
uint16_t reserved2; /* alignment */
/* MCLK */
uint32_t mclk_direction;
uint16_t frame_pulse_width;
uint16_t tdm_per_slot_padding_flag;
uint32_t clks_control;
uint32_t quirks;
uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
* will be driven, before sending data
*/
} __packed;
/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
struct sof_ipc_dai_hda_params {
struct sof_ipc_hdr hdr;
uint32_t link_dma_ch;
uint32_t rate;
uint32_t channels;
} __packed;
/* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
struct sof_ipc_dai_alh_params {
struct sof_ipc_hdr hdr;
uint32_t stream_id;
uint32_t rate;
uint32_t channels;
/* reserved for future use */
uint32_t reserved[13];
} __packed;
/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
/* This struct is defined per 2ch PDM controller available in the platform.
* Normally it is sufficient to set the used microphone specific enables to 1
* and keep other parameters as zero. The customizations are:
*
* 1. If a device mixes different microphones types with different polarity
* and/or the absolute polarity matters the PCM signal from a microphone
* can be inverted with the controls.
*
* 2. If the microphones in a stereo pair do not appear in captured stream
* in desired order due to board schematics choises they can be swapped with
* the clk_edge parameter.
*
* 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
* that delays the sampling time of data by half cycles of DMIC source clock
* can be tried for improvement. However there is no guarantee for this to fix
* data integrity problems.
*/
struct sof_ipc_dai_dmic_pdm_ctrl {
struct sof_ipc_hdr hdr;
uint16_t id; /**< PDM controller ID */
uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/
uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/
uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */
uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */
uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */
uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */
uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */
} __packed;
/* This struct contains the global settings for all 2ch PDM controllers. The
* version number used in configuration data is checked vs. version used by
* device driver src/drivers/dmic.c need to match. It is incremented from
* initial value 1 if updates done for the to driver would alter the operation
* of the microphone.
*
* Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
* parameters need to be set as defined in microphone data sheet. E.g. clock
* range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
* multi-mode capable and there may be denied mic clock frequencies between
* the modes. In such case set the clock range limits of the desired mode to
* avoid the driver to set clock to an illegal rate.
*
* The duty cycle could be set to 48-52% if not known. Generally these
* parameters can be altered within data sheet specified limits to match
* required audio application performance power.
*
* The microphone clock needs to be usually about 50-80 times the used audio
* sample rate. With highest sample rates above 48 kHz this can relaxed
* somewhat.
*
* The parameter wake_up_time describes how long time the microphone needs
* for the data line to produce valid output from mic clock start. The driver
* will mute the captured audio for the given time. The min_clock_on_time
* parameter is used to prevent too short clock bursts to happen. The driver
* will keep the clock active after capture stop if this time is not yet
* met. The unit for both is microseconds (us). Exceed of 100 ms will be
* treated as an error.
*/
struct sof_ipc_dai_dmic_params {
struct sof_ipc_hdr hdr;
uint32_t driver_ipc_version; /**< Version (1..N) */
uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */
uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */
uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */
uint32_t reserved_1; /**< Reserved */
uint16_t fifo_bits; /**< FIFO word length (16 or 32) */
uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */
uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */
uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */
uint32_t num_pdm_active; /**< Number of active pdm controllers. */
/**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */
uint32_t wake_up_time; /**< Time from clock start to data (us) */
uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */
uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */
/* reserved for future use */
uint32_t reserved[5];
/**< PDM controllers configuration */
struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL];
} __packed;
#endif
linux-7.2.3/include/sound/sof/dai-mediatek.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Copyright(c) 2021 Mediatek Corporation. All rights reserved.
*
* Author: Bo Pan <bo.pan@mediatek.com>
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__
#define __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__
#include <sound/sof/header.h>
struct sof_ipc_dai_mtk_afe_params {
struct sof_ipc_hdr hdr;
u32 channels;
u32 rate;
u32 format;
u32 stream_id;
u32 reserved[4]; /* reserve for future */
} __packed;
#endif
linux-7.2.3/include/sound/sof/dai.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_H__
#define __INCLUDE_SOUND_SOF_DAI_H__
#include <sound/sof/header.h>
#include <sound/sof/dai-intel.h>
#include <sound/sof/dai-imx.h>
#include <sound/sof/dai-amd.h>
#include <sound/sof/dai-mediatek.h>
/*
* DAI Configuration.
*
* Each different DAI type will have it's own structure and IPC cmd.
*/
#define SOF_DAI_FMT_I2S 1 /**< I2S mode */
#define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */
#define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */
#define SOF_DAI_FMT_DSP_A 4 /**< L data MSB after FRM LRC */
#define SOF_DAI_FMT_DSP_B 5 /**< L data MSB during FRM LRC */
#define SOF_DAI_FMT_PDM 6 /**< Pulse density modulation */
#define SOF_DAI_FMT_CONT (1 << 4) /**< continuous clock */
#define SOF_DAI_FMT_GATED (0 << 4) /**< clock is gated */
#define SOF_DAI_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */
#define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
#define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
#define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
#define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
#define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
#define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
#define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
/* keep old definitions for backwards compatibility */
#define SOF_DAI_FMT_CBM_CFM SOF_DAI_FMT_CBP_CFP
#define SOF_DAI_FMT_CBS_CFM SOF_DAI_FMT_CBC_CFP
#define SOF_DAI_FMT_CBM_CFS SOF_DAI_FMT_CBP_CFC
#define SOF_DAI_FMT_CBS_CFS SOF_DAI_FMT_CBC_CFC
#define SOF_DAI_FMT_FORMAT_MASK 0x000f
#define SOF_DAI_FMT_CLOCK_MASK 0x00f0
#define SOF_DAI_FMT_INV_MASK 0x0f00
#define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000
/*
* DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
* representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
* commands.
*/
#define SOF_DAI_CONFIG_FLAGS_CMD_MASK 0xF
#define SOF_DAI_CONFIG_FLAGS_NONE 0 /**< DAI_CONFIG sent without stage information */
#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< DAI_CONFIG sent during hw_params stage */
#define SOF_DAI_CONFIG_FLAGS_HW_FREE BIT(1) /**< DAI_CONFIG sent during hw_free stage */
/**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
#define SOF_DAI_CONFIG_FLAGS_PAUSE BIT(2)
#define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4
#define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT)
/*
* This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline
* stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available
* ABI 3.20 onwards.
*/
#define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0)
/** \brief Types of DAI */
enum sof_ipc_dai_type {
SOF_DAI_INTEL_NONE = 0, /**< None */
SOF_DAI_INTEL_SSP, /**< Intel SSP */
SOF_DAI_INTEL_DMIC, /**< Intel DMIC */
SOF_DAI_INTEL_HDA, /**< Intel HD/A */
SOF_DAI_INTEL_ALH, /**< Intel ALH */
SOF_DAI_IMX_SAI, /**< i.MX SAI */
SOF_DAI_IMX_ESAI, /**< i.MX ESAI */
SOF_DAI_AMD_BT, /**< AMD ACP BT*/
SOF_DAI_AMD_SP, /**< AMD ACP SP */
SOF_DAI_AMD_DMIC, /**< AMD ACP DMIC */
SOF_DAI_MEDIATEK_AFE, /**< Mediatek AFE */
SOF_DAI_AMD_HS, /**< Amd HS */
SOF_DAI_AMD_SP_VIRTUAL, /**< AMD ACP SP VIRTUAL */
SOF_DAI_AMD_HS_VIRTUAL, /**< AMD ACP HS VIRTUAL */
SOF_DAI_IMX_MICFIL, /** < i.MX MICFIL PDM */
SOF_DAI_AMD_SDW, /**< AMD ACP SDW */
};
/* general purpose DAI configuration */
struct sof_ipc_dai_config {
struct sof_ipc_cmd_hdr hdr;
uint32_t type; /**< DAI type - enum sof_ipc_dai_type */
uint32_t dai_index; /**< index of this type dai */
/* physical protocol and clocking */
uint16_t format; /**< SOF_DAI_FMT_ */
uint8_t group_id; /**< group ID, 0 means no group (ABI 3.17) */
uint8_t flags; /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */
/* reserved for future use */
uint32_t reserved[8];
/* HW specific data */
union {
struct sof_ipc_dai_ssp_params ssp;
struct sof_ipc_dai_dmic_params dmic;
struct sof_ipc_dai_hda_params hda;
struct sof_ipc_dai_alh_params alh;
struct sof_ipc_dai_esai_params esai;
struct sof_ipc_dai_sai_params sai;
struct sof_ipc_dai_acp_params acpbt;
struct sof_ipc_dai_acp_params acpsp;
struct sof_ipc_dai_acpdmic_params acpdmic;
struct sof_ipc_dai_acp_params acphs;
struct sof_ipc_dai_mtk_afe_params afe;
struct sof_ipc_dai_micfil_params micfil;
struct sof_ipc_dai_acp_sdw_params acp_sdw;
};
} __packed;
struct sof_dai_private_data {
struct sof_ipc_comp_dai *comp_dai;
struct sof_ipc_dai_config *dai_config;
};
#endif
linux-7.2.3/include/sound/sof/debug.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2020 Intel Corporation
*
* Author: Karol Trzcinski <karolx.trzcinski@linux.intel.com>
*/
#ifndef __INCLUDE_SOUND_SOF_DEBUG_H__
#define __INCLUDE_SOUND_SOF_DEBUG_H__
#include <sound/sof/header.h>
/** ABI3.18 */
enum sof_ipc_dbg_mem_zone {
SOF_IPC_MEM_ZONE_SYS = 0, /**< System zone */
SOF_IPC_MEM_ZONE_SYS_RUNTIME = 1, /**< System-runtime zone */
SOF_IPC_MEM_ZONE_RUNTIME = 2, /**< Runtime zone */
SOF_IPC_MEM_ZONE_BUFFER = 3, /**< Buffer zone */
SOF_IPC_MEM_ZONE_RUNTIME_SHARED = 4, /**< System runtime zone */
SOF_IPC_MEM_ZONE_SYS_SHARED = 5, /**< System shared zone */
};
/** ABI3.18 */
struct sof_ipc_dbg_mem_usage_elem {
uint32_t zone; /**< see sof_ipc_dbg_mem_zone */
uint32_t id; /**< heap index within zone */
uint32_t used; /**< number of bytes used in zone */
uint32_t free; /**< number of bytes free to use within zone */
uint32_t reserved; /**< for future use */
} __packed;
/** ABI3.18 */
struct sof_ipc_dbg_mem_usage {
struct sof_ipc_reply rhdr; /**< generic IPC reply header */
uint32_t reserved[4]; /**< reserved for future use */
uint32_t num_elems; /**< elems[] counter */
struct sof_ipc_dbg_mem_usage_elem elems[]; /**< memory usage information */
} __packed;
#endif
linux-7.2.3/include/sound/sof/ext_manifest.h
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2020 Intel Corporation
*/
/*
* Extended manifest is a place to store metadata about firmware, known during
* compilation time - for example firmware version or used compiler.
* Given information are read on host side before firmware startup.
* This part of output binary is not signed.
*/
#ifndef __SOF_FIRMWARE_EXT_MANIFEST_H__
#define __SOF_FIRMWARE_EXT_MANIFEST_H__
#include <linux/bits.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <sound/sof/info.h>
/* In ASCII `XMan` */
#define SOF_EXT_MAN_MAGIC_NUMBER 0x6e614d58
/* Build u32 number in format MMmmmppp */
#define SOF_EXT_MAN_BUILD_VERSION(MAJOR, MINOR, PATH) ((uint32_t)( \
((MAJOR) << 24) | \
((MINOR) << 12) | \
(PATH)))
/* check extended manifest version consistency */
#define SOF_EXT_MAN_VERSION_INCOMPATIBLE(host_ver, cli_ver) ( \
((host_ver) & GENMASK(31, 24)) != \
((cli_ver) & GENMASK(31, 24)))
/* used extended manifest header version */
#define SOF_EXT_MAN_VERSION SOF_EXT_MAN_BUILD_VERSION(1, 0, 0)
/* extended manifest header, deleting any field breaks backward compatibility */
struct sof_ext_man_header {
uint32_t magic; /*< identification number, */
/*< EXT_MAN_MAGIC_NUMBER */
uint32_t full_size; /*< [bytes] full size of ext_man, */
/*< (header + content + padding) */
uint32_t header_size; /*< [bytes] makes header extensionable, */
/*< after append new field to ext_man header */
/*< then backward compatible won't be lost */
uint32_t header_version; /*< value of EXT_MAN_VERSION */
/*< not related with following content */
/* just after this header should be list of ext_man_elem_* elements */
} __packed;
/* Now define extended manifest elements */
/* Extended manifest elements types */
enum sof_ext_man_elem_type {
SOF_EXT_MAN_ELEM_FW_VERSION = 0,
SOF_EXT_MAN_ELEM_WINDOW = 1,
SOF_EXT_MAN_ELEM_CC_VERSION = 2,
SOF_EXT_MAN_ELEM_PROBE_INFO = 3,
SOF_EXT_MAN_ELEM_DBG_ABI = 4,
SOF_EXT_MAN_ELEM_CONFIG_DATA = 5, /**< ABI3.17 */
SOF_EXT_MAN_ELEM_PLATFORM_CONFIG_DATA = 6,
};
/* extended manifest element header */
struct sof_ext_man_elem_header {
uint32_t type; /*< SOF_EXT_MAN_ELEM_ */
uint32_t size; /*< in bytes, including header size */
/* just after this header should be type dependent content */
} __packed;
/* FW version */
struct sof_ext_man_fw_version {
struct sof_ext_man_elem_header hdr;
/* use sof_ipc struct because of code re-use */
struct sof_ipc_fw_version version;
uint32_t flags;
} __packed;
/* extended data memory windows for IPC, trace and debug */
struct sof_ext_man_window {
struct sof_ext_man_elem_header hdr;
/* use sof_ipc struct because of code re-use */
struct sof_ipc_window ipc_window;
} __packed;
/* Used C compiler description */
struct sof_ext_man_cc_version {
struct sof_ext_man_elem_header hdr;
/* use sof_ipc struct because of code re-use */
struct sof_ipc_cc_version cc_version;
} __packed;
struct ext_man_dbg_abi {
struct sof_ext_man_elem_header hdr;
/* use sof_ipc struct because of code re-use */
struct sof_ipc_user_abi_version dbg_abi;
} __packed;
/* EXT_MAN_ELEM_CONFIG_DATA elements identificators, ABI3.17 */
enum config_elem_type {
SOF_EXT_MAN_CONFIG_EMPTY = 0,
SOF_EXT_MAN_CONFIG_IPC_MSG_SIZE = 1,
SOF_EXT_MAN_CONFIG_MEMORY_USAGE_SCAN = 2, /**< ABI 3.18 */
};
struct sof_config_elem {
uint32_t token;
uint32_t value;
} __packed;
/* firmware configuration information */
struct sof_ext_man_config_data {
struct sof_ext_man_elem_header hdr;
struct sof_config_elem elems[];
} __packed;
#endif /* __SOF_FIRMWARE_EXT_MANIFEST_H__ */
linux-7.2.3/include/sound/sof/ext_manifest4.h
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2022 Intel Corporation
*/
/*
* Extended manifest is a place to store metadata about firmware, known during
* compilation time - for example firmware version or used compiler.
* Given information are read on host side before firmware startup.
* This part of output binary is not signed.
*/
#ifndef __SOF_FIRMWARE_EXT_MANIFEST4_H__
#define __SOF_FIRMWARE_EXT_MANIFEST4_H__
#include <linux/uuid.h>
/* In ASCII $AE1 */
#define SOF_EXT_MAN4_MAGIC_NUMBER 0x31454124
#define MAX_MODULE_NAME_LEN 8
#define MAX_FW_BINARY_NAME 8
#define DEFAULT_HASH_SHA256_LEN 32
#define SOF_MAN4_FW_HDR_OFFSET 0x2000
#define SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5 0x284
/*********************************************************************
* extended manifest (struct sof_ext_manifest4_hdr)
*-------------------
* css_manifest hdr
*-------------------
* offset reserved for future
*-------------------
* fw_hdr (struct sof_man4_fw_binary_header)
*-------------------
* module_entry[0] (struct sof_man4_module)
*-------------------
* module_entry[1]
*-------------------
* ...
*-------------------
* module_entry[n]
*-------------------
* module_config[0] (struct sof_man4_module_config)
*-------------------
* module_config[1]
*-------------------
* ...
*-------------------
* module_config[m]
*-------------------
* FW content
*-------------------
*********************************************************************/
struct sof_ext_manifest4_hdr {
uint32_t id;
uint32_t len; /* length of extension manifest */
uint16_t version_major; /* header version */
uint16_t version_minor;
uint32_t num_module_entries;
} __packed;
struct sof_man4_fw_binary_header {
/* This part must be unchanged to be backward compatible with SPT-LP ROM */
uint32_t id;
uint32_t len; /* sizeof(sof_man4_fw_binary_header) in bytes */
uint8_t name[MAX_FW_BINARY_NAME];
uint32_t preload_page_count; /* number of pages of preloaded image */
uint32_t fw_image_flags;
uint32_t feature_mask;
uint16_t major_version; /* Firmware version */
uint16_t minor_version;
uint16_t hotfix_version;
uint16_t build_version;
uint32_t num_module_entries;
/* This part may change to contain any additional data for BaseFw that is skipped by ROM */
uint32_t hw_buf_base_addr;
uint32_t hw_buf_length;
uint32_t load_offset; /* This value is used by ROM */
} __packed;
struct sof_man4_segment_desc {
uint32_t flags;
uint32_t v_base_addr;
uint32_t file_offset;
} __packed;
struct sof_man4_module {
uint32_t id;
uint8_t name[MAX_MODULE_NAME_LEN];
guid_t uuid;
uint32_t type;
uint8_t hash[DEFAULT_HASH_SHA256_LEN];
uint32_t entry_point;
uint16_t cfg_offset;
uint16_t cfg_count;
uint32_t affinity_mask;
uint16_t instance_max_count;
uint16_t instance_stack_size;
struct sof_man4_segment_desc segments[3];
} __packed;
struct sof_man4_module_config {
uint32_t par[4]; /* module parameters */
uint32_t is_bytes; /* actual size of instance .bss (bytes) */
uint32_t cps; /* cycles per second */
uint32_t ibs; /* input buffer size (bytes) */
uint32_t obs; /* output buffer size (bytes) */
uint32_t module_flags; /* flags, reserved for future use */
uint32_t cpc; /* cycles per single run */
uint32_t obls; /* output block size, reserved for future use */
} __packed;
#endif /* __SOF_FIRMWARE_EXT_MANIFEST4_H__ */
linux-7.2.3/include/sound/sof/header.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_HEADER_H__
#define __INCLUDE_SOUND_SOF_HEADER_H__
#include <linux/types.h>
#include <uapi/sound/sof/abi.h>
/** \addtogroup sof_uapi uAPI
* SOF uAPI specification.
* @{
*/
/*
* IPC messages have a prefixed 32 bit identifier made up as follows :-
*
* 0xGCCCNNNN where
* G is global cmd type (4 bits)
* C is command type (12 bits)
* I is the ID number (16 bits) - monotonic and overflows
*
* This is sent at the start of the IPM message in the mailbox. Messages should
* not be sent in the doorbell (special exceptions for firmware .
*/
/* Global Message - Generic */
#define SOF_GLB_TYPE_SHIFT 28
#define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT)
#define SOF_GLB_TYPE(x) ((x) << SOF_GLB_TYPE_SHIFT)
/* Command Message - Generic */
#define SOF_CMD_TYPE_SHIFT 16
#define SOF_CMD_TYPE_MASK (0xfffL << SOF_CMD_TYPE_SHIFT)
#define SOF_CMD_TYPE(x) ((x) << SOF_CMD_TYPE_SHIFT)
/* Global Message Types */
#define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U)
#define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U)
#define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U)
#define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U)
#define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U)
#define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U)
#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U)
#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U)
#define SOF_IPC_GLB_GDB_DEBUG SOF_GLB_TYPE(0xAU)
#define SOF_IPC_GLB_TEST_MSG SOF_GLB_TYPE(0xBU)
#define SOF_IPC_GLB_PROBE SOF_GLB_TYPE(0xCU)
#define SOF_IPC_GLB_DEBUG SOF_GLB_TYPE(0xDU)
/*
* DSP Command Message Types
*/
/* topology */
#define SOF_IPC_TPLG_COMP_NEW SOF_CMD_TYPE(0x001)
#define SOF_IPC_TPLG_COMP_FREE SOF_CMD_TYPE(0x002)
#define SOF_IPC_TPLG_COMP_CONNECT SOF_CMD_TYPE(0x003)
#define SOF_IPC_TPLG_PIPE_NEW SOF_CMD_TYPE(0x010)
#define SOF_IPC_TPLG_PIPE_FREE SOF_CMD_TYPE(0x011)
#define SOF_IPC_TPLG_PIPE_CONNECT SOF_CMD_TYPE(0x012)
#define SOF_IPC_TPLG_PIPE_COMPLETE SOF_CMD_TYPE(0x013)
#define SOF_IPC_TPLG_BUFFER_NEW SOF_CMD_TYPE(0x020)
#define SOF_IPC_TPLG_BUFFER_FREE SOF_CMD_TYPE(0x021)
/* PM */
#define SOF_IPC_PM_CTX_SAVE SOF_CMD_TYPE(0x001)
#define SOF_IPC_PM_CTX_RESTORE SOF_CMD_TYPE(0x002)
#define SOF_IPC_PM_CTX_SIZE SOF_CMD_TYPE(0x003)
#define SOF_IPC_PM_CLK_SET SOF_CMD_TYPE(0x004)
#define SOF_IPC_PM_CLK_GET SOF_CMD_TYPE(0x005)
#define SOF_IPC_PM_CLK_REQ SOF_CMD_TYPE(0x006)
#define SOF_IPC_PM_CORE_ENABLE SOF_CMD_TYPE(0x007)
#define SOF_IPC_PM_GATE SOF_CMD_TYPE(0x008)
/* component runtime config - multiple different types */
#define SOF_IPC_COMP_SET_VALUE SOF_CMD_TYPE(0x001)
#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002)
#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003)
#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004)
#define SOF_IPC_COMP_NOTIFICATION SOF_CMD_TYPE(0x005)
/* DAI messages */
#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001)
#define SOF_IPC_DAI_LOOPBACK SOF_CMD_TYPE(0x002)
/* stream */
#define SOF_IPC_STREAM_PCM_PARAMS SOF_CMD_TYPE(0x001)
#define SOF_IPC_STREAM_PCM_PARAMS_REPLY SOF_CMD_TYPE(0x002)
#define SOF_IPC_STREAM_PCM_FREE SOF_CMD_TYPE(0x003)
#define SOF_IPC_STREAM_TRIG_START SOF_CMD_TYPE(0x004)
#define SOF_IPC_STREAM_TRIG_STOP SOF_CMD_TYPE(0x005)
#define SOF_IPC_STREAM_TRIG_PAUSE SOF_CMD_TYPE(0x006)
#define SOF_IPC_STREAM_TRIG_RELEASE SOF_CMD_TYPE(0x007)
#define SOF_IPC_STREAM_TRIG_DRAIN SOF_CMD_TYPE(0x008)
#define SOF_IPC_STREAM_TRIG_XRUN SOF_CMD_TYPE(0x009)
#define SOF_IPC_STREAM_POSITION SOF_CMD_TYPE(0x00a)
#define SOF_IPC_STREAM_VORBIS_PARAMS SOF_CMD_TYPE(0x010)
#define SOF_IPC_STREAM_VORBIS_FREE SOF_CMD_TYPE(0x011)
/* probe */
#define SOF_IPC_PROBE_INIT SOF_CMD_TYPE(0x001)
#define SOF_IPC_PROBE_DEINIT SOF_CMD_TYPE(0x002)
#define SOF_IPC_PROBE_DMA_ADD SOF_CMD_TYPE(0x003)
#define SOF_IPC_PROBE_DMA_INFO SOF_CMD_TYPE(0x004)
#define SOF_IPC_PROBE_DMA_REMOVE SOF_CMD_TYPE(0x005)
#define SOF_IPC_PROBE_POINT_ADD SOF_CMD_TYPE(0x006)
#define SOF_IPC_PROBE_POINT_INFO SOF_CMD_TYPE(0x007)
#define SOF_IPC_PROBE_POINT_REMOVE SOF_CMD_TYPE(0x008)
/* trace */
#define SOF_IPC_TRACE_DMA_PARAMS SOF_CMD_TYPE(0x001)
#define SOF_IPC_TRACE_DMA_POSITION SOF_CMD_TYPE(0x002)
#define SOF_IPC_TRACE_DMA_PARAMS_EXT SOF_CMD_TYPE(0x003)
#define SOF_IPC_TRACE_FILTER_UPDATE SOF_CMD_TYPE(0x004) /**< ABI3.17 */
#define SOF_IPC_TRACE_DMA_FREE SOF_CMD_TYPE(0x005) /**< ABI3.20 */
/* debug */
#define SOF_IPC_DEBUG_MEM_USAGE SOF_CMD_TYPE(0x001)
/* test */
#define SOF_IPC_TEST_IPC_FLOOD SOF_CMD_TYPE(0x001)
/* Get message component id */
#define SOF_IPC_MESSAGE_ID(x) ((x) & 0xffff)
/* maximum message size for mailbox Tx/Rx */
#define SOF_IPC_MSG_MAX_SIZE 384
/*
* Structure Header - Header for all IPC structures except command structs.
* The size can be greater than the structure size and that means there is
* extended bespoke data beyond the end of the structure including variable
* arrays.
*/
struct sof_ipc_hdr {
uint32_t size; /**< size of structure */
} __packed;
/*
* Command Header - Header for all IPC commands. Identifies IPC message.
* The size can be greater than the structure size and that means there is
* extended bespoke data beyond the end of the structure including variable
* arrays.
*/
struct sof_ipc_cmd_hdr {
uint32_t size; /**< size of structure */
uint32_t cmd; /**< SOF_IPC_GLB_ + cmd */
} __packed;
/*
* Generic reply message. Some commands override this with their own reply
* types that must include this at start.
*/
struct sof_ipc_reply {
struct sof_ipc_cmd_hdr hdr;
int32_t error; /**< negative error numbers */
} __packed;
/*
* Compound commands - SOF_IPC_GLB_COMPOUND.
*
* Compound commands are sent to the DSP as a single IPC operation. The
* commands are split into blocks and each block has a header. This header
* identifies the command type and the number of commands before the next
* header.
*/
struct sof_ipc_compound_hdr {
struct sof_ipc_cmd_hdr hdr;
uint32_t count; /**< count of 0 means end of compound sequence */
} __packed;
/**
* OOPS header architecture specific data.
*/
struct sof_ipc_dsp_oops_arch_hdr {
uint32_t arch; /* Identifier of architecture */
uint32_t totalsize; /* Total size of oops message */
} __packed;
/**
* OOPS header platform specific data.
*/
struct sof_ipc_dsp_oops_plat_hdr {
uint32_t configidhi; /* ConfigID hi 32bits */
uint32_t configidlo; /* ConfigID lo 32bits */
uint32_t numaregs; /* Special regs num */
uint32_t stackoffset; /* Offset to stack pointer from beginning of
* oops message
*/
uint32_t stackptr; /* Stack ptr */
} __packed;
/** @}*/
#endif
linux-7.2.3/include/sound/sof/info.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_INFO_H__
#define __INCLUDE_SOUND_SOF_INFO_H__
#include <sound/sof/header.h>
#include <sound/sof/stream.h>
/*
* Firmware boot and version
*/
#define SOF_IPC_MAX_ELEMS 16
/*
* Firmware boot info flag bits (64-bit)
*/
#define SOF_IPC_INFO_BUILD BIT(0)
#define SOF_IPC_INFO_LOCKS BIT(1)
#define SOF_IPC_INFO_LOCKSV BIT(2)
#define SOF_IPC_INFO_GDB BIT(3)
#define SOF_IPC_INFO_D3_PERSISTENT BIT(4)
/* extended data types that can be appended onto end of sof_ipc_fw_ready */
enum sof_ipc_ext_data {
SOF_IPC_EXT_UNUSED = 0,
SOF_IPC_EXT_WINDOW = 1,
SOF_IPC_EXT_CC_INFO = 2,
SOF_IPC_EXT_PROBE_INFO = 3,
SOF_IPC_EXT_USER_ABI_INFO = 4,
};
/* Build u32 number in format MMmmmppp */
#define SOF_FW_VER(MAJOR, MINOR, PATCH) ((uint32_t)( \
((MAJOR) << 24) | ((MINOR) << 12) | (PATCH)))
/* FW version - SOF_IPC_GLB_VERSION */
struct sof_ipc_fw_version {
struct sof_ipc_hdr hdr;
uint16_t major;
uint16_t minor;
uint16_t micro;
uint16_t build;
uint8_t date[12];
uint8_t time[10];
uint8_t tag[6];
uint32_t abi_version;
/* used to check FW and ldc file compatibility, reproducible value */
uint32_t src_hash;
/* reserved for future use */
uint32_t reserved[3];
} __packed;
/* FW ready Message - sent by firmware when boot has completed */
struct sof_ipc_fw_ready {
struct sof_ipc_cmd_hdr hdr;
uint32_t dspbox_offset; /* dsp initiated IPC mailbox */
uint32_t hostbox_offset; /* host initiated IPC mailbox */
uint32_t dspbox_size;
uint32_t hostbox_size;
struct sof_ipc_fw_version version;
/* Miscellaneous flags */
uint64_t flags;
/* reserved for future use */
uint32_t reserved[4];
} __packed;
/*
* Extended Firmware data. All optional, depends on platform/arch.
*/
enum sof_ipc_region {
SOF_IPC_REGION_DOWNBOX = 0,
SOF_IPC_REGION_UPBOX,
SOF_IPC_REGION_TRACE,
SOF_IPC_REGION_DEBUG,
SOF_IPC_REGION_STREAM,
SOF_IPC_REGION_REGS,
SOF_IPC_REGION_EXCEPTION,
};
struct sof_ipc_ext_data_hdr {
struct sof_ipc_cmd_hdr hdr;
uint32_t type; /**< SOF_IPC_EXT_ */
} __packed;
struct sof_ipc_window_elem {
struct sof_ipc_hdr hdr;
uint32_t type; /**< SOF_IPC_REGION_ */
uint32_t id; /**< platform specific - used to map to host memory */
uint32_t flags; /**< R, W, RW, etc - to define */
uint32_t size; /**< size of region in bytes */
/* offset in window region as windows can be partitioned */
uint32_t offset;
} __packed;
/* extended data memory windows for IPC, trace and debug */
struct sof_ipc_window {
struct sof_ipc_ext_data_hdr ext_hdr;
uint32_t num_windows;
struct sof_ipc_window_elem window[SOF_IPC_MAX_ELEMS];
} __packed;
struct sof_ipc_cc_version {
struct sof_ipc_ext_data_hdr ext_hdr;
uint32_t major;
uint32_t minor;
uint32_t micro;
/* reserved for future use */
uint32_t reserved[4];
uint8_t name[16]; /* null terminated compiler name */
uint8_t optim[4]; /* null terminated compiler -O flag value */
uint8_t desc[32]; /* null terminated compiler description */
} __packed;
/* extended data: Probe setup */
struct sof_ipc_probe_support {
struct sof_ipc_ext_data_hdr ext_hdr;
uint32_t probe_points_max;
uint32_t injection_dmas_max;
/* reserved for future use */
uint32_t reserved[2];
} __packed;
/* extended data: user abi version(s) */
struct sof_ipc_user_abi_version {
struct sof_ipc_ext_data_hdr ext_hdr;
uint32_t abi_dbg_version;
} __packed;
#endif
linux-7.2.3/include/sound/sof/ipc4/header.h
+666
View File
@@ -0,0 +1,666 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2022 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
#define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
#include <linux/types.h>
#include <uapi/sound/sof/abi.h>
/* maximum message size for mailbox Tx/Rx */
#define SOF_IPC4_MSG_MAX_SIZE 4096
/** \addtogroup sof_uapi uAPI
* SOF uAPI specification.
* @{
*/
/**
* struct sof_ipc4_msg - Placeholder of an IPC4 message
* @header_u64: IPC4 header as single u64 number
* @primary: Primary, mandatory part of the header
* @extension: Extended part of the header, if not used it should be
* set to 0
* @data_size: Size of data in bytes pointed by @data_ptr
* @data_ptr: Pointer to the optional payload of a message
*/
struct sof_ipc4_msg {
union {
u64 header_u64;
struct {
u32 primary;
u32 extension;
};
};
size_t data_size;
void *data_ptr;
};
/**
* struct sof_ipc4_tuple - Generic type/ID and parameter tuple
* @type: type/ID
* @size: size of the @value array in bytes
* @value: value for the given type
*/
struct sof_ipc4_tuple {
uint32_t type;
uint32_t size;
uint32_t value[];
} __packed;
/*
* IPC4 messages have two 32 bit identifier made up as follows :-
*
* header - msg type, msg id, msg direction ...
* extension - extra params such as msg data size in mailbox
*
* These are sent at the start of the IPC message in the mailbox. Messages
* should not be sent in the doorbell (special exceptions for firmware).
*/
/*
* IPC4 primary header bit allocation for messages
* bit 0-23: message type specific
* bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
* enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
* bit 29: response - sof_ipc4_msg_dir
* bit 30: target - enum sof_ipc4_msg_target
* bit 31: reserved, unused
*/
/* Value of target field - must fit into 1 bit */
enum sof_ipc4_msg_target {
/* Global FW message */
SOF_IPC4_FW_GEN_MSG,
/* Module message */
SOF_IPC4_MODULE_MSG
};
/* Value of type field - must fit into 5 bits */
enum sof_ipc4_global_msg {
SOF_IPC4_GLB_BOOT_CONFIG,
SOF_IPC4_GLB_ROM_CONTROL,
SOF_IPC4_GLB_IPCGATEWAY_CMD,
/* 3 .. 12: RESERVED - do not use */
SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13,
SOF_IPC4_GLB_CHAIN_DMA,
SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES,
SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES,
/* pipeline settings */
SOF_IPC4_GLB_CREATE_PIPELINE,
SOF_IPC4_GLB_DELETE_PIPELINE,
SOF_IPC4_GLB_SET_PIPELINE_STATE,
SOF_IPC4_GLB_GET_PIPELINE_STATE,
SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE,
SOF_IPC4_GLB_SAVE_PIPELINE,
SOF_IPC4_GLB_RESTORE_PIPELINE,
/*
* library loading
*
* Loads library (using Code Load or HD/A Host Output DMA)
*/
SOF_IPC4_GLB_LOAD_LIBRARY,
/*
* Prepare the host DMA channel for library loading, must be followed by
* a SOF_IPC4_GLB_LOAD_LIBRARY message as the library loading step
*/
SOF_IPC4_GLB_LOAD_LIBRARY_PREPARE,
SOF_IPC4_GLB_INTERNAL_MESSAGE,
/* Notification (FW to SW driver) */
SOF_IPC4_GLB_NOTIFICATION,
/* 28 .. 31: RESERVED - do not use */
SOF_IPC4_GLB_TYPE_LAST,
};
/* Value of response field - must fit into 1 bit */
enum sof_ipc4_msg_dir {
SOF_IPC4_MSG_REQUEST,
SOF_IPC4_MSG_REPLY,
};
enum sof_ipc4_pipeline_state {
SOF_IPC4_PIPE_INVALID_STATE,
SOF_IPC4_PIPE_UNINITIALIZED,
SOF_IPC4_PIPE_RESET,
SOF_IPC4_PIPE_PAUSED,
SOF_IPC4_PIPE_RUNNING,
SOF_IPC4_PIPE_EOS
};
/* Generic message fields (bit 24-30) */
/* encoded to header's msg_tgt field */
#define SOF_IPC4_MSG_TARGET_SHIFT 30
#define SOF_IPC4_MSG_TARGET_MASK BIT(30)
#define SOF_IPC4_MSG_TARGET(x) ((x) << SOF_IPC4_MSG_TARGET_SHIFT)
#define SOF_IPC4_MSG_IS_MODULE_MSG(x) ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0)
/* encoded to header's rsp field */
#define SOF_IPC4_MSG_DIR_SHIFT 29
#define SOF_IPC4_MSG_DIR_MASK BIT(29)
#define SOF_IPC4_MSG_DIR(x) ((x) << SOF_IPC4_MSG_DIR_SHIFT)
/* encoded to header's type field */
#define SOF_IPC4_MSG_TYPE_SHIFT 24
#define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24)
#define SOF_IPC4_MSG_TYPE_SET(x) (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \
SOF_IPC4_MSG_TYPE_MASK)
#define SOF_IPC4_MSG_TYPE_GET(x) (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \
SOF_IPC4_MSG_TYPE_SHIFT)
/* Global message type specific field definitions */
/* pipeline creation ipc msg */
#define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT 16
#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16)
#define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT)
#define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT 11
#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11)
#define SOF_IPC4_GLB_PIPE_PRIORITY(x) ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT)
#define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT 0
#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0)
#define SOF_IPC4_GLB_PIPE_MEM_SIZE(x) ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT)
#define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT 0
#define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0)
#define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT)
#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT 20
#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20)
#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT)
/* pipeline set state ipc msg */
#define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16
#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16)
#define SOF_IPC4_GLB_PIPE_STATE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT)
#define SOF_IPC4_GLB_PIPE_STATE_SHIFT 0
#define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0)
#define SOF_IPC4_GLB_PIPE_STATE(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT)
/* pipeline set state IPC msg extension */
#define SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI BIT(0)
/* load library ipc msg */
#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16
#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT)
/* chain dma ipc message */
#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0
#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0)
#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \
SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK)
#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8
#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8)
#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \
SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK)
#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16
#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16)
#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT)
#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17
#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17)
#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT)
#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18
#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18)
#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT)
#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0
#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0)
#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \
SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \
SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK)
enum sof_ipc4_channel_config {
/* one channel only. */
SOF_IPC4_CHANNEL_CONFIG_MONO,
/* L & R. */
SOF_IPC4_CHANNEL_CONFIG_STEREO,
/* L, R & LFE; PCM only. */
SOF_IPC4_CHANNEL_CONFIG_2_POINT_1,
/* L, C & R; MP3 & AAC only. */
SOF_IPC4_CHANNEL_CONFIG_3_POINT_0,
/* L, C, R & LFE; PCM only. */
SOF_IPC4_CHANNEL_CONFIG_3_POINT_1,
/* L, R, Ls & Rs; PCM only. */
SOF_IPC4_CHANNEL_CONFIG_QUATRO,
/* L, C, R & Cs; MP3 & AAC only. */
SOF_IPC4_CHANNEL_CONFIG_4_POINT_0,
/* L, C, R, Ls & Rs. */
SOF_IPC4_CHANNEL_CONFIG_5_POINT_0,
/* L, C, R, Ls, Rs & LFE. */
SOF_IPC4_CHANNEL_CONFIG_5_POINT_1,
/* one channel replicated in two. */
SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO,
/* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */
SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0,
/* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */
SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1,
/* L, C, R, Ls, Rs & LFE., LS, RS */
SOF_IPC4_CHANNEL_CONFIG_7_POINT_1,
};
enum sof_ipc4_interleaved_style {
SOF_IPC4_CHANNELS_INTERLEAVED,
SOF_IPC4_CHANNELS_NONINTERLEAVED,
};
enum sof_ipc4_sample_type {
SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */
SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */
};
struct sof_ipc4_audio_format {
uint32_t sampling_frequency;
uint32_t bit_depth;
uint32_t ch_map;
uint32_t ch_cfg; /* sof_ipc4_channel_config */
uint32_t interleaving_style;
uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */
} __packed __aligned(4);
#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT 0
#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0)
#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \
((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK)
#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8
#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8)
#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x) \
(((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \
SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT)
#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16
#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16)
#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x) \
(((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >> \
SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT)
/* Module message type specific field definitions */
enum sof_ipc4_module_type {
SOF_IPC4_MOD_INIT_INSTANCE,
SOF_IPC4_MOD_CONFIG_GET,
SOF_IPC4_MOD_CONFIG_SET,
SOF_IPC4_MOD_LARGE_CONFIG_GET,
SOF_IPC4_MOD_LARGE_CONFIG_SET,
SOF_IPC4_MOD_BIND,
SOF_IPC4_MOD_UNBIND,
SOF_IPC4_MOD_SET_DX,
SOF_IPC4_MOD_SET_D0IX,
SOF_IPC4_MOD_ENTER_MODULE_RESTORE,
SOF_IPC4_MOD_EXIT_MODULE_RESTORE,
SOF_IPC4_MOD_DELETE_INSTANCE,
SOF_IPC4_MOD_TYPE_LAST,
};
struct sof_ipc4_base_module_cfg {
uint32_t cpc; /* the max count of Cycles Per Chunk processing */
uint32_t ibs; /* input Buffer Size (in bytes) */
uint32_t obs; /* output Buffer Size (in bytes) */
uint32_t is_pages; /* number of physical pages used */
struct sof_ipc4_audio_format audio_fmt;
} __packed __aligned(4);
/* common module ipc msg */
#define SOF_IPC4_MOD_INSTANCE_SHIFT 16
#define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16)
#define SOF_IPC4_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT)
#define SOF_IPC4_MOD_INSTANCE_GET(x) (((x) & SOF_IPC4_MOD_INSTANCE_MASK) \
>> SOF_IPC4_MOD_INSTANCE_SHIFT)
#define SOF_IPC4_MOD_ID_SHIFT 0
#define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0)
#define SOF_IPC4_MOD_ID(x) ((x) << SOF_IPC4_MOD_ID_SHIFT)
#define SOF_IPC4_MOD_ID_GET(x) (((x) & SOF_IPC4_MOD_ID_MASK) \
>> SOF_IPC4_MOD_ID_SHIFT)
/* init module ipc msg */
#define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT 0
#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0)
#define SOF_IPC4_MOD_EXT_PARAM_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT)
#define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT 16
#define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16)
#define SOF_IPC4_MOD_EXT_PPL_ID(x) ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT)
#define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT 24
#define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24)
#define SOF_IPC4_MOD_EXT_CORE_ID(x) ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT)
#define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT 28
#define SOF_IPC4_MOD_EXT_DOMAIN_MASK BIT(28)
#define SOF_IPC4_MOD_EXT_DOMAIN(x) ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT)
#define SOF_IPC4_MOD_EXT_EXTENDED_INIT_SHIFT 29
#define SOF_IPC4_MOD_EXT_EXTENDED_INIT_MASK BIT(29)
#define SOF_IPC4_MOD_EXT_EXTENDED_INIT(x) ((x) << SOF_IPC4_MOD_EXT_EXTENDED_SHIFT)
/* bind/unbind module ipc msg */
#define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT 0
#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0)
#define SOF_IPC4_MOD_EXT_DST_MOD_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT)
#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16
#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16)
#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT)
#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24
#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24)
#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT)
#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27
#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27)
#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT)
#define MOD_ENABLE_LOG 6
#define MOD_SYSTEM_TIME 20
/* set module large config */
#define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT 0
#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0)
#define SOF_IPC4_MOD_EXT_MSG_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT)
#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20
#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20)
#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x) ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT)
#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT 28
#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK BIT(28)
#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT)
#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT 29
#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK BIT(29)
#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT)
/* Init instance messagees */
#define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID 0
#define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID 0
enum sof_ipc4_base_fw_params {
SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6,
SOF_IPC4_FW_PARAM_FW_CONFIG,
SOF_IPC4_FW_PARAM_HW_CONFIG_GET,
SOF_IPC4_FW_PARAM_MODULES_INFO_GET,
SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16,
SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20,
SOF_IPC4_FW_PARAM_MIC_PRIVACY_STATE_CHANGE = 35,
};
enum sof_ipc4_fw_config_params {
SOF_IPC4_FW_CFG_FW_VERSION,
SOF_IPC4_FW_CFG_MEMORY_RECLAIMED,
SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ,
SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ,
SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG,
SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL,
SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES,
SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES,
SOF_IPC4_FW_CFG_TRACE_LOG_BYTES,
SOF_IPC4_FW_CFG_MAX_PPL_COUNT,
SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT,
SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT,
SOF_IPC4_FW_CFG_MODULES_COUNT,
SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT,
SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT,
SOF_IPC4_FW_CFG_LL_PRI_COUNT,
SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT,
SOF_IPC4_FW_CFG_MAX_LIBS_COUNT,
SOF_IPC4_FW_CFG_SCHEDULER_CONFIG,
SOF_IPC4_FW_CFG_XTAL_FREQ_HZ,
SOF_IPC4_FW_CFG_CLOCKS_CONFIG,
SOF_IPC4_FW_CFG_RESERVED,
SOF_IPC4_FW_CFG_POWER_GATING_POLICY,
SOF_IPC4_FW_CFG_ASSERT_MODE,
SOF_IPC4_FW_RESERVED1,
SOF_IPC4_FW_RESERVED2,
SOF_IPC4_FW_RESERVED3,
SOF_IPC4_FW_RESERVED4,
SOF_IPC4_FW_RESERVED5,
SOF_IPC4_FW_CONTEXT_SAVE
};
struct sof_ipc4_fw_version {
uint16_t major;
uint16_t minor;
uint16_t hotfix;
uint16_t build;
} __packed;
/* Payload data for SOF_IPC4_MOD_SET_DX */
struct sof_ipc4_dx_state_info {
/* core(s) to apply the change */
uint32_t core_mask;
/* core state: 0: put core_id to D3; 1: put core_id to D0 */
uint32_t dx_mask;
} __packed __aligned(4);
enum sof_ipc4_hw_config_params {
SOF_IPC4_HW_CFG_INTEL_MIC_PRIVACY_CAPS = 11,
};
#define SOF_IPC_INTEL_MIC_PRIVACY_VERSION_PTL 1
struct sof_ipc4_intel_mic_privacy_cap {
uint32_t version;
uint32_t capabilities_length;
uint32_t capabilities[];
} __packed;
/* Reply messages */
/*
* IPC4 primary header bit allocation for replies
* bit 0-23: status
* bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
* enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
* bit 29: response - sof_ipc4_msg_dir
* bit 30: target - enum sof_ipc4_msg_target
* bit 31: reserved, unused
*/
#define SOF_IPC4_REPLY_STATUS GENMASK(23, 0)
/* Notification messages */
/*
* IPC4 primary header bit allocation for notifications
* bit 0-15: notification type specific
* bit 16-23: enum sof_ipc4_notification_type
* bit 24-28: SOF_IPC4_GLB_NOTIFICATION
* bit 29: response - sof_ipc4_msg_dir
* bit 30: target - enum sof_ipc4_msg_target
* bit 31: reserved, unused
*/
#define SOF_IPC4_MSG_IS_NOTIFICATION(x) (SOF_IPC4_MSG_TYPE_GET(x) == \
SOF_IPC4_GLB_NOTIFICATION)
#define SOF_IPC4_NOTIFICATION_TYPE_SHIFT 16
#define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16)
#define SOF_IPC4_NOTIFICATION_TYPE_GET(x) (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \
SOF_IPC4_NOTIFICATION_TYPE_SHIFT)
#define SOF_IPC4_LOG_CORE_SHIFT 12
#define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12)
#define SOF_IPC4_LOG_CORE_GET(x) (((x) & SOF_IPC4_LOG_CORE_MASK) >> \
SOF_IPC4_LOG_CORE_SHIFT)
#define SOF_IPC4_FW_READY_LIB_RESTORED BIT(15)
/* Value of notification type field - must fit into 8 bits */
enum sof_ipc4_notification_type {
/* Phrase detected (notification from WoV module) */
SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4,
/* Event from a resource (pipeline or module instance) */
SOF_IPC4_NOTIFY_RESOURCE_EVENT,
/* Debug log buffer status changed */
SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS,
/* Timestamp captured at the link */
SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED,
/* FW complete initialization */
SOF_IPC4_NOTIFY_FW_READY,
/* Audio classifier result (ACA) */
SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT,
/* Exception caught by DSP FW */
SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT,
/* 11 is skipped by the existing cavs firmware */
/* Custom module notification */
SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12,
/* 13 is reserved - do not use */
/* Probe notify data available */
SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14,
/* AM module notifications */
SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE,
SOF_IPC4_NOTIFY_TYPE_LAST,
};
struct sof_ipc4_notify_resource_data {
uint32_t resource_type;
uint32_t resource_id;
uint32_t event_type;
uint32_t reserved;
uint32_t data[6];
} __packed __aligned(4);
#define SOF_IPC4_DEBUG_DESCRIPTOR_SIZE 12 /* 3 x u32 */
/*
* The debug memory window is divided into 16 slots, and the
* first slot is used as a recorder for the other 15 slots.
*/
#define SOF_IPC4_MAX_DEBUG_SLOTS 15
#define SOF_IPC4_DEBUG_SLOT_SIZE 0x1000
/* debug log slot types */
#define SOF_IPC4_DEBUG_SLOT_UNUSED 0x00000000
#define SOF_IPC4_DEBUG_SLOT_CRITICAL_LOG 0x54524300 /* byte 0: core ID */
#define SOF_IPC4_DEBUG_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */
#define SOF_IPC4_DEBUG_SLOT_GDB_STUB 0x42444700
#define SOF_IPC4_DEBUG_SLOT_TELEMETRY 0x4c455400
#define SOF_IPC4_DEBUG_SLOT_BROKEN 0x44414544
/**
* struct sof_ipc4_notify_module_data - payload for module notification
* @instance_id: instance ID of the originator module of the notification
* @module_id: module ID of the originator of the notification
* @event_id: module specific event id
* @event_data_size: Size of the @event_data (if any) in bytes
* @event_data: Optional notification data, module and notification dependent
*/
struct sof_ipc4_notify_module_data {
uint16_t instance_id;
uint16_t module_id;
uint32_t event_id;
uint32_t event_data_size;
uint8_t event_data[];
} __packed __aligned(4);
/*
* ALSA kcontrol change notification
*
* The event_id of struct sof_ipc4_notify_module_data is divided into two u16:
* upper u16: magic number for ALSA kcontrol types: 0xA15A
* lower u16: param_id of the control, which is the type of the control
* The event_data contains the struct sof_ipc4_control_msg_payload of the control
* which sent the notification.
*/
#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_MASK GENMASK(31, 16)
#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_VAL 0xA15A0000
#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_PARAMID_MASK GENMASK(15, 0)
/*
* Macros for creating struct sof_ipc4_module_init_ext_init payload
* with its associated data. ext_init payload should be the first
* piece of payload following SOF_IPC4_MOD_INIT_INSTANCE msg, and its
* existence is indicated with SOF_IPC4_MOD_EXT_EXTENDED-bit.
*
* The macros below apply to sof_ipc4_module_init_ext_init.word0
*/
#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_SHIFT 0
#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_MASK BIT(0)
#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN(x) ((x) << SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_SHIFT)
#define SOF_IPC4_MOD_INIT_EXT_GNA_USED_SHIFT 1
#define SOF_IPC4_MOD_INIT_EXT_GNA_USED_MASK BIT(1)
#define SOF_IPC4_MOD_INIT_EXT_GNA_USED(x) ((x) << SOF_IPC4_MOD_INIT_EXT_GNA_USED_SHIFT)
#define SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_SHIFT 2
#define SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_MASK BIT(2)
#define SOF_IPC4_MOD_INIT_EXT_DATA_ARRAY(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_SHIFT)
struct sof_ipc4_module_init_ext_init {
u32 word0;
u32 rsvd1;
u32 rsvd2;
} __packed __aligned(4);
/*
* SOF_IPC4_MOD_EXT_EXTENDED payload may be followed by arbitrary
* number of object array objects. SOF_IPC4_MOD_INIT_EXT_DATA_ARRAY
* -bit indicates that an array object follows struct
* sof_ipc4_module_init_ext_init.
*
* The object header's SOF_IPC4_MOD_INIT_EXT_OBJ_LAST-bit in struct
* sof_ipc4_module_init_ext_object indicates if the array is continued
* with another object. The header has also fields to identify the
* object, SOF_IPC4_MOD_INIT_EXT_OBJ_ID, and to indicate the object's
* size in 32-bit words, SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS, not
* including the header itself.
*
* The macros below apply to sof_ipc4_module_init_ext_object.header
*/
#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_SHIFT 0
#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_MASK BIT(0)
#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_SHIFT)
#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_SHIFT 1
#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_MASK GENMASK(15, 1)
#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_ID_SHIFT)
#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_SHIFT 16
#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_MASK GENMASK(31, 16)
#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_SHIFT)
struct sof_ipc4_module_init_ext_object {
u32 header;
u32 data[];
} __packed __aligned(4);
enum sof_ipc4_mod_init_ext_obj_id {
SOF_IPC4_MOD_INIT_DATA_ID_INVALID = 0,
SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA,
SOF_IPC4_MOD_INIT_DATA_ID_MAX = SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA,
};
/* DP module memory configuration data object for ext_init object array */
struct sof_ipc4_mod_init_ext_dp_memory_data {
u32 domain_id; /* userspace domain ID */
u32 stack_bytes; /* stack size in bytes, 0 means default size */
u32 heap_bytes; /* stack size in bytes, 0 means default size */
} __packed __aligned(4);
/** @}*/
#endif
linux-7.2.3/include/sound/sof/pm.h
+56
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_PM_H__
#define __INCLUDE_SOUND_SOF_PM_H__
#include <sound/sof/header.h>
/*
* PM
*/
/* PM context element */
struct sof_ipc_pm_ctx_elem {
struct sof_ipc_hdr hdr;
uint32_t type;
uint32_t size;
uint64_t addr;
} __packed;
/*
* PM context - SOF_IPC_PM_CTX_SAVE, SOF_IPC_PM_CTX_RESTORE,
* SOF_IPC_PM_CTX_SIZE
*/
struct sof_ipc_pm_ctx {
struct sof_ipc_cmd_hdr hdr;
struct sof_ipc_host_buffer buffer;
uint32_t num_elems;
uint32_t size;
/* reserved for future use */
uint32_t reserved[8];
struct sof_ipc_pm_ctx_elem elems[];
} __packed;
/* enable or disable cores - SOF_IPC_PM_CORE_ENABLE */
struct sof_ipc_pm_core_config {
struct sof_ipc_cmd_hdr hdr;
uint32_t enable_mask;
} __packed;
struct sof_ipc_pm_gate {
struct sof_ipc_cmd_hdr hdr;
uint32_t flags; /* platform specific */
/* reserved for future use */
uint32_t reserved[5];
} __packed;
#endif
linux-7.2.3/include/sound/sof/stream.h
+151
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_STREAM_H__
#define __INCLUDE_SOUND_SOF_STREAM_H__
#include <sound/sof/header.h>
/*
* Stream configuration.
*/
#define SOF_IPC_MAX_CHANNELS 8
/* common sample rates for use in masks */
#define SOF_RATE_8000 (1 << 0) /**< 8000Hz */
#define SOF_RATE_11025 (1 << 1) /**< 11025Hz */
#define SOF_RATE_12000 (1 << 2) /**< 12000Hz */
#define SOF_RATE_16000 (1 << 3) /**< 16000Hz */
#define SOF_RATE_22050 (1 << 4) /**< 22050Hz */
#define SOF_RATE_24000 (1 << 5) /**< 24000Hz */
#define SOF_RATE_32000 (1 << 6) /**< 32000Hz */
#define SOF_RATE_44100 (1 << 7) /**< 44100Hz */
#define SOF_RATE_48000 (1 << 8) /**< 48000Hz */
#define SOF_RATE_64000 (1 << 9) /**< 64000Hz */
#define SOF_RATE_88200 (1 << 10) /**< 88200Hz */
#define SOF_RATE_96000 (1 << 11) /**< 96000Hz */
#define SOF_RATE_176400 (1 << 12) /**< 176400Hz */
#define SOF_RATE_192000 (1 << 13) /**< 192000Hz */
/* continuous and non-standard rates for flexibility */
#define SOF_RATE_CONTINUOUS (1 << 30) /**< range */
#define SOF_RATE_KNOT (1 << 31) /**< non-continuous */
/* generic PCM flags for runtime settings */
#define SOF_PCM_FLAG_XRUN_STOP (1 << 0) /**< Stop on any XRUN */
/* stream PCM frame format */
enum sof_ipc_frame {
SOF_IPC_FRAME_S16_LE = 0,
SOF_IPC_FRAME_S24_4LE,
SOF_IPC_FRAME_S32_LE,
SOF_IPC_FRAME_FLOAT,
/* other formats here */
};
/* stream buffer format */
enum sof_ipc_buffer_format {
SOF_IPC_BUFFER_INTERLEAVED,
SOF_IPC_BUFFER_NONINTERLEAVED,
/* other formats here */
};
/* stream direction */
enum sof_ipc_stream_direction {
SOF_IPC_STREAM_PLAYBACK = 0,
SOF_IPC_STREAM_CAPTURE,
};
/* stream ring info */
struct sof_ipc_host_buffer {
struct sof_ipc_hdr hdr;
uint32_t phy_addr;
uint32_t pages;
uint32_t size;
uint32_t reserved[3];
} __packed;
struct sof_ipc_stream_params {
struct sof_ipc_hdr hdr;
struct sof_ipc_host_buffer buffer;
uint32_t direction; /**< enum sof_ipc_stream_direction */
uint32_t frame_fmt; /**< enum sof_ipc_frame */
uint32_t buffer_fmt; /**< enum sof_ipc_buffer_format */
uint32_t rate;
uint16_t stream_tag;
uint16_t channels;
uint16_t sample_valid_bytes;
uint16_t sample_container_bytes;
uint32_t host_period_bytes;
uint16_t no_stream_position; /**< 1 means don't send stream position */
uint8_t cont_update_posn; /**< 1 means continuous update stream position */
uint8_t reserved0;
int16_t ext_data_length; /**< 0, means no extended data */
uint8_t reserved[2];
uint16_t chmap[SOF_IPC_MAX_CHANNELS]; /**< channel map - SOF_CHMAP_ */
uint8_t ext_data[]; /**< extended data */
} __packed;
/* PCM params info - SOF_IPC_STREAM_PCM_PARAMS */
struct sof_ipc_pcm_params {
struct sof_ipc_cmd_hdr hdr;
uint32_t comp_id;
uint32_t flags; /**< generic PCM flags - SOF_PCM_FLAG_ */
uint32_t reserved[2];
struct sof_ipc_stream_params params;
} __packed;
/* PCM params info reply - SOF_IPC_STREAM_PCM_PARAMS_REPLY */
struct sof_ipc_pcm_params_reply {
struct sof_ipc_reply rhdr;
uint32_t comp_id;
uint32_t posn_offset;
} __packed;
/* free stream - SOF_IPC_STREAM_PCM_PARAMS */
struct sof_ipc_stream {
struct sof_ipc_cmd_hdr hdr;
uint32_t comp_id;
} __packed;
/* flags indicating which time stamps are in sync with each other */
#define SOF_TIME_HOST_SYNC (1 << 0)
#define SOF_TIME_DAI_SYNC (1 << 1)
#define SOF_TIME_WALL_SYNC (1 << 2)
#define SOF_TIME_STAMP_SYNC (1 << 3)
/* flags indicating which time stamps are valid */
#define SOF_TIME_HOST_VALID (1 << 8)
#define SOF_TIME_DAI_VALID (1 << 9)
#define SOF_TIME_WALL_VALID (1 << 10)
#define SOF_TIME_STAMP_VALID (1 << 11)
/* flags indicating time stamps are 64bit else 3use low 32bit */
#define SOF_TIME_HOST_64 (1 << 16)
#define SOF_TIME_DAI_64 (1 << 17)
#define SOF_TIME_WALL_64 (1 << 18)
#define SOF_TIME_STAMP_64 (1 << 19)
struct sof_ipc_stream_posn {
struct sof_ipc_reply rhdr;
uint32_t comp_id; /**< host component ID */
uint32_t flags; /**< SOF_TIME_ */
uint32_t wallclock_hz; /**< frequency of wallclock in Hz */
uint32_t timestamp_ns; /**< resolution of timestamp in ns */
uint64_t host_posn; /**< host DMA position in bytes */
uint64_t dai_posn; /**< DAI DMA position in bytes */
uint64_t comp_posn; /**< comp position in bytes */
uint64_t wallclock; /**< audio wall clock */
uint64_t timestamp; /**< system time stamp */
uint32_t xrun_comp_id; /**< comp ID of XRUN component */
int32_t xrun_size; /**< XRUN size in bytes */
} __packed;
#endif
linux-7.2.3/include/sound/sof/topology.h
+310
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
#include <sound/sof/header.h>
/*
* Component
*/
/* types of component */
enum sof_comp_type {
SOF_COMP_NONE = 0,
SOF_COMP_HOST,
SOF_COMP_DAI,
SOF_COMP_SG_HOST, /**< scatter gather variant */
SOF_COMP_SG_DAI, /**< scatter gather variant */
SOF_COMP_VOLUME,
SOF_COMP_MIXER,
SOF_COMP_MUX,
SOF_COMP_SRC,
SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */
SOF_COMP_TONE,
SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */
SOF_COMP_BUFFER,
SOF_COMP_EQ_IIR,
SOF_COMP_EQ_FIR,
SOF_COMP_KEYWORD_DETECT,
SOF_COMP_KPB, /* A key phrase buffer component */
SOF_COMP_SELECTOR, /**< channel selector component */
SOF_COMP_DEMUX,
SOF_COMP_ASRC, /**< Asynchronous sample rate converter */
SOF_COMP_DCBLOCK,
SOF_COMP_SMART_AMP, /**< smart amplifier component */
SOF_COMP_MODULE_ADAPTER, /**< module adapter */
/* keep FILEREAD/FILEWRITE as the last ones */
SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
};
/* XRUN action for component */
#define SOF_XRUN_STOP 1 /**< stop stream */
#define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
#define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
struct sof_ipc_comp {
struct sof_ipc_cmd_hdr hdr;
uint32_t id;
uint32_t type;
uint32_t pipeline_id;
uint32_t core;
/* extended data length, 0 if no extended data */
uint32_t ext_data_length;
} __packed __aligned(4);
/*
* Component Buffers
*/
/*
* SOF memory capabilities, add new ones at the end
*/
#define SOF_MEM_CAPS_RAM BIT(0)
#define SOF_MEM_CAPS_ROM BIT(1)
#define SOF_MEM_CAPS_EXT BIT(2) /**< external */
#define SOF_MEM_CAPS_LP BIT(3) /**< low power */
#define SOF_MEM_CAPS_HP BIT(4) /**< high performance */
#define SOF_MEM_CAPS_DMA BIT(5) /**< DMA'able */
#define SOF_MEM_CAPS_CACHE BIT(6) /**< cacheable */
#define SOF_MEM_CAPS_EXEC BIT(7) /**< executable */
#define SOF_MEM_CAPS_L3 BIT(8) /**< L3 memory */
/*
* overrun will cause ring buffer overwrite, instead of XRUN.
*/
#define SOF_BUF_OVERRUN_PERMITTED BIT(0)
/*
* underrun will cause readback of 0s, instead of XRUN.
*/
#define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
/* the UUID size in bytes, shared between FW and host */
#define SOF_UUID_SIZE 16
/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
struct sof_ipc_buffer {
struct sof_ipc_comp comp;
uint32_t size; /**< buffer size in bytes */
uint32_t caps; /**< SOF_MEM_CAPS_ */
uint32_t flags; /**< SOF_BUF_ flags defined above */
uint32_t reserved; /**< reserved for future use */
} __packed __aligned(4);
/* generic component config data - must always be after struct sof_ipc_comp */
struct sof_ipc_comp_config {
struct sof_ipc_cmd_hdr hdr;
uint32_t periods_sink; /**< 0 means variable */
uint32_t periods_source;/**< 0 means variable */
uint32_t reserved1; /**< reserved */
uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
uint32_t xrun_action;
/* reserved for future use */
uint32_t reserved[2];
} __packed __aligned(4);
/* generic host component */
struct sof_ipc_comp_host {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
uint32_t direction; /**< SOF_IPC_STREAM_ */
uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
uint32_t dmac_config; /**< DMA engine specific */
} __packed __aligned(4);
/* generic DAI component */
struct sof_ipc_comp_dai {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
uint32_t direction; /**< SOF_IPC_STREAM_ */
uint32_t dai_index; /**< index of this type dai */
uint32_t type; /**< DAI type - SOF_DAI_ */
uint32_t reserved; /**< reserved */
} __packed __aligned(4);
/* generic mixer component */
struct sof_ipc_comp_mixer {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
} __packed __aligned(4);
/* volume ramping types */
enum sof_volume_ramp {
SOF_VOLUME_LINEAR = 0,
SOF_VOLUME_LOG,
SOF_VOLUME_LINEAR_ZC,
SOF_VOLUME_LOG_ZC,
SOF_VOLUME_WINDOWS_FADE,
SOF_VOLUME_WINDOWS_NO_FADE,
};
/* generic volume component */
struct sof_ipc_comp_volume {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
uint32_t channels;
uint32_t min_value;
uint32_t max_value;
uint32_t ramp; /**< SOF_VOLUME_ */
uint32_t initial_ramp; /**< ramp space in ms */
} __packed __aligned(4);
/* generic SRC component */
struct sof_ipc_comp_src {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
/* either source or sink rate must be non zero */
uint32_t source_rate; /**< source rate or 0 for variable */
uint32_t sink_rate; /**< sink rate or 0 for variable */
uint32_t rate_mask; /**< SOF_RATE_ supported rates */
} __packed __aligned(4);
/* generic ASRC component */
struct sof_ipc_comp_asrc {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
/* either source or sink rate must be non zero */
uint32_t source_rate; /**< Define fixed source rate or */
/**< use 0 to indicate need to get */
/**< the rate from stream */
uint32_t sink_rate; /**< Define fixed sink rate or */
/**< use 0 to indicate need to get */
/**< the rate from stream */
uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
/**< When 1 the ASRC tracks and */
/**< compensates for drift. */
uint32_t operation_mode; /**< push 0, pull 1, In push mode the */
/**< ASRC consumes a defined number */
/**< of frames at input, with varying */
/**< number of frames at output. */
/**< In pull mode the ASRC outputs */
/**< a defined number of frames while */
/**< number of input frames varies. */
/* reserved for future use */
uint32_t reserved[4];
} __packed __aligned(4);
/* generic MUX component */
struct sof_ipc_comp_mux {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
} __packed __aligned(4);
/* generic tone generator component */
struct sof_ipc_comp_tone {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
int32_t sample_rate;
int32_t frequency;
int32_t amplitude;
int32_t freq_mult;
int32_t ampl_mult;
int32_t length;
int32_t period;
int32_t repeats;
int32_t ramp_step;
} __packed __aligned(4);
/** \brief Types of processing components */
enum sof_ipc_process_type {
SOF_PROCESS_NONE = 0, /**< None */
SOF_PROCESS_EQFIR, /**< Intel FIR */
SOF_PROCESS_EQIIR, /**< Intel IIR */
SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
SOF_PROCESS_MUX,
SOF_PROCESS_DEMUX,
SOF_PROCESS_DCBLOCK,
SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */
};
/* generic "effect", "codec" or proprietary processing component */
struct sof_ipc_comp_process {
struct sof_ipc_comp comp;
struct sof_ipc_comp_config config;
uint32_t size; /**< size of bespoke data section in bytes */
uint32_t type; /**< sof_ipc_process_type */
/* reserved for future use */
uint32_t reserved[7];
unsigned char data[];
} __packed __aligned(4);
/* frees components, buffers and pipelines
* SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
*/
struct sof_ipc_free {
struct sof_ipc_cmd_hdr hdr;
uint32_t id;
} __packed __aligned(4);
struct sof_ipc_comp_reply {
struct sof_ipc_reply rhdr;
uint32_t id;
uint32_t offset;
} __packed __aligned(4);
/*
* Pipeline
*/
/** \brief Types of pipeline scheduling time domains */
enum sof_ipc_pipe_sched_time_domain {
SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
};
/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
struct sof_ipc_pipe_new {
struct sof_ipc_cmd_hdr hdr;
uint32_t comp_id; /**< component id for pipeline */
uint32_t pipeline_id; /**< pipeline id */
uint32_t sched_id; /**< Scheduling component id */
uint32_t core; /**< core we run on */
uint32_t period; /**< execution period in us*/
uint32_t priority; /**< priority level 0 (low) to 10 (max) */
uint32_t period_mips; /**< worst case instruction count per period */
uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
uint32_t time_domain; /**< scheduling time domain */
} __packed __aligned(4);
/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
struct sof_ipc_pipe_ready {
struct sof_ipc_cmd_hdr hdr;
uint32_t comp_id;
} __packed __aligned(4);
struct sof_ipc_pipe_free {
struct sof_ipc_cmd_hdr hdr;
uint32_t comp_id;
} __packed __aligned(4);
/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
struct sof_ipc_pipe_comp_connect {
struct sof_ipc_cmd_hdr hdr;
uint32_t source_id;
uint32_t sink_id;
} __packed __aligned(4);
/* external events */
enum sof_event_types {
SOF_EVENT_NONE = 0,
SOF_KEYWORD_DETECT_DAPM_EVENT,
};
#endif
linux-7.2.3/include/sound/sof/trace.h
+107
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_TRACE_H__
#define __INCLUDE_SOUND_SOF_TRACE_H__
#include <sound/sof/header.h>
#include <sound/sof/stream.h>
/*
* DMA for Trace
*/
#define SOF_TRACE_FILENAME_SIZE 32
/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */
/* Deprecated - use sof_ipc_dma_trace_params_ext */
struct sof_ipc_dma_trace_params {
struct sof_ipc_cmd_hdr hdr;
struct sof_ipc_host_buffer buffer;
uint32_t stream_tag;
} __packed;
/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS_EXT */
struct sof_ipc_dma_trace_params_ext {
struct sof_ipc_cmd_hdr hdr;
struct sof_ipc_host_buffer buffer;
uint32_t stream_tag;
uint64_t timestamp_ns; /* in nanosecond */
uint32_t reserved[8];
} __packed;
/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */
struct sof_ipc_dma_trace_posn {
struct sof_ipc_reply rhdr;
uint32_t host_offset; /* Offset of DMA host buffer */
uint32_t overflow; /* overflow bytes if any */
uint32_t messages; /* total trace messages */
} __packed;
/* Values used in sof_ipc_trace_filter_elem: */
/* bits 6..0 */
#define SOF_IPC_TRACE_FILTER_ELEM_SET_LEVEL 0x01 /**< trace level for selected components */
#define SOF_IPC_TRACE_FILTER_ELEM_BY_UUID 0x02 /**< filter by uuid key */
#define SOF_IPC_TRACE_FILTER_ELEM_BY_PIPE 0x03 /**< filter by pipeline */
#define SOF_IPC_TRACE_FILTER_ELEM_BY_COMP 0x04 /**< filter by component id */
/* bit 7 */
#define SOF_IPC_TRACE_FILTER_ELEM_FIN 0x80 /**< mark last filter in set */
/* bits 31..8: Unused */
/** part of sof_ipc_trace_filter, ABI3.17 */
struct sof_ipc_trace_filter_elem {
uint32_t key; /**< SOF_IPC_TRACE_FILTER_ELEM_ {LEVEL, UUID, COMP, PIPE} */
uint32_t value; /**< element value */
} __packed;
/** Runtime tracing filtration data - SOF_IPC_TRACE_FILTER_UPDATE, ABI3.17 */
struct sof_ipc_trace_filter {
struct sof_ipc_cmd_hdr hdr; /**< IPC command header */
uint32_t elem_cnt; /**< number of entries in elems[] array */
uint32_t reserved[8]; /**< reserved for future usage */
/** variable size array with new filtering settings */
struct sof_ipc_trace_filter_elem elems[];
} __packed;
/*
* Commom debug
*/
/*
* SOF panic codes
*/
#define SOF_IPC_PANIC_MAGIC 0x0dead000
#define SOF_IPC_PANIC_MAGIC_MASK 0x0ffff000
#define SOF_IPC_PANIC_CODE_MASK 0x00000fff
#define SOF_IPC_PANIC_MEM (SOF_IPC_PANIC_MAGIC | 0x0)
#define SOF_IPC_PANIC_WORK (SOF_IPC_PANIC_MAGIC | 0x1)
#define SOF_IPC_PANIC_IPC (SOF_IPC_PANIC_MAGIC | 0x2)
#define SOF_IPC_PANIC_ARCH (SOF_IPC_PANIC_MAGIC | 0x3)
#define SOF_IPC_PANIC_PLATFORM (SOF_IPC_PANIC_MAGIC | 0x4)
#define SOF_IPC_PANIC_TASK (SOF_IPC_PANIC_MAGIC | 0x5)
#define SOF_IPC_PANIC_EXCEPTION (SOF_IPC_PANIC_MAGIC | 0x6)
#define SOF_IPC_PANIC_DEADLOCK (SOF_IPC_PANIC_MAGIC | 0x7)
#define SOF_IPC_PANIC_STACK (SOF_IPC_PANIC_MAGIC | 0x8)
#define SOF_IPC_PANIC_IDLE (SOF_IPC_PANIC_MAGIC | 0x9)
#define SOF_IPC_PANIC_WFI (SOF_IPC_PANIC_MAGIC | 0xa)
#define SOF_IPC_PANIC_ASSERT (SOF_IPC_PANIC_MAGIC | 0xb)
/* panic info include filename and line number
* filename array will not include null terminator if fully filled
*/
struct sof_ipc_panic_info {
struct sof_ipc_hdr hdr;
uint32_t code; /* SOF_IPC_PANIC_ */
uint8_t filename[SOF_TRACE_FILENAME_SIZE];
uint32_t linenum;
} __packed;
#endif
linux-7.2.3/include/sound/sof/xtensa.h
+49
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation
*/
#ifndef __INCLUDE_SOUND_SOF_XTENSA_H__
#define __INCLUDE_SOUND_SOF_XTENSA_H__
#include <sound/sof/header.h>
/*
* Architecture specific debug
*/
/* Xtensa Firmware Oops data */
struct sof_ipc_dsp_oops_xtensa {
struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
uint32_t exccause;
uint32_t excvaddr;
uint32_t ps;
uint32_t epc1;
uint32_t epc2;
uint32_t epc3;
uint32_t epc4;
uint32_t epc5;
uint32_t epc6;
uint32_t epc7;
uint32_t eps2;
uint32_t eps3;
uint32_t eps4;
uint32_t eps5;
uint32_t eps6;
uint32_t eps7;
uint32_t depc;
uint32_t intenable;
uint32_t interrupt;
uint32_t sar;
uint32_t debugcause;
uint32_t windowbase;
uint32_t windowstart;
uint32_t excsave1;
uint32_t ar[];
} __packed;
#endif