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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
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linux-7.2.3/include/uapi/drm/amdgpu_drm.h
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linux-7.2.3/include/uapi/drm/amdxdna_accel.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
*/
#ifndef _UAPI_AMDXDNA_ACCEL_H_
#define _UAPI_AMDXDNA_ACCEL_H_
#include <linux/stddef.h>
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define AMDXDNA_INVALID_CMD_HANDLE (~0UL)
#define AMDXDNA_INVALID_ADDR (~0UL)
#define AMDXDNA_INVALID_CTX_HANDLE 0
#define AMDXDNA_INVALID_BO_HANDLE 0
#define AMDXDNA_INVALID_FENCE_HANDLE 0
#define AMDXDNA_INVALID_DOORBELL_OFFSET (~0U)
/*
* Define hardware context priority
*/
#define AMDXDNA_QOS_REALTIME_PRIORITY 0x100
#define AMDXDNA_QOS_HIGH_PRIORITY 0x180
#define AMDXDNA_QOS_NORMAL_PRIORITY 0x200
#define AMDXDNA_QOS_LOW_PRIORITY 0x280
enum amdxdna_device_type {
AMDXDNA_DEV_TYPE_UNKNOWN = -1,
AMDXDNA_DEV_TYPE_KMQ = 0,
AMDXDNA_DEV_TYPE_UMQ = 1,
AMDXDNA_DEV_TYPE_PF = 2,
};
enum amdxdna_drm_ioctl_id {
DRM_AMDXDNA_CREATE_HWCTX,
DRM_AMDXDNA_DESTROY_HWCTX,
DRM_AMDXDNA_CONFIG_HWCTX,
DRM_AMDXDNA_CREATE_BO,
DRM_AMDXDNA_GET_BO_INFO,
DRM_AMDXDNA_SYNC_BO,
DRM_AMDXDNA_EXEC_CMD,
DRM_AMDXDNA_GET_INFO,
DRM_AMDXDNA_SET_STATE,
DRM_AMDXDNA_WAIT_CMD,
DRM_AMDXDNA_GET_ARRAY,
};
/**
* struct qos_info - QoS information for driver.
* @gops: Giga operations per second.
* @fps: Frames per second.
* @dma_bandwidth: DMA bandwidtha.
* @latency: Frame response latency.
* @frame_exec_time: Frame execution time.
* @priority: Request priority.
*
* User program can provide QoS hints to driver.
*/
struct amdxdna_qos_info {
__u32 gops;
__u32 fps;
__u32 dma_bandwidth;
__u32 latency;
__u32 frame_exec_time;
__u32 priority;
};
/**
* struct amdxdna_drm_create_hwctx - Create hardware context.
* @ext: MBZ.
* @ext_flags: MBZ.
* @qos_p: Address of QoS info.
* @umq_bo: BO handle for user mode queue(UMQ).
* @log_buf_bo: BO handle for log buffer.
* @max_opc: Maximum operations per cycle.
* @num_tiles: Number of AIE tiles.
* @mem_size: Size of AIE tile memory.
* @umq_doorbell: Returned offset of doorbell associated with UMQ.
* @handle: Returned hardware context handle.
* @syncobj_handle: Returned syncobj handle for command completion.
*/
struct amdxdna_drm_create_hwctx {
__u64 ext;
__u64 ext_flags;
__u64 qos_p;
__u32 umq_bo;
__u32 log_buf_bo;
__u32 max_opc;
__u32 num_tiles;
__u32 mem_size;
__u32 umq_doorbell;
__u32 handle;
__u32 syncobj_handle;
};
/**
* struct amdxdna_drm_destroy_hwctx - Destroy hardware context.
* @handle: Hardware context handle.
* @pad: MBZ.
*/
struct amdxdna_drm_destroy_hwctx {
__u32 handle;
__u32 pad;
};
/**
* struct amdxdna_cu_config - configuration for one CU
* @cu_bo: CU configuration buffer bo handle.
* @cu_func: Function of a CU.
* @pad: MBZ.
*/
struct amdxdna_cu_config {
__u32 cu_bo;
__u8 cu_func;
__u8 pad[3];
};
/**
* struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context
* @num_cus: Number of CUs to configure.
* @pad: MBZ.
* @cu_configs: Array of CU configurations of struct amdxdna_cu_config.
*/
struct amdxdna_hwctx_param_config_cu {
__u16 num_cus;
__u16 pad[3];
struct amdxdna_cu_config cu_configs[] __counted_by(num_cus);
};
enum amdxdna_drm_config_hwctx_param {
DRM_AMDXDNA_HWCTX_CONFIG_CU,
DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF,
DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF,
};
/**
* struct amdxdna_drm_config_hwctx - Configure hardware context.
* @handle: hardware context handle.
* @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the
* structure passed in via param_val.
* @param_val: A structure specified by the param_type struct member.
* @param_val_size: Size of the parameter buffer pointed to by the param_val.
* If param_val is not a pointer, driver can ignore this.
* @pad: MBZ.
*
* Note: if the param_val is a pointer pointing to a buffer, the maximum size
* of the buffer is 4KiB(PAGE_SIZE).
*/
struct amdxdna_drm_config_hwctx {
__u32 handle;
__u32 param_type;
__u64 param_val;
__u32 param_val_size;
__u32 pad;
};
enum amdxdna_bo_type {
AMDXDNA_BO_INVALID = 0,
AMDXDNA_BO_SHMEM = 1, /* Be compatible with legacy application code. */
AMDXDNA_BO_SHARE = 1,
AMDXDNA_BO_DEV_HEAP = 2,
AMDXDNA_BO_DEV = 3,
AMDXDNA_BO_CMD = 4,
};
/**
* struct amdxdna_drm_va_entry
* @vaddr: Virtual address.
* @len: Size of entry.
*/
struct amdxdna_drm_va_entry {
__u64 vaddr;
__u64 len;
};
/**
* struct amdxdna_drm_va_tbl
* @dmabuf_fd: The fd of dmabuf.
* @num_entries: Number of va entries.
* @va_entries: Array of va entries.
*
* The input can be either a dmabuf fd or a virtual address entry table.
* When dmabuf_fd is used, num_entries must be zero.
*/
struct amdxdna_drm_va_tbl {
__s32 dmabuf_fd;
__u32 num_entries;
struct amdxdna_drm_va_entry va_entries[];
};
/**
* struct amdxdna_drm_create_bo - Create a buffer object.
* @flags: Buffer flags. MBZ.
* @vaddr: User VA of buffer if applied. MBZ.
* @size: Size in bytes.
* @type: Buffer type.
* @handle: Returned DRM buffer object handle.
*/
struct amdxdna_drm_create_bo {
__u64 flags;
__u64 vaddr;
__u64 size;
__u32 type;
__u32 handle;
};
/**
* struct amdxdna_drm_get_bo_info - Get buffer object information.
* @ext: MBZ.
* @ext_flags: MBZ.
* @handle: DRM buffer object handle.
* @pad: MBZ.
* @map_offset: Returned DRM fake offset for mmap().
* @vaddr: Returned user VA of buffer. 0 in case user needs mmap().
* @xdna_addr: Returned XDNA device virtual address.
*/
struct amdxdna_drm_get_bo_info {
__u64 ext;
__u64 ext_flags;
__u32 handle;
__u32 pad;
__u64 map_offset;
__u64 vaddr;
__u64 xdna_addr;
};
/**
* struct amdxdna_drm_sync_bo - Sync buffer object.
* @handle: Buffer object handle.
* @direction: Direction of sync, can be from device or to device.
* @offset: Offset in the buffer to sync.
* @size: Size in bytes.
*/
struct amdxdna_drm_sync_bo {
__u32 handle;
#define SYNC_DIRECT_TO_DEVICE 0U
#define SYNC_DIRECT_FROM_DEVICE 1U
__u32 direction;
__u64 offset;
__u64 size;
};
enum amdxdna_cmd_type {
AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0,
AMDXDNA_CMD_SUBMIT_DEPENDENCY,
AMDXDNA_CMD_SUBMIT_SIGNAL,
};
/**
* struct amdxdna_drm_exec_cmd - Execute command.
* @ext: MBZ.
* @ext_flags: MBZ.
* @hwctx: Hardware context handle.
* @type: One of command type in enum amdxdna_cmd_type.
* @cmd_handles: Array of command handles or the command handle itself
* in case of just one.
* @args: Array of arguments for all command handles.
* @cmd_count: Number of command handles in the cmd_handles array.
* @arg_count: Number of arguments in the args array.
* @seq: Returned sequence number for this command.
*/
struct amdxdna_drm_exec_cmd {
__u64 ext;
__u64 ext_flags;
__u32 hwctx;
__u32 type;
__u64 cmd_handles;
__u64 args;
__u32 cmd_count;
__u32 arg_count;
__u64 seq;
};
/**
* struct amdxdna_drm_wait_cmd - Wait execution command.
*
* @hwctx: Context handle.
* @timeout: timeout in ms, 0 implies infinite wait.
* @seq: sequence number of the command returned by execute command.
*
* Wait a command specified by seq to be completed.
*/
struct amdxdna_drm_wait_cmd {
__u32 hwctx;
__u32 timeout;
__u64 seq;
};
/**
* struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware
* @buffer: The user space buffer that will return the AIE status.
* @buffer_size: The size of the user space buffer.
* @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer.
*/
struct amdxdna_drm_query_aie_status {
__u64 buffer; /* out */
__u32 buffer_size; /* in */
__u32 cols_filled; /* out */
};
/**
* struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware
* @major: The major version number.
* @minor: The minor version number.
*/
struct amdxdna_drm_query_aie_version {
__u32 major; /* out */
__u32 minor; /* out */
};
/**
* struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim)
* @row_count: The number of rows.
* @row_start: The starting row number.
* @dma_channel_count: The number of dma channels.
* @lock_count: The number of locks.
* @event_reg_count: The number of events.
* @pad: Structure padding.
*/
struct amdxdna_drm_query_aie_tile_metadata {
__u16 row_count;
__u16 row_start;
__u16 dma_channel_count;
__u16 lock_count;
__u16 event_reg_count;
__u16 pad[3];
};
/**
* struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware
* @col_size: The size of a column in bytes.
* @cols: The total number of columns.
* @rows: The total number of rows.
* @version: The version of the AIE hardware.
* @core: The metadata for all core tiles.
* @mem: The metadata for all mem tiles.
* @shim: The metadata for all shim tiles.
*/
struct amdxdna_drm_query_aie_metadata {
__u32 col_size;
__u16 cols;
__u16 rows;
struct amdxdna_drm_query_aie_version version;
struct amdxdna_drm_query_aie_tile_metadata core;
struct amdxdna_drm_query_aie_tile_metadata mem;
struct amdxdna_drm_query_aie_tile_metadata shim;
};
/**
* struct amdxdna_drm_query_clock - Metadata for a clock
* @name: The clock name.
* @freq_mhz: The clock frequency.
* @pad: Structure padding.
*/
struct amdxdna_drm_query_clock {
__u8 name[16];
__u32 freq_mhz;
__u32 pad;
};
/**
* struct amdxdna_drm_query_clock_metadata - Query metadata for clocks
* @mp_npu_clock: The metadata for MP-NPU clock.
* @h_clock: The metadata for H clock.
*/
struct amdxdna_drm_query_clock_metadata {
struct amdxdna_drm_query_clock mp_npu_clock;
struct amdxdna_drm_query_clock h_clock;
};
enum amdxdna_sensor_type {
AMDXDNA_SENSOR_TYPE_POWER,
AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION
};
/**
* struct amdxdna_drm_query_sensor - The data for single sensor.
* @label: The name for a sensor.
* @input: The current value of the sensor.
* @max: The maximum value possible for the sensor.
* @average: The average value of the sensor.
* @highest: The highest recorded sensor value for this driver load for the sensor.
* @status: The sensor status.
* @units: The sensor units.
* @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value).
* @type: The sensor type from enum amdxdna_sensor_type.
* @pad: Structure padding.
*/
struct amdxdna_drm_query_sensor {
__u8 label[64];
__u32 input;
__u32 max;
__u32 average;
__u32 highest;
__u8 status[64];
__u8 units[16];
__s8 unitm;
__u8 type;
__u8 pad[6];
};
/**
* struct amdxdna_drm_query_hwctx - The data for single context.
* @context_id: The ID for this context.
* @start_col: The starting column for the partition assigned to this context.
* @num_col: The number of columns in the partition assigned to this context.
* @pad: Structure padding.
* @pid: The Process ID of the process that created this context.
* @command_submissions: The number of commands submitted to this context.
* @command_completions: The number of commands completed by this context.
* @migrations: The number of times this context has been moved to a different partition.
* @preemptions: The number of times this context has been preempted by another context in the
* same partition.
* @errors: The errors for this context.
*/
struct amdxdna_drm_query_hwctx {
__u32 context_id;
__u32 start_col;
__u32 num_col;
__u32 pad;
__s64 pid;
__u64 command_submissions;
__u64 command_completions;
__u64 migrations;
__u64 preemptions;
__u64 errors;
};
enum amdxdna_power_mode_type {
POWER_MODE_DEFAULT, /* Fallback to calculated DPM */
POWER_MODE_LOW, /* Set frequency to lowest DPM */
POWER_MODE_MEDIUM, /* Set frequency to medium DPM */
POWER_MODE_HIGH, /* Set frequency to highest DPM */
POWER_MODE_TURBO, /* Maximum power */
};
/**
* struct amdxdna_drm_get_power_mode - Get the configured power mode
* @power_mode: The mode type from enum amdxdna_power_mode_type
* @pad: Structure padding.
*/
struct amdxdna_drm_get_power_mode {
__u8 power_mode;
__u8 pad[7];
};
/**
* struct amdxdna_drm_query_firmware_version - Query the firmware version
* @major: The major version number
* @minor: The minor version number
* @patch: The patch level version number
* @build: The build ID
*/
struct amdxdna_drm_query_firmware_version {
__u32 major; /* out */
__u32 minor; /* out */
__u32 patch; /* out */
__u32 build; /* out */
};
enum amdxdna_drm_get_param {
DRM_AMDXDNA_QUERY_AIE_STATUS,
DRM_AMDXDNA_QUERY_AIE_METADATA,
DRM_AMDXDNA_QUERY_AIE_VERSION,
DRM_AMDXDNA_QUERY_CLOCK_METADATA,
DRM_AMDXDNA_QUERY_SENSORS,
DRM_AMDXDNA_QUERY_HW_CONTEXTS,
DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8,
DRM_AMDXDNA_GET_POWER_MODE,
DRM_AMDXDNA_QUERY_TELEMETRY,
DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE,
DRM_AMDXDNA_QUERY_RESOURCE_INFO,
DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE,
};
/**
* struct amdxdna_drm_get_resource_info - Get resource information
*/
struct amdxdna_drm_get_resource_info {
/** @npu_clk_max: max H-Clocks */
__u64 npu_clk_max;
/** @npu_tops_max: max TOPs */
__u64 npu_tops_max;
/** @npu_task_max: max number of tasks */
__u64 npu_task_max;
/** @npu_tops_curr: current TOPs */
__u64 npu_tops_curr;
/** @npu_task_curr: current number of tasks */
__u64 npu_task_curr;
};
/**
* struct amdxdna_drm_attribute_state - State of an attribute
*/
struct amdxdna_drm_attribute_state {
/** @state: enabled or disabled */
__u8 state;
/** @pad: MBZ */
__u8 pad[7];
};
/**
* struct amdxdna_drm_query_telemetry_header - Telemetry data header
*/
struct amdxdna_drm_query_telemetry_header {
/** @major: Firmware telemetry interface major version number */
__u32 major;
/** @minor: Firmware telemetry interface minor version number */
__u32 minor;
/** @type: Telemetry query type */
__u32 type;
/** @map_num_elements: Total number of elements in the map table */
__u32 map_num_elements;
/** @map: Element map */
__u32 map[];
};
/**
* struct amdxdna_drm_get_info - Get some information from the AIE hardware.
* @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer.
* @buffer_size: Size of the input buffer. Size needed/written by the kernel.
* @buffer: A structure specified by the param struct member.
*/
struct amdxdna_drm_get_info {
__u32 param; /* in */
__u32 buffer_size; /* in/out */
__u64 buffer; /* in/out */
};
#define AMDXDNA_HWCTX_STATE_IDLE 0
#define AMDXDNA_HWCTX_STATE_ACTIVE 1
/**
* struct amdxdna_drm_hwctx_entry - The hardware context array entry
*/
struct amdxdna_drm_hwctx_entry {
/** @context_id: Context ID. */
__u32 context_id;
/** @start_col: Start AIE array column assigned to context. */
__u32 start_col;
/** @num_col: Number of AIE array columns assigned to context. */
__u32 num_col;
/** @hwctx_id: The real hardware context id. */
__u32 hwctx_id;
/** @pid: ID of process which created this context. */
__s64 pid;
/** @command_submissions: Number of commands submitted. */
__u64 command_submissions;
/** @command_completions: Number of commands completed. */
__u64 command_completions;
/** @migrations: Number of times been migrated. */
__u64 migrations;
/** @preemptions: Number of times been preempted. */
__u64 preemptions;
/** @errors: Number of errors happened. */
__u64 errors;
/** @priority: Context priority. */
__u64 priority;
/** @heap_usage: Usage of device heap buffer. */
__u64 heap_usage;
/** @suspensions: Number of times been suspended. */
__u64 suspensions;
/**
* @state: Context state.
* %AMDXDNA_HWCTX_STATE_IDLE
* %AMDXDNA_HWCTX_STATE_ACTIVE
*/
__u32 state;
/** @pasid: PASID been bound. */
__u32 pasid;
/** @gops: Giga operations per second. */
__u32 gops;
/** @fps: Frames per second. */
__u32 fps;
/** @dma_bandwidth: DMA bandwidth. */
__u32 dma_bandwidth;
/** @latency: Frame response latency. */
__u32 latency;
/** @frame_exec_time: Frame execution time. */
__u32 frame_exec_time;
/** @txn_op_idx: Index of last control code executed. */
__u32 txn_op_idx;
/** @ctx_pc: Program counter. */
__u32 ctx_pc;
/** @fatal_error_type: Fatal error type if context crashes. */
__u32 fatal_error_type;
/** @fatal_error_exception_type: Firmware exception type. */
__u32 fatal_error_exception_type;
/** @fatal_error_exception_pc: Firmware exception program counter. */
__u32 fatal_error_exception_pc;
/** @fatal_error_app_module: Exception module name. */
__u32 fatal_error_app_module;
/** @pad: Structure pad. */
__u32 pad;
};
/**
* struct amdxdna_async_error - XDNA async error structure
*/
struct amdxdna_async_error {
/** @err_code: Error code. */
__u64 err_code;
/** @ts_us: Timestamp. */
__u64 ts_us;
/** @ex_err_code: Extra error code */
__u64 ex_err_code;
};
/**
* struct amdxdna_drm_bo_usage - all types of BO usage
* BOs managed by XRT/SHIM/driver is counted as internal.
* Others are counted as external which are managed by applications.
*
* Among all types of BOs:
* AMDXDNA_BO_DEV_HEAP - is counted for internal.
* AMDXDNA_BO_SHARE - is counted for external.
* AMDXDNA_BO_CMD - is counted for internal.
* AMDXDNA_BO_DEV - is counted by heap_usage only, not internal
* or external. It does not add to the total memory
* footprint since its mem comes from heap which is
* already counted as internal.
*/
struct amdxdna_drm_bo_usage {
/** @pid: The ID of the process to query from. */
__s64 pid;
/** @total_usage: Total BO size used by process. */
__u64 total_usage;
/** @internal_usage: Total internal BO size used by process. */
__u64 internal_usage;
/** @heap_usage: Total device BO size used by process. */
__u64 heap_usage;
};
/*
* Supported params in struct amdxdna_drm_get_array
*/
#define DRM_AMDXDNA_HW_CONTEXT_ALL 0
#define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2
#define DRM_AMDXDNA_BO_USAGE 6
/**
* struct amdxdna_drm_get_array - Get information array.
*/
struct amdxdna_drm_get_array {
/**
* @param:
*
* Supported params:
*
* %DRM_AMDXDNA_HW_CONTEXT_ALL:
* Returns all created hardware contexts.
*
* %DRM_AMDXDNA_HW_LAST_ASYNC_ERR:
* Returns last async error.
*
* %DRM_AMDXDNA_BO_USAGE:
* Returns usage of heap/internal/external BOs.
*/
__u32 param;
/**
* @element_size:
*
* Specifies maximum element size and returns the actual element size.
*/
__u32 element_size;
/**
* @num_element:
*
* Specifies maximum number of elements and returns the actual number
* of elements.
*/
__u32 num_element; /* in/out */
/** @pad: MBZ */
__u32 pad;
/**
* @buffer:
*
* Specifies the match conditions and returns the matched information
* array.
*/
__u64 buffer;
};
enum amdxdna_drm_set_param {
DRM_AMDXDNA_SET_POWER_MODE,
DRM_AMDXDNA_WRITE_AIE_MEM,
DRM_AMDXDNA_WRITE_AIE_REG,
DRM_AMDXDNA_SET_FORCE_PREEMPT,
DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT,
};
/**
* struct amdxdna_drm_set_state - Set the state of the AIE hardware.
* @param: Value in enum amdxdna_drm_set_param.
* @buffer_size: Size of the input param.
* @buffer: Pointer to the input param.
*/
struct amdxdna_drm_set_state {
__u32 param; /* in */
__u32 buffer_size; /* in */
__u64 buffer; /* in */
};
/**
* struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware
* @power_mode: The sensor type from enum amdxdna_power_mode_type
* @pad: MBZ.
*/
struct amdxdna_drm_set_power_mode {
__u8 power_mode;
__u8 pad[7];
};
#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
struct amdxdna_drm_create_hwctx)
#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
struct amdxdna_drm_destroy_hwctx)
#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \
struct amdxdna_drm_config_hwctx)
#define DRM_IOCTL_AMDXDNA_CREATE_BO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \
struct amdxdna_drm_create_bo)
#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
struct amdxdna_drm_get_bo_info)
#define DRM_IOCTL_AMDXDNA_SYNC_BO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
struct amdxdna_drm_sync_bo)
#define DRM_IOCTL_AMDXDNA_EXEC_CMD \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \
struct amdxdna_drm_exec_cmd)
#define DRM_IOCTL_AMDXDNA_GET_INFO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \
struct amdxdna_drm_get_info)
#define DRM_IOCTL_AMDXDNA_SET_STATE \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \
struct amdxdna_drm_set_state)
#define DRM_IOCTL_AMDXDNA_GET_ARRAY \
DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \
struct amdxdna_drm_get_array)
#define DRM_IOCTL_AMDXDNA_WAIT_CMD \
DRM_IOW(DRM_COMMAND_BASE + DRM_AMDXDNA_WAIT_CMD, \
struct amdxdna_drm_wait_cmd)
#if defined(__cplusplus)
} /* extern c end */
#endif
#endif /* _UAPI_AMDXDNA_ACCEL_H_ */
linux-7.2.3/include/uapi/drm/armada_drm.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2012 Russell King
* With inspiration from the i915 driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef DRM_ARMADA_IOCTL_H
#define DRM_ARMADA_IOCTL_H
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_ARMADA_GEM_CREATE 0x00
#define DRM_ARMADA_GEM_MMAP 0x02
#define DRM_ARMADA_GEM_PWRITE 0x03
#define ARMADA_IOCTL(dir, name, str) \
DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str)
struct drm_armada_gem_create {
__u32 handle;
__u32 size;
};
#define DRM_IOCTL_ARMADA_GEM_CREATE \
ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
struct drm_armada_gem_mmap {
__u32 handle;
__u32 pad;
__u64 offset;
__u64 size;
__u64 addr;
};
#define DRM_IOCTL_ARMADA_GEM_MMAP \
ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
struct drm_armada_gem_pwrite {
__u64 ptr;
__u32 handle;
__u32 offset;
__u32 size;
};
#define DRM_IOCTL_ARMADA_GEM_PWRITE \
ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
#if defined(__cplusplus)
}
#endif
#endif
linux-7.2.3/include/uapi/drm/asahi_drm.h
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linux-7.2.3/include/uapi/drm/drm.h
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linux-7.2.3/include/uapi/drm/drm_fourcc.h
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linux-7.2.3/include/uapi/drm/drm_mode.h
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linux-7.2.3/include/uapi/drm/drm_ras.h
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/* Do not edit directly, auto-generated from: */
/* Documentation/netlink/specs/drm_ras.yaml */
/* YNL-GEN uapi header */
/* To regenerate run: tools/net/ynl/ynl-regen.sh */
#ifndef _UAPI_LINUX_DRM_RAS_H
#define _UAPI_LINUX_DRM_RAS_H
#define DRM_RAS_FAMILY_NAME "drm-ras"
#define DRM_RAS_FAMILY_VERSION 1
/*
* Type of the node. Currently, only error-counter nodes are supported, which
* expose reliability counters for a hardware/software component.
*/
enum drm_ras_node_type {
DRM_RAS_NODE_TYPE_ERROR_COUNTER = 1,
};
enum {
DRM_RAS_A_NODE_ATTRS_NODE_ID = 1,
DRM_RAS_A_NODE_ATTRS_DEVICE_NAME,
DRM_RAS_A_NODE_ATTRS_NODE_NAME,
DRM_RAS_A_NODE_ATTRS_NODE_TYPE,
__DRM_RAS_A_NODE_ATTRS_MAX,
DRM_RAS_A_NODE_ATTRS_MAX = (__DRM_RAS_A_NODE_ATTRS_MAX - 1)
};
enum {
DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID = 1,
DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID,
DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_NAME,
DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_VALUE,
__DRM_RAS_A_ERROR_COUNTER_ATTRS_MAX,
DRM_RAS_A_ERROR_COUNTER_ATTRS_MAX = (__DRM_RAS_A_ERROR_COUNTER_ATTRS_MAX - 1)
};
enum {
DRM_RAS_CMD_LIST_NODES = 1,
DRM_RAS_CMD_GET_ERROR_COUNTER,
DRM_RAS_CMD_CLEAR_ERROR_COUNTER,
__DRM_RAS_CMD_MAX,
DRM_RAS_CMD_MAX = (__DRM_RAS_CMD_MAX - 1)
};
#endif /* _UAPI_LINUX_DRM_RAS_H */
linux-7.2.3/include/uapi/drm/drm_sarea.h
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/* SPDX-License-Identifier: MIT */
/**
* \file drm_sarea.h
* \brief SAREA definitions
*
* \author Michel Dänzer <michel@daenzer.net>
*/
/*
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*/
#ifndef _DRM_SAREA_H_
#define _DRM_SAREA_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* SAREA area needs to be at least a page */
#if defined(__alpha__)
#define SAREA_MAX 0x2000U
#elif defined(__mips__)
#define SAREA_MAX 0x4000U
#elif defined(__ia64__)
#define SAREA_MAX 0x10000U /* 64kB */
#else
/* Intel 830M driver needs at least 8k SAREA */
#define SAREA_MAX 0x2000U
#endif
/** Maximum number of drawables in the SAREA */
#define SAREA_MAX_DRAWABLES 256
#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
/** SAREA drawable */
struct drm_sarea_drawable {
unsigned int stamp;
unsigned int flags;
};
/** SAREA frame */
struct drm_sarea_frame {
unsigned int x;
unsigned int y;
unsigned int width;
unsigned int height;
unsigned int fullscreen;
};
/** SAREA */
struct drm_sarea {
/** first thing is always the DRM locking structure */
struct drm_hw_lock lock;
/** \todo Use readers/writer lock for drm_sarea::drawable_lock */
struct drm_hw_lock drawable_lock;
struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
struct drm_sarea_frame frame; /**< frame */
drm_context_t dummy_context;
};
#ifndef __KERNEL__
typedef struct drm_sarea_drawable drm_sarea_drawable_t;
typedef struct drm_sarea_frame drm_sarea_frame_t;
typedef struct drm_sarea drm_sarea_t;
#endif
#if defined(__cplusplus)
}
#endif
#endif /* _DRM_SAREA_H_ */
linux-7.2.3/include/uapi/drm/ethosu_accel.h
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/* SPDX-License-Identifier: MIT */
/* Copyright (C) 2025 Arm, Ltd. */
#ifndef _ETHOSU_DRM_H_
#define _ETHOSU_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* DOC: IOCTL IDs
*
* enum drm_ethosu_ioctl_id - IOCTL IDs
*
* Place new ioctls at the end, don't re-order, don't replace or remove entries.
*
* These IDs are not meant to be used directly. Use the DRM_IOCTL_ETHOSU_xxx
* definitions instead.
*/
enum drm_ethosu_ioctl_id {
/** @DRM_ETHOSU_DEV_QUERY: Query device information. */
DRM_ETHOSU_DEV_QUERY = 0,
/** @DRM_ETHOSU_BO_CREATE: Create a buffer object. */
DRM_ETHOSU_BO_CREATE,
/** @DRM_ETHOSU_BO_WAIT: Wait on a buffer object's fence. */
DRM_ETHOSU_BO_WAIT,
/**
* @DRM_ETHOSU_BO_MMAP_OFFSET: Get the file offset to pass to
* mmap to map a GEM object.
*/
DRM_ETHOSU_BO_MMAP_OFFSET,
/**
* @DRM_ETHOSU_CMDSTREAM_BO_CREATE: Create a command stream buffer
* object.
*/
DRM_ETHOSU_CMDSTREAM_BO_CREATE,
/** @DRM_ETHOSU_SUBMIT: Submit a job and BOs to run. */
DRM_ETHOSU_SUBMIT,
};
/**
* DOC: IOCTL arguments
*/
/**
* enum drm_ethosu_dev_query_type - Query type
*
* Place new types at the end, don't re-order, don't remove or replace.
*/
enum drm_ethosu_dev_query_type {
/** @DRM_ETHOSU_DEV_QUERY_NPU_INFO: Query NPU information. */
DRM_ETHOSU_DEV_QUERY_NPU_INFO = 0,
};
/**
* struct drm_ethosu_gpu_info - NPU information
*
* Structure grouping all queryable information relating to the NPU.
*/
struct drm_ethosu_npu_info {
/** @id : NPU ID. */
__u32 id;
#define DRM_ETHOSU_ARCH_MAJOR(x) ((x) >> 28)
#define DRM_ETHOSU_ARCH_MINOR(x) (((x) >> 20) & 0xff)
#define DRM_ETHOSU_ARCH_PATCH(x) (((x) >> 16) & 0xf)
#define DRM_ETHOSU_PRODUCT_MAJOR(x) (((x) >> 12) & 0xf)
#define DRM_ETHOSU_VERSION_MAJOR(x) (((x) >> 8) & 0xf)
#define DRM_ETHOSU_VERSION_MINOR(x) (((x) >> 4) & 0xff)
#define DRM_ETHOSU_VERSION_STATUS(x) ((x) & 0xf)
/** @gpu_rev: GPU revision. */
__u32 config;
__u32 sram_size;
};
/**
* struct drm_ethosu_dev_query - Arguments passed to DRM_ETHOSU_IOCTL_DEV_QUERY
*/
struct drm_ethosu_dev_query {
/** @type: the query type (see drm_ethosu_dev_query_type). */
__u32 type;
/**
* @size: size of the type being queried.
*
* If pointer is NULL, size is updated by the driver to provide the
* output structure size. If pointer is not NULL, the driver will
* only copy min(size, actual_structure_size) bytes to the pointer,
* and update the size accordingly. This allows us to extend query
* types without breaking userspace.
*/
__u32 size;
/**
* @pointer: user pointer to a query type struct.
*
* Pointer can be NULL, in which case, nothing is copied, but the
* actual structure size is returned. If not NULL, it must point to
* a location that's large enough to hold size bytes.
*/
__u64 pointer;
};
/**
* enum drm_ethosu_bo_flags - Buffer object flags, passed at creation time.
*/
enum drm_ethosu_bo_flags {
/**
* @DRM_ETHOSU_BO_NO_MMAP: The buffer object will never be CPU-mapped
* in userspace.
*/
DRM_ETHOSU_BO_NO_MMAP = (1 << 0),
};
/**
* struct drm_ethosu_bo_create - Arguments passed to DRM_IOCTL_ETHOSU_BO_CREATE.
*/
struct drm_ethosu_bo_create {
/**
* @size: Requested size for the object
*
* The (page-aligned) allocated size for the object will be returned.
*/
__u64 size;
/**
* @flags: Flags. Must be a combination of drm_ethosu_bo_flags flags.
*/
__u32 flags;
/**
* @handle: Returned handle for the object.
*
* Object handles are nonzero.
*/
__u32 handle;
};
/**
* struct drm_ethosu_bo_mmap_offset - Arguments passed to DRM_IOCTL_ETHOSU_BO_MMAP_OFFSET.
*/
struct drm_ethosu_bo_mmap_offset {
/** @handle: Handle of the object we want an mmap offset for. */
__u32 handle;
/** @pad: MBZ. */
__u32 pad;
/** @offset: The fake offset to use for subsequent mmap calls. */
__u64 offset;
};
/**
* struct drm_ethosu_wait_bo - ioctl argument for waiting for
* completion of the last DRM_ETHOSU_SUBMIT on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_ethosu_bo_wait {
__u32 handle;
__u32 pad;
__s64 timeout_ns; /* absolute */
};
struct drm_ethosu_cmdstream_bo_create {
/* Size of the data argument. */
__u32 size;
/* Flags, currently must be 0. */
__u32 flags;
/* Pointer to the data. */
__u64 data;
/** Returned GEM handle for the BO. */
__u32 handle;
/* Pad, must be 0. */
__u32 pad;
};
/**
* struct drm_ethosu_job - A job to be run on the NPU
*
* The kernel will schedule the execution of this job taking into account its
* dependencies with other jobs. All tasks in the same job will be executed
* sequentially on the same core, to benefit from memory residency in SRAM.
*/
struct drm_ethosu_job {
/** Input: BO handle for cmdstream. */
__u32 cmd_bo;
/** Input: Amount of SRAM to use. */
__u32 sram_size;
#define ETHOSU_MAX_REGIONS 8
/** Input: Array of BO handles for each region. */
__u32 region_bo_handles[ETHOSU_MAX_REGIONS];
};
/**
* struct drm_ethosu_submit - ioctl argument for submitting commands to the NPU.
*
* The kernel will schedule the execution of these jobs in dependency order.
*/
struct drm_ethosu_submit {
/** Input: Pointer to an array of struct drm_ethosu_job. */
__u64 jobs;
/** Input: Number of jobs passed in. */
__u32 job_count;
/** Reserved, must be zero. */
__u32 pad;
};
/**
* DRM_IOCTL_ETHOSU() - Build a ethosu IOCTL number
* @__access: Access type. Must be R, W or RW.
* @__id: One of the DRM_ETHOSU_xxx id.
* @__type: Suffix of the type being passed to the IOCTL.
*
* Don't use this macro directly, use the DRM_IOCTL_ETHOSU_xxx
* values instead.
*
* Return: An IOCTL number to be passed to ioctl() from userspace.
*/
#define DRM_IOCTL_ETHOSU(__access, __id, __type) \
DRM_IO ## __access(DRM_COMMAND_BASE + DRM_ETHOSU_ ## __id, \
struct drm_ethosu_ ## __type)
enum {
DRM_IOCTL_ETHOSU_DEV_QUERY =
DRM_IOCTL_ETHOSU(WR, DEV_QUERY, dev_query),
DRM_IOCTL_ETHOSU_BO_CREATE =
DRM_IOCTL_ETHOSU(WR, BO_CREATE, bo_create),
DRM_IOCTL_ETHOSU_BO_WAIT =
DRM_IOCTL_ETHOSU(WR, BO_WAIT, bo_wait),
DRM_IOCTL_ETHOSU_BO_MMAP_OFFSET =
DRM_IOCTL_ETHOSU(WR, BO_MMAP_OFFSET, bo_mmap_offset),
DRM_IOCTL_ETHOSU_CMDSTREAM_BO_CREATE =
DRM_IOCTL_ETHOSU(WR, CMDSTREAM_BO_CREATE, cmdstream_bo_create),
DRM_IOCTL_ETHOSU_SUBMIT =
DRM_IOCTL_ETHOSU(WR, SUBMIT, submit),
};
#if defined(__cplusplus)
}
#endif
#endif /* _ETHOSU_DRM_H_ */
linux-7.2.3/include/uapi/drm/etnaviv_drm.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2015 Etnaviv Project
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ETNAVIV_DRM_H__
#define __ETNAVIV_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints:
* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
* user/kernel compatibility
* 2) Keep fields aligned to their size
* 3) Because of how drm_ioctl() works, we can add new fields at
* the end of an ioctl if some care is taken: drm_ioctl() will
* zero out the new fields at the tail of the ioctl, so a zero
* value should have a backwards compatible meaning. And for
* output params, userspace won't see the newly added output
* fields.. so that has to be somehow ok.
*/
/* timeouts are specified in clock-monotonic absolute times (to simplify
* restarting interrupted ioctls). The following struct is logically the
* same as 'struct timespec' but 32/64b ABI safe.
*/
struct drm_etnaviv_timespec {
__s64 tv_sec; /* seconds */
__s64 tv_nsec; /* nanoseconds */
};
#define ETNAVIV_PARAM_GPU_MODEL 0x01
#define ETNAVIV_PARAM_GPU_REVISION 0x02
#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
#define ETNA_MAX_PIPES 4
struct drm_etnaviv_param {
__u32 pipe; /* in */
__u32 param; /* in, ETNAVIV_PARAM_x */
__u64 value; /* out (get_param) or in (set_param) */
};
/*
* GEM buffers:
*/
#define ETNA_BO_CACHE_MASK 0x000f0000
/* cache modes */
#define ETNA_BO_CACHED 0x00010000
#define ETNA_BO_WC 0x00020000
#define ETNA_BO_UNCACHED 0x00040000
/* map flags */
#define ETNA_BO_FORCE_MMU 0x00100000
struct drm_etnaviv_gem_new {
__u64 size; /* in */
__u32 flags; /* in, mask of ETNA_BO_x */
__u32 handle; /* out */
};
struct drm_etnaviv_gem_info {
__u32 handle; /* in */
__u32 pad;
__u64 offset; /* out, offset to pass to mmap() */
};
#define ETNA_PREP_READ 0x01
#define ETNA_PREP_WRITE 0x02
#define ETNA_PREP_NOSYNC 0x04
struct drm_etnaviv_gem_cpu_prep {
__u32 handle; /* in */
__u32 op; /* in, mask of ETNA_PREP_x */
struct drm_etnaviv_timespec timeout; /* in */
};
struct drm_etnaviv_gem_cpu_fini {
__u32 handle; /* in */
__u32 flags; /* in, placeholder for now, no defined values */
};
/*
* Cmdstream Submission:
*/
/* The value written into the cmdstream is logically:
* relocbuf->gpuaddr + reloc_offset
*
* NOTE that reloc's must be sorted by order of increasing submit_offset,
* otherwise EINVAL.
*/
struct drm_etnaviv_gem_submit_reloc {
__u32 submit_offset; /* in, offset from submit_bo */
__u32 reloc_idx; /* in, index of reloc_bo buffer */
__u64 reloc_offset; /* in, offset from start of reloc_bo */
__u32 flags; /* in, placeholder for now, no defined values */
};
/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
* cmdstream buffer(s) themselves or reloc entries) has one (and only
* one) entry in the submit->bos[] table.
*
* As a optimization, the current buffer (gpu virtual address) can be
* passed back through the 'presumed' field. If on a subsequent reloc,
* userspace passes back a 'presumed' address that is still valid,
* then patching the cmdstream for this entry is skipped. This can
* avoid kernel needing to map/access the cmdstream bo in the common
* case.
* If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
* field is interpreted as the fixed location to map the bo into the gpu
* virtual address space. If the kernel is unable to map the buffer at
* this location the submit will fail. This means userspace is responsible
* for the whole gpu virtual address management.
*/
#define ETNA_SUBMIT_BO_READ 0x0001
#define ETNA_SUBMIT_BO_WRITE 0x0002
struct drm_etnaviv_gem_submit_bo {
__u32 flags; /* in, mask of ETNA_SUBMIT_BO_x */
__u32 handle; /* in, GEM handle */
__u64 presumed; /* in/out, presumed buffer address */
};
/* performance monitor request (pmr) */
#define ETNA_PM_PROCESS_PRE 0x0001
#define ETNA_PM_PROCESS_POST 0x0002
struct drm_etnaviv_gem_submit_pmr {
__u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */
__u8 domain; /* in, pm domain */
__u8 pad;
__u16 signal; /* in, pm signal */
__u32 sequence; /* in, sequence number */
__u32 read_offset; /* in, offset from read_bo */
__u32 read_idx; /* in, index of read_bo buffer */
};
/* Each cmdstream submit consists of a table of buffers involved, and
* one or more cmdstream buffers. This allows for conditional execution
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
*/
#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
#define ETNA_SUBMIT_SOFTPIN 0x0008
#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
ETNA_SUBMIT_FENCE_FD_IN | \
ETNA_SUBMIT_FENCE_FD_OUT| \
ETNA_SUBMIT_SOFTPIN)
#define ETNA_PIPE_3D 0x00
#define ETNA_PIPE_2D 0x01
#define ETNA_PIPE_VG 0x02
struct drm_etnaviv_gem_submit {
__u32 fence; /* out */
__u32 pipe; /* in */
__u32 exec_state; /* in, initial execution state (ETNA_PIPE_x) */
__u32 nr_bos; /* in, number of submit_bo's */
__u32 nr_relocs; /* in, number of submit_reloc's */
__u32 stream_size; /* in, cmdstream size */
__u64 bos; /* in, ptr to array of submit_bo's */
__u64 relocs; /* in, ptr to array of submit_reloc's */
__u64 stream; /* in, ptr to cmdstream */
__u32 flags; /* in, mask of ETNA_SUBMIT_x */
__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
__u64 pmrs; /* in, ptr to array of submit_pmr's */
__u32 nr_pmrs; /* in, number of submit_pmr's */
__u32 pad;
};
/* The normal way to synchronize with the GPU is just to CPU_PREP on
* a buffer if you need to access it from the CPU (other cmdstream
* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
* handle the required synchronization under the hood). This ioctl
* mainly just exists as a way to implement the gallium pipe_fence
* APIs without requiring a dummy bo to synchronize on.
*/
#define ETNA_WAIT_NONBLOCK 0x01
struct drm_etnaviv_wait_fence {
__u32 pipe; /* in */
__u32 fence; /* in */
__u32 flags; /* in, mask of ETNA_WAIT_x */
__u32 pad;
struct drm_etnaviv_timespec timeout; /* in */
};
#define ETNA_USERPTR_READ 0x01
#define ETNA_USERPTR_WRITE 0x02
struct drm_etnaviv_gem_userptr {
__u64 user_ptr; /* in, page aligned user pointer */
__u64 user_size; /* in, page aligned user size */
__u32 flags; /* in, flags */
__u32 handle; /* out, non-zero handle */
};
struct drm_etnaviv_gem_wait {
__u32 pipe; /* in */
__u32 handle; /* in, bo to be waited for */
__u32 flags; /* in, mask of ETNA_WAIT_x */
__u32 pad;
struct drm_etnaviv_timespec timeout; /* in */
};
/*
* Performance Monitor (PM):
*/
struct drm_etnaviv_pm_domain {
__u32 pipe; /* in */
__u8 iter; /* in/out, select pm domain at index iter */
__u8 id; /* out, id of domain */
__u16 nr_signals; /* out, how many signals does this domain provide */
char name[64]; /* out, name of domain */
};
struct drm_etnaviv_pm_signal {
__u32 pipe; /* in */
__u8 domain; /* in, pm domain index */
__u8 pad;
__u16 iter; /* in/out, select pm source at index iter */
__u16 id; /* out, id of signal */
char name[64]; /* out, name of domain */
};
#define DRM_ETNAVIV_GET_PARAM 0x00
/* placeholder:
#define DRM_ETNAVIV_SET_PARAM 0x01
*/
#define DRM_ETNAVIV_GEM_NEW 0x02
#define DRM_ETNAVIV_GEM_INFO 0x03
#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
#define DRM_ETNAVIV_GEM_SUBMIT 0x06
#define DRM_ETNAVIV_WAIT_FENCE 0x07
#define DRM_ETNAVIV_GEM_USERPTR 0x08
#define DRM_ETNAVIV_GEM_WAIT 0x09
#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
#if defined(__cplusplus)
}
#endif
#endif /* __ETNAVIV_DRM_H__ */
linux-7.2.3/include/uapi/drm/exynos_drm.h
+424
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@@ -0,0 +1,424 @@
/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
/* exynos_drm.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* Authors:
* Inki Dae <inki.dae@samsung.com>
* Joonyoung Shim <jy0922.shim@samsung.com>
* Seung-Woo Kim <sw0312.kim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _UAPI_EXYNOS_DRM_H_
#define _UAPI_EXYNOS_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* User-desired buffer creation information structure.
*
* @size: user-desired memory allocation size.
* - this size value would be page-aligned internally.
* @flags: user request for setting memory type or cache attributes.
* @handle: returned a handle to created gem object.
* - this handle will be set by gem module of kernel side.
*/
struct drm_exynos_gem_create {
__u64 size;
__u32 flags;
__u32 handle;
};
/**
* A structure for getting a fake-offset that can be used with mmap.
*
* @handle: handle of gem object.
* @reserved: just padding to be 64-bit aligned.
* @offset: a fake-offset of gem object.
*/
struct drm_exynos_gem_map {
__u32 handle;
__u32 reserved;
__u64 offset;
};
/**
* A structure to gem information.
*
* @handle: a handle to gem object created.
* @flags: flag value including memory type and cache attribute and
* this value would be set by driver.
* @size: size to memory region allocated by gem and this size would
* be set by driver.
*/
struct drm_exynos_gem_info {
__u32 handle;
__u32 flags;
__u64 size;
};
/**
* A structure for user connection request of virtual display.
*
* @connection: indicate whether doing connection or not by user.
* @extensions: if this value is 1 then the vidi driver would need additional
* 128bytes edid data.
* @edid: the edid data pointer from user side.
*/
struct drm_exynos_vidi_connection {
__u32 connection;
__u32 extensions;
__u64 edid;
};
/* memory type definitions. */
enum e_drm_exynos_gem_mem_type {
/* Physically Continuous memory and used as default. */
EXYNOS_BO_CONTIG = 0 << 0,
/* Physically Non-Continuous memory. */
EXYNOS_BO_NONCONTIG = 1 << 0,
/* non-cachable mapping and used as default. */
EXYNOS_BO_NONCACHABLE = 0 << 1,
/* cachable mapping. */
EXYNOS_BO_CACHABLE = 1 << 1,
/* write-combine mapping. */
EXYNOS_BO_WC = 1 << 2,
EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
EXYNOS_BO_WC
};
struct drm_exynos_g2d_get_ver {
__u32 major;
__u32 minor;
};
struct drm_exynos_g2d_cmd {
__u32 offset;
__u32 data;
};
enum drm_exynos_g2d_buf_type {
G2D_BUF_USERPTR = 1 << 31,
};
enum drm_exynos_g2d_event_type {
G2D_EVENT_NOT,
G2D_EVENT_NONSTOP,
G2D_EVENT_STOP, /* not yet */
};
struct drm_exynos_g2d_userptr {
unsigned long userptr;
unsigned long size;
};
struct drm_exynos_g2d_set_cmdlist {
__u64 cmd;
__u64 cmd_buf;
__u32 cmd_nr;
__u32 cmd_buf_nr;
/* for g2d event */
__u64 event_type;
__u64 user_data;
};
struct drm_exynos_g2d_exec {
__u64 async;
};
/* Exynos DRM IPP v2 API */
/**
* Enumerate available IPP hardware modules.
*
* @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
* @reserved: padding
* @ipp_id_ptr: pointer to ipp_id array or NULL
*/
struct drm_exynos_ioctl_ipp_get_res {
__u32 count_ipps;
__u32 reserved;
__u64 ipp_id_ptr;
};
enum drm_exynos_ipp_format_type {
DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
};
struct drm_exynos_ipp_format {
__u32 fourcc;
__u32 type;
__u64 modifier;
};
enum drm_exynos_ipp_capability {
DRM_EXYNOS_IPP_CAP_CROP = 0x01,
DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
};
/**
* Get IPP hardware capabilities and supported image formats.
*
* @ipp_id: id of IPP module to query
* @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
* @reserved: padding
* @formats_count: size of formats array (in entries) / number of filled
* formats (set by driver)
* @formats_ptr: pointer to formats array or NULL
*/
struct drm_exynos_ioctl_ipp_get_caps {
__u32 ipp_id;
__u32 capabilities;
__u32 reserved;
__u32 formats_count;
__u64 formats_ptr;
};
enum drm_exynos_ipp_limit_type {
/* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
/* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
/* image buffer area */
DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
/* src/dst rectangle area */
DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
/* src/dst rectangle area when rotation enabled */
DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
};
struct drm_exynos_ipp_limit_val {
__u32 min;
__u32 max;
__u32 align;
__u32 reserved;
};
/**
* IPP module limitation.
*
* @type: limit type (see drm_exynos_ipp_limit_type enum)
* @reserved: padding
* @h: horizontal limits
* @v: vertical limits
*/
struct drm_exynos_ipp_limit {
__u32 type;
__u32 reserved;
struct drm_exynos_ipp_limit_val h;
struct drm_exynos_ipp_limit_val v;
};
/**
* Get IPP limits for given image format.
*
* @ipp_id: id of IPP module to query
* @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
* @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
* @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
* @limits_count: size of limits array (in entries) / number of filled entries
* (set by driver)
* @limits_ptr: pointer to limits array or NULL
*/
struct drm_exynos_ioctl_ipp_get_limits {
__u32 ipp_id;
__u32 fourcc;
__u64 modifier;
__u32 type;
__u32 limits_count;
__u64 limits_ptr;
};
enum drm_exynos_ipp_task_id {
/* buffer described by struct drm_exynos_ipp_task_buffer */
DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
/* rectangle described by struct drm_exynos_ipp_task_rect */
DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
/* transformation described by struct drm_exynos_ipp_task_transform */
DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
/* alpha configuration described by struct drm_exynos_ipp_task_alpha */
DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
/* source image data (for buffer and rectangle chunks) */
DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
/* destination image data (for buffer and rectangle chunks) */
DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
};
/**
* Memory buffer with image data.
*
* @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
* other parameters are same as for AddFB2 generic DRM ioctl
*/
struct drm_exynos_ipp_task_buffer {
__u32 id;
__u32 fourcc;
__u32 width, height;
__u32 gem_id[4];
__u32 offset[4];
__u32 pitch[4];
__u64 modifier;
};
/**
* Rectangle for processing.
*
* @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
* @reserved: padding
* @x,@y: left corner in pixels
* @w,@h: width/height in pixels
*/
struct drm_exynos_ipp_task_rect {
__u32 id;
__u32 reserved;
__u32 x;
__u32 y;
__u32 w;
__u32 h;
};
/**
* Image tranformation description.
*
* @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
* @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
*/
struct drm_exynos_ipp_task_transform {
__u32 id;
__u32 rotation;
};
/**
* Image global alpha configuration for formats without alpha values.
*
* @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
* @value: global alpha value (0-255)
*/
struct drm_exynos_ipp_task_alpha {
__u32 id;
__u32 value;
};
enum drm_exynos_ipp_flag {
/* generate DRM event after processing */
DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
/* dry run, only check task parameters */
DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
/* non-blocking processing */
DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
};
#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
/**
* Perform image processing described by array of drm_exynos_ipp_task_*
* structures (parameters array).
*
* @ipp_id: id of IPP module to run the task
* @flags: bitmask of drm_exynos_ipp_flag values
* @reserved: padding
* @params_size: size of parameters array (in bytes)
* @params_ptr: pointer to parameters array or NULL
* @user_data: (optional) data for drm event
*/
struct drm_exynos_ioctl_ipp_commit {
__u32 ipp_id;
__u32 flags;
__u32 reserved;
__u32 params_size;
__u64 params_ptr;
__u64 user_data;
};
#define DRM_EXYNOS_GEM_CREATE 0x00
#define DRM_EXYNOS_GEM_MAP 0x01
/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
#define DRM_EXYNOS_GEM_GET 0x04
#define DRM_EXYNOS_VIDI_CONNECTION 0x07
/* G2D */
#define DRM_EXYNOS_G2D_GET_VER 0x20
#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
#define DRM_EXYNOS_G2D_EXEC 0x22
/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
/* IPP - Image Post Processing */
#define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
#define DRM_EXYNOS_IPP_GET_CAPS 0x41
#define DRM_EXYNOS_IPP_GET_LIMITS 0x42
#define DRM_EXYNOS_IPP_COMMIT 0x43
#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_GET_RESOURCES, \
struct drm_exynos_ioctl_ipp_get_res)
#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_GET_LIMITS, \
struct drm_exynos_ioctl_ipp_get_limits)
#define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
/* Exynos specific events */
#define DRM_EXYNOS_G2D_EVENT 0x80000000
#define DRM_EXYNOS_IPP_EVENT 0x80000002
struct drm_exynos_g2d_event {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 cmdlist_no;
__u32 reserved;
};
struct drm_exynos_ipp_event {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 ipp_id;
__u32 sequence;
__u64 reserved;
};
#if defined(__cplusplus)
}
#endif
#endif /* _UAPI_EXYNOS_DRM_H_ */
linux-7.2.3/include/uapi/drm/habanalabs_accel.h
+2368
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linux-7.2.3/include/uapi/drm/i915_drm.h
+3916
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linux-7.2.3/include/uapi/drm/ivpu_accel.h
+564
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@@ -0,0 +1,564 @@
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Copyright (C) 2020-2025 Intel Corporation
*/
#ifndef __UAPI_IVPU_DRM_H__
#define __UAPI_IVPU_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_IVPU_GET_PARAM 0x00
#define DRM_IVPU_SET_PARAM 0x01
#define DRM_IVPU_BO_CREATE 0x02
#define DRM_IVPU_BO_INFO 0x03
#define DRM_IVPU_SUBMIT 0x05
#define DRM_IVPU_BO_WAIT 0x06
#define DRM_IVPU_METRIC_STREAMER_START 0x07
#define DRM_IVPU_METRIC_STREAMER_STOP 0x08
#define DRM_IVPU_METRIC_STREAMER_GET_DATA 0x09
#define DRM_IVPU_METRIC_STREAMER_GET_INFO 0x0a
#define DRM_IVPU_CMDQ_CREATE 0x0b
#define DRM_IVPU_CMDQ_DESTROY 0x0c
#define DRM_IVPU_CMDQ_SUBMIT 0x0d
#define DRM_IVPU_BO_CREATE_FROM_USERPTR 0x0e
#define DRM_IOCTL_IVPU_GET_PARAM \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
#define DRM_IOCTL_IVPU_SET_PARAM \
DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
#define DRM_IOCTL_IVPU_BO_CREATE \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
#define DRM_IOCTL_IVPU_BO_INFO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
#define DRM_IOCTL_IVPU_SUBMIT \
DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit)
#define DRM_IOCTL_IVPU_BO_WAIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
#define DRM_IOCTL_IVPU_METRIC_STREAMER_START \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_START, \
struct drm_ivpu_metric_streamer_start)
#define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP \
DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_STOP, \
struct drm_ivpu_metric_streamer_stop)
#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_DATA, \
struct drm_ivpu_metric_streamer_get_data)
#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_INFO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_INFO, \
struct drm_ivpu_metric_streamer_get_data)
#define DRM_IOCTL_IVPU_CMDQ_CREATE \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_CREATE, struct drm_ivpu_cmdq_create)
#define DRM_IOCTL_IVPU_CMDQ_DESTROY \
DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_DESTROY, struct drm_ivpu_cmdq_destroy)
#define DRM_IOCTL_IVPU_CMDQ_SUBMIT \
DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_SUBMIT, struct drm_ivpu_cmdq_submit)
#define DRM_IOCTL_IVPU_BO_CREATE_FROM_USERPTR \
DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE_FROM_USERPTR, \
struct drm_ivpu_bo_create_from_userptr)
/**
* DOC: contexts
*
* VPU contexts have private virtual address space, job queues and priority.
* Each context is identified by an unique ID. Context is created on open().
*/
#define DRM_IVPU_PARAM_DEVICE_ID 0
#define DRM_IVPU_PARAM_DEVICE_REVISION 1
#define DRM_IVPU_PARAM_PLATFORM_TYPE 2
#define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
#define DRM_IVPU_PARAM_NUM_CONTEXTS 4
#define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
#define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6 /* Deprecated */
#define DRM_IVPU_PARAM_CONTEXT_ID 7
#define DRM_IVPU_PARAM_FW_API_VERSION 8
#define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9
#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
#define DRM_IVPU_PARAM_TILE_CONFIG 11
#define DRM_IVPU_PARAM_SKU 12
#define DRM_IVPU_PARAM_CAPABILITIES 13
#define DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE 14
#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
/* Deprecated, use DRM_IVPU_JOB_PRIORITY */
#define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
#define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
#define DRM_IVPU_JOB_PRIORITY_DEFAULT 0
#define DRM_IVPU_JOB_PRIORITY_IDLE 1
#define DRM_IVPU_JOB_PRIORITY_NORMAL 2
#define DRM_IVPU_JOB_PRIORITY_FOCUS 3
#define DRM_IVPU_JOB_PRIORITY_REALTIME 4
/**
* DRM_IVPU_CAP_METRIC_STREAMER
*
* Metric streamer support. Provides sampling of various hardware performance
* metrics like DMA bandwidth and cache miss/hits. Can be used for profiling.
*/
#define DRM_IVPU_CAP_METRIC_STREAMER 1
/**
* DRM_IVPU_CAP_DMA_MEMORY_RANGE
*
* Driver has capability to allocate separate memory range
* accessible by hardware DMA.
*/
#define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2
/**
* DRM_IVPU_CAP_MANAGE_CMDQ
*
* Driver supports explicit command queue operations like command queue create,
* command queue destroy and submit job on specific command queue.
*/
#define DRM_IVPU_CAP_MANAGE_CMDQ 3
/**
* DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR
*
* Driver supports creating buffer objects from user space memory pointers.
* This allows creating GEM buffers from existing user memory regions.
*/
#define DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR 4
/**
* struct drm_ivpu_param - Get/Set VPU parameters
*/
struct drm_ivpu_param {
/**
* @param:
*
* Supported params:
*
* %DRM_IVPU_PARAM_DEVICE_ID:
* PCI Device ID of the VPU device (read-only)
*
* %DRM_IVPU_PARAM_DEVICE_REVISION:
* VPU device revision (read-only)
*
* %DRM_IVPU_PARAM_PLATFORM_TYPE:
* Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific
* platform type when executing on a simulator or emulator (read-only)
*
* %DRM_IVPU_PARAM_CORE_CLOCK_RATE:
* Maximum frequency of the NPU data processing unit clock (read-only)
*
* %DRM_IVPU_PARAM_NUM_CONTEXTS:
* Maximum number of simultaneously existing contexts (read-only)
*
* %DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
* Lowest VPU virtual address available in the current context (read-only)
*
* %DRM_IVPU_PARAM_CONTEXT_ID:
* Current context ID, always greater than 0 (read-only)
*
* %DRM_IVPU_PARAM_FW_API_VERSION:
* Firmware API version array (read-only)
*
* %DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
* Heartbeat value from an engine (read-only).
* Engine ID (i.e. DRM_IVPU_ENGINE_COMPUTE) is given via index.
*
* %DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
* Device-unique inference ID (read-only)
*
* %DRM_IVPU_PARAM_TILE_CONFIG:
* VPU tile configuration (read-only)
*
* %DRM_IVPU_PARAM_SKU:
* VPU SKU ID (read-only)
*
* %DRM_IVPU_PARAM_CAPABILITIES:
* Supported capabilities (read-only)
*
* %DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE:
* Size of the preemption buffer (read-only)
*/
__u32 param;
/** @index: Index for params that have multiple instances */
__u32 index;
/** @value: Param value */
__u64 value;
};
#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
#define DRM_IVPU_BO_MAPPABLE 0x00000002
#define DRM_IVPU_BO_DMA_MEM 0x00000004
#define DRM_IVPU_BO_READ_ONLY 0x00000008
#define DRM_IVPU_BO_CACHED 0x00000000
#define DRM_IVPU_BO_UNCACHED 0x00010000
#define DRM_IVPU_BO_WC 0x00020000
#define DRM_IVPU_BO_CACHE_MASK 0x00030000
#define DRM_IVPU_BO_FLAGS \
(DRM_IVPU_BO_HIGH_MEM | \
DRM_IVPU_BO_MAPPABLE | \
DRM_IVPU_BO_DMA_MEM | \
DRM_IVPU_BO_READ_ONLY | \
DRM_IVPU_BO_CACHE_MASK)
/**
* struct drm_ivpu_bo_create - Create BO backed by SHMEM
*
* Create GEM buffer object allocated in SHMEM memory.
*/
struct drm_ivpu_bo_create {
/** @size: The size in bytes of the allocated memory */
__u64 size;
/**
* @flags:
*
* Supported flags:
*
* %DRM_IVPU_BO_HIGH_MEM:
*
* Allocate VPU address from >4GB range.
* Buffer object with vpu address >4GB can be always accessed by the
* VPU DMA engine, but some HW generation may not be able to access
* this memory from then firmware running on the VPU management processor.
* Suitable for input, output and some scratch buffers.
*
* %DRM_IVPU_BO_MAPPABLE:
*
* Buffer object can be mapped using mmap().
*
* %DRM_IVPU_BO_CACHED:
*
* Allocated BO will be cached on host side (WB) and snooped on the VPU side.
* This is the default caching mode.
*
* %DRM_IVPU_BO_UNCACHED:
*
* Not supported. Use DRM_IVPU_BO_WC instead.
*
* %DRM_IVPU_BO_WC:
*
* Allocated BO will use write combining buffer for writes but reads will be
* uncached.
*/
__u32 flags;
/** @handle: Returned GEM object handle */
__u32 handle;
/** @vpu_addr: Returned VPU virtual address */
__u64 vpu_addr;
};
/**
* struct drm_ivpu_bo_create_from_userptr - Create dma-buf from user pointer
*
* Create a GEM buffer object from a user pointer to a memory region.
*/
struct drm_ivpu_bo_create_from_userptr {
/** @user_ptr: User pointer to memory region (must be page aligned) */
__u64 user_ptr;
/** @size: Size of the memory region in bytes (must be page aligned) */
__u64 size;
/**
* @flags:
*
* Supported flags:
*
* %DRM_IVPU_BO_HIGH_MEM:
*
* Allocate VPU address from >4GB range.
*
* %DRM_IVPU_BO_DMA_MEM:
*
* Allocate from DMA memory range accessible by hardware DMA.
*
* %DRM_IVPU_BO_READ_ONLY:
*
* Allocate as a read-only buffer object.
*/
__u32 flags;
/** @handle: Returned GEM object handle */
__u32 handle;
/** @vpu_addr: Returned VPU virtual address */
__u64 vpu_addr;
};
/**
* struct drm_ivpu_bo_info - Query buffer object info
*/
struct drm_ivpu_bo_info {
/** @handle: Handle of the queried BO */
__u32 handle;
/** @flags: Returned flags used to create the BO */
__u32 flags;
/** @vpu_addr: Returned VPU virtual address */
__u64 vpu_addr;
/**
* @mmap_offset:
*
* Returned offset to be used in mmap(). 0 in case the BO is not mappable.
*/
__u64 mmap_offset;
/** @size: Returned GEM object size, aligned to PAGE_SIZE */
__u64 size;
};
/* drm_ivpu_submit engines */
#define DRM_IVPU_ENGINE_COMPUTE 0
#define DRM_IVPU_ENGINE_COPY 1 /* Deprecated */
/**
* struct drm_ivpu_submit - Submit commands to the VPU
*
* Execute a single command buffer on a given VPU engine.
* Handles to all referenced buffer objects have to be provided in @buffers_ptr.
*
* User space may wait on job completion using %DRM_IVPU_BO_WAIT ioctl.
*/
struct drm_ivpu_submit {
/**
* @buffers_ptr:
*
* A pointer to an u32 array of GEM handles of the BOs required for this job.
* The number of elements in the array must be equal to the value given by @buffer_count.
*
* The first BO is the command buffer. The rest of array has to contain all
* BOs referenced from the command buffer.
*/
__u64 buffers_ptr;
/** @buffer_count: Number of elements in the @buffers_ptr */
__u32 buffer_count;
/**
* @engine: Select the engine this job should be executed on
*
* %DRM_IVPU_ENGINE_COMPUTE:
*
* Performs Deep Learning Neural Compute Inference Operations
*/
__u32 engine;
/** @flags: Reserved for future use - must be zero */
__u32 flags;
/**
* @commands_offset:
*
* Offset inside the first buffer in @buffers_ptr containing commands
* to be executed. The offset has to be 8-byte aligned.
*/
__u32 commands_offset;
/**
* @priority:
*
* Priority to be set for related job command queue, can be one of the following:
* %DRM_IVPU_JOB_PRIORITY_DEFAULT
* %DRM_IVPU_JOB_PRIORITY_IDLE
* %DRM_IVPU_JOB_PRIORITY_NORMAL
* %DRM_IVPU_JOB_PRIORITY_FOCUS
* %DRM_IVPU_JOB_PRIORITY_REALTIME
*/
__u32 priority;
};
/**
* struct drm_ivpu_cmdq_submit - Submit commands to the VPU using explicit command queue
*
* Execute a single command buffer on a given command queue.
* Handles to all referenced buffer objects have to be provided in @buffers_ptr.
*
* User space may wait on job completion using %DRM_IVPU_BO_WAIT ioctl.
*/
struct drm_ivpu_cmdq_submit {
/**
* @buffers_ptr:
*
* A pointer to an u32 array of GEM handles of the BOs required for this job.
* The number of elements in the array must be equal to the value given by @buffer_count.
*
* The first BO is the command buffer. The rest of array has to contain all
* BOs referenced from the command buffer.
*/
__u64 buffers_ptr;
/** @buffer_count: Number of elements in the @buffers_ptr */
__u32 buffer_count;
/** @cmdq_id: ID for the command queue where job will be submitted */
__u32 cmdq_id;
/** @flags: Reserved for future use - must be zero */
__u32 flags;
/**
* @commands_offset:
*
* Offset inside the first buffer in @buffers_ptr containing commands
* to be executed. The offset has to be 8-byte aligned.
*/
__u32 commands_offset;
/**
* @preempt_buffer_index:
*
* Index of the preemption buffer in the buffers_ptr array.
*/
__u32 preempt_buffer_index;
__u32 reserved;
};
/* drm_ivpu_bo_wait job status codes */
#define DRM_IVPU_JOB_STATUS_SUCCESS 0
#define DRM_IVPU_JOB_STATUS_ABORTED 256
/**
* struct drm_ivpu_bo_wait - Wait for BO to become inactive
*
* Blocks until a given buffer object becomes inactive.
* With @timeout_ms set to 0 returns immediately.
*/
struct drm_ivpu_bo_wait {
/** @handle: Handle to the buffer object to be waited on */
__u32 handle;
/** @flags: Reserved for future use - must be zero */
__u32 flags;
/** @timeout_ns: Absolute timeout in nanoseconds (may be zero) */
__s64 timeout_ns;
/**
* @job_status:
*
* Job status code which is updated after the job is completed.
* &DRM_IVPU_JOB_STATUS_SUCCESS or device specific error otherwise.
* Valid only if @handle points to a command buffer.
*/
__u32 job_status;
/** @pad: Padding - must be zero */
__u32 pad;
};
/**
* struct drm_ivpu_metric_streamer_start - Start collecting metric data
*/
struct drm_ivpu_metric_streamer_start {
/** @metric_group_mask: Indicates metric streamer instance */
__u64 metric_group_mask;
/** @sampling_period_ns: Sampling period in nanoseconds */
__u64 sampling_period_ns;
/**
* @read_period_samples:
*
* Number of samples after which user space will try to read the data.
* Reading the data after significantly longer period may cause data loss.
*/
__u32 read_period_samples;
/** @sample_size: Returned size of a single sample in bytes */
__u32 sample_size;
/** @max_data_size: Returned max @data_size from %DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA */
__u32 max_data_size;
};
/**
* struct drm_ivpu_metric_streamer_get_data - Copy collected metric data
*/
struct drm_ivpu_metric_streamer_get_data {
/** @metric_group_mask: Indicates metric streamer instance */
__u64 metric_group_mask;
/** @buffer_ptr: A pointer to a destination for the copied data */
__u64 buffer_ptr;
/** @buffer_size: Size of the destination buffer */
__u64 buffer_size;
/**
* @data_size: Returned size of copied metric data
*
* If the @buffer_size is zero, returns the amount of data ready to be copied.
*/
__u64 data_size;
};
/* Command queue flags */
#define DRM_IVPU_CMDQ_FLAG_TURBO 0x00000001
/**
* struct drm_ivpu_cmdq_create - Create command queue for job submission
*/
struct drm_ivpu_cmdq_create {
/** @cmdq_id: Returned ID of created command queue */
__u32 cmdq_id;
/**
* @priority:
*
* Priority to be set for related job command queue, can be one of the following:
* %DRM_IVPU_JOB_PRIORITY_DEFAULT
* %DRM_IVPU_JOB_PRIORITY_IDLE
* %DRM_IVPU_JOB_PRIORITY_NORMAL
* %DRM_IVPU_JOB_PRIORITY_FOCUS
* %DRM_IVPU_JOB_PRIORITY_REALTIME
*/
__u32 priority;
/**
* @flags:
*
* Supported flags:
*
* %DRM_IVPU_CMDQ_FLAG_TURBO
*
* Enable low-latency mode for the command queue. The NPU will maximize performance
* when executing jobs from such queue at the cost of increased power usage.
*/
__u32 flags;
};
/**
* struct drm_ivpu_cmdq_destroy - Destroy a command queue
*/
struct drm_ivpu_cmdq_destroy {
/** @cmdq_id: ID of command queue to destroy */
__u32 cmdq_id;
};
/**
* struct drm_ivpu_metric_streamer_stop - Stop collecting metric data
*/
struct drm_ivpu_metric_streamer_stop {
/** @metric_group_mask: Indicates metric streamer instance */
__u64 metric_group_mask;
};
#if defined(__cplusplus)
}
#endif
#endif /* __UAPI_IVPU_DRM_H__ */
linux-7.2.3/include/uapi/drm/lima_drm.h
+176
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/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
#ifndef __LIMA_DRM_H__
#define __LIMA_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
enum drm_lima_param_gpu_id {
DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
DRM_LIMA_PARAM_GPU_ID_MALI400,
DRM_LIMA_PARAM_GPU_ID_MALI450,
};
enum drm_lima_param {
DRM_LIMA_PARAM_GPU_ID,
DRM_LIMA_PARAM_NUM_PP,
DRM_LIMA_PARAM_GP_VERSION,
DRM_LIMA_PARAM_PP_VERSION,
};
/**
* get various information of the GPU
*/
struct drm_lima_get_param {
__u32 param; /* in, value in enum drm_lima_param */
__u32 pad; /* pad, must be zero */
__u64 value; /* out, parameter value */
};
/*
* heap buffer dynamically increase backup memory size when GP task fail
* due to lack of heap memory. size field of heap buffer is an up bound of
* the backup memory which can be set to a fairly large value.
*/
#define LIMA_BO_FLAG_HEAP (1 << 0)
/**
* create a buffer for used by GPU
*/
struct drm_lima_gem_create {
__u32 size; /* in, buffer size */
__u32 flags; /* in, buffer flags */
__u32 handle; /* out, GEM buffer handle */
__u32 pad; /* pad, must be zero */
};
/**
* get information of a buffer
*/
struct drm_lima_gem_info {
__u32 handle; /* in, GEM buffer handle */
__u32 va; /* out, virtual address mapped into GPU MMU */
__u64 offset; /* out, used to mmap this buffer to CPU */
};
#define LIMA_SUBMIT_BO_READ 0x01
#define LIMA_SUBMIT_BO_WRITE 0x02
/* buffer information used by one task */
struct drm_lima_gem_submit_bo {
__u32 handle; /* in, GEM buffer handle */
__u32 flags; /* in, buffer read/write by GPU */
};
#define LIMA_GP_FRAME_REG_NUM 6
/* frame used to setup GP for each task */
struct drm_lima_gp_frame {
__u32 frame[LIMA_GP_FRAME_REG_NUM];
};
#define LIMA_PP_FRAME_REG_NUM 23
#define LIMA_PP_WB_REG_NUM 12
/* frame used to setup mali400 GPU PP for each task */
struct drm_lima_m400_pp_frame {
__u32 frame[LIMA_PP_FRAME_REG_NUM];
__u32 num_pp;
__u32 wb[3 * LIMA_PP_WB_REG_NUM];
__u32 plbu_array_address[4];
__u32 fragment_stack_address[4];
};
/* frame used to setup mali450 GPU PP for each task */
struct drm_lima_m450_pp_frame {
__u32 frame[LIMA_PP_FRAME_REG_NUM];
__u32 num_pp;
__u32 wb[3 * LIMA_PP_WB_REG_NUM];
__u32 use_dlbu;
__u32 _pad;
union {
__u32 plbu_array_address[8];
__u32 dlbu_regs[4];
};
__u32 fragment_stack_address[8];
};
#define LIMA_PIPE_GP 0x00
#define LIMA_PIPE_PP 0x01
#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
/**
* submit a task to GPU
*
* User can always merge multi sync_file and drm_syncobj
* into one drm_syncobj as in_sync[0], but we reserve
* in_sync[1] for another task's out_sync to avoid the
* export/import/merge pass when explicit sync.
*/
struct drm_lima_gem_submit {
__u32 ctx; /* in, context handle task is submitted to */
__u32 pipe; /* in, which pipe to use, GP/PP */
__u32 nr_bos; /* in, array length of bos field */
__u32 frame_size; /* in, size of frame field */
__u64 bos; /* in, array of drm_lima_gem_submit_bo */
__u64 frame; /* in, GP/PP frame */
__u32 flags; /* in, submit flags */
__u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */
__u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */
};
#define LIMA_GEM_WAIT_READ 0x01
#define LIMA_GEM_WAIT_WRITE 0x02
/**
* wait pending GPU task finish of a buffer
*/
struct drm_lima_gem_wait {
__u32 handle; /* in, GEM buffer handle */
__u32 op; /* in, CPU want to read/write this buffer */
__s64 timeout_ns; /* in, wait timeout in absulute time */
};
/**
* create a context
*/
struct drm_lima_ctx_create {
__u32 id; /* out, context handle */
__u32 _pad; /* pad, must be zero */
};
/**
* free a context
*/
struct drm_lima_ctx_free {
__u32 id; /* in, context handle */
__u32 _pad; /* pad, must be zero */
};
#define DRM_LIMA_GET_PARAM 0x00
#define DRM_LIMA_GEM_CREATE 0x01
#define DRM_LIMA_GEM_INFO 0x02
#define DRM_LIMA_GEM_SUBMIT 0x03
#define DRM_LIMA_GEM_WAIT 0x04
#define DRM_LIMA_CTX_CREATE 0x05
#define DRM_LIMA_CTX_FREE 0x06
#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
#if defined(__cplusplus)
}
#endif
#endif /* __LIMA_DRM_H__ */
linux-7.2.3/include/uapi/drm/msm_drm.h
+577
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@@ -0,0 +1,577 @@
/*
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __MSM_DRM_H__
#define __MSM_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints:
* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
* user/kernel compatibility
* 2) Keep fields aligned to their size
* 3) Because of how drm_ioctl() works, we can add new fields at
* the end of an ioctl if some care is taken: drm_ioctl() will
* zero out the new fields at the tail of the ioctl, so a zero
* value should have a backwards compatible meaning. And for
* output params, userspace won't see the newly added output
* fields.. so that has to be somehow ok.
*/
#define MSM_PIPE_NONE 0x00
#define MSM_PIPE_2D0 0x01
#define MSM_PIPE_2D1 0x02
#define MSM_PIPE_3D0 0x10
/* The pipe-id just uses the lower bits, so can be OR'd with flags in
* the upper 16 bits (which could be extended further, if needed, maybe
* we extend/overload the pipe-id some day to deal with multiple rings,
* but even then I don't think we need the full lower 16 bits).
*/
#define MSM_PIPE_ID_MASK 0xffff
#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
/* timeouts are specified in clock-monotonic absolute times (to simplify
* restarting interrupted ioctls). The following struct is logically the
* same as 'struct timespec' but 32/64b ABI safe.
*/
struct drm_msm_timespec {
__s64 tv_sec; /* seconds */
__s64 tv_nsec; /* nanoseconds */
};
/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
* "RW" indicates a param that can be both read (GET_PARAM) and written
* (SET_PARAM)
*/
#define MSM_PARAM_GPU_ID 0x01 /* RO */
#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
#define MSM_PARAM_CHIP_ID 0x03 /* RO */
#define MSM_PARAM_MAX_FREQ 0x04 /* RO */
#define MSM_PARAM_TIMESTAMP 0x05 /* RO */
#define MSM_PARAM_GMEM_BASE 0x06 /* RO */
#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
#define MSM_PARAM_FAULTS 0x09 /* RO */
#define MSM_PARAM_SUSPENDS 0x0a /* RO */
#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
#define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */
#define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */
#define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */
#define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */
#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
#define MSM_PARAM_RAYTRACING 0x11 /* RO */
#define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */
#define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */
#define MSM_PARAM_UCHE_TRAP_BASE 0x14 /* RO */
/* PRR (Partially Resident Region) is required for sparse residency: */
#define MSM_PARAM_HAS_PRR 0x15 /* RO */
/* MSM_PARAM_EN_VM_BIND is set to 1 to enable VM_BIND ops.
*
* With VM_BIND enabled, userspace is required to allocate iova and use the
* VM_BIND ops for map/unmap ioctls. MSM_INFO_SET_IOVA and MSM_INFO_GET_IOVA
* will be rejected. (The latter does not have a sensible meaning when a BO
* can have multiple and/or partial mappings.)
*
* With VM_BIND enabled, userspace does not include a submit_bo table in the
* SUBMIT ioctl (this will be rejected), the resident set is determined by
* the the VM_BIND ops.
*
* Enabling VM_BIND will fail on devices which do not have per-process pgtables.
* And it is not allowed to disable VM_BIND once it has been enabled.
*
* Enabling VM_BIND should be done (attempted) prior to allocating any BOs or
* submitqueues of type MSM_SUBMITQUEUE_VM_BIND.
*
* Relatedly, when VM_BIND mode is enabled, the kernel will not try to recover
* from GPU faults or failed async VM_BIND ops, in particular because it is
* difficult to communicate to userspace which op failed so that userspace
* could rewind and try again. When the VM is marked unusable, the SUBMIT
* ioctl will throw -EPIPE.
*/
#define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */
#define MSM_PARAM_AQE 0x17 /* RO */
/* For backwards compat. The original support for preemption was based on
* a single ring per priority level so # of priority levels equals the #
* of rings. With drm/scheduler providing additional levels of priority,
* the number of priorities is greater than the # of rings. The param is
* renamed to better reflect this.
*/
#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
struct drm_msm_param {
__u32 pipe; /* in, MSM_PIPE_x */
__u32 param; /* in, MSM_PARAM_x */
__u64 value; /* out (get_param) or in (set_param) */
__u32 len; /* zero for non-pointer params */
__u32 pad; /* must be zero */
};
/*
* GEM buffers:
*/
#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
#define MSM_BO_GPU_READONLY 0x00000002
/* Private buffers do not need to be explicitly listed in the SUBMIT
* ioctl, unless referenced by a drm_msm_gem_submit_cmd. Private
* buffers may NOT be imported/exported or used for scanout (or any
* other situation where buffers can be indefinitely pinned, but
* cases other than scanout are all kernel owned BOs which are not
* visible to userspace).
*
* In exchange for those constraints, all private BOs associated with
* a single context (drm_file) share a single dma_resv, and if there
* has been no eviction since the last submit, there are no per-BO
* bookeeping to do, significantly cutting the SUBMIT overhead.
*/
#define MSM_BO_NO_SHARE 0x00000004
#define MSM_BO_CACHE_MASK 0x000f0000
/* cache modes */
#define MSM_BO_CACHED 0x00010000
#define MSM_BO_WC 0x00020000
#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
#define MSM_BO_CACHED_COHERENT 0x080000
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
MSM_BO_GPU_READONLY | \
MSM_BO_NO_SHARE | \
MSM_BO_CACHE_MASK)
struct drm_msm_gem_new {
__u64 size; /* in */
__u32 flags; /* in, mask of MSM_BO_x */
__u32 handle; /* out */
};
/* Get or set GEM buffer info. The requested value can be passed
* directly in 'value', or for data larger than 64b 'value' is a
* pointer to userspace buffer, with 'len' specifying the number of
* bytes copied into that buffer. For info returned by pointer,
* calling the GEM_INFO ioctl with null 'value' will return the
* required buffer size in 'len'
*/
#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
#define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */
#define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */
struct drm_msm_gem_info {
__u32 handle; /* in */
__u32 info; /* in - one of MSM_INFO_* */
__u64 value; /* in or out */
__u32 len; /* in or out */
__u32 pad;
};
#define MSM_PREP_READ 0x01
#define MSM_PREP_WRITE 0x02
#define MSM_PREP_NOSYNC 0x04
#define MSM_PREP_BOOST 0x08
#define MSM_PREP_FLAGS (MSM_PREP_READ | \
MSM_PREP_WRITE | \
MSM_PREP_NOSYNC | \
MSM_PREP_BOOST | \
0)
struct drm_msm_gem_cpu_prep {
__u32 handle; /* in */
__u32 op; /* in, mask of MSM_PREP_x */
struct drm_msm_timespec timeout; /* in */
};
struct drm_msm_gem_cpu_fini {
__u32 handle; /* in */
};
/*
* Cmdstream Submission:
*/
#define MSM_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
#define MSM_SYNCOBJ_FLAGS ( \
MSM_SYNCOBJ_RESET | \
0)
struct drm_msm_syncobj {
__u32 handle; /* in, syncobj handle. */
__u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
__u64 point; /* in, timepoint for timeline syncobjs. */
};
/* The value written into the cmdstream is logically:
*
* ((relocbuf->gpuaddr + reloc_offset) << shift) | or
*
* When we have GPU's w/ >32bit ptrs, it should be possible to deal
* with this by emit'ing two reloc entries with appropriate shift
* values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
*
* NOTE that reloc's must be sorted by order of increasing submit_offset,
* otherwise EINVAL.
*/
struct drm_msm_gem_submit_reloc {
__u32 submit_offset; /* in, offset from submit_bo */
#ifdef __cplusplus
__u32 _or; /* in, value OR'd with result */
#else
__u32 or; /* in, value OR'd with result */
#endif
__s32 shift; /* in, amount of left shift (can be negative) */
__u32 reloc_idx; /* in, index of reloc_bo buffer */
__u64 reloc_offset; /* in, offset from start of reloc_bo */
};
/* submit-types:
* BUF - this cmd buffer is executed normally.
* IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
* processed normally, but the kernel does not setup an IB to
* this buffer in the first-level ringbuffer
* CTX_RESTORE_BUF - only executed if there has been a GPU context
* switch since the last SUBMIT ioctl
*/
#define MSM_SUBMIT_CMD_BUF 0x0001
#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
struct drm_msm_gem_submit_cmd {
__u32 type; /* in, one of MSM_SUBMIT_CMD_x */
__u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
__u32 submit_offset; /* in, offset into submit_bo */
__u32 size; /* in, cmdstream size */
__u32 pad;
__u32 nr_relocs; /* in, number of submit_reloc's */
union {
__u64 relocs; /* in, ptr to array of submit_reloc's */
__u64 iova; /* cmdstream address (for VM_BIND contexts) */
};
};
/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
* cmdstream buffer(s) themselves or reloc entries) has one (and only
* one) entry in the submit->bos[] table.
*
* As a optimization, the current buffer (gpu virtual address) can be
* passed back through the 'presumed' field. If on a subsequent reloc,
* userspace passes back a 'presumed' address that is still valid,
* then patching the cmdstream for this entry is skipped. This can
* avoid kernel needing to map/access the cmdstream bo in the common
* case.
*/
#define MSM_SUBMIT_BO_READ 0x0001
#define MSM_SUBMIT_BO_WRITE 0x0002
#define MSM_SUBMIT_BO_DUMP 0x0004
#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
MSM_SUBMIT_BO_WRITE | \
MSM_SUBMIT_BO_DUMP | \
MSM_SUBMIT_BO_NO_IMPLICIT)
struct drm_msm_gem_submit_bo {
__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
__u32 handle; /* in, GEM handle */
__u64 presumed; /* in/out, presumed buffer address */
};
/* Valid submit ioctl flags: */
#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
#define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */
#define MSM_SUBMIT_FLAGS ( \
MSM_SUBMIT_NO_IMPLICIT | \
MSM_SUBMIT_FENCE_FD_IN | \
MSM_SUBMIT_FENCE_FD_OUT | \
MSM_SUBMIT_SUDO | \
MSM_SUBMIT_SYNCOBJ_IN | \
MSM_SUBMIT_SYNCOBJ_OUT | \
MSM_SUBMIT_FENCE_SN_IN | \
0)
/* Each cmdstream submit consists of a table of buffers involved, and
* one or more cmdstream buffers. This allows for conditional execution
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
*/
struct drm_msm_gem_submit {
__u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
__u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
__u32 nr_bos; /* in, number of submit_bo's */
__u32 nr_cmds; /* in, number of submit_cmd's */
__u64 bos; /* in, ptr to array of submit_bo's */
__u64 cmds; /* in, ptr to array of submit_cmd's */
__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
__u32 queueid; /* in, submitqueue id */
__u64 in_syncobjs; /* in, ptr to array of drm_msm_syncobj */
__u64 out_syncobjs; /* in, ptr to array of drm_msm_syncobj */
__u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
__u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
__u32 syncobj_stride; /* in, stride of syncobj arrays. */
__u32 pad; /*in, reserved for future use, always 0. */
};
#define MSM_VM_BIND_OP_UNMAP 0
#define MSM_VM_BIND_OP_MAP 1
#define MSM_VM_BIND_OP_MAP_NULL 2
#define MSM_VM_BIND_OP_DUMP 1
#define MSM_VM_BIND_OP_FLAGS ( \
MSM_VM_BIND_OP_DUMP | \
0)
/**
* struct drm_msm_vm_bind_op - bind/unbind op to run
*/
struct drm_msm_vm_bind_op {
/** @op: one of MSM_VM_BIND_OP_x */
__u32 op;
/** @handle: GEM object handle, MBZ for UNMAP or MAP_NULL */
__u32 handle;
/** @obj_offset: Offset into GEM object, MBZ for UNMAP or MAP_NULL */
__u64 obj_offset;
/** @iova: Address to operate on */
__u64 iova;
/** @range: Number of bites to to map/unmap */
__u64 range;
/** @flags: Bitmask of MSM_VM_BIND_OP_FLAG_x */
__u32 flags;
/** @pad: MBZ */
__u32 pad;
};
#define MSM_VM_BIND_FENCE_FD_IN 0x00000001
#define MSM_VM_BIND_FENCE_FD_OUT 0x00000002
#define MSM_VM_BIND_FLAGS ( \
MSM_VM_BIND_FENCE_FD_IN | \
MSM_VM_BIND_FENCE_FD_OUT | \
0)
/**
* struct drm_msm_vm_bind - Input of &DRM_IOCTL_MSM_VM_BIND
*/
struct drm_msm_vm_bind {
/** @flags: in, bitmask of MSM_VM_BIND_x */
__u32 flags;
/** @nr_ops: the number of bind ops in this ioctl */
__u32 nr_ops;
/** @fence_fd: in/out fence fd (see MSM_VM_BIND_FENCE_FD_IN/OUT) */
__s32 fence_fd;
/** @queue_id: in, submitqueue id */
__u32 queue_id;
/** @in_syncobjs: in, ptr to array of drm_msm_gem_syncobj */
__u64 in_syncobjs;
/** @out_syncobjs: in, ptr to array of drm_msm_gem_syncobj */
__u64 out_syncobjs;
/** @nr_in_syncobjs: in, number of entries in in_syncobj */
__u32 nr_in_syncobjs;
/** @nr_out_syncobjs: in, number of entries in out_syncobj */
__u32 nr_out_syncobjs;
/** @syncobj_stride: in, stride of syncobj arrays */
__u32 syncobj_stride;
/** @op_stride: sizeof each struct drm_msm_vm_bind_op in @ops */
__u32 op_stride;
union {
/** @op: used if num_ops == 1 */
struct drm_msm_vm_bind_op op;
/** @ops: userptr to array of drm_msm_vm_bind_op if num_ops > 1 */
__u64 ops;
};
};
#define MSM_WAIT_FENCE_BOOST 0x00000001
#define MSM_WAIT_FENCE_FLAGS ( \
MSM_WAIT_FENCE_BOOST | \
0)
/* The normal way to synchronize with the GPU is just to CPU_PREP on
* a buffer if you need to access it from the CPU (other cmdstream
* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
* handle the required synchronization under the hood). This ioctl
* mainly just exists as a way to implement the gallium pipe_fence
* APIs without requiring a dummy bo to synchronize on.
*/
struct drm_msm_wait_fence {
__u32 fence; /* in */
__u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */
struct drm_msm_timespec timeout; /* in */
__u32 queueid; /* in, submitqueue id */
};
/* madvise provides a way to tell the kernel in case a buffers contents
* can be discarded under memory pressure, which is useful for userspace
* bo cache where we want to optimistically hold on to buffer allocate
* and potential mmap, but allow the pages to be discarded under memory
* pressure.
*
* Typical usage would involve madvise(DONTNEED) when buffer enters BO
* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
* In the WILLNEED case, 'retained' indicates to userspace whether the
* backing pages still exist.
*/
#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
#define __MSM_MADV_PURGED 2 /* internal state */
struct drm_msm_gem_madvise {
__u32 handle; /* in, GEM handle */
__u32 madv; /* in, MSM_MADV_x */
__u32 retained; /* out, whether backing store still exists */
};
/*
* Draw queues allow the user to set specific submission parameter. Command
* submissions specify a specific submitqueue to use. ID 0 is reserved for
* backwards compatibility as a "default" submitqueue.
*
* Because VM_BIND async updates happen on the CPU, they must run on a
* virtual queue created with the flag MSM_SUBMITQUEUE_VM_BIND. If we had
* a way to do pgtable updates on the GPU, we could drop this restriction.
*/
#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001
#define MSM_SUBMITQUEUE_VM_BIND 0x00000002 /* virtual queue for VM_BIND ops */
#define MSM_SUBMITQUEUE_FLAGS ( \
MSM_SUBMITQUEUE_ALLOW_PREEMPT | \
MSM_SUBMITQUEUE_VM_BIND | \
0)
/*
* The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
* a lower numeric value is higher priority.
*/
struct drm_msm_submitqueue {
__u32 flags; /* in, MSM_SUBMITQUEUE_x */
__u32 prio; /* in, Priority level */
__u32 id; /* out, identifier */
};
#define MSM_SUBMITQUEUE_PARAM_FAULTS 0
struct drm_msm_submitqueue_query {
__u64 data;
__u32 id;
__u32 param;
__u32 len;
__u32 pad;
};
#define MSM_PERFCNTR_STREAM 0x00000001
#define MSM_PERFCNTR_UPDATE 0x00000002
#define MSM_PERFCNTR_FLAGS ( \
MSM_PERFCNTR_STREAM | \
MSM_PERFCNTR_UPDATE | \
0)
struct drm_msm_perfcntr_group {
char group_name[16];
__u32 nr_countables;
__u32 pad; /* mbz */
__u64 countables; /* pointer to an array of nr_countables u32 */
};
/*
* Note, for MSM_PERFCNTR_STREAM, the ioctl returns an fd to read recorded
* counters. This only works because the ioctl is DRM_IOW(), if we returned
* a out param in the ioctl struct the copy_to_user() (in drm_ioctl())
* could fault, causing us to leak the fd.
*
* If the ioctl returns with error E2BIG, that means more counters/countables
* are requested than are currently available. If MSM_PERFCNTR_UPDATE flag
* is set, drm_msm_perfcntr_group::nr_countables will be updated to return
* the actual # of counters available.
*
* The data read from the has the following format for each sampling period:
*
* uint64_t timestamp; // CP_ALWAYS_ON_COUNTER captured at sample time
* uint32_t seqno; // increments by 1 each period, reset to 0 on discontinuity
* uint32_t mbz; // pad out counters to 64b
* struct {
* uint64_t counter[nr_countables];
* } groups[nr_groups];
*
* The ordering of groups and counters matches the order in PERFCNTR_CONFIG
* ioctl.
*/
struct drm_msm_perfcntr_config {
__u32 flags; /* bitmask of MSM_PERFCNTR_x */
__u32 nr_groups; /* # of entries in groups array */
__u64 groups; /* pointer to array of drm_msm_perfcntr_group */
__u64 period; /* sampling period in ns */
__u32 bufsz_shift; /* sample buffer size in bytes is 1<<bufsz_shift */
__u32 group_stride; /* sizeof(struct drm_msm_perfcntr_group) */
};
#define DRM_MSM_GET_PARAM 0x00
#define DRM_MSM_SET_PARAM 0x01
#define DRM_MSM_GEM_NEW 0x02
#define DRM_MSM_GEM_INFO 0x03
#define DRM_MSM_GEM_CPU_PREP 0x04
#define DRM_MSM_GEM_CPU_FINI 0x05
#define DRM_MSM_GEM_SUBMIT 0x06
#define DRM_MSM_WAIT_FENCE 0x07
#define DRM_MSM_GEM_MADVISE 0x08
/* placeholder:
#define DRM_MSM_GEM_SVM_NEW 0x09
*/
#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
#define DRM_MSM_VM_BIND 0x0D
#define DRM_MSM_PERFCNTR_CONFIG 0x0E
#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
#define DRM_IOCTL_MSM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind)
#define DRM_IOCTL_MSM_PERFCNTR_CONFIG DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_PERFCNTR_CONFIG, struct drm_msm_perfcntr_config)
#if defined(__cplusplus)
}
#endif
#endif /* __MSM_DRM_H__ */
linux-7.2.3/include/uapi/drm/nouveau_drm.h
+586
View File
@@ -0,0 +1,586 @@
/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__
#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define NOUVEAU_GETPARAM_PCI_VENDOR 3
#define NOUVEAU_GETPARAM_PCI_DEVICE 4
#define NOUVEAU_GETPARAM_BUS_TYPE 5
#define NOUVEAU_GETPARAM_FB_SIZE 8
#define NOUVEAU_GETPARAM_AGP_SIZE 9
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
#define NOUVEAU_GETPARAM_PTIMER_TIME 14
#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
/*
* NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
*
* Query the maximum amount of IBs that can be pushed through a single
* &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
* ioctl().
*/
#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
/*
* NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size
*
* Query the VRAM BAR size.
*/
#define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18
/*
* NOUVEAU_GETPARAM_VRAM_USED
*
* Get remaining VRAM size.
*/
#define NOUVEAU_GETPARAM_VRAM_USED 19
/*
* NOUVEAU_GETPARAM_HAS_VMA_TILEMODE
*
* Query whether tile mode and PTE kind are accepted with VM allocs or not.
*/
#define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20
struct drm_nouveau_getparam {
__u64 param;
__u64 value;
};
/*
* Those are used to support selecting the main engine used on Kepler.
* This goes into drm_nouveau_channel_alloc::tt_ctxdma_handle
*/
#define NOUVEAU_FIFO_ENGINE_GR 0x01
#define NOUVEAU_FIFO_ENGINE_VP 0x02
#define NOUVEAU_FIFO_ENGINE_PPP 0x04
#define NOUVEAU_FIFO_ENGINE_BSP 0x08
#define NOUVEAU_FIFO_ENGINE_CE 0x30
struct drm_nouveau_channel_alloc {
__u32 fb_ctxdma_handle;
__u32 tt_ctxdma_handle;
__s32 channel;
__u32 pushbuf_domains;
/* Notifier memory */
__u32 notifier_handle;
/* DRM-enforced subchannel assignments */
struct {
__u32 handle;
__u32 grclass;
} subchan[8];
__u32 nr_subchan;
};
struct drm_nouveau_channel_free {
__s32 channel;
};
struct drm_nouveau_notifierobj_alloc {
__u32 channel;
__u32 handle;
__u32 size;
__u32 offset;
};
struct drm_nouveau_gpuobj_free {
__s32 channel;
__u32 handle;
};
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
/* The BO will never be shared via import or export. */
#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
#define NOUVEAU_GEM_TILE_16BPP 0x00000001
#define NOUVEAU_GEM_TILE_32BPP 0x00000002
#define NOUVEAU_GEM_TILE_ZETA 0x00000004
#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
struct drm_nouveau_gem_info {
__u32 handle;
__u32 domain;
__u64 size;
__u64 offset;
__u64 map_handle;
__u32 tile_mode;
__u32 tile_flags;
};
struct drm_nouveau_gem_new {
struct drm_nouveau_gem_info info;
__u32 channel_hint;
__u32 align;
};
#define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed {
__u32 valid;
__u32 domain;
__u64 offset;
};
struct drm_nouveau_gem_pushbuf_bo {
__u64 user_priv;
__u32 handle;
__u32 read_domains;
__u32 write_domains;
__u32 valid_domains;
struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
};
#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
#define NOUVEAU_GEM_RELOC_OR (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc {
__u32 reloc_bo_index;
__u32 reloc_bo_offset;
__u32 bo_index;
__u32 flags;
__u32 data;
__u32 vor;
__u32 tor;
};
#define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push {
__u32 bo_index;
__u32 pad;
__u64 offset;
__u64 length;
#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
};
struct drm_nouveau_gem_pushbuf {
__u32 channel;
__u32 nr_buffers;
__u64 buffers;
__u32 nr_relocs;
__u32 nr_push;
__u64 relocs;
__u64 push;
__u32 suffix0;
__u32 suffix1;
#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
__u64 vram_available;
__u64 gart_available;
};
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
struct drm_nouveau_gem_cpu_prep {
__u32 handle;
__u32 flags;
};
struct drm_nouveau_gem_cpu_fini {
__u32 handle;
};
/**
* struct drm_nouveau_sync - sync object
*
* This structure serves as synchronization mechanism for (potentially)
* asynchronous operations such as EXEC or VM_BIND.
*/
struct drm_nouveau_sync {
/**
* @flags: the flags for a sync object
*
* The first 8 bits are used to determine the type of the sync object.
*/
__u32 flags;
#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
/**
* @handle: the handle of the sync object
*/
__u32 handle;
/**
* @timeline_value:
*
* The timeline point of the sync object in case the syncobj is of
* type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
*/
__u64 timeline_value;
};
/**
* struct drm_nouveau_vm_init - GPU VA space init structure
*
* Used to initialize the GPU's VA space for a user client, telling the kernel
* which portion of the VA space is managed by the UMD and kernel respectively.
*
* For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
* channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
* with -ENOSYS.
*/
struct drm_nouveau_vm_init {
/**
* @kernel_managed_addr: start address of the kernel managed VA space
* region
*/
__u64 kernel_managed_addr;
/**
* @kernel_managed_size: size of the kernel managed VA space region in
* bytes
*/
__u64 kernel_managed_size;
};
/**
* struct drm_nouveau_vm_bind_op - VM_BIND operation
*
* This structure represents a single VM_BIND operation. UMDs should pass
* an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
*/
struct drm_nouveau_vm_bind_op {
/**
* @op: the operation type
*
* Supported values:
*
* %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA
* space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be
* passed to instruct the kernel to create sparse mappings for the
* given range.
*
* %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the
* GPU's VA space. If the region the mapping is located in is a
* sparse region, new sparse mappings are created where the unmapped
* (memory backed) mapping was mapped previously. To remove a sparse
* region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
*/
__u32 op;
#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
/**
* @flags: the flags for a &drm_nouveau_vm_bind_op
*
* Supported values:
*
* %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA
* space region should be sparse.
*/
__u32 flags;
#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
/**
* @handle: the handle of the DRM GEM object to map
*/
__u32 handle;
/**
* @pad: 32 bit padding, should be 0
*/
__u32 pad;
/**
* @addr:
*
* the address the VA space region or (memory backed) mapping should be mapped to
*/
__u64 addr;
/**
* @bo_offset: the offset within the BO backing the mapping
*/
__u64 bo_offset;
/**
* @range: the size of the requested mapping in bytes
*/
__u64 range;
};
/**
* struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
*/
struct drm_nouveau_vm_bind {
/**
* @op_count: the number of &drm_nouveau_vm_bind_op
*/
__u32 op_count;
/**
* @flags: the flags for a &drm_nouveau_vm_bind ioctl
*
* Supported values:
*
* %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND
* operation should be executed asynchronously by the kernel.
*
* If this flag is not supplied the kernel executes the associated
* operations synchronously and doesn't accept any &drm_nouveau_sync
* objects.
*/
__u32 flags;
#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
/**
* @wait_count: the number of wait &drm_nouveau_syncs
*/
__u32 wait_count;
/**
* @sig_count: the number of &drm_nouveau_syncs to signal when finished
*/
__u32 sig_count;
/**
* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
*/
__u64 wait_ptr;
/**
* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
*/
__u64 sig_ptr;
/**
* @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
*/
__u64 op_ptr;
};
/**
* struct drm_nouveau_exec_push - EXEC push operation
*
* This structure represents a single EXEC push operation. UMDs should pass an
* array of this structure via struct drm_nouveau_exec's &push_ptr field.
*/
struct drm_nouveau_exec_push {
/**
* @va: the virtual address of the push buffer mapping
*/
__u64 va;
/**
* @va_len: the length of the push buffer mapping
*/
__u32 va_len;
/**
* @flags: the flags for this push buffer mapping
*/
__u32 flags;
#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
};
/**
* struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
*/
struct drm_nouveau_exec {
/**
* @channel: the channel to execute the push buffer in
*/
__u32 channel;
/**
* @push_count: the number of &drm_nouveau_exec_push ops
*/
__u32 push_count;
/**
* @wait_count: the number of wait &drm_nouveau_syncs
*/
__u32 wait_count;
/**
* @sig_count: the number of &drm_nouveau_syncs to signal when finished
*/
__u32 sig_count;
/**
* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
*/
__u64 wait_ptr;
/**
* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
*/
__u64 sig_ptr;
/**
* @push_ptr: pointer to &drm_nouveau_exec_push ops
*/
__u64 push_ptr;
};
struct drm_nouveau_get_zcull_info {
/**
* @width_align_pixels: required alignment for region widths, in pixels
* (typically #TPC's * 16).
*/
__u32 width_align_pixels;
/**
* @height_align_pixels: required alignment for region heights, in
* pixels (typically 32).
*/
__u32 height_align_pixels;
/**
* @pixel_squares_by_aliquots: the pixel area covered by an aliquot
* (typically #Zcull_banks * 16 * 16).
*/
__u32 pixel_squares_by_aliquots;
/**
* @aliquot_total: the total aliquot pool available in hardware
*/
__u32 aliquot_total;
/**
* @zcull_region_byte_multiplier: the size of an aliquot in bytes, which
* is used for save/restore operations on a region
*/
__u32 zcull_region_byte_multiplier;
/**
* @zcull_region_header_size: the region header size in bytes, which is
* used for save/restore operations on a region
*/
__u32 zcull_region_header_size;
/**
* @zcull_subregion_header_size: the subregion header size in bytes,
* which is used for save/restore operations on a region
*/
__u32 zcull_subregion_header_size;
/**
* @subregion_count: the total number of subregions the hardware
* supports
*/
__u32 subregion_count;
/**
* @subregion_width_align_pixels: required alignment for subregion
* widths, in pixels (typically #TPC's * 16).
*/
__u32 subregion_width_align_pixels;
/**
* @subregion_height_align_pixels: required alignment for subregion
* heights, in pixels
*/
__u32 subregion_height_align_pixels;
/**
* @ctxsw_size: the size, in bytes, of a zcull context switching region.
* Will be zero if the kernel does not support zcull context switching.
*/
__u32 ctxsw_size;
/**
* @ctxsw_align: the alignment, in bytes, of a zcull context switching
* region
*/
__u32 ctxsw_align;
};
#define DRM_NOUVEAU_GETPARAM 0x00
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
#define DRM_NOUVEAU_CHANNEL_FREE 0x03
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
#define DRM_NOUVEAU_NVIF 0x07
#define DRM_NOUVEAU_SVM_INIT 0x08
#define DRM_NOUVEAU_SVM_BIND 0x09
#define DRM_NOUVEAU_VM_INIT 0x10
#define DRM_NOUVEAU_VM_BIND 0x11
#define DRM_NOUVEAU_EXEC 0x12
#define DRM_NOUVEAU_GET_ZCULL_INFO 0x13
#define DRM_NOUVEAU_GEM_NEW 0x40
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
#define DRM_NOUVEAU_GEM_INFO 0x44
struct drm_nouveau_svm_init {
__u64 unmanaged_addr;
__u64 unmanaged_size;
};
struct drm_nouveau_svm_bind {
__u64 header;
__u64 va_start;
__u64 va_end;
__u64 npages;
__u64 stride;
__u64 result;
__u64 reserved0;
__u64 reserved1;
};
#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
#define NOUVEAU_SVM_BIND_TARGET_BITS 32
#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
/*
* Below is use to validate ioctl argument, userspace can also use it to make
* sure that no bit are set beyond known fields for a given kernel version.
*/
#define NOUVEAU_SVM_BIND_VALID_BITS 48
#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
/*
* NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
* result: number of page successfuly migrate to the target memory.
*/
#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
/*
* NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
*/
#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
#define DRM_IOCTL_NOUVEAU_GET_ZCULL_INFO DRM_IOR (DRM_COMMAND_BASE + DRM_NOUVEAU_GET_ZCULL_INFO, struct drm_nouveau_get_zcull_info)
#if defined(__cplusplus)
}
#endif
#endif /* __NOUVEAU_DRM_H__ */
linux-7.2.3/include/uapi/drm/nova_drm.h
+101
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@@ -0,0 +1,101 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NOVA_DRM_H__
#define __NOVA_DRM_H__
#include "drm.h"
/* DISCLAIMER: Do not use, this is not a stable uAPI.
*
* This uAPI serves only testing purposes as long as this driver is still in
* development. It is required to implement and test infrastructure which is
* upstreamed in the context of this driver. See also [1].
*
* [1] https://lore.kernel.org/dri-devel/Zfsj0_tb-0-tNrJy@cassiopeiae/T/#u
*/
#if defined(__cplusplus)
extern "C" {
#endif
/*
* NOVA_GETPARAM_VRAM_BAR_SIZE
*
* Query the VRAM BAR size in bytes.
*/
#define NOVA_GETPARAM_VRAM_BAR_SIZE 0x1
/**
* struct drm_nova_getparam - query GPU and driver metadata
*/
struct drm_nova_getparam {
/**
* @param: The identifier of the parameter to query.
*/
__u64 param;
/**
* @value: The value for the specified parameter.
*/
__u64 value;
};
/**
* struct drm_nova_gem_create - create a new DRM GEM object
*/
struct drm_nova_gem_create {
/**
* @handle: The handle of the new DRM GEM object.
*/
__u32 handle;
/**
* @pad: 32 bit padding, should be 0.
*/
__u32 pad;
/**
* @size: The size of the new DRM GEM object.
*/
__u64 size;
};
/**
* struct drm_nova_gem_info - query DRM GEM object metadata
*/
struct drm_nova_gem_info {
/**
* @handle: The handle of the DRM GEM object to query.
*/
__u32 handle;
/**
* @pad: 32 bit padding, should be 0.
*/
__u32 pad;
/**
* @size: The size of the DRM GEM obejct.
*/
__u64 size;
};
#define DRM_NOVA_GETPARAM 0x00
#define DRM_NOVA_GEM_CREATE 0x01
#define DRM_NOVA_GEM_INFO 0x02
/* Note: this is an enum so that it can be resolved by Rust bindgen. */
enum {
DRM_IOCTL_NOVA_GETPARAM = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GETPARAM,
struct drm_nova_getparam),
DRM_IOCTL_NOVA_GEM_CREATE = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_CREATE,
struct drm_nova_gem_create),
DRM_IOCTL_NOVA_GEM_INFO = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_INFO,
struct drm_nova_gem_info),
};
#if defined(__cplusplus)
}
#endif
#endif /* __NOVA_DRM_H__ */
linux-7.2.3/include/uapi/drm/omap_drm.h
+126
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@@ -0,0 +1,126 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* include/uapi/drm/omap_drm.h
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __OMAP_DRM_H__
#define __OMAP_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*/
#define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */
struct drm_omap_param {
__u64 param; /* in */
__u64 value; /* in (set_param), out (get_param) */
};
/* Scanout buffer, consumable by DSS */
#define OMAP_BO_SCANOUT 0x00000001
/* Buffer CPU caching mode: cached, write-combining or uncached. */
#define OMAP_BO_CACHED 0x00000000
#define OMAP_BO_WC 0x00000002
#define OMAP_BO_UNCACHED 0x00000004
#define OMAP_BO_CACHE_MASK 0x00000006
/* Use TILER for the buffer. The TILER container unit can be 8, 16 or 32 bits. */
#define OMAP_BO_TILED_8 0x00000100
#define OMAP_BO_TILED_16 0x00000200
#define OMAP_BO_TILED_32 0x00000300
#define OMAP_BO_TILED_MASK 0x00000f00
union omap_gem_size {
__u32 bytes; /* (for non-tiled formats) */
struct {
__u16 width;
__u16 height;
} tiled; /* (for tiled formats) */
};
struct drm_omap_gem_new {
union omap_gem_size size; /* in */
__u32 flags; /* in */
__u32 handle; /* out */
__u32 __pad;
};
/* mask of operations: */
enum omap_gem_op {
OMAP_GEM_READ = 0x01,
OMAP_GEM_WRITE = 0x02,
};
struct drm_omap_gem_cpu_prep {
__u32 handle; /* buffer handle (in) */
__u32 op; /* mask of omap_gem_op (in) */
};
struct drm_omap_gem_cpu_fini {
__u32 handle; /* buffer handle (in) */
__u32 op; /* mask of omap_gem_op (in) */
/* TODO maybe here we pass down info about what regions are touched
* by sw so we can be clever about cache ops? For now a placeholder,
* set to zero and we just do full buffer flush..
*/
__u32 nregions;
__u32 __pad;
};
struct drm_omap_gem_info {
__u32 handle; /* buffer handle (in) */
__u32 pad;
__u64 offset; /* mmap offset (out) */
/* note: in case of tiled buffers, the user virtual size can be
* different from the physical size (ie. how many pages are needed
* to back the object) which is returned in DRM_IOCTL_GEM_OPEN..
* This size here is the one that should be used if you want to
* mmap() the buffer:
*/
__u32 size; /* virtual size for mmap'ing (out) */
__u32 __pad;
};
#define DRM_OMAP_GET_PARAM 0x00
#define DRM_OMAP_SET_PARAM 0x01
#define DRM_OMAP_GEM_NEW 0x03
#define DRM_OMAP_GEM_CPU_PREP 0x04 /* Deprecated, to be removed */
#define DRM_OMAP_GEM_CPU_FINI 0x05 /* Deprecated, to be removed */
#define DRM_OMAP_GEM_INFO 0x06
#define DRM_OMAP_NUM_IOCTLS 0x07
#define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param)
#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param)
#define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new)
#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep)
#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini)
#define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info)
#if defined(__cplusplus)
}
#endif
#endif /* __OMAP_DRM_H__ */
linux-7.2.3/include/uapi/drm/panfrost_drm.h
+476
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@@ -0,0 +1,476 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2014-2018 Broadcom
* Copyright © 2019 Collabora ltd.
*/
#ifndef _PANFROST_DRM_H_
#define _PANFROST_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_PANFROST_SUBMIT 0x00
#define DRM_PANFROST_WAIT_BO 0x01
#define DRM_PANFROST_CREATE_BO 0x02
#define DRM_PANFROST_MMAP_BO 0x03
#define DRM_PANFROST_GET_PARAM 0x04
#define DRM_PANFROST_GET_BO_OFFSET 0x05
#define DRM_PANFROST_PERFCNT_ENABLE 0x06
#define DRM_PANFROST_PERFCNT_DUMP 0x07
#define DRM_PANFROST_MADVISE 0x08
#define DRM_PANFROST_SET_LABEL_BO 0x09
#define DRM_PANFROST_JM_CTX_CREATE 0x0a
#define DRM_PANFROST_JM_CTX_DESTROY 0x0b
#define DRM_PANFROST_SYNC_BO 0x0c
#define DRM_PANFROST_QUERY_BO_INFO 0x0d
#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
#define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo)
#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo)
#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param)
#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
#define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise)
#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)
#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)
#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)
#define DRM_IOCTL_PANFROST_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SYNC_BO, struct drm_panfrost_sync_bo)
#define DRM_IOCTL_PANFROST_QUERY_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_QUERY_BO_INFO, struct drm_panfrost_query_bo_info)
/*
* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
* param is set to true.
* All these ioctl(s) are subject to deprecation, so please don't rely on
* them for anything but debugging purpose.
*/
#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable)
#define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump)
#define PANFROST_JD_REQ_FS (1 << 0)
#define PANFROST_JD_REQ_CYCLE_COUNT (1 << 1)
/**
* struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D
* engine.
*
* This asks the kernel to have the GPU execute a render command list.
*/
struct drm_panfrost_submit {
/**
* @jc: Address to GPU mapping of job descriptor
*/
__u64 jc;
/**
* @in_syncs: An optional array of sync objects to wait on
* before starting this job.
*/
__u64 in_syncs;
/**
* @in_sync_count: Number of sync objects to wait on before
* starting this job.
*/
__u32 in_sync_count;
/**
* @out_sync: An optional sync object to place the completion fence in.
*/
__u32 out_sync;
/**
* @bo_handles: Pointer to a u32 array of the BOs that are
* referenced by the job.
*/
__u64 bo_handles;
/**
* @bo_handle_count: Number of BO handles passed in (size is
* that times 4).
*/
__u32 bo_handle_count;
/**
* @requirements: A combination of PANFROST_JD_REQ_*
*/
__u32 requirements;
/**
* @jm_ctx_handle: JM context handle. Zero if you want to use the
* default context.
*/
__u32 jm_ctx_handle;
/**
* @pad: Padding field. Must be zero.
*/
__u32 pad;
};
/**
* struct drm_panfrost_wait_bo - ioctl argument for waiting for
* completion of the last DRM_PANFROST_SUBMIT on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_panfrost_wait_bo {
/**
* @handle: Handle for the object to wait for.
*/
__u32 handle;
/**
* @pad: Padding, must be zero-filled.
*/
__u32 pad;
/**
* @timeout_ns: absolute number of nanoseconds to wait.
*/
__s64 timeout_ns;
};
/* Valid flags to pass to drm_panfrost_create_bo.
* PANFROST_BO_WB_MMAP can't be set if PANFROST_BO_HEAP is.
*/
#define PANFROST_BO_NOEXEC 1
#define PANFROST_BO_HEAP 2
#define PANFROST_BO_WB_MMAP 4
/**
* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
*
* The flags argument is a bit mask of PANFROST_BO_* flags.
*/
struct drm_panfrost_create_bo {
/**
* @size: size of shmem/BO area to create (bytes)
*/
__u32 size;
/**
* @flags: see PANFROST_BO_* flags
*/
__u32 flags;
/**
* @handle: Returned GEM handle for the BO.
*/
__u32 handle;
/**
* @pad: Padding, must be zero-filled.
*/
__u32 pad;
/**
* @offset: Returned offset for the BO in the GPU address space.
* This offset is private to the DRM fd and is valid for the
* lifetime of the GEM handle.
*
* This offset value will always be nonzero, since various HW
* units treat 0 specially.
*/
__u64 offset;
};
/**
* struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_panfrost_mmap_bo {
/**
* @handle: Handle for the object being mapped.
*/
__u32 handle;
/**
* @flags: currently not used (should be zero)
*/
__u32 flags;
/**
* @offset: offset into the drm node to use for subsequent mmap call.
*/
__u64 offset;
};
enum drm_panfrost_param {
DRM_PANFROST_PARAM_GPU_PROD_ID,
DRM_PANFROST_PARAM_GPU_REVISION,
DRM_PANFROST_PARAM_SHADER_PRESENT,
DRM_PANFROST_PARAM_TILER_PRESENT,
DRM_PANFROST_PARAM_L2_PRESENT,
DRM_PANFROST_PARAM_STACK_PRESENT,
DRM_PANFROST_PARAM_AS_PRESENT,
DRM_PANFROST_PARAM_JS_PRESENT,
DRM_PANFROST_PARAM_L2_FEATURES,
DRM_PANFROST_PARAM_CORE_FEATURES,
DRM_PANFROST_PARAM_TILER_FEATURES,
DRM_PANFROST_PARAM_MEM_FEATURES,
DRM_PANFROST_PARAM_MMU_FEATURES,
DRM_PANFROST_PARAM_THREAD_FEATURES,
DRM_PANFROST_PARAM_MAX_THREADS,
DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ,
DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ,
DRM_PANFROST_PARAM_COHERENCY_FEATURES,
DRM_PANFROST_PARAM_TEXTURE_FEATURES0,
DRM_PANFROST_PARAM_TEXTURE_FEATURES1,
DRM_PANFROST_PARAM_TEXTURE_FEATURES2,
DRM_PANFROST_PARAM_TEXTURE_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES0,
DRM_PANFROST_PARAM_JS_FEATURES1,
DRM_PANFROST_PARAM_JS_FEATURES2,
DRM_PANFROST_PARAM_JS_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES4,
DRM_PANFROST_PARAM_JS_FEATURES5,
DRM_PANFROST_PARAM_JS_FEATURES6,
DRM_PANFROST_PARAM_JS_FEATURES7,
DRM_PANFROST_PARAM_JS_FEATURES8,
DRM_PANFROST_PARAM_JS_FEATURES9,
DRM_PANFROST_PARAM_JS_FEATURES10,
DRM_PANFROST_PARAM_JS_FEATURES11,
DRM_PANFROST_PARAM_JS_FEATURES12,
DRM_PANFROST_PARAM_JS_FEATURES13,
DRM_PANFROST_PARAM_JS_FEATURES14,
DRM_PANFROST_PARAM_JS_FEATURES15,
DRM_PANFROST_PARAM_NR_CORE_GROUPS,
DRM_PANFROST_PARAM_THREAD_TLS_ALLOC,
DRM_PANFROST_PARAM_AFBC_FEATURES,
DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,
DRM_PANFROST_PARAM_SELECTED_COHERENCY,
};
enum drm_panfrost_gpu_coherency {
DRM_PANFROST_GPU_COHERENCY_ACE_LITE = 0,
DRM_PANFROST_GPU_COHERENCY_ACE = 1,
DRM_PANFROST_GPU_COHERENCY_NONE = 31,
};
struct drm_panfrost_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
/*
* Returns the offset for the BO in the GPU address space for this DRM fd.
* This is the same value returned by drm_panfrost_create_bo, if that was called
* from this DRM fd.
*/
struct drm_panfrost_get_bo_offset {
__u32 handle;
__u32 pad;
__u64 offset;
};
struct drm_panfrost_perfcnt_enable {
__u32 enable;
/*
* On bifrost we have 2 sets of counters, this parameter defines the
* one to track.
*/
__u32 counterset;
};
struct drm_panfrost_perfcnt_dump {
__u64 buf_ptr;
};
/* madvise provides a way to tell the kernel in case a buffers contents
* can be discarded under memory pressure, which is useful for userspace
* bo cache where we want to optimistically hold on to buffer allocate
* and potential mmap, but allow the pages to be discarded under memory
* pressure.
*
* Typical usage would involve madvise(DONTNEED) when buffer enters BO
* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
* In the WILLNEED case, 'retained' indicates to userspace whether the
* backing pages still exist.
*/
#define PANFROST_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
#define PANFROST_MADV_DONTNEED 1 /* backing pages not needed */
struct drm_panfrost_madvise {
__u32 handle; /* in, GEM handle */
__u32 madv; /* in, PANFROST_MADV_x */
__u32 retained; /* out, whether backing store still exists */
};
/**
* struct drm_panfrost_set_label_bo - ioctl argument for labelling Panfrost BOs.
*/
struct drm_panfrost_set_label_bo {
/**
* @handle: Handle of the buffer object to label.
*/
__u32 handle;
/**
* @pad: Must be zero.
*/
__u32 pad;
/**
* @label: User pointer to a NUL-terminated string
*
* Length cannot be greater than 4096.
* NULL is permitted and means clear the label.
*/
__u64 label;
};
/* Valid flags to pass to drm_panfrost_bo_sync_op */
#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH 0
#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE 1
/**
* struct drm_panthor_bo_flush_map_op - BO map sync op
*/
struct drm_panfrost_bo_sync_op {
/** @handle: Handle of the buffer object to sync. */
__u32 handle;
/** @type: Type of sync operation. */
__u32 type;
/**
* @offset: Offset into the BO at which the sync range starts.
*
* This will be rounded down to the nearest cache line as needed.
*/
__u32 offset;
/**
* @size: Size of the range to sync
*
* @size + @offset will be rounded up to the nearest cache line as
* needed.
*/
__u32 size;
};
/**
* struct drm_panfrost_sync_bo - ioctl argument for syncing BO maps
*/
struct drm_panfrost_sync_bo {
/** Array of struct drm_panfrost_bo_sync_op */
__u64 ops;
/** Number of BO sync ops */
__u32 op_count;
__u32 pad;
};
/** BO comes from a different subsystem. */
#define DRM_PANFROST_BO_IS_IMPORTED (1 << 0)
struct drm_panfrost_query_bo_info {
/** Handle of the object being queried. */
__u32 handle;
/** Extra flags that are not coming from the BO_CREATE ioctl(). */
__u32 extra_flags;
/** Flags passed at creation time. */
__u32 create_flags;
/** Will be zero on return. */
__u32 pad;
};
/* Definitions for coredump decoding in user space */
#define PANFROSTDUMP_MAJOR 1
#define PANFROSTDUMP_MINOR 0
#define PANFROSTDUMP_MAGIC 0x464E4150 /* PANF */
#define PANFROSTDUMP_BUF_REG 0
#define PANFROSTDUMP_BUF_BOMAP (PANFROSTDUMP_BUF_REG + 1)
#define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1)
#define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1)
/*
* This structure is the native endianness of the dumping machine, tools can
* detect the endianness by looking at the value in 'magic'.
*/
struct panfrost_dump_object_header {
__u32 magic;
__u32 type;
__u32 file_size;
__u32 file_offset;
union {
struct {
__u64 jc;
__u32 gpu_id;
__u32 major;
__u32 minor;
__u64 nbos;
} reghdr;
struct {
__u32 valid;
__u64 iova;
__u32 data[2];
} bomap;
/*
* Force same size in case we want to expand the header
* with new fields and also keep it 512-byte aligned
*/
__u32 sizer[496];
};
};
/* Registers object, an array of these */
struct panfrost_dump_registers {
__u32 reg;
__u32 value;
};
enum drm_panfrost_jm_ctx_priority {
/**
* @PANFROST_JM_CTX_PRIORITY_LOW: Low priority context.
*/
PANFROST_JM_CTX_PRIORITY_LOW = 0,
/**
* @PANFROST_JM_CTX_PRIORITY_MEDIUM: Medium priority context.
*/
PANFROST_JM_CTX_PRIORITY_MEDIUM,
/**
* @PANFROST_JM_CTX_PRIORITY_HIGH: High priority context.
*
* Requires CAP_SYS_NICE or DRM_MASTER.
*/
PANFROST_JM_CTX_PRIORITY_HIGH,
};
struct drm_panfrost_jm_ctx_create {
/**
* @handle: Handle of the created JM context
*/
__u32 handle;
/**
* @priority: Context priority (see enum drm_panfrost_jm_ctx_priority).
*/
__u32 priority;
};
struct drm_panfrost_jm_ctx_destroy {
/**
* @handle: Handle of the JM context to destroy.
*
* Must be a valid context handle returned by DRM_IOCTL_PANTHOR_JM_CTX_CREATE.
*/
__u32 handle;
/**
* @pad: Padding field, must be zero.
*/
__u32 pad;
};
#if defined(__cplusplus)
}
#endif
#endif /* _PANFROST_DRM_H_ */
linux-7.2.3/include/uapi/drm/panthor_drm.h
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linux-7.2.3/include/uapi/drm/pvr_drm.h
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linux-7.2.3/include/uapi/drm/qaic_accel.h
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@@ -0,0 +1,399 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef QAIC_ACCEL_H_
#define QAIC_ACCEL_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* The length(4K) includes len and count fields of qaic_manage_msg */
#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
/* semaphore flags */
#define QAIC_SEM_INSYNCFENCE 2
#define QAIC_SEM_OUTSYNCFENCE 1
/* Semaphore commands */
#define QAIC_SEM_NOP 0
#define QAIC_SEM_INIT 1
#define QAIC_SEM_INC 2
#define QAIC_SEM_DEC 3
#define QAIC_SEM_WAIT_EQUAL 4
#define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */
#define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */
#define QAIC_TRANS_UNDEFINED 0
#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
#define QAIC_TRANS_PASSTHROUGH_TO_USR 2
#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
#define QAIC_TRANS_DMA_XFER_FROM_USR 5
#define QAIC_TRANS_DMA_XFER_TO_DEV 6
#define QAIC_TRANS_ACTIVATE_FROM_USR 7
#define QAIC_TRANS_ACTIVATE_FROM_DEV 8
#define QAIC_TRANS_ACTIVATE_TO_DEV 9
#define QAIC_TRANS_DEACTIVATE_FROM_USR 10
#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
#define QAIC_TRANS_STATUS_FROM_USR 12
#define QAIC_TRANS_STATUS_TO_USR 13
#define QAIC_TRANS_STATUS_FROM_DEV 14
#define QAIC_TRANS_STATUS_TO_DEV 15
#define QAIC_TRANS_TERMINATE_FROM_DEV 16
#define QAIC_TRANS_TERMINATE_TO_DEV 17
#define QAIC_TRANS_DMA_XFER_CONT 18
#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
/**
* struct qaic_manage_trans_hdr - Header for a transaction in a manage message.
* @type: In. Identifies this transaction. See QAIC_TRANS_* defines.
* @len: In. Length of this transaction, including this header.
*/
struct qaic_manage_trans_hdr {
__u32 type;
__u32 len;
};
/**
* struct qaic_manage_trans_passthrough - Defines a passthrough transaction.
* @hdr: In. Header to identify this transaction.
* @data: In. Payload of this transaction. Opaque to the driver. Userspace must
* encode in little endian and align/pad to 64-bit.
*/
struct qaic_manage_trans_passthrough {
struct qaic_manage_trans_hdr hdr;
__u8 data[];
};
/**
* struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction.
* @hdr: In. Header to identify this transaction.
* @tag: In. Identified this transfer in other transactions. Opaque to the
* driver.
* @pad: Structure padding.
* @addr: In. Address of the data to DMA to the device.
* @size: In. Length of the data to DMA to the device.
*/
struct qaic_manage_trans_dma_xfer {
struct qaic_manage_trans_hdr hdr;
__u32 tag;
__u32 pad;
__u64 addr;
__u64 size;
};
/**
* struct qaic_manage_trans_activate_to_dev - Defines an activate request.
* @hdr: In. Header to identify this transaction.
* @queue_size: In. Number of elements for DBC request and response queues.
* @eventfd: Unused.
* @options: In. Device specific options for this activate.
* @pad: Structure padding. Must be 0.
*/
struct qaic_manage_trans_activate_to_dev {
struct qaic_manage_trans_hdr hdr;
__u32 queue_size;
__u32 eventfd;
__u32 options;
__u32 pad;
};
/**
* struct qaic_manage_trans_activate_from_dev - Defines an activate response.
* @hdr: Out. Header to identify this transaction.
* @status: Out. Return code of the request from the device.
* @dbc_id: Out. Id of the assigned DBC for successful request.
* @options: Out. Device specific options for this activate.
*/
struct qaic_manage_trans_activate_from_dev {
struct qaic_manage_trans_hdr hdr;
__u32 status;
__u32 dbc_id;
__u64 options;
};
/**
* struct qaic_manage_trans_deactivate - Defines a deactivate request.
* @hdr: In. Header to identify this transaction.
* @dbc_id: In. Id of assigned DBC.
* @pad: Structure padding. Must be 0.
*/
struct qaic_manage_trans_deactivate {
struct qaic_manage_trans_hdr hdr;
__u32 dbc_id;
__u32 pad;
};
/**
* struct qaic_manage_trans_status_to_dev - Defines a status request.
* @hdr: In. Header to identify this transaction.
*/
struct qaic_manage_trans_status_to_dev {
struct qaic_manage_trans_hdr hdr;
};
/**
* struct qaic_manage_trans_status_from_dev - Defines a status response.
* @hdr: Out. Header to identify this transaction.
* @major: Out. NNC protocol version major number.
* @minor: Out. NNC protocol version minor number.
* @status: Out. Return code from device.
* @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required.
*/
struct qaic_manage_trans_status_from_dev {
struct qaic_manage_trans_hdr hdr;
__u16 major;
__u16 minor;
__u32 status;
__u64 status_flags;
};
/**
* struct qaic_manage_msg - Defines a message to the device.
* @len: In. Length of all the transactions contained within this message.
* @count: In. Number of transactions in this message.
* @data: In. Address to an array where the transactions can be found.
*/
struct qaic_manage_msg {
__u32 len;
__u32 count;
__u64 data;
};
/**
* struct qaic_create_bo - Defines a request to create a buffer object.
* @size: In. Size of the buffer in bytes.
* @handle: Out. GEM handle for the BO.
* @pad: Structure padding. Must be 0.
*/
struct qaic_create_bo {
__u64 size;
__u32 handle;
__u32 pad;
};
/**
* struct qaic_mmap_bo - Defines a request to prepare a BO for mmap().
* @handle: In. Handle of the GEM BO to prepare for mmap().
* @pad: Structure padding. Must be 0.
* @offset: Out. Offset value to provide to mmap().
*/
struct qaic_mmap_bo {
__u32 handle;
__u32 pad;
__u64 offset;
};
/**
* struct qaic_sem - Defines a semaphore command for a BO slice.
* @val: In. Only lower 12 bits are valid.
* @index: In. Only lower 5 bits are valid.
* @presync: In. 1 if presync operation, 0 if postsync.
* @cmd: In. One of QAIC_SEM_*.
* @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE
* @pad: Structure padding. Must be 0.
*/
struct qaic_sem {
__u16 val;
__u8 index;
__u8 presync;
__u8 cmd;
__u8 flags;
__u16 pad;
};
/**
* struct qaic_attach_slice_entry - Defines a single BO slice.
* @size: In. Size of this slice in bytes.
* @sem0: In. Semaphore command 0. Must be 0 is not valid.
* @sem1: In. Semaphore command 1. Must be 0 is not valid.
* @sem2: In. Semaphore command 2. Must be 0 is not valid.
* @sem3: In. Semaphore command 3. Must be 0 is not valid.
* @dev_addr: In. Device address this slice pushes to or pulls from.
* @db_addr: In. Address of the doorbell to ring.
* @db_data: In. Data to write to the doorbell.
* @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for
* inactive doorbells.
* @offset: In. Start of this slice as an offset from the start of the BO.
*/
struct qaic_attach_slice_entry {
__u64 size;
struct qaic_sem sem0;
struct qaic_sem sem1;
struct qaic_sem sem2;
struct qaic_sem sem3;
__u64 dev_addr;
__u64 db_addr;
__u32 db_data;
__u32 db_len;
__u64 offset;
};
/**
* struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices.
* @count: In. Number of slices for this BO.
* @dbc_id: In. Associate the sliced BO with this DBC.
* @handle: In. GEM handle of the BO to slice.
* @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE
* @size: Deprecated. This value is ignored and size of @handle is used instead.
*/
struct qaic_attach_slice_hdr {
__u32 count;
__u32 dbc_id;
__u32 handle;
__u32 dir;
__u64 size;
};
/**
* struct qaic_attach_slice - Defines a set of BO slices.
* @hdr: In. Metadata of the set of slices.
* @data: In. Pointer to an array containing the slice definitions.
*/
struct qaic_attach_slice {
struct qaic_attach_slice_hdr hdr;
__u64 data;
};
/**
* struct qaic_execute_entry - Defines a BO to submit to the device.
* @handle: In. GEM handle of the BO to commit to the device.
* @dir: In. Direction of data. 1 = to device, 2 = from device.
*/
struct qaic_execute_entry {
__u32 handle;
__u32 dir;
};
/**
* struct qaic_partial_execute_entry - Defines a BO to resize and submit.
* @handle: In. GEM handle of the BO to commit to the device.
* @dir: In. Direction of data. 1 = to device, 2 = from device.
* @resize: In. New size of the BO. Must be <= the original BO size.
* @resize as 0 would be interpreted as no DMA transfer is
* involved.
*/
struct qaic_partial_execute_entry {
__u32 handle;
__u32 dir;
__u64 resize;
};
/**
* struct qaic_execute_hdr - Defines metadata for BO submission.
* @count: In. Number of BOs to submit.
* @dbc_id: In. DBC to submit the BOs on.
*/
struct qaic_execute_hdr {
__u32 count;
__u32 dbc_id;
};
/**
* struct qaic_execute - Defines a list of BOs to submit to the device.
* @hdr: In. BO list metadata.
* @data: In. Pointer to an array of BOs to submit.
*/
struct qaic_execute {
struct qaic_execute_hdr hdr;
__u64 data;
};
/**
* struct qaic_wait - Defines a blocking wait for BO execution.
* @handle: In. GEM handle of the BO to wait on.
* @timeout: In. Maximum time in ms to wait for the BO.
* @dbc_id: In. DBC the BO is submitted to.
* @pad: Structure padding. Must be 0.
*/
struct qaic_wait {
__u32 handle;
__u32 timeout;
__u32 dbc_id;
__u32 pad;
};
/**
* struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info.
* @count: In. Number of BOs requested.
* @pad: Structure padding. Must be 0.
* @dbc_id: In. DBC the BO are associated with.
*/
struct qaic_perf_stats_hdr {
__u16 count;
__u16 pad;
__u32 dbc_id;
};
/**
* struct qaic_perf_stats - Defines a request for getting BO perf info.
* @hdr: In. Request metadata
* @data: In. Pointer to array of stats structures that will receive the data.
*/
struct qaic_perf_stats {
struct qaic_perf_stats_hdr hdr;
__u64 data;
};
/**
* struct qaic_perf_stats_entry - Defines a BO perf info.
* @handle: In. GEM handle of the BO to get perf stats for.
* @queue_level_before: Out. Number of elements in the queue before this BO
* was submitted.
* @num_queue_element: Out. Number of elements added to the queue to submit
* this BO.
* @submit_latency_us: Out. Time taken by the driver to submit this BO.
* @device_latency_us: Out. Time taken by the device to execute this BO.
* @pad: Structure padding. Must be 0.
*/
struct qaic_perf_stats_entry {
__u32 handle;
__u32 queue_level_before;
__u32 num_queue_element;
__u32 submit_latency_us;
__u32 device_latency_us;
__u32 pad;
};
/**
* struct qaic_detach_slice - Detaches slicing configuration from BO.
* @handle: In. GEM handle of the BO to detach slicing configuration.
* @pad: Structure padding. Must be 0.
*/
struct qaic_detach_slice {
__u32 handle;
__u32 pad;
};
#define DRM_QAIC_MANAGE 0x00
#define DRM_QAIC_CREATE_BO 0x01
#define DRM_QAIC_MMAP_BO 0x02
#define DRM_QAIC_ATTACH_SLICE_BO 0x03
#define DRM_QAIC_EXECUTE_BO 0x04
#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
#define DRM_QAIC_WAIT_BO 0x06
#define DRM_QAIC_PERF_STATS_BO 0x07
#define DRM_QAIC_DETACH_SLICE_BO 0x08
#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
#define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice)
#if defined(__cplusplus)
}
#endif
#endif /* QAIC_ACCEL_H_ */
linux-7.2.3/include/uapi/drm/qxl_drm.h
+158
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@@ -0,0 +1,158 @@
/*
* Copyright 2013 Red Hat
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef QXL_DRM_H
#define QXL_DRM_H
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*
* Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
* compatibility Keep fields aligned to their size
*/
#define QXL_GEM_DOMAIN_CPU 0
#define QXL_GEM_DOMAIN_VRAM 1
#define QXL_GEM_DOMAIN_SURFACE 2
#define DRM_QXL_ALLOC 0x00
#define DRM_QXL_MAP 0x01
#define DRM_QXL_EXECBUFFER 0x02
#define DRM_QXL_UPDATE_AREA 0x03
#define DRM_QXL_GETPARAM 0x04
#define DRM_QXL_CLIENTCAP 0x05
#define DRM_QXL_ALLOC_SURF 0x06
struct drm_qxl_alloc {
__u32 size;
__u32 handle; /* 0 is an invalid handle */
};
struct drm_qxl_map {
__u64 offset; /* use for mmap system call */
__u32 handle;
__u32 pad;
};
/*
* dest is the bo we are writing the relocation into
* src is bo we are relocating.
* *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
* src_offset)
*/
#define QXL_RELOC_TYPE_BO 1
#define QXL_RELOC_TYPE_SURF 2
struct drm_qxl_reloc {
__u64 src_offset; /* offset into src_handle or src buffer */
__u64 dst_offset; /* offset in dest handle */
__u32 src_handle; /* dest handle to compute address from */
__u32 dst_handle; /* 0 if to command buffer */
__u32 reloc_type;
__u32 pad;
};
struct drm_qxl_command {
__u64 command; /* void* */
__u64 relocs; /* struct drm_qxl_reloc* */
__u32 type;
__u32 command_size;
__u32 relocs_num;
__u32 pad;
};
struct drm_qxl_execbuffer {
__u32 flags; /* for future use */
__u32 commands_num;
__u64 commands; /* struct drm_qxl_command* */
};
struct drm_qxl_update_area {
__u32 handle;
__u32 top;
__u32 left;
__u32 bottom;
__u32 right;
__u32 pad;
};
#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
#define QXL_PARAM_MAX_RELOCS 2
struct drm_qxl_getparam {
__u64 param;
__u64 value;
};
/* these are one bit values */
struct drm_qxl_clientcap {
__u32 index;
__u32 pad;
};
struct drm_qxl_alloc_surf {
__u32 format;
__u32 width;
__u32 height;
__s32 stride;
__u32 handle;
__u32 pad;
};
#define DRM_IOCTL_QXL_ALLOC \
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
#define DRM_IOCTL_QXL_MAP \
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
#define DRM_IOCTL_QXL_EXECBUFFER \
DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
struct drm_qxl_execbuffer)
#define DRM_IOCTL_QXL_UPDATE_AREA \
DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
struct drm_qxl_update_area)
#define DRM_IOCTL_QXL_GETPARAM \
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
struct drm_qxl_getparam)
#define DRM_IOCTL_QXL_CLIENTCAP \
DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
struct drm_qxl_clientcap)
#define DRM_IOCTL_QXL_ALLOC_SURF \
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
struct drm_qxl_alloc_surf)
#if defined(__cplusplus)
}
#endif
#endif
linux-7.2.3/include/uapi/drm/radeon_drm.h
+1078
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linux-7.2.3/include/uapi/drm/rocket_accel.h
+192
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/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2024 Tomeu Vizoso
*/
#ifndef __DRM_UAPI_ROCKET_ACCEL_H__
#define __DRM_UAPI_ROCKET_ACCEL_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_ROCKET_CREATE_BO 0x00
#define DRM_ROCKET_SUBMIT 0x01
#define DRM_ROCKET_PREP_BO 0x02
#define DRM_ROCKET_FINI_BO 0x03
#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
#define DRM_IOCTL_ROCKET_PREP_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo)
#define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_FINI_BO, struct drm_rocket_fini_bo)
/**
* struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
*
*/
struct drm_rocket_create_bo {
/**
* @size: Input: Size of the requested BO.
*/
__u32 size;
/**
* @handle: Output: GEM handle for the BO.
*/
__u32 handle;
/**
* @dma_address: Output: DMA address for the BO in the NPU address
* space. This address is private to the DRM fd and is valid for
* the lifetime of the GEM handle.
*/
__u64 dma_address;
/**
* @offset: Output: Offset into the drm node to use for subsequent
* mmap call.
*/
__u64 offset;
};
/**
* struct drm_rocket_prep_bo - ioctl argument for starting CPU ownership of the BO.
*
* Takes care of waiting for any NPU jobs that might still use the NPU and performs cache
* synchronization.
*/
struct drm_rocket_prep_bo {
/**
* @handle: Input: GEM handle of the buffer object.
*/
__u32 handle;
/**
* @reserved: Reserved, must be zero.
*/
__u32 reserved;
/**
* @timeout_ns: Input: Amount of time to wait for NPU jobs.
*/
__s64 timeout_ns;
};
/**
* struct drm_rocket_fini_bo - ioctl argument for finishing CPU ownership of the BO.
*
* Synchronize caches for NPU access.
*/
struct drm_rocket_fini_bo {
/**
* @handle: Input: GEM handle of the buffer object.
*/
__u32 handle;
/**
* @reserved: Reserved, must be zero.
*/
__u32 reserved;
};
/**
* struct drm_rocket_task - A task to be run on the NPU
*
* A task is the smallest unit of work that can be run on the NPU.
*/
struct drm_rocket_task {
/**
* @regcmd: Input: DMA address to NPU mapping of register command buffer
*/
__u32 regcmd;
/**
* @regcmd_count: Input: Number of commands in the register command
* buffer
*/
__u32 regcmd_count;
};
/**
* struct drm_rocket_job - A job to be run on the NPU
*
* The kernel will schedule the execution of this job taking into account its
* dependencies with other jobs. All tasks in the same job will be executed
* sequentially on the same core, to benefit from memory residency in SRAM.
*/
struct drm_rocket_job {
/**
* @tasks: Input: Pointer to an array of struct drm_rocket_task.
*/
__u64 tasks;
/**
* @in_bo_handles: Input: Pointer to a u32 array of the BOs that
* are read by the job.
*/
__u64 in_bo_handles;
/**
* @out_bo_handles: Input: Pointer to a u32 array of the BOs that
* are written to by the job.
*/
__u64 out_bo_handles;
/**
* @task_count: Input: Number of tasks passed in.
*/
__u32 task_count;
/**
* @task_struct_size: Input: Size in bytes of the structs in the
* @tasks field.
*/
__u32 task_struct_size;
/**
* @in_bo_handle_count: Input: Number of input BO handles passed in
* (size is that times 4).
*/
__u32 in_bo_handle_count;
/**
* @out_bo_handle_count: Input: Number of output BO handles passed in
* (size is that times 4).
*/
__u32 out_bo_handle_count;
};
/**
* struct drm_rocket_submit - ioctl argument for submitting commands to the NPU.
*
* The kernel will schedule the execution of these jobs in dependency order.
*/
struct drm_rocket_submit {
/**
* @jobs: Input: Pointer to an array of struct drm_rocket_job.
*/
__u64 jobs;
/**
* @job_count: Input: Number of jobs passed in.
*/
__u32 job_count;
/**
* @job_struct_size: Input: Size in bytes of the structs in the
* @jobs field.
*/
__u32 job_struct_size;
/**
* @reserved: Reserved, must be zero.
*/
__u64 reserved;
};
#if defined(__cplusplus)
}
#endif
#endif /* __DRM_UAPI_ROCKET_ACCEL_H__ */
linux-7.2.3/include/uapi/drm/tegra_drm.h
+1076
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linux-7.2.3/include/uapi/drm/v3d_drm.h
+793
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/*
* Copyright © 2014-2018 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _V3D_DRM_H_
#define _V3D_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_V3D_SUBMIT_CL 0x00
#define DRM_V3D_WAIT_BO 0x01
#define DRM_V3D_CREATE_BO 0x02
#define DRM_V3D_MMAP_BO 0x03
#define DRM_V3D_GET_PARAM 0x04
#define DRM_V3D_GET_BO_OFFSET 0x05
#define DRM_V3D_SUBMIT_TFU 0x06
#define DRM_V3D_SUBMIT_CSD 0x07
#define DRM_V3D_PERFMON_CREATE 0x08
#define DRM_V3D_PERFMON_DESTROY 0x09
#define DRM_V3D_PERFMON_GET_VALUES 0x0a
#define DRM_V3D_SUBMIT_CPU 0x0b
#define DRM_V3D_PERFMON_GET_COUNTER 0x0c
#define DRM_V3D_PERFMON_SET_GLOBAL 0x0d
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
struct drm_v3d_perfmon_create)
#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
struct drm_v3d_perfmon_destroy)
#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
struct drm_v3d_perfmon_get_values)
#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)
#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \
struct drm_v3d_perfmon_get_counter)
#define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, \
struct drm_v3d_perfmon_set_global)
#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
#define DRM_V3D_SUBMIT_EXTENSION 0x02
/* struct drm_v3d_extension - ioctl extensions
*
* Linked-list of generic extensions where the id identify which struct is
* pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
* the extension type.
*/
struct drm_v3d_extension {
__u64 next;
__u32 id;
#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
#define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02
#define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03
#define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04
#define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05
#define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06
#define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07
__u32 flags; /* mbz */
};
/* struct drm_v3d_sem - wait/signal semaphore
*
* If binary semaphore, it only takes syncobj handle and ignores flags and
* point fields. Point is defined for timeline syncobj feature.
*/
struct drm_v3d_sem {
__u32 handle; /* syncobj */
/* rsv below, for future uses */
__u32 flags;
__u64 point; /* for timeline sem support */
__u64 mbz[2]; /* must be zero, rsv */
};
/* Enum for each of the V3D queues. */
enum v3d_queue {
V3D_BIN,
V3D_RENDER,
V3D_TFU,
V3D_CSD,
V3D_CACHE_CLEAN,
V3D_CPU,
};
/**
* struct drm_v3d_multi_sync - ioctl extension to add support multiples
* syncobjs for commands submission.
*
* When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
* this extension to define wait and signal dependencies, instead of single
* in/out sync entries on submitting commands. The field flags is used to
* determine the stage to set wait dependencies.
*/
struct drm_v3d_multi_sync {
struct drm_v3d_extension base;
/* Array of wait and signal semaphores */
__u64 in_syncs;
__u64 out_syncs;
/* Number of entries */
__u32 in_sync_count;
__u32 out_sync_count;
/* set the stage (v3d_queue) to sync */
__u32 wait_stage;
__u32 pad; /* mbz */
};
/**
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
* engine.
*
* This asks the kernel to have the GPU execute an optional binner
* command list, and a render command list.
*
* The L1T, slice, L2C, L2T, and GCA caches will be flushed before
* each CL executes. The VCD cache should be flushed (if necessary)
* by the submitted CLs. The TLB writes are guaranteed to have been
* flushed by the time the render done IRQ happens, which is the
* trigger for out_sync. Any dirtying of cachelines by the job (only
* possible using TMU writes) must be flushed by the caller using the
* DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
*/
struct drm_v3d_submit_cl {
/* Pointer to the binner command list.
*
* This is the first set of commands executed, which runs the
* coordinate shader to determine where primitives land on the screen,
* then writes out the state updates and draw calls necessary per tile
* to the tile allocation BO.
*
* This BCL will block on any previous BCL submitted on the
* same FD, but not on any RCL or BCLs submitted by other
* clients -- that is left up to the submitter to control
* using in_sync_bcl if necessary.
*/
__u32 bcl_start;
/** End address of the BCL (first byte after the BCL) */
__u32 bcl_end;
/* Offset of the render command list.
*
* This is the second set of commands executed, which will either
* execute the tiles that have been set up by the BCL, or a fixed set
* of tiles (in the case of RCL-only blits).
*
* This RCL will block on this submit's BCL, and any previous
* RCL submitted on the same FD, but not on any RCL or BCLs
* submitted by other clients -- that is left up to the
* submitter to control using in_sync_rcl if necessary.
*/
__u32 rcl_start;
/** End address of the RCL (first byte after the RCL) */
__u32 rcl_end;
/** An optional sync object to wait on before starting the BCL. */
__u32 in_sync_bcl;
/** An optional sync object to wait on before starting the RCL. */
__u32 in_sync_rcl;
/** An optional sync object to place the completion fence in. */
__u32 out_sync;
/* Offset of the tile alloc memory
*
* This is optional on V3D 3.3 (where the CL can set the value) but
* required on V3D 4.1.
*/
__u32 qma;
/** Size of the tile alloc memory. */
__u32 qms;
/** Offset of the tile state data array. */
__u32 qts;
/* Pointer to a u32 array of the BOs that are referenced by the job.
*/
__u64 bo_handles;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/* DRM_V3D_SUBMIT_* properties */
__u32 flags;
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmon_id;
__u32 pad;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
};
/**
* struct drm_v3d_wait_bo - ioctl argument for waiting for
* completion of the last DRM_V3D_SUBMIT_CL on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_v3d_wait_bo {
__u32 handle;
__u32 pad;
__u64 timeout_ns;
};
/**
* struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_v3d_create_bo {
__u32 size;
__u32 flags;
/** Returned GEM handle for the BO. */
__u32 handle;
/**
* Returned offset for the BO in the V3D address space. This offset
* is private to the DRM fd and is valid for the lifetime of the GEM
* handle.
*
* This offset value will always be nonzero, since various HW
* units treat 0 specially.
*/
__u32 offset;
};
/**
* struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_v3d_mmap_bo {
/** Handle for the object being mapped. */
__u32 handle;
__u32 flags;
/** offset into the drm node to use for subsequent mmap call. */
__u64 offset;
};
enum drm_v3d_param {
DRM_V3D_PARAM_V3D_UIFCFG,
DRM_V3D_PARAM_V3D_HUB_IDENT1,
DRM_V3D_PARAM_V3D_HUB_IDENT2,
DRM_V3D_PARAM_V3D_HUB_IDENT3,
DRM_V3D_PARAM_V3D_CORE0_IDENT0,
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
DRM_V3D_PARAM_SUPPORTS_TFU,
DRM_V3D_PARAM_SUPPORTS_CSD,
DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
DRM_V3D_PARAM_SUPPORTS_PERFMON,
DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE,
DRM_V3D_PARAM_MAX_PERF_COUNTERS,
DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES,
DRM_V3D_PARAM_GLOBAL_RESET_COUNTER,
DRM_V3D_PARAM_CONTEXT_RESET_COUNTER,
};
struct drm_v3d_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
/**
* Returns the offset for the BO in the V3D address space for this DRM fd.
* This is the same value returned by drm_v3d_create_bo, if that was called
* from this DRM fd.
*/
struct drm_v3d_get_bo_offset {
__u32 handle;
__u32 offset;
};
struct drm_v3d_submit_tfu {
__u32 icfg;
__u32 iia;
__u32 iis;
__u32 ica;
__u32 iua;
__u32 ioa;
__u32 ios;
__u32 coef[4];
/* First handle is the output BO, following are other inputs.
* 0 for unused.
*/
__u32 bo_handles[4];
/* sync object to block on before running the TFU job. Each TFU
* job will execute in the order submitted to its FD. Synchronization
* against rendering jobs requires using sync objects.
*/
__u32 in_sync;
/* Sync object to signal when the TFU job is done. */
__u32 out_sync;
__u32 flags;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
struct {
__u32 ioc;
__u32 pad;
} v71;
};
/* Submits a compute shader for dispatch. This job will block on any
* previous compute shaders submitted on this fd, and any other
* synchronization must be performed with in_sync/out_sync.
*/
struct drm_v3d_submit_csd {
__u32 cfg[7];
__u32 coef[4];
/* Pointer to a u32 array of the BOs that are referenced by the job.
*/
__u64 bo_handles;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/* sync object to block on before running the CSD job. Each
* CSD job will execute in the order submitted to its FD.
* Synchronization against rendering/TFU jobs or CSD from
* other fds requires using sync objects.
*/
__u32 in_sync;
/* Sync object to signal when the CSD job is done. */
__u32 out_sync;
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmon_id;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
__u32 flags;
__u32 pad;
};
/**
* struct drm_v3d_indirect_csd - ioctl extension for the CPU job to create an
* indirect CSD
*
* When an extension of DRM_V3D_EXT_ID_CPU_INDIRECT_CSD id is defined, it
* points to this extension to define a indirect CSD submission. It creates a
* CPU job linked to a CSD job. The CPU job waits for the indirect CSD
* dependencies and, once they are signaled, it updates the CSD job config
* before allowing the CSD job execution.
*/
struct drm_v3d_indirect_csd {
struct drm_v3d_extension base;
/* Indirect CSD */
struct drm_v3d_submit_csd submit;
/* Handle of the indirect BO, that should be also attached to the
* indirect CSD.
*/
__u32 indirect;
/* Offset within the BO where the workgroup counts are stored */
__u32 offset;
/* Workgroups size */
__u32 wg_size;
/* Indices of the uniforms with the workgroup dispatch counts
* in the uniform stream. If the uniform rewrite is not needed,
* the offset must be 0xffffffff.
*/
__u32 wg_uniform_offsets[3];
};
/**
* struct drm_v3d_timestamp_query - ioctl extension for the CPU job to calculate
* a timestamp query
*
* When an extension DRM_V3D_EXT_ID_TIMESTAMP_QUERY is defined, it points to
* this extension to define a timestamp query submission. This CPU job will
* calculate the timestamp query and update the query value within the
* timestamp BO. Moreover, it will signal the timestamp syncobj to indicate
* query availability.
*/
struct drm_v3d_timestamp_query {
struct drm_v3d_extension base;
/* Array of queries' offsets within the timestamp BO for their value */
__u64 offsets;
/* Array of timestamp's syncobjs to indicate its availability */
__u64 syncs;
/* Number of queries */
__u32 count;
/* mbz */
__u32 pad;
};
/**
* struct drm_v3d_reset_timestamp_query - ioctl extension for the CPU job to
* reset timestamp queries
*
* When an extension DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY is defined, it
* points to this extension to define a reset timestamp submission. This CPU
* job will reset the timestamp queries based on value offset of the first
* query. Moreover, it will reset the timestamp syncobj to reset query
* availability.
*/
struct drm_v3d_reset_timestamp_query {
struct drm_v3d_extension base;
/* Array of timestamp's syncobjs to indicate its availability */
__u64 syncs;
/* Offset of the first query within the timestamp BO for its value */
__u32 offset;
/* Number of queries */
__u32 count;
};
/**
* struct drm_v3d_copy_timestamp_query - ioctl extension for the CPU job to copy
* query results to a buffer
*
* When an extension DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY is defined, it
* points to this extension to define a copy timestamp query submission. This
* CPU job will copy the timestamp queries results to a BO with the offset
* and stride defined in the extension.
*/
struct drm_v3d_copy_timestamp_query {
struct drm_v3d_extension base;
/* Define if should write to buffer using 64 or 32 bits */
__u8 do_64bit;
/* Define if it can write to buffer even if the query is not available */
__u8 do_partial;
/* Define if it should write availability bit to buffer */
__u8 availability_bit;
/* mbz */
__u8 pad;
/* Offset of the buffer in the BO */
__u32 offset;
/* Stride of the buffer in the BO */
__u32 stride;
/* Number of queries */
__u32 count;
/* Array of queries' offsets within the timestamp BO for their value */
__u64 offsets;
/* Array of timestamp's syncobjs to indicate its availability */
__u64 syncs;
};
/**
* struct drm_v3d_reset_performance_query - ioctl extension for the CPU job to
* reset performance queries
*
* When an extension DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY is defined, it
* points to this extension to define a reset performance submission. This CPU
* job will reset the performance queries by resetting the values of the
* performance monitors. Moreover, it will reset the syncobj to reset query
* availability.
*/
struct drm_v3d_reset_performance_query {
struct drm_v3d_extension base;
/* Array of performance queries's syncobjs to indicate its availability */
__u64 syncs;
/* Number of queries */
__u32 count;
/* Number of performance monitors */
__u32 nperfmons;
/* Array of u64 user-pointers that point to an array of kperfmon_ids */
__u64 kperfmon_ids;
};
/**
* struct drm_v3d_copy_performance_query - ioctl extension for the CPU job to copy
* performance query results to a buffer
*
* When an extension DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY is defined, it
* points to this extension to define a copy performance query submission. This
* CPU job will copy the performance queries results to a BO with the offset
* and stride defined in the extension.
*/
struct drm_v3d_copy_performance_query {
struct drm_v3d_extension base;
/* Define if should write to buffer using 64 or 32 bits */
__u8 do_64bit;
/* Define if it can write to buffer even if the query is not available */
__u8 do_partial;
/* Define if it should write availability bit to buffer */
__u8 availability_bit;
/* mbz */
__u8 pad;
/* Offset of the buffer in the BO */
__u32 offset;
/* Stride of the buffer in the BO */
__u32 stride;
/* Number of performance monitors */
__u32 nperfmons;
/* Number of performance counters related to this query pool */
__u32 ncounters;
/* Number of queries */
__u32 count;
/* Array of performance queries's syncobjs to indicate its availability */
__u64 syncs;
/* Array of u64 user-pointers that point to an array of kperfmon_ids */
__u64 kperfmon_ids;
};
struct drm_v3d_submit_cpu {
/* Pointer to a u32 array of the BOs that are referenced by the job.
*
* For DRM_V3D_EXT_ID_CPU_INDIRECT_CSD, it must contain only one BO,
* that contains the workgroup counts.
*
* For DRM_V3D_EXT_ID_TIMESTAMP_QUERY, it must contain only one BO,
* that will contain the timestamp.
*
* For DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY, it must contain only
* one BO, that contains the timestamp.
*
* For DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY, it must contain two
* BOs. The first is the BO where the timestamp queries will be written
* to. The second is the BO that contains the timestamp.
*
* For DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY, it must contain no
* BOs.
*
* For DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY, it must contain one
* BO, where the performance queries will be written.
*/
__u64 bo_handles;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
__u32 flags;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
};
/* The performance counters index represented by this enum are deprecated and
* must no longer be used. These counters are only valid for V3D 4.2.
*
* In order to check for performance counter information,
* use DRM_IOCTL_V3D_PERFMON_GET_COUNTER.
*
* Don't use V3D_PERFCNT_NUM to retrieve the maximum number of performance
* counters. You should use DRM_IOCTL_V3D_GET_PARAM with the following
* parameter: DRM_V3D_PARAM_MAX_PERF_COUNTERS.
*/
enum {
V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
V3D_PERFCNT_FEP_VALID_PRIMS,
V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
V3D_PERFCNT_FEP_VALID_QUADS,
V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
V3D_PERFCNT_TLB_QUADS_ZERO_COV,
V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
V3D_PERFCNT_TLB_QUADS_WRITTEN,
V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
V3D_PERFCNT_PTB_PRIM_CLIP,
V3D_PERFCNT_PTB_PRIM_REV,
V3D_PERFCNT_QPU_IDLE_CYCLES,
V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
V3D_PERFCNT_QPU_IC_HIT,
V3D_PERFCNT_QPU_IC_MISS,
V3D_PERFCNT_QPU_UC_HIT,
V3D_PERFCNT_QPU_UC_MISS,
V3D_PERFCNT_TMU_TCACHE_ACCESS,
V3D_PERFCNT_TMU_TCACHE_MISS,
V3D_PERFCNT_VPM_VDW_STALL,
V3D_PERFCNT_VPM_VCD_STALL,
V3D_PERFCNT_BIN_ACTIVE,
V3D_PERFCNT_RDR_ACTIVE,
V3D_PERFCNT_L2T_HITS,
V3D_PERFCNT_L2T_MISSES,
V3D_PERFCNT_CYCLE_COUNT,
V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
V3D_PERFCNT_PTB_PRIMS_BINNED,
V3D_PERFCNT_AXI_WRITES_WATCH_0,
V3D_PERFCNT_AXI_READS_WATCH_0,
V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
V3D_PERFCNT_AXI_WRITES_WATCH_1,
V3D_PERFCNT_AXI_READS_WATCH_1,
V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
V3D_PERFCNT_TLB_PARTIAL_QUADS,
V3D_PERFCNT_TMU_CONFIG_ACCESSES,
V3D_PERFCNT_L2T_NO_ID_STALL,
V3D_PERFCNT_L2T_COM_QUE_STALL,
V3D_PERFCNT_L2T_TMU_WRITES,
V3D_PERFCNT_TMU_ACTIVE_CYCLES,
V3D_PERFCNT_TMU_STALLED_CYCLES,
V3D_PERFCNT_CLE_ACTIVE,
V3D_PERFCNT_L2T_TMU_READS,
V3D_PERFCNT_L2T_CLE_READS,
V3D_PERFCNT_L2T_VCD_READS,
V3D_PERFCNT_L2T_TMUCFG_READS,
V3D_PERFCNT_L2T_SLC0_READS,
V3D_PERFCNT_L2T_SLC1_READS,
V3D_PERFCNT_L2T_SLC2_READS,
V3D_PERFCNT_L2T_TMU_W_MISSES,
V3D_PERFCNT_L2T_TMU_R_MISSES,
V3D_PERFCNT_L2T_CLE_MISSES,
V3D_PERFCNT_L2T_VCD_MISSES,
V3D_PERFCNT_L2T_TMUCFG_MISSES,
V3D_PERFCNT_L2T_SLC0_MISSES,
V3D_PERFCNT_L2T_SLC1_MISSES,
V3D_PERFCNT_L2T_SLC2_MISSES,
V3D_PERFCNT_CORE_MEM_WRITES,
V3D_PERFCNT_L2T_MEM_WRITES,
V3D_PERFCNT_PTB_MEM_WRITES,
V3D_PERFCNT_TLB_MEM_WRITES,
V3D_PERFCNT_CORE_MEM_READS,
V3D_PERFCNT_L2T_MEM_READS,
V3D_PERFCNT_PTB_MEM_READS,
V3D_PERFCNT_PSE_MEM_READS,
V3D_PERFCNT_TLB_MEM_READS,
V3D_PERFCNT_GMP_MEM_READS,
V3D_PERFCNT_PTB_W_MEM_WORDS,
V3D_PERFCNT_TLB_W_MEM_WORDS,
V3D_PERFCNT_PSE_R_MEM_WORDS,
V3D_PERFCNT_TLB_R_MEM_WORDS,
V3D_PERFCNT_TMU_MRU_HITS,
V3D_PERFCNT_COMPUTE_ACTIVE,
V3D_PERFCNT_NUM,
};
#define DRM_V3D_MAX_PERF_COUNTERS 32
struct drm_v3d_perfmon_create {
__u32 id;
__u32 ncounters;
__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
};
struct drm_v3d_perfmon_destroy {
__u32 id;
};
/*
* Returns the values of the performance counters tracked by this
* perfmon (as an array of ncounters u64 values).
*
* No implicit synchronization is performed, so the user has to
* guarantee that any jobs using this perfmon have already been
* completed (probably by blocking on the seqno returned by the
* last exec that used the perfmon).
*/
struct drm_v3d_perfmon_get_values {
__u32 id;
__u32 pad;
__u64 values_ptr;
};
#define DRM_V3D_PERFCNT_MAX_NAME 64
#define DRM_V3D_PERFCNT_MAX_CATEGORY 32
#define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256
/**
* struct drm_v3d_perfmon_get_counter - ioctl to get the description of a
* performance counter
*
* As userspace needs to retrieve information about the performance counters
* available, this IOCTL allows users to get information about a performance
* counter (name, category and description).
*/
struct drm_v3d_perfmon_get_counter {
/*
* Counter ID
*
* Must be smaller than the maximum number of performance counters, which
* can be retrieve through DRM_V3D_PARAM_MAX_PERF_COUNTERS.
*/
__u8 counter;
/* Name of the counter */
__u8 name[DRM_V3D_PERFCNT_MAX_NAME];
/* Category of the counter */
__u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY];
/* Description of the counter */
__u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION];
/* mbz */
__u8 reserved[7];
};
#define DRM_V3D_PERFMON_CLEAR_GLOBAL 0x0001
/**
* struct drm_v3d_perfmon_set_global - ioctl to define a global performance
* monitor
*
* The global performance monitor will be used for all jobs. If a global
* performance monitor is defined, jobs with a self-defined performance
* monitor won't be allowed.
*/
struct drm_v3d_perfmon_set_global {
__u32 flags;
__u32 id;
};
#if defined(__cplusplus)
}
#endif
#endif /* _V3D_DRM_H_ */
linux-7.2.3/include/uapi/drm/vc4_drm.h
+442
View File
@@ -0,0 +1,442 @@
/*
* Copyright © 2014-2015 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _UAPI_VC4_DRM_H_
#define _UAPI_VC4_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_VC4_SUBMIT_CL 0x00
#define DRM_VC4_WAIT_SEQNO 0x01
#define DRM_VC4_WAIT_BO 0x02
#define DRM_VC4_CREATE_BO 0x03
#define DRM_VC4_MMAP_BO 0x04
#define DRM_VC4_CREATE_SHADER_BO 0x05
#define DRM_VC4_GET_HANG_STATE 0x06
#define DRM_VC4_GET_PARAM 0x07
#define DRM_VC4_SET_TILING 0x08
#define DRM_VC4_GET_TILING 0x09
#define DRM_VC4_LABEL_BO 0x0a
#define DRM_VC4_GEM_MADVISE 0x0b
#define DRM_VC4_PERFMON_CREATE 0x0c
#define DRM_VC4_PERFMON_DESTROY 0x0d
#define DRM_VC4_PERFMON_GET_VALUES 0x0e
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
struct drm_vc4_submit_rcl_surface {
__u32 hindex; /* Handle index, or ~0 if not present. */
__u32 offset; /* Offset to start of buffer. */
/*
* Bits for either render config (color_write) or load/store packet.
* Bits should all be 0 for MSAA load/stores.
*/
__u16 bits;
#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
__u16 flags;
};
/**
* struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
* engine.
*
* Drivers typically use GPU BOs to store batchbuffers / command lists and
* their associated state. However, because the VC4 lacks an MMU, we have to
* do validation of memory accesses by the GPU commands. If we were to store
* our commands in BOs, we'd need to do uncached readback from them to do the
* validation process, which is too expensive. Instead, userspace accumulates
* commands and associated state in plain memory, then the kernel copies the
* data to its own address space, and then validates and stores it in a GPU
* BO.
*/
struct drm_vc4_submit_cl {
/* Pointer to the binner command list.
*
* This is the first set of commands executed, which runs the
* coordinate shader to determine where primitives land on the screen,
* then writes out the state updates and draw calls necessary per tile
* to the tile allocation BO.
*/
__u64 bin_cl;
/* Pointer to the shader records.
*
* Shader records are the structures read by the hardware that contain
* pointers to uniforms, shaders, and vertex attributes. The
* reference to the shader record has enough information to determine
* how many pointers are necessary (fixed number for shaders/uniforms,
* and an attribute count), so those BO indices into bo_handles are
* just stored as __u32s before each shader record passed in.
*/
__u64 shader_rec;
/* Pointer to uniform data and texture handles for the textures
* referenced by the shader.
*
* For each shader state record, there is a set of uniform data in the
* order referenced by the record (FS, VS, then CS). Each set of
* uniform data has a __u32 index into bo_handles per texture
* sample operation, in the order the QPU_W_TMUn_S writes appear in
* the program. Following the texture BO handle indices is the actual
* uniform data.
*
* The individual uniform state blocks don't have sizes passed in,
* because the kernel has to determine the sizes anyway during shader
* code validation.
*/
__u64 uniforms;
__u64 bo_handles;
/* Size in bytes of the binner command list. */
__u32 bin_cl_size;
/* Size in bytes of the set of shader records. */
__u32 shader_rec_size;
/* Number of shader records.
*
* This could just be computed from the contents of shader_records and
* the address bits of references to them from the bin CL, but it
* keeps the kernel from having to resize some allocations it makes.
*/
__u32 shader_rec_count;
/* Size in bytes of the uniform state. */
__u32 uniforms_size;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/* RCL setup: */
__u16 width;
__u16 height;
__u8 min_x_tile;
__u8 min_y_tile;
__u8 max_x_tile;
__u8 max_y_tile;
struct drm_vc4_submit_rcl_surface color_read;
struct drm_vc4_submit_rcl_surface color_write;
struct drm_vc4_submit_rcl_surface zs_read;
struct drm_vc4_submit_rcl_surface zs_write;
struct drm_vc4_submit_rcl_surface msaa_color_write;
struct drm_vc4_submit_rcl_surface msaa_zs_write;
__u32 clear_color[2];
__u32 clear_z;
__u8 clear_s;
__u32 pad:24;
#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
/* By default, the kernel gets to choose the order that the tiles are
* rendered in. If this is set, then the tiles will be rendered in a
* raster order, with the right-to-left vs left-to-right and
* top-to-bottom vs bottom-to-top dictated by
* VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
* blits to be implemented using the 3D engine.
*/
#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
__u32 flags;
/* Returned value of the seqno of this render job (for the
* wait ioctl).
*/
__u64 seqno;
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmonid;
/* Syncobj handle to wait on. If set, processing of this render job
* will not start until the syncobj is signaled. 0 means ignore.
*/
__u32 in_sync;
/* Syncobj handle to export fence to. If set, the fence in the syncobj
* will be replaced with a fence that signals upon completion of this
* render job. 0 means ignore.
*/
__u32 out_sync;
__u32 pad2;
};
/**
* struct drm_vc4_wait_seqno - ioctl argument for waiting for
* DRM_VC4_SUBMIT_CL completion using its returned seqno.
*
* timeout_ns is the timeout in nanoseconds, where "0" means "don't
* block, just return the status."
*/
struct drm_vc4_wait_seqno {
__u64 seqno;
__u64 timeout_ns;
};
/**
* struct drm_vc4_wait_bo - ioctl argument for waiting for
* completion of the last DRM_VC4_SUBMIT_CL on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_vc4_wait_bo {
__u32 handle;
__u32 pad;
__u64 timeout_ns;
};
/**
* struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_vc4_create_bo {
__u32 size;
__u32 flags;
/** Returned GEM handle for the BO. */
__u32 handle;
__u32 pad;
};
/**
* struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_vc4_mmap_bo {
/** Handle for the object being mapped. */
__u32 handle;
__u32 flags;
/** offset into the drm node to use for subsequent mmap call. */
__u64 offset;
};
/**
* struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
* shader BOs.
*
* Since allowing a shader to be overwritten while it's also being
* executed from would allow privlege escalation, shaders must be
* created using this ioctl, and they can't be mmapped later.
*/
struct drm_vc4_create_shader_bo {
/* Size of the data argument. */
__u32 size;
/* Flags, currently must be 0. */
__u32 flags;
/* Pointer to the data. */
__u64 data;
/** Returned GEM handle for the BO. */
__u32 handle;
/* Pad, must be 0. */
__u32 pad;
};
struct drm_vc4_get_hang_state_bo {
__u32 handle;
__u32 paddr;
__u32 size;
__u32 pad;
};
/**
* struct drm_vc4_hang_state - ioctl argument for collecting state
* from a GPU hang for analysis.
*/
struct drm_vc4_get_hang_state {
/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
__u64 bo;
/**
* On input, the size of the bo array. Output is the number
* of bos to be returned.
*/
__u32 bo_count;
__u32 start_bin, start_render;
__u32 ct0ca, ct0ea;
__u32 ct1ca, ct1ea;
__u32 ct0cs, ct1cs;
__u32 ct0ra0, ct1ra0;
__u32 bpca, bpcs;
__u32 bpoa, bpos;
__u32 vpmbase;
__u32 dbge;
__u32 fdbgo;
__u32 fdbgb;
__u32 fdbgr;
__u32 fdbgs;
__u32 errstat;
/* Pad that we may save more registers into in the future. */
__u32 pad[16];
};
#define DRM_VC4_PARAM_V3D_IDENT0 0
#define DRM_VC4_PARAM_V3D_IDENT1 1
#define DRM_VC4_PARAM_V3D_IDENT2 2
#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7
#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8
struct drm_vc4_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
struct drm_vc4_get_tiling {
__u32 handle;
__u32 flags;
__u64 modifier;
};
struct drm_vc4_set_tiling {
__u32 handle;
__u32 flags;
__u64 modifier;
};
/**
* struct drm_vc4_label_bo - Attach a name to a BO for debug purposes.
*/
struct drm_vc4_label_bo {
__u32 handle;
__u32 len;
__u64 name;
};
/*
* States prefixed with '__' are internal states and cannot be passed to the
* DRM_IOCTL_VC4_GEM_MADVISE ioctl.
*/
#define VC4_MADV_WILLNEED 0
#define VC4_MADV_DONTNEED 1
#define __VC4_MADV_PURGED 2
#define __VC4_MADV_NOTSUPP 3
struct drm_vc4_gem_madvise {
__u32 handle;
__u32 madv;
__u32 retained;
__u32 pad;
};
enum {
VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
VC4_PERFCNT_FEP_CLIPPED_QUADS,
VC4_PERFCNT_FEP_VALID_QUADS,
VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
VC4_PERFCNT_PSE_PRIMS_REVERSED,
VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
VC4_PERFCNT_NUM_EVENTS,
};
#define DRM_VC4_MAX_PERF_COUNTERS 16
struct drm_vc4_perfmon_create {
__u32 id;
__u32 ncounters;
__u8 events[DRM_VC4_MAX_PERF_COUNTERS];
};
struct drm_vc4_perfmon_destroy {
__u32 id;
};
/*
* Returns the values of the performance counters tracked by this
* perfmon (as an array of ncounters u64 values).
*
* No implicit synchronization is performed, so the user has to
* guarantee that any jobs using this perfmon have already been
* completed (probably by blocking on the seqno returned by the
* last exec that used the perfmon).
*/
struct drm_vc4_perfmon_get_values {
__u32 id;
__u64 values_ptr;
};
#if defined(__cplusplus)
}
#endif
#endif /* _UAPI_VC4_DRM_H_ */
linux-7.2.3/include/uapi/drm/vgem_drm.h
+62
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@@ -0,0 +1,62 @@
/*
* Copyright 2016 Intel Corporation
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _UAPI_VGEM_DRM_H_
#define _UAPI_VGEM_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*/
#define DRM_VGEM_FENCE_ATTACH 0x1
#define DRM_VGEM_FENCE_SIGNAL 0x2
#define DRM_IOCTL_VGEM_FENCE_ATTACH DRM_IOWR( DRM_COMMAND_BASE + DRM_VGEM_FENCE_ATTACH, struct drm_vgem_fence_attach)
#define DRM_IOCTL_VGEM_FENCE_SIGNAL DRM_IOW( DRM_COMMAND_BASE + DRM_VGEM_FENCE_SIGNAL, struct drm_vgem_fence_signal)
struct drm_vgem_fence_attach {
__u32 handle;
__u32 flags;
#define VGEM_FENCE_WRITE 0x1
__u32 out_fence;
__u32 pad;
};
struct drm_vgem_fence_signal {
__u32 fence;
__u32 flags;
};
#if defined(__cplusplus)
}
#endif
#endif /* _UAPI_VGEM_DRM_H_ */
linux-7.2.3/include/uapi/drm/virtgpu_drm.h
+281
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/*
* Copyright 2013 Red Hat
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIRTGPU_DRM_H
#define VIRTGPU_DRM_H
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*
* Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
* compatibility Keep fields aligned to their size
*/
#define DRM_VIRTGPU_MAP 0x01
#define DRM_VIRTGPU_EXECBUFFER 0x02
#define DRM_VIRTGPU_GETPARAM 0x03
#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
#define DRM_VIRTGPU_RESOURCE_INFO 0x05
#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
#define DRM_VIRTGPU_WAIT 0x08
#define DRM_VIRTGPU_GET_CAPS 0x09
#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
#define VIRTGPU_EXECBUF_RING_IDX 0x04
#define VIRTGPU_EXECBUF_FLAGS (\
VIRTGPU_EXECBUF_FENCE_FD_IN |\
VIRTGPU_EXECBUF_FENCE_FD_OUT |\
VIRTGPU_EXECBUF_RING_IDX |\
0)
struct drm_virtgpu_map {
__u64 offset; /* use for mmap system call */
__u32 handle;
__u32 pad;
};
#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
0)
struct drm_virtgpu_execbuffer_syncobj {
__u32 handle;
__u32 flags;
__u64 point;
};
/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
struct drm_virtgpu_execbuffer {
__u32 flags;
__u32 size;
__u64 command; /* void* */
__u64 bo_handles;
__u32 num_bo_handles;
__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
__u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
__u32 num_in_syncobjs;
__u32 num_out_syncobjs;
__u64 in_syncobjs;
__u64 out_syncobjs;
};
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
#define VIRTGPU_PARAM_BLOB_ALIGNMENT 9 /* Device alignment requirements for blobs */
struct drm_virtgpu_getparam {
__u64 param;
__u64 value;
};
/* NO_BO flags? NO resource flag? */
/* resource flag for y_0_top */
struct drm_virtgpu_resource_create {
__u32 target;
__u32 format;
__u32 bind;
__u32 width;
__u32 height;
__u32 depth;
__u32 array_size;
__u32 last_level;
__u32 nr_samples;
__u32 flags;
__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
__u32 res_handle; /* returned by kernel */
__u32 size; /* validate transfer in the host */
__u32 stride; /* validate transfer in the host */
};
struct drm_virtgpu_resource_info {
__u32 bo_handle;
__u32 res_handle;
__u32 size;
__u32 blob_mem;
};
struct drm_virtgpu_3d_box {
__u32 x;
__u32 y;
__u32 z;
__u32 w;
__u32 h;
__u32 d;
};
struct drm_virtgpu_3d_transfer_to_host {
__u32 bo_handle;
struct drm_virtgpu_3d_box box;
__u32 level;
__u32 offset;
__u32 stride;
__u32 layer_stride;
};
struct drm_virtgpu_3d_transfer_from_host {
__u32 bo_handle;
struct drm_virtgpu_3d_box box;
__u32 level;
__u32 offset;
__u32 stride;
__u32 layer_stride;
};
#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
struct drm_virtgpu_3d_wait {
__u32 handle; /* 0 is an invalid handle */
__u32 flags;
};
#define VIRTGPU_DRM_CAPSET_VIRGL 1
#define VIRTGPU_DRM_CAPSET_VIRGL2 2
#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
#define VIRTGPU_DRM_CAPSET_VENUS 4
#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
#define VIRTGPU_DRM_CAPSET_DRM 6
struct drm_virtgpu_get_caps {
__u32 cap_set_id;
__u32 cap_set_ver;
__u64 addr;
__u32 size;
__u32 pad;
};
struct drm_virtgpu_resource_create_blob {
#define VIRTGPU_BLOB_MEM_GUEST 0x0001
#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
/* zero is invalid blob_mem */
__u32 blob_mem;
__u32 blob_flags;
__u32 bo_handle;
__u32 res_handle;
__u64 size;
/*
* for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
* VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
*/
__u32 pad;
__u32 cmd_size;
__u64 cmd;
__u64 blob_id;
#define DRM_VIRTGPU_BLOB_FLAG_HINT_DEFER_MAPPING 0x0001
__u32 blob_hints;
__u32 pad2;
};
#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME 0x0004
struct drm_virtgpu_context_set_param {
__u64 param;
__u64 value;
};
struct drm_virtgpu_context_init {
__u32 num_params;
__u32 pad;
/* pointer to drm_virtgpu_context_set_param array */
__u64 ctx_set_params;
};
/*
* Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
* effect. The event size is sizeof(drm_event), since there is no additional
* payload.
*/
#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
#define DRM_IOCTL_VIRTGPU_MAP \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
struct drm_virtgpu_execbuffer)
#define DRM_IOCTL_VIRTGPU_GETPARAM \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
struct drm_virtgpu_getparam)
#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
struct drm_virtgpu_resource_create)
#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
struct drm_virtgpu_resource_info)
#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
struct drm_virtgpu_3d_transfer_from_host)
#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
struct drm_virtgpu_3d_transfer_to_host)
#define DRM_IOCTL_VIRTGPU_WAIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
struct drm_virtgpu_3d_wait)
#define DRM_IOCTL_VIRTGPU_GET_CAPS \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
struct drm_virtgpu_get_caps)
#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
struct drm_virtgpu_resource_create_blob)
#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
struct drm_virtgpu_context_init)
#if defined(__cplusplus)
}
#endif
#endif
linux-7.2.3/include/uapi/drm/vmwgfx_drm.h
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linux-7.2.3/include/uapi/drm/xe_drm.h
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