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2026-09-06 12:53:21 -06:00
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linux-7.2.3/include/uapi/linux/media/amlogic/c3-isp-config.h
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Copyright (C) 2024 Amlogic, Inc. All rights reserved
*/
#ifndef _UAPI_C3_ISP_CONFIG_H_
#define _UAPI_C3_ISP_CONFIG_H_
#ifdef __KERNEL__
#include <linux/build_bug.h>
#endif /* __KERNEL__ */
#include <linux/types.h>
#include <linux/media/v4l2-isp.h>
/*
* Frames are split into zones of almost equal width and height - a zone is a
* rectangular tile of a frame. The metering blocks within the ISP collect
* aggregated statistics per zone.
*/
#define C3_ISP_AE_MAX_ZONES (17 * 15)
#define C3_ISP_AF_MAX_ZONES (17 * 15)
#define C3_ISP_AWB_MAX_ZONES (32 * 24)
/* The maximum number of point on the diagonal of the frame for statistics */
#define C3_ISP_AE_MAX_PT_NUM 18
#define C3_ISP_AF_MAX_PT_NUM 18
#define C3_ISP_AWB_MAX_PT_NUM 33
/**
* struct c3_isp_awb_zone_stats - AWB statistics of a zone
*
* AWB zone stats is aligned with 8 bytes
*
* @rg: the ratio of R / G in a zone
* @bg: the ratio of B / G in a zone
* @pixel_sum: the total number of pixels used in a zone
*/
struct c3_isp_awb_zone_stats {
__u16 rg;
__u16 bg;
__u32 pixel_sum;
};
/**
* struct c3_isp_awb_stats - Auto white balance statistics information.
*
* AWB statistical information of all zones.
*
* @stats: array of auto white balance statistics
*/
struct c3_isp_awb_stats {
struct c3_isp_awb_zone_stats stats[C3_ISP_AWB_MAX_ZONES];
} __attribute__((aligned(16)));
/**
* struct c3_isp_ae_zone_stats - AE statistics of a zone
*
* AE zone stats is aligned with 8 bytes.
* This is a 5-bin histogram and the total sum is normalized to 0xffff.
* So hist2 = 0xffff - (hist0 + hist1 + hist3 + hist4)
*
* @hist0: the global normalized pixel count for bin 0
* @hist1: the global normalized pixel count for bin 1
* @hist3: the global normalized pixel count for bin 3
* @hist4: the global normalized pixel count for bin 4
*/
struct c3_isp_ae_zone_stats {
__u16 hist0;
__u16 hist1;
__u16 hist3;
__u16 hist4;
};
/**
* struct c3_isp_ae_stats - Exposure statistics information
*
* AE statistical information consists of all blocks information and a 1024-bin
* histogram.
*
* @stats: array of auto exposure block statistics
* @reserved: undefined buffer space
* @hist: a 1024-bin histogram for the entire image
*/
struct c3_isp_ae_stats {
struct c3_isp_ae_zone_stats stats[C3_ISP_AE_MAX_ZONES];
__u32 reserved[2];
__u32 hist[1024];
} __attribute__((aligned(16)));
/**
* struct c3_isp_af_zone_stats - AF statistics of a zone
*
* AF zone stats is aligned with 8 bytes.
* The zonal accumulated contrast metrics are stored in floating point format
* with 16 bits mantissa and 5 or 6 bits exponent. Apart from contrast metrics
* we accumulate squared image and quartic image data over the zone.
*
* @i2_mat: the mantissa of zonal squared image pixel sum
* @i4_mat: the mantissa of zonal quartic image pixel sum
* @e4_mat: the mantissa of zonal multi-directional quartic edge sum
* @e4_exp: the exponent of zonal multi-directional quartic edge sum
* @i2_exp: the exponent of zonal squared image pixel sum
* @i4_exp: the exponent of zonal quartic image pixel sum
*/
struct c3_isp_af_zone_stats {
__u16 i2_mat;
__u16 i4_mat;
__u16 e4_mat;
__u16 e4_exp : 5;
__u16 i2_exp : 5;
__u16 i4_exp : 6;
};
/**
* struct c3_isp_af_stats - Auto Focus statistics information
*
* AF statistical information of each zone
*
* @stats: array of auto focus block statistics
* @reserved: undefined buffer space
*/
struct c3_isp_af_stats {
struct c3_isp_af_zone_stats stats[C3_ISP_AF_MAX_ZONES];
__u32 reserved[2];
} __attribute__((aligned(16)));
/**
* struct c3_isp_stats_info - V4L2_META_FMT_C3ISP_STATS
*
* Contains ISP statistics
*
* @awb: auto white balance stats
* @ae: auto exposure stats
* @af: auto focus stats
*/
struct c3_isp_stats_info {
struct c3_isp_awb_stats awb;
struct c3_isp_ae_stats ae;
struct c3_isp_af_stats af;
};
/**
* enum c3_isp_params_buffer_version - C3 ISP parameters block versioning
*
* @C3_ISP_PARAMS_BUFFER_V0: First version of C3 ISP parameters block
*/
enum c3_isp_params_buffer_version {
C3_ISP_PARAMS_BUFFER_V0 = V4L2_ISP_PARAMS_VERSION_V0,
};
/**
* enum c3_isp_params_block_type - Enumeration of C3 ISP parameter blocks
*
* Each block configures a specific processing block of the C3 ISP.
* The block type allows the driver to correctly interpret the parameters block
* data.
*
* @C3_ISP_PARAMS_BLOCK_AWB_GAINS: White balance gains
* @C3_ISP_PARAMS_BLOCK_AWB_CONFIG: AWB statistic format configuration for all
* blocks that control how stats are generated
* @C3_ISP_PARAMS_BLOCK_AE_CONFIG: AE statistic format configuration for all
* blocks that control how stats are generated
* @C3_ISP_PARAMS_BLOCK_AF_CONFIG: AF statistic format configuration for all
* blocks that control how stats are generated
* @C3_ISP_PARAMS_BLOCK_PST_GAMMA: post gamma parameters
* @C3_ISP_PARAMS_BLOCK_CCM: Color correction matrix parameters
* @C3_ISP_PARAMS_BLOCK_CSC: Color space conversion parameters
* @C3_ISP_PARAMS_BLOCK_BLC: Black level correction parameters
* @C3_ISP_PARAMS_BLOCK_SENTINEL: First non-valid block index
*/
enum c3_isp_params_block_type {
C3_ISP_PARAMS_BLOCK_AWB_GAINS,
C3_ISP_PARAMS_BLOCK_AWB_CONFIG,
C3_ISP_PARAMS_BLOCK_AE_CONFIG,
C3_ISP_PARAMS_BLOCK_AF_CONFIG,
C3_ISP_PARAMS_BLOCK_PST_GAMMA,
C3_ISP_PARAMS_BLOCK_CCM,
C3_ISP_PARAMS_BLOCK_CSC,
C3_ISP_PARAMS_BLOCK_BLC,
C3_ISP_PARAMS_BLOCK_SENTINEL
};
/* For backward compatibility */
#define C3_ISP_PARAMS_BLOCK_FL_DISABLE V4L2_ISP_PARAMS_FL_BLOCK_DISABLE
#define C3_ISP_PARAMS_BLOCK_FL_ENABLE V4L2_ISP_PARAMS_FL_BLOCK_ENABLE
/**
* c3_isp_params_block_header - C3 ISP parameter block header
*
* This structure represents the common part of all the ISP configuration
* blocks and is identical to :c:type:`v4l2_isp_params_block_header`.
*
* The type field is one of the values enumerated by
* :c:type:`c3_isp_params_block_type` and specifies how the data should be
* interpreted by the driver.
*
* The flags field is a bitmask of per-block flags C3_ISP_PARAMS_FL_*.
*/
#define c3_isp_params_block_header v4l2_isp_params_block_header
/**
* struct c3_isp_params_awb_gains - Gains for auto-white balance
*
* This struct allows users to configure the gains for white balance.
* There are four gain settings corresponding to each colour channel in
* the bayer domain. All of the gains are stored in Q4.8 format.
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_AWB_GAINS
* from :c:type:`c3_isp_params_block_type`
*
* @header: The C3 ISP parameters block header
* @gr_gain: Multiplier for Gr channel (Q4.8 format)
* @r_gain: Multiplier for R channel (Q4.8 format)
* @b_gain: Multiplier for B channel (Q4.8 format)
* @gb_gain: Multiplier for Gb channel (Q4.8 format)
*/
struct c3_isp_params_awb_gains {
struct c3_isp_params_block_header header;
__u16 gr_gain;
__u16 r_gain;
__u16 b_gain;
__u16 gb_gain;
} __attribute__((aligned(8)));
/**
* enum c3_isp_params_awb_tap_points - Tap points for the AWB statistics
* @C3_ISP_AWB_STATS_TAP_OFE: immediately after the optical frontend block
* @C3_ISP_AWB_STATS_TAP_GE: immediately after the green equal block
* @C3_ISP_AWB_STATS_TAP_BEFORE_WB: immediately before the white balance block
* @C3_ISP_AWB_STATS_TAP_AFTER_WB: immediately after the white balance block
*/
enum c3_isp_params_awb_tap_points {
C3_ISP_AWB_STATS_TAP_OFE = 0,
C3_ISP_AWB_STATS_TAP_GE,
C3_ISP_AWB_STATS_TAP_BEFORE_WB,
C3_ISP_AWB_STATS_TAP_AFTER_WB,
};
/**
* struct c3_isp_params_awb_config - Stats settings for auto-white balance
*
* This struct allows the configuration of the statistics generated for auto
* white balance.
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_AWB_CONFIG
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @tap_point: the tap point from enum c3_isp_params_awb_tap_point
* @satur_vald: AWB statistic over saturation control
* value: 0: disable, 1: enable
* @horiz_zones_num: active number of hotizontal zones [0..32]
* @vert_zones_num: active number of vertical zones [0..24]
* @rg_min: minimum R/G ratio (Q4.8 format)
* @rg_max: maximum R/G ratio (Q4.8 format)
* @bg_min: minimum B/G ratio (Q4.8 format)
* @bg_max: maximum B/G ratio (Q4.8 format)
* @rg_low: R/G ratio trim low (Q4.8 format)
* @rg_high: R/G ratio trim hight (Q4.8 format)
* @bg_low: B/G ratio trim low (Q4.8 format)
* @bg_high: B/G ratio trim high (Q4.8 format)
* @zone_weight: array of weights for AWB statistics zones [0..15]
* @horiz_coord: the horizontal coordinate of points on the diagonal [0..2888]
* @vert_coord: the vertical coordinate of points on the diagonal [0..2240]
*/
struct c3_isp_params_awb_config {
struct c3_isp_params_block_header header;
__u8 tap_point;
__u8 satur_vald;
__u8 horiz_zones_num;
__u8 vert_zones_num;
__u16 rg_min;
__u16 rg_max;
__u16 bg_min;
__u16 bg_max;
__u16 rg_low;
__u16 rg_high;
__u16 bg_low;
__u16 bg_high;
__u8 zone_weight[C3_ISP_AWB_MAX_ZONES];
__u16 horiz_coord[C3_ISP_AWB_MAX_PT_NUM];
__u16 vert_coord[C3_ISP_AWB_MAX_PT_NUM];
} __attribute__((aligned(8)));
/**
* enum c3_isp_params_ae_tap_points - Tap points for the AE statistics
* @C3_ISP_AE_STATS_TAP_GE: immediately after the green equal block
* @C3_ISP_AE_STATS_TAP_MLS: immediately after the mesh lens shading block
*/
enum c3_isp_params_ae_tap_points {
C3_ISP_AE_STATS_TAP_GE = 0,
C3_ISP_AE_STATS_TAP_MLS,
};
/**
* struct c3_isp_params_ae_config - Stats settings for auto-exposure
*
* This struct allows the configuration of the statistics generated for
* auto exposure.
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_AE_CONFIG
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @horiz_zones_num: active number of horizontal zones [0..17]
* @vert_zones_num: active number of vertical zones [0..15]
* @tap_point: the tap point from enum c3_isp_params_ae_tap_point
* @zone_weight: array of weights for AE statistics zones [0..15]
* @horiz_coord: the horizontal coordinate of points on the diagonal [0..2888]
* @vert_coord: the vertical coordinate of points on the diagonal [0..2240]
* @reserved: applications must zero this array
*/
struct c3_isp_params_ae_config {
struct c3_isp_params_block_header header;
__u8 tap_point;
__u8 horiz_zones_num;
__u8 vert_zones_num;
__u8 zone_weight[C3_ISP_AE_MAX_ZONES];
__u16 horiz_coord[C3_ISP_AE_MAX_PT_NUM];
__u16 vert_coord[C3_ISP_AE_MAX_PT_NUM];
__u16 reserved[3];
} __attribute__((aligned(8)));
/**
* enum c3_isp_params_af_tap_points - Tap points for the AF statistics
* @C3_ISP_AF_STATS_TAP_SNR: immediately after the spatial noise reduce block
* @C3_ISP_AF_STATS_TAP_DMS: immediately after the demosaic block
*/
enum c3_isp_params_af_tap_points {
C3_ISP_AF_STATS_TAP_SNR = 0,
C3_ISP_AF_STATS_TAP_DMS,
};
/**
* struct c3_isp_params_af_config - Stats settings for auto-focus
*
* This struct allows the configuration of the statistics generated for
* auto focus.
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_AF_CONFIG
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @tap_point: the tap point from enum c3_isp_params_af_tap_point
* @horiz_zones_num: active number of hotizontal zones [0..17]
* @vert_zones_num: active number of vertical zones [0..15]
* @reserved: applications must zero this array
* @horiz_coord: the horizontal coordinate of points on the diagonal [0..2888]
* @vert_coord: the vertical coordinate of points on the diagonal [0..2240]
*/
struct c3_isp_params_af_config {
struct c3_isp_params_block_header header;
__u8 tap_point;
__u8 horiz_zones_num;
__u8 vert_zones_num;
__u8 reserved[5];
__u16 horiz_coord[C3_ISP_AF_MAX_PT_NUM];
__u16 vert_coord[C3_ISP_AF_MAX_PT_NUM];
} __attribute__((aligned(8)));
/**
* struct c3_isp_params_pst_gamma - Post gamma configuration
*
* This struct allows the configuration of the look up table for
* post gamma. The gamma curve consists of 129 points, so need to
* set lut[129].
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_PST_GAMMA
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @lut: lookup table for P-Stitch gamma [0..1023]
* @reserved: applications must zero this array
*/
struct c3_isp_params_pst_gamma {
struct c3_isp_params_block_header header;
__u16 lut[129];
__u16 reserved[3];
} __attribute__((aligned(8)));
/**
* struct c3_isp_params_ccm - ISP CCM configuration
*
* This struct allows the configuration of the matrix for
* color correction. The matrix consists of 3 x 3 points,
* so need to set matrix[3][3].
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_CCM
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @matrix: a 3 x 3 matrix used for color correction,
* the value of matrix[x][y] is orig_value x 256. [-4096..4095]
* @reserved: applications must zero this array
*/
struct c3_isp_params_ccm {
struct c3_isp_params_block_header header;
__s16 matrix[3][3];
__u16 reserved[3];
} __attribute__((aligned(8)));
/**
* struct c3_isp_params_csc - ISP Color Space Conversion configuration
*
* This struct allows the configuration of the matrix for color space
* conversion. The matrix consists of 3 x 3 points, so need to set matrix[3][3].
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_CSC
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @matrix: a 3x3 matrix used for the color space conversion,
* the value of matrix[x][y] is orig_value x 256. [-4096..4095]
* @reserved: applications must zero this array
*/
struct c3_isp_params_csc {
struct c3_isp_params_block_header header;
__s16 matrix[3][3];
__u16 reserved[3];
} __attribute__((aligned(8)));
/**
* struct c3_isp_params_blc - ISP Black Level Correction configuration
*
* This struct allows the configuration of the block level offset for each
* color channel.
*
* header.type should be set to C3_ISP_PARAMS_BLOCK_BLC
* from :c:type:`c3_isp_params_block_type`
*
* @header: the C3 ISP parameters block header
* @gr_ofst: Gr blc offset (Q4.12 format)
* @r_ofst: R blc offset (Q4.12 format)
* @b_ofst: B blc offset (Q4.12 format)
* @gb_ofst: Gb blc offset(Q4.12 format)
*/
struct c3_isp_params_blc {
struct c3_isp_params_block_header header;
__u16 gr_ofst;
__u16 r_ofst;
__u16 b_ofst;
__u16 gb_ofst;
};
/**
* define C3_ISP_PARAMS_MAX_SIZE - Maximum size of all C3 ISP Parameters
*
* Though the parameters for the C3 ISP are passed as optional blocks, the
* driver still needs to know the absolute maximum size so that it can allocate
* a buffer sized appropriately to accommodate userspace attempting to set all
* possible parameters in a single frame.
*/
#define C3_ISP_PARAMS_MAX_SIZE \
(sizeof(struct c3_isp_params_awb_gains) + \
sizeof(struct c3_isp_params_awb_config) + \
sizeof(struct c3_isp_params_ae_config) + \
sizeof(struct c3_isp_params_af_config) + \
sizeof(struct c3_isp_params_pst_gamma) + \
sizeof(struct c3_isp_params_ccm) + \
sizeof(struct c3_isp_params_csc) + \
sizeof(struct c3_isp_params_blc))
/**
* struct c3_isp_params_cfg - C3 ISP configuration parameters
*
* This is the driver-specific implementation of
* :c:type:`v4l2_isp_params_buffer`.
*
* Currently only C3_ISP_PARAM_BUFFER_V0 is supported.
*
* The expected memory layout of the parameters buffer is::
*
* +-------------------- struct c3_isp_params_cfg ---- ------------------+
* | version = C3_ISP_PARAM_BUFFER_V0; |
* | data_size = sizeof(struct c3_isp_params_awb_gains) + |
* | sizeof(struct c3_isp_params_awb_config); |
* | +------------------------- data ---------------------------------+ |
* | | +------------ struct c3_isp_params_awb_gains) ------------------+ |
* | | | +--------- struct c3_isp_params_block_header header -----+ | | |
* | | | | type = C3_ISP_PARAMS_BLOCK_AWB_GAINS; | | | |
* | | | | flags = C3_ISP_PARAMS_BLOCK_FL_NONE; | | | |
* | | | | size = sizeof(struct c3_isp_params_awb_gains); | | | |
* | | | +---------------------------------------------------------+ | | |
* | | | gr_gain = ...; | | |
* | | | r_gain = ...; | | |
* | | | b_gain = ...; | | |
* | | | gb_gain = ...; | | |
* | | +------------------ struct c3_isp_params_awb_config ----------+ | |
* | | | +---------- struct c3_isp_param_block_header header ------+ | | |
* | | | | type = C3_ISP_PARAMS_BLOCK_AWB_CONFIG; | | | |
* | | | | flags = C3_ISP_PARAMS_BLOCK_FL_NONE; | | | |
* | | | | size = sizeof(struct c3_isp_params_awb_config) | | | |
* | | | +---------------------------------------------------------+ | | |
* | | | tap_point = ...; | | |
* | | | satur_vald = ...; | | |
* | | | horiz_zones_num = ...; | | |
* | | | vert_zones_num = ...; | | |
* | | +-------------------------------------------------------------+ | |
* | +-----------------------------------------------------------------+ |
* +---------------------------------------------------------------------+
*
* @version: The C3 ISP parameters buffer version
* @data_size: The C3 ISP configuration data effective size, excluding this
* header
* @data: The C3 ISP configuration blocks data
*/
struct c3_isp_params_cfg {
__u32 version;
__u32 data_size;
__u8 data[C3_ISP_PARAMS_MAX_SIZE];
};
#ifdef __KERNEL__
/* Make sure the header is type-convertible to the generic v4l2 params one */
static_assert((sizeof(struct c3_isp_params_cfg) - C3_ISP_PARAMS_MAX_SIZE) ==
sizeof(struct v4l2_isp_params_buffer));
#endif /* __KERNEL__ */
#endif
linux-7.2.3/include/uapi/linux/media/arm/mali-c55-config.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* ARM Mali-C55 ISP Driver - Userspace API
*
* Copyright (C) 2023 Ideas on Board Oy
*/
#ifndef __UAPI_MALI_C55_CONFIG_H
#define __UAPI_MALI_C55_CONFIG_H
#include <linux/types.h>
#include <linux/v4l2-controls.h>
#include <linux/media/v4l2-isp.h>
#define V4L2_CID_MALI_C55_CAPABILITIES (V4L2_CID_USER_MALI_C55_BASE + 0x0)
#define MALI_C55_GPS_PONG (1U << 0)
#define MALI_C55_GPS_WDR (1U << 1)
#define MALI_C55_GPS_COMPRESSION (1U << 2)
#define MALI_C55_GPS_TEMPER (1U << 3)
#define MALI_C55_GPS_SINTER_LITE (1U << 4)
#define MALI_C55_GPS_SINTER (1U << 5)
#define MALI_C55_GPS_IRIDIX_LTM (1U << 6)
#define MALI_C55_GPS_IRIDIX_GTM (1U << 7)
#define MALI_C55_GPS_CNR (1U << 8)
#define MALI_C55_GPS_FRSCALER (1U << 9)
#define MALI_C55_GPS_DS_PIPE (1U << 10)
/*
* Frames are split into zones of almost equal width and height - a zone is a
* rectangular tile of a frame. The metering blocks within the ISP collect
* aggregated statistics per zone. A maximum of 15x15 zones can be configured,
* and so the statistics buffer within the hardware is sized to accommodate
* that.
*
* The utilised number of zones is runtime configurable.
*/
#define MALI_C55_MAX_ZONES (15 * 15)
/**
* struct mali_c55_ae_1024bin_hist - Auto Exposure 1024-bin histogram statistics
*
* @bins: 1024 element array of 16-bit pixel counts.
*
* The 1024-bin histogram module collects image-global but zone-weighted
* intensity distributions of pixels in fixed-width bins. The modules can be
* configured into different "plane modes" which affect the contents of the
* collected statistics. In plane mode 0, pixel intensities are taken regardless
* of colour plane into a single 1024-bin histogram with a bin width of 4. In
* plane mode 1, four 256-bin histograms with a bin width of 16 are collected -
* one for each CFA colour plane. In plane modes 4, 5, 6 and 7 two 512-bin
* histograms with a bin width of 8 are collected - in each mode one of the
* colour planes is collected into the first histogram and all the others are
* combined into the second. The histograms are stored consecutively in the bins
* array.
*
* The 16-bit pixel counts are stored as a 4-bit exponent in the most
* significant bits followed by a 12-bit mantissa. Conversion to a usable
* format can be done according to the following pseudo-code::
*
* if (e == 0) {
* bin = m * 2;
* } else {
* bin = (m + 4096) * 2^e
* }
*
* where
* e is the exponent value in range 0..15
* m is the mantissa value in range 0..4095
*
* The pixels used in calculating the statistics can be masked using three
* methods:
*
* 1. Pixels can be skipped in X and Y directions independently.
* 2. Minimum/Maximum intensities can be configured
* 3. Zones can be differentially weighted, including 0 weighted to mask them
*
* The data for this histogram can be collected from different tap points in the
* ISP depending on configuration - after the white balance or digital gain
* blocks, or immediately after the input crossbar.
*/
struct mali_c55_ae_1024bin_hist {
__u16 bins[1024];
} __attribute__((packed));
/**
* struct mali_c55_ae_5bin_hist - Auto Exposure 5-bin histogram statistics
*
* @hist0: 16-bit normalised pixel count for the 0th intensity bin
* @hist1: 16-bit normalised pixel count for the 1st intensity bin
* @hist3: 16-bit normalised pixel count for the 3rd intensity bin
* @hist4: 16-bit normalised pixel count for the 4th intensity bin
*
* The ISP generates a 5-bin histogram of normalised pixel counts within bins of
* pixel intensity for each of 225 possible zones within a frame. The centre bin
* of the histogram for each zone is not available from the hardware and must be
* calculated by subtracting the values of hist0, hist1, hist3 and hist4 from
* 0xffff as in the following equation:
*
* hist2 = 0xffff - (hist0 + hist1 + hist3 + hist4)
*/
struct mali_c55_ae_5bin_hist {
__u16 hist0;
__u16 hist1;
__u16 hist3;
__u16 hist4;
} __attribute__((packed));
/**
* struct mali_c55_awb_average_ratios - Auto White Balance colour ratios
*
* @avg_rg_gr: Average R/G or G/R ratio in Q4.8 format.
* @avg_bg_br: Average B/G or B/R ratio in Q4.8 format.
* @num_pixels: The number of pixels used in the AWB calculation
*
* The ISP calculates and collects average colour ratios for each zone in an
* image and stores them in Q4.8 format (the lowest 8 bits are fractional, with
* bits [11:8] representing the integer). The exact ratios collected (either
* R/G, B/G or G/R, B/R) are configurable through the parameters buffer. The
* value of the 4 high bits is undefined.
*/
struct mali_c55_awb_average_ratios {
__u16 avg_rg_gr;
__u16 avg_bg_br;
__u32 num_pixels;
} __attribute__((packed));
/**
* struct mali_c55_af_statistics - Auto Focus edge and intensity statistics
*
* @intensity_stats: Packed mantissa and exponent value for pixel intensity
* @edge_stats: Packed mantissa and exponent values for edge intensity
*
* The ISP collects the squared sum of pixel intensities for each zone within a
* configurable Region of Interest on the frame. Additionally, the same data are
* collected after being passed through a bandpass filter which removes high and
* low frequency components - these are referred to as the edge statistics.
*
* The intensity and edge statistics for a zone can be used to calculate the
* contrast information for a zone
*
* C = E2 / I2
*
* Where I2 is the intensity statistic for a zone and E2 is the edge statistic
* for that zone. Optimum focus is reached when C is at its maximum.
*
* The intensity and edge statistics are stored packed into a non-standard 16
* bit floating point format, where the 7 most significant bits represent the
* exponent and the 9 least significant bits the mantissa. This format can be
* unpacked with the following pseudocode::
*
* if (e == 0) {
* x = m;
* } else {
* x = 2^e-1 * (m + 2^9)
* }
*
* where
* e is the exponent value in range 0..127
* m is the mantissa value in range 0..511
*/
struct mali_c55_af_statistics {
__u16 intensity_stats;
__u16 edge_stats;
} __attribute__((packed));
/**
* struct mali_c55_stats_buffer - 3A statistics for the mali-c55 ISP
*
* @ae_1024bin_hist: 1024-bin frame-global pixel intensity histogram
* @iridix_1024bin_hist: Post-Iridix block 1024-bin histogram
* @ae_5bin_hists: 5-bin pixel intensity histograms for AEC
* @reserved1: Undefined buffer space
* @awb_ratios: Color balance ratios for Auto White Balance
* @reserved2: Undefined buffer space
* @af_statistics: Pixel intensity statistics for Auto Focus
* @reserved3: Undefined buffer space
*
* This struct describes the metering statistics space in the Mali-C55 ISP's
* hardware in its entirety. The space between each defined area is marked as
* "unknown" and may not be 0, but should not be used. The @ae_5bin_hists,
* @awb_ratios and @af_statistics members are arrays of statistics per-zone.
* The zones are arranged in the array in raster order starting from the top
* left corner of the image.
*/
struct mali_c55_stats_buffer {
struct mali_c55_ae_1024bin_hist ae_1024bin_hist;
struct mali_c55_ae_1024bin_hist iridix_1024bin_hist;
struct mali_c55_ae_5bin_hist ae_5bin_hists[MALI_C55_MAX_ZONES];
__u32 reserved1[14];
struct mali_c55_awb_average_ratios awb_ratios[MALI_C55_MAX_ZONES];
__u32 reserved2[14];
struct mali_c55_af_statistics af_statistics[MALI_C55_MAX_ZONES];
__u32 reserved3[15];
} __attribute__((packed));
/**
* enum mali_c55_param_block_type - Enumeration of Mali-C55 parameter blocks
*
* This enumeration defines the types of Mali-C55 parameters block. Each block
* configures a specific processing block of the Mali-C55 ISP. The block
* type allows the driver to correctly interpret the parameters block data.
*
* It is the responsibility of userspace to correctly set the type of each
* parameters block.
*
* @MALI_C55_PARAM_BLOCK_SENSOR_OFFS: Sensor pre-shading black level offset
* @MALI_C55_PARAM_BLOCK_AEXP_HIST: Auto-exposure 1024-bin histogram
* configuration
* @MALI_C55_PARAM_BLOCK_AEXP_IHIST: Post-Iridix auto-exposure 1024-bin
* histogram configuration
* @MALI_C55_PARAM_BLOCK_AEXP_HIST_WEIGHTS: Auto-exposure 1024-bin histogram
* weighting
* @MALI_C55_PARAM_BLOCK_AEXP_IHIST_WEIGHTS: Post-Iridix auto-exposure 1024-bin
* histogram weighting
* @MALI_C55_PARAM_BLOCK_DIGITAL_GAIN: Digital gain
* @MALI_C55_PARAM_BLOCK_AWB_GAINS: Auto-white balance gains
* @MALI_C55_PARAM_BLOCK_AWB_CONFIG: Auto-white balance statistics config
* @MALI_C55_PARAM_BLOCK_AWB_GAINS_AEXP: Auto-white balance gains for AEXP-0 tap
* @MALI_C55_PARAM_MESH_SHADING_CONFIG : Mesh shading tables configuration
* @MALI_C55_PARAM_MESH_SHADING_SELECTION: Mesh shading table selection
*/
enum mali_c55_param_block_type {
MALI_C55_PARAM_BLOCK_SENSOR_OFFS,
MALI_C55_PARAM_BLOCK_AEXP_HIST,
MALI_C55_PARAM_BLOCK_AEXP_IHIST,
MALI_C55_PARAM_BLOCK_AEXP_HIST_WEIGHTS,
MALI_C55_PARAM_BLOCK_AEXP_IHIST_WEIGHTS,
MALI_C55_PARAM_BLOCK_DIGITAL_GAIN,
MALI_C55_PARAM_BLOCK_AWB_GAINS,
MALI_C55_PARAM_BLOCK_AWB_CONFIG,
MALI_C55_PARAM_BLOCK_AWB_GAINS_AEXP,
MALI_C55_PARAM_MESH_SHADING_CONFIG,
MALI_C55_PARAM_MESH_SHADING_SELECTION,
};
/**
* struct mali_c55_params_sensor_off_preshading - offset subtraction for each
* color channel
*
* Provides removal of the sensor black level from the sensor data. Separate
* offsets are provided for each of the four Bayer component color channels
* which are defaulted to R, Gr, Gb, B.
*
* header.type should be set to MALI_C55_PARAM_BLOCK_SENSOR_OFFS from
* :c:type:`mali_c55_param_block_type` for this block.
*
* @header: The Mali-C55 parameters block header
* @chan00: Offset for color channel 00 (default: R)
* @chan01: Offset for color channel 01 (default: Gr)
* @chan10: Offset for color channel 10 (default: Gb)
* @chan11: Offset for color channel 11 (default: B)
*/
struct mali_c55_params_sensor_off_preshading {
struct v4l2_isp_params_block_header header;
__u32 chan00;
__u32 chan01;
__u32 chan10;
__u32 chan11;
};
/**
* enum mali_c55_aexp_hist_tap_points - Tap points for the AEXP histogram
* @MALI_C55_AEXP_HIST_TAP_WB: After static white balance
* @MALI_C55_AEXP_HIST_TAP_FS: After WDR Frame Stitch
* @MALI_C55_AEXP_HIST_TAP_TPG: After the test pattern generator
*/
enum mali_c55_aexp_hist_tap_points {
MALI_C55_AEXP_HIST_TAP_WB = 0,
MALI_C55_AEXP_HIST_TAP_FS,
MALI_C55_AEXP_HIST_TAP_TPG,
};
/**
* enum mali_c55_aexp_skip_x - Horizontal pixel skipping
* @MALI_C55_AEXP_SKIP_X_EVERY_2ND: Collect every 2nd pixel horizontally
* @MALI_C55_AEXP_SKIP_X_EVERY_3RD: Collect every 3rd pixel horizontally
* @MALI_C55_AEXP_SKIP_X_EVERY_4TH: Collect every 4th pixel horizontally
* @MALI_C55_AEXP_SKIP_X_EVERY_5TH: Collect every 5th pixel horizontally
* @MALI_C55_AEXP_SKIP_X_EVERY_8TH: Collect every 8th pixel horizontally
* @MALI_C55_AEXP_SKIP_X_EVERY_9TH: Collect every 9th pixel horizontally
*/
enum mali_c55_aexp_skip_x {
MALI_C55_AEXP_SKIP_X_EVERY_2ND,
MALI_C55_AEXP_SKIP_X_EVERY_3RD,
MALI_C55_AEXP_SKIP_X_EVERY_4TH,
MALI_C55_AEXP_SKIP_X_EVERY_5TH,
MALI_C55_AEXP_SKIP_X_EVERY_8TH,
MALI_C55_AEXP_SKIP_X_EVERY_9TH
};
/**
* enum mali_c55_aexp_skip_y - Vertical pixel skipping
* @MALI_C55_AEXP_SKIP_Y_ALL: Collect every single pixel vertically
* @MALI_C55_AEXP_SKIP_Y_EVERY_2ND: Collect every 2nd pixel vertically
* @MALI_C55_AEXP_SKIP_Y_EVERY_3RD: Collect every 3rd pixel vertically
* @MALI_C55_AEXP_SKIP_Y_EVERY_4TH: Collect every 4th pixel vertically
* @MALI_C55_AEXP_SKIP_Y_EVERY_5TH: Collect every 5th pixel vertically
* @MALI_C55_AEXP_SKIP_Y_EVERY_8TH: Collect every 8th pixel vertically
* @MALI_C55_AEXP_SKIP_Y_EVERY_9TH: Collect every 9th pixel vertically
*/
enum mali_c55_aexp_skip_y {
MALI_C55_AEXP_SKIP_Y_ALL,
MALI_C55_AEXP_SKIP_Y_EVERY_2ND,
MALI_C55_AEXP_SKIP_Y_EVERY_3RD,
MALI_C55_AEXP_SKIP_Y_EVERY_4TH,
MALI_C55_AEXP_SKIP_Y_EVERY_5TH,
MALI_C55_AEXP_SKIP_Y_EVERY_8TH,
MALI_C55_AEXP_SKIP_Y_EVERY_9TH
};
/**
* enum mali_c55_aexp_row_column_offset - Start from the first or second row or
* column
* @MALI_C55_AEXP_FIRST_ROW_OR_COL: Start from the first row / column
* @MALI_C55_AEXP_SECOND_ROW_OR_COL: Start from the second row / column
*/
enum mali_c55_aexp_row_column_offset {
MALI_C55_AEXP_FIRST_ROW_OR_COL = 1,
MALI_C55_AEXP_SECOND_ROW_OR_COL = 2,
};
/**
* enum mali_c55_aexp_hist_plane_mode - Mode for the AEXP Histograms
* @MALI_C55_AEXP_HIST_COMBINED: All color planes in one 1024-bin histogram
* @MALI_C55_AEXP_HIST_SEPARATE: Each color plane in one 256-bin histogram with a bin width of 16
* @MALI_C55_AEXP_HIST_FOCUS_00: Top left plane in the first bank, rest in second bank
* @MALI_C55_AEXP_HIST_FOCUS_01: Top right plane in the first bank, rest in second bank
* @MALI_C55_AEXP_HIST_FOCUS_10: Bottom left plane in the first bank, rest in second bank
* @MALI_C55_AEXP_HIST_FOCUS_11: Bottom right plane in the first bank, rest in second bank
*
* In the "focus" modes statistics are collected into two 512-bin histograms
* with a bin width of 8. One colour plane is in the first histogram with the
* remainder combined into the second. The four options represent which of the
* four positions in a bayer pattern are the focused plane.
*/
enum mali_c55_aexp_hist_plane_mode {
MALI_C55_AEXP_HIST_COMBINED = 0,
MALI_C55_AEXP_HIST_SEPARATE = 1,
MALI_C55_AEXP_HIST_FOCUS_00 = 4,
MALI_C55_AEXP_HIST_FOCUS_01 = 5,
MALI_C55_AEXP_HIST_FOCUS_10 = 6,
MALI_C55_AEXP_HIST_FOCUS_11 = 7,
};
/**
* struct mali_c55_params_aexp_hist - configuration for AEXP metering hists
*
* This struct allows users to configure the 1024-bin AEXP histograms. Broadly
* speaking the parameters allow you to mask particular regions of the image and
* to select different kinds of histogram.
*
* The skip_x, offset_x, skip_y and offset_y fields allow users to ignore or
* mask pixels in the frame by their position relative to the top left pixel.
* First, the skip_y, offset_x and offset_y fields define which of the pixels
* within each 2x2 region will be counted in the statistics.
*
* If skip_y == 0 then two pixels from each covered region will be counted. If
* both offset_x and offset_y are zero, then the two left-most pixels in each
* 2x2 pixel region will be counted. Setting offset_x = 1 will discount the top
* left pixel and count the top right pixel. Setting offset_y = 1 will discount
* the bottom left pixel and count the bottom right pixel.
*
* If skip_y != 0 then only a single pixel from each region covered by the
* pattern will be counted. In this case offset_x controls whether the pixel
* that's counted is in the left (if offset_x == 0) or right (if offset_x == 1)
* column and offset_y controls whether the pixel that's counted is in the top
* (if offset_y == 0) or bottom (if offset_y == 1) row.
*
* The skip_x and skip_y fields control how the 2x2 pixel region is repeated
* across the image data. The first instance of the region is always in the top
* left of the image data. The skip_x field controls how many pixels are ignored
* in the x direction before the pixel masking region is repeated. The skip_y
* field controls how many pixels are ignored in the y direction before the
* pixel masking region is repeated.
*
* These fields can be used to reduce the number of pixels counted for the
* statistics, but it's important to be careful to configure them correctly.
* Some combinations of values will result in colour components from the input
* data being ignored entirely, for example in the following configuration:
*
* skip_x = 0
* offset_x = 0
* skip_y = 0
* offset_y = 0
*
* Only the R and Gb components of RGGB data that was input would be collected.
* Similarly in the following configuration:
*
* skip_x = 0
* offset_x = 0
* skip_y = 1
* offset_y = 1
*
* Only the Gb component of RGGB data that was input would be collected. To
* correct things such that all 4 colour components were included it would be
* necessary to set the skip_x and skip_y fields in a way that resulted in all
* four colour components being collected:
*
* skip_x = 1
* offset_x = 0
* skip_y = 1
* offset_y = 1
*
* header.type should be set to one of either MALI_C55_PARAM_BLOCK_AEXP_HIST or
* MALI_C55_PARAM_BLOCK_AEXP_IHIST from :c:type:`mali_c55_param_block_type`.
*
* @header: The Mali-C55 parameters block header
* @skip_x: Horizontal decimation. See enum mali_c55_aexp_skip_x
* @offset_x: Skip the first column, or not. See enum mali_c55_aexp_row_column_offset
* @skip_y: Vertical decimation. See enum mali_c55_aexp_skip_y
* @offset_y: Skip the first row, or not. See enum mali_c55_aexp_row_column_offset
* @scale_bottom: Scale pixels in bottom half of intensity range: 0=1x ,1=2x, 2=4x, 4=8x, 4=16x
* @scale_top: scale pixels in top half of intensity range: 0=1x ,1=2x, 2=4x, 4=8x, 4=16x
* @plane_mode: Plane separation mode. See enum mali_c55_aexp_hist_plane_mode
* @tap_point: Tap point for histogram from enum mali_c55_aexp_hist_tap_points.
* This parameter is unused for the post-Iridix Histogram
*/
struct mali_c55_params_aexp_hist {
struct v4l2_isp_params_block_header header;
__u8 skip_x;
__u8 offset_x;
__u8 skip_y;
__u8 offset_y;
__u8 scale_bottom;
__u8 scale_top;
__u8 plane_mode;
__u8 tap_point;
};
/**
* struct mali_c55_params_aexp_weights - Array of weights for AEXP metering
*
* This struct allows users to configure the weighting for both of the 1024-bin
* AEXP histograms. The pixel data collected for each zone is multiplied by the
* corresponding weight from this array, which may be zero if the intention is
* to mask off the zone entirely.
*
* header.type should be set to one of either MALI_C55_PARAM_BLOCK_AEXP_HIST_WEIGHTS
* or MALI_C55_PARAM_BLOCK_AEXP_IHIST_WEIGHTS from :c:type:`mali_c55_param_block_type`.
*
* @header: The Mali-C55 parameters block header
* @nodes_used_horiz: Number of active zones horizontally [0..15]
* @nodes_used_vert: Number of active zones vertically [0..15]
* @zone_weights: Zone weighting. Index is row*col where 0,0 is the top
* left zone continuing in raster order. Each zone can be
* weighted in the range [0..15]. The number of rows and
* columns is defined by @nodes_used_vert and
* @nodes_used_horiz
*/
struct mali_c55_params_aexp_weights {
struct v4l2_isp_params_block_header header;
__u8 nodes_used_horiz;
__u8 nodes_used_vert;
__u8 zone_weights[MALI_C55_MAX_ZONES];
};
/**
* struct mali_c55_params_digital_gain - Digital gain value
*
* This struct carries a digital gain value to set in the ISP.
*
* header.type should be set to MALI_C55_PARAM_BLOCK_DIGITAL_GAIN from
* :c:type:`mali_c55_param_block_type` for this block.
*
* @header: The Mali-C55 parameters block header
* @gain: The digital gain value to apply, in Q5.8 format.
*/
struct mali_c55_params_digital_gain {
struct v4l2_isp_params_block_header header;
__u16 gain;
};
/**
* enum mali_c55_awb_stats_mode - Statistics mode for AWB
* @MALI_C55_AWB_MODE_GRBR: Statistics collected as Green/Red and Blue/Red ratios
* @MALI_C55_AWB_MODE_RGBG: Statistics collected as Red/Green and Blue/Green ratios
*/
enum mali_c55_awb_stats_mode {
MALI_C55_AWB_MODE_GRBR = 0,
MALI_C55_AWB_MODE_RGBG,
};
/**
* struct mali_c55_params_awb_gains - Gain settings for auto white balance
*
* This struct allows users to configure the gains for auto-white balance. There
* are four gain settings corresponding to each colour channel in the bayer
* domain. Although named generically, the association between the gain applied
* and the colour channel is done automatically within the ISP depending on the
* input format, and so the following mapping always holds true::
*
* gain00 = R
* gain01 = Gr
* gain10 = Gb
* gain11 = B
*
* All of the gains are stored in Q4.8 format.
*
* header.type should be set to one of either MALI_C55_PARAM_BLOCK_AWB_GAINS or
* MALI_C55_PARAM_BLOCK_AWB_GAINS_AEXP from :c:type:`mali_c55_param_block_type`.
*
* @header: The Mali-C55 parameters block header
* @gain00: Multiplier for colour channel 00
* @gain01: Multiplier for colour channel 01
* @gain10: Multiplier for colour channel 10
* @gain11: Multiplier for colour channel 11
*/
struct mali_c55_params_awb_gains {
struct v4l2_isp_params_block_header header;
__u16 gain00;
__u16 gain01;
__u16 gain10;
__u16 gain11;
};
/**
* enum mali_c55_params_awb_tap_points - Tap points for the AWB statistics
* @MALI_C55_AWB_STATS_TAP_PF: Immediately after the Purple Fringe block
* @MALI_C55_AWB_STATS_TAP_CNR: Immediately after the CNR block
*/
enum mali_c55_params_awb_tap_points {
MALI_C55_AWB_STATS_TAP_PF = 0,
MALI_C55_AWB_STATS_TAP_CNR,
};
/**
* struct mali_c55_params_awb_config - Stats settings for auto-white balance
*
* This struct allows the configuration of the statistics generated for auto
* white balance. Pixel intensity limits can be set to exclude overly bright or
* dark regions of an image from the statistics entirely. Colour ratio minima
* and maxima can be set to discount pixels who's ratios fall outside the
* defined boundaries; there are two sets of registers to do this - the
* "min/max" ratios which bound a region and the "high/low" ratios which further
* trim the upper and lower ratios. For example with the boundaries configured
* as follows, only pixels whos colour ratios falls into the region marked "A"
* would be counted::
*
* cr_high
* 2.0 | |
* | cb_max --> _________________________v_____
* 1.8 | | \ |
* | | \ |
* 1.6 | | \ |
* | | \ |
* c 1.4 | cb_low -->|\ A \|<-- cb_high
* b | | \ |
* 1.2 | | \ |
* r | | \ |
* a 1.0 | cb_min --> |____\_________________________|
* t | ^ ^ ^
* i 0.8 | | | |
* o | cr_min | cr_max
* s 0.6 | |
* | cr_low
* 0.4 |
* |
* 0.2 |
* |
* 0.0 |_______________________________________________________________
* 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
* cr ratios
*
* header.type should be set to MALI_C55_PARAM_BLOCK_AWB_CONFIG from
* :c:type:`mali_c55_param_block_type` for this block.
*
* @header: The Mali-C55 parameters block header
* @tap_point: The tap point from enum mali_c55_params_awb_tap_points
* @stats_mode: AWB statistics collection mode, see :c:type:`mali_c55_awb_stats_mode`
* @white_level: Upper pixel intensity (I.E. raw pixel values) limit
* @black_level: Lower pixel intensity (I.E. raw pixel values) limit
* @cr_max: Maximum R/G ratio (Q4.8 format)
* @cr_min: Minimum R/G ratio (Q4.8 format)
* @cb_max: Maximum B/G ratio (Q4.8 format)
* @cb_min: Minimum B/G ratio (Q4.8 format)
* @nodes_used_horiz: Number of active zones horizontally [0..15]
* @nodes_used_vert: Number of active zones vertically [0..15]
* @cr_high: R/G ratio trim high (Q4.8 format)
* @cr_low: R/G ratio trim low (Q4.8 format)
* @cb_high: B/G ratio trim high (Q4.8 format)
* @cb_low: B/G ratio trim low (Q4.8 format)
*/
struct mali_c55_params_awb_config {
struct v4l2_isp_params_block_header header;
__u8 tap_point;
__u8 stats_mode;
__u16 white_level;
__u16 black_level;
__u16 cr_max;
__u16 cr_min;
__u16 cb_max;
__u16 cb_min;
__u8 nodes_used_horiz;
__u8 nodes_used_vert;
__u16 cr_high;
__u16 cr_low;
__u16 cb_high;
__u16 cb_low;
};
#define MALI_C55_NUM_MESH_SHADING_ELEMENTS 3072
/**
* struct mali_c55_params_mesh_shading_config - Mesh shading configuration
*
* The mesh shading correction module allows programming a separate table of
* either 16x16 or 32x32 node coefficients for 3 different light sources. The
* final correction coefficients applied are computed by blending the
* coefficients from two tables together.
*
* A page of 1024 32-bit integers is associated to each colour channel, with
* pages stored consecutively in memory. Each 32-bit integer packs 3 8-bit
* correction coefficients for a single node, one for each of the three light
* sources. The 8 most significant bits are unused. The following table
* describes the layout::
*
* +----------- Page (Colour Plane) 0 -------------+
* | @mesh[i] | Mesh Point | Bits | Light Source |
* +-----------+------------+-------+--------------+
* | 0 | 0,0 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
* | 1 | 0,1 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
* | ... | ... | ... | ... |
* +-----------+------------+-------+--------------+
* | 1023 | 31,31 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +----------- Page (Colour Plane) 1 -------------+
* | @mesh[i] | Mesh Point | Bits | Light Source |
* +-----------+------------+-------+--------------+
* | 1024 | 0,0 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
* | 1025 | 0,1 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
* | ... | ... | ... | ... |
* +-----------+------------+-------+--------------+
* | 2047 | 31,31 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +----------- Page (Colour Plane) 2 -------------+
* | @mesh[i] | Mesh Point | Bits | Light Source |
* +-----------+------------+-------+--------------+
* | 2048 | 0,0 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
* | 2049 | 0,1 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
* | ... | ... | ... | ... |
* +-----------+------------+-------+--------------+
* | 3071 | 31,31 | 16,23 | LS2 |
* | | | 08-15 | LS1 |
* | | | 00-07 | LS0 |
* +-----------+------------+-------+--------------+
*
* The @mesh_scale member determines the precision and minimum and maximum gain.
* For example if @mesh_scale is 0 and therefore selects 0 - 2x gain, a value of
* 0 in a coefficient means 0.0 gain, a value of 128 means 1.0 gain and 255
* means 2.0 gain.
*
* header.type should be set to MALI_C55_PARAM_MESH_SHADING_CONFIG from
* :c:type:`mali_c55_param_block_type` for this block.
*
* @header: The Mali-C55 parameters block header
* @mesh_show: Output the mesh data rather than image data
* @mesh_scale: Set the precision and maximum gain range of mesh shading
* - 0 = 0-2x gain
* - 1 = 0-4x gain
* - 2 = 0-8x gain
* - 3 = 0-16x gain
* - 4 = 1-2x gain
* - 5 = 1-3x gain
* - 6 = 1-5x gain
* - 7 = 1-9x gain
* @mesh_page_r: Mesh page select for red colour plane [0..2]
* @mesh_page_g: Mesh page select for green colour plane [0..2]
* @mesh_page_b: Mesh page select for blue colour plane [0..2]
* @mesh_width: Number of horizontal nodes minus 1 [15,31]
* @mesh_height: Number of vertical nodes minus 1 [15,31]
* @mesh: Mesh shading correction tables
*/
struct mali_c55_params_mesh_shading_config {
struct v4l2_isp_params_block_header header;
__u8 mesh_show;
__u8 mesh_scale;
__u8 mesh_page_r;
__u8 mesh_page_g;
__u8 mesh_page_b;
__u8 mesh_width;
__u8 mesh_height;
__u32 mesh[MALI_C55_NUM_MESH_SHADING_ELEMENTS];
};
/** enum mali_c55_params_mesh_alpha_bank - Mesh shading table bank selection
* @MALI_C55_MESH_ALPHA_BANK_LS0_AND_LS1 - Select Light Sources 0 and 1
* @MALI_C55_MESH_ALPHA_BANK_LS1_AND_LS2 - Select Light Sources 1 and 2
* @MALI_C55_MESH_ALPHA_BANK_LS0_AND_LS2 - Select Light Sources 0 and 2
*/
enum mali_c55_params_mesh_alpha_bank {
MALI_C55_MESH_ALPHA_BANK_LS0_AND_LS1 = 0,
MALI_C55_MESH_ALPHA_BANK_LS1_AND_LS2 = 1,
MALI_C55_MESH_ALPHA_BANK_LS0_AND_LS2 = 4
};
/**
* struct mali_c55_params_mesh_shading_selection - Mesh table selection
*
* The module computes the final correction coefficients by blending the ones
* from two light source tables, which are selected (independently for each
* colour channel) by the @mesh_alpha_bank_r/g/b fields.
*
* The final blended coefficients for each node are calculated using the
* following equation:
*
* Final coefficient = (a * LS\ :sub:`b`\ + (256 - a) * LS\ :sub:`a`\) / 256
*
* Where a is the @mesh_alpha_r/g/b value, and LS\ :sub:`a`\ and LS\ :sub:`b`\
* are the node cofficients for the two tables selected by the
* @mesh_alpha_bank_r/g/b value.
*
* The scale of the applied correction may also be controlled by tuning the
* @mesh_strength member. This is a modifier to the final coefficients which can
* be used to globally reduce the gains applied.
*
* header.type should be set to MALI_C55_PARAM_MESH_SHADING_SELECTION from
* :c:type:`mali_c55_param_block_type` for this block.
*
* @header: The Mali-C55 parameters block header
* @mesh_alpha_bank_r: Red mesh table select (c:type:`enum mali_c55_params_mesh_alpha_bank`)
* @mesh_alpha_bank_g: Green mesh table select (c:type:`enum mali_c55_params_mesh_alpha_bank`)
* @mesh_alpha_bank_b: Blue mesh table select (c:type:`enum mali_c55_params_mesh_alpha_bank`)
* @mesh_alpha_r: Blend coefficient for R [0..255]
* @mesh_alpha_g: Blend coefficient for G [0..255]
* @mesh_alpha_b: Blend coefficient for B [0..255]
* @mesh_strength: Mesh strength in Q4.12 format [0..4096]
*/
struct mali_c55_params_mesh_shading_selection {
struct v4l2_isp_params_block_header header;
__u8 mesh_alpha_bank_r;
__u8 mesh_alpha_bank_g;
__u8 mesh_alpha_bank_b;
__u8 mesh_alpha_r;
__u8 mesh_alpha_g;
__u8 mesh_alpha_b;
__u16 mesh_strength;
};
/**
* define MALI_C55_PARAMS_MAX_SIZE - Maximum size of all Mali C55 Parameters
*
* Though the parameters for the Mali-C55 are passed as optional blocks, the
* driver still needs to know the absolute maximum size so that it can allocate
* a buffer sized appropriately to accommodate userspace attempting to set all
* possible parameters in a single frame.
*
* Some structs are in this list multiple times. Where that's the case, it just
* reflects the fact that the same struct can be used with multiple different
* header types from :c:type:`mali_c55_param_block_type`.
*/
#define MALI_C55_PARAMS_MAX_SIZE \
(sizeof(struct mali_c55_params_sensor_off_preshading) + \
sizeof(struct mali_c55_params_aexp_hist) + \
sizeof(struct mali_c55_params_aexp_weights) + \
sizeof(struct mali_c55_params_aexp_hist) + \
sizeof(struct mali_c55_params_aexp_weights) + \
sizeof(struct mali_c55_params_digital_gain) + \
sizeof(struct mali_c55_params_awb_gains) + \
sizeof(struct mali_c55_params_awb_config) + \
sizeof(struct mali_c55_params_awb_gains) + \
sizeof(struct mali_c55_params_mesh_shading_config) + \
sizeof(struct mali_c55_params_mesh_shading_selection))
#endif /* __UAPI_MALI_C55_CONFIG_H */
linux-7.2.3/include/uapi/linux/media/raspberrypi/pisp_be_config.h
+969
View File
@@ -0,0 +1,969 @@
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* PiSP Back End configuration definitions.
*
* Copyright (C) 2021 - Raspberry Pi Ltd
*
*/
#ifndef _UAPI_PISP_BE_CONFIG_H_
#define _UAPI_PISP_BE_CONFIG_H_
#include <linux/types.h>
#include "pisp_common.h"
/* byte alignment for inputs */
#define PISP_BACK_END_INPUT_ALIGN 4u
/* alignment for compressed inputs */
#define PISP_BACK_END_COMPRESSED_ALIGN 8u
/* minimum required byte alignment for outputs */
#define PISP_BACK_END_OUTPUT_MIN_ALIGN 16u
/* preferred byte alignment for outputs */
#define PISP_BACK_END_OUTPUT_MAX_ALIGN 64u
/* minimum allowed tile sizes anywhere in the pipeline */
#define PISP_BACK_END_MIN_TILE_WIDTH 16u
#define PISP_BACK_END_MIN_TILE_HEIGHT 16u
#define PISP_BACK_END_MAX_TILE_WIDTH 65536u
#define PISP_BACK_END_MAX_TILE_HEIGHT 65536u
#define PISP_BACK_END_NUM_OUTPUTS 2
#define PISP_BACK_END_HOG_OUTPUT 1
#define PISP_BACK_END_NUM_TILES 64
enum pisp_be_bayer_enable {
PISP_BE_BAYER_ENABLE_INPUT = 0x000001,
PISP_BE_BAYER_ENABLE_DECOMPRESS = 0x000002,
PISP_BE_BAYER_ENABLE_DPC = 0x000004,
PISP_BE_BAYER_ENABLE_GEQ = 0x000008,
PISP_BE_BAYER_ENABLE_TDN_INPUT = 0x000010,
PISP_BE_BAYER_ENABLE_TDN_DECOMPRESS = 0x000020,
PISP_BE_BAYER_ENABLE_TDN = 0x000040,
PISP_BE_BAYER_ENABLE_TDN_COMPRESS = 0x000080,
PISP_BE_BAYER_ENABLE_TDN_OUTPUT = 0x000100,
PISP_BE_BAYER_ENABLE_SDN = 0x000200,
PISP_BE_BAYER_ENABLE_BLC = 0x000400,
PISP_BE_BAYER_ENABLE_STITCH_INPUT = 0x000800,
PISP_BE_BAYER_ENABLE_STITCH_DECOMPRESS = 0x001000,
PISP_BE_BAYER_ENABLE_STITCH = 0x002000,
PISP_BE_BAYER_ENABLE_STITCH_COMPRESS = 0x004000,
PISP_BE_BAYER_ENABLE_STITCH_OUTPUT = 0x008000,
PISP_BE_BAYER_ENABLE_WBG = 0x010000,
PISP_BE_BAYER_ENABLE_CDN = 0x020000,
PISP_BE_BAYER_ENABLE_LSC = 0x040000,
PISP_BE_BAYER_ENABLE_TONEMAP = 0x080000,
PISP_BE_BAYER_ENABLE_CAC = 0x100000,
PISP_BE_BAYER_ENABLE_DEBIN = 0x200000,
PISP_BE_BAYER_ENABLE_DEMOSAIC = 0x400000,
};
enum pisp_be_rgb_enable {
PISP_BE_RGB_ENABLE_INPUT = 0x000001,
PISP_BE_RGB_ENABLE_CCM = 0x000002,
PISP_BE_RGB_ENABLE_SAT_CONTROL = 0x000004,
PISP_BE_RGB_ENABLE_YCBCR = 0x000008,
PISP_BE_RGB_ENABLE_FALSE_COLOUR = 0x000010,
PISP_BE_RGB_ENABLE_SHARPEN = 0x000020,
/* Preferred colours would occupy 0x000040 */
PISP_BE_RGB_ENABLE_YCBCR_INVERSE = 0x000080,
PISP_BE_RGB_ENABLE_GAMMA = 0x000100,
PISP_BE_RGB_ENABLE_CSC0 = 0x000200,
PISP_BE_RGB_ENABLE_CSC1 = 0x000400,
PISP_BE_RGB_ENABLE_DOWNSCALE0 = 0x001000,
PISP_BE_RGB_ENABLE_DOWNSCALE1 = 0x002000,
PISP_BE_RGB_ENABLE_RESAMPLE0 = 0x008000,
PISP_BE_RGB_ENABLE_RESAMPLE1 = 0x010000,
PISP_BE_RGB_ENABLE_OUTPUT0 = 0x040000,
PISP_BE_RGB_ENABLE_OUTPUT1 = 0x080000,
PISP_BE_RGB_ENABLE_HOG = 0x200000
};
#define PISP_BE_RGB_ENABLE_CSC(i) (PISP_BE_RGB_ENABLE_CSC0 << (i))
#define PISP_BE_RGB_ENABLE_DOWNSCALE(i) (PISP_BE_RGB_ENABLE_DOWNSCALE0 << (i))
#define PISP_BE_RGB_ENABLE_RESAMPLE(i) (PISP_BE_RGB_ENABLE_RESAMPLE0 << (i))
#define PISP_BE_RGB_ENABLE_OUTPUT(i) (PISP_BE_RGB_ENABLE_OUTPUT0 << (i))
/*
* We use the enable flags to show when blocks are "dirty", but we need some
* extra ones too.
*/
enum pisp_be_dirty {
PISP_BE_DIRTY_GLOBAL = 0x0001,
PISP_BE_DIRTY_SH_FC_COMBINE = 0x0002,
PISP_BE_DIRTY_CROP = 0x0004
};
/**
* struct pisp_be_global_config - PiSP global enable bitmaps
* @bayer_enables: Bayer input enable flags
* @rgb_enables: RGB output enable flags
* @bayer_order: Bayer input format ordering
* @pad: Padding bytes
*/
struct pisp_be_global_config {
__u32 bayer_enables;
__u32 rgb_enables;
__u8 bayer_order;
__u8 pad[3];
} __attribute__((packed));
/**
* struct pisp_be_input_buffer_config - PiSP Back End input buffer
* @addr: Input buffer address
*/
struct pisp_be_input_buffer_config {
/* low 32 bits followed by high 32 bits (for each of up to 3 planes) */
__u32 addr[3][2];
} __attribute__((packed));
/**
* struct pisp_be_dpc_config - PiSP Back End DPC config
*
* Defective Pixel Correction configuration
*
* @coeff_level: Coefficient for the darkest neighbouring pixel value
* @coeff_range: Coefficient for the range of pixels for this Bayer channel
* @pad: Padding byte
* @flags: DPC configuration flags
*/
struct pisp_be_dpc_config {
__u8 coeff_level;
__u8 coeff_range;
__u8 pad;
#define PISP_BE_DPC_FLAG_FOLDBACK 1
__u8 flags;
} __attribute__((packed));
/**
* struct pisp_be_geq_config - PiSP Back End GEQ config
*
* Green Equalisation configuration
*
* @offset: Offset value for threshold calculation
* @slope_sharper: Slope/Sharper configuration
* @min: Minimum value the threshold may have
* @max: Maximum value the threshold may have
*/
struct pisp_be_geq_config {
__u16 offset;
#define PISP_BE_GEQ_SHARPER (1U << 15)
#define PISP_BE_GEQ_SLOPE ((1 << 10) - 1)
/* top bit is the "sharper" flag, slope value is bottom 10 bits */
__u16 slope_sharper;
__u16 min;
__u16 max;
} __attribute__((packed));
/**
* struct pisp_be_tdn_input_buffer_config - PiSP Back End TDN input buffer
* @addr: TDN input buffer address
*/
struct pisp_be_tdn_input_buffer_config {
/* low 32 bits followed by high 32 bits */
__u32 addr[2];
} __attribute__((packed));
/**
* struct pisp_be_tdn_config - PiSP Back End TDN config
*
* Temporal Denoise configuration
*
* @black_level: Black level value subtracted from pixels
* @ratio: Multiplier for the LTA input frame
* @noise_constant: Constant offset value used in noise estimation
* @noise_slope: Noise estimation multiplier
* @threshold: Threshold for TDN operations
* @reset: Disable TDN operations
* @pad: Padding byte
*/
struct pisp_be_tdn_config {
__u16 black_level;
__u16 ratio;
__u16 noise_constant;
__u16 noise_slope;
__u16 threshold;
__u8 reset;
__u8 pad;
} __attribute__((packed));
/**
* struct pisp_be_tdn_output_buffer_config - PiSP Back End TDN output buffer
* @addr: TDN output buffer address
*/
struct pisp_be_tdn_output_buffer_config {
/* low 32 bits followed by high 32 bits */
__u32 addr[2];
} __attribute__((packed));
/**
* struct pisp_be_sdn_config - PiSP Back End SDN config
*
* Spatial Denoise configuration
*
* @black_level: Black level subtracted from pixel for noise estimation
* @leakage: Proportion of the original undenoised value to mix in
* denoised output
* @pad: Padding byte
* @noise_constant: Noise constant used for noise estimation
* @noise_slope: Noise slope value used for noise estimation
* @noise_constant2: Second noise constant used for noise estimation
* @noise_slope2: Second slope value used for noise estimation
*/
struct pisp_be_sdn_config {
__u16 black_level;
__u8 leakage;
__u8 pad;
__u16 noise_constant;
__u16 noise_slope;
__u16 noise_constant2;
__u16 noise_slope2;
} __attribute__((packed));
/**
* struct pisp_be_stitch_input_buffer_config - PiSP Back End Stitch input
* @addr: Stitch input buffer address
*/
struct pisp_be_stitch_input_buffer_config {
/* low 32 bits followed by high 32 bits */
__u32 addr[2];
} __attribute__((packed));
#define PISP_BE_STITCH_STREAMING_LONG 0x8000
#define PISP_BE_STITCH_EXPOSURE_RATIO_MASK 0x7fff
/**
* struct pisp_be_stitch_config - PiSP Back End Stitch config
*
* Stitch block configuration
*
* @threshold_lo: Low threshold value
* @threshold_diff_power: Low and high threshold difference
* @pad: Padding bytes
* @exposure_ratio: Multiplier to convert long exposure pixels into
* short exposure pixels
* @motion_threshold_256: Motion threshold above which short exposure
* pixels are used
* @motion_threshold_recip: Reciprocal of motion_threshold_256 value
*/
struct pisp_be_stitch_config {
__u16 threshold_lo;
__u8 threshold_diff_power;
__u8 pad;
/* top bit indicates whether streaming input is the long exposure */
__u16 exposure_ratio;
__u8 motion_threshold_256;
__u8 motion_threshold_recip;
} __attribute__((packed));
/**
* struct pisp_be_stitch_output_buffer_config - PiSP Back End Stitch output
* @addr: Stitch input buffer address
*/
struct pisp_be_stitch_output_buffer_config {
/* low 32 bits followed by high 32 bits */
__u32 addr[2];
} __attribute__((packed));
/**
* struct pisp_be_cdn_config - PiSP Back End CDN config
*
* Colour Denoise configuration
*
* @thresh: Constant for noise estimation
* @iir_strength: Relative strength of the IIR part of the filter
* @g_adjust: Proportion of the change assigned to the G channel
*/
struct pisp_be_cdn_config {
__u16 thresh;
__u8 iir_strength;
__u8 g_adjust;
} __attribute__((packed));
#define PISP_BE_LSC_LOG_GRID_SIZE 5
#define PISP_BE_LSC_GRID_SIZE (1 << PISP_BE_LSC_LOG_GRID_SIZE)
#define PISP_BE_LSC_STEP_PRECISION 18
/**
* struct pisp_be_lsc_config - PiSP Back End LSC config
*
* Lens Shading Correction configuration
*
* @grid_step_x: Reciprocal of cell size width
* @grid_step_y: Reciprocal of cell size height
* @lut_packed: Jointly-coded RGB gains for each LSC grid
*/
struct pisp_be_lsc_config {
/* (1<<18) / grid_cell_width */
__u16 grid_step_x;
/* (1<<18) / grid_cell_height */
__u16 grid_step_y;
/* RGB gains jointly encoded in 32 bits */
#define PISP_BE_LSC_LUT_SIZE (PISP_BE_LSC_GRID_SIZE + 1)
__u32 lut_packed[PISP_BE_LSC_LUT_SIZE][PISP_BE_LSC_LUT_SIZE];
} __attribute__((packed));
/**
* struct pisp_be_lsc_extra - PiSP Back End LSC Extra config
* @offset_x: Horizontal offset into the LSC table of this tile
* @offset_y: Vertical offset into the LSC table of this tile
*/
struct pisp_be_lsc_extra {
__u16 offset_x;
__u16 offset_y;
} __attribute__((packed));
#define PISP_BE_CAC_LOG_GRID_SIZE 3
#define PISP_BE_CAC_GRID_SIZE (1 << PISP_BE_CAC_LOG_GRID_SIZE)
#define PISP_BE_CAC_STEP_PRECISION 20
/**
* struct pisp_be_cac_config - PiSP Back End CAC config
*
* Chromatic Aberration Correction config
*
* @grid_step_x: Reciprocal of cell size width
* @grid_step_y: Reciprocal of cell size height
* @lut: Pixel shift for the CAC grid
*/
struct pisp_be_cac_config {
/* (1<<20) / grid_cell_width */
__u16 grid_step_x;
/* (1<<20) / grid_cell_height */
__u16 grid_step_y;
/* [gridy][gridx][rb][xy] */
#define PISP_BE_CAC_LUT_SIZE (PISP_BE_CAC_GRID_SIZE + 1)
__s8 lut[PISP_BE_CAC_LUT_SIZE][PISP_BE_CAC_LUT_SIZE][2][2];
} __attribute__((packed));
/**
* struct pisp_be_cac_extra - PiSP Back End CAC extra config
* @offset_x: Horizontal offset into the CAC table of this tile
* @offset_y: Horizontal offset into the CAC table of this tile
*/
struct pisp_be_cac_extra {
__u16 offset_x;
__u16 offset_y;
} __attribute__((packed));
#define PISP_BE_DEBIN_NUM_COEFFS 4
/**
* struct pisp_be_debin_config - PiSP Back End Debin config
*
* Debinning configuration
*
* @coeffs: Filter coefficients for debinning
* @h_enable: Horizontal debinning enable
* @v_enable: Vertical debinning enable
* @pad: Padding bytes
*/
struct pisp_be_debin_config {
__s8 coeffs[PISP_BE_DEBIN_NUM_COEFFS];
__s8 h_enable;
__s8 v_enable;
__s8 pad[2];
} __attribute__((packed));
#define PISP_BE_TONEMAP_LUT_SIZE 64
/**
* struct pisp_be_tonemap_config - PiSP Back End Tonemap config
*
* Tonemapping configuration
*
* @detail_constant: Constant value for threshold calculation
* @detail_slope: Slope value for threshold calculation
* @iir_strength: Relative strength of the IIR fiter
* @strength: Strength factor
* @lut: Look-up table for tonemap curve
*/
struct pisp_be_tonemap_config {
__u16 detail_constant;
__u16 detail_slope;
__u16 iir_strength;
__u16 strength;
__u32 lut[PISP_BE_TONEMAP_LUT_SIZE];
} __attribute__((packed));
/**
* struct pisp_be_demosaic_config - PiSP Back End Demosaic config
*
* Demosaic configuration
*
* @sharper: Use other Bayer channels to increase sharpness
* @fc_mode: Built-in false colour suppression mode
* @pad: Padding bytes
*/
struct pisp_be_demosaic_config {
__u8 sharper;
__u8 fc_mode;
__u8 pad[2];
} __attribute__((packed));
/**
* struct pisp_be_ccm_config - PiSP Back End CCM config
*
* Colour Correction Matrix configuration
*
* @coeffs: Matrix coefficients
* @pad: Padding bytes
* @offsets: Offsets triplet
*/
struct pisp_be_ccm_config {
__s16 coeffs[9];
__u8 pad[2];
__s32 offsets[3];
} __attribute__((packed));
/**
* struct pisp_be_sat_control_config - PiSP Back End SAT config
*
* Saturation Control configuration
*
* @shift_r: Left shift for Red colour channel
* @shift_g: Left shift for Green colour channel
* @shift_b: Left shift for Blue colour channel
* @pad: Padding byte
*/
struct pisp_be_sat_control_config {
__u8 shift_r;
__u8 shift_g;
__u8 shift_b;
__u8 pad;
} __attribute__((packed));
/**
* struct pisp_be_false_colour_config - PiSP Back End False Colour config
*
* False Colour configuration
*
* @distance: Distance of neighbouring pixels, either 1 or 2
* @pad: Padding bytes
*/
struct pisp_be_false_colour_config {
__u8 distance;
__u8 pad[3];
} __attribute__((packed));
#define PISP_BE_SHARPEN_SIZE 5
#define PISP_BE_SHARPEN_FUNC_NUM_POINTS 9
/**
* struct pisp_be_sharpen_config - PiSP Back End Sharpening config
*
* Sharpening configuration
*
* @kernel0: Coefficient for filter 0
* @pad0: Padding byte
* @kernel1: Coefficient for filter 1
* @pad1: Padding byte
* @kernel2: Coefficient for filter 2
* @pad2: Padding byte
* @kernel3: Coefficient for filter 3
* @pad3: Padding byte
* @kernel4: Coefficient for filter 4
* @pad4: Padding byte
* @threshold_offset0: Offset for filter 0 response calculation
* @threshold_slope0: Slope multiplier for the filter 0 response calculation
* @scale0: Scale factor for filter 0 response calculation
* @pad5: Padding byte
* @threshold_offset1: Offset for filter 0 response calculation
* @threshold_slope1: Slope multiplier for the filter 0 response calculation
* @scale1: Scale factor for filter 0 response calculation
* @pad6: Padding byte
* @threshold_offset2: Offset for filter 0 response calculation
* @threshold_slope2: Slope multiplier for the filter 0 response calculation
* @scale2: Scale factor for filter 0 response calculation
* @pad7: Padding byte
* @threshold_offset3: Offset for filter 0 response calculation
* @threshold_slope3: Slope multiplier for the filter 0 response calculation
* @scale3: Scale factor for filter 0 response calculation
* @pad8: Padding byte
* @threshold_offset4: Offset for filter 0 response calculation
* @threshold_slope4: Slope multiplier for the filter 0 response calculation
* @scale4: Scale factor for filter 0 response calculation
* @pad9: Padding byte
* @positive_strength: Factor to scale the positive sharpening strength
* @positive_pre_limit: Maximum allowed possible positive sharpening value
* @positive_func: Gain factor applied to positive sharpening response
* @positive_limit: Final gain factor applied to positive sharpening
* @negative_strength: Factor to scale the negative sharpening strength
* @negative_pre_limit: Maximum allowed possible negative sharpening value
* @negative_func: Gain factor applied to negative sharpening response
* @negative_limit: Final gain factor applied to negative sharpening
* @enables: Filter enable mask
* @white: White output pixel filter mask
* @black: Black output pixel filter mask
* @grey: Grey output pixel filter mask
*/
struct pisp_be_sharpen_config {
__s8 kernel0[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
__s8 pad0[3];
__s8 kernel1[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
__s8 pad1[3];
__s8 kernel2[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
__s8 pad2[3];
__s8 kernel3[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
__s8 pad3[3];
__s8 kernel4[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
__s8 pad4[3];
__u16 threshold_offset0;
__u16 threshold_slope0;
__u16 scale0;
__u16 pad5;
__u16 threshold_offset1;
__u16 threshold_slope1;
__u16 scale1;
__u16 pad6;
__u16 threshold_offset2;
__u16 threshold_slope2;
__u16 scale2;
__u16 pad7;
__u16 threshold_offset3;
__u16 threshold_slope3;
__u16 scale3;
__u16 pad8;
__u16 threshold_offset4;
__u16 threshold_slope4;
__u16 scale4;
__u16 pad9;
__u16 positive_strength;
__u16 positive_pre_limit;
__u16 positive_func[PISP_BE_SHARPEN_FUNC_NUM_POINTS];
__u16 positive_limit;
__u16 negative_strength;
__u16 negative_pre_limit;
__u16 negative_func[PISP_BE_SHARPEN_FUNC_NUM_POINTS];
__u16 negative_limit;
__u8 enables;
__u8 white;
__u8 black;
__u8 grey;
} __attribute__((packed));
/**
* struct pisp_be_sh_fc_combine_config - PiSP Back End Sharpening and
* False Colour config
*
* Sharpening and False Colour configuration
*
* @y_factor: Control amount of desaturation of pixels being darkened
* @c1_factor: Control amount of brightening of a pixel for the Cb
* channel
* @c2_factor: Control amount of brightening of a pixel for the Cr
* channel
* @pad: Padding byte
*/
struct pisp_be_sh_fc_combine_config {
__u8 y_factor;
__u8 c1_factor;
__u8 c2_factor;
__u8 pad;
} __attribute__((packed));
#define PISP_BE_GAMMA_LUT_SIZE 64
/**
* struct pisp_be_gamma_config - PiSP Back End Gamma configuration
* @lut: Gamma curve look-up table
*/
struct pisp_be_gamma_config {
__u32 lut[PISP_BE_GAMMA_LUT_SIZE];
} __attribute__((packed));
/**
* struct pisp_be_crop_config - PiSP Back End Crop config
*
* Crop configuration
*
* @offset_x: Number of pixels cropped from the left of the tile
* @offset_y: Number of pixels cropped from the top of the tile
* @width: Width of the cropped tile output
* @height: Height of the cropped tile output
*/
struct pisp_be_crop_config {
__u16 offset_x, offset_y;
__u16 width, height;
} __attribute__((packed));
#define PISP_BE_RESAMPLE_FILTER_SIZE 96
/**
* struct pisp_be_resample_config - PiSP Back End Resampling config
*
* Resample configuration
*
* @scale_factor_h: Horizontal scale factor
* @scale_factor_v: Vertical scale factor
* @coef: Resample coefficients
*/
struct pisp_be_resample_config {
__u16 scale_factor_h, scale_factor_v;
__s16 coef[PISP_BE_RESAMPLE_FILTER_SIZE];
} __attribute__((packed));
/**
* struct pisp_be_resample_extra - PiSP Back End Resample config
*
* Resample configuration
*
* @scaled_width: Width in pixels of the scaled output
* @scaled_height: Height in pixels of the scaled output
* @initial_phase_h: Initial horizontal phase
* @initial_phase_v: Initial vertical phase
*/
struct pisp_be_resample_extra {
__u16 scaled_width;
__u16 scaled_height;
__s16 initial_phase_h[3];
__s16 initial_phase_v[3];
} __attribute__((packed));
/**
* struct pisp_be_downscale_config - PiSP Back End Downscale config
*
* Downscale configuration
*
* @scale_factor_h: Horizontal scale factor
* @scale_factor_v: Vertical scale factor
* @scale_recip_h: Horizontal reciprocal factor
* @scale_recip_v: Vertical reciprocal factor
*/
struct pisp_be_downscale_config {
__u16 scale_factor_h;
__u16 scale_factor_v;
__u16 scale_recip_h;
__u16 scale_recip_v;
} __attribute__((packed));
/**
* struct pisp_be_downscale_extra - PiSP Back End Downscale Extra config
* @scaled_width: Scaled image width
* @scaled_height: Scaled image height
*/
struct pisp_be_downscale_extra {
__u16 scaled_width;
__u16 scaled_height;
} __attribute__((packed));
/**
* struct pisp_be_hog_config - PiSP Back End HOG config
*
* Histogram of Oriented Gradients configuration
*
* @compute_signed: Set 0 for unsigned gradients, 1 for signed
* @channel_mix: Channels proportions to use
* @stride: Stride in bytes between blocks directly below
*/
struct pisp_be_hog_config {
__u8 compute_signed;
__u8 channel_mix[3];
__u32 stride;
} __attribute__((packed));
struct pisp_be_axi_config {
__u8 r_qos; /* Read QoS */
__u8 r_cache_prot; /* Read { prot[2:0], cache[3:0] } */
__u8 w_qos; /* Write QoS */
__u8 w_cache_prot; /* Write { prot[2:0], cache[3:0] } */
} __attribute__((packed));
/**
* enum pisp_be_transform - PiSP Back End Transform flags
* @PISP_BE_TRANSFORM_NONE: No transform
* @PISP_BE_TRANSFORM_HFLIP: Horizontal flip
* @PISP_BE_TRANSFORM_VFLIP: Vertical flip
* @PISP_BE_TRANSFORM_ROT180: 180 degress rotation
*/
enum pisp_be_transform {
PISP_BE_TRANSFORM_NONE = 0x0,
PISP_BE_TRANSFORM_HFLIP = 0x1,
PISP_BE_TRANSFORM_VFLIP = 0x2,
PISP_BE_TRANSFORM_ROT180 =
(PISP_BE_TRANSFORM_HFLIP | PISP_BE_TRANSFORM_VFLIP)
};
struct pisp_be_output_format_config {
struct pisp_image_format_config image;
__u8 transform;
__u8 pad[3];
__u16 lo;
__u16 hi;
__u16 lo2;
__u16 hi2;
} __attribute__((packed));
/**
* struct pisp_be_output_buffer_config - PiSP Back End Output buffer
* @addr: Output buffer address
*/
struct pisp_be_output_buffer_config {
/* low 32 bits followed by high 32 bits (for each of 3 planes) */
__u32 addr[3][2];
} __attribute__((packed));
/**
* struct pisp_be_hog_buffer_config - PiSP Back End HOG buffer
* @addr: HOG buffer address
*/
struct pisp_be_hog_buffer_config {
/* low 32 bits followed by high 32 bits */
__u32 addr[2];
} __attribute__((packed));
/**
* struct pisp_be_config - RaspberryPi PiSP Back End Processing configuration
*
* @input_buffer: Input buffer addresses
* @tdn_input_buffer: TDN input buffer addresses
* @stitch_input_buffer: Stitch input buffer addresses
* @tdn_output_buffer: TDN output buffer addresses
* @stitch_output_buffer: Stitch output buffer addresses
* @output_buffer: Output buffers addresses
* @hog_buffer: HOG buffer addresses
* @global: Global PiSP configuration
* @input_format: Input image format
* @decompress: Decompress configuration
* @dpc: Defective Pixel Correction configuration
* @geq: Green Equalisation configuration
* @tdn_input_format: Temporal Denoise input format
* @tdn_decompress: Temporal Denoise decompress configuration
* @tdn: Temporal Denoise configuration
* @tdn_compress: Temporal Denoise compress configuration
* @tdn_output_format: Temporal Denoise output format
* @sdn: Spatial Denoise configuration
* @blc: Black Level Correction configuration
* @stitch_compress: Stitch compress configuration
* @stitch_output_format: Stitch output format
* @stitch_input_format: Stitch input format
* @stitch_decompress: Stitch decompress configuration
* @stitch: Stitch configuration
* @lsc: Lens Shading Correction configuration
* @wbg: White Balance Gain configuration
* @cdn: Colour Denoise configuration
* @cac: Colour Aberration Correction configuration
* @debin: Debinning configuration
* @tonemap: Tonemapping configuration
* @demosaic: Demosaicing configuration
* @ccm: Colour Correction Matrix configuration
* @sat_control: Saturation Control configuration
* @ycbcr: YCbCr colour correction configuration
* @sharpen: Sharpening configuration
* @false_colour: False colour correction
* @sh_fc_combine: Sharpening and False Colour correction
* @ycbcr_inverse: Inverse YCbCr colour correction
* @gamma: Gamma curve configuration
* @csc: Color Space Conversion configuration
* @downscale: Downscale configuration
* @resample: Resampling configuration
* @output_format: Output format configuration
* @hog: HOG configuration
* @axi: AXI bus configuration
* @lsc_extra: LSC extra info
* @cac_extra: CAC extra info
* @downscale_extra: Downscaler extra info
* @resample_extra: Resample extra info
* @crop: Crop configuration
* @hog_format: HOG format info
* @dirty_flags_bayer: Bayer enable dirty flags
* (:c:type:`pisp_be_bayer_enable`)
* @dirty_flags_rgb: RGB enable dirty flags
* (:c:type:`pisp_be_rgb_enable`)
* @dirty_flags_extra: Extra dirty flags
*/
struct pisp_be_config {
/* I/O configuration: */
struct pisp_be_input_buffer_config input_buffer;
struct pisp_be_tdn_input_buffer_config tdn_input_buffer;
struct pisp_be_stitch_input_buffer_config stitch_input_buffer;
struct pisp_be_tdn_output_buffer_config tdn_output_buffer;
struct pisp_be_stitch_output_buffer_config stitch_output_buffer;
struct pisp_be_output_buffer_config
output_buffer[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_hog_buffer_config hog_buffer;
/* Processing configuration: */
struct pisp_be_global_config global;
struct pisp_image_format_config input_format;
struct pisp_decompress_config decompress;
struct pisp_be_dpc_config dpc;
struct pisp_be_geq_config geq;
struct pisp_image_format_config tdn_input_format;
struct pisp_decompress_config tdn_decompress;
struct pisp_be_tdn_config tdn;
struct pisp_compress_config tdn_compress;
struct pisp_image_format_config tdn_output_format;
struct pisp_be_sdn_config sdn;
struct pisp_bla_config blc;
struct pisp_compress_config stitch_compress;
struct pisp_image_format_config stitch_output_format;
struct pisp_image_format_config stitch_input_format;
struct pisp_decompress_config stitch_decompress;
struct pisp_be_stitch_config stitch;
struct pisp_be_lsc_config lsc;
struct pisp_wbg_config wbg;
struct pisp_be_cdn_config cdn;
struct pisp_be_cac_config cac;
struct pisp_be_debin_config debin;
struct pisp_be_tonemap_config tonemap;
struct pisp_be_demosaic_config demosaic;
struct pisp_be_ccm_config ccm;
struct pisp_be_sat_control_config sat_control;
struct pisp_be_ccm_config ycbcr;
struct pisp_be_sharpen_config sharpen;
struct pisp_be_false_colour_config false_colour;
struct pisp_be_sh_fc_combine_config sh_fc_combine;
struct pisp_be_ccm_config ycbcr_inverse;
struct pisp_be_gamma_config gamma;
struct pisp_be_ccm_config csc[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_downscale_config downscale[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_resample_config resample[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_output_format_config
output_format[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_hog_config hog;
struct pisp_be_axi_config axi;
/* Non-register fields: */
struct pisp_be_lsc_extra lsc_extra;
struct pisp_be_cac_extra cac_extra;
struct pisp_be_downscale_extra
downscale_extra[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_resample_extra resample_extra[PISP_BACK_END_NUM_OUTPUTS];
struct pisp_be_crop_config crop;
struct pisp_image_format_config hog_format;
__u32 dirty_flags_bayer; /* these use pisp_be_bayer_enable */
__u32 dirty_flags_rgb; /* use pisp_be_rgb_enable */
__u32 dirty_flags_extra; /* these use pisp_be_dirty_t */
} __attribute__((packed));
/**
* enum pisp_tile_edge - PiSP Back End Tile position
* @PISP_LEFT_EDGE: Left edge tile
* @PISP_RIGHT_EDGE: Right edge tile
* @PISP_TOP_EDGE: Top edge tile
* @PISP_BOTTOM_EDGE: Bottom edge tile
*/
enum pisp_tile_edge {
PISP_LEFT_EDGE = (1 << 0),
PISP_RIGHT_EDGE = (1 << 1),
PISP_TOP_EDGE = (1 << 2),
PISP_BOTTOM_EDGE = (1 << 3)
};
/**
* struct pisp_tile - Raspberry Pi PiSP Back End tile configuration
*
* Tile parameters: each set of tile parameters is a 160-bytes block of data
* which contains the tile processing parameters.
*
* @edge: Edge tile flag
* @pad0: Padding bytes
* @input_addr_offset: Top-left pixel offset, in bytes
* @input_addr_offset2: Top-left pixel offset, in bytes for the second/
* third image planes
* @input_offset_x: Horizontal offset in pixels of this tile in the
* input image
* @input_offset_y: Vertical offset in pixels of this tile in the
* input image
* @input_width: Width in pixels of this tile
* @input_height: Height in pixels of the this tile
* @tdn_input_addr_offset: TDN input image offset, in bytes
* @tdn_output_addr_offset: TDN output image offset, in bytes
* @stitch_input_addr_offset: Stitch input image offset, in bytes
* @stitch_output_addr_offset: Stitch output image offset, in bytes
* @lsc_grid_offset_x: Horizontal offset in the LSC table for this tile
* @lsc_grid_offset_y: Vertical offset in the LSC table for this tile
* @cac_grid_offset_x: Horizontal offset in the CAC table for this tile
* @cac_grid_offset_y: Horizontal offset in the CAC table for this tile
* @crop_x_start: Number of pixels cropped from the left of the
* tile
* @crop_x_end: Number of pixels cropped from the right of the
* tile
* @crop_y_start: Number of pixels cropped from the top of the
* tile
* @crop_y_end: Number of pixels cropped from the bottom of the
* tile
* @downscale_phase_x: Initial horizontal phase in pixels
* @downscale_phase_y: Initial vertical phase in pixels
* @resample_in_width: Width in pixels of the tile entering the
* Resample block
* @resample_in_height: Height in pixels of the tile entering the
* Resample block
* @resample_phase_x: Initial horizontal phase for the Resample block
* @resample_phase_y: Initial vertical phase for the Resample block
* @output_offset_x: Horizontal offset in pixels where the tile will
* be written into the output image
* @output_offset_y: Vertical offset in pixels where the tile will be
* written into the output image
* @output_width: Width in pixels in the output image of this tile
* @output_height: Height in pixels in the output image of this tile
* @output_addr_offset: Offset in bytes into the output buffer
* @output_addr_offset2: Offset in bytes into the output buffer for the
* second and third plane
* @output_hog_addr_offset: Offset in bytes into the HOG buffer where
* results of this tile are to be written
*/
struct pisp_tile {
__u8 edge; /* enum pisp_tile_edge */
__u8 pad0[3];
/* 4 bytes */
__u32 input_addr_offset;
__u32 input_addr_offset2;
__u16 input_offset_x;
__u16 input_offset_y;
__u16 input_width;
__u16 input_height;
/* 20 bytes */
__u32 tdn_input_addr_offset;
__u32 tdn_output_addr_offset;
__u32 stitch_input_addr_offset;
__u32 stitch_output_addr_offset;
/* 36 bytes */
__u32 lsc_grid_offset_x;
__u32 lsc_grid_offset_y;
/* 44 bytes */
__u32 cac_grid_offset_x;
__u32 cac_grid_offset_y;
/* 52 bytes */
__u16 crop_x_start[PISP_BACK_END_NUM_OUTPUTS];
__u16 crop_x_end[PISP_BACK_END_NUM_OUTPUTS];
__u16 crop_y_start[PISP_BACK_END_NUM_OUTPUTS];
__u16 crop_y_end[PISP_BACK_END_NUM_OUTPUTS];
/* 68 bytes */
/* Ordering is planes then branches */
__u16 downscale_phase_x[3 * PISP_BACK_END_NUM_OUTPUTS];
__u16 downscale_phase_y[3 * PISP_BACK_END_NUM_OUTPUTS];
/* 92 bytes */
__u16 resample_in_width[PISP_BACK_END_NUM_OUTPUTS];
__u16 resample_in_height[PISP_BACK_END_NUM_OUTPUTS];
/* 100 bytes */
/* Ordering is planes then branches */
__u16 resample_phase_x[3 * PISP_BACK_END_NUM_OUTPUTS];
__u16 resample_phase_y[3 * PISP_BACK_END_NUM_OUTPUTS];
/* 124 bytes */
__u16 output_offset_x[PISP_BACK_END_NUM_OUTPUTS];
__u16 output_offset_y[PISP_BACK_END_NUM_OUTPUTS];
__u16 output_width[PISP_BACK_END_NUM_OUTPUTS];
__u16 output_height[PISP_BACK_END_NUM_OUTPUTS];
/* 140 bytes */
__u32 output_addr_offset[PISP_BACK_END_NUM_OUTPUTS];
__u32 output_addr_offset2[PISP_BACK_END_NUM_OUTPUTS];
/* 156 bytes */
__u32 output_hog_addr_offset;
/* 160 bytes */
} __attribute__((packed));
/**
* struct pisp_be_tiles_config - Raspberry Pi PiSP Back End configuration
* @tiles: Tile descriptors
* @num_tiles: Number of tiles
* @config: PiSP Back End configuration
*/
struct pisp_be_tiles_config {
struct pisp_be_config config;
struct pisp_tile tiles[PISP_BACK_END_NUM_TILES];
__u32 num_tiles;
} __attribute__((packed));
#endif /* _UAPI_PISP_BE_CONFIG_H_ */
linux-7.2.3/include/uapi/linux/media/raspberrypi/pisp_common.h
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* RP1 PiSP common definitions.
*
* Copyright (C) 2021 - Raspberry Pi Ltd.
*
*/
#ifndef _UAPI_PISP_COMMON_H_
#define _UAPI_PISP_COMMON_H_
#include <linux/types.h>
struct pisp_image_format_config {
/* size in pixels */
__u16 width;
__u16 height;
/* must match struct pisp_image_format below */
__u32 format;
__s32 stride;
/* some planar image formats will need a second stride */
__s32 stride2;
} __attribute__((packed));
enum pisp_bayer_order {
/*
* Note how bayer_order&1 tells you if G is on the even pixels of the
* checkerboard or not, and bayer_order&2 tells you if R is on the even
* rows or is swapped with B. Note that if the top (of the 8) bits is
* set, this denotes a monochrome or greyscale image, and the lower bits
* should all be ignored.
*/
PISP_BAYER_ORDER_RGGB = 0,
PISP_BAYER_ORDER_GBRG = 1,
PISP_BAYER_ORDER_BGGR = 2,
PISP_BAYER_ORDER_GRBG = 3,
PISP_BAYER_ORDER_GREYSCALE = 128
};
enum pisp_image_format {
/*
* Precise values are mostly tbd. Generally these will be portmanteau
* values comprising bit fields and flags. This format must be shared
* throughout the PiSP.
*/
PISP_IMAGE_FORMAT_BPS_8 = 0x00000000,
PISP_IMAGE_FORMAT_BPS_10 = 0x00000001,
PISP_IMAGE_FORMAT_BPS_12 = 0x00000002,
PISP_IMAGE_FORMAT_BPS_16 = 0x00000003,
PISP_IMAGE_FORMAT_BPS_MASK = 0x00000003,
PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED = 0x00000000,
PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR = 0x00000010,
PISP_IMAGE_FORMAT_PLANARITY_PLANAR = 0x00000020,
PISP_IMAGE_FORMAT_PLANARITY_MASK = 0x00000030,
PISP_IMAGE_FORMAT_SAMPLING_444 = 0x00000000,
PISP_IMAGE_FORMAT_SAMPLING_422 = 0x00000100,
PISP_IMAGE_FORMAT_SAMPLING_420 = 0x00000200,
PISP_IMAGE_FORMAT_SAMPLING_MASK = 0x00000300,
PISP_IMAGE_FORMAT_ORDER_NORMAL = 0x00000000,
PISP_IMAGE_FORMAT_ORDER_SWAPPED = 0x00001000,
PISP_IMAGE_FORMAT_SHIFT_0 = 0x00000000,
PISP_IMAGE_FORMAT_SHIFT_1 = 0x00010000,
PISP_IMAGE_FORMAT_SHIFT_2 = 0x00020000,
PISP_IMAGE_FORMAT_SHIFT_3 = 0x00030000,
PISP_IMAGE_FORMAT_SHIFT_4 = 0x00040000,
PISP_IMAGE_FORMAT_SHIFT_5 = 0x00050000,
PISP_IMAGE_FORMAT_SHIFT_6 = 0x00060000,
PISP_IMAGE_FORMAT_SHIFT_7 = 0x00070000,
PISP_IMAGE_FORMAT_SHIFT_8 = 0x00080000,
PISP_IMAGE_FORMAT_SHIFT_MASK = 0x000f0000,
PISP_IMAGE_FORMAT_BPP_32 = 0x00100000,
PISP_IMAGE_FORMAT_UNCOMPRESSED = 0x00000000,
PISP_IMAGE_FORMAT_COMPRESSION_MODE_1 = 0x01000000,
PISP_IMAGE_FORMAT_COMPRESSION_MODE_2 = 0x02000000,
PISP_IMAGE_FORMAT_COMPRESSION_MODE_3 = 0x03000000,
PISP_IMAGE_FORMAT_COMPRESSION_MASK = 0x03000000,
PISP_IMAGE_FORMAT_HOG_SIGNED = 0x04000000,
PISP_IMAGE_FORMAT_HOG_UNSIGNED = 0x08000000,
PISP_IMAGE_FORMAT_INTEGRAL_IMAGE = 0x10000000,
PISP_IMAGE_FORMAT_WALLPAPER_ROLL = 0x20000000,
PISP_IMAGE_FORMAT_THREE_CHANNEL = 0x40000000,
/* Lastly a few specific instantiations of the above. */
PISP_IMAGE_FORMAT_SINGLE_16 = PISP_IMAGE_FORMAT_BPS_16,
PISP_IMAGE_FORMAT_THREE_16 = PISP_IMAGE_FORMAT_BPS_16 |
PISP_IMAGE_FORMAT_THREE_CHANNEL
};
#define PISP_IMAGE_FORMAT_BPS_8(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_8)
#define PISP_IMAGE_FORMAT_BPS_10(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_10)
#define PISP_IMAGE_FORMAT_BPS_12(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_12)
#define PISP_IMAGE_FORMAT_BPS_16(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_16)
#define PISP_IMAGE_FORMAT_BPS(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) ? \
8 + (2 << (((fmt) & PISP_IMAGE_FORMAT_BPS_MASK) - 1)) : 8)
#define PISP_IMAGE_FORMAT_SHIFT(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_SHIFT_MASK) / PISP_IMAGE_FORMAT_SHIFT_1)
#define PISP_IMAGE_FORMAT_THREE_CHANNEL(fmt) \
((fmt) & PISP_IMAGE_FORMAT_THREE_CHANNEL)
#define PISP_IMAGE_FORMAT_SINGLE_CHANNEL(fmt) \
(!((fmt) & PISP_IMAGE_FORMAT_THREE_CHANNEL))
#define PISP_IMAGE_FORMAT_COMPRESSED(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_COMPRESSION_MASK) != \
PISP_IMAGE_FORMAT_UNCOMPRESSED)
#define PISP_IMAGE_FORMAT_SAMPLING_444(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_SAMPLING_MASK) == \
PISP_IMAGE_FORMAT_SAMPLING_444)
#define PISP_IMAGE_FORMAT_SAMPLING_422(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_SAMPLING_MASK) == \
PISP_IMAGE_FORMAT_SAMPLING_422)
#define PISP_IMAGE_FORMAT_SAMPLING_420(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_SAMPLING_MASK) == \
PISP_IMAGE_FORMAT_SAMPLING_420)
#define PISP_IMAGE_FORMAT_ORDER_NORMAL(fmt) \
(!((fmt) & PISP_IMAGE_FORMAT_ORDER_SWAPPED))
#define PISP_IMAGE_FORMAT_ORDER_SWAPPED(fmt) \
((fmt) & PISP_IMAGE_FORMAT_ORDER_SWAPPED)
#define PISP_IMAGE_FORMAT_INTERLEAVED(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_PLANARITY_MASK) == \
PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED)
#define PISP_IMAGE_FORMAT_SEMIPLANAR(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_PLANARITY_MASK) == \
PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR)
#define PISP_IMAGE_FORMAT_PLANAR(fmt) \
(((fmt) & PISP_IMAGE_FORMAT_PLANARITY_MASK) == \
PISP_IMAGE_FORMAT_PLANARITY_PLANAR)
#define PISP_IMAGE_FORMAT_WALLPAPER(fmt) \
((fmt) & PISP_IMAGE_FORMAT_WALLPAPER_ROLL)
#define PISP_IMAGE_FORMAT_BPP_32(fmt) ((fmt) & PISP_IMAGE_FORMAT_BPP_32)
#define PISP_IMAGE_FORMAT_HOG(fmt) \
((fmt) & \
(PISP_IMAGE_FORMAT_HOG_SIGNED | PISP_IMAGE_FORMAT_HOG_UNSIGNED))
#define PISP_WALLPAPER_WIDTH 128 /* in bytes */
struct pisp_bla_config {
__u16 black_level_r;
__u16 black_level_gr;
__u16 black_level_gb;
__u16 black_level_b;
__u16 output_black_level;
__u8 pad[2];
} __attribute__((packed));
struct pisp_wbg_config {
__u16 gain_r;
__u16 gain_g;
__u16 gain_b;
__u8 pad[2];
} __attribute__((packed));
struct pisp_compress_config {
/* value subtracted from incoming data */
__u16 offset;
__u8 pad;
/* 1 => Companding; 2 => Delta (recommended); 3 => Combined (for HDR) */
__u8 mode;
} __attribute__((packed));
struct pisp_decompress_config {
/* value added to reconstructed data */
__u16 offset;
__u8 pad;
/* 1 => Companding; 2 => Delta (recommended); 3 => Combined (for HDR) */
__u8 mode;
} __attribute__((packed));
enum pisp_axi_flags {
/*
* round down bursts to end at a 32-byte boundary, to align following
* bursts
*/
PISP_AXI_FLAG_ALIGN = 128,
/* for FE writer: force WSTRB high, to pad output to 16-byte boundary */
PISP_AXI_FLAG_PAD = 64,
/* for FE writer: Use Output FIFO level to trigger "panic" */
PISP_AXI_FLAG_PANIC = 32,
};
struct pisp_axi_config {
/*
* burst length minus one, which must be in the range 0:15; OR'd with
* flags
*/
__u8 maxlen_flags;
/* { prot[2:0], cache[3:0] } fields, echoed on AXI bus */
__u8 cache_prot;
/* QoS field(s) (4x4 bits for FE writer; 4 bits for other masters) */
__u16 qos;
} __attribute__((packed));
#endif /* _UAPI_PISP_COMMON_H_ */
linux-7.2.3/include/uapi/linux/media/raspberrypi/pisp_fe_config.h
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* RP1 PiSP Front End Driver Configuration structures
*
* Copyright (C) 2021 - Raspberry Pi Ltd.
*
*/
#ifndef _UAPI_PISP_FE_CONFIG_
#define _UAPI_PISP_FE_CONFIG_
#include <linux/types.h>
#include "pisp_common.h"
#include "pisp_fe_statistics.h"
#define PISP_FE_NUM_OUTPUTS 2
enum pisp_fe_enable {
PISP_FE_ENABLE_INPUT = 0x000001,
PISP_FE_ENABLE_DECOMPRESS = 0x000002,
PISP_FE_ENABLE_DECOMPAND = 0x000004,
PISP_FE_ENABLE_BLA = 0x000008,
PISP_FE_ENABLE_DPC = 0x000010,
PISP_FE_ENABLE_STATS_CROP = 0x000020,
PISP_FE_ENABLE_DECIMATE = 0x000040,
PISP_FE_ENABLE_BLC = 0x000080,
PISP_FE_ENABLE_CDAF_STATS = 0x000100,
PISP_FE_ENABLE_AWB_STATS = 0x000200,
PISP_FE_ENABLE_RGBY = 0x000400,
PISP_FE_ENABLE_LSC = 0x000800,
PISP_FE_ENABLE_AGC_STATS = 0x001000,
PISP_FE_ENABLE_CROP0 = 0x010000,
PISP_FE_ENABLE_DOWNSCALE0 = 0x020000,
PISP_FE_ENABLE_COMPRESS0 = 0x040000,
PISP_FE_ENABLE_OUTPUT0 = 0x080000,
PISP_FE_ENABLE_CROP1 = 0x100000,
PISP_FE_ENABLE_DOWNSCALE1 = 0x200000,
PISP_FE_ENABLE_COMPRESS1 = 0x400000,
PISP_FE_ENABLE_OUTPUT1 = 0x800000
};
#define PISP_FE_ENABLE_CROP(i) (PISP_FE_ENABLE_CROP0 << (4 * (i)))
#define PISP_FE_ENABLE_DOWNSCALE(i) (PISP_FE_ENABLE_DOWNSCALE0 << (4 * (i)))
#define PISP_FE_ENABLE_COMPRESS(i) (PISP_FE_ENABLE_COMPRESS0 << (4 * (i)))
#define PISP_FE_ENABLE_OUTPUT(i) (PISP_FE_ENABLE_OUTPUT0 << (4 * (i)))
/*
* We use the enable flags to show when blocks are "dirty", but we need some
* extra ones too.
*/
enum pisp_fe_dirty {
PISP_FE_DIRTY_GLOBAL = 0x0001,
PISP_FE_DIRTY_FLOATING = 0x0002,
PISP_FE_DIRTY_OUTPUT_AXI = 0x0004
};
struct pisp_fe_global_config {
__u32 enables;
__u8 bayer_order;
__u8 pad[3];
} __attribute__((packed));
struct pisp_fe_input_axi_config {
/* burst length minus one, in the range 0..15; OR'd with flags */
__u8 maxlen_flags;
/* { prot[2:0], cache[3:0] } fields */
__u8 cache_prot;
/* QoS (only 4 LS bits are used) */
__u16 qos;
} __attribute__((packed));
struct pisp_fe_output_axi_config {
/* burst length minus one, in the range 0..15; OR'd with flags */
__u8 maxlen_flags;
/* { prot[2:0], cache[3:0] } fields */
__u8 cache_prot;
/* QoS (4 bitfields of 4 bits each for different panic levels) */
__u16 qos;
/* For Panic mode: Output FIFO panic threshold */
__u16 thresh;
/* For Panic mode: Output FIFO statistics throttle threshold */
__u16 throttle;
} __attribute__((packed));
struct pisp_fe_input_config {
__u8 streaming;
__u8 pad[3];
struct pisp_image_format_config format;
struct pisp_fe_input_axi_config axi;
/* Extra cycles delay before issuing each burst request */
__u8 holdoff;
__u8 pad2[3];
} __attribute__((packed));
struct pisp_fe_output_config {
struct pisp_image_format_config format;
__u16 ilines;
__u8 pad[2];
} __attribute__((packed));
struct pisp_fe_input_buffer_config {
__u32 addr_lo;
__u32 addr_hi;
__u16 frame_id;
__u16 pad;
} __attribute__((packed));
#define PISP_FE_DECOMPAND_LUT_SIZE 65
struct pisp_fe_decompand_config {
__u16 lut[PISP_FE_DECOMPAND_LUT_SIZE];
__u16 pad;
} __attribute__((packed));
struct pisp_fe_dpc_config {
__u8 coeff_level;
__u8 coeff_range;
__u8 coeff_range2;
#define PISP_FE_DPC_FLAG_FOLDBACK 1
#define PISP_FE_DPC_FLAG_VFLAG 2
__u8 flags;
} __attribute__((packed));
#define PISP_FE_LSC_LUT_SIZE 16
struct pisp_fe_lsc_config {
__u8 shift;
__u8 pad0;
__u16 scale;
__u16 centre_x;
__u16 centre_y;
__u16 lut[PISP_FE_LSC_LUT_SIZE];
} __attribute__((packed));
struct pisp_fe_rgby_config {
__u16 gain_r;
__u16 gain_g;
__u16 gain_b;
__u8 maxflag;
__u8 pad;
} __attribute__((packed));
struct pisp_fe_agc_stats_config {
__u16 offset_x;
__u16 offset_y;
__u16 size_x;
__u16 size_y;
/* each weight only 4 bits */
__u8 weights[PISP_AGC_STATS_NUM_ZONES / 2];
__u16 row_offset_x;
__u16 row_offset_y;
__u16 row_size_x;
__u16 row_size_y;
__u8 row_shift;
__u8 float_shift;
__u8 pad1[2];
} __attribute__((packed));
struct pisp_fe_awb_stats_config {
__u16 offset_x;
__u16 offset_y;
__u16 size_x;
__u16 size_y;
__u8 shift;
__u8 pad[3];
__u16 r_lo;
__u16 r_hi;
__u16 g_lo;
__u16 g_hi;
__u16 b_lo;
__u16 b_hi;
} __attribute__((packed));
struct pisp_fe_floating_stats_region {
__u16 offset_x;
__u16 offset_y;
__u16 size_x;
__u16 size_y;
} __attribute__((packed));
struct pisp_fe_floating_stats_config {
struct pisp_fe_floating_stats_region
regions[PISP_FLOATING_STATS_NUM_ZONES];
} __attribute__((packed));
#define PISP_FE_CDAF_NUM_WEIGHTS 8
struct pisp_fe_cdaf_stats_config {
__u16 noise_constant;
__u16 noise_slope;
__u16 offset_x;
__u16 offset_y;
__u16 size_x;
__u16 size_y;
__u16 skip_x;
__u16 skip_y;
__u32 mode;
} __attribute__((packed));
struct pisp_fe_stats_buffer_config {
__u32 addr_lo;
__u32 addr_hi;
} __attribute__((packed));
struct pisp_fe_crop_config {
__u16 offset_x;
__u16 offset_y;
__u16 width;
__u16 height;
} __attribute__((packed));
enum pisp_fe_downscale_flags {
/* downscale the four Bayer components independently... */
DOWNSCALE_BAYER = 1,
/* ...without trying to preserve their spatial relationship */
DOWNSCALE_BIN = 2,
};
struct pisp_fe_downscale_config {
__u8 xin;
__u8 xout;
__u8 yin;
__u8 yout;
__u8 flags; /* enum pisp_fe_downscale_flags */
__u8 pad[3];
__u16 output_width;
__u16 output_height;
} __attribute__((packed));
struct pisp_fe_output_buffer_config {
__u32 addr_lo;
__u32 addr_hi;
} __attribute__((packed));
/* Each of the two output channels/branches: */
struct pisp_fe_output_branch_config {
struct pisp_fe_crop_config crop;
struct pisp_fe_downscale_config downscale;
struct pisp_compress_config compress;
struct pisp_fe_output_config output;
__u32 pad;
} __attribute__((packed));
/* And finally one to rule them all: */
struct pisp_fe_config {
/* I/O configuration: */
struct pisp_fe_stats_buffer_config stats_buffer;
struct pisp_fe_output_buffer_config output_buffer[PISP_FE_NUM_OUTPUTS];
struct pisp_fe_input_buffer_config input_buffer;
/* processing configuration: */
struct pisp_fe_global_config global;
struct pisp_fe_input_config input;
struct pisp_decompress_config decompress;
struct pisp_fe_decompand_config decompand;
struct pisp_bla_config bla;
struct pisp_fe_dpc_config dpc;
struct pisp_fe_crop_config stats_crop;
__u32 spare1; /* placeholder for future decimate configuration */
struct pisp_bla_config blc;
struct pisp_fe_rgby_config rgby;
struct pisp_fe_lsc_config lsc;
struct pisp_fe_agc_stats_config agc_stats;
struct pisp_fe_awb_stats_config awb_stats;
struct pisp_fe_cdaf_stats_config cdaf_stats;
struct pisp_fe_floating_stats_config floating_stats;
struct pisp_fe_output_axi_config output_axi;
struct pisp_fe_output_branch_config ch[PISP_FE_NUM_OUTPUTS];
/* non-register fields: */
__u32 dirty_flags; /* these use pisp_fe_enable */
__u32 dirty_flags_extra; /* these use pisp_fe_dirty */
} __attribute__((packed));
#endif /* _UAPI_PISP_FE_CONFIG_ */
linux-7.2.3/include/uapi/linux/media/raspberrypi/pisp_fe_statistics.h
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* RP1 PiSP Front End statistics definitions
*
* Copyright (C) 2021 - Raspberry Pi Ltd.
*
*/
#ifndef _UAPI_PISP_FE_STATISTICS_H_
#define _UAPI_PISP_FE_STATISTICS_H_
#include <linux/types.h>
#define PISP_FLOATING_STATS_NUM_ZONES 4
#define PISP_AGC_STATS_NUM_BINS 1024
#define PISP_AGC_STATS_SIZE 16
#define PISP_AGC_STATS_NUM_ZONES (PISP_AGC_STATS_SIZE * PISP_AGC_STATS_SIZE)
#define PISP_AGC_STATS_NUM_ROW_SUMS 512
struct pisp_agc_statistics_zone {
__u64 Y_sum;
__u32 counted;
__u32 pad;
} __attribute__((packed));
struct pisp_agc_statistics {
__u32 row_sums[PISP_AGC_STATS_NUM_ROW_SUMS];
/*
* 32-bits per bin means an image (just less than) 16384x16384 pixels
* in size can weight every pixel from 0 to 15.
*/
__u32 histogram[PISP_AGC_STATS_NUM_BINS];
struct pisp_agc_statistics_zone floating[PISP_FLOATING_STATS_NUM_ZONES];
} __attribute__((packed));
#define PISP_AWB_STATS_SIZE 32
#define PISP_AWB_STATS_NUM_ZONES (PISP_AWB_STATS_SIZE * PISP_AWB_STATS_SIZE)
struct pisp_awb_statistics_zone {
__u32 R_sum;
__u32 G_sum;
__u32 B_sum;
__u32 counted;
} __attribute__((packed));
struct pisp_awb_statistics {
struct pisp_awb_statistics_zone zones[PISP_AWB_STATS_NUM_ZONES];
struct pisp_awb_statistics_zone floating[PISP_FLOATING_STATS_NUM_ZONES];
} __attribute__((packed));
#define PISP_CDAF_STATS_SIZE 8
#define PISP_CDAF_STATS_NUM_FOMS (PISP_CDAF_STATS_SIZE * PISP_CDAF_STATS_SIZE)
struct pisp_cdaf_statistics {
__u64 foms[PISP_CDAF_STATS_NUM_FOMS];
__u64 floating[PISP_FLOATING_STATS_NUM_ZONES];
} __attribute__((packed));
struct pisp_statistics {
struct pisp_awb_statistics awb;
struct pisp_agc_statistics agc;
struct pisp_cdaf_statistics cdaf;
} __attribute__((packed));
#endif /* _UAPI_PISP_FE_STATISTICS_H_ */
linux-7.2.3/include/uapi/linux/media/v4l2-isp.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Video4Linux2 generic ISP parameters and statistics support
*
* Copyright (C) 2025 Ideas On Board Oy
* Author: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
*/
#ifndef _UAPI_V4L2_ISP_H_
#define _UAPI_V4L2_ISP_H_
#include <linux/stddef.h>
#include <linux/types.h>
/**
* enum v4l2_isp_params_version - V4L2 ISP parameters versioning
*
* @V4L2_ISP_PARAMS_VERSION_V0: First version of the V4L2 ISP parameters format
* (for compatibility)
* @V4L2_ISP_PARAMS_VERSION_V1: First version of the V4L2 ISP parameters format
*
* V0 and V1 are identical in order to support drivers compatible with the V4L2
* ISP parameters format already upstreamed which use either 0 or 1 as their
* versioning identifier. Both V0 and V1 refers to the first version of the
* V4L2 ISP parameters format.
*
* Future revisions of the V4L2 ISP parameters format should start from the
* value of 2.
*/
enum v4l2_isp_params_version {
V4L2_ISP_PARAMS_VERSION_V0 = 0,
V4L2_ISP_PARAMS_VERSION_V1
};
#define V4L2_ISP_PARAMS_FL_BLOCK_DISABLE (1U << 0)
#define V4L2_ISP_PARAMS_FL_BLOCK_ENABLE (1U << 1)
/*
* Reserve the first 8 bits for V4L2_ISP_PARAMS_FL_* flag.
*
* Driver-specific flags should be defined as:
* #define DRIVER_SPECIFIC_FLAG0 ((1U << V4L2_ISP_PARAMS_FL_DRIVER_FLAGS(0))
* #define DRIVER_SPECIFIC_FLAG1 ((1U << V4L2_ISP_PARAMS_FL_DRIVER_FLAGS(1))
*/
#define V4L2_ISP_PARAMS_FL_DRIVER_FLAGS(n) ((n) + 8)
/**
* struct v4l2_isp_params_block_header - V4L2 extensible parameters block header
* @type: The parameters block type (driver-specific)
* @flags: A bitmask of block flags (driver-specific)
* @size: Size (in bytes) of the parameters block, including this header
*
* This structure represents the common part of all the ISP configuration
* blocks. Each parameters block shall embed an instance of this structure type
* as its first member, followed by the block-specific configuration data.
*
* The @type field is an ISP driver-specific value that identifies the block
* type. The @size field specifies the size of the parameters block.
*
* The @flags field is a bitmask of per-block flags V4L2_PARAMS_ISP_FL_* and
* driver-specific flags specified by the driver header.
*/
struct v4l2_isp_params_block_header {
__u16 type;
__u16 flags;
__u32 size;
} __attribute__((aligned(8)));
/**
* struct v4l2_isp_params_buffer - V4L2 extensible parameters configuration
* @version: The parameters buffer version (driver-specific)
* @data_size: The configuration data effective size, excluding this header
* @data: The configuration data
*
* This structure contains the configuration parameters of the ISP algorithms,
* serialized by userspace into a data buffer. Each configuration parameter
* block is represented by a block-specific structure which contains a
* :c:type:`v4l2_isp_params_block_header` entry as first member. Userspace
* populates the @data buffer with configuration parameters for the blocks that
* it intends to configure. As a consequence, the data buffer effective size
* changes according to the number of ISP blocks that userspace intends to
* configure and is set by userspace in the @data_size field.
*
* The parameters buffer is versioned by the @version field to allow modifying
* and extending its definition. Userspace shall populate the @version field to
* inform the driver about the version it intends to use. The driver will parse
* and handle the @data buffer according to the data layout specific to the
* indicated version and return an error if the desired version is not
* supported.
*
* For each ISP block that userspace wants to configure, a block-specific
* structure is appended to the @data buffer, one after the other without gaps
* in between. Userspace shall populate the @data_size field with the effective
* size, in bytes, of the @data buffer.
*/
struct v4l2_isp_params_buffer {
__u32 version;
__u32 data_size;
__u8 data[] __counted_by(data_size);
};
#endif /* _UAPI_V4L2_ISP_H_ */