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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/include/ufs/ufs.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Universal Flash Storage Host controller driver
* Copyright (C) 2011-2013 Samsung India Software Operations
*
* Authors:
* Santosh Yaraganavi <santosh.sy@samsung.com>
* Vinayak Holikatti <h.vinayak@samsung.com>
*/
#ifndef _UFS_H
#define _UFS_H
#include <linux/bitops.h>
#include <linux/types.h>
#include <uapi/scsi/scsi_bsg_ufs.h>
#include <linux/time64.h>
/*
* Using static_assert() is not allowed in UAPI header files. Hence the check
* in this header file of the size of struct utp_upiu_header.
*/
static_assert(sizeof(struct utp_upiu_header) == 12);
static_assert(sizeof(struct utp_upiu_query) == 20);
#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
#define QUERY_DESC_MAX_SIZE 255
#define QUERY_DESC_MIN_SIZE 2
#define QUERY_DESC_HDR_SIZE 2
#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
(sizeof(struct utp_upiu_header)))
#define UFS_SENSE_SIZE 18
/*
* UFS device may have standard LUs and LUN id could be from 0x00 to
* 0x7F. Standard LUs use "Peripheral Device Addressing Format".
* UFS device may also have the Well Known LUs (also referred as W-LU)
* which again could be from 0x00 to 0x7F. For W-LUs, device only use
* the "Extended Addressing Format" which means the W-LUNs would be
* from 0xc100 (SCSI_W_LUN_BASE) onwards.
* This means max. LUN number reported from UFS device could be 0xC17F.
*/
#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
#define UFS_UPIU_WLUN_ID (1 << 7)
/* WriteBooster buffer is available only for the logical unit from 0 to 7 */
#define UFS_UPIU_MAX_WB_LUN_ID 8
/*
* WriteBooster buffer lifetime has a limit setted by vendor.
* If it is over the limit, WriteBooster feature will be disabled.
*/
#define UFS_WB_EXCEED_LIFETIME 0x0B
/*
* In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU request/response packet
*/
#define EHS_OFFSET_IN_RESPONSE 32
/* Well known logical unit id in LUN field of UPIU */
enum {
UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
UFS_UPIU_BOOT_WLUN = 0xB0,
UFS_UPIU_RPMB_WLUN = 0xC4,
};
/*
* UFS Protocol Information Unit related definitions
*/
/* Task management functions */
enum {
UFS_ABORT_TASK = 0x01,
UFS_ABORT_TASK_SET = 0x02,
UFS_CLEAR_TASK_SET = 0x04,
UFS_LOGICAL_RESET = 0x08,
UFS_QUERY_TASK = 0x80,
UFS_QUERY_TASK_SET = 0x81,
};
/* UTP UPIU Transaction Codes Initiator to Target */
enum upiu_request_transaction {
UPIU_TRANSACTION_NOP_OUT = 0x00,
UPIU_TRANSACTION_COMMAND = 0x01,
UPIU_TRANSACTION_DATA_OUT = 0x02,
UPIU_TRANSACTION_TASK_REQ = 0x04,
UPIU_TRANSACTION_QUERY_REQ = 0x16,
};
/* UTP UPIU Transaction Codes Target to Initiator */
enum upiu_response_transaction {
UPIU_TRANSACTION_NOP_IN = 0x20,
UPIU_TRANSACTION_RESPONSE = 0x21,
UPIU_TRANSACTION_DATA_IN = 0x22,
UPIU_TRANSACTION_TASK_RSP = 0x24,
UPIU_TRANSACTION_READY_XFER = 0x31,
UPIU_TRANSACTION_QUERY_RSP = 0x36,
UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
};
/* UPIU Read/Write flags. See also table "UPIU Flags" in the UFS standard. */
enum {
UPIU_CMD_FLAGS_NONE = 0x00,
UPIU_CMD_FLAGS_CP = 0x04,
UPIU_CMD_FLAGS_WRITE = 0x20,
UPIU_CMD_FLAGS_READ = 0x40,
};
/* UPIU response flags */
enum {
UPIU_RSP_FLAG_UNDERFLOW = 0x20,
UPIU_RSP_FLAG_OVERFLOW = 0x40,
};
/* UPIU Task Attributes */
enum {
UPIU_TASK_ATTR_SIMPLE = 0x00,
UPIU_TASK_ATTR_ORDERED = 0x01,
UPIU_TASK_ATTR_HEADQ = 0x02,
UPIU_TASK_ATTR_ACA = 0x03,
};
/* UPIU Query request function */
enum {
UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
};
/* Flag idn for Query Requests*/
enum flag_idn {
QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
QUERY_FLAG_IDN_BKOPS_EN = 0x04,
QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
QUERY_FLAG_IDN_RESERVED2 = 0x07,
QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
QUERY_FLAG_IDN_BUSY_RTC = 0x09,
QUERY_FLAG_IDN_RESERVED3 = 0x0A,
QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
QUERY_FLAG_IDN_WB_EN = 0x0E,
QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
QUERY_FLAG_IDN_HPB_RESET = 0x11,
QUERY_FLAG_IDN_HPB_EN = 0x12,
};
/* Attribute idn for Query requests */
enum attr_idn {
QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
QUERY_ATTR_IDN_POWER_MODE = 0x02,
QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
QUERY_ATTR_IDN_EE_STATUS = 0x0E,
QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
QUERY_ATTR_IDN_CNTX_CONF = 0x10,
QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
QUERY_ATTR_IDN_RESERVED2 = 0x12,
QUERY_ATTR_IDN_RESERVED3 = 0x13,
QUERY_ATTR_IDN_FFU_STATUS = 0x14,
QUERY_ATTR_IDN_PSA_STATE = 0x15,
QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
QUERY_ATTR_IDN_TIMESTAMP = 0x30,
QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID = 0x34,
QUERY_ATTR_IDN_HID_DEFRAG_OPERATION = 0x35,
QUERY_ATTR_IDN_HID_AVAILABLE_SIZE = 0x36,
QUERY_ATTR_IDN_HID_SIZE = 0x37,
QUERY_ATTR_IDN_HID_PROGRESS_RATIO = 0x38,
QUERY_ATTR_IDN_HID_STATE = 0x39,
QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT = 0x3C,
QUERY_ATTR_IDN_WB_BUF_RESIZE_EN = 0x3D,
QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS = 0x3E,
QUERY_ATTR_IDN_TX_EQ_GN_SETTINGS = 0x47,
QUERY_ATTR_IDN_TX_EQ_GN_SETTINGS_EXT = 0x48,
};
/* Descriptor idn for Query requests */
enum desc_idn {
QUERY_DESC_IDN_DEVICE = 0x0,
QUERY_DESC_IDN_CONFIGURATION = 0x1,
QUERY_DESC_IDN_UNIT = 0x2,
QUERY_DESC_IDN_RFU_0 = 0x3,
QUERY_DESC_IDN_INTERCONNECT = 0x4,
QUERY_DESC_IDN_STRING = 0x5,
QUERY_DESC_IDN_RFU_1 = 0x6,
QUERY_DESC_IDN_GEOMETRY = 0x7,
QUERY_DESC_IDN_POWER = 0x8,
QUERY_DESC_IDN_HEALTH = 0x9,
QUERY_DESC_IDN_MAX,
};
enum desc_header_offset {
QUERY_DESC_LENGTH_OFFSET = 0x00,
QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
};
/* Unit descriptor parameters offsets in bytes*/
enum unit_desc_param {
UNIT_DESC_PARAM_LEN = 0x0,
UNIT_DESC_PARAM_TYPE = 0x1,
UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
UNIT_DESC_PARAM_LU_ENABLE = 0x3,
UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
UNIT_DESC_PARAM_MEM_TYPE = 0x8,
UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
};
/* RPMB Unit descriptor parameters offsets in bytes*/
enum rpmb_unit_desc_param {
RPMB_UNIT_DESC_PARAM_LEN = 0x0,
RPMB_UNIT_DESC_PARAM_TYPE = 0x1,
RPMB_UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
RPMB_UNIT_DESC_PARAM_LU_ENABLE = 0x3,
RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
RPMB_UNIT_DESC_PARAM_MEM_TYPE = 0x8,
RPMB_UNIT_DESC_PARAM_REGION_EN = 0x9,
RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
RPMB_UNIT_DESC_PARAM_REGION0_SIZE = 0x13,
RPMB_UNIT_DESC_PARAM_REGION1_SIZE = 0x14,
RPMB_UNIT_DESC_PARAM_REGION2_SIZE = 0x15,
RPMB_UNIT_DESC_PARAM_REGION3_SIZE = 0x16,
RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
};
/* Device descriptor parameters offsets in bytes*/
enum device_desc_param {
DEVICE_DESC_PARAM_LEN = 0x0,
DEVICE_DESC_PARAM_TYPE = 0x1,
DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
DEVICE_DESC_PARAM_PRTCL = 0x5,
DEVICE_DESC_PARAM_NUM_LU = 0x6,
DEVICE_DESC_PARAM_NUM_WLU = 0x7,
DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
DEVICE_DESC_PARAM_SEC_LU = 0xD,
DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
DEVICE_DESC_PARAM_SPEC_VER = 0x10,
DEVICE_DESC_PARAM_MANF_DATE = 0x12,
DEVICE_DESC_PARAM_MANF_NAME = 0x14,
DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
DEVICE_DESC_PARAM_SN = 0x16,
DEVICE_DESC_PARAM_OEM_ID = 0x17,
DEVICE_DESC_PARAM_MANF_ID = 0x18,
DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
DEVICE_DESC_PARAM_UD_LEN = 0x1B,
DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
DEVICE_DESC_PARAM_FFU_TMT = 0x20,
DEVICE_DESC_PARAM_Q_DPTH = 0x21,
DEVICE_DESC_PARAM_DEV_VER = 0x22,
DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
DEVICE_DESC_PARAM_PSA_TMT = 0x29,
DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
DEVICE_DESC_PARAM_HPB_VER = 0x40,
DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
DEVICE_DESC_PARAM_EXT_WB_SUP = 0x4D,
DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
DEVICE_DESC_PARAM_WB_TYPE = 0x54,
DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
};
/* Interconnect descriptor parameters offsets in bytes*/
enum interconnect_desc_param {
INTERCONNECT_DESC_PARAM_LEN = 0x0,
INTERCONNECT_DESC_PARAM_TYPE = 0x1,
INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
};
/* Geometry descriptor parameters offsets in bytes*/
enum geometry_desc_param {
GEOMETRY_DESC_PARAM_LEN = 0x0,
GEOMETRY_DESC_PARAM_TYPE = 0x1,
GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
};
/* Health descriptor parameters offsets in bytes*/
enum health_desc_param {
HEALTH_DESC_PARAM_LEN = 0x0,
HEALTH_DESC_PARAM_TYPE = 0x1,
HEALTH_DESC_PARAM_EOL_INFO = 0x2,
HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
};
/* WriteBooster buffer mode */
enum {
WB_BUF_MODE_LU_DEDICATED = 0x0,
WB_BUF_MODE_SHARED = 0x1,
};
/*
* Logical Unit Write Protect
* 00h: LU not write protected
* 01h: LU write protected when fPowerOnWPEn =1
* 02h: LU permanently write protected when fPermanentWPEn =1
*/
enum ufs_lu_wp_type {
UFS_LU_NO_WP = 0x00,
UFS_LU_POWER_ON_WP = 0x01,
UFS_LU_PERM_WP = 0x02,
};
/* bActiveICCLevel parameter current units */
enum {
UFSHCD_NANO_AMP = 0,
UFSHCD_MICRO_AMP = 1,
UFSHCD_MILI_AMP = 2,
UFSHCD_AMP = 3,
};
/* Possible values for wExtendedWriteBoosterSupport */
enum {
UFS_DEV_WB_BUF_RESIZE = BIT(0),
};
/* Possible values for dExtendedUFSFeaturesSupport */
enum {
UFS_DEV_HIGH_TEMP_NOTIF = BIT(4),
UFS_DEV_LOW_TEMP_NOTIF = BIT(5),
UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
UFS_DEV_HPB_SUPPORT = BIT(7),
UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
UFS_DEV_LVL_EXCEPTION_SUP = BIT(12),
UFS_DEV_HID_SUPPORT = BIT(13),
};
#define UFS_DEV_HPB_SUPPORT_VERSION 0x310
#define POWER_DESC_MAX_ACTV_ICC_LVLS 16
/* Attribute bActiveICCLevel parameter bit masks definitions */
#define ATTR_ICC_LVL_UNIT_OFFSET 14
#define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
#define ATTR_ICC_LVL_VALUE_MASK 0x3FF
/* Power descriptor parameters offsets in bytes */
enum power_desc_param_offset {
PWR_DESC_LEN = 0x0,
PWR_DESC_TYPE = 0x1,
PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
};
/* Exception event mask values */
enum {
MASK_EE_STATUS = 0xFFFF,
MASK_EE_DYNCAP_EVENT = BIT(0),
MASK_EE_SYSPOOL_EVENT = BIT(1),
MASK_EE_URGENT_BKOPS = BIT(2),
MASK_EE_TOO_HIGH_TEMP = BIT(3),
MASK_EE_TOO_LOW_TEMP = BIT(4),
MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
MASK_EE_DEV_LVL_EXCEPTION = BIT(7),
MASK_EE_HEALTH_CRITICAL = BIT(9),
};
#define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
/* Background operation status */
enum bkops_status {
BKOPS_STATUS_NO_OP = 0x0,
BKOPS_STATUS_NON_CRITICAL = 0x1,
BKOPS_STATUS_PERF_IMPACT = 0x2,
BKOPS_STATUS_CRITICAL = 0x3,
BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
};
/* UTP QUERY Transaction Specific Fields OpCode */
enum query_opcode {
UPIU_QUERY_OPCODE_NOP = 0x0,
UPIU_QUERY_OPCODE_READ_DESC = 0x1,
UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
};
/* bRefClkFreq attribute values */
enum ufs_ref_clk_freq {
REF_CLK_FREQ_19_2_MHZ = 0,
REF_CLK_FREQ_26_MHZ = 1,
REF_CLK_FREQ_38_4_MHZ = 2,
REF_CLK_FREQ_52_MHZ = 3,
REF_CLK_FREQ_INVAL = -1,
};
/* bDefragOperation attribute values */
enum ufs_hid_defrag_operation {
HID_ANALYSIS_AND_DEFRAG_DISABLE = 0,
HID_ANALYSIS_ENABLE = 1,
HID_ANALYSIS_AND_DEFRAG_ENABLE = 2,
};
/* bHIDState attribute values */
enum ufs_hid_state {
HID_IDLE = 0,
ANALYSIS_IN_PROGRESS = 1,
DEFRAG_REQUIRED = 2,
DEFRAG_IN_PROGRESS = 3,
DEFRAG_COMPLETED = 4,
DEFRAG_NOT_REQUIRED = 5,
NUM_UFS_HID_STATES = 6,
};
/* bWriteBoosterBufferResizeEn attribute */
enum wb_resize_en {
WB_RESIZE_EN_IDLE = 0,
WB_RESIZE_EN_DECREASE = 1,
WB_RESIZE_EN_INCREASE = 2,
};
/* bWriteBoosterBufferResizeHint attribute */
enum wb_resize_hint {
WB_RESIZE_HINT_KEEP = 0,
WB_RESIZE_HINT_DECREASE = 1,
WB_RESIZE_HINT_INCREASE = 2,
};
/* bWriteBoosterBufferResizeStatus attribute */
enum wb_resize_status {
WB_RESIZE_STATUS_IDLE = 0,
WB_RESIZE_STATUS_IN_PROGRESS = 1,
WB_RESIZE_STATUS_COMPLETE_SUCCESS = 2,
WB_RESIZE_STATUS_GENERAL_FAILURE = 3,
};
/* Query response result code */
enum {
QUERY_RESULT_SUCCESS = 0x00,
QUERY_RESULT_NOT_READABLE = 0xF6,
QUERY_RESULT_NOT_WRITEABLE = 0xF7,
QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
QUERY_RESULT_INVALID_LENGTH = 0xF9,
QUERY_RESULT_INVALID_VALUE = 0xFA,
QUERY_RESULT_INVALID_SELECTOR = 0xFB,
QUERY_RESULT_INVALID_INDEX = 0xFC,
QUERY_RESULT_INVALID_IDN = 0xFD,
QUERY_RESULT_INVALID_OPCODE = 0xFE,
QUERY_RESULT_GENERAL_FAILURE = 0xFF,
};
/* UTP Transfer Request Command Type (CT) */
enum {
UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
UPIU_COMMAND_SET_TYPE_UFS = 0x1,
UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
};
/* Offset of the response code in the UPIU header */
#define UPIU_RSP_CODE_OFFSET 8
enum {
MASK_TM_SERVICE_RESP = 0xFF,
};
/* Task management service response */
enum {
UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
};
/* UFS device power modes */
enum ufs_dev_pwr_mode {
UFS_ACTIVE_PWR_MODE = 1,
UFS_SLEEP_PWR_MODE = 2,
UFS_POWERDOWN_PWR_MODE = 3,
UFS_DEEPSLEEP_PWR_MODE = 4,
};
#define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
/**
* struct utp_cmd_rsp - RESPONSE UPIU structure
* @residual_transfer_count: Residual transfer count DW-3
* @reserved: Reserved double words DW-4 to DW-7
* @sense_data_len: Sense data length DW-8 U16
* @sense_data: Sense data field DW-8 to DW-12
*/
struct utp_cmd_rsp {
__be32 residual_transfer_count;
__be32 reserved[4];
__be16 sense_data_len;
u8 sense_data[UFS_SENSE_SIZE];
};
static_assert(sizeof(struct utp_cmd_rsp) == 40);
/**
* struct utp_upiu_rsp - general upiu response structure
* @header: UPIU header structure DW-0 to DW-2
* @sr: fields structure for scsi command DW-3 to DW-12
* @qr: fields structure for query request DW-3 to DW-7
*/
struct utp_upiu_rsp {
struct utp_upiu_header header;
union {
struct utp_cmd_rsp sr;
struct utp_upiu_query qr;
};
};
/*
* VCCQ & VCCQ2 current requirement when UFS device is in sleep state
* and link is in Hibern8 state.
*/
#define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
struct ufs_vreg {
struct regulator *reg;
const char *name;
bool always_on;
bool enabled;
int max_uA;
};
struct ufs_vreg_info {
struct ufs_vreg *vcc;
struct ufs_vreg *vccq;
struct ufs_vreg *vccq2;
struct ufs_vreg *vdd_hba;
};
/* UFS device descriptor wPeriodicRTCUpdate bit9 defines RTC time baseline */
#define UFS_RTC_TIME_BASELINE BIT(9)
enum ufs_rtc_time {
UFS_RTC_RELATIVE,
UFS_RTC_ABSOLUTE
};
struct ufs_dev_info {
bool f_power_on_wp_en;
/* Keeps information if any of the LU is power on write protected */
bool is_lu_power_on_wp;
/* Maximum number of general LU supported by the UFS device */
u8 max_lu_supported;
u16 wmanufacturerid;
/*UFS device Product Name */
u8 *model;
u16 wspecversion;
u32 clk_gating_wait_us;
/* Stores the depth of queue in UFS device */
u8 bqueuedepth;
/* UFS WB related flags */
bool wb_enabled;
bool wb_buf_flush_enabled;
u8 wb_dedicated_lu;
u8 wb_buffer_type;
u16 ext_wb_sup;
bool b_rpm_dev_flush_capable;
u8 b_presrv_uspc_en;
bool b_advanced_rpmb_en;
/* UFS RTC */
enum ufs_rtc_time rtc_type;
time64_t rtc_time_baseline;
u32 rtc_update_period;
u8 rtt_cap; /* bDeviceRTTCap */
bool hid_sup;
/* Unique device ID string (manufacturer+model+serial+version+date) */
char *device_id;
u8 rpmb_io_size;
u8 rpmb_region_size[4];
};
#endif /* End of Header */
linux-7.2.3/include/ufs/ufs_quirks.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*/
#ifndef _UFS_QUIRKS_H_
#define _UFS_QUIRKS_H_
/* return true if s1 is a prefix of s2 */
#define STR_PRFX_EQUAL(s1, s2) !strncmp(s1, s2, strlen(s1))
#define UFS_ANY_VENDOR 0xFFFF
#define UFS_ANY_MODEL "ANY_MODEL"
#define UFS_VENDOR_MICRON 0x12C
#define UFS_VENDOR_SAMSUNG 0x1CE
#define UFS_VENDOR_SKHYNIX 0x1AD
#define UFS_VENDOR_TOSHIBA 0x198
#define UFS_VENDOR_WDC 0x145
/**
* ufs_dev_quirk - ufs device quirk info
* @card: ufs card details
* @quirk: device quirk
*/
struct ufs_dev_quirk {
u16 wmanufacturerid;
const u8 *model;
unsigned int quirk;
};
/*
* Some vendor's UFS device sends back to back NACs for the DL data frames
* causing the host controller to raise the DFES error status. Sometimes
* such UFS devices send back to back NAC without waiting for new
* retransmitted DL frame from the host and in such cases it might be possible
* the Host UniPro goes into bad state without raising the DFES error
* interrupt. If this happens then all the pending commands would timeout
* only after respective SW command (which is generally too large).
*
* We can workaround such device behaviour like this:
* - As soon as SW sees the DL NAC error, it should schedule the error handler
* - Error handler would sleep for 50ms to see if there are any fatal errors
* raised by UFS controller.
* - If there are fatal errors then SW does normal error recovery.
* - If there are no fatal errors then SW sends the NOP command to device
* to check if link is alive.
* - If NOP command times out, SW does normal error recovery
* - If NOP command succeed, skip the error handling.
*
* If DL NAC error is seen multiple times with some vendor's UFS devices then
* enable this quirk to initiate quick error recovery and also silence related
* error logs to reduce spamming of kernel logs.
*/
#define UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS (1 << 2)
/*
* Few Toshiba UFS device models advertise RX_MIN_ACTIVATETIME_CAPABILITY as
* 600us which may not be enough for reliable hibern8 exit hardware sequence
* from UFS device.
* To workaround this issue, host should set its PA_TACTIVATE time to 1ms even
* if device advertises RX_MIN_ACTIVATETIME_CAPABILITY less than 1ms.
*/
#define UFS_DEVICE_QUIRK_PA_TACTIVATE (1 << 4)
/*
* It seems some UFS devices may keep drawing more than sleep current
* (atleast for 500us) from UFS rails (especially from VCCQ rail).
* To avoid this situation, add 2ms delay before putting these UFS
* rails in LPM mode.
*/
#define UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM (1 << 6)
/*
* Some UFS devices require host PA_TACTIVATE to be lower than device
* PA_TACTIVATE, enabling this quirk ensure this.
*/
#define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7)
/*
* The max. value PA_SaveConfigTime is 250 (10us) but this is not enough for
* some vendors.
* Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime.
* Gear switch can be issued by host controller as an error recovery and any
* software delay will not help on this case so we need to increase
* PA_SaveConfigTime to >32us as per vendor recommendation.
*/
#define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8)
/*
* Some UFS devices require VS_DebugSaveConfigTime is 0x10,
* enabling this quirk ensure this.
*/
#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 9)
/*
* Some pre-3.1 UFS devices can support extended features by upgrading
* the firmware. Enable this quirk to make UFS core driver probe and enable
* supported features on such devices.
*/
#define UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES (1 << 10)
/*
* Some ufs devices may need more time to be in hibern8 before exiting.
* Enable this quirk to give it an additional 100us.
*/
#define UFS_DEVICE_QUIRK_PA_HIBER8TIME (1 << 12)
/* Some UFS 4 devices do not support the qTimestamp attribute */
#define UFS_DEVICE_QUIRK_NO_TIMESTAMP_SUPPORT (1 << 13)
#endif /* UFS_QUIRKS_H_ */
linux-7.2.3/include/ufs/ufshcd.h
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linux-7.2.3/include/ufs/ufshci.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Universal Flash Storage Host controller driver
* Copyright (C) 2011-2013 Samsung India Software Operations
*
* Authors:
* Santosh Yaraganavi <santosh.sy@samsung.com>
* Vinayak Holikatti <h.vinayak@samsung.com>
*/
#ifndef _UFSHCI_H
#define _UFSHCI_H
#include <linux/types.h>
#include <ufs/ufs.h>
enum {
TASK_REQ_UPIU_SIZE_DWORDS = 8,
TASK_RSP_UPIU_SIZE_DWORDS = 8,
ALIGNED_UPIU_SIZE = 512,
};
/* UFSHCI Registers */
enum {
REG_CONTROLLER_CAPABILITIES = 0x00,
REG_MCQCAP = 0x04,
REG_UFS_VERSION = 0x08,
REG_EXT_CONTROLLER_CAPABILITIES = 0x0C,
REG_CONTROLLER_PID = 0x10,
REG_CONTROLLER_MID = 0x14,
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
REG_INTERRUPT_STATUS = 0x20,
REG_INTERRUPT_ENABLE = 0x24,
REG_CONTROLLER_STATUS = 0x30,
REG_CONTROLLER_ENABLE = 0x34,
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
REG_UIC_ERROR_CODE_DME = 0x48,
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
REG_UIC_COMMAND = 0x90,
REG_UIC_COMMAND_ARG_1 = 0x94,
REG_UIC_COMMAND_ARG_2 = 0x98,
REG_UIC_COMMAND_ARG_3 = 0x9C,
UFSHCI_REG_SPACE_SIZE = 0xA0,
REG_UFS_CCAP = 0x100,
REG_UFS_CRYPTOCAP = 0x104,
REG_UFS_MEM_CFG = 0x300,
REG_UFS_MCQ_CFG = 0x380,
REG_UFS_ESILBA = 0x384,
REG_UFS_ESIUBA = 0x388,
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
};
/* Controller capability masks */
enum {
MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F,
MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF,
MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00,
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
MASK_EHSLUTRD_SUPPORTED = 0x00400000,
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
MASK_CRYPTO_SUPPORT = 0x10000000,
MASK_LSDB_SUPPORT = 0x20000000,
MASK_MCQ_SUPPORT = 0x40000000,
};
enum {
/* Submission Queue (SQ) Configuration Registers */
REG_SQATTR = 0x0,
REG_SQLBA = 0x4,
REG_SQUBA = 0x8,
REG_SQDAO = 0xC,
REG_SQISAO = 0x10,
/* Completion Queue (CQ) Configuration Registers */
REG_CQATTR = 0x20,
REG_CQLBA = 0x24,
REG_CQUBA = 0x28,
REG_CQDAO = 0x2C,
REG_CQISAO = 0x30,
};
/* Operation and Runtime Registers - Submission Queues and Completion Queues */
enum {
REG_SQHP = 0x0,
REG_SQTP = 0x4,
REG_SQRTC = 0x8,
REG_SQCTI = 0xC,
REG_SQRTS = 0x10,
};
enum {
REG_CQHP = 0x0,
REG_CQTP = 0x4,
};
enum {
REG_CQIS = 0x0,
REG_CQIE = 0x4,
REG_MCQIACR = 0x8,
};
enum {
SQ_START = 0x0,
SQ_STOP = 0x1,
SQ_ICU = 0x2,
};
enum {
SQ_STS = 0x1,
SQ_CUS = 0x2,
};
#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
#define UFS_MASK(mask, offset) ((mask) << (offset))
/* UFS Version 08h */
#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
#define UFSHCD_NUM_RESERVED 1
/*
* Controller UFSHCI version
* - 2.x and newer use the following scheme:
* major << 8 + minor << 4
* - 1.x has been converted to match this in
* ufshcd_get_ufs_version()
*/
static inline u32 ufshci_version(u32 major, u32 minor)
{
return (major << 8) + (minor << 4);
}
/*
* HCDDID - Host Controller Identification Descriptor
* - Device ID and Device Class 10h
*/
#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
#define DEVICE_ID UFS_MASK(0xFF, 24)
/*
* HCPMID - Host Controller Identification Descriptor
* - Product/Manufacturer ID 14h
*/
#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
/* AHIT - Auto-Hibernate Idle Timer */
#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
/*
* IS - Interrupt Status - 20h
*/
#define UTP_TRANSFER_REQ_COMPL 0x1
#define UIC_DME_END_PT_RESET 0x2
#define UIC_ERROR 0x4
#define UIC_TEST_MODE 0x8
#define UIC_POWER_MODE 0x10
#define UIC_HIBERNATE_EXIT 0x20
#define UIC_HIBERNATE_ENTER 0x40
#define UIC_LINK_LOST 0x80
#define UIC_LINK_STARTUP 0x100
#define UTP_TASK_REQ_COMPL 0x200
#define UIC_COMMAND_COMPL 0x400
#define DEVICE_FATAL_ERROR 0x800
#define UTP_ERROR 0x1000
#define CONTROLLER_FATAL_ERROR 0x10000
#define SYSTEM_BUS_FATAL_ERROR 0x20000
#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
#define MCQ_CQ_EVENT_STATUS 0x100000
#define MCQ_IAG_EVENT_STATUS 0x200000
#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
UIC_HIBERNATE_EXIT)
#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
UIC_POWER_MODE)
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
CONTROLLER_FATAL_ERROR |\
SYSTEM_BUS_FATAL_ERROR |\
CRYPTO_ENGINE_FATAL_ERROR |\
UIC_LINK_LOST |\
UTP_ERROR)
/* HCS - Host Controller Status 30h */
#define DEVICE_PRESENT 0x1
#define UTP_TRANSFER_REQ_LIST_READY 0x2
#define UTP_TASK_REQ_LIST_READY 0x4
#define UIC_COMMAND_READY 0x8
#define HOST_ERROR_INDICATOR 0x10
#define DEVICE_ERROR_INDICATOR 0x20
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
UTP_TASK_REQ_LIST_READY |\
UIC_COMMAND_READY)
enum {
PWR_OK = 0x0,
PWR_LOCAL = 0x01,
PWR_REMOTE = 0x02,
PWR_BUSY = 0x03,
PWR_ERROR_CAP = 0x04,
PWR_FATAL_ERROR = 0x05,
};
/* HCE - Host Controller Enable 34h */
#define CONTROLLER_ENABLE 0x1
#define CONTROLLER_DISABLE 0x0
#define CRYPTO_GENERAL_ENABLE 0x2
/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
/* UECN - Host UIC Error Code Network Layer 40h */
#define UIC_NETWORK_LAYER_ERROR 0x80000000
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
/* UECT - Host UIC Error Code Transport Layer 44h */
#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
#define UIC_TRANSPORT_BAD_TC 0x10
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
/* UECDME - Host UIC Error Code DME 48h */
#define UIC_DME_ERROR 0x80000000
#define UIC_DME_ERROR_CODE_MASK 0x1
#define UIC_DME_QOS_MASK 0xE
/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
#define INT_AGGR_STATUS_BIT 0x100000
#define INT_AGGR_PARAM_WRITE 0x1000000
#define INT_AGGR_ENABLE 0x80000000
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
/* REG_UFS_MEM_CFG - Global Config Registers 300h */
#define MCQ_MODE_SELECT BIT(0)
#define ESI_ENABLE BIT(1)
/* CQISy - CQ y Interrupt Status Register */
#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
/* UICCMD - UIC Command */
#define COMMAND_OPCODE_MASK 0xFF
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
#define RESET_LEVEL 0xFF
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
#define CONFIG_RESULT_CODE_MASK 0xFF
#define GENERIC_ERROR_CODE_MASK 0xFF
/* GenSelectorIndex calculation macros for M-PHY attributes */
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
((sel) & 0xFFFF))
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
/* Link Status*/
enum link_status {
UFSHCD_LINK_IS_DOWN = 1,
UFSHCD_LINK_IS_UP = 2,
};
/* UIC Commands */
enum uic_cmd_dme {
UIC_CMD_DME_GET = 0x01,
UIC_CMD_DME_SET = 0x02,
UIC_CMD_DME_PEER_GET = 0x03,
UIC_CMD_DME_PEER_SET = 0x04,
UIC_CMD_DME_POWERON = 0x10,
UIC_CMD_DME_POWEROFF = 0x11,
UIC_CMD_DME_ENABLE = 0x12,
UIC_CMD_DME_RESET = 0x14,
UIC_CMD_DME_END_PT_RST = 0x15,
UIC_CMD_DME_LINK_STARTUP = 0x16,
UIC_CMD_DME_HIBER_ENTER = 0x17,
UIC_CMD_DME_HIBER_EXIT = 0x18,
UIC_CMD_DME_TEST_MODE = 0x1A,
};
/* UIC Config result code / Generic error code */
enum {
UIC_CMD_RESULT_SUCCESS = 0x00,
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
UIC_CMD_RESULT_FAILURE = 0x01,
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
UIC_CMD_RESULT_BAD_INDEX = 0x05,
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
UIC_CMD_RESULT_BUSY = 0x09,
UIC_CMD_RESULT_DME_FAILURE = 0x0A,
};
#define MASK_UIC_COMMAND_RESULT 0xFF
#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
/* Interrupt disable masks */
enum {
/* Interrupt disable mask for UFSHCI v1.1 */
INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
/* Interrupt disable mask for UFSHCI v2.1 */
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
};
/* CCAP - Crypto Capability 100h */
union ufs_crypto_capabilities {
__le32 reg_val;
struct {
u8 num_crypto_cap;
u8 config_count;
u8 reserved;
u8 config_array_ptr;
};
};
enum ufs_crypto_key_size {
UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
UFS_CRYPTO_KEY_SIZE_128 = 0x1,
UFS_CRYPTO_KEY_SIZE_192 = 0x2,
UFS_CRYPTO_KEY_SIZE_256 = 0x3,
UFS_CRYPTO_KEY_SIZE_512 = 0x4,
};
enum ufs_crypto_alg {
UFS_CRYPTO_ALG_AES_XTS = 0x0,
UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
UFS_CRYPTO_ALG_AES_ECB = 0x2,
UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
};
/* x-CRYPTOCAP - Crypto Capability X */
union ufs_crypto_cap_entry {
__le32 reg_val;
struct {
u8 algorithm_id;
u8 sdus_mask; /* Supported data unit size mask */
u8 key_size;
u8 reserved;
};
};
#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
#define UFS_CRYPTO_KEY_MAX_SIZE 64
/* x-CRYPTOCFG - Crypto Configuration X */
union ufs_crypto_cfg_entry {
__le32 reg_val[32];
struct {
u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
u8 data_unit_size;
u8 crypto_cap_idx;
u8 reserved_1;
u8 config_enable;
u8 reserved_multi_host;
u8 reserved_2;
u8 vsb[2];
u8 reserved_3[56];
};
};
/*
* Request Descriptor Definitions
*/
/* To accommodate UFS2.0 required Command type */
enum {
UTP_CMD_TYPE_UFS_STORAGE = 0x1,
};
enum {
UTP_SCSI_COMMAND = 0x00000000,
UTP_NATIVE_UFS_COMMAND = 0x10000000,
UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
};
/* UTP Transfer Request Data Direction (DD) */
enum utp_data_direction {
UTP_NO_DATA_TRANSFER = 0,
UTP_HOST_TO_DEVICE = 1,
UTP_DEVICE_TO_HOST = 2,
};
/* Overall command status values */
enum utp_ocs {
OCS_SUCCESS = 0x0,
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
OCS_INVALID_PRDT_ATTR = 0x2,
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
OCS_PEER_COMM_FAILURE = 0x5,
OCS_ABORTED = 0x6,
OCS_FATAL_ERROR = 0x7,
OCS_DEVICE_FATAL_ERROR = 0x8,
OCS_INVALID_CRYPTO_CONFIG = 0x9,
OCS_GENERAL_CRYPTO_ERROR = 0xA,
OCS_INVALID_COMMAND_STATUS = 0x0F,
};
enum {
MASK_OCS = 0x0F,
};
/* The maximum length of the data byte count field in the PRDT is 256KB */
#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
/* The granularity of the data byte count field in the PRDT is 32-bit */
#define PRDT_DATA_BYTE_COUNT_PAD 4
/**
* struct ufshcd_sg_entry - UFSHCI PRD Entry
* @addr: Physical address; DW-0 and DW-1.
* @reserved: Reserved for future use DW-2
* @size: size of physical segment DW-3
*/
struct ufshcd_sg_entry {
__le64 addr;
__le32 reserved;
__le32 size;
/*
* followed by variant-specific fields if
* CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
*/
};
/**
* struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
* @command_upiu: Command UPIU Frame address
* @response_upiu: Response UPIU Frame address
* @prd_table: Physical Region Descriptor: an array of SG_ALL struct
* ufshcd_sg_entry's. Variant-specific fields may be present after each.
*/
struct utp_transfer_cmd_desc {
u8 command_upiu[ALIGNED_UPIU_SIZE];
u8 response_upiu[ALIGNED_UPIU_SIZE];
u8 prd_table[];
};
/**
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
*/
struct request_desc_header {
u8 cci;
u8 ehs_length;
#if defined(__BIG_ENDIAN)
u8 enable_crypto:1;
u8 reserved2:7;
u8 command_type:4;
u8 reserved1:1;
u8 data_direction:2;
u8 interrupt:1;
#elif defined(__LITTLE_ENDIAN)
u8 reserved2:7;
u8 enable_crypto:1;
u8 interrupt:1;
u8 data_direction:2;
u8 reserved1:1;
u8 command_type:4;
#else
#error
#endif
__le32 dunl;
u8 ocs;
u8 cds;
__le16 ldbc;
__le32 dunu;
};
static_assert(sizeof(struct request_desc_header) == 16);
/**
* struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
* @header: UTRD header DW-0 to DW-3
* @command_desc_base_addr: UCD base address DW 4-5
* @response_upiu_length: response UPIU length DW-6
* @response_upiu_offset: response UPIU offset DW-6
* @prd_table_length: Physical region descriptor length DW-7
* @prd_table_offset: Physical region descriptor offset DW-7
*/
struct utp_transfer_req_desc {
/* DW 0-3 */
struct request_desc_header header;
/* DW 4-5*/
__le64 command_desc_base_addr;
/* DW 6 */
__le16 response_upiu_length;
__le16 response_upiu_offset;
/* DW 7 */
__le16 prd_table_length;
__le16 prd_table_offset;
};
/* MCQ Completion Queue Entry */
struct cq_entry {
/* DW 0-1 */
__le64 command_desc_base_addr;
/* DW 2 */
__le16 response_upiu_length;
__le16 response_upiu_offset;
/* DW 3 */
__le16 prd_table_length;
__le16 prd_table_offset;
/* DW 4 */
u8 overall_status;
u8 extended_error_code;
__le16 reserved_1;
/* DW 5 */
u8 task_tag;
u8 lun;
#if defined(__BIG_ENDIAN)
u8 ext_iid:4;
u8 iid:4;
#elif defined(__LITTLE_ENDIAN)
u8 iid:4;
u8 ext_iid:4;
#else
#error
#endif
u8 reserved_2;
/* DW 6-7 */
__le32 reserved_3[2];
};
static_assert(sizeof(struct cq_entry) == 32);
/*
* UTMRD structure.
*/
struct utp_task_req_desc {
/* DW 0-3 */
struct request_desc_header header;
/* DW 4-11 - Task request UPIU structure */
struct {
struct utp_upiu_header req_header;
__be32 input_param1;
__be32 input_param2;
__be32 input_param3;
__be32 __reserved1[2];
} upiu_req;
/* DW 12-19 - Task Management Response UPIU structure */
struct {
struct utp_upiu_header rsp_header;
__be32 output_param1;
__be32 output_param2;
__be32 __reserved2[3];
} upiu_rsp;
};
#endif /* End of Header */
linux-7.2.3/include/ufs/unipro.h
+469
View File
@@ -0,0 +1,469 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
*/
#ifndef _UNIPRO_H_
#define _UNIPRO_H_
/*
* M-TX Configuration Attributes
*/
#define TX_HIBERN8TIME_CAPABILITY 0x000F
#define TX_HS_DEEMPHASIS_SETTING_CAP 0x0012
#define TX_HS_PRESHOOT_SETTING_CAP 0x0015
#define TX_MODE 0x0021
#define TX_HSRATE_SERIES 0x0022
#define TX_HSGEAR 0x0023
#define TX_PWMGEAR 0x0024
#define TX_AMPLITUDE 0x0025
#define TX_HS_SLEWRATE 0x0026
#define TX_SYNC_SOURCE 0x0027
#define TX_HS_SYNC_LENGTH 0x0028
#define TX_HS_PREPARE_LENGTH 0x0029
#define TX_LS_PREPARE_LENGTH 0x002A
#define TX_HIBERN8_CONTROL 0x002B
#define TX_LCC_ENABLE 0x002C
#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
#define TX_BYPASS_8B10B_ENABLE 0x002E
#define TX_DRIVER_POLARITY 0x002F
#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
#define TX_LCC_SEQUENCER 0x0032
#define TX_MIN_ACTIVATETIME 0x0033
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
#define TX_HS_DEEMPHASIS_SETTING 0x0037
#define TX_HS_PRESHOOT_SETTING 0x003B
#define TX_REFCLKFREQ 0x00EB
#define TX_CFGCLKFREQVAL 0x00EC
#define CFGEXTRATTR 0x00F0
#define DITHERCTRL2 0x00F1
/*
* M-RX Configuration Attributes
*/
#define RX_HS_G5_ADAPT_INITIAL_CAP 0x0074
#define RX_HS_G6_ADAPT_INITIAL_CAP 0x007B
#define RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP 0x007D
#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
#define RX_HIBERN8TIME_CAPABILITY 0x0092
#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
#define RX_ADV_GRANULARITY_CAP 0x0098
#define RX_HIBERN8TIME_CAP 0x0092
#define RX_ADV_HIBERN8TIME_CAP 0x0099
#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
#define RX_HS_G4_ADAPT_INITIAL_CAP 0x009F
#define RX_MODE 0x00A1
#define RX_HSRATE_SERIES 0x00A2
#define RX_HSGEAR 0x00A3
#define RX_PWMGEAR 0x00A4
#define RX_LS_TERMINATED_ENABLE 0x00A5
#define RX_HS_UNTERMINATED_ENABLE 0x00A6
#define RX_ENTER_HIBERN8 0x00A7
#define RX_BYPASS_8B10B_ENABLE 0x00A8
#define RX_TERMINATION_FORCE_ENABLE 0x00A9
#define RXCALCTRL 0x00B4
#define RXSQCTRL 0x00B5
#define CFGRXCDR8 0x00BA
#define CFGRXOVR8 0x00BD
#define CFGRXOVR6 0x00BF
#define RX_FOM 0x00C2
#define RXDIRECTCTRL2 0x00C7
#define CFGRXOVR4 0x00E9
#define RX_REFCLKFREQ 0x00EB
#define RX_CFGCLKFREQVAL 0x00EC
#define CFGWIDEINLN 0x00F0
#define RX_EYEMON_CAP 0x00F1
#define RX_EYEMON_TIMING_MAX_STEPS_CAP 0x00F2
#define RX_EYEMON_TIMING_MAX_OFFSET_CAP 0x00F3
#define RX_EYEMON_VOLTAGE_MAX_STEPS_CAP 0x00F4
#define RX_EYEMON_VOLTAGE_MAX_OFFSET_CAP 0x00F5
#define RX_EYEMON_ENABLE 0x00F6
#define RX_EYEMON_TIMING_STEPS 0x00F7
#define RX_EYEMON_VOLTAGE_STEPS 0x00F8
#define RX_EYEMON_TARGET_TEST_COUNT 0x00F9
#define RX_EYEMON_TESTED_COUNT 0x00FA
#define RX_EYEMON_ERROR_COUNT 0x00FB
#define RX_EYEMON_START 0x00FC
#define RX_EYEMON_EXTENDED_ERROR_COUNT 0x00FD
#define ENARXDIRECTCFG4 0x00F2
#define ENARXDIRECTCFG3 0x00F3
#define ENARXDIRECTCFG2 0x00F4
#define RX_EYEMON_NEGATIVE_STEP_BIT BIT(6)
#define RX_EYEMON_EXTENDED_VRANGE_BIT BIT(6)
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
#define PREP_LEN(x) ((x) & 0xF)
#define RX_MIN_ACTIVATETIME_UNIT_US 100
#define HIBERN8TIME_UNIT_US 100
/*
* Common Block Attributes
*/
#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
#define ADAPT_LENGTH_MASK 0x7F
#define ADAPT_RANGE_BIT BIT(7)
#define IS_ADAPT_RANGE_COARSE(x) ((x) & ADAPT_RANGE_BIT)
/* Adapt definitions */
#define ADAPT_LENGTH_MAX 0x91
#define ADAPT_L0L3_LENGTH_MAX 0x90
#define ADAPT_L0L1L2L3_LENGTH_MAX 0x8C
#define TADAPT_FACTOR 650
#define TADAPT_L0L3_FACTOR (1 << 9)
#define TADAPT_L0L1L2L3_FACTOR (1 << 15)
/*
* PHY Adapter attributes
*/
#define PA_PHY_TYPE 0x1500
#define PA_AVAILTXDATALANES 0x1520
#define PA_MAXTXSPEEDFAST 0x1521
#define PA_MAXTXSPEEDSLOW 0x1522
#define PA_MAXRXSPEEDFAST 0x1541
#define PA_MAXRXSPEEDSLOW 0x1542
#define PA_TXLINKSTARTUPHS 0x1544
#define PA_AVAILRXDATALANES 0x1540
#define PA_MINRXTRAILINGCLOCKS 0x1543
#define PA_TXHSG1SYNCLENGTH 0x1552
#define PA_TXHSG2SYNCLENGTH 0x1554
#define PA_TXHSG3SYNCLENGTH 0x1556
#define PA_LOCAL_TX_LCC_ENABLE 0x155E
#define PA_ACTIVETXDATALANES 0x1560
#define PA_CONNECTEDTXDATALANES 0x1561
#define PA_TXFORCECLOCK 0x1562
#define PA_TXPWRMODE 0x1563
#define PA_TXTRAILINGCLOCKS 0x1564
#define PA_TXSPEEDFAST 0x1565
#define PA_TXSPEEDSLOW 0x1566
#define PA_TXPWRSTATUS 0x1567
#define PA_TXGEAR 0x1568
#define PA_TXTERMINATION 0x1569
#define PA_HSSERIES 0x156A
#define PA_LEGACYDPHYESCDL 0x1570
#define PA_PWRMODE 0x1571
#define PA_ACTIVERXDATALANES 0x1580
#define PA_CONNECTEDRXDATALANES 0x1581
#define PA_RXPWRSTATUS 0x1582
#define PA_RXGEAR 0x1583
#define PA_RXTERMINATION 0x1584
#define PA_MAXRXPWMGEAR 0x1586
#define PA_MAXRXHSGEAR 0x1587
#define PA_PACPREQTIMEOUT 0x1590
#define PA_PACPREQEOBTIMEOUT 0x1591
#define PA_REMOTEVERINFO 0x15A0
#define PA_LOGICALLANEMAP 0x15A1
#define PA_SLEEPNOCONFIGTIME 0x15A2
#define PA_STALLNOCONFIGTIME 0x15A3
#define PA_SAVECONFIGTIME 0x15A4
#define PA_RXHSUNTERMCAP 0x15A5
#define PA_RXLSTERMCAP 0x15A6
#define PA_HIBERN8TIME 0x15A7
#define PA_LOCALVERINFO 0x15A9
#define PA_GRANULARITY 0x15AA
#define PA_TACTIVATE 0x15A8
#define PA_PWRMODEUSERDATA0 0x15B0
#define PA_PWRMODEUSERDATA1 0x15B1
#define PA_PWRMODEUSERDATA2 0x15B2
#define PA_PWRMODEUSERDATA3 0x15B3
#define PA_PWRMODEUSERDATA4 0x15B4
#define PA_PWRMODEUSERDATA5 0x15B5
#define PA_PWRMODEUSERDATA6 0x15B6
#define PA_PWRMODEUSERDATA7 0x15B7
#define PA_PWRMODEUSERDATA8 0x15B8
#define PA_PWRMODEUSERDATA9 0x15B9
#define PA_PWRMODEUSERDATA10 0x15BA
#define PA_PWRMODEUSERDATA11 0x15BB
#define PA_PACPFRAMECOUNT 0x15C0
#define PA_PACPERRORCOUNT 0x15C1
#define PA_PHYTESTCONTROL 0x15C2
#define PA_TXHSG4SYNCLENGTH 0x15D0
#define PA_PEERRXHSG4ADAPTINITIAL 0x15D3
#define PA_TXHSADAPTTYPE 0x15D4
#define PA_TXHSG5SYNCLENGTH 0x15D6
#define PA_PEERRXHSG5ADAPTINITIAL 0x15D9
#define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3 0x15DE
#define PA_PEERRXHSG6ADAPTINITIALL0L3 0x15DF
#define PA_PEERRXHSG6ADAPTINITIALL0L1L2L3 0x15E0
#define PA_TXEQG1SETTING 0x15E1
#define PA_TXEQG2SETTING 0x15E2
#define PA_TXEQG3SETTING 0x15E3
#define PA_TXEQG4SETTING 0x15E4
#define PA_TXEQG5SETTING 0x15E5
#define PA_TXEQG6SETTING 0x15E6
#define PA_TXEQTRSETTING 0x15E7
#define PA_PEERTXEQTRSETTING 0x15E8
#define PA_PRECODEEN 0x15E9
#define PA_EQTR_GEAR 0x15EA
#define PA_TXADAPTLENGTH_EQTR 0x15EB
/* Adapt type for PA_TXHSADAPTTYPE attribute */
#define PA_REFRESH_ADAPT 0x00
#define PA_INITIAL_ADAPT 0x01
#define PA_NO_ADAPT 0x03
#define PA_TACTIVATE_TIME_UNIT_US 10
#define PA_HIBERN8_TIME_UNIT_US 100
/*Other attributes*/
#define VS_POWERSTATE 0xD083
#define VS_MPHYCFGUPDT 0xD085
#define VS_DEBUGOMC 0xD09E
#define VS_MPHYDISABLE 0xD0C1
#define PA_GRANULARITY_MIN_VAL 1
#define PA_GRANULARITY_MAX_VAL 6
/* PHY Adapter Protocol Constants */
#define PA_MAXDATALANES 4
/*
* TX EQTR's minimum TAdapt should not be less than 10us.
* This value is rounded up into the nearest Unit Intervals (UI)
*/
#define TX_EQTR_HS_G4_MIN_T_ADAPT 166400
#define TX_EQTR_HS_G5_MIN_T_ADAPT 332800
#define TX_EQTR_HS_G6_MIN_T_ADAPT 262144
#define TX_EQTR_HS_G4_ADAPT_DEFAULT 0x88
#define TX_EQTR_HS_G5_ADAPT_DEFAULT 0x89
#define TX_EQTR_HS_G6_ADAPT_DEFAULT 0x89
#define TX_EQTR_CAP_MASK 0x7F
#define TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT 8
#define TX_EQTR_ADAPT_RESERVED 0xFF
#define TX_HS_NUM_PRESHOOT 8
#define TX_HS_NUM_DEEMPHASIS 8
#define TX_HS_PRESHOOT_SHIFT 4
#define TX_HS_DEEMPHASIS_SHIFT 4
#define TX_HS_PRESHOOT_OFFSET 0
#define TX_HS_DEEMPHASIS_OFFSET 16
#define TX_HS_PRESHOOT_LANE_SHIFT(lane) \
(TX_HS_PRESHOOT_OFFSET + (lane) * TX_HS_PRESHOOT_SHIFT)
#define TX_HS_DEEMPHASIS_LANE_SHIFT(lane) \
(TX_HS_DEEMPHASIS_OFFSET + (lane) * TX_HS_DEEMPHASIS_SHIFT)
#define TX_HS_PRESHOOT_BITS(lane, val) \
((val) << TX_HS_PRESHOOT_LANE_SHIFT(lane))
#define TX_HS_DEEMPHASIS_BITS(lane, val) \
((val) << TX_HS_DEEMPHASIS_LANE_SHIFT(lane))
#define RX_FOM_VALUE_MASK 0x7F
#define RX_FOM_PRECODING_EN_BIT BIT(7)
#define PRECODEEN_TX_OFFSET 0
#define PRECODEEN_RX_OFFSET 4
#define PRECODEEN_TX_BIT(lane) (1 << (PRECODEEN_TX_OFFSET + (lane)))
#define PRECODEEN_RX_BIT(lane) (1 << (PRECODEEN_RX_OFFSET + (lane)))
enum ufs_tx_eq_preset {
UFS_TX_EQ_PRESET_P0,
UFS_TX_EQ_PRESET_P1,
UFS_TX_EQ_PRESET_P2,
UFS_TX_EQ_PRESET_P3,
UFS_TX_EQ_PRESET_P4,
UFS_TX_EQ_PRESET_P5,
UFS_TX_EQ_PRESET_P6,
UFS_TX_EQ_PRESET_P7,
UFS_TX_EQ_PRESET_MAX,
};
enum ufs_tx_hs_preshoot {
UFS_TX_HS_PRESHOOT_DB_0P0,
UFS_TX_HS_PRESHOOT_DB_0P4,
UFS_TX_HS_PRESHOOT_DB_0P8,
UFS_TX_HS_PRESHOOT_DB_1P2,
UFS_TX_HS_PRESHOOT_DB_1P6,
UFS_TX_HS_PRESHOOT_DB_2P5,
UFS_TX_HS_PRESHOOT_DB_3P5,
UFS_TX_HS_PRESHOOT_DB_4P7,
};
enum ufs_tx_hs_deemphasis {
UFS_TX_HS_DEEMPHASIS_DB_0P0,
UFS_TX_HS_DEEMPHASIS_DB_0P8,
UFS_TX_HS_DEEMPHASIS_DB_1P6,
UFS_TX_HS_DEEMPHASIS_DB_2P5,
UFS_TX_HS_DEEMPHASIS_DB_3P5,
UFS_TX_HS_DEEMPHASIS_DB_4P7,
UFS_TX_HS_DEEMPHASIS_DB_6P0,
UFS_TX_HS_DEEMPHASIS_DB_7P6,
};
enum ufs_eom_eye_mask {
UFS_EOM_EYE_MASK_M,
UFS_EOM_EYE_MASK_L,
UFS_EOM_EYE_MASK_U,
};
#define DL_FC0ProtectionTimeOutVal_Default 8191
#define DL_TC0ReplayTimeOutVal_Default 65535
#define DL_AFC0ReqTimeOutVal_Default 32767
#define DL_FC1ProtectionTimeOutVal_Default 8191
#define DL_TC1ReplayTimeOutVal_Default 65535
#define DL_AFC1ReqTimeOutVal_Default 32767
#define DME_LocalFC0ProtectionTimeOutVal 0xD041
#define DME_LocalTC0ReplayTimeOutVal 0xD042
#define DME_LocalAFC0ReqTimeOutVal 0xD043
enum ufs_op_mode {
LS_MODE = 1,
HS_MODE = 2,
};
/* PA power modes */
enum ufs_pa_pwr_mode {
FAST_MODE = 1,
SLOW_MODE = 2,
FASTAUTO_MODE = 4,
SLOWAUTO_MODE = 5,
UNCHANGED = 7,
};
#define PWRMODE_MASK 0xF
#define PWRMODE_RX_OFFSET 4
/* PA TX/RX Frequency Series */
enum ufs_hs_gear_rate {
PA_HS_MODE_A = 1,
PA_HS_MODE_B = 2,
};
enum ufs_pwm_gear_tag {
UFS_PWM_DONT_CHANGE, /* Don't change Gear */
UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
UFS_PWM_G2, /* PWM Gear 2 */
UFS_PWM_G3, /* PWM Gear 3 */
UFS_PWM_G4, /* PWM Gear 4 */
UFS_PWM_G5, /* PWM Gear 5 */
UFS_PWM_G6, /* PWM Gear 6 */
UFS_PWM_G7, /* PWM Gear 7 */
};
enum ufs_hs_gear_tag {
UFS_HS_DONT_CHANGE, /* Don't change Gear */
UFS_HS_G1, /* HS Gear 1 (default for reset) */
UFS_HS_G2, /* HS Gear 2 */
UFS_HS_G3, /* HS Gear 3 */
UFS_HS_G4, /* HS Gear 4 */
UFS_HS_G5, /* HS Gear 5 */
UFS_HS_G6, /* HS Gear 6 */
UFS_HS_GEAR_MAX = UFS_HS_G6,
};
enum ufs_lanes {
UFS_LANE_DONT_CHANGE, /* Don't change Lane */
UFS_LANE_1, /* Lane 1 (default for reset) */
UFS_LANE_2, /* Lane 2 */
};
enum ufs_unipro_ver {
UFS_UNIPRO_VER_RESERVED = 0,
UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
/* UniPro version field mask in PA_LOCALVERINFO */
UFS_UNIPRO_VER_MASK = 0xF,
};
/*
* Data Link Layer Attributes
*/
#define DL_TXPREEMPTIONCAP 0x2000
#define DL_TC0TXMAXSDUSIZE 0x2001
#define DL_TC0RXINITCREDITVAL 0x2002
#define DL_TC1TXMAXSDUSIZE 0x2003
#define DL_TC1RXINITCREDITVAL 0x2004
#define DL_TC0TXBUFFERSIZE 0x2005
#define DL_TC1TXBUFFERSIZE 0x2006
#define DL_TC0TXFCTHRESHOLD 0x2040
#define DL_FC0PROTTIMEOUTVAL 0x2041
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
#define DL_AFC0REQTIMEOUTVAL 0x2043
#define DL_AFC0CREDITTHRESHOLD 0x2044
#define DL_TC0OUTACKTHRESHOLD 0x2045
#define DL_PEERTC0PRESENT 0x2046
#define DL_PEERTC0RXINITCREVAL 0x2047
#define DL_TC1TXFCTHRESHOLD 0x2060
#define DL_FC1PROTTIMEOUTVAL 0x2061
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
#define DL_AFC1REQTIMEOUTVAL 0x2063
#define DL_AFC1CREDITTHRESHOLD 0x2064
#define DL_TC1OUTACKTHRESHOLD 0x2065
#define DL_PEERTC1PRESENT 0x2066
#define DL_PEERTC1RXINITCREVAL 0x2067
/*
* Network Layer Attributes
*/
#define N_DEVICEID 0x3000
#define N_DEVICEID_VALID 0x3001
#define N_TC0TXMAXSDUSIZE 0x3020
#define N_TC1TXMAXSDUSIZE 0x3021
/*
* Transport Layer Attributes
*/
#define T_NUMCPORTS 0x4000
#define T_NUMTESTFEATURES 0x4001
#define T_CONNECTIONSTATE 0x4020
#define T_PEERDEVICEID 0x4021
#define T_PEERCPORTID 0x4022
#define T_TRAFFICCLASS 0x4023
#define T_PROTOCOLID 0x4024
#define T_CPORTFLAGS 0x4025
#define T_TXTOKENVALUE 0x4026
#define T_RXTOKENVALUE 0x4027
#define T_LOCALBUFFERSPACE 0x4028
#define T_PEERBUFFERSPACE 0x4029
#define T_CREDITSTOSEND 0x402A
#define T_CPORTMODE 0x402B
#define T_TC0TXMAXSDUSIZE 0x4060
#define T_TC1TXMAXSDUSIZE 0x4061
/* CPort setting */
#define E2EFC_ON (1 << 0)
#define E2EFC_OFF (0 << 0)
#define CSD_N_ON (0 << 1)
#define CSD_N_OFF (1 << 1)
#define CSV_N_ON (0 << 2)
#define CSV_N_OFF (1 << 2)
#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
/* CPort connection state */
enum {
CPORT_IDLE = 0,
CPORT_CONNECTED,
};
#endif /* _UNIPRO_H_ */