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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/sound/soc/qcom/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
menuconfig SND_SOC_QCOM
tristate "Qualcomm"
depends on ARCH_QCOM || COMPILE_TEST
help
Say Y or M if you want to add support to use audio devices
in Qualcomm Technologies SOC-based platforms.
if SND_SOC_QCOM
config SND_SOC_LPASS_CPU
tristate
select REGMAP_MMIO
config SND_SOC_LPASS_HDMI
tristate
select REGMAP_MMIO
config SND_SOC_LPASS_PLATFORM
tristate
select REGMAP_MMIO
config SND_SOC_LPASS_CDC_DMA
tristate
select REGMAP_MMIO
config SND_SOC_LPASS_IPQ806X
tristate
select SND_SOC_LPASS_CPU
select SND_SOC_LPASS_PLATFORM
config SND_SOC_LPASS_APQ8016
tristate
select SND_SOC_LPASS_CPU
select SND_SOC_LPASS_PLATFORM
config SND_SOC_LPASS_SC7180
tristate
select SND_SOC_LPASS_CPU
select SND_SOC_LPASS_PLATFORM
select SND_SOC_LPASS_HDMI
config SND_SOC_LPASS_SC7280
tristate
select SND_SOC_LPASS_CPU
select SND_SOC_LPASS_PLATFORM
select SND_SOC_LPASS_HDMI
select SND_SOC_LPASS_CDC_DMA
config SND_SOC_STORM
tristate "ASoC I2S support for Storm boards"
depends on GPIOLIB
select SND_SOC_LPASS_IPQ806X
select SND_SOC_MAX98357A
help
Say Y or M if you want add support for SoC audio on the
Qualcomm Technologies IPQ806X-based Storm board.
config SND_SOC_APQ8016_SBC
tristate "SoC Audio support for APQ8016 SBC platforms"
select SND_SOC_LPASS_APQ8016
select SND_SOC_QCOM_COMMON
help
Support for Qualcomm Technologies LPASS audio block in
APQ8016 SOC-based systems.
Say Y if you want to use audio devices on MI2S.
config SND_SOC_QCOM_COMMON
tristate
config SND_SOC_QCOM_SDW
tristate
config SND_SOC_QDSP6_COMMON
tristate
config SND_SOC_QDSP6_CORE
tristate
config SND_SOC_QDSP6_AFE
tristate
config SND_SOC_QDSP6_AFE_DAI
tristate
config SND_SOC_QDSP6_AFE_CLOCKS
tristate
config SND_SOC_QDSP6_ADM
tristate
config SND_SOC_QDSP6_ROUTING
tristate
config SND_SOC_QDSP6_ASM
tristate
config SND_SOC_QDSP6_ASM_DAI
select SND_SOC_COMPRESS
tristate
config SND_SOC_QDSP6_APM_DAI
tristate
select SND_SOC_COMPRESS
config SND_SOC_QDSP6_APM_LPASS_DAI
tristate
config SND_SOC_QDSP6_APM
tristate
select SND_SOC_QDSP6_APM_DAI
select SND_SOC_QDSP6_APM_LPASS_DAI
config SND_SOC_QDSP6_PRM_LPASS_CLOCKS
tristate
config SND_SOC_QDSP6_PRM
tristate
select SND_SOC_QDSP6_PRM_LPASS_CLOCKS
config SND_SOC_QCOM_OFFLOAD_UTILS
tristate
config SND_SOC_QDSP6_USB
tristate "SoC ALSA USB offloading backing for QDSP6"
depends on SND_SOC_USB
select AUXILIARY_BUS
select SND_SOC_QCOM_OFFLOAD_UTILS
help
Adds support for USB offloading for QDSP6 ASoC
based platform sound cards. This will enable the
Q6USB DPCM backend DAI link, which will interact
with the SoC USB framework to initialize a session
with active USB SND devices.
config SND_SOC_QDSP6
tristate "SoC ALSA audio driver for QDSP6"
depends on QCOM_APR
depends on COMMON_CLK
select SND_SOC_QDSP6_COMMON
select SND_SOC_QDSP6_CORE
select SND_SOC_QDSP6_AFE
select SND_SOC_QDSP6_AFE_DAI
select SND_SOC_QDSP6_AFE_CLOCKS
select SND_SOC_QDSP6_ADM
select SND_SOC_QDSP6_ROUTING
select SND_SOC_QDSP6_ASM
select SND_SOC_QDSP6_ASM_DAI
select SND_SOC_TOPOLOGY
select SND_SOC_QDSP6_APM
select SND_SOC_QDSP6_PRM
help
To add support for MSM QDSP6 Soc Audio.
This will enable sound soc platform specific
audio drivers. This includes q6asm, q6adm,
q6afe interfaces to DSP using apr.
config SND_SOC_MSM8996
tristate "SoC Machine driver for MSM8996 and APQ8096 boards"
depends on QCOM_APR
depends on COMMON_CLK
select SND_SOC_QDSP6
select SND_SOC_QCOM_COMMON
help
Support for Qualcomm Technologies LPASS audio block in
APQ8096 SoC-based systems.
Say Y if you want to use audio device on this SoCs
config SND_SOC_SDM845
tristate "SoC Machine driver for SDM845 boards"
depends on QCOM_APR && I2C && SOUNDWIRE
depends on COMMON_CLK
select SND_SOC_QDSP6
select SND_SOC_QCOM_COMMON
select SND_SOC_QCOM_SDW
select SND_SOC_RT5663
select SND_SOC_MAX98927
imply SND_SOC_CROS_EC_CODEC
help
To add support for audio on Qualcomm Technologies Inc.
SDM845 SoC-based systems.
Say Y if you want to use audio device on this SoCs.
config SND_SOC_SM8250
tristate "SoC Machine driver for SM8250 boards"
depends on QCOM_APR && SOUNDWIRE
depends on COMMON_CLK
depends on SND_SOC_QCOM_OFFLOAD_UTILS || !SND_SOC_QCOM_OFFLOAD_UTILS
select SND_SOC_QDSP6
select SND_SOC_QCOM_COMMON
select SND_SOC_QCOM_SDW
help
To add support for audio on Qualcomm Technologies Inc.
SM8250 SoC-based systems.
Say Y if you want to use audio device on this SoCs.
config SND_SOC_SC8280XP
tristate "SoC Machine driver for SC8280XP boards"
depends on QCOM_APR && SOUNDWIRE
depends on COMMON_CLK
select SND_SOC_QDSP6
select SND_SOC_QCOM_COMMON
select SND_SOC_QCOM_SDW
help
To add support for audio on Qualcomm Technologies Inc.
SC8280XP SoC-based systems.
Say Y if you want to use audio device on this SoCs.
config SND_SOC_SC7180
tristate "SoC Machine driver for SC7180 boards"
depends on I2C && GPIOLIB
depends on SOUNDWIRE || SOUNDWIRE=n
select SND_SOC_QCOM_COMMON
select SND_SOC_LPASS_SC7180
select SND_SOC_MAX98357A
select SND_SOC_RT5682_I2C
select SND_SOC_RT5682S
select SND_SOC_ADAU7002
help
To add support for audio on Qualcomm Technologies Inc.
SC7180 SoC-based systems.
Say Y if you want to use audio device on this SoCs.
config SND_SOC_SC7280
tristate "SoC Machine driver for SC7280 boards"
depends on I2C && SOUNDWIRE
select SND_SOC_QCOM_COMMON
select SND_SOC_QCOM_SDW
select SND_SOC_LPASS_SC7280
select SND_SOC_MAX98357A
select SND_SOC_WCD938X_SDW
select SND_SOC_LPASS_MACRO_COMMON
imply SND_SOC_LPASS_RX_MACRO
imply SND_SOC_LPASS_TX_MACRO
select SND_SOC_RT5682_I2C
select SND_SOC_RT5682S
help
Add support for audio on Qualcomm Technologies Inc.
SC7280 SoC-based systems.
Say Y or M if you want to use audio device on this SoCs.
config SND_SOC_X1E80100
tristate "SoC Machine driver for X1E80100 boards"
depends on QCOM_APR && SOUNDWIRE
depends on COMMON_CLK
select SND_SOC_QDSP6
select SND_SOC_QCOM_COMMON
select SND_SOC_QCOM_SDW
help
Add support for audio on Qualcomm Technologies Inc.
X1E80100 SoC-based systems.
Say Y or M if you want to use audio device on this SoCs.
endif #SND_SOC_QCOM
linux-7.2.3/sound/soc/qcom/Makefile
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# SPDX-License-Identifier: GPL-2.0
# Platform
snd-soc-lpass-cpu-y := lpass-cpu.o
snd-soc-lpass-cdc-dma-y := lpass-cdc-dma.o
snd-soc-lpass-hdmi-y := lpass-hdmi.o
snd-soc-lpass-platform-y := lpass-platform.o
snd-soc-lpass-ipq806x-y := lpass-ipq806x.o
snd-soc-lpass-apq8016-y := lpass-apq8016.o
snd-soc-lpass-sc7180-y := lpass-sc7180.o
snd-soc-lpass-sc7280-y := lpass-sc7280.o
obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o
obj-$(CONFIG_SND_SOC_LPASS_CDC_DMA) += snd-soc-lpass-cdc-dma.o
obj-$(CONFIG_SND_SOC_LPASS_HDMI) += snd-soc-lpass-hdmi.o
obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o
obj-$(CONFIG_SND_SOC_LPASS_IPQ806X) += snd-soc-lpass-ipq806x.o
obj-$(CONFIG_SND_SOC_LPASS_APQ8016) += snd-soc-lpass-apq8016.o
obj-$(CONFIG_SND_SOC_LPASS_SC7180) += snd-soc-lpass-sc7180.o
obj-$(CONFIG_SND_SOC_LPASS_SC7280) += snd-soc-lpass-sc7280.o
# Machine
snd-soc-storm-y := storm.o
snd-soc-apq8016-sbc-y := apq8016_sbc.o
snd-soc-apq8096-y := apq8096.o
snd-soc-sc7180-y := sc7180.o
snd-soc-sc7280-y := sc7280.o
snd-soc-sdm845-y := sdm845.o
snd-soc-sm8250-y := sm8250.o
snd-soc-sc8280xp-y := sc8280xp.o
snd-soc-qcom-common-y := common.o
snd-soc-qcom-sdw-y := sdw.o
snd-soc-x1e80100-y := x1e80100.o
snd-soc-qcom-offload-utils-objs := usb_offload_utils.o
obj-$(CONFIG_SND_SOC_STORM) += snd-soc-storm.o
obj-$(CONFIG_SND_SOC_APQ8016_SBC) += snd-soc-apq8016-sbc.o
obj-$(CONFIG_SND_SOC_MSM8996) += snd-soc-apq8096.o
obj-$(CONFIG_SND_SOC_SC7180) += snd-soc-sc7180.o
obj-$(CONFIG_SND_SOC_SC7280) += snd-soc-sc7280.o
obj-$(CONFIG_SND_SOC_SC8280XP) += snd-soc-sc8280xp.o
obj-$(CONFIG_SND_SOC_SDM845) += snd-soc-sdm845.o
obj-$(CONFIG_SND_SOC_SM8250) += snd-soc-sm8250.o
obj-$(CONFIG_SND_SOC_QCOM_COMMON) += snd-soc-qcom-common.o
obj-$(CONFIG_SND_SOC_QCOM_SDW) += snd-soc-qcom-sdw.o
obj-$(CONFIG_SND_SOC_X1E80100) += snd-soc-x1e80100.o
obj-$(CONFIG_SND_SOC_QCOM_OFFLOAD_UTILS) += snd-soc-qcom-offload-utils.o
#DSP lib
obj-$(CONFIG_SND_SOC_QDSP6) += qdsp6/
linux-7.2.3/sound/soc/qcom/apq8016_sbc.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <uapi/linux/input-event-codes.h>
#include <dt-bindings/sound/apq8016-lpass.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "common.h"
#include "qdsp6/q6afe.h"
#define MI2S_COUNT (MI2S_QUATERNARY + 1)
struct apq8016_sbc_data {
struct snd_soc_card card;
void __iomem *mic_iomux;
void __iomem *spkr_iomux;
struct snd_soc_jack jack;
bool jack_setup;
int mi2s_clk_count[MI2S_COUNT];
};
#define MIC_CTRL_TER_WS_SLAVE_SEL BIT(21)
#define MIC_CTRL_QUA_WS_SLAVE_SEL_10 BIT(17)
#define MIC_CTRL_TLMM_SCLK_EN BIT(1)
#define SPKR_CTL_PRI_WS_SLAVE_SEL_11 (BIT(17) | BIT(16))
#define SPKR_CTL_TLMM_MCLK_EN BIT(1)
#define SPKR_CTL_TLMM_SCLK_EN BIT(2)
#define SPKR_CTL_TLMM_DATA1_EN BIT(3)
#define SPKR_CTL_TLMM_WS_OUT_SEL_MASK GENMASK(7, 6)
#define SPKR_CTL_TLMM_WS_OUT_SEL_SEC BIT(6)
#define SPKR_CTL_TLMM_WS_EN_SEL_MASK GENMASK(19, 18)
#define SPKR_CTL_TLMM_WS_EN_SEL_SEC BIT(18)
#define DEFAULT_MCLK_RATE 9600000
#define MI2S_BCLK_RATE 1536000
static struct snd_soc_jack_pin apq8016_sbc_jack_pins[] = {
{
.pin = "Mic Jack",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
};
static int apq8016_dai_init(struct snd_soc_pcm_runtime *rtd, int mi2s)
{
struct snd_soc_dai *codec_dai;
struct snd_soc_component *component;
struct snd_soc_card *card = rtd->card;
struct apq8016_sbc_data *pdata = snd_soc_card_get_drvdata(card);
int i, rval;
u32 value;
switch (mi2s) {
case MI2S_PRIMARY:
writel(readl(pdata->spkr_iomux) | SPKR_CTL_PRI_WS_SLAVE_SEL_11,
pdata->spkr_iomux);
break;
case MI2S_QUATERNARY:
/* Configure the Quat MI2S to TLMM */
writel(readl(pdata->mic_iomux) | MIC_CTRL_QUA_WS_SLAVE_SEL_10 |
MIC_CTRL_TLMM_SCLK_EN,
pdata->mic_iomux);
break;
case MI2S_SECONDARY:
/* Clear TLMM_WS_OUT_SEL and TLMM_WS_EN_SEL fields */
value = readl(pdata->spkr_iomux) &
~(SPKR_CTL_TLMM_WS_OUT_SEL_MASK | SPKR_CTL_TLMM_WS_EN_SEL_MASK);
/* Configure the Sec MI2S to TLMM */
writel(value | SPKR_CTL_TLMM_MCLK_EN | SPKR_CTL_TLMM_SCLK_EN |
SPKR_CTL_TLMM_DATA1_EN | SPKR_CTL_TLMM_WS_OUT_SEL_SEC |
SPKR_CTL_TLMM_WS_EN_SEL_SEC, pdata->spkr_iomux);
break;
case MI2S_TERTIARY:
writel(readl(pdata->mic_iomux) | MIC_CTRL_TER_WS_SLAVE_SEL |
MIC_CTRL_TLMM_SCLK_EN,
pdata->mic_iomux);
break;
default:
dev_err(card->dev, "unsupported cpu dai configuration\n");
return -EINVAL;
}
if (!pdata->jack_setup) {
struct snd_jack *jack;
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_HEADPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4,
&pdata->jack,
apq8016_sbc_jack_pins,
ARRAY_SIZE(apq8016_sbc_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headphone Jack\n");
return rval;
}
jack = pdata->jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
pdata->jack_setup = true;
}
for_each_rtd_codec_dais(rtd, i, codec_dai) {
component = codec_dai->component;
/* Set default mclk for internal codec */
rval = snd_soc_component_set_sysclk(component, 0, 0, DEFAULT_MCLK_RATE,
SND_SOC_CLOCK_IN);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set mclk: %d\n", rval);
return rval;
}
rval = snd_soc_component_set_jack(component, &pdata->jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
return 0;
}
static int apq8016_sbc_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return apq8016_dai_init(rtd, cpu_dai->id);
}
static void apq8016_sbc_add_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link)
link->init = apq8016_sbc_dai_init;
}
static int qdsp6_dai_get_lpass_id(struct snd_soc_dai *cpu_dai)
{
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
return MI2S_PRIMARY;
case SECONDARY_MI2S_RX:
case SECONDARY_MI2S_TX:
return MI2S_SECONDARY;
case TERTIARY_MI2S_RX:
case TERTIARY_MI2S_TX:
return MI2S_TERTIARY;
case QUATERNARY_MI2S_RX:
case QUATERNARY_MI2S_TX:
return MI2S_QUATERNARY;
default:
return -EINVAL;
}
}
static int msm8916_qdsp6_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
return apq8016_dai_init(rtd, qdsp6_dai_get_lpass_id(cpu_dai));
}
static int msm8916_qdsp6_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct apq8016_sbc_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
int mi2s, ret;
mi2s = qdsp6_dai_get_lpass_id(cpu_dai);
if (mi2s < 0)
return mi2s;
if (++data->mi2s_clk_count[mi2s] > 1)
return 0;
ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_BIT_CLK, MI2S_BCLK_RATE, 0);
if (ret)
dev_err(card->dev, "Failed to enable LPAIF bit clk: %d\n", ret);
return ret;
}
static void msm8916_qdsp6_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct apq8016_sbc_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
int mi2s, ret;
mi2s = qdsp6_dai_get_lpass_id(cpu_dai);
if (mi2s < 0)
return;
if (--data->mi2s_clk_count[mi2s] > 0)
return;
ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_BIT_CLK, 0, 0);
if (ret)
dev_err(card->dev, "Failed to disable LPAIF bit clk: %d\n", ret);
}
static const struct snd_soc_ops msm8916_qdsp6_be_ops = {
.startup = msm8916_qdsp6_startup,
.shutdown = msm8916_qdsp6_shutdown,
};
static int msm8916_qdsp6_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static void msm8916_qdsp6_add_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
/* Make it obvious to userspace that QDSP6 is used */
card->components = "qdsp6";
for_each_card_prelinks(card, i, link) {
if (link->no_pcm) {
link->init = msm8916_qdsp6_dai_init;
link->ops = &msm8916_qdsp6_be_ops;
link->be_hw_params_fixup = msm8916_qdsp6_be_hw_params_fixup;
}
}
}
static const struct snd_kcontrol_new apq8016_sbc_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Mic Jack"),
};
static const struct snd_soc_dapm_widget apq8016_sbc_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_MIC("Handset Mic", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Secondary Mic", NULL),
SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("Digital Mic2", NULL),
};
static int apq8016_sbc_platform_probe(struct platform_device *pdev)
{
void (*add_ops)(struct snd_soc_card *card);
struct device *dev = &pdev->dev;
struct snd_soc_card *card;
struct apq8016_sbc_data *data;
int ret;
add_ops = device_get_match_data(&pdev->dev);
if (!add_ops)
return -EINVAL;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card = &data->card;
card->dev = dev;
card->owner = THIS_MODULE;
card->dapm_widgets = apq8016_sbc_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(apq8016_sbc_dapm_widgets);
card->controls = apq8016_sbc_snd_controls;
card->num_controls = ARRAY_SIZE(apq8016_sbc_snd_controls);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
data->mic_iomux = devm_platform_ioremap_resource_byname(pdev, "mic-iomux");
if (IS_ERR(data->mic_iomux))
return PTR_ERR(data->mic_iomux);
data->spkr_iomux = devm_platform_ioremap_resource_byname(pdev, "spkr-iomux");
if (IS_ERR(data->spkr_iomux))
return PTR_ERR(data->spkr_iomux);
snd_soc_card_set_drvdata(card, data);
add_ops(card);
return devm_snd_soc_register_card(&pdev->dev, card);
}
static const struct of_device_id apq8016_sbc_device_id[] __maybe_unused = {
{ .compatible = "qcom,apq8016-sbc-sndcard", .data = apq8016_sbc_add_ops },
{ .compatible = "qcom,msm8916-qdsp6-sndcard", .data = msm8916_qdsp6_add_ops },
{},
};
MODULE_DEVICE_TABLE(of, apq8016_sbc_device_id);
static struct platform_driver apq8016_sbc_platform_driver = {
.driver = {
.name = "qcom-apq8016-sbc",
.of_match_table = of_match_ptr(apq8016_sbc_device_id),
},
.probe = apq8016_sbc_platform_probe,
};
module_platform_driver(apq8016_sbc_platform_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org");
MODULE_DESCRIPTION("APQ8016 ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/apq8096.c
+144
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@@ -0,0 +1,144 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include "common.h"
#define SLIM_MAX_TX_PORTS 16
#define SLIM_MAX_RX_PORTS 16
#define WCD9335_DEFAULT_MCLK_RATE 9600000
static int apq8096_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
return 0;
}
static int msm_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
int ret = 0;
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
if (ret != 0 && ret != -ENOTSUPP) {
pr_err("failed to get codec chan map, err:%d\n", ret);
goto end;
} else if (ret == -ENOTSUPP) {
return 0;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
rx_ch_cnt, rx_ch);
else
ret = snd_soc_dai_set_channel_map(cpu_dai, tx_ch_cnt, tx_ch,
0, NULL);
if (ret != 0 && ret != -ENOTSUPP)
pr_err("Failed to set cpu chan map, err:%d\n", ret);
else if (ret == -ENOTSUPP)
ret = 0;
end:
return ret;
}
static const struct snd_soc_ops apq8096_ops = {
.hw_params = msm_snd_hw_params,
};
static int apq8096_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
/*
* Codec SLIMBUS configuration
* RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13
* TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
* TX14, TX15, TX16
*/
unsigned int rx_ch[SLIM_MAX_RX_PORTS] = {144, 145, 146, 147, 148, 149,
150, 151, 152, 153, 154, 155, 156};
unsigned int tx_ch[SLIM_MAX_TX_PORTS] = {128, 129, 130, 131, 132, 133,
134, 135, 136, 137, 138, 139,
140, 141, 142, 143};
snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
snd_soc_dai_set_sysclk(codec_dai, 0, WCD9335_DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
return 0;
}
static void apq8096_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->be_hw_params_fixup = apq8096_be_hw_params_fixup;
link->init = apq8096_init;
link->ops = &apq8096_ops;
}
}
}
static int apq8096_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->driver_name = "apq8096";
card->dev = dev;
card->owner = THIS_MODULE;
dev_set_drvdata(dev, card);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
apq8096_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id msm_snd_apq8096_dt_match[] = {
{.compatible = "qcom,apq8096-sndcard"},
{}
};
MODULE_DEVICE_TABLE(of, msm_snd_apq8096_dt_match);
static struct platform_driver msm_snd_apq8096_driver = {
.probe = apq8096_platform_probe,
.driver = {
.name = "msm-snd-apq8096",
.of_match_table = msm_snd_apq8096_dt_match,
},
};
module_platform_driver(msm_snd_apq8096_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org");
MODULE_DESCRIPTION("APQ8096 ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/common.c
+267
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@@ -0,0 +1,267 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited.
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <sound/jack.h>
#include <linux/input-event-codes.h>
#include "common.h"
#define NAME_SIZE 32
static const struct snd_soc_dapm_widget qcom_jack_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_SPK("DP0 Jack", NULL),
SND_SOC_DAPM_SPK("DP1 Jack", NULL),
SND_SOC_DAPM_SPK("DP2 Jack", NULL),
SND_SOC_DAPM_SPK("DP3 Jack", NULL),
SND_SOC_DAPM_SPK("DP4 Jack", NULL),
SND_SOC_DAPM_SPK("DP5 Jack", NULL),
SND_SOC_DAPM_SPK("DP6 Jack", NULL),
SND_SOC_DAPM_SPK("DP7 Jack", NULL),
};
int qcom_snd_parse_of(struct snd_soc_card *card)
{
struct device *dev = card->dev;
struct snd_soc_dai_link *link;
struct of_phandle_args args;
struct snd_soc_dai_link_component *dlc;
int ret, num_links;
ret = snd_soc_of_parse_card_name(card, "model");
if (ret == 0 && !card->name)
/* Deprecated, only for compatibility with old device trees */
ret = snd_soc_of_parse_card_name(card, "qcom,model");
if (ret) {
dev_err(dev, "Error parsing card name: %d\n", ret);
return ret;
}
if (of_property_present(dev->of_node, "widgets")) {
ret = snd_soc_of_parse_audio_simple_widgets(card, "widgets");
if (ret)
return ret;
}
/* DAPM routes */
if (of_property_present(dev->of_node, "audio-routing")) {
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret)
return ret;
}
/* Deprecated, only for compatibility with old device trees */
if (of_property_present(dev->of_node, "qcom,audio-routing")) {
ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
if (ret)
return ret;
}
ret = snd_soc_of_parse_pin_switches(card, "pin-switches");
if (ret)
return ret;
ret = snd_soc_of_parse_aux_devs(card, "aux-devs");
if (ret)
return ret;
/* Populate links */
num_links = of_get_available_child_count(dev->of_node);
/* Allocate the DAI link array */
card->dai_link = devm_kcalloc(dev, num_links, sizeof(*link), GFP_KERNEL);
if (!card->dai_link)
return -ENOMEM;
card->num_links = num_links;
link = card->dai_link;
for_each_available_child_of_node_scoped(dev->of_node, np) {
dlc = devm_kcalloc(dev, 2, sizeof(*dlc), GFP_KERNEL);
if (!dlc)
return -ENOMEM;
link->cpus = &dlc[0];
link->platforms = &dlc[1];
link->num_cpus = 1;
link->num_platforms = 1;
ret = of_property_read_string(np, "link-name", &link->name);
if (ret) {
dev_err(card->dev, "error getting codec dai_link name\n");
return ret;
}
struct device_node *cpu __free(device_node) =
of_get_child_by_name(np, "cpu");
struct device_node *platform __free(device_node) =
of_get_child_by_name(np, "platform");
struct device_node *codec __free(device_node) =
of_get_child_by_name(np, "codec");
if (!cpu) {
dev_err(dev, "%s: Can't find cpu DT node\n", link->name);
return -EINVAL;
}
ret = snd_soc_of_get_dlc(cpu, &args, link->cpus, 0);
if (ret) {
dev_err_probe(card->dev, ret,
"%s: error getting cpu dai name\n", link->name);
return ret;
}
link->id = args.args[0];
if (link->id >= LPASS_MAX_PORT) {
dev_err(dev, "%s: Invalid cpu dai id %d\n", link->name, link->id);
return -EINVAL;
}
if (platform) {
link->platforms->of_node = of_parse_phandle(platform,
"sound-dai",
0);
if (!link->platforms->of_node) {
dev_err(card->dev, "%s: platform dai not found\n", link->name);
return -EINVAL;
}
} else {
link->platforms->of_node = link->cpus->of_node;
}
if (codec) {
ret = snd_soc_of_get_dai_link_codecs(dev, codec, link);
if (ret < 0) {
dev_err_probe(card->dev, ret,
"%s: codec dai not found\n", link->name);
return ret;
}
if (platform) {
/* DPCM backend */
link->no_pcm = 1;
link->ignore_pmdown_time = 1;
}
} else {
/* DPCM frontend */
link->codecs = &snd_soc_dummy_dlc;
link->num_codecs = 1;
link->dynamic = 1;
}
if (platform || !codec) {
/* DPCM */
link->ignore_suspend = 1;
link->nonatomic = 1;
}
link->stream_name = link->name;
link++;
}
if (!card->dapm_widgets) {
card->dapm_widgets = qcom_jack_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(qcom_jack_snd_widgets);
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_parse_of);
static struct snd_soc_jack_pin qcom_headset_jack_pins[] = {
/* Headset */
{
.pin = "Mic Jack",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
};
int qcom_snd_wcd_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *jack, bool *jack_setup)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_card *card = rtd->card;
int rval, i;
if (!*jack_setup) {
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_MECHANICAL |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4 | SND_JACK_BTN_5,
jack, qcom_headset_jack_pins,
ARRAY_SIZE(qcom_headset_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headphone Jack\n");
return rval;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_MEDIA);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
*jack_setup = true;
}
switch (cpu_dai->id) {
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_component_set_jack(codec_dai->component,
jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_wcd_jack_setup);
int qcom_snd_dp_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *dp_jack, int dp_pcm_id)
{
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_card *card = rtd->card;
char jack_name[NAME_SIZE];
int rval, i;
snprintf(jack_name, sizeof(jack_name), "DP%d Jack", dp_pcm_id);
rval = snd_soc_card_jack_new(card, jack_name, SND_JACK_AVOUT, dp_jack);
if (rval)
return rval;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_component_set_jack(codec_dai->component, dp_jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_dp_jack_setup);
MODULE_DESCRIPTION("ASoC Qualcomm helper functions");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/common.h
+19
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@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#ifndef __QCOM_SND_COMMON_H__
#define __QCOM_SND_COMMON_H__
#include <dt-bindings/sound/qcom,q6afe.h>
#include <sound/soc.h>
#define LPASS_MAX_PORT (SENARY_MI2S_TX + 1)
int qcom_snd_parse_of(struct snd_soc_card *card);
int qcom_snd_wcd_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *jack, bool *jack_setup);
int qcom_snd_dp_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *dp_jack, int id);
#endif
linux-7.2.3/sound/soc/qcom/lpass-apq8016.c
+309
View File
@@ -0,0 +1,309 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* lpass-apq8016.c -- ALSA SoC CPU DAI driver for APQ8016 LPASS
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/apq8016-lpass.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static struct snd_soc_dai_driver apq8016_lpass_cpu_dai_driver[] = {
[MI2S_PRIMARY] = {
.id = MI2S_PRIMARY,
.name = "Primary MI2S",
.playback = {
.stream_name = "Primary Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
[MI2S_SECONDARY] = {
.id = MI2S_SECONDARY,
.name = "Secondary MI2S",
.playback = {
.stream_name = "Secondary Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
[MI2S_TERTIARY] = {
.id = MI2S_TERTIARY,
.name = "Tertiary MI2S",
.capture = {
.stream_name = "Tertiary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
[MI2S_QUATERNARY] = {
.id = MI2S_QUATERNARY,
.name = "Quatenary MI2S",
.playback = {
.stream_name = "Quatenary Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.stream_name = "Quatenary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
};
static int apq8016_lpass_alloc_dma_channel(struct lpass_data *drvdata,
int direction, unsigned int dai_id)
{
const struct lpass_variant *v = drvdata->variant;
int chan = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
v->rdma_channels);
if (chan >= v->rdma_channels)
return -EBUSY;
} else {
chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
v->wrdma_channel_start +
v->wrdma_channels,
v->wrdma_channel_start);
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->dma_ch_bit_map);
return chan;
}
static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
clear_bit(chan, &drvdata->dma_ch_bit_map);
return 0;
}
static int apq8016_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
const struct lpass_variant *variant = drvdata->variant;
struct device *dev = &pdev->dev;
int ret, i;
drvdata->clks = devm_kcalloc(dev, variant->num_clks,
sizeof(*drvdata->clks), GFP_KERNEL);
if (!drvdata->clks)
return -ENOMEM;
drvdata->num_clks = variant->num_clks;
for (i = 0; i < drvdata->num_clks; i++)
drvdata->clks[i].id = variant->clk_name[i];
ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "Failed to get clocks %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "apq8016 clk_enable failed\n");
return ret;
}
drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
if (IS_ERR(drvdata->ahbix_clk)) {
dev_err(dev, "error getting ahbix-clk: %ld\n",
PTR_ERR(drvdata->ahbix_clk));
ret = PTR_ERR(drvdata->ahbix_clk);
goto err_ahbix_clk;
}
ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
if (ret) {
dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
dev_dbg(dev, "set ahbix_clk rate to %lu\n",
clk_get_rate(drvdata->ahbix_clk));
ret = clk_prepare_enable(drvdata->ahbix_clk);
if (ret) {
dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
return 0;
err_ahbix_clk:
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return ret;
}
static int apq8016_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
clk_disable_unprepare(drvdata->ahbix_clk);
return 0;
}
static const struct lpass_variant apq8016_data = {
.i2sctrl_reg_base = 0x1000,
.i2sctrl_reg_stride = 0x1000,
.i2s_ports = 4,
.irq_reg_base = 0x6000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0x8400,
.rdma_reg_stride = 0x1000,
.rdma_channels = 2,
.dmactl_audif_start = 1,
.wrdma_reg_base = 0xB000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 2,
.loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
.spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
.spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
.spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
.micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
.micmode = REG_FIELD_ID(0x1000, 4, 7, 4, 0x1000),
.micmono = REG_FIELD_ID(0x1000, 3, 3, 4, 0x1000),
.wssrc = REG_FIELD_ID(0x1000, 2, 2, 4, 0x1000),
.bitwidth = REG_FIELD_ID(0x1000, 0, 1, 4, 0x1000),
.rdma_dyncclk = REG_FIELD_ID(0x8400, 12, 12, 2, 0x1000),
.rdma_bursten = REG_FIELD_ID(0x8400, 11, 11, 2, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0x8400, 8, 10, 2, 0x1000),
.rdma_intf = REG_FIELD_ID(0x8400, 4, 7, 2, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0x8400, 1, 3, 2, 0x1000),
.rdma_enable = REG_FIELD_ID(0x8400, 0, 0, 2, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 2, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 2, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 2, 0x1000),
.wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 2, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 2, 0x1000),
.wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 2, 0x1000),
.clk_name = (const char*[]) {
"pcnoc-mport-clk",
"pcnoc-sway-clk",
},
.num_clks = 2,
.dai_driver = apq8016_lpass_cpu_dai_driver,
.num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
.dai_osr_clk_names = (const char *[]) {
"mi2s-osr-clk0",
"mi2s-osr-clk1",
"mi2s-osr-clk2",
"mi2s-osr-clk3",
},
.dai_bit_clk_names = (const char *[]) {
"mi2s-bit-clk0",
"mi2s-bit-clk1",
"mi2s-bit-clk2",
"mi2s-bit-clk3",
},
.init = apq8016_lpass_init,
.exit = apq8016_lpass_exit,
.alloc_dma_channel = apq8016_lpass_alloc_dma_channel,
.free_dma_channel = apq8016_lpass_free_dma_channel,
};
static const struct of_device_id apq8016_lpass_cpu_device_id[] __maybe_unused = {
{ .compatible = "qcom,lpass-cpu-apq8016", .data = &apq8016_data },
{ .compatible = "qcom,apq8016-lpass-cpu", .data = &apq8016_data },
{}
};
MODULE_DEVICE_TABLE(of, apq8016_lpass_cpu_device_id);
static struct platform_driver apq8016_lpass_cpu_platform_driver = {
.driver = {
.name = "apq8016-lpass-cpu",
.of_match_table = of_match_ptr(apq8016_lpass_cpu_device_id),
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
};
module_platform_driver(apq8016_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("APQ8016 LPASS CPU Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/lpass-cdc-dma.c
+303
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@@ -0,0 +1,303 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
*
* lpass-cdc-dma.c -- ALSA SoC CDC DMA CPU DAI driver for QTi LPASS
*/
#include <dt-bindings/sound/qcom,lpass.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/export.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
#define CODEC_MEM_HZ_NORMAL 153600000
enum codec_dma_interfaces {
LPASS_CDC_DMA_INTERFACE1 = 1,
LPASS_CDC_DMA_INTERFACE2,
LPASS_CDC_DMA_INTERFACE3,
LPASS_CDC_DMA_INTERFACE4,
LPASS_CDC_DMA_INTERFACE5,
LPASS_CDC_DMA_INTERFACE6,
LPASS_CDC_DMA_INTERFACE7,
LPASS_CDC_DMA_INTERFACE8,
LPASS_CDC_DMA_INTERFACE9,
LPASS_CDC_DMA_INTERFACE10,
};
static void __lpass_get_dmactl_handle(struct snd_pcm_substream *substream, struct snd_soc_dai *dai,
struct lpaif_dmactl **dmactl, int *id)
{
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
const struct lpass_variant *v = drvdata->variant;
unsigned int dai_id = cpu_dai->driver->id;
switch (dai_id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
*dmactl = drvdata->rxtx_rd_dmactl;
*id = pcm_data->dma_ch;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
*dmactl = drvdata->rxtx_wr_dmactl;
*id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
*dmactl = drvdata->va_wr_dmactl;
*id = pcm_data->dma_ch - v->va_wrdma_channel_start;
break;
default:
dev_err(soc_runtime->dev, "invalid dai id for dma ctl: %d\n", dai_id);
break;
}
}
static int __lpass_get_codec_dma_intf_type(int dai_id)
{
int ret;
switch (dai_id) {
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX0:
case LPASS_CDC_DMA_VA_TX0:
ret = LPASS_CDC_DMA_INTERFACE1;
break;
case LPASS_CDC_DMA_RX1:
case LPASS_CDC_DMA_TX1:
case LPASS_CDC_DMA_VA_TX1:
ret = LPASS_CDC_DMA_INTERFACE2;
break;
case LPASS_CDC_DMA_RX2:
case LPASS_CDC_DMA_TX2:
case LPASS_CDC_DMA_VA_TX2:
ret = LPASS_CDC_DMA_INTERFACE3;
break;
case LPASS_CDC_DMA_RX3:
case LPASS_CDC_DMA_TX3:
case LPASS_CDC_DMA_VA_TX3:
ret = LPASS_CDC_DMA_INTERFACE4;
break;
case LPASS_CDC_DMA_RX4:
case LPASS_CDC_DMA_TX4:
case LPASS_CDC_DMA_VA_TX4:
ret = LPASS_CDC_DMA_INTERFACE5;
break;
case LPASS_CDC_DMA_RX5:
case LPASS_CDC_DMA_TX5:
case LPASS_CDC_DMA_VA_TX5:
ret = LPASS_CDC_DMA_INTERFACE6;
break;
case LPASS_CDC_DMA_RX6:
case LPASS_CDC_DMA_TX6:
case LPASS_CDC_DMA_VA_TX6:
ret = LPASS_CDC_DMA_INTERFACE7;
break;
case LPASS_CDC_DMA_RX7:
case LPASS_CDC_DMA_TX7:
case LPASS_CDC_DMA_VA_TX7:
ret = LPASS_CDC_DMA_INTERFACE8;
break;
case LPASS_CDC_DMA_RX8:
case LPASS_CDC_DMA_TX8:
case LPASS_CDC_DMA_VA_TX8:
ret = LPASS_CDC_DMA_INTERFACE9;
break;
case LPASS_CDC_DMA_RX9:
ret = LPASS_CDC_DMA_INTERFACE10;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int __lpass_platform_codec_intf_init(struct snd_soc_dai *dai,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(soc_runtime, 0);
struct lpaif_dmactl *dmactl = NULL;
struct device *dev = soc_runtime->dev;
int ret, id, codec_intf;
unsigned int dai_id = cpu_dai->driver->id;
codec_intf = __lpass_get_codec_dma_intf_type(dai_id);
if (codec_intf < 0) {
dev_err(dev, "failed to get codec_intf: %d\n", codec_intf);
return codec_intf;
}
__lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
if (!dmactl)
return -EINVAL;
ret = regmap_fields_write(dmactl->codec_intf, id, codec_intf);
if (ret) {
dev_err(dev, "error writing to dmactl codec_intf reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_fs_sel, id, 0x0);
if (ret) {
dev_err(dev, "error writing to dmactl codec_fs_sel reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_fs_delay, id, 0x0);
if (ret) {
dev_err(dev, "error writing to dmactl codec_fs_delay reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_pack, id, 0x1);
if (ret) {
dev_err(dev, "error writing to dmactl codec_pack reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_ON);
if (ret) {
dev_err(dev, "error writing to dmactl codec_enable reg field: %d\n", ret);
return ret;
}
return 0;
}
static int lpass_cdc_dma_daiops_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
switch (dai->id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
clk_set_rate(drvdata->codec_mem0, CODEC_MEM_HZ_NORMAL);
clk_prepare_enable(drvdata->codec_mem0);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0:
clk_set_rate(drvdata->va_mem0, CODEC_MEM_HZ_NORMAL);
clk_prepare_enable(drvdata->va_mem0);
break;
default:
dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id);
break;
}
return 0;
}
static void lpass_cdc_dma_daiops_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
switch (dai->id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
clk_disable_unprepare(drvdata->codec_mem0);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0:
clk_disable_unprepare(drvdata->va_mem0);
break;
default:
dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id);
break;
}
}
static int lpass_cdc_dma_daiops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
struct lpaif_dmactl *dmactl = NULL;
unsigned int regval;
unsigned int channels = params_channels(params);
int ret;
int id;
switch (channels) {
case 1:
regval = LPASS_CDC_DMA_INTF_ONE_CHANNEL;
break;
case 2:
regval = LPASS_CDC_DMA_INTF_TWO_CHANNEL;
break;
case 4:
regval = LPASS_CDC_DMA_INTF_FOUR_CHANNEL;
break;
case 6:
regval = LPASS_CDC_DMA_INTF_SIX_CHANNEL;
break;
case 8:
regval = LPASS_CDC_DMA_INTF_EIGHT_CHANNEL;
break;
default:
dev_err(soc_runtime->dev, "invalid PCM config\n");
return -EINVAL;
}
__lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
if (!dmactl)
return -EINVAL;
ret = regmap_fields_write(dmactl->codec_channel, id, regval);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to dmactl codec_channel reg field: %d\n", ret);
return ret;
}
return 0;
}
static int lpass_cdc_dma_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
struct lpaif_dmactl *dmactl = NULL;
int ret = 0, id;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
__lpass_platform_codec_intf_init(dai, substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
__lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
if (!dmactl)
return -EINVAL;
ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_OFF);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to dmactl codec_enable reg: %d\n", ret);
return ret;
}
break;
default:
ret = -EINVAL;
dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, cmd);
break;
}
return ret;
}
const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops = {
.startup = lpass_cdc_dma_daiops_startup,
.shutdown = lpass_cdc_dma_daiops_shutdown,
.hw_params = lpass_cdc_dma_daiops_hw_params,
.trigger = lpass_cdc_dma_daiops_trigger,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cdc_dma_dai_ops);
MODULE_DESCRIPTION("QTi LPASS CDC DMA Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/lpass-cpu.c
+1303
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File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/lpass-hdmi.c
+254
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@@ -0,0 +1,254 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*
* lpass-hdmi.c -- ALSA SoC HDMI-CPU DAI driver for QTi LPASS HDMI
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/sc7180-lpass.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static int lpass_hdmi_daiops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
snd_pcm_format_t format = params_format(params);
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
int bitwidth;
unsigned int word_length;
unsigned int ch_sts_buf0;
unsigned int ch_sts_buf1;
unsigned int data_format;
unsigned int sampling_freq;
unsigned int ch = 0;
struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
int ret;
bitwidth = snd_pcm_format_width(format);
if (bitwidth < 0) {
dev_err(dai->dev, "%s invalid bit width given : %d\n",
__func__, bitwidth);
return bitwidth;
}
switch (bitwidth) {
case 16:
word_length = LPASS_DP_AUDIO_BITWIDTH16;
break;
case 24:
word_length = LPASS_DP_AUDIO_BITWIDTH24;
break;
default:
dev_err(dai->dev, "%s invalid bit width given : %d\n",
__func__, bitwidth);
return -EINVAL;
}
switch (rate) {
case 32000:
sampling_freq = LPASS_SAMPLING_FREQ32;
break;
case 44100:
sampling_freq = LPASS_SAMPLING_FREQ44;
break;
case 48000:
sampling_freq = LPASS_SAMPLING_FREQ48;
break;
default:
dev_err(dai->dev, "%s invalid bit width given : %d\n",
__func__, bitwidth);
return -EINVAL;
}
data_format = LPASS_DATA_FORMAT_LINEAR;
ch_sts_buf0 = (((data_format << LPASS_DATA_FORMAT_SHIFT) & LPASS_DATA_FORMAT_MASK)
| ((sampling_freq << LPASS_FREQ_BIT_SHIFT) & LPASS_FREQ_BIT_MASK));
ch_sts_buf1 = (word_length) & LPASS_WORDLENGTH_MASK;
ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_RESET);
if (ret)
return ret;
ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_CLEAR);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_legacy_en, LPASS_HDMITX_LEGACY_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_parity_calc_en, HDMITX_PARITY_CALC_EN);
if (ret)
return ret;
ret = regmap_field_write(drvdata->vbit_ctl->replace_vbit, REPLACE_VBIT);
if (ret)
return ret;
ret = regmap_field_write(drvdata->vbit_ctl->vbit_stream, LINEAR_PCM_DATA);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_ch_msb[0], ch_sts_buf1);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_ch_lsb[0], ch_sts_buf0);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_chs, HW_MODE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_usr, HW_MODE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->as_sdp_cc, channels - 1);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->as_sdp_ct, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->aif_db4, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->frequency, sampling_freq);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mst_index, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->dptx_index, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dma_sel, ch);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->auto_bbit_en, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->layout, LPASS_SSTREAM_DEFAULT_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->layout_sp, LPASS_LAYOUT_SP_DEFAULT);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_audio, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->set_sp_on_en, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_sp_b_hw_en, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_staffing_en, LPASS_SSTREAM_DEFAULT_ENABLE);
return ret;
}
static int lpass_hdmi_daiops_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int ret;
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
ret = regmap_field_write(drvdata->sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->meta_ctl->mute, LPASS_MUTE_DISABLE);
return ret;
}
static int lpass_hdmi_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
int ret = -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_DISABLE);
if (ret)
return ret;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_audio, 0);
if (ret)
return ret;
break;
}
return ret;
}
const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops = {
.hw_params = lpass_hdmi_daiops_hw_params,
.prepare = lpass_hdmi_daiops_prepare,
.trigger = lpass_hdmi_daiops_trigger,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_hdmi_dai_ops);
MODULE_DESCRIPTION("QTi LPASS HDMI Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/lpass-hdmi.h
+102
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@@ -0,0 +1,102 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*
* lpass_hdmi.h - Definitions for the QTi LPASS HDMI
*/
#ifndef __LPASS_HDMI_H__
#define __LPASS_HDMI_H__
#include <linux/regmap.h>
#define LPASS_HDMITX_LEGACY_DISABLE 0x0
#define LPASS_HDMITX_LEGACY_ENABLE 0x1
#define LPASS_DP_AUDIO_BITWIDTH16 0x0
#define LPASS_DP_AUDIO_BITWIDTH24 0xb
#define LPASS_DATA_FORMAT_SHIFT 0x1
#define LPASS_FREQ_BIT_SHIFT 24
#define LPASS_DATA_FORMAT_LINEAR 0x0
#define LPASS_DATA_FORMAT_NON_LINEAR 0x1
#define LPASS_SAMPLING_FREQ32 0x3
#define LPASS_SAMPLING_FREQ44 0x0
#define LPASS_SAMPLING_FREQ48 0x2
#define LPASS_TX_CTL_RESET 0x1
#define LPASS_TX_CTL_CLEAR 0x0
#define LPASS_SSTREAM_ENABLE 1
#define LPASS_SSTREAM_DISABLE 0
#define LPASS_LAYOUT_SP_DEFAULT 0xf
#define LPASS_SSTREAM_DEFAULT_ENABLE 1
#define LPASS_SSTREAM_DEFAULT_DISABLE 0
#define LPASS_MUTE_ENABLE 1
#define LPASS_MUTE_DISABLE 0
#define LPASS_META_DEFAULT_VAL 0
#define HW_MODE 1
#define SW_MODE 0
#define LEGACY_LPASS_LPAIF 1
#define LEGACY_LPASS_HDMI 0
#define REPLACE_VBIT 0x1
#define LINEAR_PCM_DATA 0x0
#define NON_LINEAR_PCM_DATA 0x1
#define HDMITX_PARITY_CALC_EN 0x1
#define HDMITX_PARITY_CALC_DIS 0x0
#define LPASS_DATA_FORMAT_MASK GENMASK(1, 1)
#define LPASS_WORDLENGTH_MASK GENMASK(3, 0)
#define LPASS_FREQ_BIT_MASK GENMASK(27, 24)
#define LPASS_HDMI_TX_CTL_ADDR(v) (v->hdmi_tx_ctl_addr)
#define LPASS_HDMI_TX_LEGACY_ADDR(v) (v->hdmi_legacy_addr)
#define LPASS_HDMI_TX_VBIT_CTL_ADDR(v) (v->hdmi_vbit_addr)
#define LPASS_HDMI_TX_PARITY_ADDR(v) (v->hdmi_parity_addr)
#define LPASS_HDMI_TX_DP_ADDR(v) (v->hdmi_DP_addr)
#define LPASS_HDMI_TX_SSTREAM_ADDR(v) (v->hdmi_sstream_addr)
#define LPASS_HDMI_TX_CH_LSB_ADDR(v, port) \
(v->hdmi_ch_lsb_addr + v->ch_stride * (port))
#define LPASS_HDMI_TX_CH_MSB_ADDR(v, port) \
(v->hdmi_ch_msb_addr + v->ch_stride * (port))
#define LPASS_HDMI_TX_DMA_ADDR(v, port) \
(v->hdmi_dmactl_addr + v->hdmi_dma_stride * (port))
struct lpass_sstream_ctl {
struct regmap_field *sstream_en;
struct regmap_field *dma_sel;
struct regmap_field *auto_bbit_en;
struct regmap_field *layout;
struct regmap_field *layout_sp;
struct regmap_field *set_sp_on_en;
struct regmap_field *dp_audio;
struct regmap_field *dp_staffing_en;
struct regmap_field *dp_sp_b_hw_en;
};
struct lpass_dp_metadata_ctl {
struct regmap_field *mute;
struct regmap_field *as_sdp_cc;
struct regmap_field *as_sdp_ct;
struct regmap_field *aif_db4;
struct regmap_field *frequency;
struct regmap_field *mst_index;
struct regmap_field *dptx_index;
};
struct lpass_hdmi_tx_ctl {
struct regmap_field *soft_reset;
struct regmap_field *force_reset;
};
struct lpass_hdmitx_dmactl {
struct regmap_field *use_hw_chs;
struct regmap_field *use_hw_usr;
struct regmap_field *hw_chs_sel;
struct regmap_field *hw_usr_sel;
};
struct lpass_vbit_ctrl {
struct regmap_field *replace_vbit;
struct regmap_field *vbit_stream;
};
extern const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops;
#endif /* __LPASS_HDMI_H__ */
linux-7.2.3/sound/soc/qcom/lpass-ipq806x.c
+180
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* lpass-ipq806x.c -- ALSA SoC CPU DAI driver for QTi LPASS
* Splited out the IPQ8064 soc specific from lpass-cpu.c
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
enum lpaif_i2s_ports {
IPQ806X_LPAIF_I2S_PORT_CODEC_SPK,
IPQ806X_LPAIF_I2S_PORT_CODEC_MIC,
IPQ806X_LPAIF_I2S_PORT_SEC_SPK,
IPQ806X_LPAIF_I2S_PORT_SEC_MIC,
IPQ806X_LPAIF_I2S_PORT_MI2S,
};
enum lpaif_dma_channels {
IPQ806X_LPAIF_RDMA_CHAN_MI2S,
IPQ806X_LPAIF_RDMA_CHAN_PCM0,
IPQ806X_LPAIF_RDMA_CHAN_PCM1,
};
static struct snd_soc_dai_driver ipq806x_lpass_cpu_dai_driver = {
.id = IPQ806X_LPAIF_I2S_PORT_MI2S,
.playback = {
.stream_name = "lpass-cpu-playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
};
static int ipq806x_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
int ret;
drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
if (IS_ERR(drvdata->ahbix_clk)) {
dev_err(dev, "error getting ahbix-clk: %ld\n",
PTR_ERR(drvdata->ahbix_clk));
ret = PTR_ERR(drvdata->ahbix_clk);
goto err_ahbix_clk;
}
ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
if (ret) {
dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
dev_dbg(dev, "set ahbix_clk rate to %lu\n",
clk_get_rate(drvdata->ahbix_clk));
ret = clk_prepare_enable(drvdata->ahbix_clk);
if (ret) {
dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
err_ahbix_clk:
return ret;
}
static int ipq806x_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_disable_unprepare(drvdata->ahbix_clk);
return 0;
}
static int ipq806x_lpass_alloc_dma_channel(struct lpass_data *drvdata, int dir, unsigned int dai_id)
{
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
return IPQ806X_LPAIF_RDMA_CHAN_MI2S;
else /* Capture currently not implemented */
return -EINVAL;
}
static int ipq806x_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
return 0;
}
static const struct lpass_variant ipq806x_data = {
.i2sctrl_reg_base = 0x0010,
.i2sctrl_reg_stride = 0x04,
.i2s_ports = 5,
.irq_reg_base = 0x3000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0x6000,
.rdma_reg_stride = 0x1000,
.rdma_channels = 4,
.wrdma_reg_base = 0xB000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 4,
.loopback = REG_FIELD_ID(0x0010, 15, 15, 5, 0x4),
.spken = REG_FIELD_ID(0x0010, 14, 14, 5, 0x4),
.spkmode = REG_FIELD_ID(0x0010, 10, 13, 5, 0x4),
.spkmono = REG_FIELD_ID(0x0010, 9, 9, 5, 0x4),
.micen = REG_FIELD_ID(0x0010, 8, 8, 5, 0x4),
.micmode = REG_FIELD_ID(0x0010, 4, 7, 5, 0x4),
.micmono = REG_FIELD_ID(0x0010, 3, 3, 5, 0x4),
.wssrc = REG_FIELD_ID(0x0010, 2, 2, 5, 0x4),
.bitwidth = REG_FIELD_ID(0x0010, 0, 1, 5, 0x4),
.rdma_dyncclk = REG_FIELD_ID(0x6000, 12, 12, 4, 0x1000),
.rdma_bursten = REG_FIELD_ID(0x6000, 11, 11, 4, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0x6000, 8, 10, 4, 0x1000),
.rdma_intf = REG_FIELD_ID(0x6000, 4, 7, 4, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0x6000, 1, 3, 4, 0x1000),
.rdma_enable = REG_FIELD_ID(0x6000, 0, 0, 4, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 4, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 4, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 4, 0x1000),
.wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 4, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 4, 0x1000),
.wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 4, 0x1000),
.dai_driver = &ipq806x_lpass_cpu_dai_driver,
.num_dai = 1,
.dai_osr_clk_names = (const char *[]) {
"mi2s-osr-clk",
},
.dai_bit_clk_names = (const char *[]) {
"mi2s-bit-clk",
},
.init = ipq806x_lpass_init,
.exit = ipq806x_lpass_exit,
.alloc_dma_channel = ipq806x_lpass_alloc_dma_channel,
.free_dma_channel = ipq806x_lpass_free_dma_channel,
};
static const struct of_device_id ipq806x_lpass_cpu_device_id[] __maybe_unused = {
{ .compatible = "qcom,lpass-cpu", .data = &ipq806x_data },
{}
};
MODULE_DEVICE_TABLE(of, ipq806x_lpass_cpu_device_id);
static struct platform_driver ipq806x_lpass_cpu_platform_driver = {
.driver = {
.name = "lpass-cpu",
.of_match_table = of_match_ptr(ipq806x_lpass_cpu_device_id),
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
};
module_platform_driver(ipq806x_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("QTi LPASS CPU Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/lpass-lpaif-reg.h
+319
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*/
#ifndef __LPASS_LPAIF_REG_H__
#define __LPASS_LPAIF_REG_H__
/* LPAIF I2S */
#define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
#define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
#define LPAIF_I2SCTL_LOOPBACK_DISABLE 0
#define LPAIF_I2SCTL_LOOPBACK_ENABLE 1
#define LPAIF_I2SCTL_SPKEN_DISABLE 0
#define LPAIF_I2SCTL_SPKEN_ENABLE 1
#define LPAIF_I2SCTL_MODE_NONE 0
#define LPAIF_I2SCTL_MODE_SD0 1
#define LPAIF_I2SCTL_MODE_SD1 2
#define LPAIF_I2SCTL_MODE_SD2 3
#define LPAIF_I2SCTL_MODE_SD3 4
#define LPAIF_I2SCTL_MODE_QUAD01 5
#define LPAIF_I2SCTL_MODE_QUAD23 6
#define LPAIF_I2SCTL_MODE_6CH 7
#define LPAIF_I2SCTL_MODE_8CH 8
#define LPAIF_I2SCTL_MODE_10CH 9
#define LPAIF_I2SCTL_MODE_12CH 10
#define LPAIF_I2SCTL_MODE_14CH 11
#define LPAIF_I2SCTL_MODE_16CH 12
#define LPAIF_I2SCTL_MODE_SD4 13
#define LPAIF_I2SCTL_MODE_SD5 14
#define LPAIF_I2SCTL_MODE_SD6 15
#define LPAIF_I2SCTL_MODE_SD7 16
#define LPAIF_I2SCTL_MODE_QUAD45 17
#define LPAIF_I2SCTL_MODE_QUAD47 18
#define LPAIF_I2SCTL_MODE_8CH_2 19
#define LPAIF_I2SCTL_SPKMODE(mode) mode
#define LPAIF_I2SCTL_SPKMONO_STEREO 0
#define LPAIF_I2SCTL_SPKMONO_MONO 1
#define LPAIF_I2SCTL_MICEN_DISABLE 0
#define LPAIF_I2SCTL_MICEN_ENABLE 1
#define LPAIF_I2SCTL_MICMODE(mode) mode
#define LPAIF_I2SCTL_MICMONO_STEREO 0
#define LPAIF_I2SCTL_MICMONO_MONO 1
#define LPAIF_I2SCTL_WSSRC_INTERNAL 0
#define LPAIF_I2SCTL_WSSRC_EXTERNAL 1
#define LPAIF_I2SCTL_BITWIDTH_16 0
#define LPAIF_I2SCTL_BITWIDTH_24 1
#define LPAIF_I2SCTL_BITWIDTH_32 2
#define LPAIF_I2SCTL_RESET_STATE 0x003C0004
#define LPAIF_DMACTL_RESET_STATE 0x00200000
/* LPAIF IRQ */
#define LPAIF_IRQ_REG_ADDR(v, addr, port) \
(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
#define LPAIF_IRQ_PORT_HOST 0
#define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
#define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
#define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
/* LPAIF RXTX IRQ */
#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
/* LPAIF VA IRQ */
#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
((v->hdmi_irq_reg_base) + (addr))
#define LPASS_HDMITX_APP_IRQEN_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
#define LPASS_HDMITX_APP_IRQSTAT_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
#define LPASS_HDMITX_APP_IRQCLEAR_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
#define LPAIF_IRQ_BITSTRIDE 3
#define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan))
#define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) (1 << (24 + chan))
#define LPAIF_IRQ_HDMI_METADONE BIT(23)
/* LPAIF DMA */
#define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
#define LPAIF_HDMI_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
#define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
#define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
#define LPAIF_HDMI_RDMABUFF_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
#define LPAIF_HDMI_RDMACURR_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
#define LPAIF_HDMI_RDMAPER_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
#define LPAIF_HDMI_RDMAPERCNT_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
#define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
#define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
#define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
#define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
#define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
#define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
#define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
#define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
#define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
(v->wrdma_reg_base + (addr) + \
v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
#define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
#define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
#define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
#define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
#define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
#define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
#define LPAIF_INTFDMA_REG(v, chan, reg, dai_id) \
((dai_id == LPASS_DP_RX) ? \
LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
LPAIF_RDMA##reg##_REG(v, chan))
#define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id) \
((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
LPAIF_WRDMA##reg##_REG(v, chan))
#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
(is_rxtx_cdc_dma_port(dai_id) ? \
(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
(is_rxtx_cdc_dma_port(dai_id) ? \
(v->rxtx_wrdma_reg_base + (addr) + \
v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
(v->va_wrdma_reg_base + (addr) + \
v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
(is_cdc_dma_port(dai_id) ? \
LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
LPAIF_DMACTL_REG(v, chan, dir, dai_id))
#define LPAIF_DMACTL_BURSTEN_SINGLE 0
#define LPAIF_DMACTL_BURSTEN_INCR4 1
#define LPAIF_DMACTL_WPSCNT_ONE 0
#define LPAIF_DMACTL_WPSCNT_TWO 1
#define LPAIF_DMACTL_WPSCNT_THREE 2
#define LPAIF_DMACTL_WPSCNT_FOUR 3
#define LPAIF_DMACTL_WPSCNT_SIX 5
#define LPAIF_DMACTL_WPSCNT_EIGHT 7
#define LPAIF_DMACTL_WPSCNT_TEN 9
#define LPAIF_DMACTL_WPSCNT_TWELVE 11
#define LPAIF_DMACTL_WPSCNT_FOURTEEN 13
#define LPAIF_DMACTL_WPSCNT_SIXTEEN 15
#define LPAIF_DMACTL_AUDINTF(id) id
#define LPAIF_DMACTL_FIFOWM_1 0
#define LPAIF_DMACTL_FIFOWM_2 1
#define LPAIF_DMACTL_FIFOWM_3 2
#define LPAIF_DMACTL_FIFOWM_4 3
#define LPAIF_DMACTL_FIFOWM_5 4
#define LPAIF_DMACTL_FIFOWM_6 5
#define LPAIF_DMACTL_FIFOWM_7 6
#define LPAIF_DMACTL_FIFOWM_8 7
#define LPAIF_DMACTL_FIFOWM_9 8
#define LPAIF_DMACTL_FIFOWM_10 9
#define LPAIF_DMACTL_FIFOWM_11 10
#define LPAIF_DMACTL_FIFOWM_12 11
#define LPAIF_DMACTL_FIFOWM_13 12
#define LPAIF_DMACTL_FIFOWM_14 13
#define LPAIF_DMACTL_FIFOWM_15 14
#define LPAIF_DMACTL_FIFOWM_16 15
#define LPAIF_DMACTL_FIFOWM_17 16
#define LPAIF_DMACTL_FIFOWM_18 17
#define LPAIF_DMACTL_FIFOWM_19 18
#define LPAIF_DMACTL_FIFOWM_20 19
#define LPAIF_DMACTL_FIFOWM_21 20
#define LPAIF_DMACTL_FIFOWM_22 21
#define LPAIF_DMACTL_FIFOWM_23 22
#define LPAIF_DMACTL_FIFOWM_24 23
#define LPAIF_DMACTL_FIFOWM_25 24
#define LPAIF_DMACTL_FIFOWM_26 25
#define LPAIF_DMACTL_FIFOWM_27 26
#define LPAIF_DMACTL_FIFOWM_28 27
#define LPAIF_DMACTL_FIFOWM_29 28
#define LPAIF_DMACTL_FIFOWM_30 29
#define LPAIF_DMACTL_FIFOWM_31 30
#define LPAIF_DMACTL_FIFOWM_32 31
#define LPAIF_DMACTL_ENABLE_OFF 0
#define LPAIF_DMACTL_ENABLE_ON 1
#define LPAIF_DMACTL_DYNCLK_OFF 0
#define LPAIF_DMACTL_DYNCLK_ON 1
#endif /* __LPASS_LPAIF_REG_H__ */
linux-7.2.3/sound/soc/qcom/lpass-platform.c
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linux-7.2.3/sound/soc/qcom/lpass-sc7180.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <dt-bindings/sound/sc7180-lpass.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
{
.id = MI2S_PRIMARY,
.name = "Primary MI2S",
.playback = {
.stream_name = "Primary Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.stream_name = "Primary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
}, {
.id = MI2S_SECONDARY,
.name = "Secondary MI2S",
.playback = {
.stream_name = "Secondary Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops2,
}, {
.id = LPASS_DP_RX,
.name = "Hdmi",
.playback = {
.stream_name = "Hdmi Playback",
.formats = SNDRV_PCM_FMTBIT_S24,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_hdmi_dai_ops,
},
};
static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata,
int direction, unsigned int dai_id)
{
const struct lpass_variant *v = drvdata->variant;
int chan = 0;
if (dai_id == LPASS_DP_RX) {
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
v->hdmi_rdma_channels);
if (chan >= v->hdmi_rdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
} else {
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
v->rdma_channels);
if (chan >= v->rdma_channels)
return -EBUSY;
} else {
chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
v->wrdma_channel_start +
v->wrdma_channels,
v->wrdma_channel_start);
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->dma_ch_bit_map);
}
return chan;
}
static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
if (dai_id == LPASS_DP_RX)
clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
else
clear_bit(chan, &drvdata->dma_ch_bit_map);
return 0;
}
static int sc7180_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
const struct lpass_variant *variant = drvdata->variant;
struct device *dev = &pdev->dev;
int ret, i;
drvdata->clks = devm_kcalloc(dev, variant->num_clks,
sizeof(*drvdata->clks), GFP_KERNEL);
if (!drvdata->clks)
return -ENOMEM;
drvdata->num_clks = variant->num_clks;
for (i = 0; i < drvdata->num_clks; i++)
drvdata->clks[i].id = variant->clk_name[i];
ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "Failed to get clocks %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "sc7180 clk_enable failed\n");
return ret;
}
return 0;
}
static int sc7180_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static int sc7180_lpass_dev_resume(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
return clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
}
static int sc7180_lpass_dev_suspend(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static const struct dev_pm_ops sc7180_lpass_pm_ops = {
SYSTEM_SLEEP_PM_OPS(sc7180_lpass_dev_suspend, sc7180_lpass_dev_resume)
};
static const struct lpass_variant sc7180_data = {
.i2sctrl_reg_base = 0x1000,
.i2sctrl_reg_stride = 0x1000,
.i2s_ports = 3,
.irq_reg_base = 0x9000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0xC000,
.rdma_reg_stride = 0x1000,
.rdma_channels = 5,
.hdmi_rdma_reg_base = 0x64000,
.hdmi_rdma_reg_stride = 0x1000,
.hdmi_rdma_channels = 4,
.dmactl_audif_start = 1,
.wrdma_reg_base = 0x18000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 4,
.loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
.spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
.spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
.spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
.micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
.micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
.micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
.wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
.bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
.rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
.rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
.rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
.rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
.wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
.wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
.hdmi_tx_ctl_addr = 0x1000,
.hdmi_legacy_addr = 0x1008,
.hdmi_vbit_addr = 0x610c0,
.hdmi_ch_lsb_addr = 0x61048,
.hdmi_ch_msb_addr = 0x6104c,
.ch_stride = 0x8,
.hdmi_parity_addr = 0x61034,
.hdmi_dmactl_addr = 0x61038,
.hdmi_dma_stride = 0x4,
.hdmi_DP_addr = 0x610c8,
.hdmi_sstream_addr = 0x6101c,
.hdmi_irq_reg_base = 0x63000,
.hdmi_irq_ports = 1,
.hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
.hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
.hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
.hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
.hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
.hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
.hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
.hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
.sstream_en = REG_FIELD(0x6101c, 0, 0),
.dma_sel = REG_FIELD(0x6101c, 1, 2),
.auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
.layout = REG_FIELD(0x6101c, 4, 4),
.layout_sp = REG_FIELD(0x6101c, 5, 8),
.set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
.dp_audio = REG_FIELD(0x6101c, 11, 11),
.dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
.dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
.mute = REG_FIELD(0x610c8, 0, 0),
.as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
.as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
.aif_db4 = REG_FIELD(0x610c8, 8, 15),
.frequency = REG_FIELD(0x610c8, 16, 21),
.mst_index = REG_FIELD(0x610c8, 28, 29),
.dptx_index = REG_FIELD(0x610c8, 30, 31),
.soft_reset = REG_FIELD(0x1000, 31, 31),
.force_reset = REG_FIELD(0x1000, 30, 30),
.use_hw_chs = REG_FIELD(0x61038, 0, 0),
.use_hw_usr = REG_FIELD(0x61038, 1, 1),
.hw_chs_sel = REG_FIELD(0x61038, 2, 4),
.hw_usr_sel = REG_FIELD(0x61038, 5, 6),
.replace_vbit = REG_FIELD(0x610c0, 0, 0),
.vbit_stream = REG_FIELD(0x610c0, 1, 1),
.legacy_en = REG_FIELD(0x1008, 0, 0),
.calc_en = REG_FIELD(0x61034, 0, 0),
.lsb_bits = REG_FIELD(0x61048, 0, 31),
.msb_bits = REG_FIELD(0x6104c, 0, 31),
.clk_name = (const char*[]) {
"pcnoc-sway-clk",
"audio-core",
"pcnoc-mport-clk",
},
.num_clks = 3,
.dai_driver = sc7180_lpass_cpu_dai_driver,
.num_dai = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver),
.dai_osr_clk_names = (const char *[]) {
"mclk0",
"null",
},
.dai_bit_clk_names = (const char *[]) {
"mi2s-bit-clk0",
"mi2s-bit-clk1",
},
.init = sc7180_lpass_init,
.exit = sc7180_lpass_exit,
.alloc_dma_channel = sc7180_lpass_alloc_dma_channel,
.free_dma_channel = sc7180_lpass_free_dma_channel,
};
static const struct of_device_id sc7180_lpass_cpu_device_id[] __maybe_unused = {
{.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data},
{}
};
MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id);
static struct platform_driver sc7180_lpass_cpu_platform_driver = {
.driver = {
.name = "sc7180-lpass-cpu",
.of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id),
.pm = pm_ptr(&sc7180_lpass_pm_ops),
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
.shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
};
module_platform_driver(sc7180_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/lpass-sc7280.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*
* lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
*/
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <linux/pm.h>
#include <dt-bindings/sound/sc7180-lpass.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static struct snd_soc_dai_driver sc7280_lpass_cpu_dai_driver[] = {
{
.id = MI2S_PRIMARY,
.name = "Primary MI2S",
.playback = {
.stream_name = "Primary Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.stream_name = "Primary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
}, {
.id = MI2S_SECONDARY,
.name = "Secondary MI2S",
.playback = {
.stream_name = "Secondary MI2S Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
}, {
.id = LPASS_DP_RX,
.name = "Hdmi",
.playback = {
.stream_name = "DP Playback",
.formats = SNDRV_PCM_FMTBIT_S24,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_hdmi_dai_ops,
}, {
.id = LPASS_CDC_DMA_RX0,
.name = "CDC DMA RX",
.playback = {
.stream_name = "WCD Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
}, {
.id = LPASS_CDC_DMA_TX3,
.name = "CDC DMA TX",
.capture = {
.stream_name = "WCD Capture",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 1,
.channels_max = 1,
},
.ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
}, {
.id = LPASS_CDC_DMA_VA_TX0,
.name = "CDC DMA VA",
.capture = {
.stream_name = "DMIC Capture",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 4,
},
.ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
},
};
static int sc7280_lpass_alloc_dma_channel(struct lpass_data *drvdata,
int direction, unsigned int dai_id)
{
const struct lpass_variant *v = drvdata->variant;
int chan = 0;
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
v->rdma_channels);
if (chan >= v->rdma_channels)
return -EBUSY;
} else {
chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
v->wrdma_channel_start +
v->wrdma_channels,
v->wrdma_channel_start);
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->dma_ch_bit_map);
break;
case LPASS_DP_RX:
chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
v->hdmi_rdma_channels);
if (chan >= v->hdmi_rdma_channels)
return -EBUSY;
set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
chan = find_first_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
v->rxtx_rdma_channels);
if (chan >= v->rxtx_rdma_channels)
return -EBUSY;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
chan = find_next_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
v->rxtx_wrdma_channel_start +
v->rxtx_wrdma_channels,
v->rxtx_wrdma_channel_start);
if (chan >= v->rxtx_wrdma_channel_start + v->rxtx_wrdma_channels)
return -EBUSY;
set_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
chan = find_next_zero_bit(&drvdata->va_dma_ch_bit_map,
v->va_wrdma_channel_start +
v->va_wrdma_channels,
v->va_wrdma_channel_start);
if (chan >= v->va_wrdma_channel_start + v->va_wrdma_channels)
return -EBUSY;
set_bit(chan, &drvdata->va_dma_ch_bit_map);
break;
default:
break;
}
return chan;
}
static int sc7280_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
clear_bit(chan, &drvdata->dma_ch_bit_map);
break;
case LPASS_DP_RX:
clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
clear_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
clear_bit(chan, &drvdata->va_dma_ch_bit_map);
break;
default:
break;
}
return 0;
}
static int sc7280_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
const struct lpass_variant *variant = drvdata->variant;
struct device *dev = &pdev->dev;
int ret, i;
drvdata->clks = devm_kcalloc(dev, variant->num_clks,
sizeof(*drvdata->clks), GFP_KERNEL);
if (!drvdata->clks)
return -ENOMEM;
drvdata->num_clks = variant->num_clks;
for (i = 0; i < drvdata->num_clks; i++)
drvdata->clks[i].id = variant->clk_name[i];
ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "Failed to get clocks %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "sc7280 clk_enable failed\n");
return ret;
}
return 0;
}
static int sc7280_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static int sc7280_lpass_dev_resume(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
return clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
}
static int sc7280_lpass_dev_suspend(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static const struct dev_pm_ops sc7280_lpass_pm_ops = {
SYSTEM_SLEEP_PM_OPS(sc7280_lpass_dev_suspend, sc7280_lpass_dev_resume)
};
static const struct lpass_variant sc7280_data = {
.i2sctrl_reg_base = 0x1000,
.i2sctrl_reg_stride = 0x1000,
.i2s_ports = 3,
.irq_reg_base = 0x9000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0xC000,
.rdma_reg_stride = 0x1000,
.rdma_channels = 5,
.rxtx_rdma_reg_base = 0xC000,
.rxtx_rdma_reg_stride = 0x1000,
.rxtx_rdma_channels = 8,
.hdmi_rdma_reg_base = 0x64000,
.hdmi_rdma_reg_stride = 0x1000,
.hdmi_rdma_channels = 4,
.dmactl_audif_start = 1,
.wrdma_reg_base = 0x18000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 4,
.rxtx_irq_reg_base = 0x9000,
.rxtx_irq_reg_stride = 0x1000,
.rxtx_irq_ports = 3,
.rxtx_wrdma_reg_base = 0x18000,
.rxtx_wrdma_reg_stride = 0x1000,
.rxtx_wrdma_channel_start = 5,
.rxtx_wrdma_channels = 6,
.va_wrdma_reg_base = 0x18000,
.va_wrdma_reg_stride = 0x1000,
.va_wrdma_channel_start = 5,
.va_wrdma_channels = 3,
.va_irq_reg_base = 0x9000,
.va_irq_reg_stride = 0x1000,
.va_irq_ports = 3,
.loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
.spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
.spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
.spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
.micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
.micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
.micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
.wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
.bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
.rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
.rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
.rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
.rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
.wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
.wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
.rxtx_rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 7, 0x1000),
.rxtx_rdma_fifowm = REG_FIELD_ID(0xC000, 1, 11, 7, 0x1000),
.rxtx_rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 7, 0x1000),
.rxtx_rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 7, 0x1000),
.rxtx_rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 7, 0x1000),
.rxtx_rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 7, 0x1000),
.rxtx_rdma_codec_ch = REG_FIELD_ID(0xC050, 0, 7, 7, 0x1000),
.rxtx_rdma_codec_intf = REG_FIELD_ID(0xC050, 16, 19, 7, 0x1000),
.rxtx_rdma_codec_fs_delay = REG_FIELD_ID(0xC050, 21, 24, 7, 0x1000),
.rxtx_rdma_codec_fs_sel = REG_FIELD_ID(0xC050, 25, 27, 7, 0x1000),
.rxtx_rdma_codec_pack = REG_FIELD_ID(0xC050, 29, 29, 5, 0x1000),
.rxtx_rdma_codec_enable = REG_FIELD_ID(0xC050, 30, 30, 7, 0x1000),
.rxtx_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
.rxtx_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
.rxtx_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
.rxtx_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
.rxtx_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
.rxtx_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
.rxtx_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
.rxtx_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
.rxtx_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
.rxtx_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
.rxtx_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
.rxtx_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
.va_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
.va_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
.va_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
.va_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
.va_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
.va_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
.va_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
.va_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
.va_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
.va_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
.va_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
.va_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
.hdmi_tx_ctl_addr = 0x1000,
.hdmi_legacy_addr = 0x1008,
.hdmi_vbit_addr = 0x610c0,
.hdmi_ch_lsb_addr = 0x61048,
.hdmi_ch_msb_addr = 0x6104c,
.ch_stride = 0x8,
.hdmi_parity_addr = 0x61034,
.hdmi_dmactl_addr = 0x61038,
.hdmi_dma_stride = 0x4,
.hdmi_DP_addr = 0x610c8,
.hdmi_sstream_addr = 0x6101c,
.hdmi_irq_reg_base = 0x63000,
.hdmi_irq_ports = 1,
.hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
.hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
.hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
.hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
.hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
.hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
.hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
.hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
.sstream_en = REG_FIELD(0x6101c, 0, 0),
.dma_sel = REG_FIELD(0x6101c, 1, 2),
.auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
.layout = REG_FIELD(0x6101c, 4, 4),
.layout_sp = REG_FIELD(0x6101c, 5, 8),
.set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
.dp_audio = REG_FIELD(0x6101c, 11, 11),
.dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
.dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
.mute = REG_FIELD(0x610c8, 0, 0),
.as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
.as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
.aif_db4 = REG_FIELD(0x610c8, 8, 15),
.frequency = REG_FIELD(0x610c8, 16, 21),
.mst_index = REG_FIELD(0x610c8, 28, 29),
.dptx_index = REG_FIELD(0x610c8, 30, 31),
.soft_reset = REG_FIELD(0x1000, 31, 31),
.force_reset = REG_FIELD(0x1000, 30, 30),
.use_hw_chs = REG_FIELD(0x61038, 0, 0),
.use_hw_usr = REG_FIELD(0x61038, 1, 1),
.hw_chs_sel = REG_FIELD(0x61038, 2, 4),
.hw_usr_sel = REG_FIELD(0x61038, 5, 6),
.replace_vbit = REG_FIELD(0x610c0, 0, 0),
.vbit_stream = REG_FIELD(0x610c0, 1, 1),
.legacy_en = REG_FIELD(0x1008, 0, 0),
.calc_en = REG_FIELD(0x61034, 0, 0),
.lsb_bits = REG_FIELD(0x61048, 0, 31),
.msb_bits = REG_FIELD(0x6104c, 0, 31),
.clk_name = (const char*[]) {
"core_cc_sysnoc_mport_core"
},
.num_clks = 1,
.dai_driver = sc7280_lpass_cpu_dai_driver,
.num_dai = ARRAY_SIZE(sc7280_lpass_cpu_dai_driver),
.dai_osr_clk_names = (const char *[]) {
"audio_cc_ext_mclk0",
"null"
},
.dai_bit_clk_names = (const char *[]) {
"core_cc_ext_if0_ibit",
"core_cc_ext_if1_ibit"
},
.init = sc7280_lpass_init,
.exit = sc7280_lpass_exit,
.alloc_dma_channel = sc7280_lpass_alloc_dma_channel,
.free_dma_channel = sc7280_lpass_free_dma_channel,
};
static const struct of_device_id sc7280_lpass_cpu_device_id[] = {
{.compatible = "qcom,sc7280-lpass-cpu", .data = &sc7280_data},
{}
};
MODULE_DEVICE_TABLE(of, sc7280_lpass_cpu_device_id);
static struct platform_driver sc7280_lpass_cpu_platform_driver = {
.driver = {
.name = "sc7280-lpass-cpu",
.of_match_table = of_match_ptr(sc7280_lpass_cpu_device_id),
.pm = pm_ptr(&sc7280_lpass_pm_ops),
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
.shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
};
module_platform_driver(sc7280_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("SC7280 LPASS CPU DRIVER");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/lpass.h
+411
View File
@@ -0,0 +1,411 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
*
* lpass.h - Definitions for the QTi LPASS
*/
#ifndef __LPASS_H__
#define __LPASS_H__
#include <linux/clk.h>
#include <linux/compiler.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "common.h"
#include "lpass-hdmi.h"
#define LPASS_AHBIX_CLOCK_FREQUENCY 131072000
#define LPASS_MAX_PORTS (LPASS_MAX_PORT)
#define LPASS_MAX_MI2S_PORTS (8)
#define LPASS_MAX_DMA_CHANNELS (8)
#define LPASS_MAX_HDMI_DMA_CHANNELS (4)
#define LPASS_MAX_CDC_DMA_CHANNELS (8)
#define LPASS_MAX_VA_CDC_DMA_CHANNELS (8)
#define LPASS_CDC_DMA_INTF_ONE_CHANNEL (0x01)
#define LPASS_CDC_DMA_INTF_TWO_CHANNEL (0x03)
#define LPASS_CDC_DMA_INTF_FOUR_CHANNEL (0x0F)
#define LPASS_CDC_DMA_INTF_SIX_CHANNEL (0x3F)
#define LPASS_CDC_DMA_INTF_EIGHT_CHANNEL (0xFF)
#define LPASS_ACTIVE_PDS (4)
#define LPASS_PROXY_PDS (8)
#define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf) \
do { \
mf = devm_regmap_field_alloc(d, m, f); \
if (IS_ERR(mf)) \
return -EINVAL; \
} while (0)
static inline bool is_cdc_dma_port(int dai_id)
{
switch (dai_id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
return true;
}
return false;
}
static inline bool is_rxtx_cdc_dma_port(int dai_id)
{
switch (dai_id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
return true;
}
return false;
}
struct lpaif_i2sctl {
struct regmap_field *loopback;
struct regmap_field *spken;
struct regmap_field *spkmode;
struct regmap_field *spkmono;
struct regmap_field *micen;
struct regmap_field *micmode;
struct regmap_field *micmono;
struct regmap_field *wssrc;
struct regmap_field *bitwidth;
};
struct lpaif_dmactl {
struct regmap_field *intf;
struct regmap_field *bursten;
struct regmap_field *wpscnt;
struct regmap_field *fifowm;
struct regmap_field *enable;
struct regmap_field *dyncclk;
struct regmap_field *burst8;
struct regmap_field *burst16;
struct regmap_field *dynburst;
struct regmap_field *codec_enable;
struct regmap_field *codec_pack;
struct regmap_field *codec_intf;
struct regmap_field *codec_fs_sel;
struct regmap_field *codec_channel;
struct regmap_field *codec_fs_delay;
};
/* Both the CPU DAI and platform drivers will access this data */
struct lpass_data {
/* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
struct clk *ahbix_clk;
/* MI2S system clock */
struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
/* MI2S bit clock (derived from system clock by a divider */
struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
struct clk *codec_mem0;
struct clk *codec_mem1;
struct clk *codec_mem2;
struct clk *va_mem0;
/* MI2S SD lines to use for playback/capture */
unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
/* The state of MI2S prepare dai_ops was called */
bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS];
int hdmi_port_enable;
int codec_dma_enable;
/* low-power audio interface (LPAIF) registers */
void __iomem *lpaif;
void __iomem *hdmiif;
void __iomem *rxtx_lpaif;
void __iomem *va_lpaif;
u32 rxtx_cdc_dma_lpm_buf;
u32 va_cdc_dma_lpm_buf;
/* regmap backed by the low-power audio interface (LPAIF) registers */
struct regmap *lpaif_map;
struct regmap *hdmiif_map;
struct regmap *rxtx_lpaif_map;
struct regmap *va_lpaif_map;
/* interrupts from the low-power audio interface (LPAIF) */
int lpaif_irq;
int hdmiif_irq;
int rxtxif_irq;
int vaif_irq;
/* SOC specific variations in the LPASS IP integration */
const struct lpass_variant *variant;
/* bit map to keep track of static channel allocations */
unsigned long dma_ch_bit_map;
unsigned long hdmi_dma_ch_bit_map;
unsigned long rxtx_dma_ch_bit_map;
unsigned long va_dma_ch_bit_map;
/* used it for handling interrupt per dma channel */
struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
struct snd_pcm_substream *rxtx_substream[LPASS_MAX_CDC_DMA_CHANNELS];
struct snd_pcm_substream *va_substream[LPASS_MAX_CDC_DMA_CHANNELS];
/* SOC specific clock list */
struct clk_bulk_data *clks;
int num_clks;
/* Regmap fields of I2SCTL & DMACTL registers bitfields */
struct lpaif_i2sctl *i2sctl;
struct lpaif_dmactl *rd_dmactl;
struct lpaif_dmactl *wr_dmactl;
struct lpaif_dmactl *hdmi_rd_dmactl;
/* Regmap fields of CODEC DMA CTRL registers */
struct lpaif_dmactl *rxtx_rd_dmactl;
struct lpaif_dmactl *rxtx_wr_dmactl;
struct lpaif_dmactl *va_wr_dmactl;
/* Regmap fields of HDMI_CTRL registers*/
struct regmap_field *hdmitx_legacy_en;
struct regmap_field *hdmitx_parity_calc_en;
struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
struct lpass_hdmi_tx_ctl *tx_ctl;
struct lpass_vbit_ctrl *vbit_ctl;
struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
struct lpass_dp_metadata_ctl *meta_ctl;
struct lpass_sstream_ctl *sstream_ctl;
};
/* Vairant data per each SOC */
struct lpass_variant {
u32 irq_reg_base;
u32 irq_reg_stride;
u32 irq_ports;
u32 rdma_reg_base;
u32 rdma_reg_stride;
u32 rdma_channels;
u32 hdmi_rdma_reg_base;
u32 hdmi_rdma_reg_stride;
u32 hdmi_rdma_channels;
u32 wrdma_reg_base;
u32 wrdma_reg_stride;
u32 wrdma_channels;
u32 rxtx_irq_reg_base;
u32 rxtx_irq_reg_stride;
u32 rxtx_irq_ports;
u32 rxtx_rdma_reg_base;
u32 rxtx_rdma_reg_stride;
u32 rxtx_rdma_channels;
u32 rxtx_wrdma_reg_base;
u32 rxtx_wrdma_reg_stride;
u32 rxtx_wrdma_channels;
u32 va_irq_reg_base;
u32 va_irq_reg_stride;
u32 va_irq_ports;
u32 va_rdma_reg_base;
u32 va_rdma_reg_stride;
u32 va_rdma_channels;
u32 va_wrdma_reg_base;
u32 va_wrdma_reg_stride;
u32 va_wrdma_channels;
u32 i2sctrl_reg_base;
u32 i2sctrl_reg_stride;
u32 i2s_ports;
/* I2SCTL Register fields */
struct reg_field loopback;
struct reg_field spken;
struct reg_field spkmode;
struct reg_field spkmono;
struct reg_field micen;
struct reg_field micmode;
struct reg_field micmono;
struct reg_field wssrc;
struct reg_field bitwidth;
u32 hdmi_irq_reg_base;
u32 hdmi_irq_reg_stride;
u32 hdmi_irq_ports;
/* HDMI specific controls */
u32 hdmi_tx_ctl_addr;
u32 hdmi_legacy_addr;
u32 hdmi_vbit_addr;
u32 hdmi_ch_lsb_addr;
u32 hdmi_ch_msb_addr;
u32 ch_stride;
u32 hdmi_parity_addr;
u32 hdmi_dmactl_addr;
u32 hdmi_dma_stride;
u32 hdmi_DP_addr;
u32 hdmi_sstream_addr;
/* HDMI SSTREAM CTRL fields */
struct reg_field sstream_en;
struct reg_field dma_sel;
struct reg_field auto_bbit_en;
struct reg_field layout;
struct reg_field layout_sp;
struct reg_field set_sp_on_en;
struct reg_field dp_audio;
struct reg_field dp_staffing_en;
struct reg_field dp_sp_b_hw_en;
/* HDMI DP METADATA CTL fields */
struct reg_field mute;
struct reg_field as_sdp_cc;
struct reg_field as_sdp_ct;
struct reg_field aif_db4;
struct reg_field frequency;
struct reg_field mst_index;
struct reg_field dptx_index;
/* HDMI TX CTRL fields */
struct reg_field soft_reset;
struct reg_field force_reset;
/* HDMI TX DMA CTRL */
struct reg_field use_hw_chs;
struct reg_field use_hw_usr;
struct reg_field hw_chs_sel;
struct reg_field hw_usr_sel;
/* HDMI VBIT CTRL */
struct reg_field replace_vbit;
struct reg_field vbit_stream;
/* HDMI TX LEGACY */
struct reg_field legacy_en;
/* HDMI TX PARITY */
struct reg_field calc_en;
/* HDMI CH LSB */
struct reg_field lsb_bits;
/* HDMI CH MSB */
struct reg_field msb_bits;
struct reg_field hdmi_rdma_bursten;
struct reg_field hdmi_rdma_wpscnt;
struct reg_field hdmi_rdma_fifowm;
struct reg_field hdmi_rdma_enable;
struct reg_field hdmi_rdma_dyncclk;
struct reg_field hdmi_rdma_burst8;
struct reg_field hdmi_rdma_burst16;
struct reg_field hdmi_rdma_dynburst;
/* RD_DMA Register fields */
struct reg_field rdma_intf;
struct reg_field rdma_bursten;
struct reg_field rdma_wpscnt;
struct reg_field rdma_fifowm;
struct reg_field rdma_enable;
struct reg_field rdma_dyncclk;
/* WR_DMA Register fields */
struct reg_field wrdma_intf;
struct reg_field wrdma_bursten;
struct reg_field wrdma_wpscnt;
struct reg_field wrdma_fifowm;
struct reg_field wrdma_enable;
struct reg_field wrdma_dyncclk;
/* CDC RXTX RD_DMA */
struct reg_field rxtx_rdma_intf;
struct reg_field rxtx_rdma_bursten;
struct reg_field rxtx_rdma_wpscnt;
struct reg_field rxtx_rdma_fifowm;
struct reg_field rxtx_rdma_enable;
struct reg_field rxtx_rdma_dyncclk;
struct reg_field rxtx_rdma_burst8;
struct reg_field rxtx_rdma_burst16;
struct reg_field rxtx_rdma_dynburst;
struct reg_field rxtx_rdma_codec_enable;
struct reg_field rxtx_rdma_codec_pack;
struct reg_field rxtx_rdma_codec_intf;
struct reg_field rxtx_rdma_codec_fs_sel;
struct reg_field rxtx_rdma_codec_ch;
struct reg_field rxtx_rdma_codec_fs_delay;
/* CDC RXTX WR_DMA */
struct reg_field rxtx_wrdma_intf;
struct reg_field rxtx_wrdma_bursten;
struct reg_field rxtx_wrdma_wpscnt;
struct reg_field rxtx_wrdma_fifowm;
struct reg_field rxtx_wrdma_enable;
struct reg_field rxtx_wrdma_dyncclk;
struct reg_field rxtx_wrdma_burst8;
struct reg_field rxtx_wrdma_burst16;
struct reg_field rxtx_wrdma_dynburst;
struct reg_field rxtx_wrdma_codec_enable;
struct reg_field rxtx_wrdma_codec_pack;
struct reg_field rxtx_wrdma_codec_intf;
struct reg_field rxtx_wrdma_codec_fs_sel;
struct reg_field rxtx_wrdma_codec_ch;
struct reg_field rxtx_wrdma_codec_fs_delay;
/* CDC VA WR_DMA */
struct reg_field va_wrdma_intf;
struct reg_field va_wrdma_bursten;
struct reg_field va_wrdma_wpscnt;
struct reg_field va_wrdma_fifowm;
struct reg_field va_wrdma_enable;
struct reg_field va_wrdma_dyncclk;
struct reg_field va_wrdma_burst8;
struct reg_field va_wrdma_burst16;
struct reg_field va_wrdma_dynburst;
struct reg_field va_wrdma_codec_enable;
struct reg_field va_wrdma_codec_pack;
struct reg_field va_wrdma_codec_intf;
struct reg_field va_wrdma_codec_fs_sel;
struct reg_field va_wrdma_codec_ch;
struct reg_field va_wrdma_codec_fs_delay;
/**
* on SOCs like APQ8016 the channel control bits start
* at different offset to ipq806x
**/
u32 dmactl_audif_start;
u32 wrdma_channel_start;
u32 rxtx_wrdma_channel_start;
u32 va_wrdma_channel_start;
/* SOC specific initialization like clocks */
int (*init)(struct platform_device *pdev);
int (*exit)(struct platform_device *pdev);
int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
/* SOC specific dais */
struct snd_soc_dai_driver *dai_driver;
int num_dai;
const char * const *dai_osr_clk_names;
const char * const *dai_bit_clk_names;
/* SOC specific clocks configuration */
const char **clk_name;
int num_clks;
};
struct lpass_pcm_data {
int dma_ch;
int i2s_port;
};
/* register the platform driver from the CPU DAI driver */
int asoc_qcom_lpass_platform_register(struct platform_device *pdev);
void asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev);
int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops2;
extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops;
#endif /* __LPASS_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/Makefile
+20
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@@ -0,0 +1,20 @@
# SPDX-License-Identifier: GPL-2.0-only
snd-q6dsp-common-y := q6dsp-common.o q6dsp-lpass-ports.o q6dsp-lpass-clocks.o
snd-q6apm-y := q6apm.o audioreach.o topology.o
obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += snd-q6dsp-common.o
obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o
obj-$(CONFIG_SND_SOC_QDSP6_AFE) += q6afe.o
obj-$(CONFIG_SND_SOC_QDSP6_AFE_DAI) += q6afe-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_AFE_CLOCKS) += q6afe-clocks.o
obj-$(CONFIG_SND_SOC_QDSP6_ADM) += q6adm.o
obj-$(CONFIG_SND_SOC_QDSP6_ROUTING) += q6routing.o
obj-$(CONFIG_SND_SOC_QDSP6_ASM) += q6asm.o
obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI) += q6apm-lpass-dais.o
obj-$(CONFIG_SND_SOC_QDSP6_PRM) += q6prm.o
obj-$(CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS) += q6prm-clocks.o
obj-$(CONFIG_SND_SOC_QDSP6_USB) += q6usb.o
linux-7.2.3/sound/soc/qcom/qdsp6/audioreach.c
+1494
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File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/qdsp6/audioreach.h
+955
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@@ -0,0 +1,955 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __AUDIOREACH_H__
#define __AUDIOREACH_H__
#include <linux/types.h>
#include <linux/soc/qcom/apr.h>
#include <uapi/sound/snd_ar_tokens.h>
#include <sound/soc.h>
struct q6apm;
struct q6apm_graph;
/* Module IDs */
#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
#define MODULE_ID_RD_SHARED_MEM_EP 0x07001001
#define MODULE_ID_GAIN 0x07001002
#define MODULE_ID_PCM_CNV 0x07001003
#define MODULE_ID_PCM_ENC 0x07001004
#define MODULE_ID_PCM_DEC 0x07001005
#define MODULE_ID_SH_MEM_PULL_MODE 0x07001006
#define MODULE_ID_SH_MEM_PUSH_MODE 0x07001007
#define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008
#define MODULE_ID_PLACEHOLDER_DECODER 0x07001009
#define MODULE_ID_I2S_SINK 0x0700100A
#define MODULE_ID_I2S_SOURCE 0x0700100B
#define MODULE_ID_SAL 0x07001010
#define MODULE_ID_MFC 0x07001015
#define MODULE_ID_DATA_LOGGING 0x0700101A
#define MODULE_ID_AAC_DEC 0x0700101F
#define MODULE_ID_CODEC_DMA_SINK 0x07001023
#define MODULE_ID_CODEC_DMA_SOURCE 0x07001024
#define MODULE_ID_FLAC_DEC 0x0700102F
#define MODULE_ID_SMECNS_V2 0x07001031
#define MODULE_ID_MP3_DECODE 0x0700103B
#define MODULE_ID_GAPLESS 0x0700104D
#define MODULE_ID_DISPLAY_PORT_SINK 0x07001069
#define MODULE_ID_SPEAKER_PROTECTION 0x070010E2
#define MODULE_ID_SPEAKER_PROTECTION_VI 0x070010E3
#define MODULE_ID_OPUS_DEC 0x07001174
#define APM_CMD_GET_SPF_STATE 0x01001021
#define APM_CMD_RSP_GET_SPF_STATE 0x02001007
#define APM_MODULE_INSTANCE_ID 0x00000001
#define PRM_MODULE_INSTANCE_ID 0x00000002
#define AMDB_MODULE_INSTANCE_ID 0x00000003
#define VCPM_MODULE_INSTANCE_ID 0x00000004
#define AR_MODULE_INSTANCE_ID_START 0x00006000
#define AR_MODULE_INSTANCE_ID_END 0x00007000
#define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000
#define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000
#define AR_CONT_INSTANCE_ID_START 0x00005000
#define AR_CONT_INSTANCE_ID_END 0x00006000
#define AR_SG_INSTANCE_ID_START 0x00004000
#define APM_CMD_GRAPH_OPEN 0x01001000
#define APM_CMD_GRAPH_PREPARE 0x01001001
#define APM_CMD_GRAPH_START 0x01001002
#define APM_CMD_GRAPH_STOP 0x01001003
#define APM_CMD_GRAPH_CLOSE 0x01001004
#define APM_CMD_GRAPH_FLUSH 0x01001005
#define APM_CMD_SET_CFG 0x01001006
#define APM_CMD_GET_CFG 0x01001007
#define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C
#define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D
#define APM_CMD_REGISTER_MODULE_EVENTS 0x0100100E
#define APM_EVENT_MODULE_TO_CLIENT 0x03001000
#define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001
#define APM_MMAP_TOKEN_GID_MASK GENMASK(15, 0)
#define APM_MMAP_TOKEN_MAP_TYPE_POS_BUF BIT(16)
#define APM_MMAP_TOKEN_MAP_TYPE_SHIFT 16
#define APM_CMD_RSP_GET_CFG 0x02001000
#define APM_CMD_CLOSE_ALL 0x01001013
#define APM_CMD_REGISTER_SHARED_CFG 0x0100100A
#define EVENT_ID_SH_MEM_PULL_PUSH_MODE_WATERMARK 0x0800101C
/**
* struct event_cfg_sh_mem_pull_push_mode_watermark_t - Watermark config
* @num_water_mark_levels: Number of watermark levels.
* @level: Watermark levels.
*
* If @num_water_mark_levels is zero, no watermark levels are specified
* and watermark events are not supported.
*/
struct event_cfg_sh_mem_pull_push_mode_watermark_t {
uint32_t num_water_mark_levels;
uint32_t level[];
} __packed;
/**
* struct apm_module_register_events - Register or unregister module events
* @module_instance_id: Module instance identifier.
* @event_id: Module event identifier.
* @is_register: 1 to register the event, 0 to unregister it.
* @error_code: Error code for out-of-band command mode.
* @event_config_payload_size: Event configuration payload size in bytes.
* @reserved: Reserved for alignment; must be zero.
*/
struct apm_module_register_events {
uint32_t module_instance_id;
uint32_t event_id;
uint32_t is_register;
uint32_t error_code;
uint32_t event_config_payload_size;
uint32_t reserved;
} __packed;
/**
* struct apm_module_event - Module event descriptor
* @event_id: Module event identifier.
* @event_payload_size: Event payload size in bytes.
*/
struct apm_module_event {
uint32_t event_id;
uint32_t event_payload_size;
} __packed;
#define APM_MEMORY_MAP_SHMEM8_4K_POOL 3
struct apm_cmd_shared_mem_map_regions {
uint16_t mem_pool_id;
uint16_t num_regions;
uint32_t property_flag;
} __packed;
struct apm_shared_map_region_payload {
uint32_t shm_addr_lsw;
uint32_t shm_addr_msw;
uint32_t mem_size_bytes;
} __packed;
struct apm_cmd_shared_mem_unmap_regions {
uint32_t mem_map_handle;
} __packed;
struct apm_cmd_rsp_shared_mem_map_regions {
uint32_t mem_map_handle;
} __packed;
/* APM module */
#define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005
#define APM_PARAM_ID_MODULE_LIST 0x08001002
struct apm_param_id_modules_list {
uint32_t num_modules_list;
} __packed;
#define APM_PARAM_ID_MODULE_PROP 0x08001003
struct apm_param_id_module_prop {
uint32_t num_modules_prop_cfg;
} __packed;
struct apm_module_prop_cfg {
uint32_t instance_id;
uint32_t num_props;
} __packed;
#define APM_PARAM_ID_MODULE_CONN 0x08001004
struct apm_param_id_module_conn {
uint32_t num_connections;
} __packed;
struct apm_module_conn_obj {
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id;
uint32_t dst_mod_inst_id;
uint32_t dst_mod_ip_port_id;
} __packed;
#define APM_PARAM_ID_GAIN 0x08001006
struct param_id_gain_cfg {
uint16_t gain;
uint16_t reserved;
} __packed;
#define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008
struct param_id_pcm_output_format_cfg {
uint32_t data_format;
uint32_t fmt_id;
uint32_t payload_size;
} __packed;
struct payload_pcm_output_format_cfg {
uint16_t bit_width;
uint16_t alignment;
uint16_t bits_per_sample;
uint16_t q_factor;
uint16_t endianness;
uint16_t interleaved;
uint16_t reserved;
uint16_t num_channels;
uint8_t channel_mapping[];
} __packed;
#define PARAM_ID_ENC_BITRATE 0x08001052
struct param_id_enc_bitrate_param {
uint32_t bitrate;
} __packed;
#define DATA_FORMAT_FIXED_POINT 1
#define DATA_FORMAT_GENERIC_COMPRESSED 5
#define DATA_FORMAT_RAW_COMPRESSED 6
#define PCM_LSB_ALIGNED 1
#define PCM_MSB_ALIGNED 2
#define PCM_LITTLE_ENDIAN 1
#define PCM_BIT_ENDIAN 2
#define MEDIA_FMT_ID_PCM 0x09001000
#define MEDIA_FMT_ID_MP3 0x09001009
#define SAMPLE_RATE_48K 48000
#define BIT_WIDTH_16 16
#define APM_PARAM_ID_PROP_PORT_INFO 0x08001015
struct apm_modules_prop_info {
uint32_t max_ip_port;
uint32_t max_op_port;
} __packed;
/* Shared memory module */
#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000
#define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31)
#define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30)
#define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29)
#define WR_SH_MEM_EP_EOF_FLAG BIT(4)
struct apm_data_cmd_wr_sh_mem_ep_data_buffer {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
} __packed;
#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A
struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
uint32_t md_addr_lsw;
uint32_t md_addr_msw;
uint32_t md_map_handle;
uint32_t md_buf_size;
} __packed;
#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000
struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t status;
} __packed;
#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004
struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t status;
uint32_t md_buf_addr_lsw;
uint32_t md_buf_addr_msw;
uint32_t md_mem_map_handle;
uint32_t md_status;
} __packed;
#define PARAM_ID_MEDIA_FORMAT 0x0800100C
#define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001
struct apm_media_format {
uint32_t data_format;
uint32_t fmt_id;
uint32_t payload_size;
} __packed;
#define MEDIA_FMT_ID_FLAC 0x09001004
struct payload_media_fmt_flac_t {
uint16_t num_channels;
uint16_t sample_size;
uint16_t min_blk_size;
uint16_t max_blk_size;
uint32_t sample_rate;
uint32_t min_frame_size;
uint32_t max_frame_size;
} __packed;
#define MEDIA_FMT_ID_AAC 0x09001001
struct payload_media_fmt_aac_t {
uint16_t aac_fmt_flag;
uint16_t audio_obj_type;
uint16_t num_channels;
uint16_t total_size_of_PCE_bits;
uint32_t sample_rate;
} __packed;
#define MEDIA_FMT_ID_OPUS 0x09001039
struct payload_media_fmt_opus_t {
uint16_t bitstream_format;
uint16_t payload_type;
uint8_t version;
uint8_t num_channels;
uint16_t pre_skip;
uint32_t sample_rate;
uint16_t output_gain;
uint8_t mapping_family;
uint8_t stream_count;
uint8_t coupled_count;
uint8_t channel_mapping[8];
uint8_t reserved[3];
} __packed;
#define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002
#define WR_SH_MEM_EP_EOS_POLICY_LAST 1
#define WR_SH_MEM_EP_EOS_POLICY_EACH 2
struct data_cmd_wr_sh_mem_ep_eos {
uint32_t policy;
} __packed;
#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003
struct data_cmd_rd_sh_mem_ep_data_buffer {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
} __packed;
#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002
struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done {
uint32_t status;
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t data_size;
uint32_t offset;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
uint32_t num_frames;
} __packed;
#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B
struct data_cmd_rd_sh_mem_ep_data_buffer_v2 {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
uint32_t md_buf_addr_lsw;
uint32_t md_buf_addr_msw;
uint32_t md_mem_map_handle;
uint32_t md_buf_size;
} __packed;
#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005
struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 {
uint32_t status;
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t data_size;
uint32_t offset;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
uint32_t num_frames;
uint32_t md_status;
uint32_t md_buf_addr_lsw;
uint32_t md_buf_addr_msw;
uint32_t md_mem_map_handle;
uint32_t md_size;
} __packed;
#define PARAM_ID_RD_SH_MEM_CFG 0x08001007
struct param_id_rd_sh_mem_cfg {
uint32_t num_frames_per_buffer;
uint32_t metadata_control_flags;
} __packed;
#define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001
struct data_cmd_wr_sh_mem_ep_eos_rendered {
uint32_t module_instance_id;
uint32_t render_status;
} __packed;
#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
struct apm_cmd_header {
uint32_t payload_address_lsw;
uint32_t payload_address_msw;
uint32_t mem_map_handle;
uint32_t payload_size;
} __packed;
#define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header)
struct apm_module_param_data {
uint32_t module_instance_id;
uint32_t param_id;
uint32_t param_size;
uint32_t error_code;
} __packed;
#define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data)
struct apm_module_param_shared_data {
uint32_t param_id;
uint32_t param_size;
} __packed;
struct apm_prop_data {
uint32_t prop_id;
uint32_t prop_size;
} __packed;
/* Sub-Graph Properties */
#define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001
struct apm_param_id_sub_graph_cfg {
uint32_t num_sub_graphs;
} __packed;
struct apm_sub_graph_cfg {
uint32_t sub_graph_id;
uint32_t num_sub_graph_prop;
} __packed;
#define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E
struct apm_sg_prop_id_perf_mode {
uint32_t perf_mode;
} __packed;
#define APM_SG_PROP_ID_PERF_MODE_SIZE 4
#define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F
struct apm_sg_prop_id_direction {
uint32_t direction;
} __packed;
#define APM_SG_PROP_ID_DIR_SIZE 4
#define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010
#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2
#define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3
struct apm_sg_prop_id_scenario_id {
uint32_t scenario_id;
} __packed;
#define APM_SG_PROP_ID_SID_SIZE 4
/* container api */
#define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000
struct apm_param_id_container_cfg {
uint32_t num_containers;
} __packed;
struct apm_container_cfg {
uint32_t container_id;
uint32_t num_prop;
} __packed;
struct apm_cont_capability {
uint32_t capability_id;
} __packed;
#define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011
#define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8
#define APM_PROP_ID_INVALID 0x0
#define APM_CONTAINER_CAP_ID_PP 0x1
#define APM_CONTAINER_CAP_ID_PP 0x1
struct apm_cont_prop_id_cap_list {
uint32_t num_capability_id;
} __packed;
#define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012
struct apm_cont_prop_id_graph_pos {
uint32_t graph_pos;
} __packed;
#define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013
struct apm_cont_prop_id_stack_size {
uint32_t stack_size;
} __packed;
#define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014
struct apm_cont_prop_id_domain {
uint32_t proc_domain;
} __packed;
#define CONFIG_I2S_WS_SRC_EXTERNAL 0x0
#define CONFIG_I2S_WS_SRC_INTERNAL 0x1
#define PARAM_ID_I2S_INTF_CFG 0x08001019
struct param_id_i2s_intf_cfg {
uint32_t lpaif_type;
uint32_t intf_idx;
uint16_t sd_line_idx;
uint16_t ws_src;
} __packed;
#define I2S_INTF_TYPE_PRIMARY 0
#define I2S_INTF_TYPE_SECONDARY 1
#define I2S_INTF_TYPE_TERTIARY 2
#define I2S_INTF_TYPE_QUATERNARY 3
#define I2S_INTF_TYPE_QUINARY 4
#define I2S_SD0 1
#define I2S_SD1 2
#define I2S_SD2 3
#define I2S_SD3 4
#define PORT_ID_I2S_INPUT 2
#define PORT_ID_I2S_OUPUT 1
#define I2S_STACK_SIZE 2048
#define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154
struct param_id_display_port_intf_cfg {
uint32_t channel_allocation;
/* Multi-Steam Transport index */
uint32_t mst_idx;
uint32_t dptx_idx;
} __packed;
#define PARAM_ID_HW_EP_MF_CFG 0x08001017
struct param_id_hw_ep_mf {
uint32_t sample_rate;
uint16_t bit_width;
uint16_t num_channels;
uint32_t data_format;
} __packed;
#define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018
struct param_id_fram_size_factor {
uint32_t frame_size_factor;
} __packed;
#define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB
struct apm_cont_prop_id_parent_container {
uint32_t parent_container_id;
} __packed;
#define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174
#define APM_CONT_HEAP_DEFAULT 0x1
#define APM_CONT_HEAP_LOW_POWER 0x2
struct apm_cont_prop_id_headp_id {
uint32_t heap_id;
} __packed;
struct apm_modules_list {
uint32_t sub_graph_id;
uint32_t container_id;
uint32_t num_modules;
} __packed;
struct apm_module_obj {
uint32_t module_id;
uint32_t instance_id;
} __packed;
#define APM_MODULE_PROP_ID_PORT_INFO 0x08001015
#define APM_MODULE_PROP_ID_PORT_INFO_SZ 8
struct apm_module_prop_id_port_info {
uint32_t max_ip_port;
uint32_t max_op_port;
} __packed;
#define DATA_LOGGING_MAX_INPUT_PORTS 0x1
#define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1
#define DATA_LOGGING_STACK_SIZE 2048
#define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031
struct data_logging_config {
uint32_t log_code;
uint32_t log_tap_point_id;
uint32_t mode;
} __packed;
/* Speaker Protection */
#define PARAM_ID_SP_OP_MODE 0x080011e9
#define PARAM_ID_SP_OP_MODE_NORMAL 0
#define PARAM_ID_SP_OP_MODE_CALIBRATION 1
#define PARAM_ID_SP_OP_MODE_FACTORY_TEST 2
#define PARAM_ID_SP_OP_MODE_VALIDATION 3
struct param_id_sp_op_mode {
uint32_t operation_mode;
} __packed;
/* Speaker Protection VI */
#define PARAM_ID_SP_VI_OP_MODE_CFG 0x080011f4
#define PARAM_ID_SP_VI_OP_MODE_NORMAL 0
#define PARAM_ID_SP_VI_OP_MODE_CALIBRATION 1
#define PARAM_ID_SP_VI_OP_MODE_FACTORY_TEST 2
#define PARAM_ID_SP_VI_OP_MODE_VALIDATION 3
struct param_id_sp_vi_op_mode_cfg {
uint32_t num_channels;
uint32_t operation_mode;
uint32_t quick_calibration;
uint32_t r0_t0_selection[];
} __packed;
#define PARAM_ID_SP_VI_EX_MODE_CFG 0x080011ff
struct param_id_sp_vi_ex_mode_cfg {
uint32_t factory_mode;
} __packed;
#define PARAM_ID_SP_VI_CHANNEL_MAP_CFG 0x08001203
struct param_id_sp_vi_channel_map_cfg {
uint32_t num_channels;
/* [ Vsense of ch 1, Isense of ch 1, Vsense of ch 2, Isense of ch 2, ... ] */
uint32_t channel_mapping[];
} __packed;
#define PARAM_ID_SAL_OUTPUT_CFG 0x08001016
struct param_id_sal_output_config {
uint32_t bits_per_sample;
} __packed;
#define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E
struct param_id_sal_limiter_enable {
uint32_t enable_lim;
} __packed;
#define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024
#define PARAM_ID_EARLY_EOS_DELAY 0x0800114C
#define EARLY_EOS_DELAY_MS 150
struct param_id_mfc_media_format {
uint32_t sample_rate;
uint16_t bit_width;
uint16_t num_channels;
uint16_t channel_mapping[];
} __packed;
struct param_id_gapless_early_eos_delay_t {
uint32_t early_eos_delay_ms;
} __packed;
struct media_format {
uint32_t data_format;
uint32_t fmt_id;
uint32_t payload_size;
} __packed;
struct payload_media_fmt_pcm {
uint32_t sample_rate;
uint16_t bit_width;
uint16_t alignment;
uint16_t bits_per_sample;
uint16_t q_factor;
uint16_t endianness;
uint16_t num_channels;
uint8_t channel_mapping[];
} __packed;
#define PARAM_ID_MODULE_ENABLE 0x08001026
struct param_id_module_enable {
uint32_t enable;
} __packed;
#define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063
struct param_id_codec_dma_intf_cfg {
/* 1 - RXTX
* 2 - WSA
* 3 - VA
* 4 - AXI
*/
uint32_t lpaif_type;
/*
* RX0 | TX0 = 1
* RX1 | TX1 = 2
* RX2 | TX2 = 3... so on
*/
uint32_t intf_index;
uint32_t active_channels_mask;
} __packed;
struct audio_hw_clk_cfg {
uint32_t clock_id;
uint32_t clock_freq;
uint32_t clock_attri;
uint32_t clock_root;
} __packed;
struct audio_hw_clk_rel_cfg {
uint32_t clock_id;
} __packed;
#define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176
#define AR_HW_EP_POWER_MODE_0 0 /* default */
#define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */
#define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */
struct param_id_hw_ep_power_mode_cfg {
uint32_t power_mode;
} __packed;
#define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233
#define AR_HW_EP_DMA_DATA_ALIGN_MSB 0
#define AR_HW_EP_DMA_DATA_ALIGN_LSB 1
#define AR_PCM_MAX_NUM_CHANNEL 8
struct param_id_hw_ep_dma_data_align {
uint32_t dma_data_align;
} __packed;
#define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035
#define VOL_CTRL_DEFAULT_GAIN 0x2000
struct param_id_vol_ctrl_master_gain {
uint16_t master_gain;
uint16_t reserved;
} __packed;
#define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B
#define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D
#define PARAM_ID_REAL_MODULE_ID 0x0800100B
struct param_id_placeholder_real_module_id {
uint32_t real_module_id;
} __packed;
#define PARAM_ID_SH_MEM_PULL_PUSH_MODE_CFG 0x0800100A
/**
* struct param_id_sh_mem_pull_push_mode_cfg - Shared memory push/pull config
* @shared_circ_buf_addr_lsw: Lower 32 bits of the circular buffer address.
* @shared_circ_buf_addr_msw: Upper 32 bits of the circular buffer address.
* @shared_circ_buf_size: Circular buffer size in bytes.
* @circ_buf_mem_map_handle: Circular buffer memory map handle.
* @shared_pos_buf_addr_lsw: Lower 32 bits of the position buffer address.
* @shared_pos_buf_addr_msw: Upper 32 bits of the position buffer address.
* @pos_buf_mem_map_handle: Position buffer memory map handle.
*/
struct param_id_sh_mem_pull_push_mode_cfg {
uint32_t shared_circ_buf_addr_lsw;
uint32_t shared_circ_buf_addr_msw;
uint32_t shared_circ_buf_size;
uint32_t circ_buf_mem_map_handle;
uint32_t shared_pos_buf_addr_lsw;
uint32_t shared_pos_buf_addr_msw;
uint32_t pos_buf_mem_map_handle;
} __packed;
/**
* struct sh_mem_pull_push_mode_position_buffer - Shared position buffer
* @frame_counter: Synchronization counter.
* @index: Current read/write index in bytes.
* @timestamp_us_lsw: Lower 32 bits of the timestamp in microseconds.
* @timestamp_us_msw: Upper 32 bits of the timestamp in microseconds.
*
* The frame counter should be read before and after the other fields to
* ensure the DSP did not update them while they were being read.
*/
struct sh_mem_pull_push_mode_position_buffer {
uint32_t frame_counter;
uint32_t index;
uint32_t timestamp_us_lsw;
uint32_t timestamp_us_msw;
} __packed;
/* Graph */
struct audioreach_connection {
/* Connections */
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id;
uint32_t dst_mod_inst_id;
uint32_t dst_mod_ip_port_id;
struct list_head node;
};
struct audioreach_graph_info {
int id;
uint32_t mem_map_handle;
uint32_t pos_buf_mem_map_handle;
uint32_t num_sub_graphs;
struct list_head sg_list;
bool is_push_pull_mode;
/* DPCM connection from FE Graph to BE graph */
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id;
uint32_t dst_mod_inst_id;
uint32_t dst_mod_ip_port_id;
};
struct audioreach_sub_graph {
uint32_t sub_graph_id;
uint32_t perf_mode;
uint32_t direction;
uint32_t scenario_id;
struct list_head node;
struct audioreach_graph_info *info;
uint32_t num_containers;
struct list_head container_list;
};
struct audioreach_container {
uint32_t container_id;
uint32_t capability_id;
uint32_t graph_pos;
uint32_t stack_size;
uint32_t proc_domain;
struct list_head node;
uint32_t num_modules;
struct list_head modules_list;
struct audioreach_sub_graph *sub_graph;
};
#define AR_MAX_MOD_LINKS 8
struct audioreach_module {
uint32_t module_id;
uint32_t instance_id;
uint32_t max_ip_port;
uint32_t max_op_port;
uint32_t num_connections;
/* Connections */
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS];
uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS];
uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS];
/* Format specifics */
uint32_t ch_fmt;
uint32_t rate;
uint32_t bit_depth;
/* I2S module */
uint32_t hw_interface_idx;
uint32_t sd_line_idx;
uint32_t ws_src;
uint32_t frame_size_factor;
uint32_t data_format;
uint32_t hw_interface_type;
/* PCM module specific */
uint32_t interleave_type;
/* GAIN/Vol Control Module */
uint16_t gain;
/* Logging */
uint32_t log_code;
uint32_t log_tap_point_id;
uint32_t log_mode;
/* bookkeeping */
struct list_head node;
struct audioreach_container *container;
struct snd_soc_dapm_widget *widget;
struct audioreach_module_priv_data *data;
};
struct audioreach_module_config {
int direction;
u32 sample_rate;
u16 bit_width;
u16 bits_per_sample;
u16 data_format;
u16 num_channels;
u16 dp_idx;
u32 channel_allocation;
u32 sd_line_mask;
int fmt;
struct snd_codec codec;
u8 channel_map[AR_PCM_MAX_NUM_CHANNEL];
};
/* Packet Allocation routines */
void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t
token);
void audioreach_set_default_channel_mapping(u8 *ch_map, int num_channels);
void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode,
uint32_t token, uint32_t src_port,
uint32_t dest_port);
void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token,
uint32_t src_port);
void *audioreach_alloc_pkt(int payload_size, uint32_t opcode,
uint32_t token, uint32_t src_port,
uint32_t dest_port);
void *audioreach_alloc_graph_pkt(struct q6apm *apm,
const struct audioreach_graph_info *info);
/* Topology specific */
int audioreach_tplg_init(struct snd_soc_component *component);
/* Module specific */
void audioreach_graph_free_buf(struct q6apm_graph *graph);
int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result,
struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait,
const struct gpr_pkt *pkt, uint32_t rsp_opcode);
int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, const struct gpr_pkt *pkt,
uint32_t rsp_opcode);
int audioreach_set_media_format(struct q6apm_graph *graph,
const struct audioreach_module *module,
const struct audioreach_module_config *cfg);
int audioreach_shared_memory_send_eos(struct q6apm_graph *graph);
int audioreach_gain_set_vol_ctrl(struct q6apm *apm,
const struct audioreach_module *module, int vol);
int audioreach_send_u32_param(struct q6apm_graph *graph,
const struct audioreach_module *module,
uint32_t param_id, uint32_t param_val);
int audioreach_compr_set_param(struct q6apm_graph *graph,
const struct audioreach_module_config *mcfg);
int audioreach_setup_push_pull(struct q6apm_graph *graph, phys_addr_t bphys,
phys_addr_t pphys, uint32_t mem_map_handle,
uint32_t pos_buf_mem_map_handle, uint32_t size);
int audioreach_map_memory_position_buffer(struct q6apm_graph *graph, unsigned int dir);
int audioreach_shmem_register_event(struct q6apm_graph *graph, int bytes, int num_levels);
#endif /* __AUDIOREACH_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6adm.c
+609
View File
@@ -0,0 +1,609 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/soc/qcom/apr.h>
#include <linux/wait.h>
#include <sound/asound.h>
#include "q6adm.h"
#include "q6afe.h"
#include "q6core.h"
#include "q6dsp-common.h"
#include "q6dsp-errno.h"
#define ADM_CMD_DEVICE_OPEN_V5 0x00010326
#define ADM_CMDRSP_DEVICE_OPEN_V5 0x00010329
#define ADM_CMD_DEVICE_CLOSE_V5 0x00010327
#define ADM_CMD_MATRIX_MAP_ROUTINGS_V5 0x00010325
#define TIMEOUT_MS 1000
#define RESET_COPP_ID 99
#define INVALID_COPP_ID 0xFF
/* Definition for a legacy device session. */
#define ADM_LEGACY_DEVICE_SESSION 0
#define ADM_MATRIX_ID_AUDIO_RX 0
#define ADM_MATRIX_ID_AUDIO_TX 1
struct q6copp {
int afe_port;
int copp_idx;
int id;
int topology;
int mode;
int rate;
int bit_width;
int channels;
int app_type;
int acdb_id;
struct aprv2_ibasic_rsp_result_t result;
struct kref refcount;
wait_queue_head_t wait;
struct list_head node;
struct q6adm *adm;
};
struct q6adm {
struct apr_device *apr;
struct device *dev;
struct q6core_svc_api_info ainfo;
unsigned long copp_bitmap[AFE_MAX_PORTS];
struct list_head copps_list;
spinlock_t copps_list_lock;
struct aprv2_ibasic_rsp_result_t result;
struct mutex lock;
wait_queue_head_t matrix_map_wait;
};
struct q6adm_cmd_device_open_v5 {
u16 flags;
u16 mode_of_operation;
u16 endpoint_id_1;
u16 endpoint_id_2;
u32 topology_id;
u16 dev_num_channel;
u16 bit_width;
u32 sample_rate;
u8 dev_channel_mapping[8];
} __packed;
struct q6adm_cmd_matrix_map_routings_v5 {
u32 matrix_id;
u32 num_sessions;
} __packed;
struct q6adm_session_map_node_v5 {
u16 session_id;
u16 num_copps;
} __packed;
static struct q6copp *q6adm_find_copp(struct q6adm *adm, int port_idx,
int copp_idx)
{
struct q6copp *c;
struct q6copp *ret = NULL;
unsigned long flags;
spin_lock_irqsave(&adm->copps_list_lock, flags);
list_for_each_entry(c, &adm->copps_list, node) {
if ((port_idx == c->afe_port) && (copp_idx == c->copp_idx)) {
ret = c;
kref_get(&c->refcount);
break;
}
}
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
return ret;
}
static int q6adm_apr_send_copp_pkt(struct q6adm *adm, struct q6copp *copp,
struct apr_pkt *pkt, uint32_t rsp_opcode)
{
struct device *dev = adm->dev;
uint32_t opcode = pkt->hdr.opcode;
int ret;
mutex_lock(&adm->lock);
copp->result.opcode = 0;
copp->result.status = 0;
ret = apr_send_pkt(adm->apr, pkt);
if (ret < 0) {
dev_err(dev, "Failed to send APR packet\n");
ret = -EINVAL;
goto err;
}
/* Wait for the callback with copp id */
if (rsp_opcode)
ret = wait_event_timeout(copp->wait,
(copp->result.opcode == opcode) ||
(copp->result.opcode == rsp_opcode),
msecs_to_jiffies(TIMEOUT_MS));
else
ret = wait_event_timeout(copp->wait,
(copp->result.opcode == opcode),
msecs_to_jiffies(TIMEOUT_MS));
if (!ret) {
dev_err(dev, "ADM copp cmd timedout\n");
ret = -ETIMEDOUT;
} else if (copp->result.status > 0) {
dev_err(dev, "DSP returned error[%d]\n",
copp->result.status);
ret = -EINVAL;
}
err:
mutex_unlock(&adm->lock);
return ret;
}
static int q6adm_device_close(struct q6adm *adm, struct q6copp *copp,
int port_id, int copp_idx)
{
struct apr_pkt close;
close.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
close.hdr.pkt_size = sizeof(close);
close.hdr.src_port = port_id;
close.hdr.dest_port = copp->id;
close.hdr.token = port_id << 16 | copp_idx;
close.hdr.opcode = ADM_CMD_DEVICE_CLOSE_V5;
return q6adm_apr_send_copp_pkt(adm, copp, &close, 0);
}
static void q6adm_free_copp(struct kref *ref)
{
struct q6copp *c = container_of(ref, struct q6copp, refcount);
struct q6adm *adm = c->adm;
unsigned long flags;
int ret;
ret = q6adm_device_close(adm, c, c->afe_port, c->copp_idx);
if (ret < 0)
dev_err(adm->dev, "Failed to close copp %d\n", ret);
spin_lock_irqsave(&adm->copps_list_lock, flags);
clear_bit(c->copp_idx, &adm->copp_bitmap[c->afe_port]);
list_del(&c->node);
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
kfree(c);
}
static int q6adm_callback(struct apr_device *adev, const struct apr_resp_pkt *data)
{
const struct aprv2_ibasic_rsp_result_t *result = data->payload;
int port_idx, copp_idx;
const struct apr_hdr *hdr = &data->hdr;
struct q6copp *copp;
struct q6adm *adm = dev_get_drvdata(&adev->dev);
if (!data->payload_size)
return 0;
copp_idx = (hdr->token) & 0XFF;
port_idx = ((hdr->token) >> 16) & 0xFF;
if (port_idx < 0 || port_idx >= AFE_MAX_PORTS) {
dev_err(&adev->dev, "Invalid port idx %d token %d\n",
port_idx, hdr->token);
return 0;
}
if (copp_idx < 0 || copp_idx >= MAX_COPPS_PER_PORT) {
dev_err(&adev->dev, "Invalid copp idx %d token %d\n",
copp_idx, hdr->token);
return 0;
}
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT: {
if (result->status != 0) {
dev_err(&adev->dev, "cmd = 0x%x return error = 0x%x\n",
result->opcode, result->status);
}
switch (result->opcode) {
case ADM_CMD_DEVICE_OPEN_V5:
case ADM_CMD_DEVICE_CLOSE_V5:
list_for_each_entry(copp, &adm->copps_list, node) {
if ((port_idx == copp->afe_port) && (copp_idx == copp->copp_idx)) {
copp->result = *result;
wake_up(&copp->wait);
break;
}
}
break;
case ADM_CMD_MATRIX_MAP_ROUTINGS_V5:
adm->result = *result;
wake_up(&adm->matrix_map_wait);
break;
default:
dev_err(&adev->dev, "Unknown Cmd: 0x%x\n",
result->opcode);
break;
}
return 0;
}
case ADM_CMDRSP_DEVICE_OPEN_V5: {
struct adm_cmd_rsp_device_open_v5 {
u32 status;
u16 copp_id;
u16 reserved;
} __packed *open = data->payload;
copp = q6adm_find_copp(adm, port_idx, copp_idx);
if (!copp)
return 0;
if (open->copp_id == INVALID_COPP_ID) {
dev_err(&adev->dev, "Invalid coppid rxed %d\n",
open->copp_id);
copp->result.status = ADSP_EBADPARAM;
wake_up(&copp->wait);
kref_put(&copp->refcount, q6adm_free_copp);
break;
}
copp->result.opcode = hdr->opcode;
copp->id = open->copp_id;
wake_up(&copp->wait);
kref_put(&copp->refcount, q6adm_free_copp);
}
break;
default:
dev_err(&adev->dev, "Unknown cmd:0x%x\n",
hdr->opcode);
break;
}
return 0;
}
static struct q6copp *q6adm_alloc_copp(struct q6adm *adm, int port_idx)
{
struct q6copp *c;
int idx;
idx = find_first_zero_bit(&adm->copp_bitmap[port_idx],
MAX_COPPS_PER_PORT);
if (idx >= MAX_COPPS_PER_PORT)
return ERR_PTR(-EBUSY);
c = kzalloc_obj(*c, GFP_ATOMIC);
if (!c)
return ERR_PTR(-ENOMEM);
set_bit(idx, &adm->copp_bitmap[port_idx]);
c->copp_idx = idx;
c->afe_port = port_idx;
c->adm = adm;
init_waitqueue_head(&c->wait);
return c;
}
static struct q6copp *q6adm_find_matching_copp(struct q6adm *adm,
int port_id, int topology,
int mode, int rate,
int channel_mode, int bit_width,
int app_type)
{
struct q6copp *c;
struct q6copp *ret = NULL;
unsigned long flags;
spin_lock_irqsave(&adm->copps_list_lock, flags);
list_for_each_entry(c, &adm->copps_list, node) {
if ((port_id == c->afe_port) && (topology == c->topology) &&
(mode == c->mode) && (rate == c->rate) &&
(bit_width == c->bit_width) && (app_type == c->app_type)) {
ret = c;
kref_get(&c->refcount);
}
}
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
return ret;
}
static int q6adm_device_open(struct q6adm *adm, struct q6copp *copp,
int port_id, int path, int topology,
int channel_mode, int bit_width, int rate)
{
struct q6adm_cmd_device_open_v5 *open;
int afe_port = q6afe_get_port_id(port_id);
struct apr_pkt *pkt;
int ret, pkt_size = APR_HDR_SIZE + sizeof(*open);
void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
open = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = afe_port;
pkt->hdr.dest_port = afe_port;
pkt->hdr.token = port_id << 16 | copp->copp_idx;
pkt->hdr.opcode = ADM_CMD_DEVICE_OPEN_V5;
open->flags = ADM_LEGACY_DEVICE_SESSION;
open->mode_of_operation = path;
open->endpoint_id_1 = afe_port;
open->topology_id = topology;
open->dev_num_channel = channel_mode & 0x00FF;
open->bit_width = bit_width;
open->sample_rate = rate;
ret = q6dsp_map_channels(&open->dev_channel_mapping[0],
channel_mode);
if (ret)
return ret;
return q6adm_apr_send_copp_pkt(adm, copp, pkt, ADM_CMDRSP_DEVICE_OPEN_V5);
}
/**
* q6adm_open() - open adm and grab a free copp
*
* @dev: Pointer to adm child device.
* @port_id: port id
* @path: playback or capture path.
* @rate: rate at which copp is required.
* @channel_mode: channel mode
* @topology: adm topology id
* @perf_mode: performace mode.
* @bit_width: audio sample bit width
* @app_type: Application type.
* @acdb_id: ACDB id
*
* Return: Will be an negative on error or a valid copp pointer on success.
*/
struct q6copp *q6adm_open(struct device *dev, int port_id, int path, int rate,
int channel_mode, int topology, int perf_mode,
uint16_t bit_width, int app_type, int acdb_id)
{
struct q6adm *adm = dev_get_drvdata(dev->parent);
struct q6copp *copp;
unsigned long flags;
int ret = 0;
if (port_id < 0) {
dev_err(dev, "Invalid port_id %d\n", port_id);
return ERR_PTR(-EINVAL);
}
copp = q6adm_find_matching_copp(adm, port_id, topology, perf_mode,
rate, channel_mode, bit_width, app_type);
if (copp) {
dev_err(dev, "Found Matching Copp 0x%x\n", copp->copp_idx);
return copp;
}
spin_lock_irqsave(&adm->copps_list_lock, flags);
copp = q6adm_alloc_copp(adm, port_id);
if (IS_ERR(copp)) {
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
return ERR_CAST(copp);
}
list_add_tail(&copp->node, &adm->copps_list);
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
kref_init(&copp->refcount);
copp->topology = topology;
copp->mode = perf_mode;
copp->rate = rate;
copp->channels = channel_mode;
copp->bit_width = bit_width;
copp->app_type = app_type;
ret = q6adm_device_open(adm, copp, port_id, path, topology,
channel_mode, bit_width, rate);
if (ret < 0) {
kref_put(&copp->refcount, q6adm_free_copp);
return ERR_PTR(ret);
}
return copp;
}
EXPORT_SYMBOL_GPL(q6adm_open);
/**
* q6adm_get_copp_id() - get copp index
*
* @copp: Pointer to valid copp
*
* Return: Will be an negative on error or a valid copp index on success.
**/
int q6adm_get_copp_id(struct q6copp *copp)
{
if (!copp)
return -EINVAL;
return copp->copp_idx;
}
EXPORT_SYMBOL_GPL(q6adm_get_copp_id);
/**
* q6adm_matrix_map() - Map asm streams and afe ports using payload
*
* @dev: Pointer to adm child device.
* @path: playback or capture path.
* @payload_map: map between session id and afe ports.
* @perf_mode: Performace mode.
*
* Return: Will be an negative on error or a zero on success.
*/
int q6adm_matrix_map(struct device *dev, int path,
struct route_payload payload_map, int perf_mode)
{
struct q6adm *adm = dev_get_drvdata(dev->parent);
struct q6adm_cmd_matrix_map_routings_v5 *route;
struct q6adm_session_map_node_v5 *node;
struct apr_pkt *pkt;
uint16_t *copps_list;
int ret, i, copp_idx;
/* Assumes port_ids have already been validated during adm_open */
struct q6copp *copp;
int pkt_size = (APR_HDR_SIZE + sizeof(*route) + sizeof(*node) +
(sizeof(uint32_t) * payload_map.num_copps));
void *matrix_map __free(kfree) = kzalloc(pkt_size, GFP_KERNEL);
if (!matrix_map)
return -ENOMEM;
pkt = matrix_map;
route = matrix_map + APR_HDR_SIZE;
node = matrix_map + APR_HDR_SIZE + sizeof(*route);
copps_list = matrix_map + APR_HDR_SIZE + sizeof(*route) + sizeof(*node);
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.token = 0;
pkt->hdr.opcode = ADM_CMD_MATRIX_MAP_ROUTINGS_V5;
route->num_sessions = 1;
switch (path) {
case ADM_PATH_PLAYBACK:
route->matrix_id = ADM_MATRIX_ID_AUDIO_RX;
break;
case ADM_PATH_LIVE_REC:
route->matrix_id = ADM_MATRIX_ID_AUDIO_TX;
break;
default:
dev_err(dev, "Wrong path set[%d]\n", path);
break;
}
node->session_id = payload_map.session_id;
node->num_copps = payload_map.num_copps;
for (i = 0; i < payload_map.num_copps; i++) {
int port_idx = payload_map.port_id[i];
if (port_idx < 0) {
dev_err(dev, "Invalid port_id %d\n",
payload_map.port_id[i]);
return -EINVAL;
}
copp_idx = payload_map.copp_idx[i];
copp = q6adm_find_copp(adm, port_idx, copp_idx);
if (!copp)
return -EINVAL;
copps_list[i] = copp->id;
kref_put(&copp->refcount, q6adm_free_copp);
}
mutex_lock(&adm->lock);
adm->result.status = 0;
adm->result.opcode = 0;
ret = apr_send_pkt(adm->apr, pkt);
if (ret < 0) {
dev_err(dev, "routing for stream %d failed ret %d\n",
payload_map.session_id, ret);
goto fail_cmd;
}
ret = wait_event_timeout(adm->matrix_map_wait,
adm->result.opcode == pkt->hdr.opcode,
msecs_to_jiffies(TIMEOUT_MS));
if (!ret) {
dev_err(dev, "routing for stream %d failed\n",
payload_map.session_id);
ret = -ETIMEDOUT;
goto fail_cmd;
} else if (adm->result.status > 0) {
dev_err(dev, "DSP returned error[%d]\n",
adm->result.status);
ret = -EINVAL;
goto fail_cmd;
}
fail_cmd:
mutex_unlock(&adm->lock);
return ret;
}
EXPORT_SYMBOL_GPL(q6adm_matrix_map);
/**
* q6adm_close() - Close adm copp
*
* @dev: Pointer to adm child device.
* @copp: pointer to previously opened copp
*
* Return: Will be an negative on error or a zero on success.
*/
int q6adm_close(struct device *dev, struct q6copp *copp)
{
kref_put(&copp->refcount, q6adm_free_copp);
return 0;
}
EXPORT_SYMBOL_GPL(q6adm_close);
static int q6adm_probe(struct apr_device *adev)
{
struct device *dev = &adev->dev;
struct q6adm *adm;
adm = devm_kzalloc(dev, sizeof(*adm), GFP_KERNEL);
if (!adm)
return -ENOMEM;
adm->apr = adev;
dev_set_drvdata(dev, adm);
adm->dev = dev;
q6core_get_svc_api_info(adev->svc_id, &adm->ainfo);
mutex_init(&adm->lock);
init_waitqueue_head(&adm->matrix_map_wait);
INIT_LIST_HEAD(&adm->copps_list);
spin_lock_init(&adm->copps_list_lock);
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id q6adm_device_id[] = {
{ .compatible = "qcom,q6adm" },
{},
};
MODULE_DEVICE_TABLE(of, q6adm_device_id);
#endif
static struct apr_driver qcom_q6adm_driver = {
.probe = q6adm_probe,
.callback = q6adm_callback,
.driver = {
.name = "qcom-q6adm",
.of_match_table = of_match_ptr(q6adm_device_id),
},
};
module_apr_driver(qcom_q6adm_driver);
MODULE_DESCRIPTION("Q6 Audio Device Manager");
MODULE_LICENSE("GPL v2");
linux-7.2.3/sound/soc/qcom/qdsp6/q6adm.h
+27
View File
@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6_ADM_V2_H__
#define __Q6_ADM_V2_H__
#define ADM_PATH_PLAYBACK 0x1
#define ADM_PATH_LIVE_REC 0x2
#define MAX_COPPS_PER_PORT 8
#define NULL_COPP_TOPOLOGY 0x00010312
/* multiple copp per stream. */
struct route_payload {
int num_copps;
int session_id;
int copp_idx[MAX_COPPS_PER_PORT];
int port_id[MAX_COPPS_PER_PORT];
};
struct q6copp;
struct q6copp *q6adm_open(struct device *dev, int port_id, int path, int rate,
int channel_mode, int topology, int perf_mode,
uint16_t bit_width, int app_type, int acdb_id);
int q6adm_close(struct device *dev, struct q6copp *copp);
int q6adm_get_copp_id(struct q6copp *copp);
int q6adm_matrix_map(struct device *dev, int path,
struct route_payload payload_map, int perf_mode);
#endif /* __Q6_ADM_V2_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6afe-clocks.c
+120
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@@ -0,0 +1,120 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include "q6dsp-lpass-clocks.h"
#include "q6afe.h"
#define Q6AFE_CLK(id) { \
.clk_id = id, \
.q6dsp_clk_id = Q6AFE_##id, \
.name = #id, \
.rate = 19200000, \
}
static const struct q6dsp_clk_init q6afe_clks[] = {
Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUI_PCM_OSR),
Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_OSR),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_1),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_2),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_3),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_4),
Q6AFE_CLK(LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE),
Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_0),
Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_1),
Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6DSP_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
Q6AFE_LPASS_CORE_AVTIMER_BLOCK,
"LPASS_AVTIMER_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE,
Q6AFE_LPASS_CORE_HW_MACRO_BLOCK,
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK,
"LPASS_HW_DCODEC"),
};
static const struct q6dsp_clk_desc q6dsp_clk_q6afe __maybe_unused = {
.clks = q6afe_clks,
.num_clks = ARRAY_SIZE(q6afe_clks),
.lpass_set_clk = q6afe_set_lpass_clock,
.lpass_vote_clk = q6afe_vote_lpass_core_hw,
.lpass_unvote_clk = q6afe_unvote_lpass_core_hw,
};
#ifdef CONFIG_OF
static const struct of_device_id q6afe_clock_device_id[] = {
{ .compatible = "qcom,q6afe-clocks", .data = &q6dsp_clk_q6afe },
{},
};
MODULE_DEVICE_TABLE(of, q6afe_clock_device_id);
#endif
static struct platform_driver q6afe_clock_platform_driver = {
.driver = {
.name = "q6afe-clock",
.of_match_table = of_match_ptr(q6afe_clock_device_id),
},
.probe = q6dsp_clock_dev_probe,
};
module_platform_driver(q6afe_clock_platform_driver);
MODULE_DESCRIPTION("Q6 Audio Frontend clock driver");
MODULE_LICENSE("GPL v2");
linux-7.2.3/sound/soc/qcom/qdsp6/q6afe-dai.c
+1153
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/qdsp6/q6afe.c
+1949
View File
File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/qdsp6/q6afe.h
+275
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@@ -0,0 +1,275 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6AFE_H__
#define __Q6AFE_H__
#include "../common.h"
#define AFE_PORT_MAX (LPASS_MAX_PORT)
#define MSM_AFE_PORT_TYPE_RX 0
#define MSM_AFE_PORT_TYPE_TX 1
#define AFE_MAX_PORTS AFE_PORT_MAX
#define Q6AFE_MAX_MI2S_LINES 4
#define AFE_MAX_CHAN_COUNT 8
#define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
#define LPAIF_DIG_CLK 1
#define LPAIF_BIT_CLK 2
#define LPAIF_OSR_CLK 3
/* Clock ID for Primary I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
/* Clock ID for Primary I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
/* Clock ID for Secondary I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
/* Clock ID for Secondary I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
/* Clock ID for Tertiary I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
/* Clock ID for Tertiary I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
/* Clock ID for Quartnery I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
/* Clock ID for Quartnery I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
/* Clock ID for Speaker I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
/* Clock ID for Speaker I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
/* Clock ID for Speaker I2S OSR */
#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
/* Clock ID for QUINARY I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
/* Clock ID for QUINARY I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
/* Clock ID for SENARY I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
/* Clock ID for SENARY I2S EBIT */
#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
/* Clock ID for INT0 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
/* Clock ID for INT1 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
/* Clock ID for INT2 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
/* Clock ID for INT3 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
/* Clock ID for INT4 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
/* Clock ID for INT5 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
/* Clock ID for INT6 I2S IBIT */
#define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
/* Clock ID for QUINARY MI2S OSR CLK */
#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
/* Clock ID for Primary PCM IBIT */
#define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
/* Clock ID for Primary PCM EBIT */
#define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
/* Clock ID for Secondary PCM IBIT */
#define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
/* Clock ID for Secondary PCM EBIT */
#define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
/* Clock ID for Tertiary PCM IBIT */
#define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
/* Clock ID for Tertiary PCM EBIT */
#define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
/* Clock ID for Quartery PCM IBIT */
#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
/* Clock ID for Quartery PCM EBIT */
#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
/* Clock ID for Quinary PCM IBIT */
#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
/* Clock ID for Quinary PCM EBIT */
#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
/* Clock ID for QUINARY PCM OSR */
#define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
/** Clock ID for Primary TDM IBIT */
#define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
/** Clock ID for Primary TDM EBIT */
#define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
/** Clock ID for Secondary TDM IBIT */
#define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
/** Clock ID for Secondary TDM EBIT */
#define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
/** Clock ID for Tertiary TDM IBIT */
#define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
/** Clock ID for Tertiary TDM EBIT */
#define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
/** Clock ID for Quartery TDM IBIT */
#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
/** Clock ID for Quartery TDM EBIT */
#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
/** Clock ID for Quinary TDM IBIT */
#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
/** Clock ID for Quinary TDM EBIT */
#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
/** Clock ID for Quinary TDM OSR */
#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
/* Clock ID for MCLK1 */
#define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
/* Clock ID for MCLK2 */
#define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
/* Clock ID for MCLK3 */
#define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
/* Clock ID for MCLK4 */
#define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
/* Clock ID for Internal Digital Codec Core */
#define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
/* Clock ID for INT MCLK0 */
#define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
/* Clock ID for INT MCLK1 */
#define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
#define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309
#define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a
#define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
#define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
#define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
#define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
#define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b
#define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310
#define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2
#define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3
#define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4
/* Clock attribute for invalid use (reserved for internal usage) */
#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
/* Clock attribute for no couple case */
#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
/* Clock attribute for dividend couple case */
#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
/* Clock attribute for divisor couple case */
#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
/* Clock attribute for invert and no couple case */
#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
#define Q6AFE_CMAP_INVALID 0xFFFF
struct q6afe_hdmi_cfg {
u16 datatype;
u16 channel_allocation;
u32 sample_rate;
u16 bit_width;
};
struct q6afe_slim_cfg {
u32 sample_rate;
u16 bit_width;
u16 data_format;
u16 num_channels;
u8 ch_mapping[AFE_MAX_CHAN_COUNT];
};
struct q6afe_i2s_cfg {
u32 sample_rate;
u16 bit_width;
u16 data_format;
u16 num_channels;
u32 sd_line_mask;
int fmt;
};
struct q6afe_tdm_cfg {
u16 num_channels;
u32 sample_rate;
u16 bit_width;
u16 data_format;
u16 sync_mode;
u16 sync_src;
u16 nslots_per_frame;
u16 slot_width;
u16 slot_mask;
u32 data_align_type;
u16 ch_mapping[AFE_MAX_CHAN_COUNT];
};
struct q6afe_cdc_dma_cfg {
u16 sample_rate;
u16 bit_width;
u16 data_format;
u16 num_channels;
u16 active_channels_mask;
};
/**
* struct q6afe_usb_cfg
* @cfg_minor_version: Minor version used for tracking USB audio device
* configuration.
* Supported values:
* AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG
* @sample_rate: Sampling rate of the port
* Supported values:
* AFE_PORT_SAMPLE_RATE_8K
* AFE_PORT_SAMPLE_RATE_11025
* AFE_PORT_SAMPLE_RATE_12K
* AFE_PORT_SAMPLE_RATE_16K
* AFE_PORT_SAMPLE_RATE_22050
* AFE_PORT_SAMPLE_RATE_24K
* AFE_PORT_SAMPLE_RATE_32K
* AFE_PORT_SAMPLE_RATE_44P1K
* AFE_PORT_SAMPLE_RATE_48K
* AFE_PORT_SAMPLE_RATE_96K
* AFE_PORT_SAMPLE_RATE_192K
* @bit_width: Bit width of the sample.
* Supported values: 16, 24
* @num_channels: Number of channels
* Supported values: 1, 2
**/
struct q6afe_usb_cfg {
u32 cfg_minor_version;
u32 sample_rate;
u16 bit_width;
u16 num_channels;
};
struct q6afe_port_config {
struct q6afe_hdmi_cfg hdmi;
struct q6afe_slim_cfg slim;
struct q6afe_i2s_cfg i2s_cfg;
struct q6afe_tdm_cfg tdm;
struct q6afe_cdc_dma_cfg dma_cfg;
struct q6afe_usb_cfg usb_audio;
};
struct q6afe_port;
struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);
int q6afe_port_start(struct q6afe_port *port);
int q6afe_port_stop(struct q6afe_port *port);
void q6afe_port_put(struct q6afe_port *port);
int q6afe_get_port_id(int index);
void q6afe_usb_port_prepare(struct q6afe_port *port,
struct q6afe_usb_cfg *cfg);
void q6afe_hdmi_port_prepare(struct q6afe_port *port,
struct q6afe_hdmi_cfg *cfg);
void q6afe_slim_port_prepare(struct q6afe_port *port,
struct q6afe_slim_cfg *cfg);
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
struct q6afe_cdc_dma_cfg *cfg);
int afe_port_send_usb_dev_param(struct q6afe_port *port, int cardidx, int pcmidx);
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
int clk_src, int clk_root,
unsigned int freq, int dir);
int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,
int clk_root, unsigned int freq);
int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle);
int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
uint32_t client_handle);
#endif /* __Q6AFE_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6apm-dai.c
+1061
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linux-7.2.3/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "q6dsp-lpass-ports.h"
#include "q6dsp-common.h"
#include "audioreach.h"
#include "q6apm.h"
#define AUDIOREACH_BE_PCM_BASE 16
struct q6apm_lpass_dai_data {
struct q6apm_graph *graph[APM_PORT_MAX];
bool is_port_started[APM_PORT_MAX];
struct audioreach_module_config module_config[APM_PORT_MAX];
};
static int q6dma_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num,
const unsigned int *tx_ch_mask,
unsigned int rx_num,
const unsigned int *rx_ch_mask)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
int i;
switch (dai->id) {
case WSA_CODEC_DMA_TX_0:
case WSA_CODEC_DMA_TX_1:
case WSA_CODEC_DMA_TX_2:
case VA_CODEC_DMA_TX_0:
case VA_CODEC_DMA_TX_1:
case VA_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
case TX_CODEC_DMA_TX_4:
case TX_CODEC_DMA_TX_5:
if (!tx_ch_mask) {
dev_err(dai->dev, "tx slot not found\n");
return -EINVAL;
}
if (tx_num > AR_PCM_MAX_NUM_CHANNEL) {
dev_err(dai->dev, "invalid tx num %d\n",
tx_num);
return -EINVAL;
}
for (i = 0; i < tx_num; i++)
cfg->channel_map[i] = tx_ch_mask[i];
break;
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_2:
case RX_CODEC_DMA_RX_3:
case RX_CODEC_DMA_RX_4:
case RX_CODEC_DMA_RX_5:
case RX_CODEC_DMA_RX_6:
case RX_CODEC_DMA_RX_7:
/* rx */
if (!rx_ch_mask) {
dev_err(dai->dev, "rx slot not found\n");
return -EINVAL;
}
if (rx_num > APM_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid rx num %d\n",
rx_num);
return -EINVAL;
}
for (i = 0; i < rx_num; i++)
cfg->channel_map[i] = rx_ch_mask[i];
break;
default:
dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
__func__, dai->id);
return -EINVAL;
}
return 0;
}
static int q6hdmi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
int channels = hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS)->max;
int ret;
cfg->bit_width = params_width(params);
cfg->sample_rate = params_rate(params);
cfg->num_channels = channels;
audioreach_set_default_channel_mapping(cfg->channel_map, channels);
switch (dai->id) {
case DISPLAY_PORT_RX_0:
cfg->dp_idx = 0;
break;
case DISPLAY_PORT_RX_1 ... DISPLAY_PORT_RX_7:
cfg->dp_idx = dai->id - DISPLAY_PORT_RX_1 + 1;
break;
}
ret = q6dsp_get_channel_allocation(channels);
if (ret < 0)
return ret;
cfg->channel_allocation = ret;
return 0;
}
static int q6dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
int channels = hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS)->max;
cfg->bit_width = params_width(params);
cfg->sample_rate = params_rate(params);
cfg->num_channels = channels;
audioreach_set_default_channel_mapping(cfg->channel_map, channels);
return 0;
}
static void q6apm_lpass_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc;
if (dai_data->is_port_started[dai->id]) {
rc = q6apm_graph_stop(dai_data->graph[dai->id]);
dai_data->is_port_started[dai->id] = false;
if (rc < 0)
dev_err(dai->dev, "failed to stop APM port (%d)\n", rc);
}
if (dai_data->graph[dai->id]) {
q6apm_graph_close(dai_data->graph[dai->id]);
dai_data->graph[dai->id] = NULL;
}
}
static int q6apm_lpass_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (!dai_data->is_port_started[dai->id]) {
ret = q6apm_graph_start(dai_data->graph[dai->id]);
if (ret < 0)
dev_err(dai->dev, "Failed to start APM port %d\n", dai->id);
else
dai_data->is_port_started[dai->id] = true;
}
break;
default:
break;
}
return ret;
}
static int q6apm_lpass_dai_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
struct q6apm_graph *graph;
int graph_id = dai->id;
int rc;
if (dai_data->is_port_started[dai->id]) {
q6apm_graph_stop(dai_data->graph[dai->id]);
dai_data->is_port_started[dai->id] = false;
}
/**
* It is recommend to load DSP with source graph first and then sink
* graph, so sequence for playback and capture will be different
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && dai_data->graph[dai->id] == NULL) {
graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id, substream->stream);
if (IS_ERR(graph)) {
dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id);
rc = PTR_ERR(graph);
return rc;
}
dai_data->graph[graph_id] = graph;
}
cfg->direction = substream->stream;
rc = q6apm_graph_media_format_pcm(dai_data->graph[dai->id], cfg);
if (rc) {
dev_err(dai->dev, "Failed to set media format %d\n", rc);
goto err;
}
rc = q6apm_graph_prepare(dai_data->graph[dai->id]);
if (rc) {
dev_err(dai->dev, "Failed to prepare Graph %d\n", rc);
goto err;
}
return 0;
err:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
q6apm_graph_close(dai_data->graph[dai->id]);
dai_data->graph[dai->id] = NULL;
}
return rc;
}
static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6apm_graph *graph;
int graph_id = dai->id;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id, substream->stream);
if (IS_ERR(graph)) {
dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id);
return PTR_ERR(graph);
}
dai_data->graph[graph_id] = graph;
}
return 0;
}
static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
cfg->fmt = fmt;
return 0;
}
static const struct snd_soc_dai_ops q6dma_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
.trigger = q6apm_lpass_dai_trigger,
};
static const struct snd_soc_dai_ops q6i2s_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
.set_fmt = q6i2s_set_fmt,
.trigger = q6apm_lpass_dai_trigger,
};
static const struct snd_soc_dai_ops q6hdmi_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.hw_params = q6hdmi_hw_params,
.set_fmt = q6i2s_set_fmt,
.trigger = q6apm_lpass_dai_trigger,
};
static const struct snd_soc_component_driver q6apm_lpass_dai_component = {
.name = "q6apm-be-dai-component",
.of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name,
.be_pcm_base = AUDIOREACH_BE_PCM_BASE,
.use_dai_pcm_id = true,
.remove_order = SND_SOC_COMP_ORDER_FIRST,
};
static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev)
{
struct q6dsp_audio_port_dai_driver_config cfg;
struct q6apm_lpass_dai_data *dai_data;
struct snd_soc_dai_driver *dais;
struct device *dev = &pdev->dev;
int num_dais;
dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL);
if (!dai_data)
return -ENOMEM;
dev_set_drvdata(dev, dai_data);
memset(&cfg, 0, sizeof(cfg));
cfg.q6i2s_ops = &q6i2s_ops;
cfg.q6dma_ops = &q6dma_ops;
cfg.q6hdmi_ops = &q6hdmi_ops;
dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais);
return devm_snd_soc_register_component(dev, &q6apm_lpass_dai_component, dais, num_dais);
}
#ifdef CONFIG_OF
static const struct of_device_id q6apm_lpass_dai_device_id[] = {
{ .compatible = "qcom,q6apm-lpass-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6apm_lpass_dai_device_id);
#endif
static struct platform_driver q6apm_lpass_dai_platform_driver = {
.driver = {
.name = "q6apm-lpass-dais",
.of_match_table = of_match_ptr(q6apm_lpass_dai_device_id),
},
.probe = q6apm_lpass_dai_dev_probe,
};
module_platform_driver(q6apm_lpass_dai_platform_driver);
MODULE_DESCRIPTION("AUDIOREACH APM LPASS dai driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/qdsp6/q6apm.c
+1013
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linux-7.2.3/sound/soc/qcom/qdsp6/q6apm.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6APM_H__
#define __Q6APM_H__
#include <linux/types.h>
#include <linux/atomic.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <sound/soc.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include "../common.h"
#include "audioreach.h"
#define APM_PORT_MAX LPASS_MAX_PORT
#define APM_PORT_MAX_AUDIO_CHAN_CNT 8
#define PCM_CHANNEL_NULL 0
#define PCM_CHANNEL_FL 1 /* Front left channel. */
#define PCM_CHANNEL_FR 2 /* Front right channel. */
#define PCM_CHANNEL_FC 3 /* Front center channel. */
#define PCM_CHANNEL_LS 4 /* Left surround channel. */
#define PCM_CHANNEL_RS 5 /* Right surround channel. */
#define PCM_CHANNEL_LFE 6 /* Low frequency effect channel. */
#define PCM_CHANNEL_CS 7 /* Center surround channel; Rear center ch */
#define PCM_CHANNEL_LB 8 /* Left back channel; Rear left channel. */
#define PCM_CHANNEL_RB 9 /* Right back channel; Rear right channel. */
#define PCM_CHANNELS 10 /* Top surround channel. */
#define APM_TIMESTAMP_FLAG 0x80000000
#define FORMAT_LINEAR_PCM 0x0000
/* APM client callback events */
#define APM_CMD_EOS 0x0003
#define APM_CLIENT_EVENT_CMD_EOS_DONE 0x1003
#define APM_CMD_CLOSE 0x0004
#define APM_CLIENT_EVENT_CMD_CLOSE_DONE 0x1004
#define APM_CLIENT_EVENT_CMD_RUN_DONE 0x1008
#define APM_CLIENT_EVENT_DATA_WRITE_DONE 0x1009
#define APM_CLIENT_EVENT_DATA_READ_DONE 0x100a
#define APM_CLIENT_EVENT_WATERMARK_EVENT 0x100b
#define APM_WRITE_TOKEN_MASK GENMASK(15, 0)
#define APM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16)
#define APM_WRITE_TOKEN_LEN_SHIFT 16
#define APM_MAX_SESSIONS 8
#define APM_LAST_BUFFER_FLAG BIT(30)
#define NO_TIMESTAMP 0xFF00
struct q6apm {
struct device *dev;
gpr_port_t *port;
gpr_device_t *gdev;
/* For Graph OPEN/START/STOP/CLOSE operations */
wait_queue_head_t wait;
struct gpr_ibasic_rsp_result_t result;
struct mutex cmd_lock;
struct mutex lock;
uint32_t state;
struct list_head widget_list;
struct idr graph_idr;
struct idr graph_info_idr;
struct idr sub_graphs_idr;
struct idr containers_idr;
struct idr modules_idr;
};
struct audio_buffer {
phys_addr_t phys;
uint32_t size; /* size of buffer */
};
struct audioreach_graph_data {
struct audio_buffer *buf;
uint32_t num_periods;
uint32_t dsp_buf;
atomic_t hw_ptr;
};
struct audioreach_graph {
struct audioreach_graph_info *info;
uint32_t id;
int state;
int start_count;
/* Cached Graph data */
void *graph;
struct kref refcount;
struct q6apm *apm;
};
typedef void (*q6apm_cb) (uint32_t opcode, uint32_t token,
void *payload, void *priv);
struct q6apm_graph {
void *priv;
q6apm_cb cb;
uint32_t id;
uint32_t shm_iid;
struct device *dev;
struct q6apm *apm;
gpr_port_t *port;
struct audioreach_graph_data rx_data;
struct audioreach_graph_data tx_data;
struct gpr_ibasic_rsp_result_t result;
wait_queue_head_t cmd_wait;
struct mutex lock;
struct audioreach_graph *ar_graph;
struct audioreach_graph_info *info;
};
/* Graph Operations */
struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb,
void *priv, int graph_id, int dir);
int q6apm_graph_close(struct q6apm_graph *graph);
int q6apm_graph_prepare(struct q6apm_graph *graph);
int q6apm_graph_start(struct q6apm_graph *graph);
int q6apm_graph_stop(struct q6apm_graph *graph);
int q6apm_graph_flush(struct q6apm_graph *graph);
/* Media Format */
int q6apm_graph_media_format_pcm(struct q6apm_graph *graph,
struct audioreach_module_config *cfg);
int q6apm_graph_media_format_shmem(struct q6apm_graph *graph,
struct audioreach_module_config *cfg);
/* read/write related */
int q6apm_read(struct q6apm_graph *graph);
int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts,
uint32_t lsw_ts, uint32_t wflags);
/* Memory Map related */
int q6apm_map_memory_fixed_region(struct device *dev,
unsigned int graph_id, phys_addr_t phys,
size_t sz);
int q6apm_map_pos_buffer(struct device *dev,
unsigned int graph_id, phys_addr_t phys,
size_t sz);
int q6apm_unmap_pos_buffer(struct device *dev, unsigned int graph_id);
int q6apm_alloc_fragments(struct q6apm_graph *graph,
unsigned int dir, phys_addr_t phys,
size_t period_sz, unsigned int periods);
int q6apm_free_fragments(struct q6apm_graph *graph, unsigned int dir);
int q6apm_unmap_memory_fixed_region(struct device *dev, unsigned int graph_id);
/* Helpers */
int q6apm_send_cmd_sync(struct q6apm *apm, const struct gpr_pkt *pkt,
uint32_t rsp_opcode);
/* Callback for graph specific */
struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph,
uint32_t mid);
bool q6apm_is_adsp_ready(void);
int q6apm_enable_compress_module(struct device *dev, struct q6apm_graph *graph, bool en);
int q6apm_remove_initial_silence(struct device *dev, struct q6apm_graph *graph, uint32_t samples);
int q6apm_remove_trailing_silence(struct device *dev, struct q6apm_graph *graph, uint32_t samples);
int q6apm_set_real_module_id(struct device *dev, struct q6apm_graph *graph, uint32_t codec_id);
int q6apm_get_hw_pointer(struct q6apm_graph *graph, int dir);
bool q6apm_is_graph_in_push_pull_mode(struct q6apm_graph *graph);
bool q6apm_is_graph_in_push_pull_mode_from_id(struct device *dev, unsigned int graph_id, int dir);
int q6apm_push_pull_config(struct q6apm_graph *graph, phys_addr_t bphys,
phys_addr_t pphys, uint32_t size);
int q6apm_register_watermark_event(struct q6apm_graph *graph, int watermark_bytes, int num_levels);
#endif /* __APM_GRAPH_ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6asm-dai.c
+1345
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File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/qdsp6/q6asm.c
+1687
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File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/qdsp6/q6asm.h
+152
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@@ -0,0 +1,152 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6_ASM_H__
#define __Q6_ASM_H__
#include "q6dsp-common.h"
/* ASM client callback events */
#define CMD_PAUSE 0x0001
#define ASM_CLIENT_EVENT_CMD_PAUSE_DONE 0x1001
#define CMD_FLUSH 0x0002
#define ASM_CLIENT_EVENT_CMD_FLUSH_DONE 0x1002
#define CMD_EOS 0x0003
#define ASM_CLIENT_EVENT_CMD_EOS_DONE 0x1003
#define CMD_CLOSE 0x0004
#define ASM_CLIENT_EVENT_CMD_CLOSE_DONE 0x1004
#define CMD_OUT_FLUSH 0x0005
#define ASM_CLIENT_EVENT_CMD_OUT_FLUSH_DONE 0x1005
#define CMD_SUSPEND 0x0006
#define ASM_CLIENT_EVENT_CMD_SUSPEND_DONE 0x1006
#define ASM_CLIENT_EVENT_CMD_RUN_DONE 0x1008
#define ASM_CLIENT_EVENT_DATA_WRITE_DONE 0x1009
#define ASM_CLIENT_EVENT_DATA_READ_DONE 0x100a
#define ASM_WRITE_TOKEN_MASK GENMASK(15, 0)
#define ASM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16)
#define ASM_WRITE_TOKEN_LEN_SHIFT 16
enum {
LEGACY_PCM_MODE = 0,
LOW_LATENCY_PCM_MODE,
ULTRA_LOW_LATENCY_PCM_MODE,
ULL_POST_PROCESSING_PCM_MODE,
};
#define MAX_SESSIONS 8
#define FORMAT_LINEAR_PCM 0x0000
#define ASM_LAST_BUFFER_FLAG BIT(30)
struct q6asm_flac_cfg {
u32 sample_rate;
u32 ext_sample_rate;
u32 min_frame_size;
u32 max_frame_size;
u16 stream_info_present;
u16 min_blk_size;
u16 max_blk_size;
u16 ch_cfg;
u16 sample_size;
u16 md5_sum;
};
struct q6asm_wma_cfg {
u32 fmtag;
u32 num_channels;
u32 sample_rate;
u32 bytes_per_sec;
u32 block_align;
u32 bits_per_sample;
u32 channel_mask;
u32 enc_options;
u32 adv_enc_options;
u32 adv_enc_options2;
};
struct q6asm_alac_cfg {
u32 frame_length;
u8 compatible_version;
u8 bit_depth;
u8 pb;
u8 mb;
u8 kb;
u8 num_channels;
u16 max_run;
u32 max_frame_bytes;
u32 avg_bit_rate;
u32 sample_rate;
u32 channel_layout_tag;
};
struct q6asm_ape_cfg {
u16 compatible_version;
u16 compression_level;
u32 format_flags;
u32 blocks_per_frame;
u32 final_frame_blocks;
u32 total_frames;
u16 bits_per_sample;
u16 num_channels;
u32 sample_rate;
u32 seek_table_present;
};
typedef void (*q6asm_cb) (uint32_t opcode, uint32_t token,
void *payload, void *priv);
struct audio_client;
struct audio_client *q6asm_audio_client_alloc(struct device *dev,
q6asm_cb cb, void *priv,
int session_id, int perf_mode);
void q6asm_audio_client_free(struct audio_client *ac);
int q6asm_write_async(struct audio_client *ac, uint32_t stream_id, uint32_t len,
uint32_t msw_ts, uint32_t lsw_ts, uint32_t wflags);
int q6asm_open_write(struct audio_client *ac, uint32_t stream_id,
uint32_t format, u32 codec_profile,
uint16_t bits_per_sample, bool is_gapless);
int q6asm_open_read(struct audio_client *ac, uint32_t stream_id,
uint32_t format, uint16_t bits_per_sample);
int q6asm_enc_cfg_blk_pcm_format_support(struct audio_client *ac,
uint32_t stream_id, uint32_t rate,
uint32_t channels,
uint16_t bits_per_sample);
int q6asm_read(struct audio_client *ac, uint32_t stream_id);
int q6asm_media_format_block_multi_ch_pcm(struct audio_client *ac,
uint32_t stream_id,
uint32_t rate, uint32_t channels,
u8 channel_map[PCM_MAX_NUM_CHANNEL],
uint16_t bits_per_sample);
int q6asm_stream_media_format_block_flac(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_flac_cfg *cfg);
int q6asm_stream_media_format_block_wma_v9(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_wma_cfg *cfg);
int q6asm_stream_media_format_block_wma_v10(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_wma_cfg *cfg);
int q6asm_stream_media_format_block_alac(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_alac_cfg *cfg);
int q6asm_stream_media_format_block_ape(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_ape_cfg *cfg);
int q6asm_run(struct audio_client *ac, uint32_t stream_id, uint32_t flags,
uint32_t msw_ts, uint32_t lsw_ts);
int q6asm_run_nowait(struct audio_client *ac, uint32_t stream_id,
uint32_t flags, uint32_t msw_ts, uint32_t lsw_ts);
int q6asm_stream_remove_initial_silence(struct audio_client *ac,
uint32_t stream_id,
uint32_t initial_samples);
int q6asm_stream_remove_trailing_silence(struct audio_client *ac,
uint32_t stream_id,
uint32_t trailing_samples);
int q6asm_cmd(struct audio_client *ac, uint32_t stream_id, int cmd);
int q6asm_cmd_nowait(struct audio_client *ac, uint32_t stream_id, int cmd);
int q6asm_get_session_id(struct audio_client *c);
int q6asm_map_memory_regions(unsigned int dir,
struct audio_client *ac,
phys_addr_t phys,
size_t period_sz, unsigned int periods);
int q6asm_unmap_memory_regions(unsigned int dir, struct audio_client *ac);
int q6asm_get_hw_pointer(struct audio_client *ac, unsigned int dir);
#endif /* __Q6_ASM_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6core.c
+375
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@@ -0,0 +1,375 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include "q6core.h"
#include "q6dsp-errno.h"
#define ADSP_STATE_READY_TIMEOUT_MS 3000
#define Q6_READY_TIMEOUT_MS 100
#define AVCS_CMD_ADSP_EVENT_GET_STATE 0x0001290C
#define AVCS_CMDRSP_ADSP_EVENT_GET_STATE 0x0001290D
#define AVCS_GET_VERSIONS 0x00012905
#define AVCS_GET_VERSIONS_RSP 0x00012906
#define AVCS_CMD_GET_FWK_VERSION 0x001292c
#define AVCS_CMDRSP_GET_FWK_VERSION 0x001292d
struct avcs_svc_info {
uint32_t service_id;
uint32_t version;
} __packed;
struct avcs_cmdrsp_get_version {
uint32_t build_id;
uint32_t num_services;
struct avcs_svc_info svc_api_info[];
} __packed;
/* for ADSP2.8 and above */
struct avcs_svc_api_info {
uint32_t service_id;
uint32_t api_version;
uint32_t api_branch_version;
} __packed;
struct avcs_cmdrsp_get_fwk_version {
uint32_t build_major_version;
uint32_t build_minor_version;
uint32_t build_branch_version;
uint32_t build_subbranch_version;
uint32_t num_services;
struct avcs_svc_api_info svc_api_info[];
} __packed;
struct q6core {
struct apr_device *adev;
wait_queue_head_t wait;
uint32_t avcs_state;
struct mutex lock;
bool resp_received;
uint32_t num_services;
struct avcs_cmdrsp_get_fwk_version *fwk_version;
struct avcs_cmdrsp_get_version *svc_version;
bool fwk_version_supported;
bool get_state_supported;
bool get_version_supported;
bool is_version_requested;
};
static struct q6core *g_core;
static int q6core_callback(struct apr_device *adev, const struct apr_resp_pkt *data)
{
struct q6core *core = dev_get_drvdata(&adev->dev);
const struct aprv2_ibasic_rsp_result_t *result;
const struct apr_hdr *hdr = &data->hdr;
result = data->payload;
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT:{
result = data->payload;
switch (result->opcode) {
case AVCS_GET_VERSIONS:
if (result->status == ADSP_EUNSUPPORTED)
core->get_version_supported = false;
core->resp_received = true;
break;
case AVCS_CMD_GET_FWK_VERSION:
if (result->status == ADSP_EUNSUPPORTED)
core->fwk_version_supported = false;
core->resp_received = true;
break;
case AVCS_CMD_ADSP_EVENT_GET_STATE:
if (result->status == ADSP_EUNSUPPORTED)
core->get_state_supported = false;
core->resp_received = true;
break;
}
break;
}
case AVCS_CMDRSP_GET_FWK_VERSION: {
struct avcs_cmdrsp_get_fwk_version *fwk;
fwk = data->payload;
core->fwk_version = kmemdup(data->payload,
struct_size(fwk, svc_api_info,
fwk->num_services),
GFP_ATOMIC);
if (!core->fwk_version)
return -ENOMEM;
core->fwk_version_supported = true;
core->resp_received = true;
break;
}
case AVCS_GET_VERSIONS_RSP: {
struct avcs_cmdrsp_get_version *v;
v = data->payload;
core->svc_version = kmemdup(data->payload,
struct_size(v, svc_api_info,
v->num_services),
GFP_ATOMIC);
if (!core->svc_version)
return -ENOMEM;
core->get_version_supported = true;
core->resp_received = true;
break;
}
case AVCS_CMDRSP_ADSP_EVENT_GET_STATE:
core->get_state_supported = true;
core->avcs_state = result->opcode;
core->resp_received = true;
break;
default:
dev_err(&adev->dev, "Message id from adsp core svc: 0x%x\n",
hdr->opcode);
break;
}
if (core->resp_received)
wake_up(&core->wait);
return 0;
}
static int q6core_get_fwk_versions(struct q6core *core)
{
struct apr_device *adev = core->adev;
struct apr_pkt pkt;
int rc;
pkt.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
pkt.hdr.pkt_size = APR_HDR_SIZE;
pkt.hdr.opcode = AVCS_CMD_GET_FWK_VERSION;
rc = apr_send_pkt(adev, &pkt);
if (rc < 0)
return rc;
rc = wait_event_timeout(core->wait, (core->resp_received),
msecs_to_jiffies(Q6_READY_TIMEOUT_MS));
if (rc > 0 && core->resp_received) {
core->resp_received = false;
if (!core->fwk_version_supported)
return -ENOTSUPP;
else
return 0;
}
return rc;
}
static int q6core_get_svc_versions(struct q6core *core)
{
struct apr_device *adev = core->adev;
struct apr_pkt pkt;
int rc;
pkt.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
pkt.hdr.pkt_size = APR_HDR_SIZE;
pkt.hdr.opcode = AVCS_GET_VERSIONS;
rc = apr_send_pkt(adev, &pkt);
if (rc < 0)
return rc;
rc = wait_event_timeout(core->wait, (core->resp_received),
msecs_to_jiffies(Q6_READY_TIMEOUT_MS));
if (rc > 0 && core->resp_received) {
core->resp_received = false;
return 0;
}
return rc;
}
static bool __q6core_is_adsp_ready(struct q6core *core)
{
struct apr_device *adev = core->adev;
struct apr_pkt pkt;
int rc;
core->get_state_supported = false;
pkt.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
pkt.hdr.pkt_size = APR_HDR_SIZE;
pkt.hdr.opcode = AVCS_CMD_ADSP_EVENT_GET_STATE;
rc = apr_send_pkt(adev, &pkt);
if (rc < 0)
return false;
rc = wait_event_timeout(core->wait, (core->resp_received),
msecs_to_jiffies(Q6_READY_TIMEOUT_MS));
if (rc > 0 && core->resp_received) {
core->resp_received = false;
if (core->avcs_state)
return true;
}
/* assume that the adsp is up if we not support this command */
if (!core->get_state_supported)
return true;
return false;
}
/**
* q6core_get_svc_api_info() - Get version number of a service.
*
* @svc_id: service id of the service.
* @ainfo: Valid struct pointer to fill svc api information.
*
* Return: zero on success and error code on failure or unsupported
*/
int q6core_get_svc_api_info(int svc_id, struct q6core_svc_api_info *ainfo)
{
int i;
int ret = -ENOTSUPP;
if (!g_core || !ainfo)
return 0;
mutex_lock(&g_core->lock);
if (!g_core->is_version_requested) {
if (q6core_get_fwk_versions(g_core) == -ENOTSUPP)
q6core_get_svc_versions(g_core);
g_core->is_version_requested = true;
}
if (g_core->fwk_version_supported) {
for (i = 0; i < g_core->fwk_version->num_services; i++) {
struct avcs_svc_api_info *info;
info = &g_core->fwk_version->svc_api_info[i];
if (svc_id != info->service_id)
continue;
ainfo->api_version = info->api_version;
ainfo->api_branch_version = info->api_branch_version;
ret = 0;
break;
}
} else if (g_core->get_version_supported) {
for (i = 0; i < g_core->svc_version->num_services; i++) {
struct avcs_svc_info *info;
info = &g_core->svc_version->svc_api_info[i];
if (svc_id != info->service_id)
continue;
ainfo->api_version = info->version;
ainfo->api_branch_version = 0;
ret = 0;
break;
}
}
mutex_unlock(&g_core->lock);
return ret;
}
EXPORT_SYMBOL_GPL(q6core_get_svc_api_info);
/**
* q6core_is_adsp_ready() - Get status of adsp
*
* Return: Will be an true if adsp is ready and false if not.
*/
bool q6core_is_adsp_ready(void)
{
unsigned long timeout;
bool ret = false;
if (!g_core)
return false;
mutex_lock(&g_core->lock);
timeout = jiffies + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
for (;;) {
if (__q6core_is_adsp_ready(g_core)) {
ret = true;
break;
}
if (!time_after(timeout, jiffies)) {
ret = false;
break;
}
}
mutex_unlock(&g_core->lock);
return ret;
}
EXPORT_SYMBOL_GPL(q6core_is_adsp_ready);
static int q6core_probe(struct apr_device *adev)
{
g_core = kzalloc_obj(*g_core);
if (!g_core)
return -ENOMEM;
dev_set_drvdata(&adev->dev, g_core);
mutex_init(&g_core->lock);
g_core->adev = adev;
init_waitqueue_head(&g_core->wait);
return 0;
}
static void q6core_exit(struct apr_device *adev)
{
struct q6core *core = dev_get_drvdata(&adev->dev);
if (core->fwk_version_supported)
kfree(core->fwk_version);
if (core->get_version_supported)
kfree(core->svc_version);
g_core = NULL;
kfree(core);
}
#ifdef CONFIG_OF
static const struct of_device_id q6core_device_id[] = {
{ .compatible = "qcom,q6core" },
{},
};
MODULE_DEVICE_TABLE(of, q6core_device_id);
#endif
static struct apr_driver qcom_q6core_driver = {
.probe = q6core_probe,
.remove = q6core_exit,
.callback = q6core_callback,
.driver = {
.name = "qcom-q6core",
.of_match_table = of_match_ptr(q6core_device_id),
},
};
module_apr_driver(qcom_q6core_driver);
MODULE_DESCRIPTION("q6 core");
MODULE_LICENSE("GPL v2");
linux-7.2.3/sound/soc/qcom/qdsp6/q6core.h
+15
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@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6CORE_H__
#define __Q6CORE_H__
struct q6core_svc_api_info {
uint32_t service_id;
uint32_t api_version;
uint32_t api_branch_version;
};
bool q6core_is_adsp_ready(void);
int q6core_get_svc_api_info(int svc_id, struct q6core_svc_api_info *ainfo);
#endif /* __Q6CORE_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-common.c
+103
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@@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include "q6dsp-common.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/errno.h>
int q6dsp_map_channels(u8 ch_map[PCM_MAX_NUM_CHANNEL], int ch)
{
memset(ch_map, 0, PCM_MAX_NUM_CHANNEL);
switch (ch) {
case 1:
ch_map[0] = PCM_CHANNEL_FC;
break;
case 2:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
break;
case 3:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_FC;
break;
case 4:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_LS;
ch_map[3] = PCM_CHANNEL_RS;
break;
case 5:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_FC;
ch_map[3] = PCM_CHANNEL_LS;
ch_map[4] = PCM_CHANNEL_RS;
break;
case 6:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_LFE;
ch_map[3] = PCM_CHANNEL_FC;
ch_map[4] = PCM_CHANNEL_LS;
ch_map[5] = PCM_CHANNEL_RS;
break;
case 8:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_LFE;
ch_map[3] = PCM_CHANNEL_FC;
ch_map[4] = PCM_CHANNEL_LS;
ch_map[5] = PCM_CHANNEL_RS;
ch_map[6] = PCM_CHANNEL_LB;
ch_map[7] = PCM_CHANNEL_RB;
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(q6dsp_map_channels);
int q6dsp_get_channel_allocation(int channels)
{
int channel_allocation;
/* HDMI spec CEA-861-E: Table 28 Audio InfoFrame Data Byte 4 */
switch (channels) {
case 2:
channel_allocation = 0;
break;
case 3:
channel_allocation = 0x02;
break;
case 4:
channel_allocation = 0x06;
break;
case 5:
channel_allocation = 0x0A;
break;
case 6:
channel_allocation = 0x0B;
break;
case 7:
channel_allocation = 0x12;
break;
case 8:
channel_allocation = 0x13;
break;
default:
return -EINVAL;
}
return channel_allocation;
}
EXPORT_SYMBOL_GPL(q6dsp_get_channel_allocation);
MODULE_DESCRIPTION("ASoC MSM QDSP6 helper functions");
MODULE_LICENSE("GPL v2");
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-common.h
+25
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6DSP_COMMON_H__
#define __Q6DSP_COMMON_H__
#include <linux/kernel.h>
#define PCM_MAX_NUM_CHANNEL 8
#define PCM_CHANNEL_NULL 0
#define PCM_CHANNEL_FL 1 /* Front left channel. */
#define PCM_CHANNEL_FR 2 /* Front right channel. */
#define PCM_CHANNEL_FC 3 /* Front center channel. */
#define PCM_CHANNEL_LS 4 /* Left surround channel. */
#define PCM_CHANNEL_RS 5 /* Right surround channel. */
#define PCM_CHANNEL_LFE 6 /* Low frequency effect channel. */
#define PCM_CHANNEL_CS 7 /* Center surround channel; Rear center ch */
#define PCM_CHANNEL_LB 8 /* Left back channel; Rear left channel. */
#define PCM_CHANNEL_RB 9 /* Right back channel; Rear right channel. */
#define PCM_CHANNELS 10 /* Top surround channel. */
int q6dsp_map_channels(u8 ch_map[PCM_MAX_NUM_CHANNEL], int ch);
int q6dsp_get_channel_allocation(int channels);
#endif /* __Q6DSP_COMMON_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-errno.h
+51
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@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6DSP_ERR_NO_H__
#define __Q6DSP_ERR_NO_H__
#include <linux/kernel.h>
/* Success. The operation completed with no errors. */
#define ADSP_EOK 0x00000000
/* General failure. */
#define ADSP_EFAILED 0x00000001
/* Bad operation parameter. */
#define ADSP_EBADPARAM 0x00000002
/* Unsupported routine or operation. */
#define ADSP_EUNSUPPORTED 0x00000003
/* Unsupported version. */
#define ADSP_EVERSION 0x00000004
/* Unexpected problem encountered. */
#define ADSP_EUNEXPECTED 0x00000005
/* Unhandled problem occurred. */
#define ADSP_EPANIC 0x00000006
/* Unable to allocate resource. */
#define ADSP_ENORESOURCE 0x00000007
/* Invalid handle. */
#define ADSP_EHANDLE 0x00000008
/* Operation is already processed. */
#define ADSP_EALREADY 0x00000009
/* Operation is not ready to be processed. */
#define ADSP_ENOTREADY 0x0000000A
/* Operation is pending completion. */
#define ADSP_EPENDING 0x0000000B
/* Operation could not be accepted or processed. */
#define ADSP_EBUSY 0x0000000C
/* Operation aborted due to an error. */
#define ADSP_EABORTED 0x0000000D
/* Operation preempted by a higher priority. */
#define ADSP_EPREEMPTED 0x0000000E
/* Operation requests intervention to complete. */
#define ADSP_ECONTINUE 0x0000000F
/* Operation requests immediate intervention to complete. */
#define ADSP_EIMMEDIATE 0x00000010
/* Operation is not implemented. */
#define ADSP_ENOTIMPL 0x00000011
/* Operation needs more data or resources. */
#define ADSP_ENEEDMORE 0x00000012
/* Operation does not have memory. */
#define ADSP_ENOMEMORY 0x00000014
/* Item does not exist. */
#define ADSP_ENOTEXIST 0x00000015
/* Max count for adsp error code sent to HLOS*/
#endif /*__Q6DSP_ERR_NO_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c
+185
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6dsp-lpass-clocks.h"
#define Q6DSP_MAX_CLK_ID 104
#define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0
struct q6dsp_clk {
struct device *dev;
int q6dsp_clk_id;
int attributes;
int rate;
uint32_t handle;
struct clk_hw hw;
};
#define to_q6dsp_clk(_hw) container_of(_hw, struct q6dsp_clk, hw)
struct q6dsp_cc {
struct device *dev;
struct q6dsp_clk *clks[Q6DSP_MAX_CLK_ID];
const struct q6dsp_clk_desc *desc;
};
static int clk_q6dsp_prepare(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
return cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
Q6DSP_LPASS_CLK_ROOT_DEFAULT, clk->rate);
}
static void clk_q6dsp_unprepare(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
Q6DSP_LPASS_CLK_ROOT_DEFAULT, 0);
}
static int clk_q6dsp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
clk->rate = rate;
return 0;
}
static unsigned long clk_q6dsp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
return clk->rate;
}
static int clk_q6dsp_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
return 0;
}
static const struct clk_ops clk_q6dsp_ops = {
.prepare = clk_q6dsp_prepare,
.unprepare = clk_q6dsp_unprepare,
.set_rate = clk_q6dsp_set_rate,
.determine_rate = clk_q6dsp_determine_rate,
.recalc_rate = clk_q6dsp_recalc_rate,
};
static int clk_vote_q6dsp_block(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
return cc->desc->lpass_vote_clk(clk->dev, clk->q6dsp_clk_id,
clk_hw_get_name(&clk->hw), &clk->handle);
}
static void clk_unvote_q6dsp_block(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
cc->desc->lpass_unvote_clk(clk->dev, clk->q6dsp_clk_id, clk->handle);
}
static const struct clk_ops clk_vote_q6dsp_ops = {
.prepare = clk_vote_q6dsp_block,
.unprepare = clk_unvote_q6dsp_block,
};
static struct clk_hw *q6dsp_of_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct q6dsp_cc *cc = data;
unsigned int idx = clkspec->args[0];
unsigned int attr = clkspec->args[1];
if (idx >= Q6DSP_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
return ERR_PTR(-EINVAL);
}
if (cc->clks[idx]) {
cc->clks[idx]->attributes = attr;
return &cc->clks[idx]->hw;
}
return ERR_PTR(-ENOENT);
}
int q6dsp_clock_dev_probe(struct platform_device *pdev)
{
struct q6dsp_cc *cc;
struct device *dev = &pdev->dev;
const struct q6dsp_clk_init *q6dsp_clks;
const struct q6dsp_clk_desc *desc;
int i, ret;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
cc->desc = desc;
cc->dev = dev;
q6dsp_clks = desc->clks;
for (i = 0; i < desc->num_clks; i++) {
unsigned int id = q6dsp_clks[i].clk_id;
struct clk_init_data init = {
.name = q6dsp_clks[i].name,
};
struct q6dsp_clk *clk;
clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
clk->dev = dev;
clk->q6dsp_clk_id = q6dsp_clks[i].q6dsp_clk_id;
clk->rate = q6dsp_clks[i].rate;
clk->hw.init = &init;
if (clk->rate)
init.ops = &clk_q6dsp_ops;
else
init.ops = &clk_vote_q6dsp_ops;
cc->clks[id] = clk;
ret = devm_clk_hw_register(dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(dev, q6dsp_of_clk_hw_get, cc);
if (ret)
return ret;
dev_set_drvdata(dev, cc);
return 0;
}
EXPORT_SYMBOL_GPL(q6dsp_clock_dev_probe);
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6DSP_AUDIO_CLOCKS_H__
#define __Q6DSP_AUDIO_CLOCKS_H__
struct q6dsp_clk_init {
int clk_id;
int q6dsp_clk_id;
char *name;
int rate;
};
#define Q6DSP_VOTE_CLK(id, blkid, n) { \
.clk_id = id, \
.q6dsp_clk_id = blkid, \
.name = n, \
}
struct q6dsp_clk_desc {
const struct q6dsp_clk_init *clks;
size_t num_clks;
int (*lpass_set_clk)(struct device *dev, int clk_id, int attr,
int root_clk, unsigned int freq);
int (*lpass_vote_clk)(struct device *dev, uint32_t hid, const char *n, uint32_t *h);
int (*lpass_unvote_clk)(struct device *dev, uint32_t hid, uint32_t h);
};
int q6dsp_clock_dev_probe(struct platform_device *pdev);
#endif /* __Q6DSP_AUDIO_CLOCKS_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "q6dsp-lpass-ports.h"
#define Q6AFE_TDM_PB_DAI(pre, num, did) { \
.playback = { \
.stream_name = pre" TDM"#num" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \
.capture = { \
.stream_name = pre" TDM"#num" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_CDC_DMA_RX_DAI(did) { \
.playback = { \
.stream_name = #did" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_CDC_DMA_TX_DAI(did) { \
.capture = { \
.stream_name = #did" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_DP_RX_DAI(did) { \
.playback = { \
.stream_name = #did" Playback", \
.rates = SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE, \
.channels_min = 2, \
.channels_max = 8, \
.rate_min = 48000, \
.rate_max = 192000, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_MI2S_RX_DAI(pre, did) { \
.playback = { \
.stream_name = pre" MI2S Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_MI2S_TX_DAI(pre, did) { \
.capture = { \
.stream_name = pre" MI2S Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = {
{
.playback = {
.stream_name = "USB Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |
SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.id = USB_RX,
.name = "USB_RX",
},
{
.playback = {
.stream_name = "HDMI Playback",
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 8,
.rate_max = 192000,
.rate_min = 48000,
},
.id = HDMI_RX,
.name = "HDMI",
}, {
.name = "SLIMBUS_0_RX",
.id = SLIMBUS_0_RX,
.playback = {
.stream_name = "Slimbus Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.name = "SLIMBUS_0_TX",
.id = SLIMBUS_0_TX,
.capture = {
.stream_name = "Slimbus Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus1 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_1_RX",
.id = SLIMBUS_1_RX,
}, {
.name = "SLIMBUS_1_TX",
.id = SLIMBUS_1_TX,
.capture = {
.stream_name = "Slimbus1 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus2 Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_2_RX",
.id = SLIMBUS_2_RX,
}, {
.name = "SLIMBUS_2_TX",
.id = SLIMBUS_2_TX,
.capture = {
.stream_name = "Slimbus2 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus3 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_3_RX",
.id = SLIMBUS_3_RX,
}, {
.name = "SLIMBUS_3_TX",
.id = SLIMBUS_3_TX,
.capture = {
.stream_name = "Slimbus3 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus4 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_4_RX",
.id = SLIMBUS_4_RX,
}, {
.name = "SLIMBUS_4_TX",
.id = SLIMBUS_4_TX,
.capture = {
.stream_name = "Slimbus4 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus5 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_5_RX",
.id = SLIMBUS_5_RX,
}, {
.name = "SLIMBUS_5_TX",
.id = SLIMBUS_5_TX,
.capture = {
.stream_name = "Slimbus5 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus6 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_6_RX",
.id = SLIMBUS_6_RX,
}, {
.name = "SLIMBUS_6_TX",
.id = SLIMBUS_6_TX,
.capture = {
.stream_name = "Slimbus6 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Primary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_RX,
.name = "PRI_MI2S_RX",
}, {
.capture = {
.stream_name = "Primary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_TX,
.name = "PRI_MI2S_TX",
}, {
.playback = {
.stream_name = "Secondary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "SEC_MI2S_RX",
.id = SECONDARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Secondary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = SECONDARY_MI2S_TX,
.name = "SEC_MI2S_TX",
}, {
.playback = {
.stream_name = "Tertiary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "TERT_MI2S_RX",
.id = TERTIARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Tertiary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = TERTIARY_MI2S_TX,
.name = "TERT_MI2S_TX",
}, {
.playback = {
.stream_name = "Quaternary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "QUAT_MI2S_RX",
.id = QUATERNARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Quaternary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUATERNARY_MI2S_TX,
.name = "QUAT_MI2S_TX",
}, {
.playback = {
.stream_name = "Quinary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.id = QUINARY_MI2S_RX,
.name = "QUIN_MI2S_RX",
}, {
.capture = {
.stream_name = "Quinary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUINARY_MI2S_TX,
.name = "QUIN_MI2S_TX",
}, {
.playback = {
.stream_name = "Senary MI2S Playback",
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.id = SENARY_MI2S_RX,
.name = "SEN_MI2S_RX",
}, {
.capture = {
.stream_name = "Senary MI2S Capture",
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.id = SENARY_MI2S_TX,
.name = "SEN_MI2S_TX",
},
Q6AFE_MI2S_RX_DAI("LPI RX0", LPI_MI2S_RX_0),
Q6AFE_MI2S_RX_DAI("LPI RX1", LPI_MI2S_RX_1),
Q6AFE_MI2S_RX_DAI("LPI RX2", LPI_MI2S_RX_2),
Q6AFE_MI2S_RX_DAI("LPI RX3", LPI_MI2S_RX_3),
Q6AFE_MI2S_RX_DAI("LPI RX4", LPI_MI2S_RX_4),
Q6AFE_MI2S_TX_DAI("LPI TX0", LPI_MI2S_TX_0),
Q6AFE_MI2S_TX_DAI("LPI TX1", LPI_MI2S_TX_1),
Q6AFE_MI2S_TX_DAI("LPI TX2", LPI_MI2S_TX_2),
Q6AFE_MI2S_TX_DAI("LPI TX3", LPI_MI2S_TX_3),
Q6AFE_MI2S_TX_DAI("LPI TX4", LPI_MI2S_TX_4),
Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_0),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_1),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_2),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_3),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_4),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_5),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_6),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_7),
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_2),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_3),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_3),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_4),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_4),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_5),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_5),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_6),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_7),
};
int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
int id = args->args[0];
int ret = -EINVAL;
int i;
for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) {
if (q6dsp_audio_fe_dais[i].id == id) {
*dai_name = q6dsp_audio_fe_dais[i].name;
ret = 0;
break;
}
}
return ret;
}
EXPORT_SYMBOL_GPL(q6dsp_audio_ports_of_xlate_dai_name);
struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev,
struct q6dsp_audio_port_dai_driver_config *cfg,
int *num_dais)
{
int i;
for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) {
switch (q6dsp_audio_fe_dais[i].id) {
case HDMI_RX:
case DISPLAY_PORT_RX:
q6dsp_audio_fe_dais[i].ops = cfg->q6hdmi_ops;
break;
case DISPLAY_PORT_RX_1 ... DISPLAY_PORT_RX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6hdmi_ops;
break;
case SLIMBUS_0_RX ... SLIMBUS_6_TX:
q6dsp_audio_fe_dais[i].ops = cfg->q6slim_ops;
break;
case SENARY_MI2S_RX ... SENARY_MI2S_TX:
case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4:
q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops;
break;
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6tdm_ops;
break;
case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6dma_ops;
break;
case USB_RX:
q6dsp_audio_fe_dais[i].ops = cfg->q6usb_ops;
break;
default:
break;
}
}
*num_dais = ARRAY_SIZE(q6dsp_audio_fe_dais);
return q6dsp_audio_fe_dais;
}
EXPORT_SYMBOL_GPL(q6dsp_audio_ports_set_config);
linux-7.2.3/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h
+23
View File
@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6DSP_AUDIO_PORTS_H__
#define __Q6DSP_AUDIO_PORTS_H__
struct q6dsp_audio_port_dai_driver_config {
int (*probe)(struct snd_soc_dai *dai);
int (*remove)(struct snd_soc_dai *dai);
const struct snd_soc_dai_ops *q6hdmi_ops;
const struct snd_soc_dai_ops *q6slim_ops;
const struct snd_soc_dai_ops *q6i2s_ops;
const struct snd_soc_dai_ops *q6tdm_ops;
const struct snd_soc_dai_ops *q6dma_ops;
const struct snd_soc_dai_ops *q6usb_ops;
};
struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev,
struct q6dsp_audio_port_dai_driver_config *cfg,
int *num_dais);
int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name);
#endif /* __Q6DSP_AUDIO_PORTS_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6prm-clocks.c
+94
View File
@@ -0,0 +1,94 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include "q6dsp-lpass-clocks.h"
#include "q6prm.h"
#define Q6PRM_CLK(id) { \
.clk_id = id, \
.q6dsp_clk_id = Q6PRM_##id, \
.name = #id, \
.rate = 19200000, \
}
static const struct q6dsp_clk_init q6prm_clks[] = {
Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
"LPASS_HW_DCODEC"),
};
static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused = {
.clks = q6prm_clks,
.num_clks = ARRAY_SIZE(q6prm_clks),
.lpass_set_clk = q6prm_set_lpass_clock,
.lpass_vote_clk = q6prm_vote_lpass_core_hw,
.lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
};
#ifdef CONFIG_OF
static const struct of_device_id q6prm_clock_device_id[] = {
{ .compatible = "qcom,q6prm-lpass-clocks", .data = &q6dsp_clk_q6prm },
{},
};
MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
#endif
static struct platform_driver q6prm_clock_platform_driver = {
.driver = {
.name = "q6prm-lpass-clock",
.of_match_table = of_match_ptr(q6prm_clock_device_id),
},
.probe = q6dsp_clock_dev_probe,
};
module_platform_driver(q6prm_clock_platform_driver);
MODULE_DESCRIPTION("Q6 Proxy Resource Manager LPASS clock driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/qdsp6/q6prm.c
+240
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@@ -0,0 +1,240 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6apm.h"
#include "q6prm.h"
#include "audioreach.h"
struct q6prm {
struct device *dev;
gpr_device_t *gdev;
wait_queue_head_t wait;
struct gpr_ibasic_rsp_result_t result;
struct mutex lock;
};
#define PRM_CMD_REQUEST_HW_RSC 0x0100100F
#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002
#define PRM_CMD_RELEASE_HW_RSC 0x01001010
#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003
#define PARAM_ID_RSC_HW_CORE 0x08001032
#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
struct prm_cmd_request_hw_core {
struct apm_module_param_data param_data;
uint32_t hw_clk_id;
} __packed;
struct prm_cmd_request_rsc {
struct apm_module_param_data param_data;
uint32_t num_clk_id;
struct audio_hw_clk_cfg clock_id;
} __packed;
struct prm_cmd_release_rsc {
struct apm_module_param_data param_data;
uint32_t num_clk_id;
struct audio_hw_clk_rel_cfg clock_id;
} __packed;
static int q6prm_send_cmd_sync(struct q6prm *prm, struct gpr_pkt *pkt, uint32_t rsp_opcode)
{
return audioreach_send_cmd_sync(prm->dev, prm->gdev, &prm->result, &prm->lock,
NULL, &prm->wait, pkt, rsp_opcode);
}
static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_request_hw_core *req;
gpr_device_t *gdev = prm->gdev;
uint32_t opcode, rsp_opcode;
if (enable) {
opcode = PRM_CMD_REQUEST_HW_RSC;
rsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC;
} else {
opcode = PRM_CMD_RELEASE_HW_RSC;
rsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC;
}
struct gpr_pkt *pkt __free(kfree) =
audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->svc.id, GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &req->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_HW_CORE;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->hw_clk_id = hw_block_id;
return q6prm_send_cmd_sync(prm, pkt, rsp_opcode);
}
int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle)
{
return q6prm_set_hw_core_req(dev, hw_block_id, true);
}
EXPORT_SYMBOL_GPL(q6prm_vote_lpass_core_hw);
int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle)
{
return q6prm_set_hw_core_req(dev, hw_block_id, false);
}
EXPORT_SYMBOL_GPL(q6prm_unvote_lpass_core_hw);
static int q6prm_request_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_request_rsc *req;
gpr_device_t *gdev = prm->gdev;
struct gpr_pkt *pkt __free(kfree) =
audioreach_alloc_cmd_pkt(sizeof(*req), PRM_CMD_REQUEST_HW_RSC, 0,
gdev->svc.id, GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &req->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->num_clk_id = 1;
req->clock_id.clock_id = clk_id;
req->clock_id.clock_freq = freq;
req->clock_id.clock_attri = clk_attr;
req->clock_id.clock_root = clk_root;
return q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_REQUEST_HW_RSC);
}
static int q6prm_release_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_release_rsc *rel;
gpr_device_t *gdev = prm->gdev;
struct gpr_pkt *pkt __free(kfree) =
audioreach_alloc_cmd_pkt(sizeof(*rel), PRM_CMD_RELEASE_HW_RSC, 0,
gdev->svc.id, GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
rel = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &rel->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
param_data->param_size = sizeof(*rel) - APM_MODULE_PARAM_DATA_SIZE;
rel->num_clk_id = 1;
rel->clock_id.clock_id = clk_id;
return q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_RELEASE_HW_RSC);
}
int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
if (freq)
return q6prm_request_lpass_clock(dev, clk_id, clk_attr, clk_root, freq);
return q6prm_release_lpass_clock(dev, clk_id, clk_attr, clk_root, freq);
}
EXPORT_SYMBOL_GPL(q6prm_set_lpass_clock);
static int prm_callback(const struct gpr_resp_pkt *data, void *priv, int op)
{
gpr_device_t *gdev = priv;
struct q6prm *prm = dev_get_drvdata(&gdev->dev);
const struct gpr_ibasic_rsp_result_t *result;
const struct gpr_hdr *hdr = &data->hdr;
switch (hdr->opcode) {
case PRM_CMD_RSP_REQUEST_HW_RSC:
case PRM_CMD_RSP_RELEASE_HW_RSC:
result = data->payload;
prm->result.opcode = hdr->opcode;
prm->result.status = result->status;
wake_up(&prm->wait);
break;
default:
break;
}
return 0;
}
static int prm_probe(gpr_device_t *gdev)
{
struct device *dev = &gdev->dev;
struct q6prm *cc;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
cc->dev = dev;
cc->gdev = gdev;
mutex_init(&cc->lock);
init_waitqueue_head(&cc->wait);
dev_set_drvdata(dev, cc);
if (!q6apm_is_adsp_ready())
return -EPROBE_DEFER;
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id prm_device_id[] = {
{ .compatible = "qcom,q6prm" },
{},
};
MODULE_DEVICE_TABLE(of, prm_device_id);
#endif
static gpr_driver_t prm_driver = {
.probe = prm_probe,
.gpr_callback = prm_callback,
.driver = {
.name = "qcom-prm",
.of_match_table = of_match_ptr(prm_device_id),
},
};
module_gpr_driver(prm_driver);
MODULE_DESCRIPTION("Q6 Proxy Resource Manager");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/qdsp6/q6prm.h
+97
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@@ -0,0 +1,97 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6PRM_H__
#define __Q6PRM_H__
/* Clock ID for Primary I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
/* Clock ID for Primary I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
/* Clock ID for Secondary I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
/* Clock ID for Secondary I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
/* Clock ID for Tertiary I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
/* Clock ID for Tertiary I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
/* Clock ID for Quartnery I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
/* Clock ID for Quartnery I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
/* Clock ID for Speaker I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
/* Clock ID for Speaker I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
/* Clock ID for Speaker I2S OSR */
#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
/* Clock ID for QUINARY I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
/* Clock ID for QUINARY I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
/* Clock ID for SENARY I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
/* Clock ID for SENARY I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
/* Clock ID for INT0 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
/* Clock ID for INT1 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
/* Clock ID for INT2 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
/* Clock ID for INT3 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
/* Clock ID for INT4 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
/* Clock ID for INT5 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
/* Clock ID for INT6 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
/* Clock ID for QUINARY MI2S OSR CLK */
#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307
#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308
#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
/* Clock ID for MCLK for WSA2 core */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310
/* Clock ID for NPL MCLK for WSA2 core */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311
/* Clock ID for RX Core TX MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312
/* Clock ID for RX CORE TX 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313
/* Clock ID for WSA core TX MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314
/* Clock ID for WSA core TX 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315
/* Clock ID for WSA2 core TX MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316
/* Clock ID for WSA2 core TX 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317
/* Clock ID for RX CORE MCLK2 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318
#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
#define Q6PRM_HW_CORE_ID_LPASS 1
#define Q6PRM_HW_CORE_ID_DCODEC 2
int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
int clk_root, unsigned int freq);
int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle);
int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
uint32_t client_handle);
#endif /* __Q6PRM_H__ */
linux-7.2.3/sound/soc/qcom/qdsp6/q6routing.c
+1174
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File diff suppressed because it is too large Load Diff
linux-7.2.3/sound/soc/qcom/qdsp6/q6routing.h
+9
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@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _Q6_PCM_ROUTING_H
#define _Q6_PCM_ROUTING_H
int q6routing_stream_open(int fedai_id, int perf_mode,
int stream_id, int stream_type);
void q6routing_stream_close(int fedai_id, int stream_type);
#endif /*_Q6_PCM_ROUTING_H */
linux-7.2.3/sound/soc/qcom/qdsp6/q6usb.c
+422
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@@ -0,0 +1,422 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/auxiliary_bus.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dma-map-ops.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/asound.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/q6usboffload.h>
#include <sound/soc.h>
#include <sound/soc-usb.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "q6afe.h"
#include "q6dsp-lpass-ports.h"
#define Q6_USB_SID_MASK 0xF
struct q6usb_port_data {
struct auxiliary_device uauxdev;
struct q6afe_usb_cfg usb_cfg;
struct snd_soc_usb *usb;
struct snd_soc_jack *hs_jack;
struct q6usb_offload priv;
/* Protects against operations between SOC USB and ASoC */
struct mutex mutex;
struct list_head devices;
};
static const struct snd_soc_dapm_widget q6usb_dai_widgets[] = {
SND_SOC_DAPM_HP("USB_RX_BE", NULL),
};
static const struct snd_soc_dapm_route q6usb_dapm_routes[] = {
{"USB Playback", NULL, "USB_RX_BE"},
};
static int q6usb_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct q6usb_port_data *data = dev_get_drvdata(dai->dev);
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
int direction = substream->stream;
struct q6afe_port *q6usb_afe;
struct snd_soc_usb_device *sdev;
int ret = -EINVAL;
mutex_lock(&data->mutex);
/* No active chip index */
if (list_empty(&data->devices))
goto out;
sdev = list_last_entry(&data->devices, struct snd_soc_usb_device, list);
ret = snd_soc_usb_find_supported_format(sdev->chip_idx, params, direction);
if (ret < 0)
goto out;
q6usb_afe = q6afe_port_get_from_id(cpu_dai->dev, USB_RX);
if (IS_ERR(q6usb_afe)) {
ret = PTR_ERR(q6usb_afe);
goto out;
}
/* Notify audio DSP about the devices being offloaded */
ret = afe_port_send_usb_dev_param(q6usb_afe, sdev->card_idx,
sdev->ppcm_idx[sdev->num_playback - 1]);
out:
mutex_unlock(&data->mutex);
return ret;
}
static const struct snd_soc_dai_ops q6usb_ops = {
.hw_params = q6usb_hw_params,
};
static struct snd_soc_dai_driver q6usb_be_dais[] = {
{
.playback = {
.stream_name = "USB BE RX",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |
SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE,
.channels_min = 1,
.channels_max = 2,
.rate_max = 192000,
.rate_min = 8000,
},
.id = USB_RX,
.name = "USB_RX_BE",
.ops = &q6usb_ops,
},
};
static int q6usb_audio_ports_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
int id = args->args[0];
int ret = -EINVAL;
int i;
for (i = 0; i < ARRAY_SIZE(q6usb_be_dais); i++) {
if (q6usb_be_dais[i].id == id) {
*dai_name = q6usb_be_dais[i].name;
ret = 0;
break;
}
}
return ret;
}
static int q6usb_get_pcm_id_from_widget(struct snd_soc_dapm_widget *w)
{
struct snd_soc_card *card = snd_soc_dapm_to_card(w->dapm);
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *dai;
for_each_card_rtds(card, rtd) {
dai = snd_soc_rtd_to_cpu(rtd, 0);
/*
* Only look for playback widget. RTD number carries the assigned
* PCM index.
*/
if (dai->stream[0].widget == w)
return rtd->id;
}
return -1;
}
static int q6usb_usb_mixer_enabled(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dapm_path *p;
/* Checks to ensure USB path is enabled/connected */
snd_soc_dapm_widget_for_each_sink_path(w, p)
if (!strcmp(p->sink->name, "USB Mixer") && p->connect)
return 1;
return 0;
}
static int q6usb_get_pcm_id(struct snd_soc_component *component)
{
struct snd_soc_dapm_widget *w;
struct snd_soc_dapm_path *p;
int pidx;
/*
* Traverse widgets to find corresponding FE widget. The DAI links are
* built like the following:
* MultiMedia* <-> MM_DL* <-> USB Mixer*
*/
for_each_card_widgets(component->card, w) {
if (!strncmp(w->name, "MultiMedia", 10)) {
/*
* Look up all paths associated with the FE widget to see if
* the USB BE is enabled. The sink widget is responsible to
* link with the USB mixers.
*/
snd_soc_dapm_widget_for_each_sink_path(w, p) {
if (q6usb_usb_mixer_enabled(p->sink)) {
pidx = q6usb_get_pcm_id_from_widget(w);
return pidx;
}
}
}
}
return -1;
}
static int q6usb_update_offload_route(struct snd_soc_component *component, int card,
int pcm, int direction, enum snd_soc_usb_kctl path,
long *route)
{
struct q6usb_port_data *data = dev_get_drvdata(component->dev);
struct snd_soc_usb_device *sdev;
int ret = 0;
int idx = -1;
mutex_lock(&data->mutex);
if (list_empty(&data->devices) ||
direction == SNDRV_PCM_STREAM_CAPTURE) {
ret = -ENODEV;
goto out;
}
sdev = list_last_entry(&data->devices, struct snd_soc_usb_device, list);
/*
* Will always look for last PCM device discovered/probed as the
* active offload index.
*/
if (card == sdev->card_idx &&
pcm == sdev->ppcm_idx[sdev->num_playback - 1]) {
idx = path == SND_SOC_USB_KCTL_CARD_ROUTE ?
component->card->snd_card->number :
q6usb_get_pcm_id(component);
}
out:
route[0] = idx;
mutex_unlock(&data->mutex);
return ret;
}
static int q6usb_alsa_connection_cb(struct snd_soc_usb *usb,
struct snd_soc_usb_device *sdev, bool connected)
{
struct q6usb_port_data *data;
if (!usb->component)
return -ENODEV;
data = dev_get_drvdata(usb->component->dev);
mutex_lock(&data->mutex);
if (connected) {
if (data->hs_jack)
snd_jack_report(data->hs_jack->jack, SND_JACK_USB);
/* Selects the latest USB headset plugged in for offloading */
list_add_tail(&sdev->list, &data->devices);
} else {
list_del(&sdev->list);
if (data->hs_jack)
snd_jack_report(data->hs_jack->jack, 0);
}
mutex_unlock(&data->mutex);
return 0;
}
static void q6usb_component_disable_jack(struct q6usb_port_data *data)
{
/* Offload jack has already been disabled */
if (!data->hs_jack)
return;
snd_jack_report(data->hs_jack->jack, 0);
data->hs_jack = NULL;
}
static void q6usb_component_enable_jack(struct q6usb_port_data *data,
struct snd_soc_jack *jack)
{
snd_jack_report(jack->jack, !list_empty(&data->devices) ? SND_JACK_USB : 0);
data->hs_jack = jack;
}
static int q6usb_component_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *priv)
{
struct q6usb_port_data *data = dev_get_drvdata(component->dev);
mutex_lock(&data->mutex);
if (jack)
q6usb_component_enable_jack(data, jack);
else
q6usb_component_disable_jack(data);
mutex_unlock(&data->mutex);
return 0;
}
static void q6usb_dai_aux_release(struct device *dev) {}
static int q6usb_dai_add_aux_device(struct q6usb_port_data *data,
struct auxiliary_device *auxdev)
{
int ret;
auxdev->dev.parent = data->priv.dev;
auxdev->dev.release = q6usb_dai_aux_release;
auxdev->name = "qc-usb-audio-offload";
ret = auxiliary_device_init(auxdev);
if (ret)
return ret;
ret = auxiliary_device_add(auxdev);
if (ret)
auxiliary_device_uninit(auxdev);
return ret;
}
static int q6usb_component_probe(struct snd_soc_component *component)
{
struct q6usb_port_data *data = dev_get_drvdata(component->dev);
struct snd_soc_usb *usb;
int ret;
/* Add the QC USB SND aux device */
ret = q6usb_dai_add_aux_device(data, &data->uauxdev);
if (ret < 0)
return ret;
usb = snd_soc_usb_allocate_port(component, &data->priv);
if (IS_ERR(usb))
return -ENOMEM;
usb->connection_status_cb = q6usb_alsa_connection_cb;
usb->update_offload_route_info = q6usb_update_offload_route;
snd_soc_usb_add_port(usb);
data->usb = usb;
return 0;
}
static void q6usb_component_remove(struct snd_soc_component *component)
{
struct q6usb_port_data *data = dev_get_drvdata(component->dev);
snd_soc_usb_remove_port(data->usb);
auxiliary_device_delete(&data->uauxdev);
auxiliary_device_uninit(&data->uauxdev);
snd_soc_usb_free_port(data->usb);
}
static const struct snd_soc_component_driver q6usb_dai_component = {
.probe = q6usb_component_probe,
.set_jack = q6usb_component_set_jack,
.remove = q6usb_component_remove,
.name = "q6usb-dai-component",
.dapm_widgets = q6usb_dai_widgets,
.num_dapm_widgets = ARRAY_SIZE(q6usb_dai_widgets),
.dapm_routes = q6usb_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(q6usb_dapm_routes),
.of_xlate_dai_name = q6usb_audio_ports_of_xlate_dai_name,
};
static int q6usb_dai_dev_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct q6usb_port_data *data;
struct device *dev = &pdev->dev;
struct of_phandle_args args;
int ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
ret = of_property_read_u16(node, "qcom,usb-audio-intr-idx",
&data->priv.intr_num);
if (ret) {
dev_err(&pdev->dev, "failed to read intr idx.\n");
return ret;
}
ret = of_parse_phandle_with_fixed_args(node, "iommus", 1, 0, &args);
if (!ret)
data->priv.sid = args.args[0] & Q6_USB_SID_MASK;
ret = devm_mutex_init(dev, &data->mutex);
if (ret < 0)
return ret;
data->priv.domain = iommu_get_domain_for_dev(&pdev->dev);
data->priv.dev = dev;
INIT_LIST_HEAD(&data->devices);
dev_set_drvdata(dev, data);
return devm_snd_soc_register_component(dev, &q6usb_dai_component,
q6usb_be_dais, ARRAY_SIZE(q6usb_be_dais));
}
static const struct of_device_id q6usb_dai_device_id[] = {
{ .compatible = "qcom,q6usb" },
{},
};
MODULE_DEVICE_TABLE(of, q6usb_dai_device_id);
static struct platform_driver q6usb_dai_platform_driver = {
.driver = {
.name = "q6usb-dai",
.of_match_table = q6usb_dai_device_id,
},
.probe = q6usb_dai_dev_probe,
/*
* Remove not required as resources are cleaned up as part of
* component removal. Others are device managed resources.
*/
};
module_platform_driver(q6usb_dai_platform_driver);
MODULE_DESCRIPTION("Q6 USB backend dai driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/qdsp6/topology.c
+1342
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linux-7.2.3/sound/soc/qcom/sc7180.c
+582
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@@ -0,0 +1,582 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2020, The Linux Foundation. All rights reserved.
//
// sc7180.c -- ALSA SoC Machine driver for SC7180
#include <dt-bindings/sound/sc7180-lpass.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <uapi/linux/input-event-codes.h>
#include "../codecs/rt5682.h"
#include "../codecs/rt5682s.h"
#include "common.h"
#include "qdsp6/q6afe.h"
#define DEFAULT_MCLK_RATE 19200000
#define MI2S_BCLK_RATE 1536000
#define RT5682_PLL1_FREQ (48000 * 512)
#define DRIVER_NAME "SC7180"
struct sc7180_snd_data {
struct snd_soc_card card;
u32 pri_mi2s_clk_count;
struct snd_soc_jack hs_jack;
struct snd_soc_jack hdmi_jack;
struct gpio_desc *dmic_sel;
int dmic_switch;
};
static void sc7180_jack_free(struct snd_jack *jack)
{
struct snd_soc_component *component = jack->private_data;
snd_soc_component_set_jack(component, NULL, NULL);
}
static struct snd_soc_jack_pin sc7180_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int sc7180_headset_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval;
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_HEADPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&pdata->hs_jack,
sc7180_jack_pins,
ARRAY_SIZE(sc7180_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headset Jack\n");
return rval;
}
jack = pdata->hs_jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
jack->private_data = component;
jack->private_free = sc7180_jack_free;
return snd_soc_component_set_jack(component, &pdata->hs_jack, NULL);
}
static int sc7180_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval;
rval = snd_soc_card_jack_new(
card, "HDMI Jack",
SND_JACK_LINEOUT,
&pdata->hdmi_jack);
if (rval < 0) {
dev_err(card->dev, "Unable to add HDMI Jack\n");
return rval;
}
jack = pdata->hdmi_jack.jack;
jack->private_data = component;
jack->private_free = sc7180_jack_free;
return snd_soc_component_set_jack(component, &pdata->hdmi_jack, NULL);
}
static int sc7180_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
return sc7180_headset_init(rtd);
case MI2S_SECONDARY:
return 0;
case LPASS_DP_RX:
return sc7180_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_qdsp_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
return sc7180_headset_init(rtd);
case PRIMARY_MI2S_TX:
case TERTIARY_MI2S_RX:
return 0;
case DISPLAY_PORT_RX:
return sc7180_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_startup_realtek_codec(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int pll_id, pll_source, pll_in, pll_out, clk_id, ret;
if (!strcmp(codec_dai->name, "rt5682-aif1")) {
pll_source = RT5682_PLL1_S_MCLK;
pll_id = 0;
clk_id = RT5682_SCLK_S_PLL1;
pll_out = RT5682_PLL1_FREQ;
pll_in = DEFAULT_MCLK_RATE;
} else if (!strcmp(codec_dai->name, "rt5682s-aif1")) {
pll_source = RT5682S_PLL_S_MCLK;
pll_id = RT5682S_PLL2;
clk_id = RT5682S_SCLK_S_PLL2;
pll_out = RT5682_PLL1_FREQ;
pll_in = DEFAULT_MCLK_RATE;
} else {
return 0;
}
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_BC_FC |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
/* Configure PLL1 for codec */
ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source,
pll_in, pll_out);
if (ret) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
/* Configure sysclk for codec */
ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, pll_out,
SND_SOC_CLOCK_IN);
if (ret)
dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n",
ret);
return ret;
}
static int sc7180_snd_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
int ret;
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (++data->pri_mi2s_clk_count == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
}
ret = sc7180_startup_realtek_codec(rtd);
if (ret)
return ret;
break;
case MI2S_SECONDARY:
break;
case LPASS_DP_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_qdsp_snd_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int ret;
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
if (++data->pri_mi2s_clk_count == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_MCLK_1,
DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
MI2S_BCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
}
snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
ret = sc7180_startup_realtek_codec(rtd);
if (ret)
return ret;
break;
case TERTIARY_MI2S_RX:
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
MI2S_BCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_BC_FC |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
break;
case DISPLAY_PORT_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
struct snd_soc_card *card = snd_soc_dapm_to_card(dapm);
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
ucontrol->value.integer.value[0] = data->dmic_switch;
return 0;
}
static int dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
struct snd_soc_card *card = snd_soc_dapm_to_card(dapm);
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
data->dmic_switch = ucontrol->value.integer.value[0];
gpiod_set_value(data->dmic_sel, data->dmic_switch);
return 0;
}
static void sc7180_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (--data->pri_mi2s_clk_count == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
0,
SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case MI2S_SECONDARY:
break;
case LPASS_DP_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
break;
}
}
static void sc7180_qdsp_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
if (--data->pri_mi2s_clk_count == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_MCLK_1,
0,
SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
0,
SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case TERTIARY_MI2S_RX:
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
0,
SNDRV_PCM_STREAM_PLAYBACK);
break;
case DISPLAY_PORT_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
break;
}
}
static int sc7180_adau7002_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
return 0;
case MI2S_SECONDARY:
return 0;
case LPASS_DP_RX:
return sc7180_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_adau7002_snd_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_pcm_runtime *runtime = substream->runtime;
switch (cpu_dai->id) {
case MI2S_PRIMARY:
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_CBC_CFC |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE;
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 32);
break;
case MI2S_SECONDARY:
break;
case LPASS_DP_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_qdsp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
return 0;
}
static const struct snd_soc_ops sc7180_ops = {
.startup = sc7180_snd_startup,
.shutdown = sc7180_snd_shutdown,
};
static const struct snd_soc_ops sc7180_qdsp_ops = {
.startup = sc7180_qdsp_snd_startup,
.shutdown = sc7180_qdsp_snd_shutdown,
};
static const struct snd_soc_ops sc7180_adau7002_ops = {
.startup = sc7180_adau7002_snd_startup,
};
static const struct snd_soc_dapm_widget sc7180_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_kcontrol_new sc7180_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget sc7180_adau7002_snd_widgets[] = {
SND_SOC_DAPM_MIC("DMIC", NULL),
};
static const char * const dmic_mux_text[] = {
"Front Mic",
"Rear Mic",
};
static SOC_ENUM_SINGLE_DECL(sc7180_dmic_enum,
SND_SOC_NOPM, 0, dmic_mux_text);
static const struct snd_kcontrol_new sc7180_dmic_mux_control =
SOC_DAPM_ENUM_EXT("DMIC Select Mux", sc7180_dmic_enum,
dmic_get, dmic_set);
static const struct snd_soc_dapm_widget sc7180_snd_dual_mic_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("DMIC", NULL),
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0, &sc7180_dmic_mux_control),
};
static const struct snd_kcontrol_new sc7180_snd_dual_mic_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_route sc7180_snd_dual_mic_audio_route[] = {
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
};
static int sc7180_snd_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sc7180_snd_data *data;
struct device *dev = &pdev->dev;
struct snd_soc_dai_link *link;
int ret;
int i;
bool qdsp = false, no_headphone = false;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card = &data->card;
snd_soc_card_set_drvdata(card, data);
card->owner = THIS_MODULE;
card->driver_name = DRIVER_NAME;
card->dev = dev;
card->dapm_widgets = sc7180_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_snd_widgets);
card->controls = sc7180_snd_controls;
card->num_controls = ARRAY_SIZE(sc7180_snd_controls);
if (of_property_present(dev->of_node, "dmic-gpios")) {
card->dapm_widgets = sc7180_snd_dual_mic_widgets,
card->num_dapm_widgets = ARRAY_SIZE(sc7180_snd_dual_mic_widgets),
card->controls = sc7180_snd_dual_mic_controls,
card->num_controls = ARRAY_SIZE(sc7180_snd_dual_mic_controls),
card->dapm_routes = sc7180_snd_dual_mic_audio_route,
card->num_dapm_routes = ARRAY_SIZE(sc7180_snd_dual_mic_audio_route),
data->dmic_sel = devm_gpiod_get(&pdev->dev, "dmic", GPIOD_OUT_LOW);
if (IS_ERR(data->dmic_sel)) {
dev_err(&pdev->dev, "DMIC gpio failed err=%ld\n", PTR_ERR(data->dmic_sel));
return PTR_ERR(data->dmic_sel);
}
}
if (of_device_is_compatible(dev->of_node, "google,sc7180-coachz")) {
no_headphone = true;
card->dapm_widgets = sc7180_adau7002_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_adau7002_snd_widgets);
} else if (of_device_is_compatible(dev->of_node, "qcom,sc7180-qdsp6-sndcard")) {
qdsp = true;
}
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
for_each_card_prelinks(card, i, link) {
if (no_headphone) {
link->ops = &sc7180_adau7002_ops;
link->init = sc7180_adau7002_init;
} else if (qdsp) {
if (link->no_pcm == 1) {
link->ops = &sc7180_qdsp_ops;
link->be_hw_params_fixup = sc7180_qdsp_be_hw_params_fixup;
link->init = sc7180_qdsp_init;
}
} else {
link->ops = &sc7180_ops;
link->init = sc7180_init;
}
}
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id sc7180_snd_device_id[] = {
{.compatible = "google,sc7180-trogdor"},
{.compatible = "google,sc7180-coachz"},
{.compatible = "qcom,sc7180-qdsp6-sndcard"},
{},
};
MODULE_DEVICE_TABLE(of, sc7180_snd_device_id);
static struct platform_driver sc7180_snd_driver = {
.probe = sc7180_snd_platform_probe,
.driver = {
.name = "msm-snd-sc7180",
.of_match_table = sc7180_snd_device_id,
.pm = &snd_soc_pm_ops,
},
};
module_platform_driver(sc7180_snd_driver);
MODULE_DESCRIPTION("sc7180 ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/sc7280.c
+399
View File
@@ -0,0 +1,399 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
//
// ALSA SoC Machine driver for sc7280
#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/rt5682s.h>
#include <linux/soundwire/sdw.h>
#include <sound/pcm_params.h>
#include "../codecs/rt5682.h"
#include "../codecs/rt5682s.h"
#include "common.h"
#include "lpass.h"
#include "qdsp6/q6afe.h"
#include "sdw.h"
#define DEFAULT_MCLK_RATE 19200000
#define RT5682_PLL_FREQ (48000 * 512)
#define MI2S_BCLK_RATE 1536000
struct sc7280_snd_data {
struct snd_soc_card card;
u32 pri_mi2s_clk_count;
struct snd_soc_jack hs_jack;
struct snd_soc_jack hdmi_jack;
bool jack_setup;
bool stream_prepared[LPASS_MAX_PORTS];
};
static void sc7280_jack_free(struct snd_jack *jack)
{
struct snd_soc_component *component = jack->private_data;
snd_soc_component_set_jack(component, NULL, NULL);
}
static struct snd_soc_jack_pin sc7280_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int sc7280_headset_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval, i;
if (!pdata->jack_setup) {
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_MECHANICAL |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4 | SND_JACK_BTN_5,
&pdata->hs_jack,
sc7280_jack_pins,
ARRAY_SIZE(sc7280_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headset Jack\n");
return rval;
}
jack = pdata->hs_jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
jack->private_data = component;
jack->private_free = sc7280_jack_free;
pdata->jack_setup = true;
}
switch (cpu_dai->id) {
case MI2S_PRIMARY:
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX3:
case TX_CODEC_DMA_TX_3:
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_component_set_jack(component, &pdata->hs_jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_err(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
break;
default:
break;
}
return 0;
}
static int sc7280_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval;
rval = snd_soc_card_jack_new(card, "HDMI Jack", SND_JACK_LINEOUT,
&pdata->hdmi_jack);
if (rval < 0) {
dev_err(card->dev, "Unable to add HDMI Jack\n");
return rval;
}
jack = pdata->hdmi_jack.jack;
jack->private_data = component;
jack->private_free = sc7280_jack_free;
return snd_soc_component_set_jack(component, &pdata->hdmi_jack, NULL);
}
static int sc7280_rt5682_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(card);
int ret;
if (++data->pri_mi2s_clk_count == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
}
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_CBC_CFC |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
DEFAULT_MCLK_RATE, RT5682_PLL_FREQ);
if (ret) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL2,
RT5682_PLL_FREQ,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n",
ret);
return ret;
}
return 0;
}
static int sc7280_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
case LPASS_CDC_DMA_TX3:
case TX_CODEC_DMA_TX_3:
return sc7280_headset_init(rtd);
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_VA_TX0:
case MI2S_SECONDARY:
case RX_CODEC_DMA_RX_0:
case SECONDARY_MI2S_RX:
case VA_CODEC_DMA_TX_0:
return 0;
case LPASS_DP_RX:
return sc7280_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
}
return -EINVAL;
}
static int sc7280_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
if (!rtd->dai_link->no_pcm) {
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_CHANNELS, 2, 2);
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_RATE, 48000, 48000);
}
return 0;
}
static int sc7280_snd_swr_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
const struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]);
}
static int sc7280_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
const struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX3:
case RX_CODEC_DMA_RX_0:
case TX_CODEC_DMA_TX_3:
case VA_CODEC_DMA_TX_0:
return sc7280_snd_swr_prepare(substream);
default:
break;
}
return 0;
}
static int sc7280_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
const struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return qcom_snd_sdw_hw_free(substream, &data->stream_prepared[cpu_dai->id]);
}
static void sc7280_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (--data->pri_mi2s_clk_count == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
0,
SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case SECONDARY_MI2S_RX:
snd_soc_dai_set_sysclk(cpu_dai, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
0, SNDRV_PCM_STREAM_PLAYBACK);
break;
default:
break;
}
qcom_snd_sdw_shutdown(substream);
}
static int sc7280_snd_startup(struct snd_pcm_substream *substream)
{
unsigned int fmt = SND_SOC_DAIFMT_CBC_CFC;
unsigned int codec_dai_fmt = SND_SOC_DAIFMT_CBC_CFC;
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int ret = 0;
switch (cpu_dai->id) {
case MI2S_PRIMARY:
ret = sc7280_rt5682_init(rtd);
if (ret)
return ret;
break;
case SECONDARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
default:
break;
}
return qcom_snd_sdw_startup(substream);
}
static const struct snd_soc_ops sc7280_ops = {
.startup = sc7280_snd_startup,
.hw_params = sc7280_snd_hw_params,
.hw_free = sc7280_snd_hw_free,
.prepare = sc7280_snd_prepare,
.shutdown = sc7280_snd_shutdown,
};
static const struct snd_soc_dapm_widget sc7280_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_kcontrol_new sc7280_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static int sc7280_snd_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static int sc7280_snd_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sc7280_snd_data *data;
struct device *dev = &pdev->dev;
struct snd_soc_dai_link *link;
int ret, i;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card = &data->card;
snd_soc_card_set_drvdata(card, data);
card->owner = THIS_MODULE;
card->driver_name = "SC7280";
card->dev = dev;
card->dapm_widgets = sc7280_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7280_snd_widgets);
card->controls = sc7280_snd_controls;
card->num_controls = ARRAY_SIZE(sc7280_snd_controls);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
for_each_card_prelinks(card, i, link) {
link->init = sc7280_init;
link->ops = &sc7280_ops;
if (link->no_pcm == 1)
link->be_hw_params_fixup = sc7280_snd_be_hw_params_fixup;
}
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id sc7280_snd_device_id[] = {
{ .compatible = "google,sc7280-herobrine" },
{}
};
MODULE_DEVICE_TABLE(of, sc7280_snd_device_id);
static struct platform_driver sc7280_snd_driver = {
.probe = sc7280_snd_platform_probe,
.driver = {
.name = "msm-snd-sc7280",
.of_match_table = sc7280_snd_device_id,
.pm = &snd_soc_pm_ops,
},
};
module_platform_driver(sc7280_snd_driver);
MODULE_DESCRIPTION("sc7280 ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/sc8280xp.c
+195
View File
@@ -0,0 +1,195 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, Linaro Limited
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/soundwire/sdw.h>
#include <sound/jack.h>
#include <linux/input-event-codes.h>
#include "qdsp6/q6afe.h"
#include "common.h"
#include "sdw.h"
struct sc8280xp_snd_data {
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
struct snd_soc_jack jack;
struct snd_soc_jack dp_jack[8];
bool jack_setup;
};
static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
{
struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct snd_soc_jack *dp_jack = NULL;
int dp_pcm_id = 0;
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
break;
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
/*
* Set limit of -3 dB on Digital Volume and 0 dB on PA Volume
* to reduce the risk of speaker damage until we have active
* speaker protection in place.
*/
snd_soc_limit_volume(card, "WSA_RX0 Digital Volume", 81);
snd_soc_limit_volume(card, "WSA_RX1 Digital Volume", 81);
snd_soc_limit_volume(card, "SpkrLeft PA Volume", 17);
snd_soc_limit_volume(card, "SpkrRight PA Volume", 17);
break;
case DISPLAY_PORT_RX_0:
/* DISPLAY_PORT dai ids are not contiguous */
dp_pcm_id = 0;
dp_jack = &data->dp_jack[dp_pcm_id];
break;
case DISPLAY_PORT_RX_1 ... DISPLAY_PORT_RX_7:
dp_pcm_id = cpu_dai->id - DISPLAY_PORT_RX_1 + 1;
dp_jack = &data->dp_jack[dp_pcm_id];
break;
default:
break;
}
if (dp_jack)
return qcom_snd_dp_jack_setup(rtd, dp_jack, dp_pcm_id);
return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
}
static int sc8280xp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = 48000;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
channels->min = 2;
channels->max = 2;
switch (cpu_dai->id) {
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
channels->min = 1;
break;
default:
break;
}
return 0;
}
static int sc8280xp_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]);
}
static int sc8280xp_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return qcom_snd_sdw_hw_free(substream, &data->stream_prepared[cpu_dai->id]);
}
static const struct snd_soc_ops sc8280xp_be_ops = {
.startup = qcom_snd_sdw_startup,
.shutdown = qcom_snd_sdw_shutdown,
.hw_free = sc8280xp_snd_hw_free,
.prepare = sc8280xp_snd_prepare,
};
static void sc8280xp_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->init = sc8280xp_snd_init;
link->be_hw_params_fixup = sc8280xp_be_hw_params_fixup;
link->ops = &sc8280xp_be_ops;
}
}
}
static int sc8280xp_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sc8280xp_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->owner = THIS_MODULE;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->dev = dev;
dev_set_drvdata(dev, card);
snd_soc_card_set_drvdata(card, data);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
card->driver_name = of_device_get_match_data(dev);
sc8280xp_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id snd_sc8280xp_dt_match[] = {
{.compatible = "qcom,eliza-sndcard", "eliza"},
{.compatible = "qcom,kaanapali-sndcard", "kaanapali"},
{.compatible = "qcom,qcm6490-idp-sndcard", "qcm6490"},
{.compatible = "qcom,qcs615-sndcard", "qcs615"},
{.compatible = "qcom,qcs6490-rb3gen2-sndcard", "qcs6490"},
{.compatible = "qcom,qcs8275-sndcard", "qcs8300"},
{.compatible = "qcom,qcs9075-sndcard", "sa8775p"},
{.compatible = "qcom,qcs9100-sndcard", "sa8775p"},
{.compatible = "qcom,sc8280xp-sndcard", "sc8280xp"},
{.compatible = "qcom,sm8450-sndcard", "sm8450"},
{.compatible = "qcom,sm8550-sndcard", "sm8550"},
{.compatible = "qcom,sm8650-sndcard", "sm8650"},
{.compatible = "qcom,sm8750-sndcard", "sm8750"},
{}
};
MODULE_DEVICE_TABLE(of, snd_sc8280xp_dt_match);
static struct platform_driver snd_sc8280xp_driver = {
.probe = sc8280xp_platform_probe,
.driver = {
.name = "snd-sc8280xp",
.of_match_table = snd_sc8280xp_dt_match,
},
};
module_platform_driver(snd_sc8280xp_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org");
MODULE_DESCRIPTION("SC8280XP ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/sdm845.c
+593
View File
@@ -0,0 +1,593 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <linux/soundwire/sdw.h>
#include <uapi/linux/input-event-codes.h>
#include "common.h"
#include "qdsp6/q6afe.h"
#include "sdw.h"
#include "../codecs/rt5663.h"
#define DRIVER_NAME "sdm845"
#define DEFAULT_SAMPLE_RATE_48K 48000
#define DEFAULT_MCLK_RATE 24576000
#define TDM_BCLK_RATE 6144000
#define MI2S_BCLK_RATE 1536000
#define LEFT_SPK_TDM_TX_MASK 0x30
#define RIGHT_SPK_TDM_TX_MASK 0xC0
#define SPK_TDM_RX_MASK 0x03
#define NUM_TDM_SLOTS 8
#define SLIM_MAX_TX_PORTS 16
#define SLIM_MAX_RX_PORTS 13
#define WCD934X_DEFAULT_MCLK_RATE 9600000
struct sdm845_snd_data {
struct snd_soc_jack jack;
bool jack_setup;
bool slim_port_setup;
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
uint32_t pri_mi2s_clk_count;
uint32_t sec_mi2s_clk_count;
uint32_t quat_tdm_clk_count;
};
static struct snd_soc_jack_pin sdm845_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static unsigned int tdm_slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
static int sdm845_slim_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai;
u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
int ret = 0, i;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
if (ret != 0 && ret != -ENOTSUPP) {
pr_err("failed to get codec chan map, err:%d\n", ret);
return ret;
} else if (ret == -ENOTSUPP) {
/* Ignore unsupported */
continue;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
rx_ch_cnt, rx_ch);
else
ret = snd_soc_dai_set_channel_map(cpu_dai, tx_ch_cnt,
tx_ch, 0, NULL);
if (ret != 0 && ret != -ENOTSUPP) {
dev_err(rtd->dev, "failed to set cpu chan map, err:%d\n", ret);
return ret;
}
}
return 0;
}
static int sdm845_tdm_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai;
int ret = 0, j;
int channels, slot_width;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
slot_width = 16;
break;
default:
dev_err(rtd->dev, "%s: invalid param format 0x%x\n",
__func__, params_format(params));
return -EINVAL;
}
channels = params_channels(params);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0x3,
8, slot_width);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set tdm slot, err:%d\n",
__func__, ret);
goto end;
}
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
channels, tdm_slot_offset);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set channel map, err:%d\n",
__func__, ret);
goto end;
}
} else {
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xf, 0,
8, slot_width);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set tdm slot, err:%d\n",
__func__, ret);
goto end;
}
ret = snd_soc_dai_set_channel_map(cpu_dai, channels,
tdm_slot_offset, 0, NULL);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set channel map, err:%d\n",
__func__, ret);
goto end;
}
}
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name_prefix, "Left")) {
ret = snd_soc_dai_set_tdm_slot(
codec_dai, LEFT_SPK_TDM_TX_MASK,
SPK_TDM_RX_MASK, NUM_TDM_SLOTS,
slot_width);
if (ret < 0) {
dev_err(rtd->dev,
"DEV0 TDM slot err:%d\n", ret);
return ret;
}
}
if (!strcmp(codec_dai->component->name_prefix, "Right")) {
ret = snd_soc_dai_set_tdm_slot(
codec_dai, RIGHT_SPK_TDM_TX_MASK,
SPK_TDM_RX_MASK, NUM_TDM_SLOTS,
slot_width);
if (ret < 0) {
dev_err(rtd->dev,
"DEV1 TDM slot err:%d\n", ret);
return ret;
}
}
}
end:
return ret;
}
static int sdm845_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int ret = 0;
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
/*
* Use ASRC for internal clocks, as PLL rate isn't multiple
* of BCLK.
*/
rt5663_sel_asrc_clk_src(
codec_dai->component,
RT5663_DA_STEREO_FILTER | RT5663_AD_STEREO_FILTER,
RT5663_CLK_SEL_I2S1_ASRC);
ret = snd_soc_dai_set_sysclk(
codec_dai, RT5663_SCLK_S_MCLK, DEFAULT_MCLK_RATE,
SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(rtd->dev,
"snd_soc_dai_set_sysclk err = %d\n", ret);
break;
case QUATERNARY_TDM_RX_0:
case QUATERNARY_TDM_TX_0:
ret = sdm845_tdm_snd_hw_params(substream, params);
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
ret = sdm845_slim_snd_hw_params(substream, params);
break;
case QUATERNARY_MI2S_RX:
case SECONDARY_MI2S_RX:
break;
default:
pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
break;
}
return ret;
}
static void sdm845_jack_free(struct snd_jack *jack)
{
struct snd_soc_component *component = jack->private_data;
snd_soc_component_set_jack(component, NULL, NULL);
}
static int sdm845_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sdm845_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai_link *link = rtd->dai_link;
struct snd_jack *jack;
/*
* Codec SLIMBUS configuration
* RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13
* TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
* TX14, TX15, TX16
*/
unsigned int rx_ch[SLIM_MAX_RX_PORTS] = {144, 145, 146, 147, 148, 149,
150, 151, 152, 153, 154, 155, 156};
unsigned int tx_ch[SLIM_MAX_TX_PORTS] = {128, 129, 130, 131, 132, 133,
134, 135, 136, 137, 138, 139,
140, 141, 142, 143};
int rval, i;
if (!pdata->jack_setup) {
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_HEADPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&pdata->jack,
sdm845_jack_pins,
ARRAY_SIZE(sdm845_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headphone Jack\n");
return rval;
}
jack = pdata->jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
pdata->jack_setup = true;
}
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
jack = pdata->jack.jack;
component = codec_dai->component;
jack->private_data = component;
jack->private_free = sdm845_jack_free;
rval = snd_soc_component_set_jack(component,
&pdata->jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
/* setting up wcd multiple times for slim port is redundant */
if (pdata->slim_port_setup || !link->no_pcm)
return 0;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_dai_set_channel_map(codec_dai,
ARRAY_SIZE(tx_ch),
tx_ch,
ARRAY_SIZE(rx_ch),
rx_ch);
if (rval != 0 && rval != -ENOTSUPP)
return rval;
snd_soc_dai_set_sysclk(codec_dai, 0,
WCD934X_DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
rval = snd_soc_component_set_jack(codec_dai->component,
&pdata->jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
pdata->slim_port_setup = true;
break;
default:
break;
}
return 0;
}
static int sdm845_snd_startup(struct snd_pcm_substream *substream)
{
unsigned int fmt = SND_SOC_DAIFMT_BP_FP;
unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC;
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int j;
int ret;
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF;
if (++(data->pri_mi2s_clk_count) == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_MCLK_1,
DEFAULT_MCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
}
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case SECONDARY_MI2S_RX:
case SECONDARY_MI2S_TX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
if (++(data->sec_mi2s_clk_count) == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_CAPTURE);
}
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case QUATERNARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case QUATERNARY_TDM_RX_0:
case QUATERNARY_TDM_TX_0:
if (++(data->quat_tdm_clk_count) == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT,
TDM_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
}
codec_dai_fmt |= SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_DSP_B;
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name_prefix,
"Left")) {
ret = snd_soc_dai_set_fmt(
codec_dai, codec_dai_fmt);
if (ret < 0) {
dev_err(rtd->dev,
"Left TDM fmt err:%d\n", ret);
return ret;
}
}
if (!strcmp(codec_dai->component->name_prefix,
"Right")) {
ret = snd_soc_dai_set_fmt(
codec_dai, codec_dai_fmt);
if (ret < 0) {
dev_err(rtd->dev,
"Right TDM slot err:%d\n", ret);
return ret;
}
}
}
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
break;
default:
pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
break;
}
return qcom_snd_sdw_startup(substream);
}
static void sdm845_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
if (--(data->pri_mi2s_clk_count) == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_MCLK_1,
0, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
0, SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case SECONDARY_MI2S_RX:
case SECONDARY_MI2S_TX:
if (--(data->sec_mi2s_clk_count) == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
0, SNDRV_PCM_STREAM_CAPTURE);
}
break;
case QUATERNARY_TDM_RX_0:
case QUATERNARY_TDM_TX_0:
if (--(data->quat_tdm_clk_count) == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT,
0, SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
case QUATERNARY_MI2S_RX:
break;
default:
pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
break;
}
qcom_snd_sdw_shutdown(substream);
}
static int sdm845_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]);
}
static int sdm845_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return qcom_snd_sdw_hw_free(substream, &data->stream_prepared[cpu_dai->id]);
}
static const struct snd_soc_ops sdm845_be_ops = {
.hw_params = sdm845_snd_hw_params,
.hw_free = sdm845_snd_hw_free,
.prepare = sdm845_snd_prepare,
.startup = sdm845_snd_startup,
.shutdown = sdm845_snd_shutdown,
};
static int sdm845_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = DEFAULT_SAMPLE_RATE_48K;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static const struct snd_soc_dapm_widget sdm845_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
};
static const struct snd_kcontrol_new sdm845_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static void sdm845_add_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->ops = &sdm845_be_ops;
link->be_hw_params_fixup = sdm845_be_hw_params_fixup;
}
link->init = sdm845_dai_init;
}
}
static int sdm845_snd_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sdm845_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->driver_name = DRIVER_NAME;
card->dapm_widgets = sdm845_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sdm845_snd_widgets);
card->controls = sdm845_snd_controls;
card->num_controls = ARRAY_SIZE(sdm845_snd_controls);
card->dev = dev;
card->owner = THIS_MODULE;
dev_set_drvdata(dev, card);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
data->card = card;
snd_soc_card_set_drvdata(card, data);
sdm845_add_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id sdm845_snd_device_id[] = {
{ .compatible = "qcom,sdm845-sndcard" },
/* Do not grow the list for compatible devices */
{ .compatible = "qcom,db845c-sndcard" },
{ .compatible = "lenovo,yoga-c630-sndcard" },
{},
};
MODULE_DEVICE_TABLE(of, sdm845_snd_device_id);
static struct platform_driver sdm845_snd_driver = {
.probe = sdm845_snd_platform_probe,
.driver = {
.name = "msm-snd-sdm845",
.of_match_table = sdm845_snd_device_id,
},
};
module_platform_driver(sdm845_snd_driver);
MODULE_DESCRIPTION("sdm845 ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/sdw.c
+216
View File
@@ -0,0 +1,216 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018-2023, Linaro Limited.
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <sound/soc.h>
#include "sdw.h"
static bool qcom_snd_is_sdw_dai(int id)
{
switch (id) {
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_TX_0:
case WSA_CODEC_DMA_RX_1:
case WSA_CODEC_DMA_TX_1:
case WSA_CODEC_DMA_TX_2:
case RX_CODEC_DMA_RX_0:
case TX_CODEC_DMA_TX_0:
case RX_CODEC_DMA_RX_1:
case TX_CODEC_DMA_TX_1:
case RX_CODEC_DMA_RX_2:
case TX_CODEC_DMA_TX_2:
case RX_CODEC_DMA_RX_3:
case TX_CODEC_DMA_TX_3:
case RX_CODEC_DMA_RX_4:
case TX_CODEC_DMA_TX_4:
case RX_CODEC_DMA_RX_5:
case TX_CODEC_DMA_TX_5:
case RX_CODEC_DMA_RX_6:
case RX_CODEC_DMA_RX_7:
case SLIMBUS_0_RX...SLIMBUS_6_TX:
return true;
default:
break;
}
/* DSP Bypass usecase, cpu dai index overlaps with DSP dai ids,
* DO NOT MERGE into top switch case */
switch (id) {
case LPASS_CDC_DMA_TX3:
case LPASS_CDC_DMA_RX0:
return true;
default:
break;
}
return false;
}
/**
* qcom_snd_sdw_startup() - Helper to start Soundwire stream for SoC audio card
* @substream: The PCM substream from audio, as passed to snd_soc_ops->startup()
*
* Helper for the SoC audio card (snd_soc_ops->startup()) to allocate and set
* Soundwire stream runtime to each codec DAI.
*
* The shutdown() callback should call sdw_release_stream() on the same
* sdw_stream_runtime.
*
* Return: 0 or errno
*/
int qcom_snd_sdw_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
u32 rx_ch[SDW_MAX_PORTS], tx_ch[SDW_MAX_PORTS];
struct sdw_stream_runtime *sruntime;
struct snd_soc_dai *codec_dai;
u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
int ret, i, j;
if (!qcom_snd_is_sdw_dai(cpu_dai->id))
return 0;
sruntime = sdw_alloc_stream(cpu_dai->name, SDW_STREAM_PCM);
if (!sruntime)
return -ENOMEM;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_stream(codec_dai, sruntime,
substream->stream);
if (ret < 0 && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to set sdw stream on %s\n", codec_dai->name);
goto err_set_stream;
} else if (ret == -ENOTSUPP) {
/* Ignore unsupported */
continue;
}
ret = snd_soc_dai_get_channel_map(codec_dai, &tx_ch_cnt, tx_ch,
&rx_ch_cnt, rx_ch);
if (ret != 0 && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to get codec chan map %s\n", codec_dai->name);
goto err_set_stream;
} else if (ret == -ENOTSUPP) {
/* Ignore unsupported */
continue;
}
}
switch (cpu_dai->id) {
case RX_CODEC_DMA_RX_0:
case TX_CODEC_DMA_TX_3:
if (tx_ch_cnt || rx_ch_cnt) {
for_each_rtd_codec_dais(rtd, j, codec_dai) {
ret = snd_soc_dai_set_channel_map(codec_dai,
tx_ch_cnt, tx_ch,
rx_ch_cnt, rx_ch);
if (ret != 0 && ret != -ENOTSUPP)
goto err_set_stream;
}
}
}
return 0;
err_set_stream:
sdw_release_stream(sruntime);
return ret;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_startup);
int qcom_snd_sdw_prepare(struct snd_pcm_substream *substream,
bool *stream_prepared)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime;
int ret;
if (!qcom_snd_is_sdw_dai(cpu_dai->id))
return 0;
sruntime = qcom_snd_sdw_get_stream(substream);
if (!sruntime)
return 0;
if (*stream_prepared)
return 0;
ret = sdw_prepare_stream(sruntime);
if (ret)
return ret;
/**
* NOTE: there is a strict hw requirement about the ordering of port
* enables and actual WSA881x PA enable. PA enable should only happen
* after soundwire ports are enabled if not DC on the line is
* accumulated resulting in Click/Pop Noise
* PA enable/mute are handled as part of codec DAPM and digital mute.
*/
ret = sdw_enable_stream(sruntime);
if (ret) {
sdw_deprepare_stream(sruntime);
return ret;
}
*stream_prepared = true;
return ret;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_prepare);
struct sdw_stream_runtime *qcom_snd_sdw_get_stream(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime;
int i;
if (!qcom_snd_is_sdw_dai(cpu_dai->id))
return NULL;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
sruntime = snd_soc_dai_get_stream(codec_dai, substream->stream);
if (sruntime != ERR_PTR(-ENOTSUPP))
return sruntime;
}
return NULL;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_get_stream);
void qcom_snd_sdw_shutdown(struct snd_pcm_substream *substream)
{
struct sdw_stream_runtime *sruntime = qcom_snd_sdw_get_stream(substream);
sdw_release_stream(sruntime);
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_shutdown);
int qcom_snd_sdw_hw_free(struct snd_pcm_substream *substream, bool *stream_prepared)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime;
if (!qcom_snd_is_sdw_dai(cpu_dai->id))
return 0;
sruntime = qcom_snd_sdw_get_stream(substream);
if (sruntime && *stream_prepared) {
sdw_disable_stream(sruntime);
sdw_deprepare_stream(sruntime);
*stream_prepared = false;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_hw_free);
MODULE_DESCRIPTION("Qualcomm ASoC SoundWire helper functions");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/sdw.h
+16
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@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#ifndef __QCOM_SND_SDW_H__
#define __QCOM_SND_SDW_H__
#include <linux/soundwire/sdw.h>
int qcom_snd_sdw_startup(struct snd_pcm_substream *substream);
void qcom_snd_sdw_shutdown(struct snd_pcm_substream *substream);
int qcom_snd_sdw_prepare(struct snd_pcm_substream *substream,
bool *stream_prepared);
struct sdw_stream_runtime *qcom_snd_sdw_get_stream(struct snd_pcm_substream *stream);
int qcom_snd_sdw_hw_free(struct snd_pcm_substream *substream,
bool *stream_prepared);
#endif
linux-7.2.3/sound/soc/qcom/sm8250.c
+213
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@@ -0,0 +1,213 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/soundwire/sdw.h>
#include <sound/jack.h>
#include <linux/input-event-codes.h>
#include "qdsp6/q6afe.h"
#include "common.h"
#include "usb_offload_utils.h"
#include "sdw.h"
#define MI2S_BCLK_RATE 1536000
struct sm8250_snd_data {
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
struct snd_soc_jack jack;
struct snd_soc_jack usb_offload_jack;
bool usb_offload_jack_setup;
struct snd_soc_jack dp_jack;
bool jack_setup;
};
static int sm8250_snd_init(struct snd_soc_pcm_runtime *rtd)
{
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case DISPLAY_PORT_RX:
return qcom_snd_dp_jack_setup(rtd, &data->dp_jack, 0);
case USB_RX:
return qcom_snd_usb_offload_jack_setup(rtd, &data->usb_offload_jack,
&data->usb_offload_jack_setup);
default:
return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
}
}
static void sm8250_snd_exit(struct snd_soc_pcm_runtime *rtd)
{
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
if (cpu_dai->id == USB_RX)
qcom_snd_usb_offload_jack_remove(rtd,
&data->usb_offload_jack_setup);
}
static int sm8250_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static int sm8250_snd_startup(struct snd_pcm_substream *substream)
{
unsigned int fmt = SND_SOC_DAIFMT_BP_FP;
unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC;
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case SECONDARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case TERTIARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case QUINARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
default:
break;
}
return qcom_snd_sdw_startup(substream);
}
static int sm8250_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]);
}
static int sm8250_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return qcom_snd_sdw_hw_free(substream, &data->stream_prepared[cpu_dai->id]);
}
static const struct snd_soc_ops sm8250_be_ops = {
.startup = sm8250_snd_startup,
.shutdown = qcom_snd_sdw_shutdown,
.hw_free = sm8250_snd_hw_free,
.prepare = sm8250_snd_prepare,
};
static void sm8250_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->init = sm8250_snd_init;
link->exit = sm8250_snd_exit;
link->be_hw_params_fixup = sm8250_be_hw_params_fixup;
link->ops = &sm8250_be_ops;
}
}
}
static int sm8250_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sm8250_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->owner = THIS_MODULE;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->dev = dev;
dev_set_drvdata(dev, card);
snd_soc_card_set_drvdata(card, data);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
card->driver_name = of_device_get_match_data(dev);
sm8250_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id snd_sm8250_dt_match[] = {
{ .compatible = "fairphone,fp4-sndcard", .data = "sm7225" },
{ .compatible = "fairphone,fp5-sndcard", .data = "qcm6490" },
{ .compatible = "qcom,qrb2210-sndcard", .data = "qcm2290" },
{ .compatible = "qcom,qrb4210-rb2-sndcard", .data = "sm4250" },
{ .compatible = "qcom,qrb5165-rb5-sndcard", .data = "sm8250" },
{ .compatible = "qcom,sm8250-sndcard", .data = "sm8250" },
{}
};
MODULE_DEVICE_TABLE(of, snd_sm8250_dt_match);
static struct platform_driver snd_sm8250_driver = {
.probe = sm8250_platform_probe,
.driver = {
.name = "snd-sm8250",
.of_match_table = snd_sm8250_dt_match,
},
};
module_platform_driver(snd_sm8250_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org");
MODULE_DESCRIPTION("SM8250 ASoC Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/storm.c
+142
View File
@@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* storm.c -- ALSA SoC machine driver for QTi ipq806x-based Storm board
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define STORM_SYSCLK_MULT 4
static int storm_ops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream);
struct snd_soc_card *card = soc_runtime->card;
snd_pcm_format_t format = params_format(params);
unsigned int rate = params_rate(params);
unsigned int sysclk_freq;
int bitwidth, ret;
bitwidth = snd_pcm_format_width(format);
if (bitwidth < 0) {
dev_err(card->dev, "invalid bit width given: %d\n", bitwidth);
return bitwidth;
}
/*
* as the CPU DAI is the I2S bus master and no system clock is needed by
* the MAX98357a DAC, simply set the system clock to be a constant
* multiple of the bit clock for the clock divider
*/
sysclk_freq = rate * bitwidth * 2 * STORM_SYSCLK_MULT;
ret = snd_soc_dai_set_sysclk(snd_soc_rtd_to_cpu(soc_runtime, 0), 0, sysclk_freq, 0);
if (ret) {
dev_err(card->dev, "error setting sysclk to %u: %d\n",
sysclk_freq, ret);
return ret;
}
return 0;
}
static const struct snd_soc_ops storm_soc_ops = {
.hw_params = storm_ops_hw_params,
};
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link storm_dai_link = {
.name = "Primary",
.stream_name = "Primary",
.ops = &storm_soc_ops,
SND_SOC_DAILINK_REG(hifi),
};
static int storm_parse_of(struct snd_soc_card *card)
{
struct snd_soc_dai_link *dai_link = card->dai_link;
struct device_node *np = card->dev->of_node;
dai_link->cpus->of_node = of_parse_phandle(np, "cpu", 0);
if (!dai_link->cpus->of_node) {
dev_err(card->dev, "error getting cpu phandle\n");
return -EINVAL;
}
dai_link->platforms->of_node = dai_link->cpus->of_node;
dai_link->codecs->of_node = of_parse_phandle(np, "codec", 0);
if (!dai_link->codecs->of_node) {
dev_err(card->dev, "error getting codec phandle\n");
return -EINVAL;
}
return 0;
}
static int storm_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
int ret;
card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->dev = &pdev->dev;
card->owner = THIS_MODULE;
ret = snd_soc_of_parse_card_name(card, "qcom,model");
if (ret) {
dev_err(&pdev->dev, "error parsing card name: %d\n", ret);
return ret;
}
card->dai_link = &storm_dai_link;
card->num_links = 1;
ret = storm_parse_of(card);
if (ret) {
dev_err(&pdev->dev, "error resolving dai links: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "error registering soundcard: %d\n", ret);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id storm_device_id[] = {
{ .compatible = "google,storm-audio" },
{},
};
MODULE_DEVICE_TABLE(of, storm_device_id);
#endif
static struct platform_driver storm_platform_driver = {
.driver = {
.name = "storm-audio",
.of_match_table =
of_match_ptr(storm_device_id),
},
.probe = storm_platform_probe,
};
module_platform_driver(storm_platform_driver);
MODULE_DESCRIPTION("QTi IPQ806x-based Storm Machine Driver");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/usb_offload_utils.c
+56
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@@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <sound/jack.h>
#include <sound/soc-usb.h>
#include "usb_offload_utils.h"
int qcom_snd_usb_offload_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *jack, bool *jack_setup)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int ret = 0;
if (cpu_dai->id != USB_RX)
return -EINVAL;
if (!*jack_setup) {
ret = snd_soc_usb_setup_offload_jack(codec_dai->component, jack);
if (ret)
return ret;
}
*jack_setup = true;
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_usb_offload_jack_setup);
int qcom_snd_usb_offload_jack_remove(struct snd_soc_pcm_runtime *rtd,
bool *jack_setup)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int ret = 0;
if (cpu_dai->id != USB_RX)
return -EINVAL;
if (*jack_setup) {
ret = snd_soc_component_set_jack(codec_dai->component, NULL, NULL);
if (ret)
return ret;
}
*jack_setup = false;
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_usb_offload_jack_remove);
MODULE_DESCRIPTION("ASoC Q6 USB offload controls");
MODULE_LICENSE("GPL");
linux-7.2.3/sound/soc/qcom/usb_offload_utils.h
+30
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@@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __QCOM_SND_USB_OFFLOAD_UTILS_H__
#define __QCOM_SND_USB_OFFLOAD_UTILS_H__
#include <sound/soc.h>
#if IS_ENABLED(CONFIG_SND_SOC_QCOM_OFFLOAD_UTILS)
int qcom_snd_usb_offload_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *jack, bool *jack_setup);
int qcom_snd_usb_offload_jack_remove(struct snd_soc_pcm_runtime *rtd,
bool *jack_setup);
#else
static inline int qcom_snd_usb_offload_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *jack,
bool *jack_setup)
{
return -ENODEV;
}
static inline int qcom_snd_usb_offload_jack_remove(struct snd_soc_pcm_runtime *rtd,
bool *jack_setup)
{
return -ENODEV;
}
#endif /* IS_ENABLED(CONFIG_SND_SOC_QCOM_OFFLOAD_UTILS) */
#endif /* __QCOM_SND_USB_OFFLOAD_UTILS_H__ */
linux-7.2.3/sound/soc/qcom/x1e80100.c
+229
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@@ -0,0 +1,229 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2023, Linaro Limited
#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/soundwire/sdw.h>
#include <sound/pcm.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "common.h"
#include "qdsp6/q6afe.h"
#include "qdsp6/q6dsp-common.h"
#include "sdw.h"
struct x1e80100_snd_data {
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
struct snd_soc_jack jack;
struct snd_soc_jack dp_jack[8];
bool jack_setup;
};
static int x1e80100_snd_init(struct snd_soc_pcm_runtime *rtd)
{
struct x1e80100_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct snd_soc_jack *dp_jack = NULL;
int dp_pcm_id = 0;
switch (cpu_dai->id) {
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
/*
* Set limit of -3 dB on Digital Volume and 0 dB on PA Volume
* to reduce the risk of speaker damage until we have active
* speaker protection in place.
*/
snd_soc_limit_volume(card, "WSA WSA_RX0 Digital Volume", 81);
snd_soc_limit_volume(card, "WSA WSA_RX1 Digital Volume", 81);
snd_soc_limit_volume(card, "WSA2 WSA_RX0 Digital Volume", 81);
snd_soc_limit_volume(card, "WSA2 WSA_RX1 Digital Volume", 81);
snd_soc_limit_volume(card, "SpkrLeft PA Volume", 6);
snd_soc_limit_volume(card, "SpkrRight PA Volume", 6);
snd_soc_limit_volume(card, "WooferLeft PA Volume", 6);
snd_soc_limit_volume(card, "TweeterLeft PA Volume", 6);
snd_soc_limit_volume(card, "WooferRight PA Volume", 6);
snd_soc_limit_volume(card, "TweeterRight PA Volume", 6);
break;
case DISPLAY_PORT_RX_0:
dp_pcm_id = 0;
dp_jack = &data->dp_jack[dp_pcm_id];
break;
case DISPLAY_PORT_RX_1 ... DISPLAY_PORT_RX_7:
dp_pcm_id = cpu_dai->id - DISPLAY_PORT_RX_1 + 1;
dp_jack = &data->dp_jack[dp_pcm_id];
break;
default:
break;
}
if (dp_jack)
return qcom_snd_dp_jack_setup(rtd, dp_jack, dp_pcm_id);
return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
}
static int x1e80100_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
rate->min = rate->max = 48000;
switch (cpu_dai->id) {
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
channels->min = 1;
break;
default:
break;
}
return 0;
}
static int x1e80100_snd_hw_map_channels(unsigned int *ch_map, int num)
{
switch (num) {
case 1:
ch_map[0] = PCM_CHANNEL_FC;
break;
case 2:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
break;
case 3:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_FC;
break;
case 4:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_LB;
ch_map[2] = PCM_CHANNEL_FR;
ch_map[3] = PCM_CHANNEL_RB;
break;
default:
return -EINVAL;
}
return 0;
}
static int x1e80100_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct x1e80100_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
unsigned int channels = substream->runtime->channels;
unsigned int rx_slot[4];
int ret;
switch (cpu_dai->id) {
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
ret = x1e80100_snd_hw_map_channels(rx_slot, channels);
if (ret)
return ret;
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
channels, rx_slot);
if (ret)
return ret;
break;
default:
break;
}
return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]);
}
static int x1e80100_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct x1e80100_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
return qcom_snd_sdw_hw_free(substream, &data->stream_prepared[cpu_dai->id]);
}
static const struct snd_soc_ops x1e80100_be_ops = {
.startup = qcom_snd_sdw_startup,
.shutdown = qcom_snd_sdw_shutdown,
.hw_free = x1e80100_snd_hw_free,
.prepare = x1e80100_snd_prepare,
};
static void x1e80100_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->init = x1e80100_snd_init;
link->be_hw_params_fixup = x1e80100_be_hw_params_fixup;
link->ops = &x1e80100_be_ops;
}
}
}
static int x1e80100_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct x1e80100_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->owner = THIS_MODULE;
card->dev = dev;
dev_set_drvdata(dev, card);
snd_soc_card_set_drvdata(card, data);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
card->driver_name = of_device_get_match_data(dev);
x1e80100_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id snd_x1e80100_dt_match[] = {
{ .compatible = "qcom,x1e80100-sndcard", .data = "x1e80100" },
{ .compatible = "qcom,glymur-sndcard", .data = "glymur" },
{}
};
MODULE_DEVICE_TABLE(of, snd_x1e80100_dt_match);
static struct platform_driver snd_x1e80100_driver = {
.probe = x1e80100_platform_probe,
.driver = {
.name = "snd-x1e80100",
.of_match_table = snd_x1e80100_dt_match,
},
};
module_platform_driver(snd_x1e80100_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org");
MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>");
MODULE_DESCRIPTION("Qualcomm X1E80100 ASoC Machine Driver");
MODULE_LICENSE("GPL");