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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/branch.json
+17
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[
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/bus.json
+32
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "CNT_CYCLES"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
+103
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[
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL",
"Errata": "Errata AC03_CPU_41",
"BriefDescription": "L1D cache invalidate. Impacted by errata -"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2I_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "L2I_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L1I_CACHE_LMISS"
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json
+578
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[
{
"PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
"EventCode": "0x10A",
"EventName": "L2_PREFETCH_REFILL",
"BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
},
{
"PublicDescription": "Level 2 prefetch requests, late",
"EventCode": "0x10B",
"EventName": "L2_PREFETCH_UPGRADE",
"BriefDescription": "Level 2 prefetch requests, late"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
"EventCode": "0x110",
"EventName": "BPU_HIT_BTB",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
"EventCode": "0x111",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
"EventCode": "0x112",
"EventName": "BPU_HIT_INDIRECT_PREDICTOR",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
"EventCode": "0x113",
"EventName": "BPU_HIT_RSB",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
},
{
"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
"EventCode": "0x114",
"EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted",
"EventCode": "0x115",
"EventName": "BPU_BRANCH_NO_HIT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
"EventCode": "0x116",
"EventName": "BPU_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
"EventCode": "0x117",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
"EventCode": "0x118",
"EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
"EventCode": "0x119",
"EventName": "BPU_HIT_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
"EventCode": "0x11a",
"EventName": "BPU_MISS_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
"EventCode": "0x11b",
"EventName": "BPU_NO_PREDICTION_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
"EventCode": "0x11c",
"EventName": "BPU_BTB_UPDATE",
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
},
{
"PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
"EventCode": "0x11d",
"EventName": "BPU_RSB_FULL_STALL",
"BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
},
{
"PublicDescription": "Macro-ops speculatively decoded",
"EventCode": "0x11f",
"EventName": "ICF_INST_SPEC_DECODE",
"BriefDescription": "Macro-ops speculatively decoded"
},
{
"PublicDescription": "Flushes",
"EventCode": "0x120",
"EventName": "GPC_FLUSH",
"BriefDescription": "Flushes"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "GPC_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
},
{
"PublicDescription": "ETM extout bit 0",
"EventCode": "0x141",
"EventName": "MSC_ETM_EXTOUT0",
"BriefDescription": "ETM extout bit 0"
},
{
"PublicDescription": "ETM extout bit 1",
"EventCode": "0x142",
"EventName": "MSC_ETM_EXTOUT1",
"BriefDescription": "ETM extout bit 1"
},
{
"PublicDescription": "ETM extout bit 2",
"EventCode": "0x143",
"EventName": "MSC_ETM_EXTOUT2",
"BriefDescription": "ETM extout bit 2"
},
{
"PublicDescription": "ETM extout bit 3",
"EventCode": "0x144",
"EventName": "MSC_ETM_EXTOUT3",
"BriefDescription": "ETM extout bit 3"
},
{
"PublicDescription": "Bus request sn",
"EventCode": "0x156",
"EventName": "L2C_SNOOP",
"BriefDescription": "Bus request sn"
},
{
"PublicDescription": "L2 TXDAT LCRD blocked",
"EventCode": "0x169",
"EventName": "L2C_DAT_CRD_STALL",
"BriefDescription": "L2 TXDAT LCRD blocked"
},
{
"PublicDescription": "L2 TXRSP LCRD blocked",
"EventCode": "0x16a",
"EventName": "L2C_RSP_CRD_STALL",
"BriefDescription": "L2 TXRSP LCRD blocked"
},
{
"PublicDescription": "L2 TXREQ LCRD blocked",
"EventCode": "0x16b",
"EventName": "L2C_REQ_CRD_STALL",
"BriefDescription": "L2 TXREQ LCRD blocked"
},
{
"PublicDescription": "Early mispredict",
"EventCode": "0xD100",
"EventName": "ICF_EARLY_MIS_PRED",
"BriefDescription": "Early mispredict"
},
{
"PublicDescription": "FEQ full cycles",
"EventCode": "0xD101",
"EventName": "ICF_FEQ_FULL",
"BriefDescription": "FEQ full cycles"
},
{
"PublicDescription": "Instruction FIFO Full",
"EventCode": "0xD102",
"EventName": "ICF_INST_FIFO_FULL",
"BriefDescription": "Instruction FIFO Full"
},
{
"PublicDescription": "L1I TLB miss",
"EventCode": "0xD103",
"EventName": "L1I_TLB_MISS",
"BriefDescription": "L1I TLB miss"
},
{
"PublicDescription": "ICF sent 0 instructions to IDR this cycle",
"EventCode": "0xD104",
"EventName": "ICF_STALL",
"BriefDescription": "ICF sent 0 instructions to IDR this cycle"
},
{
"PublicDescription": "PC FIFO Full",
"EventCode": "0xD105",
"EventName": "ICF_PC_FIFO_FULL",
"BriefDescription": "PC FIFO Full"
},
{
"PublicDescription": "Stall due to BOB ID",
"EventCode": "0xD200",
"EventName": "IDR_STALL_BOB_ID",
"BriefDescription": "Stall due to BOB ID"
},
{
"PublicDescription": "Dispatch stall due to LOB entries",
"EventCode": "0xD201",
"EventName": "IDR_STALL_LOB_ID",
"BriefDescription": "Dispatch stall due to LOB entries"
},
{
"PublicDescription": "Dispatch stall due to SOB entries",
"EventCode": "0xD202",
"EventName": "IDR_STALL_SOB_ID",
"BriefDescription": "Dispatch stall due to SOB entries"
},
{
"PublicDescription": "Dispatch stall due to IXU scheduler entries",
"EventCode": "0xD203",
"EventName": "IDR_STALL_IXU_SCHED",
"BriefDescription": "Dispatch stall due to IXU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to FSU scheduler entries",
"EventCode": "0xD204",
"EventName": "IDR_STALL_FSU_SCHED",
"BriefDescription": "Dispatch stall due to FSU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to ROB entries",
"EventCode": "0xD205",
"EventName": "IDR_STALL_ROB_ID",
"BriefDescription": "Dispatch stall due to ROB entries"
},
{
"PublicDescription": "Dispatch stall due to flush (6 cycles)",
"EventCode": "0xD206",
"EventName": "IDR_STALL_FLUSH",
"BriefDescription": "Dispatch stall due to flush (6 cycles)"
},
{
"PublicDescription": "Dispatch stall due to WFI",
"EventCode": "0xD207",
"EventName": "IDR_STALL_WFI",
"BriefDescription": "Dispatch stall due to WFI"
},
{
"PublicDescription": "Number of SWOB drains triggered by timeout",
"EventCode": "0xD208",
"EventName": "IDR_STALL_SWOB_TIMEOUT",
"BriefDescription": "Number of SWOB drains triggered by timeout"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
"EventCode": "0xD209",
"EventName": "IDR_STALL_SWOB_RAW",
"BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
"EventCode": "0xD20A",
"EventName": "IDR_STALL_SWOB_FULL",
"BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
},
{
"PublicDescription": "Dispatch stall due to L1 instruction cache miss",
"EventCode": "0xD20B",
"EventName": "STALL_FRONTEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 instruction cache miss"
},
{
"PublicDescription": "Dispatch stall due to L1 instruction TLB miss",
"EventCode": "0xD20C",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "Dispatch stall due to L1 instruction TLB miss"
},
{
"PublicDescription": "Dispatch stall due to L1 data cache miss",
"EventCode": "0xD20D",
"EventName": "STALL_BACKEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 data cache miss"
},
{
"PublicDescription": "Dispatch stall due to L1 data TLB miss",
"EventCode": "0xD20E",
"EventName": "STALL_BACKEND_TLB",
"BriefDescription": "Dispatch stall due to L1 data TLB miss"
},
{
"PublicDescription": "Dispatch stall due to lack of any core resource",
"EventCode": "0xD20F",
"EventName": "STALL_BACKEND_RESOURCE",
"BriefDescription": "Dispatch stall due to lack of any core resource"
},
{
"PublicDescription": "Instructions issued by the scheduler",
"EventCode": "0xD300",
"EventName": "IXU_NUM_UOPS_ISSUED",
"BriefDescription": "Instructions issued by the scheduler"
},
{
"PublicDescription": "Any uop issued was canceled for any reason",
"EventCode": "0xD301",
"EventName": "IXU_ISSUE_CANCEL",
"BriefDescription": "Any uop issued was canceled for any reason"
},
{
"PublicDescription": "A load wakeup to the scheduler has been cancelled",
"EventCode": "0xD302",
"EventName": "IXU_LOAD_CANCEL",
"BriefDescription": "A load wakeup to the scheduler has been cancelled"
},
{
"PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
"EventCode": "0xD303",
"EventName": "IXU_SLOW_CANCEL",
"BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA",
"EventCode": "0xD304",
"EventName": "IXU_IXA_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 0",
"EventCode": "0xD305",
"EventName": "IXU_IXA_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 1",
"EventCode": "0xD306",
"EventName": "IXU_IXA_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB",
"EventCode": "0xD307",
"EventName": "IXU_IXB_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 0",
"EventCode": "0xD308",
"EventName": "IXU_IXB_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 1",
"EventCode": "0xD309",
"EventName": "IXU_IXB_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC",
"EventCode": "0xD30A",
"EventName": "IXU_IXC_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 0",
"EventCode": "0xD30B",
"EventName": "IXU_IXC_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 1",
"EventCode": "0xD30C",
"EventName": "IXU_IXC_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD",
"EventCode": "0xD30D",
"EventName": "IXU_IXD_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 0",
"EventCode": "0xD30E",
"EventName": "IXU_IXD_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 1",
"EventCode": "0xD30F",
"EventName": "IXU_IXD_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 1"
},
{
"PublicDescription": "Uops issued by the FSU scheduler",
"EventCode": "0xD400",
"EventName": "FSU_ISSUED",
"BriefDescription": "Uops issued by the FSU scheduler"
},
{
"PublicDescription": "Uops issued by the scheduler on pipe X",
"EventCode": "0xD401",
"EventName": "FSU_FSX_ISSUED",
"BriefDescription": "Uops issued by the scheduler on pipe X"
},
{
"PublicDescription": "Uops issued by the scheduler on pipe Y",
"EventCode": "0xD402",
"EventName": "FSU_FSY_ISSUED",
"BriefDescription": "Uops issued by the scheduler on pipe Y"
},
{
"PublicDescription": "Uops issued by the scheduler on pipe Z",
"EventCode": "0xD403",
"EventName": "FSU_FSZ_ISSUED",
"BriefDescription": "Uops issued by the scheduler on pipe Z"
},
{
"PublicDescription": "Uops canceled (load cancels)",
"EventCode": "0xD404",
"EventName": "FSU_CANCEL",
"BriefDescription": "Uops canceled (load cancels)"
},
{
"PublicDescription": "Count scheduler stalls due to divide/sqrt",
"EventCode": "0xD405",
"EventName": "FSU_DIV_SQRT_STALL",
"BriefDescription": "Count scheduler stalls due to divide/sqrt"
},
{
"PublicDescription": "Number of SWOB drains",
"EventCode": "0xD500",
"EventName": "GPC_SWOB_DRAIN",
"BriefDescription": "Number of SWOB drains"
},
{
"PublicDescription": "GPC detected a Breakpoint instruction match",
"EventCode": "0xD501",
"EventName": "BREAKPOINT_MATCH",
"BriefDescription": "GPC detected a Breakpoint instruction match"
},
{
"PublicDescription": "L1D TLB miss",
"EventCode": "0xD600",
"EventName": "L1D_TLB_MISS",
"BriefDescription": "L1D TLB miss"
},
{
"PublicDescription": "OFB full cycles",
"EventCode": "0xD601",
"EventName": "OFB_FULL",
"BriefDescription": "OFB full cycles"
},
{
"PublicDescription": "Load satisified from store forwarded data",
"EventCode": "0xD605",
"EventName": "LD_FROM_ST_FWD",
"BriefDescription": "Load satisified from store forwarded data"
},
{
"PublicDescription": "L1 prefetcher, load prefetch requests generated",
"EventCode": "0xD606",
"EventName": "L1_PFETCH_LD_GEN",
"BriefDescription": "L1 prefetcher, load prefetch requests generated"
},
{
"PublicDescription": "L1 prefetcher, load prefetch fills into the L1 cache",
"EventCode": "0xD607",
"EventName": "L1_PFETCH_LD_FILL",
"BriefDescription": "L1 prefetcher, load prefetch fills into the L1 cache"
},
{
"PublicDescription": "L1 prefetcher, load prefetch to L2 generated",
"EventCode": "0xD608",
"EventName": "L1_PFETCH_L2_REQ",
"BriefDescription": "L1 prefetcher, load prefetch to L2 generated"
},
{
"PublicDescription": "L1 prefetcher, distance was reset",
"EventCode": "0xD609",
"EventName": "L1_PFETCH_DIST_RST",
"BriefDescription": "L1 prefetcher, distance was reset"
},
{
"PublicDescription": "L1 prefetcher, distance was increased",
"EventCode": "0xD60A",
"EventName": "L1_PFETCH_DIST_INC",
"BriefDescription": "L1 prefetcher, distance was increased"
},
{
"PublicDescription": "L1 prefetcher, table entry is trained",
"EventCode": "0xD60B",
"EventName": "L1_PFETCH_ENTRY_TRAINED",
"BriefDescription": "L1 prefetcher, table entry is trained"
},
{
"PublicDescription": "Store retirement pipe stall",
"EventCode": "0xD60C",
"EventName": "LSU_ST_RETIRE_STALL",
"BriefDescription": "Store retirement pipe stall"
},
{
"PublicDescription": "LSU detected a Watchpoint data match",
"EventCode": "0xD60D",
"EventName": "WATCHPOINT_MATCH",
"BriefDescription": "LSU detected a Watchpoint data match"
},
{
"PublicDescription": "L2 pipeline replay",
"EventCode": "0xD700",
"EventName": "L2C_PIPE_REPLAY",
"BriefDescription": "L2 pipeline replay"
},
{
"PublicDescription": "L2 refill from I-side miss",
"EventCode": "0xD701",
"EventName": "L2C_INST_REFILL",
"BriefDescription": "L2 refill from I-side miss"
},
{
"PublicDescription": "L2 refill from D-side miss",
"EventCode": "0xD702",
"EventName": "L2C_DATA_REFILL",
"BriefDescription": "L2 refill from D-side miss"
},
{
"PublicDescription": "L2 prefetcher, load prefetch requests generated",
"EventCode": "0xD703",
"EventName": "L2_PREFETCH_REQ",
"BriefDescription": "L2 prefetcher, load prefetch requests generated"
},
{
"PublicDescription": "L2D OTB allocate",
"EventCode": "0xD800",
"EventName": "MMU_D_OTB_ALLOC",
"BriefDescription": "L2D OTB allocate"
},
{
"PublicDescription": "D-side Stage1 tablewalk fault",
"EventCode": "0xD80B",
"EventName": "MMU_D_S1_WALK_FAULT",
"BriefDescription": "D-side Stage1 tablewalk fault"
},
{
"PublicDescription": "D-side Stage2 tablewalk fault",
"EventCode": "0xD80C",
"EventName": "MMU_D_S2_WALK_FAULT",
"BriefDescription": "D-side Stage2 tablewalk fault"
},
{
"PublicDescription": "D-side Tablewalk steps or descriptor fetches",
"EventCode": "0xD80D",
"EventName": "MMU_D_WALK_STEPS",
"BriefDescription": "D-side Tablewalk steps or descriptor fetches"
},
{
"PublicDescription": "L2I OTB allocate",
"EventCode": "0xD900",
"EventName": "MMU_I_OTB_ALLOC",
"BriefDescription": "L2I OTB allocate"
},
{
"PublicDescription": "I-side Stage1 tablewalk fault",
"EventCode": "0xD90B",
"EventName": "MMU_I_S1_WALK_FAULT",
"BriefDescription": "I-side Stage1 tablewalk fault"
},
{
"PublicDescription": "I-side Stage2 tablewalk fault",
"EventCode": "0xD90C",
"EventName": "MMU_I_S2_WALK_FAULT",
"BriefDescription": "I-side Stage2 tablewalk fault"
},
{
"PublicDescription": "I-side Tablewalk steps or descriptor fetches",
"EventCode": "0xD90D",
"EventName": "MMU_I_WALK_STEPS",
"BriefDescription": "I-side Tablewalk steps or descriptor fetches"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/exception.json
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[
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "EXC_RETURN"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "OP_RETIRED"
},
{
"PublicDescription": "Operation speculatively executed, NOP",
"EventCode": "0x100",
"EventName": "NOP_SPEC",
"BriefDescription": "Speculatively executed, NOP"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/intrinsic.json
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[
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json
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[
{
"ArchStdEvent": "LD_RETIRED",
"Errata": "Errata AC03_CPU_52",
"BriefDescription": "Instruction architecturally executed, condition code check pass, load. Impacted by errata -"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/metrics.json
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[
{
"MetricName": "branch_miss_pred_rate",
"MetricExpr": "BR_MIS_PRED / BR_PRED",
"BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch",
"MetricGroup": "branch",
"ScaleUnit": "100%"
},
{
"MetricName": "bus_utilization",
"MetricExpr": "((BUS_ACCESS / (BUS_CYCLES * 1)) * 100)",
"BriefDescription": "Core-to-uncore bus utilization",
"MetricGroup": "Bus",
"ScaleUnit": "1percent of bus cycles"
},
{
"MetricName": "l1d_cache_miss_ratio",
"MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)",
"BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.",
"MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l1i_cache_miss_ratio",
"MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)",
"BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.",
"MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "Miss_Ratio;l1d_cache_read_miss",
"MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD",
"BriefDescription": "L1D cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache read access"
},
{
"MetricName": "l2_cache_miss_ratio",
"MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)",
"BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
"MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l1i_cache_read_miss_rate",
"MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE",
"BriefDescription": "L1I cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l2d_cache_read_miss_rate",
"MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD",
"BriefDescription": "L2 cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache read access"
},
{
"MetricName": "l1d_cache_miss_mpki",
"MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (data)",
"MetricGroup": "Cache",
"ScaleUnit": "1MPKI"
},
{
"MetricName": "l1i_cache_miss_mpki",
"MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (instruction)",
"MetricGroup": "Cache",
"ScaleUnit": "1MPKI"
},
{
"MetricName": "simd_percentage",
"MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)",
"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "crypto_percentage",
"MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)",
"BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "gflops",
"MetricExpr": "VFP_SPEC / (duration_time * 1e9)",
"BriefDescription": "Giga-floating point operations per second",
"MetricGroup": "InstructionMix"
},
{
"MetricName": "integer_dp_percentage",
"MetricExpr": "((DP_SPEC / INST_SPEC) * 100)",
"BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "ipc",
"MetricExpr": "(INST_RETIRED / CPU_CYCLES)",
"BriefDescription": "This metric measures the number of instructions retired per cycle.",
"MetricGroup": "General",
"ScaleUnit": "1per cycle"
},
{
"MetricName": "load_percentage",
"MetricExpr": "((LD_SPEC / INST_SPEC) * 100)",
"BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "load_store_spec_rate",
"MetricExpr": "((LDST_SPEC / INST_SPEC) * 100)",
"BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speculatively executed",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "retired_mips",
"MetricExpr": "INST_RETIRED / (duration_time * 1e6)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "InstructionMix"
},
{
"MetricName": "spec_utilization_mips",
"MetricExpr": "INST_SPEC / (duration_time * 1e6)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "PEutilization"
},
{
"MetricName": "pc_write_spec_rate",
"MetricExpr": "((PC_WRITE_SPEC / INST_SPEC) * 100)",
"BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speculatively executed",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "store_percentage",
"MetricExpr": "((ST_SPEC / INST_SPEC) * 100)",
"BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "scalar_fp_percentage",
"MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)",
"BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "1percent of operations"
},
{
"MetricName": "retired_rate",
"MetricExpr": "OP_RETIRED / OP_SPEC",
"BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "wasted",
"MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
"BriefDescription": "Of all the micro-operations issued, what proportion are lost",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "wasted_rate",
"MetricExpr": "1 - OP_RETIRED / OP_SPEC",
"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "stall_backend_cache_rate",
"MetricExpr": "((STALL_BACKEND_CACHE / CPU_CYCLES) * 100)",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss",
"MetricGroup": "Stall",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_backend_resource_rate",
"MetricExpr": "((STALL_BACKEND_RESOURCE / CPU_CYCLES) * 100)",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full",
"MetricGroup": "Stall",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_backend_tlb_rate",
"MetricExpr": "((STALL_BACKEND_TLB / CPU_CYCLES) * 100)",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
"MetricGroup": "Stall",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_frontend_cache_rate",
"MetricExpr": "((STALL_FRONTEND_CACHE / CPU_CYCLES) * 100)",
"BriefDescription": "Proportion of cycles stalled and no operations delivered from frontend and cache miss",
"MetricGroup": "Stall",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_frontend_tlb_rate",
"MetricExpr": "((STALL_FRONTEND_TLB / CPU_CYCLES) * 100)",
"BriefDescription": "Proportion of cycles stalled and no operations delivered from frontend and TLB miss",
"MetricGroup": "Stall",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "dtlb_walk_ratio",
"MetricExpr": "(DTLB_WALK / L1D_TLB)",
"BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.",
"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
"ScaleUnit": "1per TLB access"
},
{
"MetricName": "itlb_walk_ratio",
"MetricExpr": "(ITLB_WALK / L1I_TLB)",
"BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.",
"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
"ScaleUnit": "1per TLB access"
},
{
"ArchStdEvent": "backend_bound"
},
{
"ArchStdEvent": "frontend_bound",
"MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)"
},
{
"MetricName": "slots_lost_misspeculation_fraction",
"MetricExpr": "100 * ((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots))",
"BriefDescription": "Fraction of slots lost due to misspeculation",
"DefaultMetricgroupName": "TopdownL1",
"MetricGroup": "Default;TopdownL1",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "retired_fraction",
"MetricExpr": "100 * (OP_RETIRED / (CPU_CYCLES * #slots))",
"BriefDescription": "Fraction of slots retiring, useful work",
"DefaultMetricgroupName": "TopdownL1",
"MetricGroup": "Default;TopdownL1",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "backend_core",
"MetricExpr": "(backend_bound / 100) - backend_memory",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_memory",
"MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"MetricName": "branch_mispredict",
"MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction",
"BriefDescription": "Fraction of slots lost due to branch misprediciton",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "frontend_bandwidth",
"MetricExpr": "frontend_bound - frontend_latency",
"BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "frontend_latency",
"MetricExpr": "((STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES) * 100",
"BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "other_miss_pred",
"MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict",
"BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "pipe_utilization",
"MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))",
"BriefDescription": "Fraction of execute slots utilized",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "d_cache_l2_miss_rate",
"MetricExpr": "((STALL_BACKEND_MEM / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "d_cache_miss_rate",
"MetricExpr": "((STALL_BACKEND_CACHE / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "d_tlb_miss_rate",
"MetricExpr": "((STALL_BACKEND_TLB / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "fsu_pipe_utilization",
"MetricExpr": "((FSU_ISSUED / (CPU_CYCLES * 2)) * 100)",
"BriefDescription": "Fraction of FSU execute slots utilized",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "i_cache_miss_rate",
"MetricExpr": "((STALL_FRONTEND_CACHE / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "i_tlb_miss_rate",
"MetricExpr": "((STALL_FRONTEND_TLB / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "ixu_pipe_utilization",
"MetricExpr": "((IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)) * 100)",
"BriefDescription": "Fraction of IXU execute slots utilized",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "stall_recovery_rate",
"MetricExpr": "((IDR_STALL_FLUSH / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
"MetricGroup": "TopdownL3",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "stall_fsu_sched_rate",
"MetricExpr": "((IDR_STALL_FSU_SCHED / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_ixu_sched_rate",
"MetricExpr": "((IDR_STALL_IXU_SCHED / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_lob_id_rate",
"MetricExpr": "((IDR_STALL_LOB_ID / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_rob_id_rate",
"MetricExpr": "((IDR_STALL_ROB_ID / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "stall_sob_id_rate",
"MetricExpr": "((IDR_STALL_SOB_ID / CPU_CYCLES) * 100)",
"BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "1percent of cycles"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json
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[
{
"ArchStdEvent": "STALL_FRONTEND",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"ArchStdEvent": "STALL",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND"
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_SLOT"
},
{
"ArchStdEvent": "STALL_BACKEND_MEM"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereone/spe.json
+14
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[
{
"ArchStdEvent": "SAMPLE_POP"
},
{
"ArchStdEvent": "SAMPLE_FEED"
},
{
"ArchStdEvent": "SAMPLE_FILTRATE"
},
{
"ArchStdEvent": "SAMPLE_COLLISION"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/branch.json
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[
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"PublicDescription": "Instruction architecturally executed, branch not taken",
"EventCode": "0x8107",
"EventName": "BR_SKIP_RETIRED",
"BriefDescription": "Instruction architecturally executed, branch not taken"
},
{
"PublicDescription": "Instruction architecturally executed, immediate branch taken",
"EventCode": "0x8108",
"EventName": "BR_IMMED_TAKEN_RETIRED",
"BriefDescription": "Instruction architecturally executed, immediate branch taken"
},
{
"PublicDescription": "Instruction architecturally executed, indirect branch excluding return retired",
"EventCode": "0x810c",
"EventName": "BR_INDNR_TAKEN_RETIRED",
"BriefDescription": "Instruction architecturally executed, indirect branch excluding return retired"
},
{
"PublicDescription": "Instruction architecturally executed, predicted immediate branch",
"EventCode": "0x8110",
"EventName": "BR_IMMED_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted immediate branch"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted immediate branch",
"EventCode": "0x8111",
"EventName": "BR_IMMED_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted immediate branch"
},
{
"PublicDescription": "Instruction architecturally executed, predicted indirect branch",
"EventCode": "0x8112",
"EventName": "BR_IND_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted indirect branch"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",
"EventCode": "0x8113",
"EventName": "BR_IND_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"
},
{
"PublicDescription": "Instruction architecturally executed, predicted procedure return",
"EventCode": "0x8114",
"EventName": "BR_RETURN_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted procedure return"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted procedure return",
"EventCode": "0x8115",
"EventName": "BR_RETURN_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted procedure return"
},
{
"PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding return",
"EventCode": "0x8116",
"EventName": "BR_INDNR_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding return"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return",
"EventCode": "0x8117",
"EventName": "BR_INDNR_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return"
},
{
"PublicDescription": "Instruction architecturally executed, predicted branch, taken",
"EventCode": "0x8118",
"EventName": "BR_TAKEN_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted branch, taken"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted branch, taken",
"EventCode": "0x8119",
"EventName": "BR_TAKEN_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted branch, taken"
},
{
"PublicDescription": "Instruction architecturally executed, predicted branch, not taken",
"EventCode": "0x811a",
"EventName": "BR_SKIP_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted branch, not taken"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted branch, not taken",
"EventCode": "0x811b",
"EventName": "BR_SKIP_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted branch, not taken"
},
{
"PublicDescription": "Instruction architecturally executed, predicted branch",
"EventCode": "0x811c",
"EventName": "BR_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted branch"
},
{
"PublicDescription": "Instruction architecturally executed, indirect branch",
"EventCode": "0x811d",
"EventName": "BR_IND_RETIRED",
"BriefDescription": "Instruction architecturally executed, indirect branch"
},
{
"PublicDescription": "Branch Record captured.",
"EventCode": "0x811f",
"EventName": "BRB_FILTRATE",
"BriefDescription": "Branch Record captured."
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/bus.json
+20
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@@ -0,0 +1,20 @@
[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "CNT_CYCLES"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
+208
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[
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL",
"Errata": "Errata AC04_CPU_1",
"BriefDescription": "L1D cache invalidate. Impacted by errata -"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2I_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "L2I_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L1I_CACHE_LMISS"
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
},
{
"PublicDescription": "Level 1 data or unified cache demand access",
"EventCode": "0x8140",
"EventName": "L1D_CACHE_RW",
"BriefDescription": "Level 1 data or unified cache demand access"
},
{
"PublicDescription": "Level 1 data or unified cache preload or prefetch",
"EventCode": "0x8142",
"EventName": "L1D_CACHE_PRFM",
"BriefDescription": "Level 1 data or unified cache preload or prefetch"
},
{
"PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
"EventCode": "0x8146",
"EventName": "L1D_CACHE_REFILL_PRFM",
"BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
},
{
"ArchStdEvent": "L1D_TLB_RD"
},
{
"ArchStdEvent": "L1D_TLB_WR"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_TLB_RD"
},
{
"ArchStdEvent": "L2D_TLB_WR"
},
{
"PublicDescription": "L1D TLB miss",
"EventCode": "0xD600",
"EventName": "L1D_TLB_MISS",
"BriefDescription": "L1D TLB miss"
},
{
"PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
"EventCode": "0xd606",
"EventName": "L1_PREFETCH_LD_GEN",
"BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
},
{
"PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
"EventCode": "0xd607",
"EventName": "L1_PREFETCH_LD_FILL",
"BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
},
{
"PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
"EventCode": "0xd608",
"EventName": "L1_PREFETCH_L2_REQ",
"BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
},
{
"PublicDescription": "L1 prefetcher, distance was reset",
"EventCode": "0xd609",
"EventName": "L1_PREFETCH_DIST_RST",
"BriefDescription": "L1 prefetcher, distance was reset"
},
{
"PublicDescription": "L1 prefetcher, distance was increased",
"EventCode": "0xd60a",
"EventName": "L1_PREFETCH_DIST_INC",
"BriefDescription": "L1 prefetcher, distance was increased"
},
{
"PublicDescription": "Level 1 prefetcher, table entry is trained",
"EventCode": "0xd60b",
"EventName": "L1_PREFETCH_ENTRY_TRAINED",
"BriefDescription": "Level 1 prefetcher, table entry is trained"
},
{
"PublicDescription": "L1 data cache refill - Read or Write",
"EventCode": "0xd60e",
"EventName": "L1D_CACHE_REFILL_RW",
"BriefDescription": "L1 data cache refill - Read or Write"
},
{
"PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
"EventCode": "0xD701",
"EventName": "L2C_INST_REFILL",
"BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
},
{
"PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
"EventCode": "0xD702",
"EventName": "L2C_DATA_REFILL",
"BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
},
{
"PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
"EventCode": "0xD703",
"EventName": "L2_PREFETCH_REQ",
"BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/core-imp-def.json
+464
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[
{
"PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
"EventCode": "0x10A",
"EventName": "L2_PREFETCH_REFILL",
"BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
},
{
"PublicDescription": "Level 2 prefetch requests, late",
"EventCode": "0x10B",
"EventName": "L2_PREFETCH_UPGRADE",
"BriefDescription": "Level 2 prefetch requests, late"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
"EventCode": "0x110",
"EventName": "BPU_HIT_BTB",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
"EventCode": "0x111",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
"EventCode": "0x112",
"EventName": "BPU_HIT_INDIRECT_PREDICTOR",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
"EventCode": "0x113",
"EventName": "BPU_HIT_RSB",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
},
{
"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
"EventCode": "0x114",
"EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted",
"EventCode": "0x115",
"EventName": "BPU_BRANCH_NO_HIT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
"EventCode": "0x116",
"EventName": "BPU_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
"EventCode": "0x117",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
"EventCode": "0x118",
"EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
"EventCode": "0x119",
"EventName": "BPU_HIT_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
"EventCode": "0x11a",
"EventName": "BPU_MISS_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
"EventCode": "0x11b",
"EventName": "BPU_NO_PREDICTION_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
},
{
"PublicDescription": "Preditable branch update the BTB region buffer entry",
"EventCode": "0x11c",
"EventName": "BPU_BTB_UPDATE",
"BriefDescription": "Preditable branch update the BTB region buffer entry"
},
{
"PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
"EventCode": "0x11d",
"EventName": "BPU_RSB_FULL_STALL",
"BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
},
{
"PublicDescription": "Macro-ops speculatively decoded",
"EventCode": "0x11f",
"EventName": "ICF_INST_SPEC_DECODE",
"BriefDescription": "Macro-ops speculatively decoded"
},
{
"PublicDescription": "Flushes",
"EventCode": "0x120",
"EventName": "GPC_FLUSH",
"BriefDescription": "Flushes"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "GPC_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
},
{
"PublicDescription": "ETM extout bit 0",
"EventCode": "0x141",
"EventName": "MSC_ETM_EXTOUT0",
"BriefDescription": "ETM extout bit 0"
},
{
"PublicDescription": "ETM extout bit 1",
"EventCode": "0x142",
"EventName": "MSC_ETM_EXTOUT1",
"BriefDescription": "ETM extout bit 1"
},
{
"PublicDescription": "ETM extout bit 2",
"EventCode": "0x143",
"EventName": "MSC_ETM_EXTOUT2",
"BriefDescription": "ETM extout bit 2"
},
{
"PublicDescription": "ETM extout bit 3",
"EventCode": "0x144",
"EventName": "MSC_ETM_EXTOUT3",
"BriefDescription": "ETM extout bit 3"
},
{
"PublicDescription": "Bus request sn",
"EventCode": "0x156",
"EventName": "L2C_SNOOP",
"BriefDescription": "Bus request sn"
},
{
"PublicDescription": "L2 TXDAT LCRD blocked",
"EventCode": "0x169",
"EventName": "L2C_DAT_CRD_STALL",
"BriefDescription": "L2 TXDAT LCRD blocked"
},
{
"PublicDescription": "L2 TXRSP LCRD blocked",
"EventCode": "0x16a",
"EventName": "L2C_RSP_CRD_STALL",
"BriefDescription": "L2 TXRSP LCRD blocked"
},
{
"PublicDescription": "L2 TXREQ LCRD blocked",
"EventCode": "0x16b",
"EventName": "L2C_REQ_CRD_STALL",
"BriefDescription": "L2 TXREQ LCRD blocked"
},
{
"PublicDescription": "Early mispredict",
"EventCode": "0xD100",
"EventName": "ICF_EARLY_MIS_PRED",
"BriefDescription": "Early mispredict"
},
{
"PublicDescription": "FEQ full cycles",
"EventCode": "0xD101",
"EventName": "ICF_FEQ_FULL",
"BriefDescription": "FEQ full cycles"
},
{
"PublicDescription": "Instruction FIFO Full",
"EventCode": "0xD102",
"EventName": "ICF_INST_FIFO_FULL",
"BriefDescription": "Instruction FIFO Full"
},
{
"PublicDescription": "L1I TLB miss",
"EventCode": "0xD103",
"EventName": "L1I_TLB_MISS",
"BriefDescription": "L1I TLB miss"
},
{
"PublicDescription": "ICF sent 0 instructions to IDR this cycle",
"EventCode": "0xD104",
"EventName": "ICF_STALL",
"BriefDescription": "ICF sent 0 instructions to IDR this cycle"
},
{
"PublicDescription": "PC FIFO Full",
"EventCode": "0xD105",
"EventName": "ICF_PC_FIFO_FULL",
"BriefDescription": "PC FIFO Full"
},
{
"PublicDescription": "Stall due to BOB ID",
"EventCode": "0xD200",
"EventName": "IDR_STALL_BOB_ID",
"BriefDescription": "Stall due to BOB ID"
},
{
"PublicDescription": "Dispatch stall due to LOB entries",
"EventCode": "0xD201",
"EventName": "IDR_STALL_LOB_ID",
"BriefDescription": "Dispatch stall due to LOB entries"
},
{
"PublicDescription": "Dispatch stall due to SOB entries",
"EventCode": "0xD202",
"EventName": "IDR_STALL_SOB_ID",
"BriefDescription": "Dispatch stall due to SOB entries"
},
{
"PublicDescription": "Dispatch stall due to IXU scheduler entries",
"EventCode": "0xD203",
"EventName": "IDR_STALL_IXU_SCHED",
"BriefDescription": "Dispatch stall due to IXU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to FSU scheduler entries",
"EventCode": "0xD204",
"EventName": "IDR_STALL_FSU_SCHED",
"BriefDescription": "Dispatch stall due to FSU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to ROB entries",
"EventCode": "0xD205",
"EventName": "IDR_STALL_ROB_ID",
"BriefDescription": "Dispatch stall due to ROB entries"
},
{
"PublicDescription": "Dispatch stall due to flush",
"EventCode": "0xD206",
"EventName": "IDR_STALL_FLUSH",
"BriefDescription": "Dispatch stall due to flush"
},
{
"PublicDescription": "Dispatch stall due to WFI",
"EventCode": "0xD207",
"EventName": "IDR_STALL_WFI",
"BriefDescription": "Dispatch stall due to WFI"
},
{
"PublicDescription": "Number of SWOB drains triggered by timeout",
"EventCode": "0xD208",
"EventName": "IDR_STALL_SWOB_TIMEOUT",
"BriefDescription": "Number of SWOB drains triggered by timeout"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
"EventCode": "0xD209",
"EventName": "IDR_STALL_SWOB_RAW",
"BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
"EventCode": "0xD20A",
"EventName": "IDR_STALL_SWOB_FULL",
"BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
},
{
"PublicDescription": "Dispatch stall due to L1 instruction cache miss",
"EventCode": "0xD20B",
"EventName": "STALL_FRONTEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 instruction cache miss"
},
{
"PublicDescription": "Dispatch stall due to L1 data cache miss",
"EventCode": "0xD20D",
"EventName": "STALL_BACKEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 data cache miss"
},
{
"PublicDescription": "Dispatch stall due to lack of any core resource",
"EventCode": "0xD20F",
"EventName": "STALL_BACKEND_RESOURCE",
"BriefDescription": "Dispatch stall due to lack of any core resource"
},
{
"PublicDescription": "Instructions issued by the scheduler",
"EventCode": "0xD300",
"EventName": "IXU_NUM_UOPS_ISSUED",
"BriefDescription": "Instructions issued by the scheduler"
},
{
"PublicDescription": "Any uop issued was canceled for any reason",
"EventCode": "0xD301",
"EventName": "IXU_ISSUE_CANCEL",
"BriefDescription": "Any uop issued was canceled for any reason"
},
{
"PublicDescription": "A load wakeup to the scheduler has been canceled",
"EventCode": "0xD302",
"EventName": "IXU_LOAD_CANCEL",
"BriefDescription": "A load wakeup to the scheduler has been canceled"
},
{
"PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
"EventCode": "0xD303",
"EventName": "IXU_SLOW_CANCEL",
"BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA",
"EventCode": "0xD304",
"EventName": "IXU_IXA_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 0",
"EventCode": "0xD305",
"EventName": "IXU_IXA_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 1",
"EventCode": "0xD306",
"EventName": "IXU_IXA_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB",
"EventCode": "0xD307",
"EventName": "IXU_IXB_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 0",
"EventCode": "0xD308",
"EventName": "IXU_IXB_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 1",
"EventCode": "0xD309",
"EventName": "IXU_IXB_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC",
"EventCode": "0xD30A",
"EventName": "IXU_IXC_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 0",
"EventCode": "0xD30B",
"EventName": "IXU_IXC_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 1",
"EventCode": "0xD30C",
"EventName": "IXU_IXC_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD",
"EventCode": "0xD30D",
"EventName": "IXU_IXD_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 0",
"EventCode": "0xD30E",
"EventName": "IXU_IXD_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 1",
"EventCode": "0xD30F",
"EventName": "IXU_IXD_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 1"
},
{
"PublicDescription": "Uops issued by the FSU scheduler",
"EventCode": "0xD400",
"EventName": "FSU_ISSUED",
"BriefDescription": "Uops issued by the FSU scheduler"
},
{
"PublicDescription": "Uops issued by the scheduler on FSX",
"EventCode": "0xD401",
"EventName": "FSU_FSX_ISSUED",
"BriefDescription": "Uops issued by the scheduler on FSX"
},
{
"PublicDescription": "Uops issued by the scheduler on FSY",
"EventCode": "0xD402",
"EventName": "FSU_FSY_ISSUED",
"BriefDescription": "Uops issued by the scheduler on FSY"
},
{
"PublicDescription": "Uops issued by the scheduler on FSZ",
"EventCode": "0xD403",
"EventName": "FSU_FSZ_ISSUED",
"BriefDescription": "Uops issued by the scheduler on FSZ"
},
{
"PublicDescription": "Uops canceled (load cancels)",
"EventCode": "0xD404",
"EventName": "FSU_CANCEL",
"BriefDescription": "Uops canceled (load cancels)"
},
{
"PublicDescription": "Count scheduler stalls due to divide/sqrt",
"EventCode": "0xD405",
"EventName": "FSU_DIV_SQRT_STALL",
"BriefDescription": "Count scheduler stalls due to divide/sqrt"
},
{
"PublicDescription": "Number of SWOB drains",
"EventCode": "0xD500",
"EventName": "GPC_SWOB_DRAIN",
"BriefDescription": "Number of SWOB drains"
},
{
"PublicDescription": "GPC detected a Breakpoint instruction match",
"EventCode": "0xD501",
"EventName": "BREAKPOINT_MATCH",
"BriefDescription": "GPC detected a Breakpoint instruction match"
},
{
"PublicDescription": "Core progress monitor triggered",
"EventCode": "0xd502",
"EventName": "GPC_CPM_TRIGGER",
"BriefDescription": "Core progress monitor triggered"
},
{
"PublicDescription": "Fill buffer full",
"EventCode": "0xD601",
"EventName": "OFB_FULL",
"BriefDescription": "Fill buffer full"
},
{
"PublicDescription": "Load satisified from store forwarded data",
"EventCode": "0xD605",
"EventName": "LD_FROM_ST_FWD",
"BriefDescription": "Load satisified from store forwarded data"
},
{
"PublicDescription": "Store retirement pipe stall",
"EventCode": "0xD60C",
"EventName": "LSU_ST_RETIRE_STALL",
"BriefDescription": "Store retirement pipe stall"
},
{
"PublicDescription": "LSU detected a Watchpoint data match",
"EventCode": "0xD60D",
"EventName": "WATCHPOINT_MATCH",
"BriefDescription": "LSU detected a Watchpoint data match"
},
{
"PublicDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature",
"EventCode": "0xda00",
"EventName": "MSC_ETM_COMMIT_STALL",
"BriefDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/exception.json
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[
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "EXC_SMC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/instruction.json
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "OP_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"PublicDescription": "Operation speculatively executed - ASE Scalar",
"EventCode": "0xd210",
"EventName": "ASE_SCALAR_SPEC",
"BriefDescription": "Operation speculatively executed - ASE Scalar"
},
{
"PublicDescription": "Operation speculatively executed - ASE Vector",
"EventCode": "0xd211",
"EventName": "ASE_VECTOR_SPEC",
"BriefDescription": "Operation speculatively executed - ASE Vector"
},
{
"PublicDescription": "Barrier speculatively executed, CSDB",
"EventCode": "0x7f",
"EventName": "CSDB_SPEC",
"BriefDescription": "Barrier speculatively executed, CSDB"
},
{
"PublicDescription": "Prefetch sent to L2.",
"EventCode": "0xd106",
"EventName": "ICF_PREFETCH_DISPATCH",
"BriefDescription": "Prefetch sent to L2."
},
{
"PublicDescription": "Prefetch response received but was dropped since we don't support inflight upgrades.",
"EventCode": "0xd107",
"EventName": "ICF_PREFETCH_DROPPED_NO_UPGRADE",
"BriefDescription": "Prefetch response received but was dropped since we don't support inflight upgrades."
},
{
"PublicDescription": "Prefetch request missed TLB.",
"EventCode": "0xd108",
"EventName": "ICF_PREFETCH_DROPPED_TLB_MISS",
"BriefDescription": "Prefetch request missed TLB."
},
{
"PublicDescription": "Prefetch request dropped since duplicate was found in TLB.",
"EventCode": "0xd109",
"EventName": "ICF_PREFETCH_DROPPED_DUPLICATE",
"BriefDescription": "Prefetch request dropped since duplicate was found in TLB."
},
{
"PublicDescription": "Prefetch request dropped since it was found in cache.",
"EventCode": "0xd10a",
"EventName": "ICF_PREFETCH_DROPPED_CACHE_HIT",
"BriefDescription": "Prefetch request dropped since it was found in cache."
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/intrinsic.json
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[
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json
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[
{
"ArchStdEvent": "LD_RETIRED",
"Errata": "Errata AC04_CPU_21",
"BriefDescription": "Instruction architecturally executed, condition code check pass, load. Impacted by errata -"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "BPU_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
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[
{
"MetricName": "branch_miss_pred_rate",
"MetricExpr": "BR_MIS_PRED / BR_PRED",
"BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch",
"MetricGroup": "branch",
"ScaleUnit": "100%"
},
{
"MetricName": "bus_utilization",
"MetricExpr": "BUS_ACCESS / (BUS_CYCLES * 1)",
"BriefDescription": "Core-to-uncore bus utilization",
"MetricGroup": "Bus",
"ScaleUnit": "100percent of bus cycles"
},
{
"MetricName": "l1d_cache_miss_ratio",
"MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
"BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.",
"MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l1i_cache_miss_ratio",
"MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
"BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.",
"MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "Miss_Ratio;l1d_cache_read_miss",
"MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD",
"BriefDescription": "L1D cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache read access"
},
{
"MetricName": "l2_cache_miss_ratio",
"MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
"BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
"MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l1i_cache_read_miss_rate",
"MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE",
"BriefDescription": "L1I cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l2d_cache_read_miss_rate",
"MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD",
"BriefDescription": "L2 cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache read access"
},
{
"MetricName": "l1d_cache_miss_mpki",
"MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (data)",
"MetricGroup": "Cache",
"ScaleUnit": "1MPKI"
},
{
"MetricName": "l1i_cache_miss_mpki",
"MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (instruction)",
"MetricGroup": "Cache",
"ScaleUnit": "1MPKI"
},
{
"MetricName": "simd_percentage",
"MetricExpr": "ASE_SPEC / INST_SPEC",
"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "crypto_percentage",
"MetricExpr": "CRYPTO_SPEC / INST_SPEC",
"BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "gflops",
"MetricExpr": "VFP_SPEC / (duration_time * 1e9)",
"BriefDescription": "Giga-floating point operations per second",
"MetricGroup": "InstructionMix"
},
{
"MetricName": "integer_dp_percentage",
"MetricExpr": "DP_SPEC / INST_SPEC",
"BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "ipc",
"MetricExpr": "INST_RETIRED / CPU_CYCLES",
"BriefDescription": "This metric measures the number of instructions retired per cycle.",
"MetricGroup": "General",
"ScaleUnit": "1per cycle"
},
{
"MetricName": "load_percentage",
"MetricExpr": "LD_SPEC / INST_SPEC",
"BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "load_store_spec_rate",
"MetricExpr": "LDST_SPEC / INST_SPEC",
"BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speculatively executed",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "retired_mips",
"MetricExpr": "INST_RETIRED / (duration_time * 1e6)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "InstructionMix"
},
{
"MetricName": "spec_utilization_mips",
"MetricExpr": "INST_SPEC / (duration_time * 1e6)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "PEutilization"
},
{
"MetricName": "pc_write_spec_rate",
"MetricExpr": "PC_WRITE_SPEC / INST_SPEC",
"BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speculatively executed",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "store_percentage",
"MetricExpr": "ST_SPEC / INST_SPEC",
"BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "scalar_fp_percentage",
"MetricExpr": "VFP_SPEC / INST_SPEC",
"BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "retired_rate",
"MetricExpr": "OP_RETIRED / OP_SPEC",
"BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "wasted",
"MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
"BriefDescription": "Of all the micro-operations issued, what proportion are lost",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "wasted_rate",
"MetricExpr": "1 - OP_RETIRED / OP_SPEC",
"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "stall_backend_cache_rate",
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_backend_resource_rate",
"MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_backend_tlb_rate",
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_frontend_cache_rate",
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations delivered from frontend and cache miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_frontend_tlb_rate",
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations delivered from frontend and TLB miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "dtlb_walk_ratio",
"MetricExpr": "DTLB_WALK / L1D_TLB",
"BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.",
"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
"ScaleUnit": "1per TLB access"
},
{
"MetricName": "itlb_walk_ratio",
"MetricExpr": "ITLB_WALK / L1I_TLB",
"BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.",
"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
"ScaleUnit": "1per TLB access"
},
{
"ArchStdEvent": "backend_bound"
},
{
"ArchStdEvent": "frontend_bound",
"MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)"
},
{
"MetricName": "slots_lost_misspeculation_fraction",
"MetricExpr": "100 * (OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots)",
"BriefDescription": "Fraction of slots lost due to misspeculation",
"DefaultMetricgroupName": "TopdownL1",
"MetricGroup": "Default;TopdownL1",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "retired_fraction",
"MetricExpr": "100 * OP_RETIRED / (CPU_CYCLES * #slots)",
"BriefDescription": "Fraction of slots retiring, useful work",
"DefaultMetricgroupName": "TopdownL1",
"MetricGroup": "Default;TopdownL1",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "backend_core",
"MetricExpr": "(backend_bound / 100) - backend_memory",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_memory",
"MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"MetricName": "branch_mispredict",
"MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction",
"BriefDescription": "Fraction of slots lost due to branch misprediciton",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "frontend_bandwidth",
"MetricExpr": "frontend_bound - 100 * frontend_latency",
"BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "frontend_latency",
"MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES",
"BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "other_miss_pred",
"MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict",
"BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "pipe_utilization",
"MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))",
"BriefDescription": "Fraction of execute slots utilized",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "d_cache_l2_miss_rate",
"MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "d_cache_miss_rate",
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "d_tlb_miss_rate",
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "fsu_pipe_utilization",
"MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)",
"BriefDescription": "Fraction of FSU execute slots utilized",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "i_cache_miss_rate",
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "i_tlb_miss_rate",
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "ixu_pipe_utilization",
"MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)",
"BriefDescription": "Fraction of IXU execute slots utilized",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "stall_recovery_rate",
"MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "stall_fsu_sched_rate",
"MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_ixu_sched_rate",
"MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_lob_id_rate",
"MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_rob_id_rate",
"MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_sob_id_rate",
"MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "l1d_cache_access_demand",
"MetricExpr": "L1D_CACHE_RW / L1D_CACHE",
"BriefDescription": "L1D cache access - demand",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "l1d_cache_access_prefetches",
"MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE",
"BriefDescription": "L1D cache access - prefetch",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "l1d_cache_demand_misses",
"MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE",
"BriefDescription": "L1D cache demand misses",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "l1d_cache_demand_misses_read",
"MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE",
"BriefDescription": "L1D cache demand misses - read",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "l1d_cache_demand_misses_write",
"MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE",
"BriefDescription": "L1D cache demand misses - write",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "l1d_cache_prefetch_misses",
"MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE",
"BriefDescription": "L1D cache prefetch misses",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "ase_scalar_mix",
"MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC",
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations",
"MetricGroup": "Instructions",
"ScaleUnit": "100percent of cache accesses"
},
{
"MetricName": "ase_vector_mix",
"MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC",
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations",
"MetricGroup": "Instructions",
"ScaleUnit": "100percent of cache accesses"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
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[
{
"PublicDescription": "Level 2 data translation buffer allocation",
"EventCode": "0xD800",
"EventName": "MMU_D_OTB_ALLOC",
"BriefDescription": "Level 2 data translation buffer allocation"
},
{
"PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
"EventCode": "0xd801",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
"EventCode": "0xd802",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
"EventCode": "0xd803",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
"EventCode": "0xd804",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
"EventCode": "0xd805",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry",
"EventCode": "0xd806",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescrition": "Data-side S1 page walk cache lookup",
"EventCode": "0xd807",
"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "Data-side S1 page walk cache lookup"
},
{
"PublicDescrition": "Data-side S1 page walk cache refill",
"EventCode": "0xd808",
"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
"BriefDescription": "Data-side S1 page walk cache refill"
},
{
"PublicDescrition": "Data-side S2 page walk cache lookup",
"EventCode": "0xd809",
"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "Data-side S2 page walk cache lookup"
},
{
"PublicDescrition": "Data-side S2 page walk cache refill",
"EventCode": "0xd80a",
"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
"BriefDescription": "Data-side S2 page walk cache refill"
},
{
"PublicDescription": "Data-side S1 table walk fault",
"EventCode": "0xD80B",
"EventName": "MMU_D_S1_WALK_FAULT",
"BriefDescription": "Data-side S1 table walk fault"
},
{
"PublicDescription": "Data-side S2 table walk fault",
"EventCode": "0xD80C",
"EventName": "MMU_D_S2_WALK_FAULT",
"BriefDescription": "Data-side S2 table walk fault"
},
{
"PublicDescription": "Data-side table walk steps or descriptor fetches",
"EventCode": "0xD80D",
"EventName": "MMU_D_WALK_STEPS",
"BriefDescription": "Data-side table walk steps or descriptor fetches"
},
{
"PublicDescription": "Level 2 instruction translation buffer allocation",
"EventCode": "0xD900",
"EventName": "MMU_I_OTB_ALLOC",
"BriefDescription": "Level 2 instruction translation buffer allocation"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry",
"EventCode": "0xd901",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry",
"EventCode": "0xd902",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry",
"EventCode": "0xd903",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry",
"EventCode": "0xd904",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry",
"EventCode": "0xd905",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry",
"EventCode": "0xd906",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescrition": "Instruction-side S1 page walk cache lookup",
"EventCode": "0xd907",
"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "Instruction-side S1 page walk cache lookup"
},
{
"PublicDescrition": "Instruction-side S1 page walk cache refill",
"EventCode": "0xd908",
"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
"BriefDescription": "Instruction-side S1 page walk cache refill"
},
{
"PublicDescrition": "Instruction-side S2 page walk cache lookup",
"EventCode": "0xd909",
"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "Instruction-side S2 page walk cache lookup"
},
{
"PublicDescrition": "Instruction-side S2 page walk cache refill",
"EventCode": "0xd90a",
"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
"BriefDescription": "Instruction-side S2 page walk cache refill"
},
{
"PublicDescription": "Instruction-side S1 table walk fault",
"EventCode": "0xD90B",
"EventName": "MMU_I_S1_WALK_FAULT",
"BriefDescription": "Instruction-side S1 table walk fault"
},
{
"PublicDescription": "Instruction-side S2 table walk fault",
"EventCode": "0xD90C",
"EventName": "MMU_I_S2_WALK_FAULT",
"BriefDescription": "Instruction-side S2 table walk fault"
},
{
"PublicDescription": "Instruction-side table walk steps or descriptor fetches",
"EventCode": "0xD90D",
"EventName": "MMU_I_WALK_STEPS",
"BriefDescription": "Instruction-side table walk steps or descriptor fetches"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/pipeline.json
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[
{
"ArchStdEvent": "STALL_FRONTEND",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"ArchStdEvent": "STALL",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND"
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_SLOT"
},
{
"ArchStdEvent": "STALL_BACKEND_MEM"
},
{
"PublicDescription": "Frontend stall cycles, TLB",
"EventCode": "0x815c",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "Frontend stall cycles, TLB"
},
{
"PublicDescription": "Backend stall cycles, TLB",
"EventCode": "0x8167",
"EventName": "STALL_BACKEND_TLB",
"BriefDescription": "Backend stall cycles, TLB"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/spe.json
+14
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[
{
"ArchStdEvent": "SAMPLE_POP"
},
{
"ArchStdEvent": "SAMPLE_FEED"
},
{
"ArchStdEvent": "SAMPLE_FILTRATE"
},
{
"ArchStdEvent": "SAMPLE_COLLISION"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
+19
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[
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "BR_MIS_PRED",
"BriefDescription": "Branch mispredicted"
},
{
"ArchStdEvent": "BR_PRED",
"BriefDescription": "Predictable branch"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
+23
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[
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH"
},
{
"ArchStdEvent": "BUS_ACCESS"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
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[
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
"ArchStdEvent": "L1D_TLB",
"BriefDescription": "L1D TLB access"
},
{
"PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",
"ArchStdEvent": "L1I_TLB"
},
{
"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",
"EventCode": "0x34",
"EventName": "L2D_TLB_ACCESS",
"BriefDescription": "L2D TLB access"
},
{
"PublicDescription": "Level 2 access to instruction TLB that caused a page table walk. This event counts on any instruction access which causes L2I_TLB_REFILL to count",
"EventCode": "0x35",
"EventName": "L2I_TLB_ACCESS",
"BriefDescription": "L2I TLB access"
},
{
"PublicDescription": "Branch target buffer misprediction",
"EventCode": "0x102",
"EventName": "BTB_MIS_PRED",
"BriefDescription": "BTB misprediction"
},
{
"PublicDescription": "ITB miss",
"EventCode": "0x103",
"EventName": "ITB_MISS",
"BriefDescription": "ITB miss"
},
{
"PublicDescription": "DTB miss",
"EventCode": "0x104",
"EventName": "DTB_MISS",
"BriefDescription": "DTB miss"
},
{
"PublicDescription": "Level 1 data cache late miss",
"EventCode": "0x105",
"EventName": "L1D_CACHE_LATE_MISS",
"BriefDescription": "L1D cache late miss"
},
{
"PublicDescription": "Level 1 data cache prefetch request",
"EventCode": "0x106",
"EventName": "L1D_CACHE_PREFETCH",
"BriefDescription": "L1D cache prefetch"
},
{
"PublicDescription": "Level 2 data cache prefetch request",
"EventCode": "0x107",
"EventName": "L2D_CACHE_PREFETCH",
"BriefDescription": "L2D cache prefetch"
},
{
"PublicDescription": "Level 1 stage 2 TLB refill",
"EventCode": "0x111",
"EventName": "L1_STAGE2_TLB_REFILL",
"BriefDescription": "L1 stage 2 TLB refill"
},
{
"PublicDescription": "Page walk cache level-0 stage-1 hit",
"EventCode": "0x112",
"EventName": "PAGE_WALK_L0_STAGE1_HIT",
"BriefDescription": "Page walk, L0 stage-1 hit"
},
{
"PublicDescription": "Page walk cache level-1 stage-1 hit",
"EventCode": "0x113",
"EventName": "PAGE_WALK_L1_STAGE1_HIT",
"BriefDescription": "Page walk, L1 stage-1 hit"
},
{
"PublicDescription": "Page walk cache level-2 stage-1 hit",
"EventCode": "0x114",
"EventName": "PAGE_WALK_L2_STAGE1_HIT",
"BriefDescription": "Page walk, L2 stage-1 hit"
},
{
"PublicDescription": "Page walk cache level-1 stage-2 hit",
"EventCode": "0x115",
"EventName": "PAGE_WALK_L1_STAGE2_HIT",
"BriefDescription": "Page walk, L1 stage-2 hit"
},
{
"PublicDescription": "Page walk cache level-2 stage-2 hit",
"EventCode": "0x116",
"EventName": "PAGE_WALK_L2_STAGE2_HIT",
"BriefDescription": "Page walk, L2 stage-2 hit"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
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[
{
"PublicDescription": "The number of core clock cycles",
"ArchStdEvent": "CPU_CYCLES"
},
{
"PublicDescription": "FSU clocking gated off cycle",
"EventCode": "0x101",
"EventName": "FSU_CLOCK_OFF_CYCLES",
"BriefDescription": "FSU clocking gated off cycle"
},
{
"PublicDescription": "Wait state cycle",
"EventCode": "0x110",
"EventName": "Wait_CYCLES",
"BriefDescription": "Wait state cycle"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
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[
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "EXC_RETURN"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
+73
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[
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"PublicDescription": "Instruction architecturally executed, software increment",
"ArchStdEvent": "SW_INCR",
"BriefDescription": "Software increment"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED",
"BriefDescription": "Write to CONTEXTIDR"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches",
"ArchStdEvent": "BR_RETIRED"
},
{
"PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush",
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"PublicDescription": "Operation speculatively executed, NOP",
"EventCode": "0x100",
"EventName": "NOP_SPEC",
"BriefDescription": "Speculatively executed, NOP"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json
+14
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[
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
+24
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[
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
"ArchStdEvent": "MEMORY_ERROR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json
+50
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[
{
"PublicDescription": "Decode starved for instruction cycle",
"EventCode": "0x108",
"EventName": "DECODE_STALL",
"BriefDescription": "Decode starved"
},
{
"PublicDescription": "Op dispatch stalled cycle",
"EventCode": "0x109",
"EventName": "DISPATCH_STALL",
"BriefDescription": "Dispatch stalled"
},
{
"PublicDescription": "IXA Op non-issue",
"EventCode": "0x10a",
"EventName": "IXA_STALL",
"BriefDescription": "IXA stalled"
},
{
"PublicDescription": "IXB Op non-issue",
"EventCode": "0x10b",
"EventName": "IXB_STALL",
"BriefDescription": "IXB stalled"
},
{
"PublicDescription": "BX Op non-issue",
"EventCode": "0x10c",
"EventName": "BX_STALL",
"BriefDescription": "BX stalled"
},
{
"PublicDescription": "LX Op non-issue",
"EventCode": "0x10d",
"EventName": "LX_STALL",
"BriefDescription": "LX stalled"
},
{
"PublicDescription": "SX Op non-issue",
"EventCode": "0x10e",
"EventName": "SX_STALL",
"BriefDescription": "SX stalled"
},
{
"PublicDescription": "FX Op non-issue",
"EventCode": "0x10f",
"EventName": "FX_STALL",
"BriefDescription": "FX stalled"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/cmn.json
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[
{
"EventName": "hnf_cache_miss",
"EventidCode": "0x1",
"NodeType": "0x5",
"BriefDescription": "Counts total cache misses in first lookup result (high priority).",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_slc_sf_cache_access",
"EventidCode": "0x2",
"NodeType": "0x5",
"BriefDescription": "Counts number of cache accesses in first access (high priority).",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_cache_fill",
"EventidCode": "0x3",
"NodeType": "0x5",
"BriefDescription": "Counts total allocations in HN SLC (all cache line allocations to SLC).",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_pocq_retry",
"EventidCode": "0x4",
"NodeType": "0x5",
"BriefDescription": "Counts number of retried requests.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_pocq_reqs_recvd",
"EventidCode": "0x5",
"NodeType": "0x5",
"BriefDescription": "Counts number of requests that HN receives.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_sf_hit",
"EventidCode": "0x6",
"NodeType": "0x5",
"BriefDescription": "Counts number of SF hits.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_sf_evictions",
"EventidCode": "0x7",
"NodeType": "0x5",
"BriefDescription": "Counts number of SF eviction cache invalidations initiated.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_dir_snoops_sent",
"EventidCode": "0x8",
"NodeType": "0x5",
"BriefDescription": "Counts number of directed snoops sent (not including SF back invalidation).",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_brd_snoops_sent",
"EventidCode": "0x9",
"NodeType": "0x5",
"BriefDescription": "Counts number of multicast snoops sent (not including SF back invalidation).",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_slc_eviction",
"EventidCode": "0xa",
"NodeType": "0x5",
"BriefDescription": "Counts number of SLC evictions (dirty only).",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_slc_fill_invalid_way",
"EventidCode": "0xb",
"NodeType": "0x5",
"BriefDescription": "Counts number of SLC fills to an invalid way.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_mc_retries",
"EventidCode": "0xc",
"NodeType": "0x5",
"BriefDescription": "Counts number of retried transactions by the MC.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_mc_reqs",
"EventidCode": "0xd",
"NodeType": "0x5",
"BriefDescription": "Counts number of requests that are sent to MC.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hnf_qos_hh_retry",
"EventidCode": "0xe",
"NodeType": "0x5",
"BriefDescription": "Counts number of times a HighHigh priority request is protocolretried at the HN-F.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_s0_rdata_beats",
"EventidCode": "0x1",
"NodeType": "0xa",
"BriefDescription": "Number of RData beats (RVALID and RREADY) dispatched on port 0. This event measures the read bandwidth, including CMO responses.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_s1_rdata_beats",
"EventidCode": "0x2",
"NodeType": "0xa",
"BriefDescription": "Number of RData beats (RVALID and RREADY) dispatched on port 1. This event measures the read bandwidth, including CMO responses.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_s2_rdata_beats",
"EventidCode": "0x3",
"NodeType": "0xa",
"BriefDescription": "Number of RData beats (RVALID and RREADY) dispatched on port 2. This event measures the read bandwidth, including CMO responses.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_rxdat_flits",
"EventidCode": "0x4",
"NodeType": "0xa",
"BriefDescription": "Number of RXDAT flits received. This event measures the true read data bandwidth, excluding CMOs.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_txdat_flits",
"EventidCode": "0x5",
"NodeType": "0xa",
"BriefDescription": "Number of TXDAT flits dispatched. This event measures the write bandwidth.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_txreq_flits_total",
"EventidCode": "0x6",
"NodeType": "0xa",
"BriefDescription": "Number of TXREQ flits dispatched. This event measures the total request bandwidth.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "rnid_txreq_flits_retried",
"EventidCode": "0x7",
"NodeType": "0xa",
"BriefDescription": "Number of retried TXREQ flits dispatched. This event measures the retry rate.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "sbsx_txrsp_retryack",
"EventidCode": "0x4",
"NodeType": "0x7",
"BriefDescription": "Number of RXREQ flits dispatched. This event is a measure of the retry rate.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "sbsx_txdat_flitv",
"EventidCode": "0x5",
"NodeType": "0x7",
"BriefDescription": "Number of TXDAT flits dispatched from XP to SBSX. This event is a measure of the write bandwidth.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "sbsx_arvalid_no_arready",
"EventidCode": "0x21",
"NodeType": "0x7",
"BriefDescription": "Number of cycles the SBSX bridge is stalled because of backpressure on AR channel.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "sbsx_awvalid_no_awready",
"EventidCode": "0x22",
"NodeType": "0x7",
"BriefDescription": "Number of cycles the SBSX bridge is stalled because of backpressure on AW channel.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "sbsx_wvalid_no_wready",
"EventidCode": "0x23",
"NodeType": "0x7",
"BriefDescription": "Number of cycles the SBSX bridge is stalled because of backpressure on W channel.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_txrsp_retryack",
"EventidCode": "0x2a",
"NodeType": "0x4",
"BriefDescription": "Number of RXREQ flits dispatched. This event is a measure of the retry rate.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_arvalid_no_arready",
"EventidCode": "0x2b",
"NodeType": "0x4",
"BriefDescription": "Number of cycles the HN-I bridge is stalled because of backpressure on AR channel.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_arready_no_arvalid",
"EventidCode": "0x2c",
"NodeType": "0x4",
"BriefDescription": "Number of cycles the AR channel is waiting for new requests from HN-I bridge.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_awvalid_no_awready",
"EventidCode": "0x2d",
"NodeType": "0x4",
"BriefDescription": "Number of cycles the HN-I bridge is stalled because of backpressure on AW channel.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_awready_no_awvalid",
"EventidCode": "0x2e",
"NodeType": "0x4",
"BriefDescription": "Number of cycles the AW channel is waiting for new requests from HN-I bridge.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_wvalid_no_wready",
"EventidCode": "0x2f",
"NodeType": "0x4",
"BriefDescription": "Number of cycles the HN-I bridge is stalled because of backpressure on W channel.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"EventName": "hni_txdat_stall",
"EventidCode": "0x30",
"NodeType": "0x4",
"BriefDescription": "TXDAT valid but no link credit available.",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/metric.json
+74
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[
{
"MetricName": "slc_miss_rate",
"BriefDescription": "The system level cache miss rate.",
"MetricGroup": "cmn",
"MetricExpr": "hnf_cache_miss / hnf_slc_sf_cache_access",
"ScaleUnit": "100%",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "hnf_message_retry_rate",
"BriefDescription": "HN-F message retry rate indicates whether a lack of credits is causing the bottlenecks.",
"MetricGroup": "cmn",
"MetricExpr": "hnf_pocq_retry / hnf_pocq_reqs_recvd",
"ScaleUnit": "100%",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "sf_hit_rate",
"BriefDescription": "Snoop filter hit rate can be used to measure the snoop filter efficiency.",
"MetricGroup": "cmn",
"MetricExpr": "hnf_sf_hit / hnf_slc_sf_cache_access",
"ScaleUnit": "100%",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "mc_message_retry_rate",
"BriefDescription": "The memory controller request retries rate indicates whether the memory controller is the bottleneck.",
"MetricGroup": "cmn",
"MetricExpr": "hnf_mc_retries / hnf_mc_reqs",
"ScaleUnit": "100%",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "rni_actual_read_bandwidth.all",
"BriefDescription": "This event measure the actual bandwidth that RN-I bridge sends to the interconnect.",
"MetricGroup": "cmn",
"MetricExpr": "rnid_rxdat_flits * 32 / 1e6 / duration_time",
"ScaleUnit": "1MB/s",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "rni_actual_write_bandwidth.all",
"BriefDescription": "This event measures the actual write bandwidth at RN-I bridges.",
"MetricGroup": "cmn",
"MetricExpr": "rnid_txdat_flits * 32 / 1e6 / duration_time",
"ScaleUnit": "1MB/s",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "rni_retry_rate",
"BriefDescription": "RN-I bridge retry rate indicates whether the memory controller is the bottleneck.",
"MetricGroup": "cmn",
"MetricExpr": "rnid_txreq_flits_retried / rnid_txreq_flits_total",
"ScaleUnit": "100%",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
},
{
"MetricName": "sbsx_actual_write_bandwidth.all",
"BriefDescription": "sbsx actual write bandwidth.",
"MetricGroup": "cmn",
"MetricExpr": "sbsx_txdat_flitv * 32 / 1e6 / duration_time",
"ScaleUnit": "1MB/s",
"Unit": "arm_cmn",
"Compat": "(434|436|43c|43a).*"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
+11
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
+17
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
+32
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
+14
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[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
+29
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
+8
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[
{
"ArchStdEvent": "UNALIGNED_LDST_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
+11
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
+17
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
+32
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
+14
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@@ -0,0 +1,14 @@
[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
+44
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
+8
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@@ -0,0 +1,8 @@
[
{
"ArchStdEvent": "UNALIGNED_LDST_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
+59
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"PublicDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
"EventCode": "0xC9",
"EventName": "BR_COND_PRED",
"BriefDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
},
{
"PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MIS_PRED",
"BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_ADDR_MIS_PRED",
"BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count",
"EventCode": "0xCC",
"EventName": "BR_COND_MIS_PRED",
"BriefDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count"
},
{
"PublicDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCD",
"EventName": "BR_INDIRECT_ADDR_PRED",
"BriefDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCE",
"EventName": "BR_RETURN_ADDR_PRED",
"BriefDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCF",
"EventName": "BR_RETURN_ADDR_MIS_PRED",
"BriefDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
+17
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
+182
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L3D_CACHE"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "LL_CACHE_RD"
},
{
"ArchStdEvent": "LL_CACHE_MISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L3D_CACHE_RD"
},
{
"ArchStdEvent": "L3D_CACHE_REFILL_RD"
},
{
"PublicDescription": "L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented",
"EventCode": "0xC1",
"EventName": "L2D_CACHE_REFILL_PREFETCH",
"BriefDescription": "L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented"
},
{
"PublicDescription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache",
"EventCode": "0xC2",
"EventName": "L1D_CACHE_REFILL_PREFETCH",
"BriefDescription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache"
},
{
"PublicDescription": "L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache",
"EventCode": "0xC3",
"EventName": "L2D_WS_MODE",
"BriefDescription": "L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache"
},
{
"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode",
"EventCode": "0xC4",
"EventName": "L1D_WS_MODE_ENTRY",
"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode"
},
{
"PublicDescription": "L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache",
"EventCode": "0xC5",
"EventName": "L1D_WS_MODE",
"BriefDescription": "L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache"
},
{
"PublicDescription": "L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache",
"EventCode": "0xC7",
"EventName": "L3D_WS_MODE",
"BriefDescription": "L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache"
},
{
"PublicDescription": "Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache",
"EventCode": "0xC8",
"EventName": "LL_WS_MODE",
"BriefDescription": "Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache"
},
{
"PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
"EventCode": "0xD0",
"EventName": "L2D_WALK_TLB",
"BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
"EventCode": "0xD1",
"EventName": "L2D_WALK_TLB_REFILL",
"BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count",
"EventCode": "0xD4",
"EventName": "L2D_S2_TLB",
"BriefDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count"
},
{
"PublicDescription": "L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count",
"EventCode": "0xD5",
"EventName": "L2D_S2_TLB_REFILL",
"BriefDescription": "L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count"
},
{
"PublicDescription": "L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request",
"EventCode": "0xD6",
"EventName": "L2D_CACHE_STASH_DROPPED",
"BriefDescription": "L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request"
},
{
"ArchStdEvent": "L1I_CACHE_LMISS"
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L3D_CACHE_LMISS_RD"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
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[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
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[
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "OP_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "SVE_INST_RETIRED"
},
{
"ArchStdEvent": "SVE_INST_SPEC"
},
{
"ArchStdEvent": "FP_HP_SPEC"
},
{
"ArchStdEvent": "FP_SP_SPEC"
},
{
"ArchStdEvent": "FP_DP_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT8_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT16_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT32_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT64_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
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[
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "REMOTE_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
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[
{
"ArchStdEvent": "STALL_FRONTEND"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"ArchStdEvent": "STALL"
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND"
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND"
},
{
"ArchStdEvent": "STALL_SLOT"
},
{
"PublicDescription": "No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed",
"EventCode": "0xE1",
"EventName": "STALL_FRONTEND_CACHE",
"BriefDescription": "No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed"
},
{
"PublicDescription": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed",
"EventCode": "0xE2",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed"
},
{
"PublicDescription": "No operation issued due to the frontend, pre-decode error",
"EventCode": "0xE3",
"EventName": "STALL_FRONTEND_PDERR",
"BriefDescription": "No operation issued due to the frontend, pre-decode error"
},
{
"PublicDescription": "No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded",
"EventCode": "0xE4",
"EventName": "STALL_BACKEND_ILOCK",
"BriefDescription": "No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded"
},
{
"PublicDescription": "No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded",
"EventCode": "0xE5",
"EventName": "STALL_BACKEND_ILOCK_ADDR",
"BriefDescription": "No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded"
},
{
"PublicDescription": "No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded",
"EventCode": "0xE6",
"EventName": "STALL_BACKEND_ILOCK_VPU",
"BriefDescription": "No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded"
},
{
"PublicDescription": "No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load",
"EventCode": "0xE7",
"EventName": "STALL_BACKEND_LD",
"BriefDescription": "No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load"
},
{
"PublicDescription": "No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store",
"EventCode": "0xE8",
"EventName": "STALL_BACKEND_ST",
"BriefDescription": "No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store"
},
{
"PublicDescription": "No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable",
"EventCode": "0xE9",
"EventName": "STALL_BACKEND_LD_CACHE",
"BriefDescription": "No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable"
},
{
"PublicDescription": "No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB",
"EventCode": "0xEA",
"EventName": "STALL_BACKEND_LD_TLB",
"BriefDescription": "No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB"
},
{
"PublicDescription": "No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full",
"EventCode": "0xEB",
"EventName": "STALL_BACKEND_ST_STB",
"BriefDescription": "No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full"
},
{
"PublicDescription": "No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB",
"EventCode": "0xEC",
"EventName": "STALL_BACKEND_ST_TLB",
"BriefDescription": "No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB"
},
{
"PublicDescription": "No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core",
"EventCode": "0xED",
"EventName": "STALL_BACKEND_VPU_HAZARD",
"BriefDescription": "No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core"
},
{
"PublicDescription": "Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock",
"EventCode": "0xEE",
"EventName": "STALL_SLOT_BACKEND_ILOCK",
"BriefDescription": "Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock"
},
{
"ArchStdEvent": "STALL_BACKEND_MEM"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
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[
{
"ArchStdEvent": "TRB_WRAP"
},
{
"ArchStdEvent": "TRB_TRIG"
},
{
"ArchStdEvent": "TRCEXTOUT0"
},
{
"ArchStdEvent": "TRCEXTOUT1"
},
{
"ArchStdEvent": "TRCEXTOUT2"
},
{
"ArchStdEvent": "TRCEXTOUT3"
},
{
"ArchStdEvent": "CTI_TRIGOUT4"
},
{
"ArchStdEvent": "CTI_TRIGOUT5"
},
{
"ArchStdEvent": "CTI_TRIGOUT6"
},
{
"ArchStdEvent": "CTI_TRIGOUT7"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
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[
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"EventCode": "0xC9",
"EventName": "BR_COND",
"BriefDescription": "Conditional branch executed"
},
{
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MISPRED",
"BriefDescription": "Indirect branch mispredicted"
},
{
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_MISPRED_ADDR",
"BriefDescription": "Indirect branch mispredicted because of address miscompare"
},
{
"EventCode": "0xCC",
"EventName": "BR_COND_MISPRED",
"BriefDescription": "Conditional branch mispredicted"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
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[
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
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[
{
"EventCode": "0xC2",
"EventName": "PREFETCH_LINEFILL",
"BriefDescription": "Linefill because of prefetch"
},
{
"EventCode": "0xC3",
"EventName": "PREFETCH_LINEFILL_DROP",
"BriefDescription": "Instruction Cache Throttle occurred"
},
{
"EventCode": "0xC4",
"EventName": "READ_ALLOC_ENTER",
"BriefDescription": "Entering read allocate mode"
},
{
"EventCode": "0xC5",
"EventName": "READ_ALLOC",
"BriefDescription": "Read allocate mode"
},
{
"EventCode": "0xC8",
"EventName": "EXT_SNOOP",
"BriefDescription": "SCU Snooped data from another CPU for this CPU"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
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[
{
"EventCode": "0xC0",
"EventName": "EXT_MEM_REQ",
"BriefDescription": "External memory request"
},
{
"EventCode": "0xC1",
"EventName": "EXT_MEM_REQ_NC",
"BriefDescription": "Non-cacheable external memory request"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
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[
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"EventCode": "0xC6",
"EventName": "PRE_DECODE_ERR",
"BriefDescription": "Pre-decode error"
},
{
"EventCode": "0xD0",
"EventName": "L1I_CACHE_ERR",
"BriefDescription": "L1 Instruction Cache (data or tag) memory error"
},
{
"EventCode": "0xD1",
"EventName": "L1D_CACHE_ERR",
"BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
},
{
"EventCode": "0xD2",
"EventName": "TLB_ERR",
"BriefDescription": "TLB memory error"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
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[
{
"EventCode": "0xC7",
"EventName": "STALL_SB_FULL",
"BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
},
{
"EventCode": "0xE0",
"EventName": "OTHER_IQ_DEP_STALL",
"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
},
{
"EventCode": "0xE1",
"EventName": "IC_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
},
{
"EventCode": "0xE2",
"EventName": "IUTLB_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
},
{
"EventCode": "0xE3",
"EventName": "DECODE_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
},
{
"EventCode": "0xE4",
"EventName": "OTHER_INTERLOCK_STALL",
"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
},
{
"EventCode": "0xE5",
"EventName": "AGU_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
},
{
"EventCode": "0xE6",
"EventName": "SIMD_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
},
{
"EventCode": "0xE7",
"EventName": "LD_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
},
{
"EventCode": "0xE8",
"EventName": "ST_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"PublicDescription": "Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xC9",
"EventName": "BR_COND_PRED",
"BriefDescription": "Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MIS_PRED",
"BriefDescription": "Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_ADDR_MIS_PRED",
"BriefDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event",
"EventCode": "0xCC",
"EventName": "BR_COND_MIS_PRED",
"BriefDescription": "Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event"
},
{
"PublicDescription": "Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCD",
"EventName": "BR_INDIRECT_ADDR_PRED",
"BriefDescription": "Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCE",
"EventName": "BR_RETURN_ADDR_PRED",
"BriefDescription": "Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
},
{
"PublicDescription": "Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
"EventCode": "0xCF",
"EventName": "BR_RETURN_ADDR_MIS_PRED",
"BriefDescription": "Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L3D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L3D_CACHE_REFILL"
},
{
"ArchStdEvent": "L3D_CACHE"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "LL_CACHE_RD"
},
{
"ArchStdEvent": "LL_CACHE_MISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L3D_CACHE_RD"
},
{
"ArchStdEvent": "L3D_CACHE_REFILL_RD"
},
{
"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented",
"EventCode": "0xC0",
"EventName": "L3D_CACHE_REFILL_PREFETCH",
"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented"
},
{
"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented",
"EventCode": "0xC1",
"EventName": "L2D_CACHE_REFILL_PREFETCH",
"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented"
},
{
"PublicDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
"EventCode": "0xC2",
"EventName": "L1D_CACHE_REFILL_PREFETCH",
"BriefDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
},
{
"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache",
"EventCode": "0xC3",
"EventName": "L2D_WS_MODE",
"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache"
},
{
"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode",
"EventCode": "0xC4",
"EventName": "L1D_WS_MODE_ENTRY",
"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode"
},
{
"PublicDescription": "Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache",
"EventCode": "0xC5",
"EventName": "L1D_WS_MODE",
"BriefDescription": "Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache"
},
{
"PublicDescription": "Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache",
"EventCode": "0xC7",
"EventName": "L3D_WS_MODE",
"BriefDescription": "Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache"
},
{
"PublicDescription": "Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled",
"EventCode": "0xD0",
"EventName": "L2D_LLWALK_TLB",
"BriefDescription": "Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled",
"EventCode": "0xD1",
"EventName": "L2D_LLWALK_TLB_REFILL",
"BriefDescription": "Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled",
"EventCode": "0xD2",
"EventName": "L2D_L2WALK_TLB",
"BriefDescription": "Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled",
"EventCode": "0xD3",
"EventName": "L2D_L2WALK_TLB_REFILL",
"BriefDescription": "Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count",
"EventCode": "0xD4",
"EventName": "L2D_S2_TLB",
"BriefDescription": "Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count"
},
{
"PublicDescription": "Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count",
"EventCode": "0xD5",
"EventName": "L2D_S2_TLB_REFILL",
"BriefDescription": "Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count"
},
{
"PublicDescription": "Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request",
"EventCode": "0xD6",
"EventName": "L2D_CACHE_STASH_DROPPED",
"BriefDescription": "Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
+20
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[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"PublicDescription": "Predecode error",
"EventCode": "0xC6",
"EventName": "PREDECODE_ERROR",
"BriefDescription": "Predecode error"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
+65
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
+17
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[
{
"ArchStdEvent": "UNALIGNED_LDST_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "REMOTE_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
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[
{
"ArchStdEvent": "STALL_FRONTEND"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"PublicDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed",
"EventCode": "0xE1",
"EventName": "STALL_FRONTEND_CACHE",
"BriefDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed"
},
{
"PublicDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed",
"EventCode": "0xE2",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed"
},
{
"PublicDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed",
"EventCode": "0xE3",
"EventName": "STALL_FRONTEND_PDERR",
"BriefDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed"
},
{
"PublicDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
"EventCode": "0xE4",
"EventName": "STALL_BACKEND_ILOCK",
"BriefDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
},
{
"PublicDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
"EventCode": "0xE5",
"EventName": "STALL_BACKEND_ILOCK_AGU",
"BriefDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
},
{
"PublicDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded",
"EventCode": "0xE6",
"EventName": "STALL_BACKEND_ILOCK_FPU",
"BriefDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded"
},
{
"PublicDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load",
"EventCode": "0xE7",
"EventName": "STALL_BACKEND_LD",
"BriefDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load"
},
{
"PublicDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store",
"EventCode": "0xE8",
"EventName": "STALL_BACKEND_ST",
"BriefDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store"
},
{
"PublicDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)",
"EventCode": "0xE9",
"EventName": "STALL_BACKEND_LD_CACHE",
"BriefDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)"
},
{
"PublicDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB",
"EventCode": "0xEA",
"EventName": "STALL_BACKEND_LD_TLB",
"BriefDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB"
},
{
"PublicDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full",
"EventCode": "0xEB",
"EventName": "STALL_BACKEND_ST_STB",
"BriefDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full"
},
{
"PublicDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB",
"EventCode": "0xEC",
"EventName": "STALL_BACKEND_ST_TLB",
"BriefDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/branch.json
+17
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/bus.json
+29
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json
+80
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/exception.json
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[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_SMC"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/instruction.json
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/memory.json
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[
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/branch.json
+17
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/bus.json
+17
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/cache.json
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L3D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L3D_CACHE_REFILL"
},
{
"ArchStdEvent": "L3D_CACHE"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "LL_CACHE_RD"
},
{
"ArchStdEvent": "LL_CACHE_MISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L3D_CACHE_RD"
},
{
"ArchStdEvent": "L3D_CACHE_REFILL_RD"
},
{
"PublicDescription": "Merge in the store buffer",
"EventCode": "0xC0",
"EventName": "STB_STALL",
"BriefDescription": "Merge in the store buffer"
},
{
"PublicDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
"EventCode": "0xC3",
"EventName": "L1D_PREF_LINE_FILL",
"BriefDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
},
{
"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented",
"EventCode": "0xC4",
"EventName": "L2D_PREF_LINE_FILL",
"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented"
},
{
"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to distinguish between both hardware and software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented",
"EventCode": "0xC5",
"EventName": "L3_PREF_LINE_FILL",
"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to distinguish between both hardware and software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented"
},
{
"PublicDescription": "L1D entering write stream mode",
"EventCode": "0xC6",
"EventName": "L1D_WS_MODE_ENTER",
"BriefDescription": "L1D entering write stream mode"
},
{
"PublicDescription": "L1D is in write stream mode",
"EventCode": "0xC7",
"EventName": "L1D_WS_MODE",
"BriefDescription": "L1D is in write stream mode"
},
{
"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache",
"EventCode": "0xC8",
"EventName": "L2D_WS_MODE",
"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache"
},
{
"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache",
"EventCode": "0xC9",
"EventName": "L3D_WS_MODE",
"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache"
},
{
"PublicDescription": "Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled",
"EventCode": "0xCA",
"EventName": "TLB_L2TLB_LLWALK_ACCESS",
"BriefDescription": "Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled",
"EventCode": "0xCB",
"EventName": "TLB_L2TLB_LLWALK_REFILL",
"BriefDescription": "Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB level-2 walk cache access. This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled",
"EventCode": "0xCC",
"EventName": "TLB_L2TLB_L2WALK_ACCESS",
"BriefDescription": "Level 2 TLB level-2 walk cache access. This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled",
"EventCode": "0xCD",
"EventName": "TLB_L2TLB_L2WALK_REFILL",
"BriefDescription": "Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled"
},
{
"PublicDescription": "Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count",
"EventCode": "0xCE",
"EventName": "TLB_L2TLB_S2_ACCESS",
"BriefDescription": "Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count"
},
{
"PublicDescription": "Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count",
"EventCode": "0xCF",
"EventName": "TLB_L2TLB_S2_REFILL",
"BriefDescription": "Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count"
},
{
"PublicDescription": "Unattributable Level 1 data cache write-back. This event occurs when a requestor outside the PE makes a coherency request that results in writeback",
"EventCode": "0xF0",
"EventName": "L2_L1D_CACHE_WB_UNATT",
"BriefDescription": "Unattributable Level 1 data cache write-back. This event occurs when a requestor outside the PE makes a coherency request that results in writeback"
},
{
"PublicDescription": "Unattributable Level 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache access",
"EventCode": "0xF1",
"EventName": "L2_L2D_CACHE_UNATT",
"BriefDescription": "Unattributable Level 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache access"
},
{
"PublicDescription": "Unattributable Level 2 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache read access",
"EventCode": "0xF2",
"EventName": "L2_L2D_CACHE_RD_UNATT",
"BriefDescription": "Unattributable Level 2 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache read access"
},
{
"PublicDescription": "Unattributable Level 3 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access",
"EventCode": "0xF3",
"EventName": "L2_L3D_CACHE_UNATT",
"BriefDescription": "Unattributable Level 3 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access"
},
{
"PublicDescription": "Unattributable Level 3 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access",
"EventCode": "0xF4",
"EventName": "L2_L3D_CACHE_RD_UNATT",
"BriefDescription": "Unattributable Level 3 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access"
},
{
"PublicDescription": "Unattributable Level 3 data or unified cache allocation without refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache allocate without refill",
"EventCode": "0xF5",
"EventName": "L2_L3D_CACHE_ALLOC_UNATT",
"BriefDescription": "Unattributable Level 3 data or unified cache allocation without refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache allocate without refill"
},
{
"PublicDescription": "Unattributable Level 3 data or unified cache refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache refill",
"EventCode": "0xF6",
"EventName": "L2_L3D_CACHE_REFILL_UNATT",
"BriefDescription": "Unattributable Level 3 data or unified cache refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache refill"
},
{
"PublicDescription": "Level 2 cache stash dropped. This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request. L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these events depends on the configuration of the core. If the private L2 cache is present, the L2D_CACHE* events count the activity in the private L2 cache, and the L3D_CACHE* events count the activity in the DSU L3 cache (if present). If the private L2 cache is not present but the DSU L3 cache is present, the L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* events do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR events do not count in this configuration. If neither the private L2 cache nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* events will count",
"EventCode": "0xF7",
"EventName": "L2D_CACHE_STASH_DROPPED",
"BriefDescription": "Level 2 cache stash dropped. This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request. L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these events depends on the configuration of the core. If the private L2 cache is present, the L2D_CACHE* events count the activity in the private L2 cache, and the L3D_CACHE* events count the activity in the DSU L3 cache (if present). If the private L2 cache is not present but the DSU L3 cache is present, the L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* events do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR events do not count in this configuration. If neither the private L2 cache nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* events will count"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/dpu.json
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[
{
"PublicDescription": "Instruction retired, indirect branch, mispredicted",
"EventCode": "0xE9",
"EventName": "DPU_BR_IND_MIS",
"BriefDescription": "Instruction retired, indirect branch, mispredicted"
},
{
"PublicDescription": "Instruction retired, conditional branch, mispredicted",
"EventCode": "0xEA",
"EventName": "DPU_BR_COND_MIS",
"BriefDescription": "Instruction retired, conditional branch, mispredicted"
},
{
"PublicDescription": "Memory error (any type) from IFU",
"EventCode": "0xEB",
"EventName": "DPU_MEM_ERR_IFU",
"BriefDescription": "Memory error (any type) from IFU"
},
{
"PublicDescription": "Memory error (any type) from DCU",
"EventCode": "0xEC",
"EventName": "DPU_MEM_ERR_DCU",
"BriefDescription": "Memory error (any type) from DCU"
},
{
"PublicDescription": "Memory error (any type) from TLB",
"EventCode": "0xED",
"EventName": "DPU_MEM_ERR_TLB",
"BriefDescription": "Memory error (any type) from TLB"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/exception.json
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[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ifu.json
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[
{
"PublicDescription": "I-Cache miss on an access from the prefetch block",
"EventCode": "0xD0",
"EventName": "IFU_IC_MISS_WAIT",
"BriefDescription": "I-Cache miss on an access from the prefetch block"
},
{
"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss",
"EventCode": "0xD1",
"EventName": "IFU_IUTLB_MISS_WAIT",
"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss"
},
{
"PublicDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 predictor",
"EventCode": "0xD2",
"EventName": "IFU_MICRO_COND_MISPRED",
"BriefDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 predictor"
},
{
"PublicDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor",
"EventCode": "0xD3",
"EventName": "IFU_MICRO_CADDR_MISPRED",
"BriefDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor"
},
{
"PublicDescription": "Micro-predictor hit with immediate redirect",
"EventCode": "0xD4",
"EventName": "IFU_MICRO_HIT",
"BriefDescription": "Micro-predictor hit with immediate redirect"
},
{
"PublicDescription": "Micro-predictor negative cache hit",
"EventCode": "0xD6",
"EventName": "IFU_MICRO_NEG_HIT",
"BriefDescription": "Micro-predictor negative cache hit"
},
{
"PublicDescription": "Micro-predictor correction",
"EventCode": "0xD7",
"EventName": "IFU_MICRO_CORRECTION",
"BriefDescription": "Micro-predictor correction"
},
{
"PublicDescription": "A 2nd instruction could have been pushed but was not because it was nonsequential",
"EventCode": "0xD8",
"EventName": "IFU_MICRO_NO_INSTR1",
"BriefDescription": "A 2nd instruction could have been pushed but was not because it was nonsequential"
},
{
"PublicDescription": "Micro-predictor miss",
"EventCode": "0xD9",
"EventName": "IFU_MICRO_NO_PRED",
"BriefDescription": "Micro-predictor miss"
},
{
"PublicDescription": "Thread flushed due to TLB miss",
"EventCode": "0xDA",
"EventName": "IFU_FLUSHED_TLB_MISS",
"BriefDescription": "Thread flushed due to TLB miss"
},
{
"PublicDescription": "Thread flushed due to reasons other than TLB miss",
"EventCode": "0xDB",
"EventName": "IFU_FLUSHED_EXCL_TLB_MISS",
"BriefDescription": "Thread flushed due to reasons other than TLB miss"
},
{
"PublicDescription": "This thread and the other thread both ready for scheduling in if0",
"EventCode": "0xDC",
"EventName": "IFU_ALL_THRDS_RDY",
"BriefDescription": "This thread and the other thread both ready for scheduling in if0"
},
{
"PublicDescription": "This thread was arbitrated when the other thread was also ready for scheduling",
"EventCode": "0xDD",
"EventName": "IFU_WIN_ARB_OTHER_RDY",
"BriefDescription": "This thread was arbitrated when the other thread was also ready for scheduling"
},
{
"PublicDescription": "This thread was arbitrated when the other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB",
"EventCode": "0xDE",
"EventName": "IFU_WIN_ARB_OTHER_ACT",
"BriefDescription": "This thread was arbitrated when the other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB"
},
{
"PublicDescription": "This thread was not arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss",
"EventCode": "0xDF",
"EventName": "IFU_NOT_RDY_FOR_ARB",
"BriefDescription": "This thread was not arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss"
},
{
"PublicDescription": "The thread moved from an active state to an inactive state (long-term sleep state, causing deallocation of some resources)",
"EventCode": "0xE0",
"EventName": "IFU_GOTO_IDLE",
"BriefDescription": "The thread moved from an active state to an inactive state (long-term sleep state, causing deallocation of some resources)"
},
{
"PublicDescription": "I-Cache lookup under miss from other thread",
"EventCode": "0xE1",
"EventName": "IFU_IC_LOOKUP_UNDER_MISS",
"BriefDescription": "I-Cache lookup under miss from other thread"
},
{
"PublicDescription": "I-Cache miss under miss from other thread",
"EventCode": "0xE2",
"EventName": "IFU_IC_MISS_UNDER_MISS",
"BriefDescription": "I-Cache miss under miss from other thread"
},
{
"PublicDescription": "This thread pushed an instruction into the IQ",
"EventCode": "0xE3",
"EventName": "IFU_INSTR_PUSHED",
"BriefDescription": "This thread pushed an instruction into the IQ"
},
{
"PublicDescription": "I-Cache Speculative line fill",
"EventCode": "0xE4",
"EventName": "IFU_IC_LF_SP",
"BriefDescription": "I-Cache Speculative line fill"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/instruction.json
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"PublicDescription": "Instruction retired, conditional branch",
"EventCode": "0xE8",
"EventName": "DPU_BR_COND_RETIRED",
"BriefDescription": "Instruction retired, conditional branch"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/memory.json
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[
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "REMOTE_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"PublicDescription": "External memory request",
"EventCode": "0xC1",
"EventName": "BIU_EXT_MEM_REQ",
"BriefDescription": "External memory request"
},
{
"PublicDescription": "External memory request to non-cacheable memory",
"EventCode": "0xC2",
"EventName": "BIU_EXT_MEM_REQ_NC",
"BriefDescription": "External memory request to non-cacheable memory"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/pipeline.json
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[
{
"ArchStdEvent": "STALL_FRONTEND"
},
{
"ArchStdEvent": "STALL_BACKEND"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
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[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
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[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "CNT_CYCLES"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
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[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L3D_CACHE_ALLOCATE"
},
{
"ArchStdEvent": "L3D_CACHE_REFILL"
},
{
"ArchStdEvent": "L3D_CACHE"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "LL_CACHE_RD"
},
{
"ArchStdEvent": "LL_CACHE_MISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
},
{
"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L1D_TLB_RD"
},
{
"ArchStdEvent": "L1D_TLB_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_TLB_RD"
},
{
"ArchStdEvent": "L2D_TLB_WR"
},
{
"ArchStdEvent": "L3D_CACHE_RD"
},
{
"ArchStdEvent": "L1I_CACHE_LMISS"
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L3D_CACHE_LMISS_RD"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
+47
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@@ -0,0 +1,47 @@
[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_SMC"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
+134
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@@ -0,0 +1,134 @@
[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "OP_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"ArchStdEvent": "ASE_INST_SPEC"
},
{
"ArchStdEvent": "SVE_INST_SPEC"
},
{
"ArchStdEvent": "FP_HP_SPEC"
},
{
"ArchStdEvent": "FP_SP_SPEC"
},
{
"ArchStdEvent": "FP_DP_SPEC"
},
{
"ArchStdEvent": "SVE_PRED_SPEC"
},
{
"ArchStdEvent": "SVE_PRED_EMPTY_SPEC"
},
{
"ArchStdEvent": "SVE_PRED_FULL_SPEC"
},
{
"ArchStdEvent": "SVE_PRED_PARTIAL_SPEC"
},
{
"ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC"
},
{
"ArchStdEvent": "SVE_LDFF_SPEC"
},
{
"ArchStdEvent": "SVE_LDFF_FAULT_SPEC"
},
{
"ArchStdEvent": "FP_SCALE_OPS_SPEC"
},
{
"ArchStdEvent": "FP_FIXED_OPS_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT8_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT16_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT32_SPEC"
},
{
"ArchStdEvent": "ASE_SVE_INT64_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
+41
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@@ -0,0 +1,41 @@
[
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "REMOTE_ACCESS"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
+23
View File
@@ -0,0 +1,23 @@
[
{
"ArchStdEvent": "STALL_FRONTEND"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"ArchStdEvent": "STALL"
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND"
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND"
},
{
"ArchStdEvent": "STALL_SLOT"
},
{
"ArchStdEvent": "STALL_BACKEND_MEM"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
+29
View File
@@ -0,0 +1,29 @@
[
{
"ArchStdEvent": "TRB_WRAP"
},
{
"ArchStdEvent": "TRCEXTOUT0"
},
{
"ArchStdEvent": "TRCEXTOUT1"
},
{
"ArchStdEvent": "TRCEXTOUT2"
},
{
"ArchStdEvent": "TRCEXTOUT3"
},
{
"ArchStdEvent": "CTI_TRIGOUT4"
},
{
"ArchStdEvent": "CTI_TRIGOUT5"
},
{
"ArchStdEvent": "CTI_TRIGOUT6"
},
{
"ArchStdEvent": "CTI_TRIGOUT7"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
+11
View File
@@ -0,0 +1,11 @@
[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
+23
View File
@@ -0,0 +1,23 @@
[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
+107
View File
@@ -0,0 +1,107 @@
[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
"EventCode": "0xC2",
"EventName": "I_TAG_RAM_RD",
"BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
},
{
"PublicDescription": "Number of ways read in the instruction cache - Data RAM",
"EventCode": "0xC3",
"EventName": "I_DATA_RAM_RD",
"BriefDescription": "Number of ways read in the instruction cache - Data RAM"
},
{
"PublicDescription": "Number of ways read in the instruction BTAC RAM",
"EventCode": "0xC4",
"EventName": "I_BTAC_RAM_RD",
"BriefDescription": "Number of ways read in the instruction BTAC RAM"
},
{
"PublicDescription": "Level 1 PLD TLB refill",
"EventCode": "0xE7",
"EventName": "PLD_UTLB_REFILL",
"BriefDescription": "Level 1 PLD TLB refill"
},
{
"PublicDescription": "Level 1 CP15 TLB refill",
"EventCode": "0xE8",
"EventName": "CP15_UTLB_REFILL",
"BriefDescription": "Level 1 CP15 TLB refill"
},
{
"PublicDescription": "Level 1 TLB flush",
"EventCode": "0xE9",
"EventName": "UTLB_FLUSH",
"BriefDescription": "Level 1 TLB flush"
},
{
"PublicDescription": "Level 2 TLB access",
"EventCode": "0xEA",
"EventName": "TLB_ACCESS",
"BriefDescription": "Level 2 TLB access"
},
{
"PublicDescription": "Level 2 TLB miss",
"EventCode": "0xEB",
"EventName": "TLB_MISS",
"BriefDescription": "Level 2 TLB miss"
},
{
"PublicDescription": "Data cache hit in itself due to VIPT aliasing",
"EventCode": "0xEC",
"EventName": "DCACHE_SELF_HIT_VIPT",
"BriefDescription": "Data cache hit in itself due to VIPT aliasing"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
+14
View File
@@ -0,0 +1,14 @@
[
{
"PublicDescription": "ETM trace unit output 0",
"EventCode": "0xDE",
"EventName": "ETM_EXT_OUT0",
"BriefDescription": "ETM trace unit output 0"
},
{
"PublicDescription": "ETM trace unit output 1",
"EventCode": "0xDF",
"EventName": "ETM_EXT_OUT1",
"BriefDescription": "ETM trace unit output 1"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
+14
View File
@@ -0,0 +1,14 @@
[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"PublicDescription": "Number of Traps to hypervisor",
"EventCode": "0xDC",
"EventName": "EXC_TRAP_HYP",
"BriefDescription": "Number of Traps to hypervisor"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
+65
View File
@@ -0,0 +1,65 @@
[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
+14
View File
@@ -0,0 +1,14 @@
[
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
+44
View File
@@ -0,0 +1,44 @@
[
{
"PublicDescription": "Duration of a translation table walk handled by the MMU",
"EventCode": "0xE0",
"EventName": "MMU_PTW",
"BriefDescription": "Duration of a translation table walk handled by the MMU"
},
{
"PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU",
"EventCode": "0xE1",
"EventName": "MMU_PTW_ST1",
"BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU"
},
{
"PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU",
"EventCode": "0xE2",
"EventName": "MMU_PTW_ST2",
"BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU"
},
{
"PublicDescription": "Duration of a translation table walk requested by the LSU",
"EventCode": "0xE3",
"EventName": "MMU_PTW_LSU",
"BriefDescription": "Duration of a translation table walk requested by the LSU"
},
{
"PublicDescription": "Duration of a translation table walk requested by the Instruction Side",
"EventCode": "0xE4",
"EventName": "MMU_PTW_ISIDE",
"BriefDescription": "Duration of a translation table walk requested by the Instruction Side"
},
{
"PublicDescription": "Duration of a translation table walk requested by a Preload instruction or Prefetch request",
"EventCode": "0xE5",
"EventName": "MMU_PTW_PLD",
"BriefDescription": "Duration of a translation table walk requested by a Preload instruction or Prefetch request"
},
{
"PublicDescription": "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)",
"EventCode": "0xE6",
"EventName": "MMU_PTW_CP15",
"BriefDescription": "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
+38
View File
@@ -0,0 +1,38 @@
[
{
"PublicDescription": "A linefill caused an instruction side stall",
"EventCode": "0xC0",
"EventName": "LF_STALL",
"BriefDescription": "A linefill caused an instruction side stall"
},
{
"PublicDescription": "A translation table walk caused an instruction side stall",
"EventCode": "0xC1",
"EventName": "PTW_STALL",
"BriefDescription": "A translation table walk caused an instruction side stall"
},
{
"PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
"EventCode": "0xD3",
"EventName": "D_LSU_SLOT_FULL",
"BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
},
{
"PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
"EventCode": "0xD8",
"EventName": "LS_IQ_FULL",
"BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
},
{
"PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
"EventCode": "0xD9",
"EventName": "DP_IQ_FULL",
"BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
},
{
"PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
"EventCode": "0xDA",
"EventName": "DE_IQ_FULL",
"BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
+11
View File
@@ -0,0 +1,11 @@
[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]

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