Resguardo inicial

This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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../bullet-07/cycle-and-instruction-count.json
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../bullet/firmware.json
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../bullet/instruction.json
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[
{
"EventName": "ICACHE_MISS",
"EventCode": "0x102",
"BriefDescription": "Counts instruction cache misses"
},
{
"EventName": "DCACHE_MISS",
"EventCode": "0x202",
"BriefDescription": "Counts data cache misses"
},
{
"EventName": "DCACHE_RELEASE",
"EventCode": "0x402",
"BriefDescription": "Counts writeback requests from the data cache"
},
{
"EventName": "ITLB_MISS",
"EventCode": "0x802",
"BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
},
{
"EventName": "DTLB_MISS",
"EventCode": "0x1002",
"BriefDescription": "Counts Data TLB misses caused by data address translation requests"
},
{
"EventName": "UTLB_MISS",
"EventCode": "0x2002",
"BriefDescription": "Counts Unified TLB misses caused by address translation requests"
},
{
"EventName": "UTLB_HIT",
"EventCode": "0x4002",
"BriefDescription": "Counts Unified TLB hits for address translation requests"
},
{
"EventName": "PTE_CACHE_MISS",
"EventCode": "0x8002",
"BriefDescription": "Counts Page Table Entry cache misses"
},
{
"EventName": "PTE_CACHE_HIT",
"EventCode": "0x10002",
"BriefDescription": "Counts Page Table Entry cache hits"
},
{
"EventName": "ITLB_MULTI_HIT",
"EventCode": "0x20002",
"BriefDescription": "Counts Instruction TLB multi-hits"
},
{
"EventName": "DTLB_MULTI_HIT",
"EventCode": "0x40002",
"BriefDescription": "Counts Data TLB multi-hits"
}
]
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[
{
"EventName": "ADDRESSGEN_INTERLOCK",
"EventCode": "0x101",
"BriefDescription": "Counts cycles with an address-generation interlock"
},
{
"EventName": "LONGLATENCY_INTERLOCK",
"EventCode": "0x201",
"BriefDescription": "Counts cycles with a long-latency interlock"
},
{
"EventName": "CSR_INTERLOCK",
"EventCode": "0x401",
"BriefDescription": "Counts cycles with a CSR interlock"
},
{
"EventName": "ICACHE_BLOCKED",
"EventCode": "0x801",
"BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
},
{
"EventName": "DCACHE_BLOCKED",
"EventCode": "0x1001",
"BriefDescription": "Counts cycles in which the data cache blocked an instruction"
},
{
"EventName": "BRANCH_DIRECTION_MISPREDICTION",
"EventCode": "0x2001",
"BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
},
{
"EventName": "BRANCH_TARGET_MISPREDICTION",
"EventCode": "0x4001",
"BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
},
{
"EventName": "PIPELINE_FLUSH",
"EventCode": "0x8001",
"BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
},
{
"EventName": "REPLAY",
"EventCode": "0x10001",
"BriefDescription": "Counts instruction replays"
},
{
"EventName": "INTEGER_MUL_DIV_INTERLOCK",
"EventCode": "0x20001",
"BriefDescription": "Counts cycles with a multiply or divide interlock"
},
{
"EventName": "FP_INTERLOCK",
"EventCode": "0x40001",
"BriefDescription": "Counts cycles with a floating-point interlock"
},
{
"EventName": "TRACE_STALL",
"EventCode": "0x80001",
"BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder"
}
]
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../bullet-07/watchpoint.json