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lastdragon
2026-09-06 12:53:21 -06:00
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linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
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[
{
"BriefDescription": "L1D data line replacements",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts the number of lines brought into the L1 data cache.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "L1D miss outstanding duration in cycles",
"Counter": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
"Counter": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
"PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
"UMask": "0xf"
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"PublicDescription": "Not rejected writebacks that missed LLC.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "L2 cache lines filling L2.",
"SampleAfterValue": "100003",
"UMask": "0x7"
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"PublicDescription": "Dirty L2 cache lines filling the L2.",
"SampleAfterValue": "100003",
"UMask": "0xa"
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "L2 code requests",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
"SampleAfterValue": "200003",
"UMask": "0x30"
},
{
"BriefDescription": "Demand Data Read requests",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
"SampleAfterValue": "200003",
"UMask": "0xc0"
},
{
"BriefDescription": "RFO requests to L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
"SampleAfterValue": "200003",
"UMask": "0xc"
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Demand Data Read requests that hit L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "RFO requests that hit L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "RFOs that access cache lines in any state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"PublicDescription": "RFOs that access cache lines in any state.",
"SampleAfterValue": "200003",
"UMask": "0xf"
},
{
"BriefDescription": "RFOs that hit cache lines in M state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"PublicDescription": "RFOs that hit cache lines in M state.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "RFOs that miss cache lines",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"PublicDescription": "RFOs that miss cache lines.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Transactions accessing L2 pipe",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "RFO requests that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when L1D is locked",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
"SampleAfterValue": "100003",
"UMask": "0x4f"
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
"PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
"SampleAfterValue": "50021",
"UMask": "0x10"
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PEBS": "1",
"SampleAfterValue": "50021",
"UMask": "0x4"
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"PEBS": "1",
"SampleAfterValue": "100007",
"UMask": "0x20"
},
{
"BriefDescription": "All retired load uops. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x81"
},
{
"BriefDescription": "All retired store uops. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x82"
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
"SampleAfterValue": "100007",
"UMask": "0x21"
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests sent to uncore.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
"PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
"Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
"PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0244",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0244",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000105B3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0091",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0091",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0091",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0091",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000107F7",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch prefetch RFOs",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010122",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0122",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0122",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all writebacks from the core to the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010004",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0004",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0004",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010001",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0001",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0001",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0001",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0001",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand rfo's",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010002",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0002",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0002",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0002",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts non-temporal stores",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
"Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
"UMask": "0x10"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/counter.json
+17
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[
{
"Unit": "core",
"CountersNumFixed": "3",
"CountersNumGeneric": "4"
},
{
"Unit": "ARB",
"CountersNumFixed": "1",
"CountersNumGeneric": "2"
},
{
"Unit": "CBOX",
"CountersNumFixed": "0",
"CountersNumGeneric": "2"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
+152
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[
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
"SampleAfterValue": "100003",
"UMask": "0x1e"
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"PublicDescription": "Counts number of X87 uops executed.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
+285
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[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
"SampleAfterValue": "100003",
"UMask": "0x1f"
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "Number of DSB to MITE switches.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Cycles DSB to MITE switches caused delay.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"PublicDescription": "DSB Fill encountered > 3 DSB lines.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "Counts cycles the IDQ is empty.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
"SampleAfterValue": "2000003",
"UMask": "0x3c"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
"PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_OCCUR",
"PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
+1041
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linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
+201
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[
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Loads with latency value being above 128",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 128.",
"SampleAfterValue": "1009",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 16.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 256.",
"SampleAfterValue": "503",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 32.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 4.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 512.",
"SampleAfterValue": "101",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 64.",
"SampleAfterValue": "2003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 8.",
"SampleAfterValue": "50021",
"UMask": "0x1"
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
"Counter": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400244",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400091",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3004003f7",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts LLC replacements",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004001b3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400004",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400001",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of any page walk that had a miss in LLC.",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "PAGE_WALKS.LLC_MISS",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/metricgroups.json
+126
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{
"Backend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Bad": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"DataSharing": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Fed": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"FetchBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"FpVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"LockCont": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Machine_Clears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryTLB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Memory_BW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Memory_Lat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MicroSeq": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"OS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"PGO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Prefetches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Ret": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Retire": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"SMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Server": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"SoC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"TmaL3mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"TopdownL1": "Metrics for top-down breakdown at level 1",
"TopdownL2": "Metrics for top-down breakdown at level 2",
"TopdownL3": "Metrics for top-down breakdown at level 3",
"TopdownL4": "Metrics for top-down breakdown at level 4",
"TopdownL5": "Metrics for top-down breakdown at level 5",
"TopdownL6": "Metrics for top-down breakdown at level 6",
"tma_L1_group": "Metrics for top-down breakdown at level 1",
"tma_L2_group": "Metrics for top-down breakdown at level 2",
"tma_L3_group": "Metrics for top-down breakdown at level 3",
"tma_L4_group": "Metrics for top-down breakdown at level 4",
"tma_L5_group": "Metrics for top-down breakdown at level 5",
"tma_L6_group": "Metrics for top-down breakdown at level 6",
"tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_utilization category",
"tma_backend_bound_group": "Metrics contributing to tma_backend_bound category",
"tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category",
"tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category",
"tma_core_bound_group": "Metrics contributing to tma_core_bound category",
"tma_divider_group": "Metrics contributing to tma_divider category",
"tma_dram_bound_group": "Metrics contributing to tma_dram_bound category",
"tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category",
"tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store category",
"tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwidth category",
"tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency category",
"tma_fp_arith_group": "Metrics contributing to tma_fp_arith category",
"tma_fp_vector_group": "Metrics contributing to tma_fp_vector category",
"tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category",
"tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category",
"tma_issue2P": "Metrics related by the issue $issue2P",
"tma_issueBM": "Metrics related by the issue $issueBM",
"tma_issueBW": "Metrics related by the issue $issueBW",
"tma_issueFB": "Metrics related by the issue $issueFB",
"tma_issueL1": "Metrics related by the issue $issueL1",
"tma_issueLat": "Metrics related by the issue $issueLat",
"tma_issueMC": "Metrics related by the issue $issueMC",
"tma_issueMS": "Metrics related by the issue $issueMS",
"tma_issueMV": "Metrics related by the issue $issueMV",
"tma_issueRFO": "Metrics related by the issue $issueRFO",
"tma_issueSL": "Metrics related by the issue $issueSL",
"tma_issueSO": "Metrics related by the issue $issueSO",
"tma_issueSmSt": "Metrics related by the issue $issueSmSt",
"tma_issueSpSt": "Metrics related by the issue $issueSpSt",
"tma_issueSyncxn": "Metrics related by the issue $issueSyncxn",
"tma_issueTLB": "Metrics related by the issue $issueTLB",
"tma_itlb_misses_group": "Metrics contributing to tma_itlb_misses category",
"tma_l1_bound_group": "Metrics contributing to tma_l1_bound category",
"tma_l3_bound_group": "Metrics contributing to tma_l3_bound category",
"tma_light_operations_group": "Metrics contributing to tma_light_operations category",
"tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category",
"tma_machine_clears_group": "Metrics contributing to tma_machine_clears category",
"tma_mem_latency_group": "Metrics contributing to tma_mem_latency category",
"tma_memory_bound_group": "Metrics contributing to tma_memory_bound category",
"tma_microcode_sequencer_group": "Metrics contributing to tma_microcode_sequencer category",
"tma_ports_utilization_group": "Metrics contributing to tma_ports_utilization category",
"tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utilized_0 category",
"tma_ports_utilized_3m_group": "Metrics contributing to tma_ports_utilized_3m category",
"tma_retiring_group": "Metrics contributing to tma_retiring category",
"tma_serializing_operation_group": "Metrics contributing to tma_serializing_operation category",
"tma_store_bound_group": "Metrics contributing to tma_store_bound category",
"tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category"
}
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/other.json
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[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0_TRANS",
"PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
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linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
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[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
"UMask": "0x86",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
"UMask": "0x88",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
"UMask": "0x81",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
"UMask": "0x8f",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
"UMask": "0x46",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
"UMask": "0x48",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
"UMask": "0x41",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
"UMask": "0x4f",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
"UMask": "0x16",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
"UMask": "0x18",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
"UMask": "0x1f",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
"UMask": "0x26",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
"UMask": "0x28",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
"UMask": "0x2f",
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
"UMask": "0x88",
"Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
"UMask": "0x28",
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
"UMask": "0x84",
"Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
"UMask": "0x24",
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
"Unit": "CBOX"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
"Unit": "CBOX"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json
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[
{
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"Counter": "0",
"EventCode": "0x83",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "10",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of LLC evictions allocated.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "Fixed",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
"Unit": "ARB"
}
]
linux-7.2.3/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
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[
{
"BriefDescription": "Page walk for a large page completed for Demand load.",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
"SampleAfterValue": "100003",
"UMask": "0x88"
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
"SampleAfterValue": "100003",
"UMask": "0x81"
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
"SampleAfterValue": "100003",
"UMask": "0x82"
},
{
"BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
"SampleAfterValue": "2000003",
"UMask": "0x84"
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "Cycles PMH is busy with this walk.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all ITLB levels that cause page walks.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "Cycle PMH is busy with a walk.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
"SampleAfterValue": "100007",
"UMask": "0x20"
}
]