// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
		};
	};

	/* Base bus clock and default for the UART. It will be replaced once a clock driver has
	 * been added.
	 */
	uartclk: uartclk-26000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		clock-frequency = <26000000>;
		interrupt-parent = <&gic>;
		/* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
		 * arm timer at all. Since this is a single CPU system I don't think it
		 * really matters that the offset is random though.
		 */
		arm,cpu-registers-not-fw-configured;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		/* The GIC has a non-standard way of configuring ints between level-low/level
		 * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE
		 * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source
		 * seem wrong.
		 *
		 * Everything defaults to active-high/rising edge, but the timer is active-low. We
		 * currently rely on the boot loader to change timer IRQs to active-low for us for
		 * now.
		 */
		gic: interrupt-controller@f2000000 {
			compatible = "arm,gic-v3";
			interrupt-controller;
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xf2000000 0x10000>,
			      <0xf2040000 0x20000>;
		};

		uart0: serial@131000 {
			compatible = "arm,pl011", "arm,primecell";
			arm,primecell-periphid = <0x0018c011>;
			reg = <0x00131000 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&uartclk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@1408000 {
			compatible = "arm,pl011", "arm,primecell";
			arm,primecell-periphid = <0x0018c011>;
			reg = <0x01408000 0x1000>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&uartclk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@140d000 {
			compatible = "arm,pl011", "arm,primecell";
			arm,primecell-periphid = <0x0018c011>;
			reg = <0x0140d000 0x1000>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&uartclk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};