// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright (C) 2025 PHYTEC Messtechnik GmbH */ #include #include #include "imx8mp-pinfunc.h" &{/} { backlight_lvds1: backlight-lvds1 { compatible = "pwm-backlight"; pinctrl-0 = <&pinctrl_lvds1>; pinctrl-names = "default"; power-supply = <®_vcc_12v>; status = "disabled"; }; panel_lvds1: panel-lvds1 { backlight = <&backlight_lvds1>; power-supply = <®_vdd_3v3>; status = "disabled"; port { panel1_in: endpoint { remote-endpoint = <&ldb_lvds_ch1>; }; }; }; reg_vcc_12v: regulator-12v { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; regulator-max-microvolt = <12000000>; regulator-min-microvolt = <12000000>; regulator-name = "VCC_12V"; }; reg_vcc_1v8_audio: regulator-1v8 { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; regulator-name = "VCC_1V8_Audio"; }; reg_vcc_3v3_analog: regulator-3v3 { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "VCC_3V3_Analog"; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "snd-peb-av-10"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,mclk-fs = <32>; simple-audio-card,widgets = "Line", "Line In", "Speaker", "Speaker", "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; simple-audio-card,routing = "Speaker", "SPOP", "Speaker", "SPOM", "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "LINE1L", "Line In", "LINE1R", "Line In", "MIC3R", "Microphone Jack", "Microphone Jack", "Mic Bias"; simple-audio-card,codec { sound-dai = <&codec>; }; dailink_master: simple-audio-card,cpu { sound-dai = <&sai5>; }; }; }; &i2c5 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_i2c5>; pinctrl-1 = <&pinctrl_i2c5_gpio>; pinctrl-names = "default", "gpio"; scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; status = "okay"; codec: audio-codec@18 { compatible = "ti,tlv320aic3007"; reg = <0x18>; pinctrl-0 = <&pinctrl_tlv320>; pinctrl-names = "default"; #sound-dai-cells = <0>; ai3x-gpio-func = <0xd 0x0>; ai3x-micbias-vg = <2>; AVDD-supply = <®_vcc_3v3_analog>; DRVDD-supply = <®_vcc_3v3_analog>; DVDD-supply = <®_vcc_1v8_audio>; IOVDD-supply = <®_vdd_3v3>; }; eeprom@57 { compatible = "atmel,24c32"; reg = <0x57>; pagesize = <32>; vcc-supply = <®_vdd_3v3>; }; }; &ldb_lvds_ch1 { remote-endpoint = <&panel1_in>; }; &pwm2 { pinctrl-0 = <&pinctrl_pwm2>; pinctrl-names = "default"; }; &sai5 { pinctrl-0 = <&pinctrl_sai5>; pinctrl-names = "default"; assigned-clocks = <&clk IMX8MP_CLK_SAI5>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, <&clk IMX8MP_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; #sound-dai-cells = <0>; fsl,sai-mclk-direction-output; fsl,sai-synchronous-rx; status = "okay"; }; &iomuxc { pinctrl_i2c5: i2c5grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 >; }; pinctrl_i2c5_gpio: i2c5gpiogrp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 >; }; pinctrl_lvds1: lvds1grp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x12 >; }; pinctrl_pwm2: pwm2grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x12 >; }; pinctrl_sai5: sai5grp { fsl,pins = < MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0xd6 MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0xd6 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 >; }; pinctrl_tlv320: tlv320grp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x16 >; }; };