// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2023 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada 7020 Com Express CPU module board.
 */

#include "armada-7020.dtsi"

/ {
	model = "Marvell Armada-7020 COMEXPRESS board setup";
	compatible = "marvell,armada7020-cpu-module", "marvell,armada7020",
			"marvell,armada-ap806-dual", "marvell,armada-ap806";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x2 0x00000000>;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth1;
	};
};

&ap_clk {
	status = "okay";
};

&gic {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;
};

&spi0 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&cp0_mdio {
	status = "okay";

	phy0: ethernet-phy@10 {
		reg = <0x10>;
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	managed = "in-band-status";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy4 0>;
};

&cp0_eth1 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
};

&cp0_usb3_0 {
	status = "okay";
};

&cp0_usb3_1 {
	status = "okay";
};

&cp0_clk {
	status = "okay";
};

&cp0_i2c0 {
	status = "okay";
	clock-frequency = <100000>;
};

&cp0_nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "main-storage";
		nand-rb = <0>;
		nand-ecc-mode = "hw";
		nand-on-flash-bbt;
		nand-ecc-strength = <8>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x400000>;
			};
			partition@200000 {
				label = "Linux";
				reg = <0x400000 0x100000>;
			};
			partition@1000000 {
				label = "Filesystem";
				reg = <0x500000 0x1e00000>;
			};
		};
	};
};

&cp0_pcie0 {
	status = "okay";
	num-lanes = <4>;
	num-viewport = <8>;

	ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000
		  0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>;

	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy0 0
		&cp0_comphy1 0
		&cp0_comphy2 0
		&cp0_comphy3 0>;
};

&cp0_sata0 {
	/* CPM Lane 0 - U29 */
	status = "okay";

	sata-port@1 {
		status = "okay";
		/* Generic PHY, providing serdes lanes */
		phys = <&cp0_comphy5 1>;
	};
};

&cp0_sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhci_pins>;
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	broken-cd;
};