// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

&{/} {
	model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine";

	dp2-connector {
		compatible = "dp-connector";
		label = "eDP2";
		type = "full-size";

		port {
			dp2_connector_in: endpoint {
				remote-endpoint = <&mdss1_dp0_out>;
			};
		};
	};

	dp3-connector {
		compatible = "dp-connector";
		label = "eDP3";
		type = "full-size";

		port {
			dp3_connector_in: endpoint {
				remote-endpoint = <&mdss1_dp1_out>;
			};
		};
	};

	vreg_0p9: regulator-0v9 {
		compatible = "regulator-fixed";
		regulator-name = "VREG_0P9";

		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vreg_1p8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "VREG_1P8";

		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&ethernet1 {
	phy-handle = <&hsgmii_phy1>;
	phy-mode = "2500base-x";

	pinctrl-0 = <&ethernet1_default>;
	pinctrl-names = "default";

	snps,mtl-rx-config = <&mtl_rx_setup1>;
	snps,mtl-tx-config = <&mtl_tx_setup1>;

	nvmem-cells = <&mac_addr1>;
	nvmem-cell-names = "mac-address";

	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		hsgmii_phy1: ethernet-phy@18 {
			compatible = "ethernet-phy-id004d.d101";
			reg = <0x18>;
			reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <11000>;
			reset-deassert-us = <70000>;
		};
	};

	mtl_rx_setup1: rx-queues-config {
		snps,rx-queues-to-use = <4>;
		snps,rx-sched-sp;

		queue0 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x0>;
			snps,route-up;
			snps,priority = <0x1>;
		};

		queue1 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x1>;
			snps,route-ptp;
		};

		queue2 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x2>;
			snps,route-avcp;
		};

		queue3 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x3>;
			snps,priority = <0xc>;
		};
	};

	mtl_tx_setup1: tx-queues-config {
		snps,tx-queues-to-use = <4>;

		queue0 {
			snps,dcb-algorithm;
		};

		queue1 {
			snps,dcb-algorithm;
		};

		queue2 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3e800>;
			snps,low_credit = <0xffc18000>;
		};

		queue3 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3e800>;
			snps,low_credit = <0xffc18000>;
		};
	};
};

&i2c18 {
	#address-cells = <1>;
	#size-cells = <0>;

	eeprom@52 {
		compatible = "giantec,gt24c256c", "atmel,24c256";
		reg = <0x52>;
		pagesize = <64>;

		nvmem-layout {
			compatible = "fixed-layout";
			#address-cells = <1>;
			#size-cells = <1>;

			mac_addr1: mac-addr@0 {
				reg = <0x0 0x6>;
			};
		};
	};
};

&mdss1 {
	status = "okay";
};

&mdss1_dp0 {
	pinctrl-0 = <&dp2_hot_plug_det>;
	pinctrl-names = "default";

	status = "okay";
};

&mdss1_dp1 {
	pinctrl-0 = <&dp3_hot_plug_det>;
	pinctrl-names = "default";

	status = "okay";
};

&mdss1_dp0_out {
	data-lanes = <0 1 2 3>;
	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
	remote-endpoint = <&dp2_connector_in>;
};

&mdss1_dp1_out {
	data-lanes = <0 1 2 3>;
	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
	remote-endpoint = <&dp3_connector_in>;
};

&mdss1_dp0_phy {
	status = "okay";
};

&mdss1_dp1_phy {
	status = "okay";
};

&pcie0 {
	iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
		    <0x100 &pcie_smmu 0x1 0x1>,
		    <0x208 &pcie_smmu 0x2 0x1>,
		    <0x210 &pcie_smmu 0x3 0x1>,
		    <0x218 &pcie_smmu 0x4 0x1>,
		    <0x300 &pcie_smmu 0x5 0x1>,
		    <0x400 &pcie_smmu 0x6 0x1>,
		    <0x500 &pcie_smmu 0x7 0x1>,
		    <0x501 &pcie_smmu 0x8 0x1>;
};

&pcieport0 {
	#address-cells = <3>;
	#size-cells = <2>;

	pcie@0,0 {
		compatible = "pci1179,0623";
		reg = <0x10000 0x0 0x0 0x0 0x0>;
		#address-cells = <3>;
		#size-cells = <2>;

		device_type = "pci";
		ranges;
		bus-range = <0x2 0xff>;

		vddc-supply = <&vreg_0p9>;
		vdd18-supply = <&vreg_1p8>;
		vdd09-supply = <&vreg_0p9>;
		vddio1-supply = <&vreg_1p8>;
		vddio2-supply = <&vreg_1p8>;
		vddio18-supply = <&vreg_1p8>;

		i2c-parent = <&i2c18 0x77>;

		resx-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;

		pinctrl-0 = <&tc9563_resx_n>;
		pinctrl-names = "default";

		pcie@1,0 {
			reg = <0x20800 0x0 0x0 0x0 0x0>;
			#address-cells = <3>;
			#size-cells = <2>;

			device_type = "pci";
			ranges;
			bus-range = <0x3 0xff>;
		};

		pcie@2,0 {
			reg = <0x21000 0x0 0x0 0x0 0x0>;
			#address-cells = <3>;
			#size-cells = <2>;

			device_type = "pci";
			ranges;
			bus-range = <0x4 0xff>;
		};

		pcie@3,0 {
			reg = <0x21800 0x0 0x0 0x0 0x0>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges;
			bus-range = <0x5 0xff>;

			pci@0,0 {
				reg = <0x50000 0x0 0x0 0x0 0x0>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges;
			};

			pci@0,1 {
				reg = <0x50100 0x0 0x0 0x0 0x0>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges;
			};
		};
	};
};

&serdes1 {
	phy-supply = <&vreg_l5a>;

	status = "okay";
};

&tlmm {
	dp2_hot_plug_det: dp2-hot-plug-det-state {
		pins = "gpio104";
		function = "edp2_hot";
		bias-disable;
	};

	dp3_hot_plug_det: dp3-hot-plug-det-state {
		pins = "gpio103";
		function = "edp3_hot";
		bias-disable;
	};

	ethernet1_default: ethernet1-default-state {
		ethernet1-mdc-pins {
			pins = "gpio20";
			function = "emac1_mdc";
			drive-strength = <16>;
			bias-pull-up;
		};

		ethernet1-mdio-pins {
			pins = "gpio21";
			function = "emac1_mdio";
			drive-strength = <16>;
			bias-pull-up;
		};
	};

	tc9563_resx_n: tc9563-resx-state {
		pins = "gpio140";
		function = "gpio";
		bias-disable;
		/* Reset pin of tc9563 is active low hence set default
		 * state of this pin to output-high.
		 */
		output-high;
	};
};