// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for R9A08G046L48 SMARC SoM board.
 *
 * Copyright (C) 2026 Renesas Electronics Corp.
 */

/*
 * Please set the below switch position on the SoM and the corresponding macro
 * on the board DTS:
 *
 * Switch position SYS.2, Macro SW_I3C_EN:
 *      0 - SMARC_I2C_GP is enabled
 *      1 - I3C is enabled
 *
 * Switch position SYS.4, Macro SW_SD2_EN:
 *      0 - Select I2S0
 *      1 - Select SD2
 *
 * Switch position SYS.5, Macro SW_DPI_EN:
 *      0 - Select multiple SMARC signals active
 *      1 - Select LCD
 *
 * Switch position BOOT.1, Macro RZ_BOOT_MODE3:
 *      0 - Select JTAG enabled
 *      1 - Select SDIO {CD,IOVS,PWEN} and GPIO4 Active
 *
 * Switch position SW_GPIO4, Macro SW_GPIO4:
 *      0 - Select RZ_VBAT_TAMPER (position 2-1)
 *      1 - Select GPIO4 (position 2-3)
 */

/ {
	compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046";

	aliases {
		ethernet0 = &eth0;
		ethernet1 = &eth1;
		i2c0 = &i2c0;
	};

	memory@48000000 {
		device_type = "memory";
		/* First 128MiB is reserved for secure area. */
		reg = <0x0 0x48000000 0x0 0x78000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	x2_clk: x2-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
	};
};

&eth0 {
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";

	pinctrl-0 = <&eth0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&eth0_rxc_rx_clk {
	clock-frequency = <125000000>;
};

&eth1 {
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";

	pinctrl-0 = <&eth1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&eth1_rxc_rx_clk {
	clock-frequency = <125000000>;
};

&extal_clk {
	clock-frequency = <24000000>;
};

&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	versa3: clock-generator@68 {
		compatible = "renesas,5p35023";
		reg = <0x68>;
		#clock-cells = <1>;
		clocks = <&x2_clk>;

		assigned-clocks = <&versa3 1>, <&versa3 2>,
				  <&versa3 3>, <&versa3 4>;
		assigned-clock-rates = <12288000>, <11289600>,
				       <12288000>, <25000000>;
	};
};

&mdio0 {
	phy0: ethernet-phy@7 {
		compatible = "ethernet-phy-id0022.1640";
		reg = <7>;
		interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
		rxc-skew-psec = <1400>;
		txc-skew-psec = <1400>;
		rxdv-skew-psec = <0>;
		txen-skew-psec = <0>;
		rxd0-skew-psec = <0>;
		rxd1-skew-psec = <0>;
		rxd2-skew-psec = <0>;
		rxd3-skew-psec = <0>;
		txd0-skew-psec = <0>;
		txd1-skew-psec = <0>;
		txd2-skew-psec = <0>;
		txd3-skew-psec = <0>;
	};
};

&mdio1 {
	phy1: ethernet-phy@7 {
		compatible = "ethernet-phy-id0022.1640";
		reg = <7>;
		interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
		rxc-skew-psec = <1400>;
		txc-skew-psec = <1400>;
		rxdv-skew-psec = <0>;
		txen-skew-psec = <0>;
		rxd0-skew-psec = <0>;
		rxd1-skew-psec = <0>;
		rxd2-skew-psec = <0>;
		rxd3-skew-psec = <0>;
		txd0-skew-psec = <0>;
		txd1-skew-psec = <0>;
		txd2-skew-psec = <0>;
		txd3-skew-psec = <0>;
	};
};

&pinctrl {
	eth0_pins: eth0 {
		txc {
			pinmux = <RZG3L_PORT_PINMUX(B, 1, 1)>;  /* ETH0_TXC_REF_CLK */
			power-source = <1800>;
			output-enable;
			drive-strength-microamp = <5200>;
		};

		ctrl {
			pinmux = <RZG3L_PORT_PINMUX(A, 0, 1)>, /* MDIO */
				 <RZG3L_PORT_PINMUX(A, 1, 1)>, /* MDC */
				 <RZG3L_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
				 <RZG3L_PORT_PINMUX(A, 3, 1)>, /* TX_CTL */
				 <RZG3L_PORT_PINMUX(B, 0, 1)>, /* RXC */
				 <RZG3L_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
				 <RZG3L_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
				 <RZG3L_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
				 <RZG3L_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
				 <RZG3L_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
				 <RZG3L_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
				 <RZG3L_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
				 <RZG3L_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
				 <RZG3L_PORT_PINMUX(C, 2, 15)>; /* PHY_INTR */
				 power-source = <1800>;
		};
	};

	eth1_pins: eth1 {
		txc {
			pinmux = <RZG3L_PORT_PINMUX(E, 1, 1)>;  /* ETH1_TXC_REF_CLK */
			power-source = <1800>;
			output-enable;
			drive-strength-microamp = <5200>;
		};

		ctrl {
			pinmux = <RZG3L_PORT_PINMUX(D, 0, 1)>, /* MDIO */
				 <RZG3L_PORT_PINMUX(D, 1, 1)>, /* MDC */
				 <RZG3L_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
				 <RZG3L_PORT_PINMUX(D, 3, 1)>, /* TX_CTL */
				 <RZG3L_PORT_PINMUX(E, 0, 1)>, /* RXC */
				 <RZG3L_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
				 <RZG3L_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
				 <RZG3L_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
				 <RZG3L_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
				 <RZG3L_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
				 <RZG3L_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
				 <RZG3L_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
				 <RZG3L_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
				 <RZG3L_PORT_PINMUX(F, 2, 15)>; /* PHY_INTR */
				 power-source = <1800>;
		};
	};

	i2c0_pins: i2c0 {
		pinmux = <RZG3L_PORT_PINMUX(L, 2, 4)>, /* RIIC0_SCL */
			 <RZG3L_PORT_PINMUX(L, 3, 4)>; /* RIIC0_SDA */
	};
};

&wdt0 {
	timeout-sec = <60>;
	status = "okay";
};