// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * DT-overlay to enable the onboard PCIe x1 slot, which shares pins and the PHY
 * with the USB3 host port.
 * To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 right
 * next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host port
 * will be unusable (not even in 2.0 mode)
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/pinctrl/rockchip.h>

&pcie1 {
	pinctrl-0 = <&pcie1m0_pins &pcie1_rst>;
	pinctrl-names = "default";
	status = "okay";
};

&pinctrl {
	pcie1 {
		pcie1_rst: pcie1-rst {
			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&usb_drd1_dwc3 {
	status = "disabled";
};