// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
 * DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM
 *
 * AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM
 * DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE-EVM
 *
 * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include "k3-pinctrl.h"

&{/} {
	icssg0_eth: icssg0-eth {
		compatible = "ti,am642-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pins_default>;
		sram = <&oc_sram>;

		dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
		       <&main_pktdma 0xc101 15>, /* egress slice 0 */
		       <&main_pktdma 0xc102 15>, /* egress slice 0 */
		       <&main_pktdma 0xc103 15>, /* egress slice 0 */
		       <&main_pktdma 0xc104 15>, /* egress slice 1 */
		       <&main_pktdma 0xc105 15>, /* egress slice 1 */
		       <&main_pktdma 0xc106 15>, /* egress slice 1 */
		       <&main_pktdma 0xc107 15>, /* egress slice 1 */
		       <&main_pktdma 0x4100 15>, /* ingress slice 0 */
		       <&main_pktdma 0x4101 15>; /* ingress slice 1 */
		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
			    "rx0", "rx1";

		interrupt-parent = <&icssg0_intc>;
		interrupts = <24 0 2>, <25 1 3>;
		interrupt-names = "tx_ts0", "tx_ts1";

		ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
		firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
				"ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
				"ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
				"ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
				"ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
				"ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";

		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
				      <2>,
				      <2>,
				      <2>,	/* MII mode */
				      <2>,
				      <2>;

		ti,mii-g-rt = <&icssg0_mii_g_rt>;
		ti,mii-rt = <&icssg0_mii_rt>;
		ti,iep = <&icssg0_iep0>,  <&icssg0_iep1>;
		ti,pa-stats = <&icssg0_pa_stats>;

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			icssg0_emac0: port@0 {
				reg = <0>;
				phy-handle = <&icssg0_phy00>;
				phy-mode = "rgmii-id";
				ti,syscon-rgmii-delay = <&main_conf 0x4100>;
				/* Filled in by bootloader */
				local-mac-address = [00 00 00 00 00 00];
			};

			icssg0_emac1: port@1 {
				reg = <1>;
				phy-handle = <&icssg0_phy01>;
				phy-mode = "rgmii-id";
				ti,syscon-rgmii-delay = <&main_conf 0x4104>;
				/* Filled in by bootloader */
				local-mac-address = [00 00 00 00 00 00];
			};
		};
	};
};

&main_pmx0 {
	pru_icssg0_mdio_pins_default: pru-icssg0-mdio-pins {
		pinctrl-single,pins = <
			/* (P3) PRG0_MDIO0_MDC */
			AM64X_IOPAD(0x0204, PIN_OUTPUT, 0)
			/* (P2) PRG0_MDIO0_MDIO */
			AM64X_IOPAD(0x0200, PIN_INPUT, 0)
			/* (P16) GPIO0_32 - GPMC0_ADVn_ALE - GPIO_ETH0/1_RESETn# */
			AM64X_IOPAD(0x0084, PIN_OUTPUT, 7)
		>;
	};

	pru_icssg0_rgmii1_pins_default: pru-icssg0-rgmii1-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0160, PIN_INPUT, 2)  /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
			AM64X_IOPAD(0x0164, PIN_INPUT, 2)  /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
			AM64X_IOPAD(0x0168, PIN_INPUT, 2)  /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
			AM64X_IOPAD(0x016c, PIN_INPUT, 2)  /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
			AM64X_IOPAD(0x0178, PIN_INPUT, 2)  /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
			AM64X_IOPAD(0x0170, PIN_INPUT, 2)  /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
			AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
			AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
			AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
			AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
			AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
			AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
		>;
	};

	pru_icssg0_rgmii2_pins_default: pru-icssg0-rgmii2-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01b0, PIN_INPUT, 2)  /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
			AM64X_IOPAD(0x01b4, PIN_INPUT, 2)  /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
			AM64X_IOPAD(0x01b8, PIN_INPUT, 2)  /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
			AM64X_IOPAD(0x01bc, PIN_INPUT, 2)  /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
			AM64X_IOPAD(0x01c8, PIN_INPUT, 2)  /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
			AM64X_IOPAD(0x01c0, PIN_INPUT, 2)  /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
			AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
			AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
			AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
			AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
			AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
			AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
		>;
	};

	icssg0_iep0_pins_default: icssg0-iep0-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01ac, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
		>;
	};
};

&icssg0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pru_icssg0_mdio_pins_default>;
	#address-cells = <1>;
	#size-cells = <0>;

	icssg0_phy00: ethernet-phy@0 {
		reg = <0x0>;
	};

	icssg0_phy01: ethernet-phy@a {
		reg = <0xa>;
	};
};

&icssg0_iep0 {
	pinctrl-names = "default";
	pinctrl-0 = <&icssg0_iep0_pins_default>;
};

&main_gpio0 {
	phy-line-hog {
		gpio-hog;
		gpios = <32 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "phy-hog-line";
	};
};