// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2025 Josua Mayer <josua@solid-run.com>
 */

#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mm.dtsi"

/ {
	compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm";
	model = "SolidRun i.MX8MM SoM";

	chosen {
		bootargs = "earlycon=ec_imx6q,0x30890000,115200";
		stdout-path = &uart2;
	};

	v_1_8: regulator-1-8 {
		compatible = "regulator-fixed";
		regulator-name = "1v8";
		regulator-max-microvolt = <1800000>;
		regulator-min-microvolt = <1800000>;
	};

	v_3_3: regulator-3-3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
	};

	usdhc1_pwrseq: usdhc1-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	};

	memory@40000000 {
		reg = <0x0 0x40000000 0 0x80000000>;
		device_type = "memory";
	};
};

&fec1 {
	phy = <&phy0>;
	phy-mode = "rgmii-id";
	pinctrl-0 = <&fec1_pins>;
	pinctrl-names = "default";
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		phy0: ethernet-phy@4 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x4>;
			phy-reset-duration = <10>;
			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
			vddio-supply = <&vddio>;
			qca,smarteee-tw-us-1g = <24>;

			vddio: vddio-regulator {
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
			};
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&osc_32k>;
		#clock-cells = <0>;
		clock-output-names = "clk-32k-out";
		pinctrl-0 = <&pmic_pins>;
		pinctrl-names = "default";
		rohm,reset-snvs-powered;

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1300000>;
				regulator-min-microvolt = <700000>;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1300000>;
				regulator-min-microvolt = <700000>;
				regulator-ramp-delay = <1250>;
				rohm,dvs-idle-voltage = <900000>;
				rohm,dvs-run-voltage = <1000000>;
			};

			buck3_reg: BUCK3 {
				// BUCK5 in datasheet
				regulator-name = "buck3";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1350000>;
				regulator-min-microvolt = <700000>;
			};

			buck4_reg: BUCK4 {
				// BUCK6 in datasheet
				regulator-name = "buck4";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <3000000>;
			};

			buck5_reg: BUCK5 {
				// BUCK7 in datasheet
				regulator-name = "buck5";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1995000>;
				regulator-min-microvolt = <1605000>;
			};

			buck6_reg: BUCK6 {
				// BUCK8 in datasheet
				regulator-name = "buck6";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1400000>;
				regulator-min-microvolt = <800000>;
			};

			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1600000>;
			};

			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <900000>;
				regulator-min-microvolt = <800000>;
			};

			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
			};

			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <900000>;
			};

			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <900000>;
			};
		};
	};

	som_eeprom: eeprom@50 {
		compatible = "st,24c01", "atmel,24c01";
		reg = <0x50>;
		pagesize = <16>;
	};
};

&iomuxc {
	fec1_pins: pinctrl-fec1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
		>;
	};

	i2c1_pins: pinctrl-i2c1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
		>;
	};

	pcie_pins: pinctrl-pcie-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x0
		>;
	};

	pmic_pins: pinctrl-pmic-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x140
		>;
	};

	uart1_pins: pinctrl-uart1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
			/* BT_REG_ON */
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x0
			/* BT_WAKE_DEV */
			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x0
			/* BT_WAKE_HOST */
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x100
		>;
	};

	uart2_pins: pinctrl-uart2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140
		>;
	};

	usdhc1_pins: pinctrl-usdhc1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
			/* wifi refclk */
			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x0
			/* WL_REG_ON */
			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x0
			/* WL_WAKE_HOST */
			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x100
		>;
	};

	usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	usdhc3_pins: pinctrl-usdhc3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	wdog1_pins: pinctrl-wdog1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x140
		>;
	};
};

/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */
&pcie0 {
	pinctrl-0 = <&pcie_pins>;
	pinctrl-names = "default";
	reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pcie_phy {
	fsl,clkreq-unsupported;
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
	status = "okay";
};

&uart1 {
	/* select 80MHz parent clock to support maximum baudrate 4Mbps */
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	pinctrl-0 = <&uart1_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm4330-bt";
		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
		max-speed = <3000000>;
		shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
	};
};

&uart2 {
	pinctrl-0 = <&uart2_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&usdhc1 {
	bus-width = <4>;
	mmc-pwrseq = <&usdhc1_pwrseq>;
	pinctrl-0 = <&usdhc1_pins>;
	pinctrl-names = "default";
	vmmc-supply = <&v_3_3>;
	vqmmc-supply = <&v_1_8>;
	status = "okay";
};

&usdhc3 {
	bus-width = <8>;
	non-removable;
	pinctrl-0 = <&usdhc3_pins>;
	pinctrl-1 = <&usdhc3_100mhz_pins>;
	pinctrl-2 = <&usdhc3_200mhz_pins>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	vmmc-supply = <&v_3_3>;
	vqmmc-supply = <&v_1_8>;
	status = "okay";
};

&wdog1 {
	pinctrl-0 = <&wdog1_pins>;
	pinctrl-names = "default";
	status = "okay";
};