// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Variscite Sonata carrier board for DART-MX91
 *
 * Link: https://variscite.com/carrier-boards/sonata-board/
 *
 * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
 *
 */

/dts-v1/;

#include "imx91-var-dart.dtsi"

/ {
	model = "Variscite DART-MX91 on Sonata-Board";
	compatible = "variscite,var-dart-mx91-sonata",
		     "variscite,var-dart-mx91",
		     "fsl,imx91";

	aliases {
		ethernet0 = &eqos;
		ethernet1 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		i2c0 = &lpi2c1;
		i2c1 = &lpi2c2;
		i2c2 = &lpi2c3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &lpuart1;
		serial1 = &lpuart2;
		serial2 = &lpuart3;
		serial3 = &lpuart4;
		serial4 = &lpuart5;
		serial5 = &lpuart6;
	};

	chosen {
		stdout-path = &lpuart1;
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-home {
			label = "Home";
			linux,code = <KEY_HOME>;
			gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};

		button-up {
			label = "Up";
			linux,code = <KEY_UP>;
			gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};

		button-down {
			label = "Down";
			linux,code = <KEY_DOWN>;
			gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};

		button-back {
			label = "Back";
			linux,code = <KEY_BACK>;
			gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led-emmc {
			label = "eMMC";
			gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc0";
		};
	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_rgb_sel: regulator-rgb-enable {
		compatible = "regulator-fixed";
		regulator-name = "RGBSEL";
		gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VDD_SD2_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		off-on-delay-us = <20000>;
	};

	reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x80000000 0 0x40000000>;
			reusable;
			size = <0 0x10000000>;
			linux,cma-default;
		};
	};
};

&adc1 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

/* Use external instead of internal RTC */
&bbnsm_rtc {
	status = "disabled";
};

&eqos {
	mdio {
		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
			reset-assert-us = <15000>;
			reset-deassert-us = <100000>;

			leds {
				#address-cells = <1>;
				#size-cells = <0>;

				led@0 {
					reg = <0>;
					color = <LED_COLOR_ID_YELLOW>;
					function = LED_FUNCTION_LAN;
					linux,default-trigger = "netdev";
				};

				led@1 {
					reg = <1>;
					color = <LED_COLOR_ID_GREEN>;
					function = LED_FUNCTION_LAN;
					linux,default-trigger = "netdev";
				};
			};
		};
	};
};

&fec {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec>;
	pinctrl-1 = <&pinctrl_fec_sleep>;
	/*
	 * The required RGMII TX and RX 2ns delays are implemented directly
	 * in hardware via passive delay elements on the SOM PCB.
	 * No delay configuration is needed in software via PHY driver.
	 */
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	status = "okay";
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
};

&lpi2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "sleep", "gpio";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
	pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
	scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pca6408_1: gpio@20 {
		compatible = "nxp,pcal6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio1>;
		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
		vcc-supply = <&reg_rgb_sel>;
	};

	pca6408_2: gpio@21 {
		compatible = "nxp,pcal6408";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio1>;
		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
		vcc-supply = <&reg_rgb_sel>;
	};

	pca9534: gpio@22 {
		compatible = "nxp,pca9534";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio1>;
		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
	};

	st33ktpm2xi2c: tpm@2e {
		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
		reg = <0x2e>;
	};

	/* Capacitive touch controller */
	ft5x06_ts: touchscreen@38 {
		compatible = "edt,edt-ft5206";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_captouch>;
		reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
		interrupt-parent = <&gpio3>;
		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
		wakeup-source;
	};

	/* USB Type-C Controller */
	typec@3d {
		compatible = "nxp,ptn5150";
		reg = <0x3d>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_extcon>;
		interrupt-parent = <&gpio4>;
		interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;

		port {
			typec1_dr_sw: endpoint {
				remote-endpoint = <&usb1_drd_sw>;
			};
		};
	};

	rtc@68 {
		compatible = "dallas,ds1337";
		reg = <0x68>;
	};
};

/* Console (J10) */
&lpuart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* Header (J12.4, J12.6) */
&lpuart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	disable-over-current;
	samsung,picophy-pre-emp-curr-control = <3>;
	samsung,picophy-dc-vol-level-adjust = <7>;
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usbotg2 {
	disable-over-current;
	dr_mode = "host";
	status = "okay";
};

/* SD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	no-sdio;
	no-mmc;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* GPIO Expanders shared IRQ */
			MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10            0x31e
		>;
	};

	pinctrl_captouch: captouchgrp {
		fsl,pins = <
			MX91_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
		>;
	};

	pinctrl_extcon: extcongrp {
		fsl,pins = <
			MX91_PAD_CCM_CLKO4__GPIO4_IO29			0x31e
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0             0x57e
			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1             0x57e
			MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2             0x57e
			MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3             0x37e
			MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC             0x5fe
			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL       0x57e
			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0             0x57e
			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1             0x57e
			MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2             0x57e
			MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3             0x57e
			MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC             0x5fe
			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL       0x57e
		>;
	};

	pinctrl_fec_sleep: fecsleepgrp {
		fsl,pins = <
			MX91_PAD_ENET2_RD0__GPIO4_IO24                  0x51e
			MX91_PAD_ENET2_RD1__GPIO4_IO25                  0x51e
			MX91_PAD_ENET2_RD2__GPIO4_IO26                  0x51e
			MX91_PAD_ENET2_RD3__GPIO4_IO27                  0x31e
			MX91_PAD_ENET2_RXC__GPIO4_IO23                  0x51e
			MX91_PAD_ENET2_RX_CTL__GPIO4_IO22               0x51e
			MX91_PAD_ENET2_TD0__GPIO4_IO19                  0x51e
			MX91_PAD_ENET2_TD1__GPIO4_IO18                  0x51e
			MX91_PAD_ENET2_TD2__GPIO4_IO17                  0x51e
			MX91_PAD_ENET2_TD3__GPIO4_IO16                  0x51e
			MX91_PAD_ENET2_TXC__GPIO4_IO21                  0x51e
			MX91_PAD_ENET2_TX_CTL__GPIO4_IO20               0x51e
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX91_PAD_PDM_CLK__CAN1_TX			0x139e
			MX91_PAD_PDM_BIT_STREAM0__CAN1_RX		0x139e
		>;
	};

	pinctrl_lpi2c1: lpi2c1grp {
		fsl,pins = <
			MX91_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
			MX91_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
		>;
	};

	pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp {
		fsl,pins = <
			MX91_PAD_I2C1_SCL__GPIO1_IO0			0x31e
			MX91_PAD_I2C1_SDA__GPIO1_IO1			0x31e
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX91_PAD_CCM_CLKO3__GPIO4_IO28			0x31e
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX91_PAD_UART1_RXD__LPUART1_RX			0x31e
			MX91_PAD_UART1_TXD__LPUART1_TX			0x31e
		>;
	};

	pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX91_PAD_GPIO_IO05__LPUART6_RX			0x31e
			MX91_PAD_GPIO_IO04__LPUART6_TX			0x31e
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX91_PAD_SD2_CLK__USDHC2_CLK			0x1582
			MX91_PAD_SD2_CMD__USDHC2_CMD			0x1382
			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x1382
			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x1382
			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x1382
			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x1382
			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX91_PAD_SD2_CLK__USDHC2_CLK			0x158e
			MX91_PAD_SD2_CMD__USDHC2_CMD			0x138e
			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX91_PAD_SD2_CLK__USDHC2_CLK			0x15fe
			MX91_PAD_SD2_CMD__USDHC2_CMD			0x13fe
			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe
			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe
			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe
			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe
			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
		>;
	};

	pinctrl_usdhc2_sleep: usdhc2sleepgrp {
		fsl,pins = <
			MX91_PAD_SD2_CLK__GPIO3_IO1			0x51e
			MX91_PAD_SD2_CMD__GPIO3_IO2			0x51e
			MX91_PAD_SD2_DATA0__GPIO3_IO3			0x51e
			MX91_PAD_SD2_DATA1__GPIO3_IO4			0x51e
			MX91_PAD_SD2_DATA2__GPIO3_IO5			0x51e
			MX91_PAD_SD2_DATA3__GPIO3_IO6			0x51e
			MX91_PAD_SD2_VSELECT__GPIO3_IO19		0x51e
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX91_PAD_SD2_CD_B__GPIO3_IO0			0x31e
		>;
	};

	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
		fsl,pins = <
			MX91_PAD_SD2_CD_B__GPIO3_IO0			0x51e
		>;
	};
};