// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

&{/} {
	model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine";

	vreg_0p9: regulator-0v9 {
		compatible = "regulator-fixed";
		regulator-name = "VREG_0P9";

		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vreg_1p8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "VREG_1P8";

		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&i2c15 {
	#address-cells = <1>;
	#size-cells = <0>;

	eeprom1: eeprom@52 {
		compatible = "giantec,gt24c256c", "atmel,24c256";
		reg = <0x52>;
		pagesize = <64>;

		nvmem-layout {
			compatible = "fixed-layout";
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};
};

&pcie0 {
	iommu-map = <0x0   &pcie_smmu 0x0 0x1>,
		    <0x100 &pcie_smmu 0x1 0x1>,
		    <0x208 &pcie_smmu 0x2 0x1>,
		    <0x210 &pcie_smmu 0x3 0x1>,
		    <0x218 &pcie_smmu 0x4 0x1>,
		    <0x300 &pcie_smmu 0x5 0x1>,
		    <0x400 &pcie_smmu 0x6 0x1>,
		    <0x500 &pcie_smmu 0x7 0x1>,
		    <0x501 &pcie_smmu 0x8 0x1>;
};

&pcieport0 {
	#address-cells = <3>;
	#size-cells = <2>;

	pcie@0,0 {
		compatible = "pci1179,0623";
		reg = <0x10000 0x0 0x0 0x0 0x0>;
		#address-cells = <3>;
		#size-cells = <2>;

		device_type = "pci";
		ranges;
		bus-range = <0x2 0xff>;

		vddc-supply = <&vreg_0p9>;
		vdd18-supply = <&vreg_1p8>;
		vdd09-supply = <&vreg_0p9>;
		vddio1-supply = <&vreg_1p8>;
		vddio2-supply = <&vreg_1p8>;
		vddio18-supply = <&vreg_1p8>;

		i2c-parent = <&i2c15 0x77>;

		resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;

		pinctrl-0 = <&tc9563_resx_n>;
		pinctrl-names = "default";

		pcie@1,0 {
			reg = <0x20800 0x0 0x0 0x0 0x0>;
			#address-cells = <3>;
			#size-cells = <2>;

			device_type = "pci";
			ranges;
			bus-range = <0x3 0xff>;
		};

		pcie@2,0 {
			reg = <0x21000 0x0 0x0 0x0 0x0>;
			#address-cells = <3>;
			#size-cells = <2>;

			device_type = "pci";
			ranges;
			bus-range = <0x4 0xff>;
		};

		pcie@3,0 {
			reg = <0x21800 0x0 0x0 0x0 0x0>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges;
			bus-range = <0x5 0xff>;

			pci@0,0 {
				reg = <0x50000 0x0 0x0 0x0 0x0>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges;
			};

			pci@0,1 {
				reg = <0x50100 0x0 0x0 0x0 0x0>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges;
			};
		};
	};
};

&tlmm {
	tc9563_resx_n: tc9563-resx-state {
		pins = "gpio124";
		function = "gpio";
		bias-disable;
		/* Reset pin of tc9563 is active low hence set default
		 * state of this pin to output-high.
		 */
		output-high;
	};
};