# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/rockchip,rk3568-vicap.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip RK3568 Video Capture (VICAP) maintainers: - Michael Riesch description: The Rockchip RK3568 Video Capture (VICAP) block features a digital video port (DVP, a parallel video interface) and a MIPI CSI-2 port. It receives the data from camera sensors, video decoders, or other companion ICs and transfers it into system main memory by AXI bus. The Rockchip RK3588 Video Capture (VICAP) is similar to its RK3568 counterpart, but features six MIPI CSI-2 ports and additional connections to the image signal processor (ISP) blocks. properties: compatible: enum: - rockchip,rk3568-vicap - rockchip,rk3588-vicap reg: maxItems: 1 interrupts: maxItems: 1 clocks: minItems: 4 maxItems: 5 clock-names: items: - const: aclk - const: hclk - const: dclk - const: iclk - const: iclk1 minItems: 4 iommus: maxItems: 1 resets: minItems: 5 maxItems: 9 reset-names: minItems: 5 maxItems: 9 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to general register file used for video input block control. power-domains: maxItems: 1 ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false properties: "#address-cells": const: 1 "#size-cells": const: 0 port@0: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: The digital video port (DVP, a parallel video interface). properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: bus-type: enum: - 5 # MEDIA_BUS_TYPE_PARALLEL - 6 # MEDIA_BUS_TYPE_BT656 rockchip,dvp-clk-delay: $ref: /schemas/types.yaml#/definitions/uint32 default: 0 minimum: 0 maximum: 127 description: Delay the DVP path clock input to align the sampling phase, only valid in dual edge sampling mode. Delay is zero by default and can be adjusted optionally. required: - bus-type port@1: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the MIPI CSI-2 receiver 0 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@2: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the MIPI CSI-2 receiver 1 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@3: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the MIPI CSI-2 receiver 2 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@4: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the MIPI CSI-2 receiver 3 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@5: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the MIPI CSI-2 receiver 4 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@6: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the MIPI CSI-2 receiver 5 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@10: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the ISP0 input. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false port@11: $ref: /schemas/graph.yaml#/properties/port description: Port connected to the ISP1 input. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false required: - compatible - reg - interrupts - clocks - ports allOf: - if: properties: compatible: contains: const: rockchip,rk3568-vicap then: properties: clocks: maxItems: 4 clock-names: maxItems: 4 resets: maxItems: 5 reset-names: items: - const: arst - const: hrst - const: drst - const: prst - const: irst ports: properties: port@2: false port@3: false port@4: false port@5: false port@6: false port@10: false port@11: false - if: properties: compatible: contains: const: rockchip,rk3588-vicap then: properties: clocks: minItems: 5 clock-names: minItems: 5 resets: minItems: 9 reset-names: items: - const: arst - const: hrst - const: drst - const: irst0 - const: irst1 - const: irst2 - const: irst3 - const: irst4 - const: irst5 additionalProperties: false examples: - | #include #include #include #include #include soc { #address-cells = <2>; #size-cells = <2>; vicap: video-capture@fdfe0000 { compatible = "rockchip,rk3568-vicap"; reg = <0x0 0xfdfe0000 0x0 0x200>; interrupts = ; assigned-clocks = <&cru DCLK_VICAP>; assigned-clock-rates = <300000000>; clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; clock-names = "aclk", "hclk", "dclk", "iclk"; iommus = <&vicap_mmu>; power-domains = <&power RK3568_PD_VI>; resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, <&cru SRST_I_VICAP>; reset-names = "arst", "hrst", "drst", "prst", "irst"; rockchip,grf = <&grf>; ports { #address-cells = <1>; #size-cells = <0>; vicap_dvp: port@0 { reg = <0>; vicap_dvp_input: endpoint { bus-type = ; bus-width = <16>; pclk-sample = ; remote-endpoint = <&it6801_output>; }; }; vicap_mipi: port@1 { reg = <1>; vicap_mipi_input: endpoint { remote-endpoint = <&csi_output>; }; }; }; }; };