// SPDX-License-Identifier: GPL-2.0+
/*
 * Ethernet ENET2 support for Variscite VAR-SOM-6UL module.
 *
 * Copyright 2019-2024 Variscite Ltd.
 * Copyright 2026 Dimonoff
 */

/ {
	rmii_ref_clk: rmii-ref-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "rmii-ref";
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio_enet2: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			clocks = <&rmii_ref_clk>;
			clock-names = "rmii-ref";
			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
			reset-assert-us = <100000>;
			micrel,led-mode = <1>;
			micrel,rmii-reference-clock-select-25-mhz;
		};

		ethphy1: ethernet-phy@3 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <3>;
			clocks = <&rmii_ref_clk>;
			clock-names = "rmii-ref";
			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
			reset-assert-us = <100000>;
			micrel,led-mode = <0>;
			micrel,rmii-reference-clock-select-25-mhz;
		};
	};
};

&iomuxc {
	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
		>;
	};

	pinctrl_enet2_gpio: enet2-gpiogrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
		>;
	};

	pinctrl_enet2_mdio: enet2-mdiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
		>;
	};
};