// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-var-som.dtsi"
#include "imx8mm-var-som-wifi-bt-iw61x.dtsi"

/ {
	model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
	compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";

	chosen {
		stdout-path = &uart4;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <20000>;
		enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
		pinctrl-1 = <&pinctrl_reg_usb_otg2_vbus_sleep>;
		regulator-name = "usb_otg2_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-back {
			label = "Back";
			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_BACK>;
		};

		key-home {
			label = "Home";
			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_HOME>;
		};

		key-menu {
			label = "Menu";
			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_MENU>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led {
			label = "Heartbeat";
			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&ethphy {
	leds {
		#address-cells = <1>;
		#size-cells = <0>;

		led@0 {
			reg = <0>;
			color = <LED_COLOR_ID_YELLOW>;
			function = LED_FUNCTION_LAN;
			linux,default-trigger = "netdev";
		};

		led@1 {
			reg = <1>;
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_LAN;
			linux,default-trigger = "netdev";
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pca9534: gpio@20 {
		compatible = "nxp,pca9534";
		reg = <0x20>;
		gpio-controller;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pca9534>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
		#gpio-cells = <2>;
		wakeup-source;

		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
		usb3-sata-sel-hog {
			gpio-hog;
			gpios = <4 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "usb3_sata_sel";
		};

		som-vselect-hog {
			gpio-hog;
			gpios = <6 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "som_vselect";
		};

		enet-sel-hog {
			gpio-hog;
			gpios = <7 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "enet_sel";
		};
	};

	/* USB Type-C Controller */
	ptn5150: typec@3d {
		compatible = "nxp,ptn5150";
		reg = <0x3d>;
		interrupt-parent = <&gpio1>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ptn5150>;

		port {
			typec1_dr_sw: endpoint {
				remote-endpoint = <&usb1_drd_sw>;
			};
		};
	};
};

&i2c3 {
	pca6408: gpio@21 {
		compatible = "nxp,pcal6408";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	st33ktpm2xi2c: tpm@2e {
		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
		reg = <0x2e>;
		label = "tpm";
		reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
	};

	/* Capacitive touch controller */
	ft5x06_ts: touchscreen@38 {
		compatible = "edt,edt-ft5406";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_captouch>;
		interrupt-parent = <&gpio5>;
		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
	};

	rtc@68 {
		compatible = "dallas,ds1337";
		reg = <0x68>;
	};
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pcie_phy {
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,tx-deemph-gen1 = <0x2d>;
	fsl,tx-deemph-gen2 = <0xf>;
	fsl,clkreq-unsupported;
	status = "okay";
};

&pcie0 {
	reset-gpio = <&pca6408 1 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
		 <&clk IMX8MM_CLK_PCIE1_AUX>;
	clock-names = "pcie", "pcie_bus", "pcie_aux";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

/* Header */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* Header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

/* Console */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	samsung,picophy-pre-emp-curr-control = <3>;
	samsung,picophy-dc-vol-level-adjust = <7>;
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usbotg2 {
	dr_mode = "host";
	vbus-supply = <&reg_usb_otg2_vbus>;
	samsung,picophy-pre-emp-curr-control = <3>;
	samsung,picophy-dc-vol-level-adjust = <7>;
	disable-over-current;
	status = "okay";
};

/* SD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

&pinctrl_fec1 {
	fsl,pins = <
		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
		MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
		MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
		MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
		MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
		MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
		MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
	>;
};

&iomuxc {
	pinctrl_captouch: captouchgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x1c3
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x1c3
		>;
	};

	pinctrl_pca9534: pca9534grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
		>;
	};

	pinctrl_ptn5150: ptn5150grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
		>;
	};

	pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x16
		>;
	};

	pinctrl_reg_usb_otg2_vbus_sleep: regusbotg2vbus-sleepgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x120
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xc1
		>;
	};
};