// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// Copyright 2025 Tenstorrent AI ULC
/dts-v1/;

/ {
	compatible = "tenstorrent,blackhole";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <50000000>;

		cpu@0 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <0>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu@1 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <1>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu@2 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <2>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu@3 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <3>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};
	};

	pmu {
		compatible = "riscv,pmu";
		riscv,event-to-mhpmevent =
			/* SBI_PMU_HW_CPU_CYCLES -> CPU cycles */
			<0x00001 0x00000000 0x0001>,
			/* SBI_PMU_HW_INSTRUCTIONS -> Instructions executed */
			<0x00002 0x00000000 0x0004>,
			/* SBI_PMU_HW_CACHE_REFERENCES -> I-cache/ITIM busy | D-cache/DTIM busy */
			<0x00003 0x00000000 0x1801>,
			/* SBI_PMU_HW_CACHE_MISSES -> I-cache miss | D-cache miss */
			<0x00004 0x00000000 0x0302>,
			/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
			<0x00005 0x00000000 0x4000>,
			/*
			 * SBI_PMU_HW_BRANCH_MISSES ->
			 * Branch direction misprediction | Branch/jump target misprediction
			 */
			<0x00006 0x00000000 0x6001>,
			/* L1D_READ_MISS -> Data cache miss or MMIO access */
			<0x10001 0x00000000 0x0202>,
			/* L1D_WRITE_ACCESS -> Data cache write-back */
			<0x10002 0x00000000 0x0402>,
			/* L1I_READ_MISS -> Instruction cache miss */
			<0x10009 0x00000000 0x0102>,
			/* LL_READ_MISS -> UTLB miss */
			<0x10011 0x00000000 0x2002>,
			/* DTLB_READ_MISS -> Data TLB miss */
			<0x10019 0x00000000 0x1002>,
			/* ITLB_READ_MISS -> Instruction TLB miss */
			<0x10021 0x00000000 0x0802>;
		riscv,event-to-mhpmcounters =
			<0x00001 0x00001 0x01>,
			<0x00002 0x00002 0x04>,
			<0x00003 0x00006 0x78>,
			<0x10001 0x10002 0x78>,
			<0x10009 0x10009 0x78>,
			<0x10011 0x10011 0x78>,
			<0x10019 0x10019 0x78>,
			<0x10021 0x10021 0x78>;
		riscv,raw-event-to-mhpmcounters =
			/* Class 0: Instruction Commit Events, bits 8-25 variant */
			<0x0 0x0 0xffffffff 0xfc0000ff 0x78>,
			/* Class 1: Microarchitectural Events, bits 8-18 variant */
			<0x0 0x1 0xffffffff 0xfff800ff 0x78>,
			/* Class 2: Memory System Events, bits 8-13 variant */
			<0x0 0x2 0xffffffff 0xffffc0ff 0x78>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		clint0: timer@2000000 {
			compatible = "tenstorrent,blackhole-clint", "sifive,clint0";
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
					      <&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
					      <&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
					      <&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
		};

		plic0: interrupt-controller@c000000 {
			compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0";
			reg = <0x0 0x0c000000 0x0 0x04000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>,
					      <&cpu2_intc 11>, <&cpu2_intc 9>,
					      <&cpu3_intc 11>, <&cpu3_intc 9>;
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			riscv,ndev = <128>;
		};
	};
};