99 lines
2.3 KiB
YAML
99 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fpga/efinix,trion-config.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Efinix SPI FPGA Manager
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maintainers:
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- Ian Dannapel <iansdannapel@gmail.com>
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description: |
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Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams
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through "SPI Passive Mode".
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Additional pin hogs for bus width configuration should be set
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elsewhere, if necessary.
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References:
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- https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf
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- https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf
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- https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf
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allOf:
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- efinix,titanium-config
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- efinix,topaz-config
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- const: efinix,trion-config
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- const: efinix,trion-config
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spi-cpha: true
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spi-cpol: true
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spi-max-frequency:
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maximum: 25000000
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reg:
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maxItems: 1
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reset-gpios:
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description:
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reset and re-configuration trigger pin (low active)
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maxItems: 1
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cdone-gpios:
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description:
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optional configuration done status pin (high active)
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maxItems: 1
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required:
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- compatible
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- reg
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- reset-gpios
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- spi-cpha
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- spi-cpol
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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fpga-mgr@0 {
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compatible = "efinix,trion-config";
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reg = <0>;
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spi-max-frequency = <25000000>;
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spi-cpha;
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spi-cpol;
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reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
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cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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fpga-mgr@0 {
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compatible = "efinix,titanium-config", "efinix,trion-config";
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reg = <0>;
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spi-max-frequency = <25000000>;
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spi-cpha;
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spi-cpol;
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reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
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cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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};
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...
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